1 /******************************************************************************
3 Copyright (c) 2001-2008, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
38 #include "e1000_osdep.h"
39 #include "e1000_regs.h"
40 #include "e1000_defines.h"
44 #define E1000_DEV_ID_82542 0x1000
45 #define E1000_DEV_ID_82543GC_FIBER 0x1001
46 #define E1000_DEV_ID_82543GC_COPPER 0x1004
47 #define E1000_DEV_ID_82544EI_COPPER 0x1008
48 #define E1000_DEV_ID_82544EI_FIBER 0x1009
49 #define E1000_DEV_ID_82544GC_COPPER 0x100C
50 #define E1000_DEV_ID_82544GC_LOM 0x100D
51 #define E1000_DEV_ID_82540EM 0x100E
52 #define E1000_DEV_ID_82540EM_LOM 0x1015
53 #define E1000_DEV_ID_82540EP_LOM 0x1016
54 #define E1000_DEV_ID_82540EP 0x1017
55 #define E1000_DEV_ID_82540EP_LP 0x101E
56 #define E1000_DEV_ID_82545EM_COPPER 0x100F
57 #define E1000_DEV_ID_82545EM_FIBER 0x1011
58 #define E1000_DEV_ID_82545GM_COPPER 0x1026
59 #define E1000_DEV_ID_82545GM_FIBER 0x1027
60 #define E1000_DEV_ID_82545GM_SERDES 0x1028
61 #define E1000_DEV_ID_82546EB_COPPER 0x1010
62 #define E1000_DEV_ID_82546EB_FIBER 0x1012
63 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
64 #define E1000_DEV_ID_82546GB_COPPER 0x1079
65 #define E1000_DEV_ID_82546GB_FIBER 0x107A
66 #define E1000_DEV_ID_82546GB_SERDES 0x107B
67 #define E1000_DEV_ID_82546GB_PCIE 0x108A
68 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
70 #define E1000_DEV_ID_82541EI 0x1013
71 #define E1000_DEV_ID_82541EI_MOBILE 0x1018
72 #define E1000_DEV_ID_82541ER_LOM 0x1014
73 #define E1000_DEV_ID_82541ER 0x1078
74 #define E1000_DEV_ID_82541GI 0x1076
75 #define E1000_DEV_ID_82541GI_LF 0x107C
76 #define E1000_DEV_ID_82541GI_MOBILE 0x1077
77 #define E1000_DEV_ID_82547EI 0x1019
78 #define E1000_DEV_ID_82547EI_MOBILE 0x101A
79 #define E1000_DEV_ID_82547GI 0x1075
80 #define E1000_DEV_ID_82571EB_COPPER 0x105E
81 #define E1000_DEV_ID_82571EB_FIBER 0x105F
82 #define E1000_DEV_ID_82571EB_SERDES 0x1060
83 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
84 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
85 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
86 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
87 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
89 #define E1000_DEV_ID_82572EI_COPPER 0x107D
90 #define E1000_DEV_ID_82572EI_FIBER 0x107E
91 #define E1000_DEV_ID_82572EI_SERDES 0x107F
92 #define E1000_DEV_ID_82572EI 0x10B9
93 #define E1000_DEV_ID_82573E 0x108B
94 #define E1000_DEV_ID_82573E_IAMT 0x108C
95 #define E1000_DEV_ID_82573L 0x109A
96 #define E1000_DEV_ID_82574L 0x10D3
97 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
98 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
99 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
100 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
101 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
102 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
103 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
104 #define E1000_DEV_ID_ICH8_IFE 0x104C
105 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
106 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
107 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
108 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF
109 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
110 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
111 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
112 #define E1000_DEV_ID_ICH9_BM 0x10E5
113 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
114 #define E1000_DEV_ID_ICH9_IFE 0x10C0
115 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
116 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
117 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
118 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
119 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
120 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
121 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
122 #define E1000_DEV_ID_82576 0x10C9
123 #define E1000_DEV_ID_82576_FIBER 0x10E6
124 #define E1000_DEV_ID_82576_SERDES 0x10E7
125 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
126 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
127 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
128 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
130 #define E1000_REVISION_0 0
131 #define E1000_REVISION_1 1
132 #define E1000_REVISION_2 2
133 #define E1000_REVISION_3 3
134 #define E1000_REVISION_4 4
136 #define E1000_FUNC_0 0
137 #define E1000_FUNC_1 1
139 enum e1000_mac_type {
163 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
166 enum e1000_media_type {
167 e1000_media_type_unknown = 0,
168 e1000_media_type_copper = 1,
169 e1000_media_type_fiber = 2,
170 e1000_media_type_internal_serdes = 3,
171 e1000_num_media_types
174 enum e1000_nvm_type {
175 e1000_nvm_unknown = 0,
177 e1000_nvm_eeprom_spi,
178 e1000_nvm_eeprom_microwire,
183 enum e1000_nvm_override {
184 e1000_nvm_override_none = 0,
185 e1000_nvm_override_spi_small,
186 e1000_nvm_override_spi_large,
187 e1000_nvm_override_microwire_small,
188 e1000_nvm_override_microwire_large
191 enum e1000_phy_type {
192 e1000_phy_unknown = 0,
204 enum e1000_bus_type {
205 e1000_bus_type_unknown = 0,
208 e1000_bus_type_pci_express,
209 e1000_bus_type_reserved
212 enum e1000_bus_speed {
213 e1000_bus_speed_unknown = 0,
219 e1000_bus_speed_2500,
220 e1000_bus_speed_5000,
221 e1000_bus_speed_reserved
224 enum e1000_bus_width {
225 e1000_bus_width_unknown = 0,
226 e1000_bus_width_pcie_x1,
227 e1000_bus_width_pcie_x2,
228 e1000_bus_width_pcie_x4 = 4,
229 e1000_bus_width_pcie_x8 = 8,
232 e1000_bus_width_reserved
235 enum e1000_1000t_rx_status {
236 e1000_1000t_rx_status_not_ok = 0,
237 e1000_1000t_rx_status_ok,
238 e1000_1000t_rx_status_undefined = 0xFF
241 enum e1000_rev_polarity {
242 e1000_rev_polarity_normal = 0,
243 e1000_rev_polarity_reversed,
244 e1000_rev_polarity_undefined = 0xFF
252 e1000_fc_default = 0xFF
255 enum e1000_ffe_config {
256 e1000_ffe_config_enabled = 0,
257 e1000_ffe_config_active,
258 e1000_ffe_config_blocked
261 enum e1000_dsp_config {
262 e1000_dsp_config_disabled = 0,
263 e1000_dsp_config_enabled,
264 e1000_dsp_config_activated,
265 e1000_dsp_config_undefined = 0xFF
268 /* Receive Descriptor */
269 struct e1000_rx_desc {
270 u64 buffer_addr; /* Address of the descriptor's data buffer */
271 u16 length; /* Length of data DMAed into data buffer */
272 u16 csum; /* Packet checksum */
273 u8 status; /* Descriptor status */
274 u8 errors; /* Descriptor Errors */
278 /* Receive Descriptor - Extended */
279 union e1000_rx_desc_extended {
286 u32 mrq; /* Multiple Rx Queues */
288 u32 rss; /* RSS Hash */
290 u16 ip_id; /* IP id */
291 u16 csum; /* Packet Checksum */
296 u32 status_error; /* ext status/error */
298 u16 vlan; /* VLAN tag */
300 } wb; /* writeback */
303 #define MAX_PS_BUFFERS 4
304 /* Receive Descriptor - Packet Split */
305 union e1000_rx_desc_packet_split {
307 /* one buffer for protocol header(s), three data buffers */
308 u64 buffer_addr[MAX_PS_BUFFERS];
312 u32 mrq; /* Multiple Rx Queues */
314 u32 rss; /* RSS Hash */
316 u16 ip_id; /* IP id */
317 u16 csum; /* Packet Checksum */
322 u32 status_error; /* ext status/error */
323 u16 length0; /* length of buffer 0 */
324 u16 vlan; /* VLAN tag */
328 u16 length[3]; /* length of buffers 1-3 */
331 } wb; /* writeback */
334 /* Transmit Descriptor */
335 struct e1000_tx_desc {
336 u64 buffer_addr; /* Address of the descriptor's data buffer */
340 u16 length; /* Data buffer length */
341 u8 cso; /* Checksum offset */
342 u8 cmd; /* Descriptor control */
348 u8 status; /* Descriptor status */
349 u8 css; /* Checksum start */
355 /* Offload Context Descriptor */
356 struct e1000_context_desc {
360 u8 ipcss; /* IP checksum start */
361 u8 ipcso; /* IP checksum offset */
362 u16 ipcse; /* IP checksum end */
368 u8 tucss; /* TCP checksum start */
369 u8 tucso; /* TCP checksum offset */
370 u16 tucse; /* TCP checksum end */
377 u8 status; /* Descriptor status */
378 u8 hdr_len; /* Header length */
379 u16 mss; /* Maximum segment size */
384 /* Offload data descriptor */
385 struct e1000_data_desc {
386 u64 buffer_addr; /* Address of the descriptor's buffer address */
390 u16 length; /* Data buffer length */
398 u8 status; /* Descriptor status */
399 u8 popts; /* Packet Options */
405 /* Statistics counters collected by the MAC */
406 struct e1000_hw_stats {
484 struct e1000_phy_stats {
489 struct e1000_host_mng_dhcp_cookie {
500 /* Host Interface "Rev 1" */
501 struct e1000_host_command_header {
508 #define E1000_HI_MAX_DATA_LENGTH 252
509 struct e1000_host_command_info {
510 struct e1000_host_command_header command_header;
511 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
514 /* Host Interface "Rev 2" */
515 struct e1000_host_mng_command_header {
523 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
524 struct e1000_host_mng_command_info {
525 struct e1000_host_mng_command_header command_header;
526 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
529 #include "e1000_mac.h"
530 #include "e1000_phy.h"
531 #include "e1000_nvm.h"
532 #include "e1000_manage.h"
534 struct e1000_mac_operations {
535 /* Function pointers for the MAC. */
536 s32 (*init_params)(struct e1000_hw *);
537 s32 (*blink_led)(struct e1000_hw *);
538 s32 (*check_for_link)(struct e1000_hw *);
539 bool (*check_mng_mode)(struct e1000_hw *hw);
540 s32 (*cleanup_led)(struct e1000_hw *);
541 void (*clear_hw_cntrs)(struct e1000_hw *);
542 void (*clear_vfta)(struct e1000_hw *);
543 s32 (*get_bus_info)(struct e1000_hw *);
544 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
545 s32 (*led_on)(struct e1000_hw *);
546 s32 (*led_off)(struct e1000_hw *);
547 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32,
549 void (*remove_device)(struct e1000_hw *);
550 s32 (*reset_hw)(struct e1000_hw *);
551 s32 (*init_hw)(struct e1000_hw *);
552 void (*shutdown_serdes)(struct e1000_hw *);
553 s32 (*setup_link)(struct e1000_hw *);
554 s32 (*setup_physical_interface)(struct e1000_hw *);
555 s32 (*setup_led)(struct e1000_hw *);
556 void (*write_vfta)(struct e1000_hw *, u32, u32);
557 void (*mta_set)(struct e1000_hw *, u32);
558 void (*config_collision_dist)(struct e1000_hw*);
559 void (*rar_set)(struct e1000_hw*, u8*, u32);
560 s32 (*read_mac_addr)(struct e1000_hw*);
561 s32 (*validate_mdi_setting)(struct e1000_hw*);
562 s32 (*mng_host_if_write)(struct e1000_hw*, u8*, u16, u16, u8*);
563 s32 (*mng_write_cmd_header)(struct e1000_hw *hw,
564 struct e1000_host_mng_command_header*);
565 s32 (*mng_enable_host_if)(struct e1000_hw*);
566 s32 (*wait_autoneg)(struct e1000_hw*);
569 struct e1000_phy_operations {
570 s32 (*init_params)(struct e1000_hw *);
571 s32 (*acquire)(struct e1000_hw *);
572 s32 (*check_polarity)(struct e1000_hw *);
573 s32 (*check_reset_block)(struct e1000_hw *);
574 s32 (*commit)(struct e1000_hw *);
575 s32 (*force_speed_duplex)(struct e1000_hw *);
576 s32 (*get_cfg_done)(struct e1000_hw *hw);
577 s32 (*get_cable_length)(struct e1000_hw *);
578 s32 (*get_info)(struct e1000_hw *);
579 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
580 void (*release)(struct e1000_hw *);
581 s32 (*reset)(struct e1000_hw *);
582 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
583 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
584 s32 (*write_reg)(struct e1000_hw *, u32, u16);
585 void (*power_up)(struct e1000_hw *);
586 void (*power_down)(struct e1000_hw *);
589 struct e1000_nvm_operations {
590 s32 (*init_params)(struct e1000_hw *);
591 s32 (*acquire)(struct e1000_hw *);
592 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
593 void (*release)(struct e1000_hw *);
594 void (*reload)(struct e1000_hw *);
595 s32 (*update)(struct e1000_hw *);
596 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
597 s32 (*validate)(struct e1000_hw *);
598 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
601 struct e1000_mac_info {
602 struct e1000_mac_operations ops;
606 enum e1000_mac_type type;
624 u8 forced_speed_duplex;
627 bool arc_subsystem_valid;
628 bool asf_firmware_present;
632 bool disable_hw_init_bits;
633 bool get_link_status;
634 bool ifs_params_forced;
636 bool report_tx_early;
637 bool serdes_has_link;
638 bool tx_pkt_filtering;
641 struct e1000_phy_info {
642 struct e1000_phy_operations ops;
643 enum e1000_phy_type type;
645 enum e1000_1000t_rx_status local_rx;
646 enum e1000_1000t_rx_status remote_rx;
647 enum e1000_ms_type ms_type;
648 enum e1000_ms_type original_ms_type;
649 enum e1000_rev_polarity cable_polarity;
650 enum e1000_smart_speed smart_speed;
654 u32 reset_delay_us; /* in usec */
657 enum e1000_media_type media_type;
659 u16 autoneg_advertised;
662 u16 max_cable_length;
663 u16 min_cable_length;
667 bool disable_polarity_correction;
669 bool polarity_correction;
671 bool speed_downgraded;
672 bool autoneg_wait_to_complete;
675 struct e1000_nvm_info {
676 struct e1000_nvm_operations ops;
677 enum e1000_nvm_type type;
678 enum e1000_nvm_override override;
691 struct e1000_bus_info {
692 enum e1000_bus_type type;
693 enum e1000_bus_speed speed;
694 enum e1000_bus_width width;
702 struct e1000_fc_info {
703 u32 high_water; /* Flow control high-water mark */
704 u32 low_water; /* Flow control low-water mark */
705 u16 pause_time; /* Flow control pause timer */
706 bool send_xon; /* Flow control send XON */
707 bool strict_ieee; /* Strict IEEE mode */
708 enum e1000_fc_type type; /* Type of flow control */
709 enum e1000_fc_type original_type;
718 unsigned long io_base;
720 struct e1000_mac_info mac;
721 struct e1000_fc_info fc;
722 struct e1000_phy_info phy;
723 struct e1000_nvm_info nvm;
724 struct e1000_bus_info bus;
725 struct e1000_host_mng_dhcp_cookie mng_cookie;
730 u16 subsystem_vendor_id;
731 u16 subsystem_device_id;
737 #include "e1000_82541.h"
738 #include "e1000_82543.h"
739 #include "e1000_82571.h"
740 #include "e1000_80003es2lan.h"
741 #include "e1000_ich8lan.h"
742 #include "e1000_82575.h"
744 /* These functions must be implemented by drivers */
745 void e1000_pci_clear_mwi(struct e1000_hw *hw);
746 void e1000_pci_set_mwi(struct e1000_hw *hw);
747 s32 e1000_alloc_zeroed_dev_spec_struct(struct e1000_hw *hw, u32 size);
748 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
749 void e1000_free_dev_spec_struct(struct e1000_hw *hw);
750 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
751 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);