1 /******************************************************************************
3 Copyright (c) 2001-2013, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
38 #include "e1000_osdep.h"
39 #include "e1000_regs.h"
40 #include "e1000_defines.h"
44 #define E1000_DEV_ID_82542 0x1000
45 #define E1000_DEV_ID_82543GC_FIBER 0x1001
46 #define E1000_DEV_ID_82543GC_COPPER 0x1004
47 #define E1000_DEV_ID_82544EI_COPPER 0x1008
48 #define E1000_DEV_ID_82544EI_FIBER 0x1009
49 #define E1000_DEV_ID_82544GC_COPPER 0x100C
50 #define E1000_DEV_ID_82544GC_LOM 0x100D
51 #define E1000_DEV_ID_82540EM 0x100E
52 #define E1000_DEV_ID_82540EM_LOM 0x1015
53 #define E1000_DEV_ID_82540EP_LOM 0x1016
54 #define E1000_DEV_ID_82540EP 0x1017
55 #define E1000_DEV_ID_82540EP_LP 0x101E
56 #define E1000_DEV_ID_82545EM_COPPER 0x100F
57 #define E1000_DEV_ID_82545EM_FIBER 0x1011
58 #define E1000_DEV_ID_82545GM_COPPER 0x1026
59 #define E1000_DEV_ID_82545GM_FIBER 0x1027
60 #define E1000_DEV_ID_82545GM_SERDES 0x1028
61 #define E1000_DEV_ID_82546EB_COPPER 0x1010
62 #define E1000_DEV_ID_82546EB_FIBER 0x1012
63 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
64 #define E1000_DEV_ID_82546GB_COPPER 0x1079
65 #define E1000_DEV_ID_82546GB_FIBER 0x107A
66 #define E1000_DEV_ID_82546GB_SERDES 0x107B
67 #define E1000_DEV_ID_82546GB_PCIE 0x108A
68 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
70 #define E1000_DEV_ID_82541EI 0x1013
71 #define E1000_DEV_ID_82541EI_MOBILE 0x1018
72 #define E1000_DEV_ID_82541ER_LOM 0x1014
73 #define E1000_DEV_ID_82541ER 0x1078
74 #define E1000_DEV_ID_82541GI 0x1076
75 #define E1000_DEV_ID_82541GI_LF 0x107C
76 #define E1000_DEV_ID_82541GI_MOBILE 0x1077
77 #define E1000_DEV_ID_82547EI 0x1019
78 #define E1000_DEV_ID_82547EI_MOBILE 0x101A
79 #define E1000_DEV_ID_82547GI 0x1075
80 #define E1000_DEV_ID_82571EB_COPPER 0x105E
81 #define E1000_DEV_ID_82571EB_FIBER 0x105F
82 #define E1000_DEV_ID_82571EB_SERDES 0x1060
83 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
84 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
85 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
86 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
87 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
89 #define E1000_DEV_ID_82572EI_COPPER 0x107D
90 #define E1000_DEV_ID_82572EI_FIBER 0x107E
91 #define E1000_DEV_ID_82572EI_SERDES 0x107F
92 #define E1000_DEV_ID_82572EI 0x10B9
93 #define E1000_DEV_ID_82573E 0x108B
94 #define E1000_DEV_ID_82573E_IAMT 0x108C
95 #define E1000_DEV_ID_82573L 0x109A
96 #define E1000_DEV_ID_82574L 0x10D3
97 #define E1000_DEV_ID_82574LA 0x10F6
98 #define E1000_DEV_ID_82583V 0x150C
99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
103 #define E1000_DEV_ID_ICH8_82567V_3 0x1501
104 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
105 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
106 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
107 #define E1000_DEV_ID_ICH8_IFE 0x104C
108 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
109 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
110 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
111 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF
112 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
113 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
114 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
115 #define E1000_DEV_ID_ICH9_BM 0x10E5
116 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
117 #define E1000_DEV_ID_ICH9_IFE 0x10C0
118 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
119 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
120 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
121 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
122 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
123 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
124 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
125 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525
126 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
127 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
128 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
129 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
130 #define E1000_DEV_ID_PCH2_LV_LM 0x1502
131 #define E1000_DEV_ID_PCH2_LV_V 0x1503
132 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
133 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
134 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
135 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
136 #define E1000_DEV_ID_82576 0x10C9
137 #define E1000_DEV_ID_82576_FIBER 0x10E6
138 #define E1000_DEV_ID_82576_SERDES 0x10E7
139 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
140 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
141 #define E1000_DEV_ID_82576_NS 0x150A
142 #define E1000_DEV_ID_82576_NS_SERDES 0x1518
143 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
144 #define E1000_DEV_ID_82576_VF 0x10CA
145 #define E1000_DEV_ID_82576_VF_HV 0x152D
146 #define E1000_DEV_ID_I350_VF 0x1520
147 #define E1000_DEV_ID_I350_VF_HV 0x152F
148 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
149 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
150 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
151 #define E1000_DEV_ID_82580_COPPER 0x150E
152 #define E1000_DEV_ID_82580_FIBER 0x150F
153 #define E1000_DEV_ID_82580_SERDES 0x1510
154 #define E1000_DEV_ID_82580_SGMII 0x1511
155 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
156 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
157 #define E1000_DEV_ID_I350_COPPER 0x1521
158 #define E1000_DEV_ID_I350_FIBER 0x1522
159 #define E1000_DEV_ID_I350_SERDES 0x1523
160 #define E1000_DEV_ID_I350_SGMII 0x1524
161 #define E1000_DEV_ID_I350_DA4 0x1546
162 #define E1000_DEV_ID_I210_COPPER 0x1533
163 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534
164 #define E1000_DEV_ID_I210_COPPER_IT 0x1535
165 #define E1000_DEV_ID_I210_FIBER 0x1536
166 #define E1000_DEV_ID_I210_SERDES 0x1537
167 #define E1000_DEV_ID_I210_SGMII 0x1538
168 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B
169 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C
170 #define E1000_DEV_ID_I211_COPPER 0x1539
171 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40
172 #define E1000_DEV_ID_I354_SGMII 0x1F41
173 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45
174 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
175 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
176 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
177 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440
179 #define E1000_REVISION_0 0
180 #define E1000_REVISION_1 1
181 #define E1000_REVISION_2 2
182 #define E1000_REVISION_3 3
183 #define E1000_REVISION_4 4
185 #define E1000_FUNC_0 0
186 #define E1000_FUNC_1 1
187 #define E1000_FUNC_2 2
188 #define E1000_FUNC_3 3
190 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
191 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
192 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
193 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
195 enum e1000_mac_type {
230 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
233 enum e1000_media_type {
234 e1000_media_type_unknown = 0,
235 e1000_media_type_copper = 1,
236 e1000_media_type_fiber = 2,
237 e1000_media_type_internal_serdes = 3,
238 e1000_num_media_types
241 enum e1000_nvm_type {
242 e1000_nvm_unknown = 0,
244 e1000_nvm_eeprom_spi,
245 e1000_nvm_eeprom_microwire,
251 enum e1000_nvm_override {
252 e1000_nvm_override_none = 0,
253 e1000_nvm_override_spi_small,
254 e1000_nvm_override_spi_large,
255 e1000_nvm_override_microwire_small,
256 e1000_nvm_override_microwire_large
259 enum e1000_phy_type {
260 e1000_phy_unknown = 0,
278 enum e1000_bus_type {
279 e1000_bus_type_unknown = 0,
282 e1000_bus_type_pci_express,
283 e1000_bus_type_reserved
286 enum e1000_bus_speed {
287 e1000_bus_speed_unknown = 0,
293 e1000_bus_speed_2500,
294 e1000_bus_speed_5000,
295 e1000_bus_speed_reserved
298 enum e1000_bus_width {
299 e1000_bus_width_unknown = 0,
300 e1000_bus_width_pcie_x1,
301 e1000_bus_width_pcie_x2,
302 e1000_bus_width_pcie_x4 = 4,
303 e1000_bus_width_pcie_x8 = 8,
306 e1000_bus_width_reserved
309 enum e1000_1000t_rx_status {
310 e1000_1000t_rx_status_not_ok = 0,
311 e1000_1000t_rx_status_ok,
312 e1000_1000t_rx_status_undefined = 0xFF
315 enum e1000_rev_polarity {
316 e1000_rev_polarity_normal = 0,
317 e1000_rev_polarity_reversed,
318 e1000_rev_polarity_undefined = 0xFF
326 e1000_fc_default = 0xFF
329 enum e1000_ffe_config {
330 e1000_ffe_config_enabled = 0,
331 e1000_ffe_config_active,
332 e1000_ffe_config_blocked
335 enum e1000_dsp_config {
336 e1000_dsp_config_disabled = 0,
337 e1000_dsp_config_enabled,
338 e1000_dsp_config_activated,
339 e1000_dsp_config_undefined = 0xFF
343 e1000_ms_hw_default = 0,
344 e1000_ms_force_master,
345 e1000_ms_force_slave,
349 enum e1000_smart_speed {
350 e1000_smart_speed_default = 0,
351 e1000_smart_speed_on,
352 e1000_smart_speed_off
355 enum e1000_serdes_link_state {
356 e1000_serdes_link_down = 0,
357 e1000_serdes_link_autoneg_progress,
358 e1000_serdes_link_autoneg_complete,
359 e1000_serdes_link_forced_up
365 /* Receive Descriptor */
366 struct e1000_rx_desc {
367 __le64 buffer_addr; /* Address of the descriptor's data buffer */
368 __le16 length; /* Length of data DMAed into data buffer */
369 __le16 csum; /* Packet checksum */
370 u8 status; /* Descriptor status */
371 u8 errors; /* Descriptor Errors */
375 /* Receive Descriptor - Extended */
376 union e1000_rx_desc_extended {
383 __le32 mrq; /* Multiple Rx Queues */
385 __le32 rss; /* RSS Hash */
387 __le16 ip_id; /* IP id */
388 __le16 csum; /* Packet Checksum */
393 __le32 status_error; /* ext status/error */
395 __le16 vlan; /* VLAN tag */
397 } wb; /* writeback */
400 #define MAX_PS_BUFFERS 4
402 /* Number of packet split data buffers (not including the header buffer) */
403 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
405 /* Receive Descriptor - Packet Split */
406 union e1000_rx_desc_packet_split {
408 /* one buffer for protocol header(s), three data buffers */
409 __le64 buffer_addr[MAX_PS_BUFFERS];
413 __le32 mrq; /* Multiple Rx Queues */
415 __le32 rss; /* RSS Hash */
417 __le16 ip_id; /* IP id */
418 __le16 csum; /* Packet Checksum */
423 __le32 status_error; /* ext status/error */
424 __le16 length0; /* length of buffer 0 */
425 __le16 vlan; /* VLAN tag */
428 __le16 header_status;
429 /* length of buffers 1-3 */
430 __le16 length[PS_PAGE_BUFFERS];
433 } wb; /* writeback */
436 /* Transmit Descriptor */
437 struct e1000_tx_desc {
438 __le64 buffer_addr; /* Address of the descriptor's data buffer */
442 __le16 length; /* Data buffer length */
443 u8 cso; /* Checksum offset */
444 u8 cmd; /* Descriptor control */
450 u8 status; /* Descriptor status */
451 u8 css; /* Checksum start */
457 /* Offload Context Descriptor */
458 struct e1000_context_desc {
462 u8 ipcss; /* IP checksum start */
463 u8 ipcso; /* IP checksum offset */
464 __le16 ipcse; /* IP checksum end */
470 u8 tucss; /* TCP checksum start */
471 u8 tucso; /* TCP checksum offset */
472 __le16 tucse; /* TCP checksum end */
475 __le32 cmd_and_length;
479 u8 status; /* Descriptor status */
480 u8 hdr_len; /* Header length */
481 __le16 mss; /* Maximum segment size */
486 /* Offload data descriptor */
487 struct e1000_data_desc {
488 __le64 buffer_addr; /* Address of the descriptor's buffer address */
492 __le16 length; /* Data buffer length */
500 u8 status; /* Descriptor status */
501 u8 popts; /* Packet Options */
507 /* Statistics counters collected by the MAC */
508 struct e1000_hw_stats {
591 struct e1000_vf_stats {
623 struct e1000_phy_stats {
628 struct e1000_host_mng_dhcp_cookie {
639 /* Host Interface "Rev 1" */
640 struct e1000_host_command_header {
647 #define E1000_HI_MAX_DATA_LENGTH 252
648 struct e1000_host_command_info {
649 struct e1000_host_command_header command_header;
650 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
653 /* Host Interface "Rev 2" */
654 struct e1000_host_mng_command_header {
662 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
663 struct e1000_host_mng_command_info {
664 struct e1000_host_mng_command_header command_header;
665 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
668 #include "e1000_mac.h"
669 #include "e1000_phy.h"
670 #include "e1000_nvm.h"
671 #include "e1000_manage.h"
672 #include "e1000_mbx.h"
674 /* Function pointers for the MAC. */
675 struct e1000_mac_operations {
676 s32 (*init_params)(struct e1000_hw *);
677 s32 (*id_led_init)(struct e1000_hw *);
678 s32 (*blink_led)(struct e1000_hw *);
679 bool (*check_mng_mode)(struct e1000_hw *);
680 s32 (*check_for_link)(struct e1000_hw *);
681 s32 (*cleanup_led)(struct e1000_hw *);
682 void (*clear_hw_cntrs)(struct e1000_hw *);
683 void (*clear_vfta)(struct e1000_hw *);
684 s32 (*get_bus_info)(struct e1000_hw *);
685 void (*set_lan_id)(struct e1000_hw *);
686 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
687 s32 (*led_on)(struct e1000_hw *);
688 s32 (*led_off)(struct e1000_hw *);
689 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
690 s32 (*reset_hw)(struct e1000_hw *);
691 s32 (*init_hw)(struct e1000_hw *);
692 void (*shutdown_serdes)(struct e1000_hw *);
693 void (*power_up_serdes)(struct e1000_hw *);
694 s32 (*setup_link)(struct e1000_hw *);
695 s32 (*setup_physical_interface)(struct e1000_hw *);
696 s32 (*setup_led)(struct e1000_hw *);
697 void (*write_vfta)(struct e1000_hw *, u32, u32);
698 void (*config_collision_dist)(struct e1000_hw *);
699 void (*rar_set)(struct e1000_hw *, u8*, u32);
700 s32 (*read_mac_addr)(struct e1000_hw *);
701 s32 (*validate_mdi_setting)(struct e1000_hw *);
702 s32 (*set_obff_timer)(struct e1000_hw *, u32);
703 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);
704 void (*release_swfw_sync)(struct e1000_hw *, u16);
707 /* When to use various PHY register access functions:
710 * Function Does Does When to use
711 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
712 * X_reg L,P,A n/a for simple PHY reg accesses
713 * X_reg_locked P,A L for multiple accesses of different regs
715 * X_reg_page A L,P for multiple accesses of different regs
718 * Where X=[read|write], L=locking, P=sets page, A=register access
721 struct e1000_phy_operations {
722 s32 (*init_params)(struct e1000_hw *);
723 s32 (*acquire)(struct e1000_hw *);
724 s32 (*cfg_on_link_up)(struct e1000_hw *);
725 s32 (*check_polarity)(struct e1000_hw *);
726 s32 (*check_reset_block)(struct e1000_hw *);
727 s32 (*commit)(struct e1000_hw *);
728 s32 (*force_speed_duplex)(struct e1000_hw *);
729 s32 (*get_cfg_done)(struct e1000_hw *hw);
730 s32 (*get_cable_length)(struct e1000_hw *);
731 s32 (*get_info)(struct e1000_hw *);
732 s32 (*set_page)(struct e1000_hw *, u16);
733 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
734 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
735 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
736 void (*release)(struct e1000_hw *);
737 s32 (*reset)(struct e1000_hw *);
738 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
739 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
740 s32 (*write_reg)(struct e1000_hw *, u32, u16);
741 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
742 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
743 void (*power_up)(struct e1000_hw *);
744 void (*power_down)(struct e1000_hw *);
745 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
746 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
749 /* Function pointers for the NVM. */
750 struct e1000_nvm_operations {
751 s32 (*init_params)(struct e1000_hw *);
752 s32 (*acquire)(struct e1000_hw *);
753 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
754 void (*release)(struct e1000_hw *);
755 void (*reload)(struct e1000_hw *);
756 s32 (*update)(struct e1000_hw *);
757 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
758 s32 (*validate)(struct e1000_hw *);
759 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
762 struct e1000_mac_info {
763 struct e1000_mac_operations ops;
764 u8 addr[ETH_ADDR_LEN];
765 u8 perm_addr[ETH_ADDR_LEN];
767 enum e1000_mac_type type;
785 /* Maximum size of the MTA register table in all supported adapters */
786 #define MAX_MTA_REG 128
787 u32 mta_shadow[MAX_MTA_REG];
790 u8 forced_speed_duplex;
794 bool arc_subsystem_valid;
795 bool asf_firmware_present;
798 bool get_link_status;
800 bool report_tx_early;
801 enum e1000_serdes_link_state serdes_link_state;
802 bool serdes_has_link;
803 bool tx_pkt_filtering;
807 struct e1000_phy_info {
808 struct e1000_phy_operations ops;
809 enum e1000_phy_type type;
811 enum e1000_1000t_rx_status local_rx;
812 enum e1000_1000t_rx_status remote_rx;
813 enum e1000_ms_type ms_type;
814 enum e1000_ms_type original_ms_type;
815 enum e1000_rev_polarity cable_polarity;
816 enum e1000_smart_speed smart_speed;
820 u32 reset_delay_us; /* in usec */
823 enum e1000_media_type media_type;
825 u16 autoneg_advertised;
828 u16 max_cable_length;
829 u16 min_cable_length;
833 bool disable_polarity_correction;
835 bool polarity_correction;
836 bool speed_downgraded;
837 bool autoneg_wait_to_complete;
840 struct e1000_nvm_info {
841 struct e1000_nvm_operations ops;
842 enum e1000_nvm_type type;
843 enum e1000_nvm_override override;
855 struct e1000_bus_info {
856 enum e1000_bus_type type;
857 enum e1000_bus_speed speed;
858 enum e1000_bus_width width;
864 struct e1000_fc_info {
865 u32 high_water; /* Flow control high-water mark */
866 u32 low_water; /* Flow control low-water mark */
867 u16 pause_time; /* Flow control pause timer */
868 u16 refresh_time; /* Flow control refresh timer */
869 bool send_xon; /* Flow control send XON */
870 bool strict_ieee; /* Strict IEEE mode */
871 enum e1000_fc_mode current_mode; /* FC mode in effect */
872 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
875 struct e1000_mbx_operations {
876 s32 (*init_params)(struct e1000_hw *hw);
877 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
878 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
879 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
880 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
881 s32 (*check_for_msg)(struct e1000_hw *, u16);
882 s32 (*check_for_ack)(struct e1000_hw *, u16);
883 s32 (*check_for_rst)(struct e1000_hw *, u16);
886 struct e1000_mbx_stats {
895 struct e1000_mbx_info {
896 struct e1000_mbx_operations ops;
897 struct e1000_mbx_stats stats;
903 struct e1000_dev_spec_82541 {
904 enum e1000_dsp_config dsp_config;
905 enum e1000_ffe_config ffe_config;
907 bool phy_init_script;
910 struct e1000_dev_spec_82542 {
914 struct e1000_dev_spec_82543 {
915 u32 tbi_compatibility;
917 bool init_phy_disabled;
920 struct e1000_dev_spec_82571 {
923 E1000_MUTEX swflag_mutex;
926 struct e1000_dev_spec_80003es2lan {
930 struct e1000_shadow_ram {
935 #define E1000_SHADOW_RAM_WORDS 2048
937 struct e1000_dev_spec_ich8lan {
938 bool kmrn_lock_loss_workaround_enabled;
939 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
940 E1000_MUTEX nvm_mutex;
941 E1000_MUTEX swflag_mutex;
947 struct e1000_dev_spec_82575 {
949 bool global_device_reset;
952 bool clear_semaphore_once;
954 struct sfp_e1000_flags eth_flags;
959 struct e1000_dev_spec_vf {
969 unsigned long io_base;
971 struct e1000_mac_info mac;
972 struct e1000_fc_info fc;
973 struct e1000_phy_info phy;
974 struct e1000_nvm_info nvm;
975 struct e1000_bus_info bus;
976 struct e1000_mbx_info mbx;
977 struct e1000_host_mng_dhcp_cookie mng_cookie;
980 struct e1000_dev_spec_82541 _82541;
981 struct e1000_dev_spec_82542 _82542;
982 struct e1000_dev_spec_82543 _82543;
983 struct e1000_dev_spec_82571 _82571;
984 struct e1000_dev_spec_80003es2lan _80003es2lan;
985 struct e1000_dev_spec_ich8lan ich8lan;
986 struct e1000_dev_spec_82575 _82575;
987 struct e1000_dev_spec_vf vf;
991 u16 subsystem_vendor_id;
992 u16 subsystem_device_id;
998 #include "e1000_82541.h"
999 #include "e1000_82543.h"
1000 #include "e1000_82571.h"
1001 #include "e1000_80003es2lan.h"
1002 #include "e1000_ich8lan.h"
1003 #include "e1000_82575.h"
1004 #include "e1000_i210.h"
1006 /* These functions must be implemented by drivers */
1007 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1008 void e1000_pci_set_mwi(struct e1000_hw *hw);
1009 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1010 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1011 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1012 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);