sys/dev/e1000/e1000_hw.h

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2015, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #ifndef _E1000_HW_H_
  36 #define _E1000_HW_H_
  37
  38 #include "e1000_osdep.h"
  39 #include "e1000_regs.h"
  40 #include "e1000_defines.h"
  41
  42 struct e1000_hw;
  43
  44 #define E1000_DEV_ID_82542                      0x1000
  45 #define E1000_DEV_ID_82543GC_FIBER              0x1001
  46 #define E1000_DEV_ID_82543GC_COPPER             0x1004
  47 #define E1000_DEV_ID_82544EI_COPPER             0x1008
  48 #define E1000_DEV_ID_82544EI_FIBER              0x1009
  49 #define E1000_DEV_ID_82544GC_COPPER             0x100C
  50 #define E1000_DEV_ID_82544GC_LOM                0x100D
  51 #define E1000_DEV_ID_82540EM                    0x100E
  52 #define E1000_DEV_ID_82540EM_LOM                0x1015
  53 #define E1000_DEV_ID_82540EP_LOM                0x1016
  54 #define E1000_DEV_ID_82540EP                    0x1017
  55 #define E1000_DEV_ID_82540EP_LP                 0x101E
  56 #define E1000_DEV_ID_82545EM_COPPER             0x100F
  57 #define E1000_DEV_ID_82545EM_FIBER              0x1011
  58 #define E1000_DEV_ID_82545GM_COPPER             0x1026
  59 #define E1000_DEV_ID_82545GM_FIBER              0x1027
  60 #define E1000_DEV_ID_82545GM_SERDES             0x1028
  61 #define E1000_DEV_ID_82546EB_COPPER             0x1010
  62 #define E1000_DEV_ID_82546EB_FIBER              0x1012
  63 #define E1000_DEV_ID_82546EB_QUAD_COPPER        0x101D
  64 #define E1000_DEV_ID_82546GB_COPPER             0x1079
  65 #define E1000_DEV_ID_82546GB_FIBER              0x107A
  66 #define E1000_DEV_ID_82546GB_SERDES             0x107B
  67 #define E1000_DEV_ID_82546GB_PCIE               0x108A
  68 #define E1000_DEV_ID_82546GB_QUAD_COPPER        0x1099
  69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3   0x10B5
  70 #define E1000_DEV_ID_82541EI                    0x1013
  71 #define E1000_DEV_ID_82541EI_MOBILE             0x1018
  72 #define E1000_DEV_ID_82541ER_LOM                0x1014
  73 #define E1000_DEV_ID_82541ER                    0x1078
  74 #define E1000_DEV_ID_82541GI                    0x1076
  75 #define E1000_DEV_ID_82541GI_LF                 0x107C
  76 #define E1000_DEV_ID_82541GI_MOBILE             0x1077
  77 #define E1000_DEV_ID_82547EI                    0x1019
  78 #define E1000_DEV_ID_82547EI_MOBILE             0x101A
  79 #define E1000_DEV_ID_82547GI                    0x1075
  80 #define E1000_DEV_ID_82571EB_COPPER             0x105E
  81 #define E1000_DEV_ID_82571EB_FIBER              0x105F
  82 #define E1000_DEV_ID_82571EB_SERDES             0x1060
  83 #define E1000_DEV_ID_82571EB_SERDES_DUAL        0x10D9
  84 #define E1000_DEV_ID_82571EB_SERDES_QUAD        0x10DA
  85 #define E1000_DEV_ID_82571EB_QUAD_COPPER        0x10A4
  86 #define E1000_DEV_ID_82571PT_QUAD_COPPER        0x10D5
  87 #define E1000_DEV_ID_82571EB_QUAD_FIBER         0x10A5
  88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP     0x10BC
  89 #define E1000_DEV_ID_82572EI_COPPER             0x107D
  90 #define E1000_DEV_ID_82572EI_FIBER              0x107E
  91 #define E1000_DEV_ID_82572EI_SERDES             0x107F
  92 #define E1000_DEV_ID_82572EI                    0x10B9
  93 #define E1000_DEV_ID_82573E                     0x108B
  94 #define E1000_DEV_ID_82573E_IAMT                0x108C
  95 #define E1000_DEV_ID_82573L                     0x109A
  96 #define E1000_DEV_ID_82574L                     0x10D3
  97 #define E1000_DEV_ID_82574LA                    0x10F6
  98 #define E1000_DEV_ID_82583V                     0x150C
  99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096
 100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098
 101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA
 102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB
 103 #define E1000_DEV_ID_ICH8_82567V_3              0x1501
 104 #define E1000_DEV_ID_ICH8_IGP_M_AMT             0x1049
 105 #define E1000_DEV_ID_ICH8_IGP_AMT               0x104A
 106 #define E1000_DEV_ID_ICH8_IGP_C                 0x104B
 107 #define E1000_DEV_ID_ICH8_IFE                   0x104C
 108 #define E1000_DEV_ID_ICH8_IFE_GT                0x10C4
 109 #define E1000_DEV_ID_ICH8_IFE_G                 0x10C5
 110 #define E1000_DEV_ID_ICH8_IGP_M                 0x104D
 111 #define E1000_DEV_ID_ICH9_IGP_M                 0x10BF
 112 #define E1000_DEV_ID_ICH9_IGP_M_AMT             0x10F5
 113 #define E1000_DEV_ID_ICH9_IGP_M_V               0x10CB
 114 #define E1000_DEV_ID_ICH9_IGP_AMT               0x10BD
 115 #define E1000_DEV_ID_ICH9_BM                    0x10E5
 116 #define E1000_DEV_ID_ICH9_IGP_C                 0x294C
 117 #define E1000_DEV_ID_ICH9_IFE                   0x10C0
 118 #define E1000_DEV_ID_ICH9_IFE_GT                0x10C3
 119 #define E1000_DEV_ID_ICH9_IFE_G                 0x10C2
 120 #define E1000_DEV_ID_ICH10_R_BM_LM              0x10CC
 121 #define E1000_DEV_ID_ICH10_R_BM_LF              0x10CD
 122 #define E1000_DEV_ID_ICH10_R_BM_V               0x10CE
 123 #define E1000_DEV_ID_ICH10_D_BM_LM              0x10DE
 124 #define E1000_DEV_ID_ICH10_D_BM_LF              0x10DF
 125 #define E1000_DEV_ID_ICH10_D_BM_V               0x1525
 126 #define E1000_DEV_ID_PCH_M_HV_LM                0x10EA
 127 #define E1000_DEV_ID_PCH_M_HV_LC                0x10EB
 128 #define E1000_DEV_ID_PCH_D_HV_DM                0x10EF
 129 #define E1000_DEV_ID_PCH_D_HV_DC                0x10F0
 130 #define E1000_DEV_ID_PCH2_LV_LM                 0x1502
 131 #define E1000_DEV_ID_PCH2_LV_V                  0x1503
 132 #define E1000_DEV_ID_PCH_LPT_I217_LM            0x153A
 133 #define E1000_DEV_ID_PCH_LPT_I217_V             0x153B
 134 #define E1000_DEV_ID_PCH_LPTLP_I218_LM          0x155A
 135 #define E1000_DEV_ID_PCH_LPTLP_I218_V           0x1559
 136 #define E1000_DEV_ID_PCH_I218_LM2               0x15A0
 137 #define E1000_DEV_ID_PCH_I218_V2                0x15A1
 138 #define E1000_DEV_ID_PCH_I218_LM3               0x15A2 /* Wildcat Point PCH */
 139 #define E1000_DEV_ID_PCH_I218_V3                0x15A3 /* Wildcat Point PCH */
 140 #define E1000_DEV_ID_PCH_SPT_I219_LM            0x156F /* Sunrise Point PCH */
 141 #define E1000_DEV_ID_PCH_SPT_I219_V             0x1570 /* Sunrise Point PCH */
 142 #define E1000_DEV_ID_PCH_SPT_I219_LM2           0x15B7 /* Sunrise Point-H PCH */
 143 #define E1000_DEV_ID_PCH_SPT_I219_V2            0x15B8 /* Sunrise Point-H PCH */
 144 #define E1000_DEV_ID_PCH_LBG_I219_LM3           0x15B9 /* LEWISBURG PCH */
 145 #define E1000_DEV_ID_PCH_SPT_I219_LM4           0x15D7
 146 #define E1000_DEV_ID_PCH_SPT_I219_V4            0x15D8
 147 #define E1000_DEV_ID_PCH_SPT_I219_LM5           0x15E3
 148 #define E1000_DEV_ID_PCH_SPT_I219_V5            0x15D6
 149 #define E1000_DEV_ID_82576                      0x10C9
 150 #define E1000_DEV_ID_82576_FIBER                0x10E6
 151 #define E1000_DEV_ID_82576_SERDES               0x10E7
 152 #define E1000_DEV_ID_82576_QUAD_COPPER          0x10E8
 153 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2      0x1526
 154 #define E1000_DEV_ID_82576_NS                   0x150A
 155 #define E1000_DEV_ID_82576_NS_SERDES            0x1518
 156 #define E1000_DEV_ID_82576_SERDES_QUAD          0x150D
 157 #define E1000_DEV_ID_82576_VF                   0x10CA
 158 #define E1000_DEV_ID_82576_VF_HV                0x152D
 159 #define E1000_DEV_ID_I350_VF                    0x1520
 160 #define E1000_DEV_ID_I350_VF_HV                 0x152F
 161 #define E1000_DEV_ID_82575EB_COPPER             0x10A7
 162 #define E1000_DEV_ID_82575EB_FIBER_SERDES       0x10A9
 163 #define E1000_DEV_ID_82575GB_QUAD_COPPER        0x10D6
 164 #define E1000_DEV_ID_82580_COPPER               0x150E
 165 #define E1000_DEV_ID_82580_FIBER                0x150F
 166 #define E1000_DEV_ID_82580_SERDES               0x1510
 167 #define E1000_DEV_ID_82580_SGMII                0x1511
 168 #define E1000_DEV_ID_82580_COPPER_DUAL          0x1516
 169 #define E1000_DEV_ID_82580_QUAD_FIBER           0x1527
 170 #define E1000_DEV_ID_I350_COPPER                0x1521
 171 #define E1000_DEV_ID_I350_FIBER                 0x1522
 172 #define E1000_DEV_ID_I350_SERDES                0x1523
 173 #define E1000_DEV_ID_I350_SGMII                 0x1524
 174 #define E1000_DEV_ID_I350_DA4                   0x1546
 175 #define E1000_DEV_ID_I210_COPPER                0x1533
 176 #define E1000_DEV_ID_I210_COPPER_OEM1           0x1534
 177 #define E1000_DEV_ID_I210_COPPER_IT             0x1535
 178 #define E1000_DEV_ID_I210_FIBER                 0x1536
 179 #define E1000_DEV_ID_I210_SERDES                0x1537
 180 #define E1000_DEV_ID_I210_SGMII                 0x1538
 181 #define E1000_DEV_ID_I210_COPPER_FLASHLESS      0x157B
 182 #define E1000_DEV_ID_I210_SERDES_FLASHLESS      0x157C
 183 #define E1000_DEV_ID_I211_COPPER                0x1539
 184 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS       0x1F40
 185 #define E1000_DEV_ID_I354_SGMII                 0x1F41
 186 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS     0x1F45
 187 #define E1000_DEV_ID_DH89XXCC_SGMII             0x0438
 188 #define E1000_DEV_ID_DH89XXCC_SERDES            0x043A
 189 #define E1000_DEV_ID_DH89XXCC_BACKPLANE         0x043C
 190 #define E1000_DEV_ID_DH89XXCC_SFP               0x0440
 191
 192 #define E1000_REVISION_0        0
 193 #define E1000_REVISION_1        1
 194 #define E1000_REVISION_2        2
 195 #define E1000_REVISION_3        3
 196 #define E1000_REVISION_4        4
 197
 198 #define E1000_FUNC_0            0
 199 #define E1000_FUNC_1            1
 200 #define E1000_FUNC_2            2
 201 #define E1000_FUNC_3            3
 202
 203 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0       0
 204 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1       3
 205 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2       6
 206 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3       9
 207
 208 enum e1000_mac_type {
 209         e1000_undefined = 0,
 210         e1000_82542,
 211         e1000_82543,
 212         e1000_82544,
 213         e1000_82540,
 214         e1000_82545,
 215         e1000_82545_rev_3,
 216         e1000_82546,
 217         e1000_82546_rev_3,
 218         e1000_82541,
 219         e1000_82541_rev_2,
 220         e1000_82547,
 221         e1000_82547_rev_2,
 222         e1000_82571,
 223         e1000_82572,
 224         e1000_82573,
 225         e1000_82574,
 226         e1000_82583,
 227         e1000_80003es2lan,
 228         e1000_ich8lan,
 229         e1000_ich9lan,
 230         e1000_ich10lan,
 231         e1000_pchlan,
 232         e1000_pch2lan,
 233         e1000_pch_lpt,
 234         e1000_pch_spt,
 235         e1000_82575,
 236         e1000_82576,
 237         e1000_82580,
 238         e1000_i350,
 239         e1000_i354,
 240         e1000_i210,
 241         e1000_i211,
 242         e1000_vfadapt,
 243         e1000_vfadapt_i350,
 244         e1000_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
 245 };
 246
 247 enum e1000_media_type {
 248         e1000_media_type_unknown = 0,
 249         e1000_media_type_copper = 1,
 250         e1000_media_type_fiber = 2,
 251         e1000_media_type_internal_serdes = 3,
 252         e1000_num_media_types
 253 };
 254
 255 enum e1000_nvm_type {
 256         e1000_nvm_unknown = 0,
 257         e1000_nvm_none,
 258         e1000_nvm_eeprom_spi,
 259         e1000_nvm_eeprom_microwire,
 260         e1000_nvm_flash_hw,
 261         e1000_nvm_invm,
 262         e1000_nvm_flash_sw
 263 };
 264
 265 enum e1000_nvm_override {
 266         e1000_nvm_override_none = 0,
 267         e1000_nvm_override_spi_small,
 268         e1000_nvm_override_spi_large,
 269         e1000_nvm_override_microwire_small,
 270         e1000_nvm_override_microwire_large
 271 };
 272
 273 enum e1000_phy_type {
 274         e1000_phy_unknown = 0,
 275         e1000_phy_none,
 276         e1000_phy_m88,
 277         e1000_phy_igp,
 278         e1000_phy_igp_2,
 279         e1000_phy_gg82563,
 280         e1000_phy_igp_3,
 281         e1000_phy_ife,
 282         e1000_phy_bm,
 283         e1000_phy_82578,
 284         e1000_phy_82577,
 285         e1000_phy_82579,
 286         e1000_phy_i217,
 287         e1000_phy_82580,
 288         e1000_phy_vf,
 289         e1000_phy_i210,
 290 };
 291
 292 enum e1000_bus_type {
 293         e1000_bus_type_unknown = 0,
 294         e1000_bus_type_pci,
 295         e1000_bus_type_pcix,
 296         e1000_bus_type_pci_express,
 297         e1000_bus_type_reserved
 298 };
 299
 300 enum e1000_bus_speed {
 301         e1000_bus_speed_unknown = 0,
 302         e1000_bus_speed_33,
 303         e1000_bus_speed_66,
 304         e1000_bus_speed_100,
 305         e1000_bus_speed_120,
 306         e1000_bus_speed_133,
 307         e1000_bus_speed_2500,
 308         e1000_bus_speed_5000,
 309         e1000_bus_speed_reserved
 310 };
 311
 312 enum e1000_bus_width {
 313         e1000_bus_width_unknown = 0,
 314         e1000_bus_width_pcie_x1,
 315         e1000_bus_width_pcie_x2,
 316         e1000_bus_width_pcie_x4 = 4,
 317         e1000_bus_width_pcie_x8 = 8,
 318         e1000_bus_width_32,
 319         e1000_bus_width_64,
 320         e1000_bus_width_reserved
 321 };
 322
 323 enum e1000_1000t_rx_status {
 324         e1000_1000t_rx_status_not_ok = 0,
 325         e1000_1000t_rx_status_ok,
 326         e1000_1000t_rx_status_undefined = 0xFF
 327 };
 328
 329 enum e1000_rev_polarity {
 330         e1000_rev_polarity_normal = 0,
 331         e1000_rev_polarity_reversed,
 332         e1000_rev_polarity_undefined = 0xFF
 333 };
 334
 335 enum e1000_fc_mode {
 336         e1000_fc_none = 0,
 337         e1000_fc_rx_pause,
 338         e1000_fc_tx_pause,
 339         e1000_fc_full,
 340         e1000_fc_default = 0xFF
 341 };
 342
 343 enum e1000_ffe_config {
 344         e1000_ffe_config_enabled = 0,
 345         e1000_ffe_config_active,
 346         e1000_ffe_config_blocked
 347 };
 348
 349 enum e1000_dsp_config {
 350         e1000_dsp_config_disabled = 0,
 351         e1000_dsp_config_enabled,
 352         e1000_dsp_config_activated,
 353         e1000_dsp_config_undefined = 0xFF
 354 };
 355
 356 enum e1000_ms_type {
 357         e1000_ms_hw_default = 0,
 358         e1000_ms_force_master,
 359         e1000_ms_force_slave,
 360         e1000_ms_auto
 361 };
 362
 363 enum e1000_smart_speed {
 364         e1000_smart_speed_default = 0,
 365         e1000_smart_speed_on,
 366         e1000_smart_speed_off
 367 };
 368
 369 enum e1000_serdes_link_state {
 370         e1000_serdes_link_down = 0,
 371         e1000_serdes_link_autoneg_progress,
 372         e1000_serdes_link_autoneg_complete,
 373         e1000_serdes_link_forced_up
 374 };
 375
 376 #define __le16 u16
 377 #define __le32 u32
 378 #define __le64 u64
 379 /* Receive Descriptor */
 380 struct e1000_rx_desc {
 381         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 382         __le16 length;      /* Length of data DMAed into data buffer */
 383         __le16 csum; /* Packet checksum */
 384         u8  status;  /* Descriptor status */
 385         u8  errors;  /* Descriptor Errors */
 386         __le16 special;
 387 };
 388
 389 /* Receive Descriptor - Extended */
 390 union e1000_rx_desc_extended {
 391         struct {
 392                 __le64 buffer_addr;
 393                 __le64 reserved;
 394         } read;
 395         struct {
 396                 struct {
 397                         __le32 mrq; /* Multiple Rx Queues */
 398                         union {
 399                                 __le32 rss; /* RSS Hash */
 400                                 struct {
 401                                         __le16 ip_id;  /* IP id */
 402                                         __le16 csum;   /* Packet Checksum */
 403                                 } csum_ip;
 404                         } hi_dword;
 405                 } lower;
 406                 struct {
 407                         __le32 status_error;  /* ext status/error */
 408                         __le16 length;
 409                         __le16 vlan; /* VLAN tag */
 410                 } upper;
 411         } wb;  /* writeback */
 412 };
 413
 414 #define MAX_PS_BUFFERS 4
 415
 416 /* Number of packet split data buffers (not including the header buffer) */
 417 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
 418
 419 /* Receive Descriptor - Packet Split */
 420 union e1000_rx_desc_packet_split {
 421         struct {
 422                 /* one buffer for protocol header(s), three data buffers */
 423                 __le64 buffer_addr[MAX_PS_BUFFERS];
 424         } read;
 425         struct {
 426                 struct {
 427                         __le32 mrq;  /* Multiple Rx Queues */
 428                         union {
 429                                 __le32 rss; /* RSS Hash */
 430                                 struct {
 431                                         __le16 ip_id;    /* IP id */
 432                                         __le16 csum;     /* Packet Checksum */
 433                                 } csum_ip;
 434                         } hi_dword;
 435                 } lower;
 436                 struct {
 437                         __le32 status_error;  /* ext status/error */
 438                         __le16 length0;  /* length of buffer 0 */
 439                         __le16 vlan;  /* VLAN tag */
 440                 } middle;
 441                 struct {
 442                         __le16 header_status;
 443                         /* length of buffers 1-3 */
 444                         __le16 length[PS_PAGE_BUFFERS];
 445                 } upper;
 446                 __le64 reserved;
 447         } wb; /* writeback */
 448 };
 449
 450 /* Transmit Descriptor */
 451 struct e1000_tx_desc {
 452         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 453         union {
 454                 __le32 data;
 455                 struct {
 456                         __le16 length;  /* Data buffer length */
 457                         u8 cso;  /* Checksum offset */
 458                         u8 cmd;  /* Descriptor control */
 459                 } flags;
 460         } lower;
 461         union {
 462                 __le32 data;
 463                 struct {
 464                         u8 status; /* Descriptor status */
 465                         u8 css;  /* Checksum start */
 466                         __le16 special;
 467                 } fields;
 468         } upper;
 469 };
 470
 471 /* Offload Context Descriptor */
 472 struct e1000_context_desc {
 473         union {
 474                 __le32 ip_config;
 475                 struct {
 476                         u8 ipcss;  /* IP checksum start */
 477                         u8 ipcso;  /* IP checksum offset */
 478                         __le16 ipcse;  /* IP checksum end */
 479                 } ip_fields;
 480         } lower_setup;
 481         union {
 482                 __le32 tcp_config;
 483                 struct {
 484                         u8 tucss;  /* TCP checksum start */
 485                         u8 tucso;  /* TCP checksum offset */
 486                         __le16 tucse;  /* TCP checksum end */
 487                 } tcp_fields;
 488         } upper_setup;
 489         __le32 cmd_and_length;
 490         union {
 491                 __le32 data;
 492                 struct {
 493                         u8 status;  /* Descriptor status */
 494                         u8 hdr_len;  /* Header length */
 495                         __le16 mss;  /* Maximum segment size */
 496                 } fields;
 497         } tcp_seg_setup;
 498 };
 499
 500 /* Offload data descriptor */
 501 struct e1000_data_desc {
 502         __le64 buffer_addr;  /* Address of the descriptor's buffer address */
 503         union {
 504                 __le32 data;
 505                 struct {
 506                         __le16 length;  /* Data buffer length */
 507                         u8 typ_len_ext;
 508                         u8 cmd;
 509                 } flags;
 510         } lower;
 511         union {
 512                 __le32 data;
 513                 struct {
 514                         u8 status;  /* Descriptor status */
 515                         u8 popts;  /* Packet Options */
 516                         __le16 special;
 517                 } fields;
 518         } upper;
 519 };
 520
 521 /* Statistics counters collected by the MAC */
 522 struct e1000_hw_stats {
 523         u64 crcerrs;
 524         u64 algnerrc;
 525         u64 symerrs;
 526         u64 rxerrc;
 527         u64 mpc;
 528         u64 scc;
 529         u64 ecol;
 530         u64 mcc;
 531         u64 latecol;
 532         u64 colc;
 533         u64 dc;
 534         u64 tncrs;
 535         u64 sec;
 536         u64 cexterr;
 537         u64 rlec;
 538         u64 xonrxc;
 539         u64 xontxc;
 540         u64 xoffrxc;
 541         u64 xofftxc;
 542         u64 fcruc;
 543         u64 prc64;
 544         u64 prc127;
 545         u64 prc255;
 546         u64 prc511;
 547         u64 prc1023;
 548         u64 prc1522;
 549         u64 gprc;
 550         u64 bprc;
 551         u64 mprc;
 552         u64 gptc;
 553         u64 gorc;
 554         u64 gotc;
 555         u64 rnbc;
 556         u64 ruc;
 557         u64 rfc;
 558         u64 roc;
 559         u64 rjc;
 560         u64 mgprc;
 561         u64 mgpdc;
 562         u64 mgptc;
 563         u64 tor;
 564         u64 tot;
 565         u64 tpr;
 566         u64 tpt;
 567         u64 ptc64;
 568         u64 ptc127;
 569         u64 ptc255;
 570         u64 ptc511;
 571         u64 ptc1023;
 572         u64 ptc1522;
 573         u64 mptc;
 574         u64 bptc;
 575         u64 tsctc;
 576         u64 tsctfc;
 577         u64 iac;
 578         u64 icrxptc;
 579         u64 icrxatc;
 580         u64 ictxptc;
 581         u64 ictxatc;
 582         u64 ictxqec;
 583         u64 ictxqmtc;
 584         u64 icrxdmtc;
 585         u64 icrxoc;
 586         u64 cbtmpc;
 587         u64 htdpmc;
 588         u64 cbrdpc;
 589         u64 cbrmpc;
 590         u64 rpthc;
 591         u64 hgptc;
 592         u64 htcbdpc;
 593         u64 hgorc;
 594         u64 hgotc;
 595         u64 lenerrs;
 596         u64 scvpc;
 597         u64 hrmpc;
 598         u64 doosync;
 599         u64 o2bgptc;
 600         u64 o2bspc;
 601         u64 b2ospc;
 602         u64 b2ogprc;
 603 };
 604
 605 struct e1000_vf_stats {
 606         u64 base_gprc;
 607         u64 base_gptc;
 608         u64 base_gorc;
 609         u64 base_gotc;
 610         u64 base_mprc;
 611         u64 base_gotlbc;
 612         u64 base_gptlbc;
 613         u64 base_gorlbc;
 614         u64 base_gprlbc;
 615
 616         u32 last_gprc;
 617         u32 last_gptc;
 618         u32 last_gorc;
 619         u32 last_gotc;
 620         u32 last_mprc;
 621         u32 last_gotlbc;
 622         u32 last_gptlbc;
 623         u32 last_gorlbc;
 624         u32 last_gprlbc;
 625
 626         u64 gprc;
 627         u64 gptc;
 628         u64 gorc;
 629         u64 gotc;
 630         u64 mprc;
 631         u64 gotlbc;
 632         u64 gptlbc;
 633         u64 gorlbc;
 634         u64 gprlbc;
 635 };
 636
 637 struct e1000_phy_stats {
 638         u32 idle_errors;
 639         u32 receive_errors;
 640 };
 641
 642 struct e1000_host_mng_dhcp_cookie {
 643         u32 signature;
 644         u8  status;
 645         u8  reserved0;
 646         u16 vlan_id;
 647         u32 reserved1;
 648         u16 reserved2;
 649         u8  reserved3;
 650         u8  checksum;
 651 };
 652
 653 /* Host Interface "Rev 1" */
 654 struct e1000_host_command_header {
 655         u8 command_id;
 656         u8 command_length;
 657         u8 command_options;
 658         u8 checksum;
 659 };
 660
 661 #define E1000_HI_MAX_DATA_LENGTH        252
 662 struct e1000_host_command_info {
 663         struct e1000_host_command_header command_header;
 664         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 665 };
 666
 667 /* Host Interface "Rev 2" */
 668 struct e1000_host_mng_command_header {
 669         u8  command_id;
 670         u8  checksum;
 671         u16 reserved1;
 672         u16 reserved2;
 673         u16 command_length;
 674 };
 675
 676 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
 677 struct e1000_host_mng_command_info {
 678         struct e1000_host_mng_command_header command_header;
 679         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 680 };
 681
 682 #include "e1000_mac.h"
 683 #include "e1000_phy.h"
 684 #include "e1000_nvm.h"
 685 #include "e1000_manage.h"
 686 #include "e1000_mbx.h"
 687
 688 /* Function pointers for the MAC. */
 689 struct e1000_mac_operations {
 690         s32  (*init_params)(struct e1000_hw *);
 691         s32  (*id_led_init)(struct e1000_hw *);
 692         s32  (*blink_led)(struct e1000_hw *);
 693         bool (*check_mng_mode)(struct e1000_hw *);
 694         s32  (*check_for_link)(struct e1000_hw *);
 695         s32  (*cleanup_led)(struct e1000_hw *);
 696         void (*clear_hw_cntrs)(struct e1000_hw *);
 697         void (*clear_vfta)(struct e1000_hw *);
 698         s32  (*get_bus_info)(struct e1000_hw *);
 699         void (*set_lan_id)(struct e1000_hw *);
 700         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 701         s32  (*led_on)(struct e1000_hw *);
 702         s32  (*led_off)(struct e1000_hw *);
 703         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 704         s32  (*reset_hw)(struct e1000_hw *);
 705         s32  (*init_hw)(struct e1000_hw *);
 706         void (*shutdown_serdes)(struct e1000_hw *);
 707         void (*power_up_serdes)(struct e1000_hw *);
 708         s32  (*setup_link)(struct e1000_hw *);
 709         s32  (*setup_physical_interface)(struct e1000_hw *);
 710         s32  (*setup_led)(struct e1000_hw *);
 711         void (*write_vfta)(struct e1000_hw *, u32, u32);
 712         void (*config_collision_dist)(struct e1000_hw *);
 713         int  (*rar_set)(struct e1000_hw *, u8*, u32);
 714         s32  (*read_mac_addr)(struct e1000_hw *);
 715         s32  (*validate_mdi_setting)(struct e1000_hw *);
 716         s32  (*set_obff_timer)(struct e1000_hw *, u32);
 717         s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
 718         void (*release_swfw_sync)(struct e1000_hw *, u16);
 719 };
 720
 721 /* When to use various PHY register access functions:
 722  *
 723  *                 Func   Caller
 724  *   Function      Does   Does    When to use
 725  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 726  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 727  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 728  *                                on different pages
 729  *   X_reg_page    A      L,P     for multiple accesses of different regs
 730  *                                on the same page
 731  *
 732  * Where X=[read|write], L=locking, P=sets page, A=register access
 733  *
 734  */
 735 struct e1000_phy_operations {
 736         s32  (*init_params)(struct e1000_hw *);
 737         s32  (*acquire)(struct e1000_hw *);
 738         s32  (*cfg_on_link_up)(struct e1000_hw *);
 739         s32  (*check_polarity)(struct e1000_hw *);
 740         s32  (*check_reset_block)(struct e1000_hw *);
 741         s32  (*commit)(struct e1000_hw *);
 742         s32  (*force_speed_duplex)(struct e1000_hw *);
 743         s32  (*get_cfg_done)(struct e1000_hw *hw);
 744         s32  (*get_cable_length)(struct e1000_hw *);
 745         s32  (*get_info)(struct e1000_hw *);
 746         s32  (*set_page)(struct e1000_hw *, u16);
 747         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 748         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 749         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 750         void (*release)(struct e1000_hw *);
 751         s32  (*reset)(struct e1000_hw *);
 752         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 753         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 754         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 755         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 756         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 757         void (*power_up)(struct e1000_hw *);
 758         void (*power_down)(struct e1000_hw *);
 759         s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
 760         s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
 761 };
 762
 763 /* Function pointers for the NVM. */
 764 struct e1000_nvm_operations {
 765         s32  (*init_params)(struct e1000_hw *);
 766         s32  (*acquire)(struct e1000_hw *);
 767         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 768         void (*release)(struct e1000_hw *);
 769         void (*reload)(struct e1000_hw *);
 770         s32  (*update)(struct e1000_hw *);
 771         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 772         s32  (*validate)(struct e1000_hw *);
 773         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 774 };
 775
 776 struct e1000_mac_info {
 777         struct e1000_mac_operations ops;
 778         u8 addr[ETH_ADDR_LEN];
 779         u8 perm_addr[ETH_ADDR_LEN];
 780
 781         enum e1000_mac_type type;
 782
 783         u32 collision_delta;
 784         u32 ledctl_default;
 785         u32 ledctl_mode1;
 786         u32 ledctl_mode2;
 787         u32 mc_filter_type;
 788         u32 tx_packet_delta;
 789         u32 txcw;
 790
 791         u16 current_ifs_val;
 792         u16 ifs_max_val;
 793         u16 ifs_min_val;
 794         u16 ifs_ratio;
 795         u16 ifs_step_size;
 796         u16 mta_reg_count;
 797         u16 uta_reg_count;
 798
 799         /* Maximum size of the MTA register table in all supported adapters */
 800 #define MAX_MTA_REG 128
 801         u32 mta_shadow[MAX_MTA_REG];
 802         u16 rar_entry_count;
 803
 804         u8  forced_speed_duplex;
 805
 806         bool adaptive_ifs;
 807         bool has_fwsm;
 808         bool arc_subsystem_valid;
 809         bool asf_firmware_present;
 810         bool autoneg;
 811         bool autoneg_failed;
 812         bool get_link_status;
 813         bool in_ifs_mode;
 814         bool report_tx_early;
 815         enum e1000_serdes_link_state serdes_link_state;
 816         bool serdes_has_link;
 817         bool tx_pkt_filtering;
 818         u32  max_frame_size;
 819 };
 820
 821 struct e1000_phy_info {
 822         struct e1000_phy_operations ops;
 823         enum e1000_phy_type type;
 824
 825         enum e1000_1000t_rx_status local_rx;
 826         enum e1000_1000t_rx_status remote_rx;
 827         enum e1000_ms_type ms_type;
 828         enum e1000_ms_type original_ms_type;
 829         enum e1000_rev_polarity cable_polarity;
 830         enum e1000_smart_speed smart_speed;
 831
 832         u32 addr;
 833         u32 id;
 834         u32 reset_delay_us; /* in usec */
 835         u32 revision;
 836
 837         enum e1000_media_type media_type;
 838
 839         u16 autoneg_advertised;
 840         u16 autoneg_mask;
 841         u16 cable_length;
 842         u16 max_cable_length;
 843         u16 min_cable_length;
 844
 845         u8 mdix;
 846
 847         bool disable_polarity_correction;
 848         bool is_mdix;
 849         bool polarity_correction;
 850         bool speed_downgraded;
 851         bool autoneg_wait_to_complete;
 852 };
 853
 854 struct e1000_nvm_info {
 855         struct e1000_nvm_operations ops;
 856         enum e1000_nvm_type type;
 857         enum e1000_nvm_override override;
 858
 859         u32 flash_bank_size;
 860         u32 flash_base_addr;
 861
 862         u16 word_size;
 863         u16 delay_usec;
 864         u16 address_bits;
 865         u16 opcode_bits;
 866         u16 page_size;
 867 };
 868
 869 struct e1000_bus_info {
 870         enum e1000_bus_type type;
 871         enum e1000_bus_speed speed;
 872         enum e1000_bus_width width;
 873
 874         u16 func;
 875         u16 pci_cmd_word;
 876 };
 877
 878 struct e1000_fc_info {
 879         u32 high_water;  /* Flow control high-water mark */
 880         u32 low_water;  /* Flow control low-water mark */
 881         u16 pause_time;  /* Flow control pause timer */
 882         u16 refresh_time;  /* Flow control refresh timer */
 883         bool send_xon;  /* Flow control send XON */
 884         bool strict_ieee;  /* Strict IEEE mode */
 885         enum e1000_fc_mode current_mode;  /* FC mode in effect */
 886         enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
 887 };
 888
 889 struct e1000_mbx_operations {
 890         s32 (*init_params)(struct e1000_hw *hw);
 891         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 892         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 893         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 894         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 895         s32 (*check_for_msg)(struct e1000_hw *, u16);
 896         s32 (*check_for_ack)(struct e1000_hw *, u16);
 897         s32 (*check_for_rst)(struct e1000_hw *, u16);
 898 };
 899
 900 struct e1000_mbx_stats {
 901         u32 msgs_tx;
 902         u32 msgs_rx;
 903
 904         u32 acks;
 905         u32 reqs;
 906         u32 rsts;
 907 };
 908
 909 struct e1000_mbx_info {
 910         struct e1000_mbx_operations ops;
 911         struct e1000_mbx_stats stats;
 912         u32 timeout;
 913         u32 usec_delay;
 914         u16 size;
 915 };
 916
 917 struct e1000_dev_spec_82541 {
 918         enum e1000_dsp_config dsp_config;
 919         enum e1000_ffe_config ffe_config;
 920         u16 spd_default;
 921         bool phy_init_script;
 922 };
 923
 924 struct e1000_dev_spec_82542 {
 925         bool dma_fairness;
 926 };
 927
 928 struct e1000_dev_spec_82543 {
 929         u32  tbi_compatibility;
 930         bool dma_fairness;
 931         bool init_phy_disabled;
 932 };
 933
 934 struct e1000_dev_spec_82571 {
 935         bool laa_is_present;
 936         u32 smb_counter;
 937         E1000_MUTEX swflag_mutex;
 938 };
 939
 940 struct e1000_dev_spec_80003es2lan {
 941         bool  mdic_wa_enable;
 942 };
 943
 944 struct e1000_shadow_ram {
 945         u16  value;
 946         bool modified;
 947 };
 948
 949 #define E1000_SHADOW_RAM_WORDS          2048
 950
 951 /* I218 PHY Ultra Low Power (ULP) states */
 952 enum e1000_ulp_state {
 953         e1000_ulp_state_unknown,
 954         e1000_ulp_state_off,
 955         e1000_ulp_state_on,
 956 };
 957
 958 struct e1000_dev_spec_ich8lan {
 959         bool kmrn_lock_loss_workaround_enabled;
 960         struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
 961         E1000_MUTEX nvm_mutex;
 962         E1000_MUTEX swflag_mutex;
 963         bool nvm_k1_enabled;
 964         bool disable_k1_off;
 965         bool eee_disable;
 966         u16 eee_lp_ability;
 967         enum e1000_ulp_state ulp_state;
 968         bool ulp_capability_disabled;
 969         bool during_suspend_flow;
 970         bool during_dpg_exit;
 971 };
 972
 973 struct e1000_dev_spec_82575 {
 974         bool sgmii_active;
 975         bool global_device_reset;
 976         bool eee_disable;
 977         bool module_plugged;
 978         bool clear_semaphore_once;
 979         u32 mtu;
 980         struct sfp_e1000_flags eth_flags;
 981         u8 media_port;
 982         bool media_changed;
 983 };
 984
 985 struct e1000_dev_spec_vf {
 986         u32 vf_number;
 987         u32 v2p_mailbox;
 988 };
 989
 990 struct e1000_hw {
 991         void *back;
 992
 993         u8 *hw_addr;
 994         u8 *flash_address;
 995         unsigned long io_base;
 996
 997         struct e1000_mac_info  mac;
 998         struct e1000_fc_info   fc;
 999         struct e1000_phy_info  phy;
1000         struct e1000_nvm_info  nvm;
1001         struct e1000_bus_info  bus;
1002         struct e1000_mbx_info mbx;
1003         struct e1000_host_mng_dhcp_cookie mng_cookie;
1004
1005         union {
1006                 struct e1000_dev_spec_82541 _82541;
1007                 struct e1000_dev_spec_82542 _82542;
1008                 struct e1000_dev_spec_82543 _82543;
1009                 struct e1000_dev_spec_82571 _82571;
1010                 struct e1000_dev_spec_80003es2lan _80003es2lan;
1011                 struct e1000_dev_spec_ich8lan ich8lan;
1012                 struct e1000_dev_spec_82575 _82575;
1013                 struct e1000_dev_spec_vf vf;
1014         } dev_spec;
1015
1016         u16 device_id;
1017         u16 subsystem_vendor_id;
1018         u16 subsystem_device_id;
1019         u16 vendor_id;
1020
1021         u8  revision_id;
1022 };
1023
1024 #include "e1000_82541.h"
1025 #include "e1000_82543.h"
1026 #include "e1000_82571.h"
1027 #include "e1000_80003es2lan.h"
1028 #include "e1000_ich8lan.h"
1029 #include "e1000_82575.h"
1030 #include "e1000_i210.h"
1031
1032 /* These functions must be implemented by drivers */
1033 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1034 void e1000_pci_set_mwi(struct e1000_hw *hw);
1035 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1036 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1037 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1038 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1039
1040 #endif