sys/dev/e1000/e1000_hw.h

   1 /******************************************************************************
   2   SPDX-License-Identifier: BSD-3-Clause
   3
   4   Copyright (c) 2001-2015, Intel Corporation
   5   All rights reserved.
   6
   7   Redistribution and use in source and binary forms, with or without
   8   modification, are permitted provided that the following conditions are met:
   9
  10    1. Redistributions of source code must retain the above copyright notice,
  11       this list of conditions and the following disclaimer.
  12
  13    2. Redistributions in binary form must reproduce the above copyright
  14       notice, this list of conditions and the following disclaimer in the
  15       documentation and/or other materials provided with the distribution.
  16
  17    3. Neither the name of the Intel Corporation nor the names of its
  18       contributors may be used to endorse or promote products derived from
  19       this software without specific prior written permission.
  20
  21   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31   POSSIBILITY OF SUCH DAMAGE.
  32
  33 ******************************************************************************/
  34 /*$FreeBSD$*/
  35
  36 #ifndef _E1000_HW_H_
  37 #define _E1000_HW_H_
  38
  39 #include "e1000_osdep.h"
  40 #include "e1000_regs.h"
  41 #include "e1000_defines.h"
  42
  43 struct e1000_hw;
  44
  45 #define E1000_DEV_ID_82542                      0x1000
  46 #define E1000_DEV_ID_82543GC_FIBER              0x1001
  47 #define E1000_DEV_ID_82543GC_COPPER             0x1004
  48 #define E1000_DEV_ID_82544EI_COPPER             0x1008
  49 #define E1000_DEV_ID_82544EI_FIBER              0x1009
  50 #define E1000_DEV_ID_82544GC_COPPER             0x100C
  51 #define E1000_DEV_ID_82544GC_LOM                0x100D
  52 #define E1000_DEV_ID_82540EM                    0x100E
  53 #define E1000_DEV_ID_82540EM_LOM                0x1015
  54 #define E1000_DEV_ID_82540EP_LOM                0x1016
  55 #define E1000_DEV_ID_82540EP                    0x1017
  56 #define E1000_DEV_ID_82540EP_LP                 0x101E
  57 #define E1000_DEV_ID_82545EM_COPPER             0x100F
  58 #define E1000_DEV_ID_82545EM_FIBER              0x1011
  59 #define E1000_DEV_ID_82545GM_COPPER             0x1026
  60 #define E1000_DEV_ID_82545GM_FIBER              0x1027
  61 #define E1000_DEV_ID_82545GM_SERDES             0x1028
  62 #define E1000_DEV_ID_82546EB_COPPER             0x1010
  63 #define E1000_DEV_ID_82546EB_FIBER              0x1012
  64 #define E1000_DEV_ID_82546EB_QUAD_COPPER        0x101D
  65 #define E1000_DEV_ID_82546GB_COPPER             0x1079
  66 #define E1000_DEV_ID_82546GB_FIBER              0x107A
  67 #define E1000_DEV_ID_82546GB_SERDES             0x107B
  68 #define E1000_DEV_ID_82546GB_PCIE               0x108A
  69 #define E1000_DEV_ID_82546GB_QUAD_COPPER        0x1099
  70 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3   0x10B5
  71 #define E1000_DEV_ID_82541EI                    0x1013
  72 #define E1000_DEV_ID_82541EI_MOBILE             0x1018
  73 #define E1000_DEV_ID_82541ER_LOM                0x1014
  74 #define E1000_DEV_ID_82541ER                    0x1078
  75 #define E1000_DEV_ID_82541GI                    0x1076
  76 #define E1000_DEV_ID_82541GI_LF                 0x107C
  77 #define E1000_DEV_ID_82541GI_MOBILE             0x1077
  78 #define E1000_DEV_ID_82547EI                    0x1019
  79 #define E1000_DEV_ID_82547EI_MOBILE             0x101A
  80 #define E1000_DEV_ID_82547GI                    0x1075
  81 #define E1000_DEV_ID_82571EB_COPPER             0x105E
  82 #define E1000_DEV_ID_82571EB_FIBER              0x105F
  83 #define E1000_DEV_ID_82571EB_SERDES             0x1060
  84 #define E1000_DEV_ID_82571EB_SERDES_DUAL        0x10D9
  85 #define E1000_DEV_ID_82571EB_SERDES_QUAD        0x10DA
  86 #define E1000_DEV_ID_82571EB_QUAD_COPPER        0x10A4
  87 #define E1000_DEV_ID_82571PT_QUAD_COPPER        0x10D5
  88 #define E1000_DEV_ID_82571EB_QUAD_FIBER         0x10A5
  89 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP     0x10BC
  90 #define E1000_DEV_ID_82572EI_COPPER             0x107D
  91 #define E1000_DEV_ID_82572EI_FIBER              0x107E
  92 #define E1000_DEV_ID_82572EI_SERDES             0x107F
  93 #define E1000_DEV_ID_82572EI                    0x10B9
  94 #define E1000_DEV_ID_82573E                     0x108B
  95 #define E1000_DEV_ID_82573E_IAMT                0x108C
  96 #define E1000_DEV_ID_82573L                     0x109A
  97 #define E1000_DEV_ID_82574L                     0x10D3
  98 #define E1000_DEV_ID_82574LA                    0x10F6
  99 #define E1000_DEV_ID_82583V                     0x150C
 100 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096
 101 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098
 102 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA
 103 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB
 104 #define E1000_DEV_ID_ICH8_82567V_3              0x1501
 105 #define E1000_DEV_ID_ICH8_IGP_M_AMT             0x1049
 106 #define E1000_DEV_ID_ICH8_IGP_AMT               0x104A
 107 #define E1000_DEV_ID_ICH8_IGP_C                 0x104B
 108 #define E1000_DEV_ID_ICH8_IFE                   0x104C
 109 #define E1000_DEV_ID_ICH8_IFE_GT                0x10C4
 110 #define E1000_DEV_ID_ICH8_IFE_G                 0x10C5
 111 #define E1000_DEV_ID_ICH8_IGP_M                 0x104D
 112 #define E1000_DEV_ID_ICH9_IGP_M                 0x10BF
 113 #define E1000_DEV_ID_ICH9_IGP_M_AMT             0x10F5
 114 #define E1000_DEV_ID_ICH9_IGP_M_V               0x10CB
 115 #define E1000_DEV_ID_ICH9_IGP_AMT               0x10BD
 116 #define E1000_DEV_ID_ICH9_BM                    0x10E5
 117 #define E1000_DEV_ID_ICH9_IGP_C                 0x294C
 118 #define E1000_DEV_ID_ICH9_IFE                   0x10C0
 119 #define E1000_DEV_ID_ICH9_IFE_GT                0x10C3
 120 #define E1000_DEV_ID_ICH9_IFE_G                 0x10C2
 121 #define E1000_DEV_ID_ICH10_R_BM_LM              0x10CC
 122 #define E1000_DEV_ID_ICH10_R_BM_LF              0x10CD
 123 #define E1000_DEV_ID_ICH10_R_BM_V               0x10CE
 124 #define E1000_DEV_ID_ICH10_D_BM_LM              0x10DE
 125 #define E1000_DEV_ID_ICH10_D_BM_LF              0x10DF
 126 #define E1000_DEV_ID_ICH10_D_BM_V               0x1525
 127 #define E1000_DEV_ID_PCH_M_HV_LM                0x10EA
 128 #define E1000_DEV_ID_PCH_M_HV_LC                0x10EB
 129 #define E1000_DEV_ID_PCH_D_HV_DM                0x10EF
 130 #define E1000_DEV_ID_PCH_D_HV_DC                0x10F0
 131 #define E1000_DEV_ID_PCH2_LV_LM                 0x1502
 132 #define E1000_DEV_ID_PCH2_LV_V                  0x1503
 133 #define E1000_DEV_ID_PCH_LPT_I217_LM            0x153A
 134 #define E1000_DEV_ID_PCH_LPT_I217_V             0x153B
 135 #define E1000_DEV_ID_PCH_LPTLP_I218_LM          0x155A
 136 #define E1000_DEV_ID_PCH_LPTLP_I218_V           0x1559
 137 #define E1000_DEV_ID_PCH_I218_LM2               0x15A0
 138 #define E1000_DEV_ID_PCH_I218_V2                0x15A1
 139 #define E1000_DEV_ID_PCH_I218_LM3               0x15A2 /* Wildcat Point PCH */
 140 #define E1000_DEV_ID_PCH_I218_V3                0x15A3 /* Wildcat Point PCH */
 141 #define E1000_DEV_ID_PCH_SPT_I219_LM            0x156F /* Sunrise Point PCH */
 142 #define E1000_DEV_ID_PCH_SPT_I219_V             0x1570 /* Sunrise Point PCH */
 143 #define E1000_DEV_ID_PCH_SPT_I219_LM2           0x15B7 /* Sunrise Point-H PCH */
 144 #define E1000_DEV_ID_PCH_SPT_I219_V2            0x15B8 /* Sunrise Point-H PCH */
 145 #define E1000_DEV_ID_PCH_LBG_I219_LM3           0x15B9 /* LEWISBURG PCH */
 146 #define E1000_DEV_ID_PCH_SPT_I219_LM4           0x15D7
 147 #define E1000_DEV_ID_PCH_SPT_I219_V4            0x15D8
 148 #define E1000_DEV_ID_PCH_SPT_I219_LM5           0x15E3
 149 #define E1000_DEV_ID_PCH_SPT_I219_V5            0x15D6
 150 #define E1000_DEV_ID_PCH_CNP_I219_LM6           0x15BD
 151 #define E1000_DEV_ID_PCH_CNP_I219_V6            0x15BE
 152 #define E1000_DEV_ID_PCH_CNP_I219_LM7           0x15BB
 153 #define E1000_DEV_ID_PCH_CNP_I219_V7            0x15BC
 154 #define E1000_DEV_ID_PCH_ICP_I219_LM8           0x15DF
 155 #define E1000_DEV_ID_PCH_ICP_I219_V8            0x15E0
 156 #define E1000_DEV_ID_PCH_ICP_I219_LM9           0x15E1
 157 #define E1000_DEV_ID_PCH_ICP_I219_V9            0x15E2
 158 #define E1000_DEV_ID_PCH_CMP_I219_LM10          0x0D4E
 159 #define E1000_DEV_ID_PCH_CMP_I219_V10           0x0D4F
 160 #define E1000_DEV_ID_PCH_CMP_I219_LM11          0x0D4C
 161 #define E1000_DEV_ID_PCH_CMP_I219_V11           0x0D4D
 162 #define E1000_DEV_ID_PCH_CMP_I219_LM12          0x0D53
 163 #define E1000_DEV_ID_PCH_CMP_I219_V12           0x0D55
 164 #define E1000_DEV_ID_82576                      0x10C9
 165 #define E1000_DEV_ID_82576_FIBER                0x10E6
 166 #define E1000_DEV_ID_82576_SERDES               0x10E7
 167 #define E1000_DEV_ID_82576_QUAD_COPPER          0x10E8
 168 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2      0x1526
 169 #define E1000_DEV_ID_82576_NS                   0x150A
 170 #define E1000_DEV_ID_82576_NS_SERDES            0x1518
 171 #define E1000_DEV_ID_82576_SERDES_QUAD          0x150D
 172 #define E1000_DEV_ID_82576_VF                   0x10CA
 173 #define E1000_DEV_ID_82576_VF_HV                0x152D
 174 #define E1000_DEV_ID_I350_VF                    0x1520
 175 #define E1000_DEV_ID_I350_VF_HV                 0x152F
 176 #define E1000_DEV_ID_82575EB_COPPER             0x10A7
 177 #define E1000_DEV_ID_82575EB_FIBER_SERDES       0x10A9
 178 #define E1000_DEV_ID_82575GB_QUAD_COPPER        0x10D6
 179 #define E1000_DEV_ID_82580_COPPER               0x150E
 180 #define E1000_DEV_ID_82580_FIBER                0x150F
 181 #define E1000_DEV_ID_82580_SERDES               0x1510
 182 #define E1000_DEV_ID_82580_SGMII                0x1511
 183 #define E1000_DEV_ID_82580_COPPER_DUAL          0x1516
 184 #define E1000_DEV_ID_82580_QUAD_FIBER           0x1527
 185 #define E1000_DEV_ID_I350_COPPER                0x1521
 186 #define E1000_DEV_ID_I350_FIBER                 0x1522
 187 #define E1000_DEV_ID_I350_SERDES                0x1523
 188 #define E1000_DEV_ID_I350_SGMII                 0x1524
 189 #define E1000_DEV_ID_I350_DA4                   0x1546
 190 #define E1000_DEV_ID_I210_COPPER                0x1533
 191 #define E1000_DEV_ID_I210_COPPER_OEM1           0x1534
 192 #define E1000_DEV_ID_I210_COPPER_IT             0x1535
 193 #define E1000_DEV_ID_I210_FIBER                 0x1536
 194 #define E1000_DEV_ID_I210_SERDES                0x1537
 195 #define E1000_DEV_ID_I210_SGMII                 0x1538
 196 #define E1000_DEV_ID_I210_COPPER_FLASHLESS      0x157B
 197 #define E1000_DEV_ID_I210_SERDES_FLASHLESS      0x157C
 198 #define E1000_DEV_ID_I211_COPPER                0x1539
 199 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS       0x1F40
 200 #define E1000_DEV_ID_I354_SGMII                 0x1F41
 201 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS     0x1F45
 202 #define E1000_DEV_ID_DH89XXCC_SGMII             0x0438
 203 #define E1000_DEV_ID_DH89XXCC_SERDES            0x043A
 204 #define E1000_DEV_ID_DH89XXCC_BACKPLANE         0x043C
 205 #define E1000_DEV_ID_DH89XXCC_SFP               0x0440
 206
 207 #define E1000_REVISION_0        0
 208 #define E1000_REVISION_1        1
 209 #define E1000_REVISION_2        2
 210 #define E1000_REVISION_3        3
 211 #define E1000_REVISION_4        4
 212
 213 #define E1000_FUNC_0            0
 214 #define E1000_FUNC_1            1
 215 #define E1000_FUNC_2            2
 216 #define E1000_FUNC_3            3
 217
 218 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0       0
 219 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1       3
 220 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2       6
 221 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3       9
 222
 223 enum e1000_mac_type {
 224         e1000_undefined = 0,
 225         e1000_82542,
 226         e1000_82543,
 227         e1000_82544,
 228         e1000_82540,
 229         e1000_82545,
 230         e1000_82545_rev_3,
 231         e1000_82546,
 232         e1000_82546_rev_3,
 233         e1000_82541,
 234         e1000_82541_rev_2,
 235         e1000_82547,
 236         e1000_82547_rev_2,
 237         e1000_82571,
 238         e1000_82572,
 239         e1000_82573,
 240         e1000_82574,
 241         e1000_82583,
 242         e1000_80003es2lan,
 243         e1000_ich8lan,
 244         e1000_ich9lan,
 245         e1000_ich10lan,
 246         e1000_pchlan,
 247         e1000_pch2lan,
 248         e1000_pch_lpt,
 249         e1000_pch_spt,
 250         e1000_pch_cnp,
 251         e1000_82575,
 252         e1000_82576,
 253         e1000_82580,
 254         e1000_i350,
 255         e1000_i354,
 256         e1000_i210,
 257         e1000_i211,
 258         e1000_vfadapt,
 259         e1000_vfadapt_i350,
 260         e1000_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
 261 };
 262
 263 enum e1000_media_type {
 264         e1000_media_type_unknown = 0,
 265         e1000_media_type_copper = 1,
 266         e1000_media_type_fiber = 2,
 267         e1000_media_type_internal_serdes = 3,
 268         e1000_num_media_types
 269 };
 270
 271 enum e1000_nvm_type {
 272         e1000_nvm_unknown = 0,
 273         e1000_nvm_none,
 274         e1000_nvm_eeprom_spi,
 275         e1000_nvm_eeprom_microwire,
 276         e1000_nvm_flash_hw,
 277         e1000_nvm_invm,
 278         e1000_nvm_flash_sw
 279 };
 280
 281 enum e1000_nvm_override {
 282         e1000_nvm_override_none = 0,
 283         e1000_nvm_override_spi_small,
 284         e1000_nvm_override_spi_large,
 285         e1000_nvm_override_microwire_small,
 286         e1000_nvm_override_microwire_large
 287 };
 288
 289 enum e1000_phy_type {
 290         e1000_phy_unknown = 0,
 291         e1000_phy_none,
 292         e1000_phy_m88,
 293         e1000_phy_igp,
 294         e1000_phy_igp_2,
 295         e1000_phy_gg82563,
 296         e1000_phy_igp_3,
 297         e1000_phy_ife,
 298         e1000_phy_bm,
 299         e1000_phy_82578,
 300         e1000_phy_82577,
 301         e1000_phy_82579,
 302         e1000_phy_i217,
 303         e1000_phy_82580,
 304         e1000_phy_vf,
 305         e1000_phy_i210,
 306 };
 307
 308 enum e1000_bus_type {
 309         e1000_bus_type_unknown = 0,
 310         e1000_bus_type_pci,
 311         e1000_bus_type_pcix,
 312         e1000_bus_type_pci_express,
 313         e1000_bus_type_reserved
 314 };
 315
 316 enum e1000_bus_speed {
 317         e1000_bus_speed_unknown = 0,
 318         e1000_bus_speed_33,
 319         e1000_bus_speed_66,
 320         e1000_bus_speed_100,
 321         e1000_bus_speed_120,
 322         e1000_bus_speed_133,
 323         e1000_bus_speed_2500,
 324         e1000_bus_speed_5000,
 325         e1000_bus_speed_reserved
 326 };
 327
 328 enum e1000_bus_width {
 329         e1000_bus_width_unknown = 0,
 330         e1000_bus_width_pcie_x1,
 331         e1000_bus_width_pcie_x2,
 332         e1000_bus_width_pcie_x4 = 4,
 333         e1000_bus_width_pcie_x8 = 8,
 334         e1000_bus_width_32,
 335         e1000_bus_width_64,
 336         e1000_bus_width_reserved
 337 };
 338
 339 enum e1000_1000t_rx_status {
 340         e1000_1000t_rx_status_not_ok = 0,
 341         e1000_1000t_rx_status_ok,
 342         e1000_1000t_rx_status_undefined = 0xFF
 343 };
 344
 345 enum e1000_rev_polarity {
 346         e1000_rev_polarity_normal = 0,
 347         e1000_rev_polarity_reversed,
 348         e1000_rev_polarity_undefined = 0xFF
 349 };
 350
 351 enum e1000_fc_mode {
 352         e1000_fc_none = 0,
 353         e1000_fc_rx_pause,
 354         e1000_fc_tx_pause,
 355         e1000_fc_full,
 356         e1000_fc_default = 0xFF
 357 };
 358
 359 enum e1000_ffe_config {
 360         e1000_ffe_config_enabled = 0,
 361         e1000_ffe_config_active,
 362         e1000_ffe_config_blocked
 363 };
 364
 365 enum e1000_dsp_config {
 366         e1000_dsp_config_disabled = 0,
 367         e1000_dsp_config_enabled,
 368         e1000_dsp_config_activated,
 369         e1000_dsp_config_undefined = 0xFF
 370 };
 371
 372 enum e1000_ms_type {
 373         e1000_ms_hw_default = 0,
 374         e1000_ms_force_master,
 375         e1000_ms_force_slave,
 376         e1000_ms_auto
 377 };
 378
 379 enum e1000_smart_speed {
 380         e1000_smart_speed_default = 0,
 381         e1000_smart_speed_on,
 382         e1000_smart_speed_off
 383 };
 384
 385 enum e1000_serdes_link_state {
 386         e1000_serdes_link_down = 0,
 387         e1000_serdes_link_autoneg_progress,
 388         e1000_serdes_link_autoneg_complete,
 389         e1000_serdes_link_forced_up
 390 };
 391
 392 #define __le16 u16
 393 #define __le32 u32
 394 #define __le64 u64
 395 /* Receive Descriptor */
 396 struct e1000_rx_desc {
 397         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 398         __le16 length;      /* Length of data DMAed into data buffer */
 399         __le16 csum; /* Packet checksum */
 400         u8  status;  /* Descriptor status */
 401         u8  errors;  /* Descriptor Errors */
 402         __le16 special;
 403 };
 404
 405 /* Receive Descriptor - Extended */
 406 union e1000_rx_desc_extended {
 407         struct {
 408                 __le64 buffer_addr;
 409                 __le64 reserved;
 410         } read;
 411         struct {
 412                 struct {
 413                         __le32 mrq; /* Multiple Rx Queues */
 414                         union {
 415                                 __le32 rss; /* RSS Hash */
 416                                 struct {
 417                                         __le16 ip_id;  /* IP id */
 418                                         __le16 csum;   /* Packet Checksum */
 419                                 } csum_ip;
 420                         } hi_dword;
 421                 } lower;
 422                 struct {
 423                         __le32 status_error;  /* ext status/error */
 424                         __le16 length;
 425                         __le16 vlan; /* VLAN tag */
 426                 } upper;
 427         } wb;  /* writeback */
 428 };
 429
 430 #define MAX_PS_BUFFERS 4
 431
 432 /* Number of packet split data buffers (not including the header buffer) */
 433 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
 434
 435 /* Receive Descriptor - Packet Split */
 436 union e1000_rx_desc_packet_split {
 437         struct {
 438                 /* one buffer for protocol header(s), three data buffers */
 439                 __le64 buffer_addr[MAX_PS_BUFFERS];
 440         } read;
 441         struct {
 442                 struct {
 443                         __le32 mrq;  /* Multiple Rx Queues */
 444                         union {
 445                                 __le32 rss; /* RSS Hash */
 446                                 struct {
 447                                         __le16 ip_id;    /* IP id */
 448                                         __le16 csum;     /* Packet Checksum */
 449                                 } csum_ip;
 450                         } hi_dword;
 451                 } lower;
 452                 struct {
 453                         __le32 status_error;  /* ext status/error */
 454                         __le16 length0;  /* length of buffer 0 */
 455                         __le16 vlan;  /* VLAN tag */
 456                 } middle;
 457                 struct {
 458                         __le16 header_status;
 459                         /* length of buffers 1-3 */
 460                         __le16 length[PS_PAGE_BUFFERS];
 461                 } upper;
 462                 __le64 reserved;
 463         } wb; /* writeback */
 464 };
 465
 466 /* Transmit Descriptor */
 467 struct e1000_tx_desc {
 468         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 469         union {
 470                 __le32 data;
 471                 struct {
 472                         __le16 length;  /* Data buffer length */
 473                         u8 cso;  /* Checksum offset */
 474                         u8 cmd;  /* Descriptor control */
 475                 } flags;
 476         } lower;
 477         union {
 478                 __le32 data;
 479                 struct {
 480                         u8 status; /* Descriptor status */
 481                         u8 css;  /* Checksum start */
 482                         __le16 special;
 483                 } fields;
 484         } upper;
 485 };
 486
 487 /* Offload Context Descriptor */
 488 struct e1000_context_desc {
 489         union {
 490                 __le32 ip_config;
 491                 struct {
 492                         u8 ipcss;  /* IP checksum start */
 493                         u8 ipcso;  /* IP checksum offset */
 494                         __le16 ipcse;  /* IP checksum end */
 495                 } ip_fields;
 496         } lower_setup;
 497         union {
 498                 __le32 tcp_config;
 499                 struct {
 500                         u8 tucss;  /* TCP checksum start */
 501                         u8 tucso;  /* TCP checksum offset */
 502                         __le16 tucse;  /* TCP checksum end */
 503                 } tcp_fields;
 504         } upper_setup;
 505         __le32 cmd_and_length;
 506         union {
 507                 __le32 data;
 508                 struct {
 509                         u8 status;  /* Descriptor status */
 510                         u8 hdr_len;  /* Header length */
 511                         __le16 mss;  /* Maximum segment size */
 512                 } fields;
 513         } tcp_seg_setup;
 514 };
 515
 516 /* Offload data descriptor */
 517 struct e1000_data_desc {
 518         __le64 buffer_addr;  /* Address of the descriptor's buffer address */
 519         union {
 520                 __le32 data;
 521                 struct {
 522                         __le16 length;  /* Data buffer length */
 523                         u8 typ_len_ext;
 524                         u8 cmd;
 525                 } flags;
 526         } lower;
 527         union {
 528                 __le32 data;
 529                 struct {
 530                         u8 status;  /* Descriptor status */
 531                         u8 popts;  /* Packet Options */
 532                         __le16 special;
 533                 } fields;
 534         } upper;
 535 };
 536
 537 /* Statistics counters collected by the MAC */
 538 struct e1000_hw_stats {
 539         u64 crcerrs;
 540         u64 algnerrc;
 541         u64 symerrs;
 542         u64 rxerrc;
 543         u64 mpc;
 544         u64 scc;
 545         u64 ecol;
 546         u64 mcc;
 547         u64 latecol;
 548         u64 colc;
 549         u64 dc;
 550         u64 tncrs;
 551         u64 sec;
 552         u64 cexterr;
 553         u64 rlec;
 554         u64 xonrxc;
 555         u64 xontxc;
 556         u64 xoffrxc;
 557         u64 xofftxc;
 558         u64 fcruc;
 559         u64 prc64;
 560         u64 prc127;
 561         u64 prc255;
 562         u64 prc511;
 563         u64 prc1023;
 564         u64 prc1522;
 565         u64 gprc;
 566         u64 bprc;
 567         u64 mprc;
 568         u64 gptc;
 569         u64 gorc;
 570         u64 gotc;
 571         u64 rnbc;
 572         u64 ruc;
 573         u64 rfc;
 574         u64 roc;
 575         u64 rjc;
 576         u64 mgprc;
 577         u64 mgpdc;
 578         u64 mgptc;
 579         u64 tor;
 580         u64 tot;
 581         u64 tpr;
 582         u64 tpt;
 583         u64 ptc64;
 584         u64 ptc127;
 585         u64 ptc255;
 586         u64 ptc511;
 587         u64 ptc1023;
 588         u64 ptc1522;
 589         u64 mptc;
 590         u64 bptc;
 591         u64 tsctc;
 592         u64 tsctfc;
 593         u64 iac;
 594         u64 icrxptc;
 595         u64 icrxatc;
 596         u64 ictxptc;
 597         u64 ictxatc;
 598         u64 ictxqec;
 599         u64 ictxqmtc;
 600         u64 icrxdmtc;
 601         u64 icrxoc;
 602         u64 cbtmpc;
 603         u64 htdpmc;
 604         u64 cbrdpc;
 605         u64 cbrmpc;
 606         u64 rpthc;
 607         u64 hgptc;
 608         u64 htcbdpc;
 609         u64 hgorc;
 610         u64 hgotc;
 611         u64 lenerrs;
 612         u64 scvpc;
 613         u64 hrmpc;
 614         u64 doosync;
 615         u64 o2bgptc;
 616         u64 o2bspc;
 617         u64 b2ospc;
 618         u64 b2ogprc;
 619 };
 620
 621 struct e1000_vf_stats {
 622         u64 base_gprc;
 623         u64 base_gptc;
 624         u64 base_gorc;
 625         u64 base_gotc;
 626         u64 base_mprc;
 627         u64 base_gotlbc;
 628         u64 base_gptlbc;
 629         u64 base_gorlbc;
 630         u64 base_gprlbc;
 631
 632         u32 last_gprc;
 633         u32 last_gptc;
 634         u32 last_gorc;
 635         u32 last_gotc;
 636         u32 last_mprc;
 637         u32 last_gotlbc;
 638         u32 last_gptlbc;
 639         u32 last_gorlbc;
 640         u32 last_gprlbc;
 641
 642         u64 gprc;
 643         u64 gptc;
 644         u64 gorc;
 645         u64 gotc;
 646         u64 mprc;
 647         u64 gotlbc;
 648         u64 gptlbc;
 649         u64 gorlbc;
 650         u64 gprlbc;
 651 };
 652
 653 struct e1000_phy_stats {
 654         u32 idle_errors;
 655         u32 receive_errors;
 656 };
 657
 658 struct e1000_host_mng_dhcp_cookie {
 659         u32 signature;
 660         u8  status;
 661         u8  reserved0;
 662         u16 vlan_id;
 663         u32 reserved1;
 664         u16 reserved2;
 665         u8  reserved3;
 666         u8  checksum;
 667 };
 668
 669 /* Host Interface "Rev 1" */
 670 struct e1000_host_command_header {
 671         u8 command_id;
 672         u8 command_length;
 673         u8 command_options;
 674         u8 checksum;
 675 };
 676
 677 #define E1000_HI_MAX_DATA_LENGTH        252
 678 struct e1000_host_command_info {
 679         struct e1000_host_command_header command_header;
 680         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 681 };
 682
 683 /* Host Interface "Rev 2" */
 684 struct e1000_host_mng_command_header {
 685         u8  command_id;
 686         u8  checksum;
 687         u16 reserved1;
 688         u16 reserved2;
 689         u16 command_length;
 690 };
 691
 692 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
 693 struct e1000_host_mng_command_info {
 694         struct e1000_host_mng_command_header command_header;
 695         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 696 };
 697
 698 #include "e1000_mac.h"
 699 #include "e1000_phy.h"
 700 #include "e1000_nvm.h"
 701 #include "e1000_manage.h"
 702 #include "e1000_mbx.h"
 703
 704 /* Function pointers for the MAC. */
 705 struct e1000_mac_operations {
 706         s32  (*init_params)(struct e1000_hw *);
 707         s32  (*id_led_init)(struct e1000_hw *);
 708         s32  (*blink_led)(struct e1000_hw *);
 709         bool (*check_mng_mode)(struct e1000_hw *);
 710         s32  (*check_for_link)(struct e1000_hw *);
 711         s32  (*cleanup_led)(struct e1000_hw *);
 712         void (*clear_hw_cntrs)(struct e1000_hw *);
 713         void (*clear_vfta)(struct e1000_hw *);
 714         s32  (*get_bus_info)(struct e1000_hw *);
 715         void (*set_lan_id)(struct e1000_hw *);
 716         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 717         s32  (*led_on)(struct e1000_hw *);
 718         s32  (*led_off)(struct e1000_hw *);
 719         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 720         s32  (*reset_hw)(struct e1000_hw *);
 721         s32  (*init_hw)(struct e1000_hw *);
 722         void (*shutdown_serdes)(struct e1000_hw *);
 723         void (*power_up_serdes)(struct e1000_hw *);
 724         s32  (*setup_link)(struct e1000_hw *);
 725         s32  (*setup_physical_interface)(struct e1000_hw *);
 726         s32  (*setup_led)(struct e1000_hw *);
 727         void (*write_vfta)(struct e1000_hw *, u32, u32);
 728         void (*config_collision_dist)(struct e1000_hw *);
 729         int  (*rar_set)(struct e1000_hw *, u8*, u32);
 730         s32  (*read_mac_addr)(struct e1000_hw *);
 731         s32  (*validate_mdi_setting)(struct e1000_hw *);
 732         s32  (*set_obff_timer)(struct e1000_hw *, u32);
 733         s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
 734         void (*release_swfw_sync)(struct e1000_hw *, u16);
 735 };
 736
 737 /* When to use various PHY register access functions:
 738  *
 739  *                 Func   Caller
 740  *   Function      Does   Does    When to use
 741  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 742  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 743  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 744  *                                on different pages
 745  *   X_reg_page    A      L,P     for multiple accesses of different regs
 746  *                                on the same page
 747  *
 748  * Where X=[read|write], L=locking, P=sets page, A=register access
 749  *
 750  */
 751 struct e1000_phy_operations {
 752         s32  (*init_params)(struct e1000_hw *);
 753         s32  (*acquire)(struct e1000_hw *);
 754         s32  (*cfg_on_link_up)(struct e1000_hw *);
 755         s32  (*check_polarity)(struct e1000_hw *);
 756         s32  (*check_reset_block)(struct e1000_hw *);
 757         s32  (*commit)(struct e1000_hw *);
 758         s32  (*force_speed_duplex)(struct e1000_hw *);
 759         s32  (*get_cfg_done)(struct e1000_hw *hw);
 760         s32  (*get_cable_length)(struct e1000_hw *);
 761         s32  (*get_info)(struct e1000_hw *);
 762         s32  (*set_page)(struct e1000_hw *, u16);
 763         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 764         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 765         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 766         void (*release)(struct e1000_hw *);
 767         s32  (*reset)(struct e1000_hw *);
 768         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 769         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 770         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 771         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 772         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 773         void (*power_up)(struct e1000_hw *);
 774         void (*power_down)(struct e1000_hw *);
 775         s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
 776         s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
 777 };
 778
 779 /* Function pointers for the NVM. */
 780 struct e1000_nvm_operations {
 781         s32  (*init_params)(struct e1000_hw *);
 782         s32  (*acquire)(struct e1000_hw *);
 783         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 784         void (*release)(struct e1000_hw *);
 785         void (*reload)(struct e1000_hw *);
 786         s32  (*update)(struct e1000_hw *);
 787         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 788         s32  (*validate)(struct e1000_hw *);
 789         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 790 };
 791
 792 struct e1000_mac_info {
 793         struct e1000_mac_operations ops;
 794         u8 addr[ETHER_ADDR_LEN];
 795         u8 perm_addr[ETHER_ADDR_LEN];
 796
 797         enum e1000_mac_type type;
 798
 799         u32 collision_delta;
 800         u32 ledctl_default;
 801         u32 ledctl_mode1;
 802         u32 ledctl_mode2;
 803         u32 mc_filter_type;
 804         u32 tx_packet_delta;
 805         u32 txcw;
 806
 807         u16 current_ifs_val;
 808         u16 ifs_max_val;
 809         u16 ifs_min_val;
 810         u16 ifs_ratio;
 811         u16 ifs_step_size;
 812         u16 mta_reg_count;
 813         u16 uta_reg_count;
 814
 815         /* Maximum size of the MTA register table in all supported adapters */
 816 #define MAX_MTA_REG 128
 817         u32 mta_shadow[MAX_MTA_REG];
 818         u16 rar_entry_count;
 819
 820         u8  forced_speed_duplex;
 821
 822         bool adaptive_ifs;
 823         bool has_fwsm;
 824         bool arc_subsystem_valid;
 825         bool asf_firmware_present;
 826         bool autoneg;
 827         bool autoneg_failed;
 828         bool get_link_status;
 829         bool in_ifs_mode;
 830         bool report_tx_early;
 831         enum e1000_serdes_link_state serdes_link_state;
 832         bool serdes_has_link;
 833         bool tx_pkt_filtering;
 834         u32  max_frame_size;
 835 };
 836
 837 struct e1000_phy_info {
 838         struct e1000_phy_operations ops;
 839         enum e1000_phy_type type;
 840
 841         enum e1000_1000t_rx_status local_rx;
 842         enum e1000_1000t_rx_status remote_rx;
 843         enum e1000_ms_type ms_type;
 844         enum e1000_ms_type original_ms_type;
 845         enum e1000_rev_polarity cable_polarity;
 846         enum e1000_smart_speed smart_speed;
 847
 848         u32 addr;
 849         u32 id;
 850         u32 reset_delay_us; /* in usec */
 851         u32 revision;
 852
 853         enum e1000_media_type media_type;
 854
 855         u16 autoneg_advertised;
 856         u16 autoneg_mask;
 857         u16 cable_length;
 858         u16 max_cable_length;
 859         u16 min_cable_length;
 860
 861         u8 mdix;
 862
 863         bool disable_polarity_correction;
 864         bool is_mdix;
 865         bool polarity_correction;
 866         bool speed_downgraded;
 867         bool autoneg_wait_to_complete;
 868 };
 869
 870 struct e1000_nvm_info {
 871         struct e1000_nvm_operations ops;
 872         enum e1000_nvm_type type;
 873         enum e1000_nvm_override override;
 874
 875         u32 flash_bank_size;
 876         u32 flash_base_addr;
 877
 878         u16 word_size;
 879         u16 delay_usec;
 880         u16 address_bits;
 881         u16 opcode_bits;
 882         u16 page_size;
 883 };
 884
 885 struct e1000_bus_info {
 886         enum e1000_bus_type type;
 887         enum e1000_bus_speed speed;
 888         enum e1000_bus_width width;
 889
 890         u16 func;
 891         u16 pci_cmd_word;
 892 };
 893
 894 struct e1000_fc_info {
 895         u32 high_water;  /* Flow control high-water mark */
 896         u32 low_water;  /* Flow control low-water mark */
 897         u16 pause_time;  /* Flow control pause timer */
 898         u16 refresh_time;  /* Flow control refresh timer */
 899         bool send_xon;  /* Flow control send XON */
 900         bool strict_ieee;  /* Strict IEEE mode */
 901         enum e1000_fc_mode current_mode;  /* FC mode in effect */
 902         enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
 903 };
 904
 905 struct e1000_mbx_operations {
 906         s32 (*init_params)(struct e1000_hw *hw);
 907         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 908         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 909         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 910         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 911         s32 (*check_for_msg)(struct e1000_hw *, u16);
 912         s32 (*check_for_ack)(struct e1000_hw *, u16);
 913         s32 (*check_for_rst)(struct e1000_hw *, u16);
 914 };
 915
 916 struct e1000_mbx_stats {
 917         u32 msgs_tx;
 918         u32 msgs_rx;
 919
 920         u32 acks;
 921         u32 reqs;
 922         u32 rsts;
 923 };
 924
 925 struct e1000_mbx_info {
 926         struct e1000_mbx_operations ops;
 927         struct e1000_mbx_stats stats;
 928         u32 timeout;
 929         u32 usec_delay;
 930         u16 size;
 931 };
 932
 933 struct e1000_dev_spec_82541 {
 934         enum e1000_dsp_config dsp_config;
 935         enum e1000_ffe_config ffe_config;
 936         u16 spd_default;
 937         bool phy_init_script;
 938 };
 939
 940 struct e1000_dev_spec_82542 {
 941         bool dma_fairness;
 942 };
 943
 944 struct e1000_dev_spec_82543 {
 945         u32  tbi_compatibility;
 946         bool dma_fairness;
 947         bool init_phy_disabled;
 948 };
 949
 950 struct e1000_dev_spec_82571 {
 951         bool laa_is_present;
 952         u32 smb_counter;
 953 };
 954
 955 struct e1000_dev_spec_80003es2lan {
 956         bool  mdic_wa_enable;
 957 };
 958
 959 struct e1000_shadow_ram {
 960         u16  value;
 961         bool modified;
 962 };
 963
 964 #define E1000_SHADOW_RAM_WORDS          2048
 965
 966 /* I218 PHY Ultra Low Power (ULP) states */
 967 enum e1000_ulp_state {
 968         e1000_ulp_state_unknown,
 969         e1000_ulp_state_off,
 970         e1000_ulp_state_on,
 971 };
 972
 973 struct e1000_dev_spec_ich8lan {
 974         bool kmrn_lock_loss_workaround_enabled;
 975         struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
 976         bool nvm_k1_enabled;
 977         bool disable_k1_off;
 978         bool eee_disable;
 979         u16 eee_lp_ability;
 980         enum e1000_ulp_state ulp_state;
 981         bool ulp_capability_disabled;
 982         bool during_suspend_flow;
 983         bool during_dpg_exit;
 984 };
 985
 986 struct e1000_dev_spec_82575 {
 987         bool sgmii_active;
 988         bool global_device_reset;
 989         bool eee_disable;
 990         bool module_plugged;
 991         bool clear_semaphore_once;
 992         u32 mtu;
 993         struct sfp_e1000_flags eth_flags;
 994         u8 media_port;
 995         bool media_changed;
 996 };
 997
 998 struct e1000_dev_spec_vf {
 999         u32 vf_number;
1000         u32 v2p_mailbox;
1001 };
1002
1003 struct e1000_hw {
1004         void *back;
1005
1006         u8 *hw_addr;
1007         u8 *flash_address;
1008         unsigned long io_base;
1009
1010         struct e1000_mac_info  mac;
1011         struct e1000_fc_info   fc;
1012         struct e1000_phy_info  phy;
1013         struct e1000_nvm_info  nvm;
1014         struct e1000_bus_info  bus;
1015         struct e1000_mbx_info mbx;
1016         struct e1000_host_mng_dhcp_cookie mng_cookie;
1017
1018         union {
1019                 struct e1000_dev_spec_82541 _82541;
1020                 struct e1000_dev_spec_82542 _82542;
1021                 struct e1000_dev_spec_82543 _82543;
1022                 struct e1000_dev_spec_82571 _82571;
1023                 struct e1000_dev_spec_80003es2lan _80003es2lan;
1024                 struct e1000_dev_spec_ich8lan ich8lan;
1025                 struct e1000_dev_spec_82575 _82575;
1026                 struct e1000_dev_spec_vf vf;
1027         } dev_spec;
1028
1029         u16 device_id;
1030         u16 subsystem_vendor_id;
1031         u16 subsystem_device_id;
1032         u16 vendor_id;
1033
1034         u8  revision_id;
1035 };
1036
1037 #include "e1000_82541.h"
1038 #include "e1000_82543.h"
1039 #include "e1000_82571.h"
1040 #include "e1000_80003es2lan.h"
1041 #include "e1000_ich8lan.h"
1042 #include "e1000_82575.h"
1043 #include "e1000_i210.h"
1044
1045 /* These functions must be implemented by drivers */
1046 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1047 void e1000_pci_set_mwi(struct e1000_hw *hw);
1048 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1049 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1050 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1051 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1052
1053 #endif