1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2015, Intel Corporation
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
33 ******************************************************************************/
39 #include "e1000_osdep.h"
40 #include "e1000_regs.h"
41 #include "e1000_defines.h"
45 #define E1000_DEV_ID_82542 0x1000
46 #define E1000_DEV_ID_82543GC_FIBER 0x1001
47 #define E1000_DEV_ID_82543GC_COPPER 0x1004
48 #define E1000_DEV_ID_82544EI_COPPER 0x1008
49 #define E1000_DEV_ID_82544EI_FIBER 0x1009
50 #define E1000_DEV_ID_82544GC_COPPER 0x100C
51 #define E1000_DEV_ID_82544GC_LOM 0x100D
52 #define E1000_DEV_ID_82540EM 0x100E
53 #define E1000_DEV_ID_82540EM_LOM 0x1015
54 #define E1000_DEV_ID_82540EP_LOM 0x1016
55 #define E1000_DEV_ID_82540EP 0x1017
56 #define E1000_DEV_ID_82540EP_LP 0x101E
57 #define E1000_DEV_ID_82545EM_COPPER 0x100F
58 #define E1000_DEV_ID_82545EM_FIBER 0x1011
59 #define E1000_DEV_ID_82545GM_COPPER 0x1026
60 #define E1000_DEV_ID_82545GM_FIBER 0x1027
61 #define E1000_DEV_ID_82545GM_SERDES 0x1028
62 #define E1000_DEV_ID_82546EB_COPPER 0x1010
63 #define E1000_DEV_ID_82546EB_FIBER 0x1012
64 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
65 #define E1000_DEV_ID_82546GB_COPPER 0x1079
66 #define E1000_DEV_ID_82546GB_FIBER 0x107A
67 #define E1000_DEV_ID_82546GB_SERDES 0x107B
68 #define E1000_DEV_ID_82546GB_PCIE 0x108A
69 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
70 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
71 #define E1000_DEV_ID_82541EI 0x1013
72 #define E1000_DEV_ID_82541EI_MOBILE 0x1018
73 #define E1000_DEV_ID_82541ER_LOM 0x1014
74 #define E1000_DEV_ID_82541ER 0x1078
75 #define E1000_DEV_ID_82541GI 0x1076
76 #define E1000_DEV_ID_82541GI_LF 0x107C
77 #define E1000_DEV_ID_82541GI_MOBILE 0x1077
78 #define E1000_DEV_ID_82547EI 0x1019
79 #define E1000_DEV_ID_82547EI_MOBILE 0x101A
80 #define E1000_DEV_ID_82547GI 0x1075
81 #define E1000_DEV_ID_82571EB_COPPER 0x105E
82 #define E1000_DEV_ID_82571EB_FIBER 0x105F
83 #define E1000_DEV_ID_82571EB_SERDES 0x1060
84 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
85 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
86 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
87 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
88 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
89 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
90 #define E1000_DEV_ID_82572EI_COPPER 0x107D
91 #define E1000_DEV_ID_82572EI_FIBER 0x107E
92 #define E1000_DEV_ID_82572EI_SERDES 0x107F
93 #define E1000_DEV_ID_82572EI 0x10B9
94 #define E1000_DEV_ID_82573E 0x108B
95 #define E1000_DEV_ID_82573E_IAMT 0x108C
96 #define E1000_DEV_ID_82573L 0x109A
97 #define E1000_DEV_ID_82574L 0x10D3
98 #define E1000_DEV_ID_82574LA 0x10F6
99 #define E1000_DEV_ID_82583V 0x150C
100 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
101 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
102 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
103 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
104 #define E1000_DEV_ID_ICH8_82567V_3 0x1501
105 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
106 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
107 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
108 #define E1000_DEV_ID_ICH8_IFE 0x104C
109 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
110 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
111 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
112 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF
113 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
114 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
115 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
116 #define E1000_DEV_ID_ICH9_BM 0x10E5
117 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
118 #define E1000_DEV_ID_ICH9_IFE 0x10C0
119 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
120 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
121 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
122 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
123 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
124 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
125 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
126 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525
127 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
128 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
129 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
130 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
131 #define E1000_DEV_ID_PCH2_LV_LM 0x1502
132 #define E1000_DEV_ID_PCH2_LV_V 0x1503
133 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
134 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
135 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
136 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
137 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0
138 #define E1000_DEV_ID_PCH_I218_V2 0x15A1
139 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */
140 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */
141 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */
142 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */
143 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */
144 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */
145 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */
146 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7
147 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8
148 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3
149 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6
150 #define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD
151 #define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE
152 #define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB
153 #define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC
154 #define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF
155 #define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0
156 #define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1
157 #define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2
158 #define E1000_DEV_ID_PCH_CMP_I219_LM10 0x0D4E
159 #define E1000_DEV_ID_PCH_CMP_I219_V10 0x0D4F
160 #define E1000_DEV_ID_PCH_CMP_I219_LM11 0x0D4C
161 #define E1000_DEV_ID_PCH_CMP_I219_V11 0x0D4D
162 #define E1000_DEV_ID_PCH_CMP_I219_LM12 0x0D53
163 #define E1000_DEV_ID_PCH_CMP_I219_V12 0x0D55
164 #define E1000_DEV_ID_82576 0x10C9
165 #define E1000_DEV_ID_82576_FIBER 0x10E6
166 #define E1000_DEV_ID_82576_SERDES 0x10E7
167 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
168 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
169 #define E1000_DEV_ID_82576_NS 0x150A
170 #define E1000_DEV_ID_82576_NS_SERDES 0x1518
171 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
172 #define E1000_DEV_ID_82576_VF 0x10CA
173 #define E1000_DEV_ID_82576_VF_HV 0x152D
174 #define E1000_DEV_ID_I350_VF 0x1520
175 #define E1000_DEV_ID_I350_VF_HV 0x152F
176 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
177 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
178 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
179 #define E1000_DEV_ID_82580_COPPER 0x150E
180 #define E1000_DEV_ID_82580_FIBER 0x150F
181 #define E1000_DEV_ID_82580_SERDES 0x1510
182 #define E1000_DEV_ID_82580_SGMII 0x1511
183 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
184 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
185 #define E1000_DEV_ID_I350_COPPER 0x1521
186 #define E1000_DEV_ID_I350_FIBER 0x1522
187 #define E1000_DEV_ID_I350_SERDES 0x1523
188 #define E1000_DEV_ID_I350_SGMII 0x1524
189 #define E1000_DEV_ID_I350_DA4 0x1546
190 #define E1000_DEV_ID_I210_COPPER 0x1533
191 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534
192 #define E1000_DEV_ID_I210_COPPER_IT 0x1535
193 #define E1000_DEV_ID_I210_FIBER 0x1536
194 #define E1000_DEV_ID_I210_SERDES 0x1537
195 #define E1000_DEV_ID_I210_SGMII 0x1538
196 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B
197 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C
198 #define E1000_DEV_ID_I211_COPPER 0x1539
199 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40
200 #define E1000_DEV_ID_I354_SGMII 0x1F41
201 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45
202 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
203 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
204 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
205 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440
207 #define E1000_REVISION_0 0
208 #define E1000_REVISION_1 1
209 #define E1000_REVISION_2 2
210 #define E1000_REVISION_3 3
211 #define E1000_REVISION_4 4
213 #define E1000_FUNC_0 0
214 #define E1000_FUNC_1 1
215 #define E1000_FUNC_2 2
216 #define E1000_FUNC_3 3
218 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
219 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
220 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
221 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
223 enum e1000_mac_type {
260 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
263 enum e1000_media_type {
264 e1000_media_type_unknown = 0,
265 e1000_media_type_copper = 1,
266 e1000_media_type_fiber = 2,
267 e1000_media_type_internal_serdes = 3,
268 e1000_num_media_types
271 enum e1000_nvm_type {
272 e1000_nvm_unknown = 0,
274 e1000_nvm_eeprom_spi,
275 e1000_nvm_eeprom_microwire,
281 enum e1000_nvm_override {
282 e1000_nvm_override_none = 0,
283 e1000_nvm_override_spi_small,
284 e1000_nvm_override_spi_large,
285 e1000_nvm_override_microwire_small,
286 e1000_nvm_override_microwire_large
289 enum e1000_phy_type {
290 e1000_phy_unknown = 0,
308 enum e1000_bus_type {
309 e1000_bus_type_unknown = 0,
312 e1000_bus_type_pci_express,
313 e1000_bus_type_reserved
316 enum e1000_bus_speed {
317 e1000_bus_speed_unknown = 0,
323 e1000_bus_speed_2500,
324 e1000_bus_speed_5000,
325 e1000_bus_speed_reserved
328 enum e1000_bus_width {
329 e1000_bus_width_unknown = 0,
330 e1000_bus_width_pcie_x1,
331 e1000_bus_width_pcie_x2,
332 e1000_bus_width_pcie_x4 = 4,
333 e1000_bus_width_pcie_x8 = 8,
336 e1000_bus_width_reserved
339 enum e1000_1000t_rx_status {
340 e1000_1000t_rx_status_not_ok = 0,
341 e1000_1000t_rx_status_ok,
342 e1000_1000t_rx_status_undefined = 0xFF
345 enum e1000_rev_polarity {
346 e1000_rev_polarity_normal = 0,
347 e1000_rev_polarity_reversed,
348 e1000_rev_polarity_undefined = 0xFF
356 e1000_fc_default = 0xFF
359 enum e1000_ffe_config {
360 e1000_ffe_config_enabled = 0,
361 e1000_ffe_config_active,
362 e1000_ffe_config_blocked
365 enum e1000_dsp_config {
366 e1000_dsp_config_disabled = 0,
367 e1000_dsp_config_enabled,
368 e1000_dsp_config_activated,
369 e1000_dsp_config_undefined = 0xFF
373 e1000_ms_hw_default = 0,
374 e1000_ms_force_master,
375 e1000_ms_force_slave,
379 enum e1000_smart_speed {
380 e1000_smart_speed_default = 0,
381 e1000_smart_speed_on,
382 e1000_smart_speed_off
385 enum e1000_serdes_link_state {
386 e1000_serdes_link_down = 0,
387 e1000_serdes_link_autoneg_progress,
388 e1000_serdes_link_autoneg_complete,
389 e1000_serdes_link_forced_up
395 /* Receive Descriptor */
396 struct e1000_rx_desc {
397 __le64 buffer_addr; /* Address of the descriptor's data buffer */
398 __le16 length; /* Length of data DMAed into data buffer */
399 __le16 csum; /* Packet checksum */
400 u8 status; /* Descriptor status */
401 u8 errors; /* Descriptor Errors */
405 /* Receive Descriptor - Extended */
406 union e1000_rx_desc_extended {
413 __le32 mrq; /* Multiple Rx Queues */
415 __le32 rss; /* RSS Hash */
417 __le16 ip_id; /* IP id */
418 __le16 csum; /* Packet Checksum */
423 __le32 status_error; /* ext status/error */
425 __le16 vlan; /* VLAN tag */
427 } wb; /* writeback */
430 #define MAX_PS_BUFFERS 4
432 /* Number of packet split data buffers (not including the header buffer) */
433 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
435 /* Receive Descriptor - Packet Split */
436 union e1000_rx_desc_packet_split {
438 /* one buffer for protocol header(s), three data buffers */
439 __le64 buffer_addr[MAX_PS_BUFFERS];
443 __le32 mrq; /* Multiple Rx Queues */
445 __le32 rss; /* RSS Hash */
447 __le16 ip_id; /* IP id */
448 __le16 csum; /* Packet Checksum */
453 __le32 status_error; /* ext status/error */
454 __le16 length0; /* length of buffer 0 */
455 __le16 vlan; /* VLAN tag */
458 __le16 header_status;
459 /* length of buffers 1-3 */
460 __le16 length[PS_PAGE_BUFFERS];
463 } wb; /* writeback */
466 /* Transmit Descriptor */
467 struct e1000_tx_desc {
468 __le64 buffer_addr; /* Address of the descriptor's data buffer */
472 __le16 length; /* Data buffer length */
473 u8 cso; /* Checksum offset */
474 u8 cmd; /* Descriptor control */
480 u8 status; /* Descriptor status */
481 u8 css; /* Checksum start */
487 /* Offload Context Descriptor */
488 struct e1000_context_desc {
492 u8 ipcss; /* IP checksum start */
493 u8 ipcso; /* IP checksum offset */
494 __le16 ipcse; /* IP checksum end */
500 u8 tucss; /* TCP checksum start */
501 u8 tucso; /* TCP checksum offset */
502 __le16 tucse; /* TCP checksum end */
505 __le32 cmd_and_length;
509 u8 status; /* Descriptor status */
510 u8 hdr_len; /* Header length */
511 __le16 mss; /* Maximum segment size */
516 /* Offload data descriptor */
517 struct e1000_data_desc {
518 __le64 buffer_addr; /* Address of the descriptor's buffer address */
522 __le16 length; /* Data buffer length */
530 u8 status; /* Descriptor status */
531 u8 popts; /* Packet Options */
537 /* Statistics counters collected by the MAC */
538 struct e1000_hw_stats {
621 struct e1000_vf_stats {
653 struct e1000_phy_stats {
658 struct e1000_host_mng_dhcp_cookie {
669 /* Host Interface "Rev 1" */
670 struct e1000_host_command_header {
677 #define E1000_HI_MAX_DATA_LENGTH 252
678 struct e1000_host_command_info {
679 struct e1000_host_command_header command_header;
680 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
683 /* Host Interface "Rev 2" */
684 struct e1000_host_mng_command_header {
692 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
693 struct e1000_host_mng_command_info {
694 struct e1000_host_mng_command_header command_header;
695 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
698 #include "e1000_mac.h"
699 #include "e1000_phy.h"
700 #include "e1000_nvm.h"
701 #include "e1000_manage.h"
702 #include "e1000_mbx.h"
704 /* Function pointers for the MAC. */
705 struct e1000_mac_operations {
706 s32 (*init_params)(struct e1000_hw *);
707 s32 (*id_led_init)(struct e1000_hw *);
708 s32 (*blink_led)(struct e1000_hw *);
709 bool (*check_mng_mode)(struct e1000_hw *);
710 s32 (*check_for_link)(struct e1000_hw *);
711 s32 (*cleanup_led)(struct e1000_hw *);
712 void (*clear_hw_cntrs)(struct e1000_hw *);
713 void (*clear_vfta)(struct e1000_hw *);
714 s32 (*get_bus_info)(struct e1000_hw *);
715 void (*set_lan_id)(struct e1000_hw *);
716 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
717 s32 (*led_on)(struct e1000_hw *);
718 s32 (*led_off)(struct e1000_hw *);
719 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
720 s32 (*reset_hw)(struct e1000_hw *);
721 s32 (*init_hw)(struct e1000_hw *);
722 void (*shutdown_serdes)(struct e1000_hw *);
723 void (*power_up_serdes)(struct e1000_hw *);
724 s32 (*setup_link)(struct e1000_hw *);
725 s32 (*setup_physical_interface)(struct e1000_hw *);
726 s32 (*setup_led)(struct e1000_hw *);
727 void (*write_vfta)(struct e1000_hw *, u32, u32);
728 void (*config_collision_dist)(struct e1000_hw *);
729 int (*rar_set)(struct e1000_hw *, u8*, u32);
730 s32 (*read_mac_addr)(struct e1000_hw *);
731 s32 (*validate_mdi_setting)(struct e1000_hw *);
732 s32 (*set_obff_timer)(struct e1000_hw *, u32);
733 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);
734 void (*release_swfw_sync)(struct e1000_hw *, u16);
737 /* When to use various PHY register access functions:
740 * Function Does Does When to use
741 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
742 * X_reg L,P,A n/a for simple PHY reg accesses
743 * X_reg_locked P,A L for multiple accesses of different regs
745 * X_reg_page A L,P for multiple accesses of different regs
748 * Where X=[read|write], L=locking, P=sets page, A=register access
751 struct e1000_phy_operations {
752 s32 (*init_params)(struct e1000_hw *);
753 s32 (*acquire)(struct e1000_hw *);
754 s32 (*cfg_on_link_up)(struct e1000_hw *);
755 s32 (*check_polarity)(struct e1000_hw *);
756 s32 (*check_reset_block)(struct e1000_hw *);
757 s32 (*commit)(struct e1000_hw *);
758 s32 (*force_speed_duplex)(struct e1000_hw *);
759 s32 (*get_cfg_done)(struct e1000_hw *hw);
760 s32 (*get_cable_length)(struct e1000_hw *);
761 s32 (*get_info)(struct e1000_hw *);
762 s32 (*set_page)(struct e1000_hw *, u16);
763 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
764 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
765 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
766 void (*release)(struct e1000_hw *);
767 s32 (*reset)(struct e1000_hw *);
768 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
769 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
770 s32 (*write_reg)(struct e1000_hw *, u32, u16);
771 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
772 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
773 void (*power_up)(struct e1000_hw *);
774 void (*power_down)(struct e1000_hw *);
775 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
776 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
779 /* Function pointers for the NVM. */
780 struct e1000_nvm_operations {
781 s32 (*init_params)(struct e1000_hw *);
782 s32 (*acquire)(struct e1000_hw *);
783 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
784 void (*release)(struct e1000_hw *);
785 void (*reload)(struct e1000_hw *);
786 s32 (*update)(struct e1000_hw *);
787 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
788 s32 (*validate)(struct e1000_hw *);
789 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
792 struct e1000_mac_info {
793 struct e1000_mac_operations ops;
794 u8 addr[ETHER_ADDR_LEN];
795 u8 perm_addr[ETHER_ADDR_LEN];
797 enum e1000_mac_type type;
815 /* Maximum size of the MTA register table in all supported adapters */
816 #define MAX_MTA_REG 128
817 u32 mta_shadow[MAX_MTA_REG];
820 u8 forced_speed_duplex;
824 bool arc_subsystem_valid;
825 bool asf_firmware_present;
828 bool get_link_status;
830 bool report_tx_early;
831 enum e1000_serdes_link_state serdes_link_state;
832 bool serdes_has_link;
833 bool tx_pkt_filtering;
837 struct e1000_phy_info {
838 struct e1000_phy_operations ops;
839 enum e1000_phy_type type;
841 enum e1000_1000t_rx_status local_rx;
842 enum e1000_1000t_rx_status remote_rx;
843 enum e1000_ms_type ms_type;
844 enum e1000_ms_type original_ms_type;
845 enum e1000_rev_polarity cable_polarity;
846 enum e1000_smart_speed smart_speed;
850 u32 reset_delay_us; /* in usec */
853 enum e1000_media_type media_type;
855 u16 autoneg_advertised;
858 u16 max_cable_length;
859 u16 min_cable_length;
863 bool disable_polarity_correction;
865 bool polarity_correction;
866 bool speed_downgraded;
867 bool autoneg_wait_to_complete;
870 struct e1000_nvm_info {
871 struct e1000_nvm_operations ops;
872 enum e1000_nvm_type type;
873 enum e1000_nvm_override override;
885 struct e1000_bus_info {
886 enum e1000_bus_type type;
887 enum e1000_bus_speed speed;
888 enum e1000_bus_width width;
894 struct e1000_fc_info {
895 u32 high_water; /* Flow control high-water mark */
896 u32 low_water; /* Flow control low-water mark */
897 u16 pause_time; /* Flow control pause timer */
898 u16 refresh_time; /* Flow control refresh timer */
899 bool send_xon; /* Flow control send XON */
900 bool strict_ieee; /* Strict IEEE mode */
901 enum e1000_fc_mode current_mode; /* FC mode in effect */
902 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
905 struct e1000_mbx_operations {
906 s32 (*init_params)(struct e1000_hw *hw);
907 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
908 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
909 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
910 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
911 s32 (*check_for_msg)(struct e1000_hw *, u16);
912 s32 (*check_for_ack)(struct e1000_hw *, u16);
913 s32 (*check_for_rst)(struct e1000_hw *, u16);
916 struct e1000_mbx_stats {
925 struct e1000_mbx_info {
926 struct e1000_mbx_operations ops;
927 struct e1000_mbx_stats stats;
933 struct e1000_dev_spec_82541 {
934 enum e1000_dsp_config dsp_config;
935 enum e1000_ffe_config ffe_config;
937 bool phy_init_script;
940 struct e1000_dev_spec_82542 {
944 struct e1000_dev_spec_82543 {
945 u32 tbi_compatibility;
947 bool init_phy_disabled;
950 struct e1000_dev_spec_82571 {
955 struct e1000_dev_spec_80003es2lan {
959 struct e1000_shadow_ram {
964 #define E1000_SHADOW_RAM_WORDS 2048
966 /* I218 PHY Ultra Low Power (ULP) states */
967 enum e1000_ulp_state {
968 e1000_ulp_state_unknown,
973 struct e1000_dev_spec_ich8lan {
974 bool kmrn_lock_loss_workaround_enabled;
975 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
980 enum e1000_ulp_state ulp_state;
981 bool ulp_capability_disabled;
982 bool during_suspend_flow;
983 bool during_dpg_exit;
986 struct e1000_dev_spec_82575 {
988 bool global_device_reset;
991 bool clear_semaphore_once;
993 struct sfp_e1000_flags eth_flags;
998 struct e1000_dev_spec_vf {
1008 unsigned long io_base;
1010 struct e1000_mac_info mac;
1011 struct e1000_fc_info fc;
1012 struct e1000_phy_info phy;
1013 struct e1000_nvm_info nvm;
1014 struct e1000_bus_info bus;
1015 struct e1000_mbx_info mbx;
1016 struct e1000_host_mng_dhcp_cookie mng_cookie;
1019 struct e1000_dev_spec_82541 _82541;
1020 struct e1000_dev_spec_82542 _82542;
1021 struct e1000_dev_spec_82543 _82543;
1022 struct e1000_dev_spec_82571 _82571;
1023 struct e1000_dev_spec_80003es2lan _80003es2lan;
1024 struct e1000_dev_spec_ich8lan ich8lan;
1025 struct e1000_dev_spec_82575 _82575;
1026 struct e1000_dev_spec_vf vf;
1030 u16 subsystem_vendor_id;
1031 u16 subsystem_device_id;
1037 #include "e1000_82541.h"
1038 #include "e1000_82543.h"
1039 #include "e1000_82571.h"
1040 #include "e1000_80003es2lan.h"
1041 #include "e1000_ich8lan.h"
1042 #include "e1000_82575.h"
1043 #include "e1000_i210.h"
1045 /* These functions must be implemented by drivers */
1046 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1047 void e1000_pci_set_mwi(struct e1000_hw *hw);
1048 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1049 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1050 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1051 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);