sys/dev/e1000/e1000_hw.h

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2012, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #ifndef _E1000_HW_H_
  36 #define _E1000_HW_H_
  37
  38 #include "e1000_osdep.h"
  39 #include "e1000_regs.h"
  40 #include "e1000_defines.h"
  41
  42 struct e1000_hw;
  43
  44 #define E1000_DEV_ID_82542                      0x1000
  45 #define E1000_DEV_ID_82543GC_FIBER              0x1001
  46 #define E1000_DEV_ID_82543GC_COPPER             0x1004
  47 #define E1000_DEV_ID_82544EI_COPPER             0x1008
  48 #define E1000_DEV_ID_82544EI_FIBER              0x1009
  49 #define E1000_DEV_ID_82544GC_COPPER             0x100C
  50 #define E1000_DEV_ID_82544GC_LOM                0x100D
  51 #define E1000_DEV_ID_82540EM                    0x100E
  52 #define E1000_DEV_ID_82540EM_LOM                0x1015
  53 #define E1000_DEV_ID_82540EP_LOM                0x1016
  54 #define E1000_DEV_ID_82540EP                    0x1017
  55 #define E1000_DEV_ID_82540EP_LP                 0x101E
  56 #define E1000_DEV_ID_82545EM_COPPER             0x100F
  57 #define E1000_DEV_ID_82545EM_FIBER              0x1011
  58 #define E1000_DEV_ID_82545GM_COPPER             0x1026
  59 #define E1000_DEV_ID_82545GM_FIBER              0x1027
  60 #define E1000_DEV_ID_82545GM_SERDES             0x1028
  61 #define E1000_DEV_ID_82546EB_COPPER             0x1010
  62 #define E1000_DEV_ID_82546EB_FIBER              0x1012
  63 #define E1000_DEV_ID_82546EB_QUAD_COPPER        0x101D
  64 #define E1000_DEV_ID_82546GB_COPPER             0x1079
  65 #define E1000_DEV_ID_82546GB_FIBER              0x107A
  66 #define E1000_DEV_ID_82546GB_SERDES             0x107B
  67 #define E1000_DEV_ID_82546GB_PCIE               0x108A
  68 #define E1000_DEV_ID_82546GB_QUAD_COPPER        0x1099
  69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3   0x10B5
  70 #define E1000_DEV_ID_82541EI                    0x1013
  71 #define E1000_DEV_ID_82541EI_MOBILE             0x1018
  72 #define E1000_DEV_ID_82541ER_LOM                0x1014
  73 #define E1000_DEV_ID_82541ER                    0x1078
  74 #define E1000_DEV_ID_82541GI                    0x1076
  75 #define E1000_DEV_ID_82541GI_LF                 0x107C
  76 #define E1000_DEV_ID_82541GI_MOBILE             0x1077
  77 #define E1000_DEV_ID_82547EI                    0x1019
  78 #define E1000_DEV_ID_82547EI_MOBILE             0x101A
  79 #define E1000_DEV_ID_82547GI                    0x1075
  80 #define E1000_DEV_ID_82571EB_COPPER             0x105E
  81 #define E1000_DEV_ID_82571EB_FIBER              0x105F
  82 #define E1000_DEV_ID_82571EB_SERDES             0x1060
  83 #define E1000_DEV_ID_82571EB_SERDES_DUAL        0x10D9
  84 #define E1000_DEV_ID_82571EB_SERDES_QUAD        0x10DA
  85 #define E1000_DEV_ID_82571EB_QUAD_COPPER        0x10A4
  86 #define E1000_DEV_ID_82571PT_QUAD_COPPER        0x10D5
  87 #define E1000_DEV_ID_82571EB_QUAD_FIBER         0x10A5
  88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP     0x10BC
  89 #define E1000_DEV_ID_82572EI_COPPER             0x107D
  90 #define E1000_DEV_ID_82572EI_FIBER              0x107E
  91 #define E1000_DEV_ID_82572EI_SERDES             0x107F
  92 #define E1000_DEV_ID_82572EI                    0x10B9
  93 #define E1000_DEV_ID_82573E                     0x108B
  94 #define E1000_DEV_ID_82573E_IAMT                0x108C
  95 #define E1000_DEV_ID_82573L                     0x109A
  96 #define E1000_DEV_ID_82574L                     0x10D3
  97 #define E1000_DEV_ID_82574LA                    0x10F6
  98 #define E1000_DEV_ID_82583V                     0x150C
  99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096
 100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098
 101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA
 102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB
 103 #define E1000_DEV_ID_ICH8_82567V_3              0x1501
 104 #define E1000_DEV_ID_ICH8_IGP_M_AMT             0x1049
 105 #define E1000_DEV_ID_ICH8_IGP_AMT               0x104A
 106 #define E1000_DEV_ID_ICH8_IGP_C                 0x104B
 107 #define E1000_DEV_ID_ICH8_IFE                   0x104C
 108 #define E1000_DEV_ID_ICH8_IFE_GT                0x10C4
 109 #define E1000_DEV_ID_ICH8_IFE_G                 0x10C5
 110 #define E1000_DEV_ID_ICH8_IGP_M                 0x104D
 111 #define E1000_DEV_ID_ICH9_IGP_M                 0x10BF
 112 #define E1000_DEV_ID_ICH9_IGP_M_AMT             0x10F5
 113 #define E1000_DEV_ID_ICH9_IGP_M_V               0x10CB
 114 #define E1000_DEV_ID_ICH9_IGP_AMT               0x10BD
 115 #define E1000_DEV_ID_ICH9_BM                    0x10E5
 116 #define E1000_DEV_ID_ICH9_IGP_C                 0x294C
 117 #define E1000_DEV_ID_ICH9_IFE                   0x10C0
 118 #define E1000_DEV_ID_ICH9_IFE_GT                0x10C3
 119 #define E1000_DEV_ID_ICH9_IFE_G                 0x10C2
 120 #define E1000_DEV_ID_ICH10_R_BM_LM              0x10CC
 121 #define E1000_DEV_ID_ICH10_R_BM_LF              0x10CD
 122 #define E1000_DEV_ID_ICH10_R_BM_V               0x10CE
 123 #define E1000_DEV_ID_ICH10_D_BM_LM              0x10DE
 124 #define E1000_DEV_ID_ICH10_D_BM_LF              0x10DF
 125 #define E1000_DEV_ID_ICH10_D_BM_V               0x1525
 126
 127 #define E1000_DEV_ID_PCH_M_HV_LM                0x10EA
 128 #define E1000_DEV_ID_PCH_M_HV_LC                0x10EB
 129 #define E1000_DEV_ID_PCH_D_HV_DM                0x10EF
 130 #define E1000_DEV_ID_PCH_D_HV_DC                0x10F0
 131 #define E1000_DEV_ID_PCH2_LV_LM                 0x1502
 132 #define E1000_DEV_ID_PCH2_LV_V                  0x1503
 133 #define E1000_DEV_ID_82576                      0x10C9
 134 #define E1000_DEV_ID_82576_FIBER                0x10E6
 135 #define E1000_DEV_ID_82576_SERDES               0x10E7
 136 #define E1000_DEV_ID_82576_QUAD_COPPER          0x10E8
 137 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2      0x1526
 138 #define E1000_DEV_ID_82576_NS                   0x150A
 139 #define E1000_DEV_ID_82576_NS_SERDES            0x1518
 140 #define E1000_DEV_ID_82576_SERDES_QUAD          0x150D
 141 #define E1000_DEV_ID_82576_VF                   0x10CA
 142 #define E1000_DEV_ID_I350_VF                    0x1520
 143 #define E1000_DEV_ID_82575EB_COPPER             0x10A7
 144 #define E1000_DEV_ID_82575EB_FIBER_SERDES       0x10A9
 145 #define E1000_DEV_ID_82575GB_QUAD_COPPER        0x10D6
 146 #define E1000_DEV_ID_82580_COPPER               0x150E
 147 #define E1000_DEV_ID_82580_FIBER                0x150F
 148 #define E1000_DEV_ID_82580_SERDES               0x1510
 149 #define E1000_DEV_ID_82580_SGMII                0x1511
 150 #define E1000_DEV_ID_82580_COPPER_DUAL          0x1516
 151 #define E1000_DEV_ID_82580_QUAD_FIBER           0x1527
 152 #define E1000_DEV_ID_I350_COPPER                0x1521
 153 #define E1000_DEV_ID_I350_FIBER                 0x1522
 154 #define E1000_DEV_ID_I350_SERDES                0x1523
 155 #define E1000_DEV_ID_I350_SGMII                 0x1524
 156 #define E1000_DEV_ID_I350_DA4                   0x1546
 157 #define E1000_DEV_ID_I210_COPPER                0x1533
 158 #define E1000_DEV_ID_I210_COPPER_OEM1           0x1534
 159 #define E1000_DEV_ID_I210_COPPER_IT             0x1535
 160 #define E1000_DEV_ID_I210_FIBER                 0x1536
 161 #define E1000_DEV_ID_I210_SERDES                0x1537
 162 #define E1000_DEV_ID_I210_SGMII                 0x1538
 163 #define E1000_DEV_ID_I211_COPPER                0x1539
 164 #define E1000_DEV_ID_DH89XXCC_SGMII             0x0438
 165 #define E1000_DEV_ID_DH89XXCC_SERDES            0x043A
 166 #define E1000_DEV_ID_DH89XXCC_BACKPLANE         0x043C
 167 #define E1000_DEV_ID_DH89XXCC_SFP               0x0440
 168 #define E1000_REVISION_0        0
 169 #define E1000_REVISION_1        1
 170 #define E1000_REVISION_2        2
 171 #define E1000_REVISION_3        3
 172 #define E1000_REVISION_4        4
 173
 174 #define E1000_FUNC_0            0
 175 #define E1000_FUNC_1            1
 176 #define E1000_FUNC_2            2
 177 #define E1000_FUNC_3            3
 178
 179 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0       0
 180 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1       3
 181 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2       6
 182 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3       9
 183
 184 enum e1000_mac_type {
 185         e1000_undefined = 0,
 186         e1000_82542,
 187         e1000_82543,
 188         e1000_82544,
 189         e1000_82540,
 190         e1000_82545,
 191         e1000_82545_rev_3,
 192         e1000_82546,
 193         e1000_82546_rev_3,
 194         e1000_82541,
 195         e1000_82541_rev_2,
 196         e1000_82547,
 197         e1000_82547_rev_2,
 198         e1000_82571,
 199         e1000_82572,
 200         e1000_82573,
 201         e1000_82574,
 202         e1000_82583,
 203         e1000_80003es2lan,
 204         e1000_ich8lan,
 205         e1000_ich9lan,
 206         e1000_ich10lan,
 207         e1000_pchlan,
 208         e1000_pch2lan,
 209         e1000_82575,
 210         e1000_82576,
 211         e1000_82580,
 212         e1000_i350,
 213         e1000_i210,
 214         e1000_i211,
 215         e1000_vfadapt,
 216         e1000_vfadapt_i350,
 217         e1000_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
 218 };
 219
 220 enum e1000_media_type {
 221         e1000_media_type_unknown = 0,
 222         e1000_media_type_copper = 1,
 223         e1000_media_type_fiber = 2,
 224         e1000_media_type_internal_serdes = 3,
 225         e1000_num_media_types
 226 };
 227
 228 enum e1000_nvm_type {
 229         e1000_nvm_unknown = 0,
 230         e1000_nvm_none,
 231         e1000_nvm_eeprom_spi,
 232         e1000_nvm_eeprom_microwire,
 233         e1000_nvm_flash_hw,
 234         e1000_nvm_flash_sw
 235 };
 236
 237 enum e1000_nvm_override {
 238         e1000_nvm_override_none = 0,
 239         e1000_nvm_override_spi_small,
 240         e1000_nvm_override_spi_large,
 241         e1000_nvm_override_microwire_small,
 242         e1000_nvm_override_microwire_large
 243 };
 244
 245 enum e1000_phy_type {
 246         e1000_phy_unknown = 0,
 247         e1000_phy_none,
 248         e1000_phy_m88,
 249         e1000_phy_igp,
 250         e1000_phy_igp_2,
 251         e1000_phy_gg82563,
 252         e1000_phy_igp_3,
 253         e1000_phy_ife,
 254         e1000_phy_bm,
 255         e1000_phy_82578,
 256         e1000_phy_82577,
 257         e1000_phy_82579,
 258         e1000_phy_82580,
 259         e1000_phy_vf,
 260         e1000_phy_i210,
 261 };
 262
 263 enum e1000_bus_type {
 264         e1000_bus_type_unknown = 0,
 265         e1000_bus_type_pci,
 266         e1000_bus_type_pcix,
 267         e1000_bus_type_pci_express,
 268         e1000_bus_type_reserved
 269 };
 270
 271 enum e1000_bus_speed {
 272         e1000_bus_speed_unknown = 0,
 273         e1000_bus_speed_33,
 274         e1000_bus_speed_66,
 275         e1000_bus_speed_100,
 276         e1000_bus_speed_120,
 277         e1000_bus_speed_133,
 278         e1000_bus_speed_2500,
 279         e1000_bus_speed_5000,
 280         e1000_bus_speed_reserved
 281 };
 282
 283 enum e1000_bus_width {
 284         e1000_bus_width_unknown = 0,
 285         e1000_bus_width_pcie_x1,
 286         e1000_bus_width_pcie_x2,
 287         e1000_bus_width_pcie_x4 = 4,
 288         e1000_bus_width_pcie_x8 = 8,
 289         e1000_bus_width_32,
 290         e1000_bus_width_64,
 291         e1000_bus_width_reserved
 292 };
 293
 294 enum e1000_1000t_rx_status {
 295         e1000_1000t_rx_status_not_ok = 0,
 296         e1000_1000t_rx_status_ok,
 297         e1000_1000t_rx_status_undefined = 0xFF
 298 };
 299
 300 enum e1000_rev_polarity {
 301         e1000_rev_polarity_normal = 0,
 302         e1000_rev_polarity_reversed,
 303         e1000_rev_polarity_undefined = 0xFF
 304 };
 305
 306 enum e1000_fc_mode {
 307         e1000_fc_none = 0,
 308         e1000_fc_rx_pause,
 309         e1000_fc_tx_pause,
 310         e1000_fc_full,
 311         e1000_fc_default = 0xFF
 312 };
 313
 314 enum e1000_ffe_config {
 315         e1000_ffe_config_enabled = 0,
 316         e1000_ffe_config_active,
 317         e1000_ffe_config_blocked
 318 };
 319
 320 enum e1000_dsp_config {
 321         e1000_dsp_config_disabled = 0,
 322         e1000_dsp_config_enabled,
 323         e1000_dsp_config_activated,
 324         e1000_dsp_config_undefined = 0xFF
 325 };
 326
 327 enum e1000_ms_type {
 328         e1000_ms_hw_default = 0,
 329         e1000_ms_force_master,
 330         e1000_ms_force_slave,
 331         e1000_ms_auto
 332 };
 333
 334 enum e1000_smart_speed {
 335         e1000_smart_speed_default = 0,
 336         e1000_smart_speed_on,
 337         e1000_smart_speed_off
 338 };
 339
 340 enum e1000_serdes_link_state {
 341         e1000_serdes_link_down = 0,
 342         e1000_serdes_link_autoneg_progress,
 343         e1000_serdes_link_autoneg_complete,
 344         e1000_serdes_link_forced_up
 345 };
 346
 347 #define __le16 u16
 348 #define __le32 u32
 349 #define __le64 u64
 350 /* Receive Descriptor */
 351 struct e1000_rx_desc {
 352         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 353         __le16 length;      /* Length of data DMAed into data buffer */
 354         __le16 csum; /* Packet checksum */
 355         u8  status;  /* Descriptor status */
 356         u8  errors;  /* Descriptor Errors */
 357         __le16 special;
 358 };
 359
 360 /* Receive Descriptor - Extended */
 361 union e1000_rx_desc_extended {
 362         struct {
 363                 __le64 buffer_addr;
 364                 __le64 reserved;
 365         } read;
 366         struct {
 367                 struct {
 368                         __le32 mrq; /* Multiple Rx Queues */
 369                         union {
 370                                 __le32 rss; /* RSS Hash */
 371                                 struct {
 372                                         __le16 ip_id;  /* IP id */
 373                                         __le16 csum;   /* Packet Checksum */
 374                                 } csum_ip;
 375                         } hi_dword;
 376                 } lower;
 377                 struct {
 378                         __le32 status_error;  /* ext status/error */
 379                         __le16 length;
 380                         __le16 vlan; /* VLAN tag */
 381                 } upper;
 382         } wb;  /* writeback */
 383 };
 384
 385 #define MAX_PS_BUFFERS 4
 386 /* Receive Descriptor - Packet Split */
 387 union e1000_rx_desc_packet_split {
 388         struct {
 389                 /* one buffer for protocol header(s), three data buffers */
 390                 __le64 buffer_addr[MAX_PS_BUFFERS];
 391         } read;
 392         struct {
 393                 struct {
 394                         __le32 mrq;  /* Multiple Rx Queues */
 395                         union {
 396                                 __le32 rss; /* RSS Hash */
 397                                 struct {
 398                                         __le16 ip_id;    /* IP id */
 399                                         __le16 csum;     /* Packet Checksum */
 400                                 } csum_ip;
 401                         } hi_dword;
 402                 } lower;
 403                 struct {
 404                         __le32 status_error;  /* ext status/error */
 405                         __le16 length0;  /* length of buffer 0 */
 406                         __le16 vlan;  /* VLAN tag */
 407                 } middle;
 408                 struct {
 409                         __le16 header_status;
 410                         __le16 length[3];     /* length of buffers 1-3 */
 411                 } upper;
 412                 __le64 reserved;
 413         } wb; /* writeback */
 414 };
 415
 416 /* Transmit Descriptor */
 417 struct e1000_tx_desc {
 418         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 419         union {
 420                 __le32 data;
 421                 struct {
 422                         __le16 length;  /* Data buffer length */
 423                         u8 cso;  /* Checksum offset */
 424                         u8 cmd;  /* Descriptor control */
 425                 } flags;
 426         } lower;
 427         union {
 428                 __le32 data;
 429                 struct {
 430                         u8 status; /* Descriptor status */
 431                         u8 css;  /* Checksum start */
 432                         __le16 special;
 433                 } fields;
 434         } upper;
 435 };
 436
 437 /* Offload Context Descriptor */
 438 struct e1000_context_desc {
 439         union {
 440                 __le32 ip_config;
 441                 struct {
 442                         u8 ipcss;  /* IP checksum start */
 443                         u8 ipcso;  /* IP checksum offset */
 444                         __le16 ipcse;  /* IP checksum end */
 445                 } ip_fields;
 446         } lower_setup;
 447         union {
 448                 __le32 tcp_config;
 449                 struct {
 450                         u8 tucss;  /* TCP checksum start */
 451                         u8 tucso;  /* TCP checksum offset */
 452                         __le16 tucse;  /* TCP checksum end */
 453                 } tcp_fields;
 454         } upper_setup;
 455         __le32 cmd_and_length;
 456         union {
 457                 __le32 data;
 458                 struct {
 459                         u8 status;  /* Descriptor status */
 460                         u8 hdr_len;  /* Header length */
 461                         __le16 mss;  /* Maximum segment size */
 462                 } fields;
 463         } tcp_seg_setup;
 464 };
 465
 466 /* Offload data descriptor */
 467 struct e1000_data_desc {
 468         __le64 buffer_addr;  /* Address of the descriptor's buffer address */
 469         union {
 470                 __le32 data;
 471                 struct {
 472                         __le16 length;  /* Data buffer length */
 473                         u8 typ_len_ext;
 474                         u8 cmd;
 475                 } flags;
 476         } lower;
 477         union {
 478                 __le32 data;
 479                 struct {
 480                         u8 status;  /* Descriptor status */
 481                         u8 popts;  /* Packet Options */
 482                         __le16 special;
 483                 } fields;
 484         } upper;
 485 };
 486
 487 /* Statistics counters collected by the MAC */
 488 struct e1000_hw_stats {
 489         u64 crcerrs;
 490         u64 algnerrc;
 491         u64 symerrs;
 492         u64 rxerrc;
 493         u64 mpc;
 494         u64 scc;
 495         u64 ecol;
 496         u64 mcc;
 497         u64 latecol;
 498         u64 colc;
 499         u64 dc;
 500         u64 tncrs;
 501         u64 sec;
 502         u64 cexterr;
 503         u64 rlec;
 504         u64 xonrxc;
 505         u64 xontxc;
 506         u64 xoffrxc;
 507         u64 xofftxc;
 508         u64 fcruc;
 509         u64 prc64;
 510         u64 prc127;
 511         u64 prc255;
 512         u64 prc511;
 513         u64 prc1023;
 514         u64 prc1522;
 515         u64 gprc;
 516         u64 bprc;
 517         u64 mprc;
 518         u64 gptc;
 519         u64 gorc;
 520         u64 gotc;
 521         u64 rnbc;
 522         u64 ruc;
 523         u64 rfc;
 524         u64 roc;
 525         u64 rjc;
 526         u64 mgprc;
 527         u64 mgpdc;
 528         u64 mgptc;
 529         u64 tor;
 530         u64 tot;
 531         u64 tpr;
 532         u64 tpt;
 533         u64 ptc64;
 534         u64 ptc127;
 535         u64 ptc255;
 536         u64 ptc511;
 537         u64 ptc1023;
 538         u64 ptc1522;
 539         u64 mptc;
 540         u64 bptc;
 541         u64 tsctc;
 542         u64 tsctfc;
 543         u64 iac;
 544         u64 icrxptc;
 545         u64 icrxatc;
 546         u64 ictxptc;
 547         u64 ictxatc;
 548         u64 ictxqec;
 549         u64 ictxqmtc;
 550         u64 icrxdmtc;
 551         u64 icrxoc;
 552         u64 cbtmpc;
 553         u64 htdpmc;
 554         u64 cbrdpc;
 555         u64 cbrmpc;
 556         u64 rpthc;
 557         u64 hgptc;
 558         u64 htcbdpc;
 559         u64 hgorc;
 560         u64 hgotc;
 561         u64 lenerrs;
 562         u64 scvpc;
 563         u64 hrmpc;
 564         u64 doosync;
 565         u64 o2bgptc;
 566         u64 o2bspc;
 567         u64 b2ospc;
 568         u64 b2ogprc;
 569 };
 570
 571 struct e1000_vf_stats {
 572         u64 base_gprc;
 573         u64 base_gptc;
 574         u64 base_gorc;
 575         u64 base_gotc;
 576         u64 base_mprc;
 577         u64 base_gotlbc;
 578         u64 base_gptlbc;
 579         u64 base_gorlbc;
 580         u64 base_gprlbc;
 581
 582         u32 last_gprc;
 583         u32 last_gptc;
 584         u32 last_gorc;
 585         u32 last_gotc;
 586         u32 last_mprc;
 587         u32 last_gotlbc;
 588         u32 last_gptlbc;
 589         u32 last_gorlbc;
 590         u32 last_gprlbc;
 591
 592         u64 gprc;
 593         u64 gptc;
 594         u64 gorc;
 595         u64 gotc;
 596         u64 mprc;
 597         u64 gotlbc;
 598         u64 gptlbc;
 599         u64 gorlbc;
 600         u64 gprlbc;
 601 };
 602
 603 struct e1000_phy_stats {
 604         u32 idle_errors;
 605         u32 receive_errors;
 606 };
 607
 608 struct e1000_host_mng_dhcp_cookie {
 609         u32 signature;
 610         u8  status;
 611         u8  reserved0;
 612         u16 vlan_id;
 613         u32 reserved1;
 614         u16 reserved2;
 615         u8  reserved3;
 616         u8  checksum;
 617 };
 618
 619 /* Host Interface "Rev 1" */
 620 struct e1000_host_command_header {
 621         u8 command_id;
 622         u8 command_length;
 623         u8 command_options;
 624         u8 checksum;
 625 };
 626
 627 #define E1000_HI_MAX_DATA_LENGTH        252
 628 struct e1000_host_command_info {
 629         struct e1000_host_command_header command_header;
 630         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 631 };
 632
 633 /* Host Interface "Rev 2" */
 634 struct e1000_host_mng_command_header {
 635         u8  command_id;
 636         u8  checksum;
 637         u16 reserved1;
 638         u16 reserved2;
 639         u16 command_length;
 640 };
 641
 642 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
 643 struct e1000_host_mng_command_info {
 644         struct e1000_host_mng_command_header command_header;
 645         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 646 };
 647
 648 #include "e1000_mac.h"
 649 #include "e1000_phy.h"
 650 #include "e1000_nvm.h"
 651 #include "e1000_manage.h"
 652 #include "e1000_mbx.h"
 653
 654 struct e1000_mac_operations {
 655         /* Function pointers for the MAC. */
 656         s32  (*init_params)(struct e1000_hw *);
 657         s32  (*id_led_init)(struct e1000_hw *);
 658         s32  (*blink_led)(struct e1000_hw *);
 659         s32  (*check_for_link)(struct e1000_hw *);
 660         bool (*check_mng_mode)(struct e1000_hw *hw);
 661         s32  (*cleanup_led)(struct e1000_hw *);
 662         void (*clear_hw_cntrs)(struct e1000_hw *);
 663         void (*clear_vfta)(struct e1000_hw *);
 664         s32  (*get_bus_info)(struct e1000_hw *);
 665         void (*set_lan_id)(struct e1000_hw *);
 666         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 667         s32  (*led_on)(struct e1000_hw *);
 668         s32  (*led_off)(struct e1000_hw *);
 669         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 670         s32  (*reset_hw)(struct e1000_hw *);
 671         s32  (*init_hw)(struct e1000_hw *);
 672         void (*shutdown_serdes)(struct e1000_hw *);
 673         void (*power_up_serdes)(struct e1000_hw *);
 674         s32  (*setup_link)(struct e1000_hw *);
 675         s32  (*setup_physical_interface)(struct e1000_hw *);
 676         s32  (*setup_led)(struct e1000_hw *);
 677         void (*write_vfta)(struct e1000_hw *, u32, u32);
 678         void (*config_collision_dist)(struct e1000_hw *);
 679         void (*rar_set)(struct e1000_hw *, u8*, u32);
 680         s32  (*read_mac_addr)(struct e1000_hw *);
 681         s32  (*validate_mdi_setting)(struct e1000_hw *);
 682         s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
 683         s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
 684                                      struct e1000_host_mng_command_header*);
 685         s32  (*mng_enable_host_if)(struct e1000_hw *);
 686         s32  (*wait_autoneg)(struct e1000_hw *);
 687         s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
 688         void (*release_swfw_sync)(struct e1000_hw *, u16);
 689 };
 690
 691 /*
 692  * When to use various PHY register access functions:
 693  *
 694  *                 Func   Caller
 695  *   Function      Does   Does    When to use
 696  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 697  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 698  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 699  *                                on different pages
 700  *   X_reg_page    A      L,P     for multiple accesses of different regs
 701  *                                on the same page
 702  *
 703  * Where X=[read|write], L=locking, P=sets page, A=register access
 704  *
 705  */
 706 struct e1000_phy_operations {
 707         s32  (*init_params)(struct e1000_hw *);
 708         s32  (*acquire)(struct e1000_hw *);
 709         s32  (*cfg_on_link_up)(struct e1000_hw *);
 710         s32  (*check_polarity)(struct e1000_hw *);
 711         s32  (*check_reset_block)(struct e1000_hw *);
 712         s32  (*commit)(struct e1000_hw *);
 713         s32  (*force_speed_duplex)(struct e1000_hw *);
 714         s32  (*get_cfg_done)(struct e1000_hw *hw);
 715         s32  (*get_cable_length)(struct e1000_hw *);
 716         s32  (*get_info)(struct e1000_hw *);
 717         s32  (*set_page)(struct e1000_hw *, u16);
 718         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 719         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 720         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 721         void (*release)(struct e1000_hw *);
 722         s32  (*reset)(struct e1000_hw *);
 723         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 724         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 725         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 726         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 727         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 728         void (*power_up)(struct e1000_hw *);
 729         void (*power_down)(struct e1000_hw *);
 730         s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
 731         s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
 732 };
 733
 734 struct e1000_nvm_operations {
 735         s32  (*init_params)(struct e1000_hw *);
 736         s32  (*acquire)(struct e1000_hw *);
 737         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 738         void (*release)(struct e1000_hw *);
 739         void (*reload)(struct e1000_hw *);
 740         s32  (*update)(struct e1000_hw *);
 741         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 742         s32  (*validate)(struct e1000_hw *);
 743         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 744 };
 745
 746 struct e1000_mac_info {
 747         struct e1000_mac_operations ops;
 748         u8 addr[ETH_ADDR_LEN];
 749         u8 perm_addr[ETH_ADDR_LEN];
 750
 751         enum e1000_mac_type type;
 752
 753         u32 collision_delta;
 754         u32 ledctl_default;
 755         u32 ledctl_mode1;
 756         u32 ledctl_mode2;
 757         u32 mc_filter_type;
 758         u32 tx_packet_delta;
 759         u32 txcw;
 760
 761         u16 current_ifs_val;
 762         u16 ifs_max_val;
 763         u16 ifs_min_val;
 764         u16 ifs_ratio;
 765         u16 ifs_step_size;
 766         u16 mta_reg_count;
 767         u16 uta_reg_count;
 768
 769         /* Maximum size of the MTA register table in all supported adapters */
 770         #define MAX_MTA_REG 128
 771         u32 mta_shadow[MAX_MTA_REG];
 772         u16 rar_entry_count;
 773
 774         u8  forced_speed_duplex;
 775
 776         bool adaptive_ifs;
 777         bool has_fwsm;
 778         bool arc_subsystem_valid;
 779         bool asf_firmware_present;
 780         bool autoneg;
 781         bool autoneg_failed;
 782         bool get_link_status;
 783         bool in_ifs_mode;
 784         bool report_tx_early;
 785         enum e1000_serdes_link_state serdes_link_state;
 786         bool serdes_has_link;
 787         bool tx_pkt_filtering;
 788 };
 789
 790 struct e1000_phy_info {
 791         struct e1000_phy_operations ops;
 792         enum e1000_phy_type type;
 793
 794         enum e1000_1000t_rx_status local_rx;
 795         enum e1000_1000t_rx_status remote_rx;
 796         enum e1000_ms_type ms_type;
 797         enum e1000_ms_type original_ms_type;
 798         enum e1000_rev_polarity cable_polarity;
 799         enum e1000_smart_speed smart_speed;
 800
 801         u32 addr;
 802         u32 id;
 803         u32 reset_delay_us; /* in usec */
 804         u32 revision;
 805
 806         enum e1000_media_type media_type;
 807
 808         u16 autoneg_advertised;
 809         u16 autoneg_mask;
 810         u16 cable_length;
 811         u16 max_cable_length;
 812         u16 min_cable_length;
 813
 814         u8 mdix;
 815
 816         bool disable_polarity_correction;
 817         bool is_mdix;
 818         bool polarity_correction;
 819         bool speed_downgraded;
 820         bool autoneg_wait_to_complete;
 821 };
 822
 823 struct e1000_nvm_info {
 824         struct e1000_nvm_operations ops;
 825         enum e1000_nvm_type type;
 826         enum e1000_nvm_override override;
 827
 828         u32 flash_bank_size;
 829         u32 flash_base_addr;
 830
 831         u16 word_size;
 832         u16 delay_usec;
 833         u16 address_bits;
 834         u16 opcode_bits;
 835         u16 page_size;
 836 };
 837
 838 struct e1000_bus_info {
 839         enum e1000_bus_type type;
 840         enum e1000_bus_speed speed;
 841         enum e1000_bus_width width;
 842
 843         u16 func;
 844         u16 pci_cmd_word;
 845 };
 846
 847 struct e1000_fc_info {
 848         u32 high_water;  /* Flow control high-water mark */
 849         u32 low_water;  /* Flow control low-water mark */
 850         u16 pause_time;  /* Flow control pause timer */
 851         u16 refresh_time;  /* Flow control refresh timer */
 852         bool send_xon;  /* Flow control send XON */
 853         bool strict_ieee;  /* Strict IEEE mode */
 854         enum e1000_fc_mode current_mode;  /* FC mode in effect */
 855         enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
 856 };
 857
 858 struct e1000_mbx_operations {
 859         s32 (*init_params)(struct e1000_hw *hw);
 860         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 861         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 862         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 863         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 864         s32 (*check_for_msg)(struct e1000_hw *, u16);
 865         s32 (*check_for_ack)(struct e1000_hw *, u16);
 866         s32 (*check_for_rst)(struct e1000_hw *, u16);
 867 };
 868
 869 struct e1000_mbx_stats {
 870         u32 msgs_tx;
 871         u32 msgs_rx;
 872
 873         u32 acks;
 874         u32 reqs;
 875         u32 rsts;
 876 };
 877
 878 struct e1000_mbx_info {
 879         struct e1000_mbx_operations ops;
 880         struct e1000_mbx_stats stats;
 881         u32 timeout;
 882         u32 usec_delay;
 883         u16 size;
 884 };
 885
 886 struct e1000_dev_spec_82541 {
 887         enum e1000_dsp_config dsp_config;
 888         enum e1000_ffe_config ffe_config;
 889         u16 spd_default;
 890         bool phy_init_script;
 891 };
 892
 893 struct e1000_dev_spec_82542 {
 894         bool dma_fairness;
 895 };
 896
 897 struct e1000_dev_spec_82543 {
 898         u32  tbi_compatibility;
 899         bool dma_fairness;
 900         bool init_phy_disabled;
 901 };
 902
 903 struct e1000_dev_spec_82571 {
 904         bool laa_is_present;
 905         u32 smb_counter;
 906         E1000_MUTEX swflag_mutex;
 907 };
 908
 909 struct e1000_dev_spec_80003es2lan {
 910         bool  mdic_wa_enable;
 911 };
 912
 913 struct e1000_shadow_ram {
 914         u16  value;
 915         bool modified;
 916 };
 917
 918 #define E1000_SHADOW_RAM_WORDS  2048
 919
 920 struct e1000_dev_spec_ich8lan {
 921         bool kmrn_lock_loss_workaround_enabled;
 922         struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
 923         E1000_MUTEX nvm_mutex;
 924         E1000_MUTEX swflag_mutex;
 925         bool nvm_k1_enabled;
 926         bool eee_disable;
 927 };
 928
 929 struct e1000_dev_spec_82575 {
 930         bool sgmii_active;
 931         bool global_device_reset;
 932         bool eee_disable;
 933         bool module_plugged;
 934         u32 mtu;
 935 };
 936
 937 struct e1000_dev_spec_vf {
 938         u32 vf_number;
 939         u32 v2p_mailbox;
 940 };
 941
 942 struct e1000_hw {
 943         void *back;
 944
 945         u8 *hw_addr;
 946         u8 *flash_address;
 947         unsigned long io_base;
 948
 949         struct e1000_mac_info  mac;
 950         struct e1000_fc_info   fc;
 951         struct e1000_phy_info  phy;
 952         struct e1000_nvm_info  nvm;
 953         struct e1000_bus_info  bus;
 954         struct e1000_mbx_info mbx;
 955         struct e1000_host_mng_dhcp_cookie mng_cookie;
 956
 957         union {
 958                 struct e1000_dev_spec_82541 _82541;
 959                 struct e1000_dev_spec_82542 _82542;
 960                 struct e1000_dev_spec_82543 _82543;
 961                 struct e1000_dev_spec_82571 _82571;
 962                 struct e1000_dev_spec_80003es2lan _80003es2lan;
 963                 struct e1000_dev_spec_ich8lan ich8lan;
 964                 struct e1000_dev_spec_82575 _82575;
 965                 struct e1000_dev_spec_vf vf;
 966         } dev_spec;
 967
 968         u16 device_id;
 969         u16 subsystem_vendor_id;
 970         u16 subsystem_device_id;
 971         u16 vendor_id;
 972
 973         u8  revision_id;
 974 };
 975
 976 #include "e1000_82541.h"
 977 #include "e1000_82543.h"
 978 #include "e1000_82571.h"
 979 #include "e1000_80003es2lan.h"
 980 #include "e1000_ich8lan.h"
 981 #include "e1000_82575.h"
 982 #include "e1000_i210.h"
 983
 984 /* These functions must be implemented by drivers */
 985 void e1000_pci_clear_mwi(struct e1000_hw *hw);
 986 void e1000_pci_set_mwi(struct e1000_hw *hw);
 987 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 988 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 989 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 990 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 991
 992 #endif