sys/dev/e1000/e1000_hw.h

   1 /******************************************************************************
   2   SPDX-License-Identifier: BSD-3-Clause
   3
   4   Copyright (c) 2001-2015, Intel Corporation
   5   All rights reserved.
   6
   7   Redistribution and use in source and binary forms, with or without
   8   modification, are permitted provided that the following conditions are met:
   9
  10    1. Redistributions of source code must retain the above copyright notice,
  11       this list of conditions and the following disclaimer.
  12
  13    2. Redistributions in binary form must reproduce the above copyright
  14       notice, this list of conditions and the following disclaimer in the
  15       documentation and/or other materials provided with the distribution.
  16
  17    3. Neither the name of the Intel Corporation nor the names of its
  18       contributors may be used to endorse or promote products derived from
  19       this software without specific prior written permission.
  20
  21   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31   POSSIBILITY OF SUCH DAMAGE.
  32
  33 ******************************************************************************/
  34 /*$FreeBSD$*/
  35
  36 #ifndef _E1000_HW_H_
  37 #define _E1000_HW_H_
  38
  39 #include "e1000_osdep.h"
  40 #include "e1000_regs.h"
  41 #include "e1000_defines.h"
  42
  43 struct e1000_hw;
  44
  45 #define E1000_DEV_ID_82542                      0x1000
  46 #define E1000_DEV_ID_82543GC_FIBER              0x1001
  47 #define E1000_DEV_ID_82543GC_COPPER             0x1004
  48 #define E1000_DEV_ID_82544EI_COPPER             0x1008
  49 #define E1000_DEV_ID_82544EI_FIBER              0x1009
  50 #define E1000_DEV_ID_82544GC_COPPER             0x100C
  51 #define E1000_DEV_ID_82544GC_LOM                0x100D
  52 #define E1000_DEV_ID_82540EM                    0x100E
  53 #define E1000_DEV_ID_82540EM_LOM                0x1015
  54 #define E1000_DEV_ID_82540EP_LOM                0x1016
  55 #define E1000_DEV_ID_82540EP                    0x1017
  56 #define E1000_DEV_ID_82540EP_LP                 0x101E
  57 #define E1000_DEV_ID_82545EM_COPPER             0x100F
  58 #define E1000_DEV_ID_82545EM_FIBER              0x1011
  59 #define E1000_DEV_ID_82545GM_COPPER             0x1026
  60 #define E1000_DEV_ID_82545GM_FIBER              0x1027
  61 #define E1000_DEV_ID_82545GM_SERDES             0x1028
  62 #define E1000_DEV_ID_82546EB_COPPER             0x1010
  63 #define E1000_DEV_ID_82546EB_FIBER              0x1012
  64 #define E1000_DEV_ID_82546EB_QUAD_COPPER        0x101D
  65 #define E1000_DEV_ID_82546GB_COPPER             0x1079
  66 #define E1000_DEV_ID_82546GB_FIBER              0x107A
  67 #define E1000_DEV_ID_82546GB_SERDES             0x107B
  68 #define E1000_DEV_ID_82546GB_PCIE               0x108A
  69 #define E1000_DEV_ID_82546GB_QUAD_COPPER        0x1099
  70 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3   0x10B5
  71 #define E1000_DEV_ID_82541EI                    0x1013
  72 #define E1000_DEV_ID_82541EI_MOBILE             0x1018
  73 #define E1000_DEV_ID_82541ER_LOM                0x1014
  74 #define E1000_DEV_ID_82541ER                    0x1078
  75 #define E1000_DEV_ID_82541GI                    0x1076
  76 #define E1000_DEV_ID_82541GI_LF                 0x107C
  77 #define E1000_DEV_ID_82541GI_MOBILE             0x1077
  78 #define E1000_DEV_ID_82547EI                    0x1019
  79 #define E1000_DEV_ID_82547EI_MOBILE             0x101A
  80 #define E1000_DEV_ID_82547GI                    0x1075
  81 #define E1000_DEV_ID_82571EB_COPPER             0x105E
  82 #define E1000_DEV_ID_82571EB_FIBER              0x105F
  83 #define E1000_DEV_ID_82571EB_SERDES             0x1060
  84 #define E1000_DEV_ID_82571EB_SERDES_DUAL        0x10D9
  85 #define E1000_DEV_ID_82571EB_SERDES_QUAD        0x10DA
  86 #define E1000_DEV_ID_82571EB_QUAD_COPPER        0x10A4
  87 #define E1000_DEV_ID_82571PT_QUAD_COPPER        0x10D5
  88 #define E1000_DEV_ID_82571EB_QUAD_FIBER         0x10A5
  89 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP     0x10BC
  90 #define E1000_DEV_ID_82572EI_COPPER             0x107D
  91 #define E1000_DEV_ID_82572EI_FIBER              0x107E
  92 #define E1000_DEV_ID_82572EI_SERDES             0x107F
  93 #define E1000_DEV_ID_82572EI                    0x10B9
  94 #define E1000_DEV_ID_82573E                     0x108B
  95 #define E1000_DEV_ID_82573E_IAMT                0x108C
  96 #define E1000_DEV_ID_82573L                     0x109A
  97 #define E1000_DEV_ID_82574L                     0x10D3
  98 #define E1000_DEV_ID_82574LA                    0x10F6
  99 #define E1000_DEV_ID_82583V                     0x150C
 100 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096
 101 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098
 102 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA
 103 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB
 104 #define E1000_DEV_ID_ICH8_82567V_3              0x1501
 105 #define E1000_DEV_ID_ICH8_IGP_M_AMT             0x1049
 106 #define E1000_DEV_ID_ICH8_IGP_AMT               0x104A
 107 #define E1000_DEV_ID_ICH8_IGP_C                 0x104B
 108 #define E1000_DEV_ID_ICH8_IFE                   0x104C
 109 #define E1000_DEV_ID_ICH8_IFE_GT                0x10C4
 110 #define E1000_DEV_ID_ICH8_IFE_G                 0x10C5
 111 #define E1000_DEV_ID_ICH8_IGP_M                 0x104D
 112 #define E1000_DEV_ID_ICH9_IGP_M                 0x10BF
 113 #define E1000_DEV_ID_ICH9_IGP_M_AMT             0x10F5
 114 #define E1000_DEV_ID_ICH9_IGP_M_V               0x10CB
 115 #define E1000_DEV_ID_ICH9_IGP_AMT               0x10BD
 116 #define E1000_DEV_ID_ICH9_BM                    0x10E5
 117 #define E1000_DEV_ID_ICH9_IGP_C                 0x294C
 118 #define E1000_DEV_ID_ICH9_IFE                   0x10C0
 119 #define E1000_DEV_ID_ICH9_IFE_GT                0x10C3
 120 #define E1000_DEV_ID_ICH9_IFE_G                 0x10C2
 121 #define E1000_DEV_ID_ICH10_R_BM_LM              0x10CC
 122 #define E1000_DEV_ID_ICH10_R_BM_LF              0x10CD
 123 #define E1000_DEV_ID_ICH10_R_BM_V               0x10CE
 124 #define E1000_DEV_ID_ICH10_D_BM_LM              0x10DE
 125 #define E1000_DEV_ID_ICH10_D_BM_LF              0x10DF
 126 #define E1000_DEV_ID_ICH10_D_BM_V               0x1525
 127 #define E1000_DEV_ID_PCH_M_HV_LM                0x10EA
 128 #define E1000_DEV_ID_PCH_M_HV_LC                0x10EB
 129 #define E1000_DEV_ID_PCH_D_HV_DM                0x10EF
 130 #define E1000_DEV_ID_PCH_D_HV_DC                0x10F0
 131 #define E1000_DEV_ID_PCH2_LV_LM                 0x1502
 132 #define E1000_DEV_ID_PCH2_LV_V                  0x1503
 133 #define E1000_DEV_ID_PCH_LPT_I217_LM            0x153A
 134 #define E1000_DEV_ID_PCH_LPT_I217_V             0x153B
 135 #define E1000_DEV_ID_PCH_LPTLP_I218_LM          0x155A
 136 #define E1000_DEV_ID_PCH_LPTLP_I218_V           0x1559
 137 #define E1000_DEV_ID_PCH_I218_LM2               0x15A0
 138 #define E1000_DEV_ID_PCH_I218_V2                0x15A1
 139 #define E1000_DEV_ID_PCH_I218_LM3               0x15A2 /* Wildcat Point PCH */
 140 #define E1000_DEV_ID_PCH_I218_V3                0x15A3 /* Wildcat Point PCH */
 141 #define E1000_DEV_ID_PCH_SPT_I219_LM            0x156F /* Sunrise Point PCH */
 142 #define E1000_DEV_ID_PCH_SPT_I219_V             0x1570 /* Sunrise Point PCH */
 143 #define E1000_DEV_ID_PCH_SPT_I219_LM2           0x15B7 /* Sunrise Point-H PCH */
 144 #define E1000_DEV_ID_PCH_SPT_I219_V2            0x15B8 /* Sunrise Point-H PCH */
 145 #define E1000_DEV_ID_PCH_LBG_I219_LM3           0x15B9 /* LEWISBURG PCH */
 146 #define E1000_DEV_ID_PCH_SPT_I219_LM4           0x15D7
 147 #define E1000_DEV_ID_PCH_SPT_I219_V4            0x15D8
 148 #define E1000_DEV_ID_PCH_SPT_I219_LM5           0x15E3
 149 #define E1000_DEV_ID_PCH_SPT_I219_V5            0x15D6
 150 #define E1000_DEV_ID_PCH_CNP_I219_LM6           0x15BD
 151 #define E1000_DEV_ID_PCH_CNP_I219_V6            0x15BE
 152 #define E1000_DEV_ID_PCH_CNP_I219_LM7           0x15BB
 153 #define E1000_DEV_ID_PCH_CNP_I219_V7            0x15BC
 154 #define E1000_DEV_ID_PCH_ICP_I219_LM8           0x15DF
 155 #define E1000_DEV_ID_PCH_ICP_I219_V8            0x15E0
 156 #define E1000_DEV_ID_PCH_ICP_I219_LM9           0x15E1
 157 #define E1000_DEV_ID_PCH_ICP_I219_V9            0x15E2
 158 #define E1000_DEV_ID_82576                      0x10C9
 159 #define E1000_DEV_ID_82576_FIBER                0x10E6
 160 #define E1000_DEV_ID_82576_SERDES               0x10E7
 161 #define E1000_DEV_ID_82576_QUAD_COPPER          0x10E8
 162 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2      0x1526
 163 #define E1000_DEV_ID_82576_NS                   0x150A
 164 #define E1000_DEV_ID_82576_NS_SERDES            0x1518
 165 #define E1000_DEV_ID_82576_SERDES_QUAD          0x150D
 166 #define E1000_DEV_ID_82576_VF                   0x10CA
 167 #define E1000_DEV_ID_82576_VF_HV                0x152D
 168 #define E1000_DEV_ID_I350_VF                    0x1520
 169 #define E1000_DEV_ID_I350_VF_HV                 0x152F
 170 #define E1000_DEV_ID_82575EB_COPPER             0x10A7
 171 #define E1000_DEV_ID_82575EB_FIBER_SERDES       0x10A9
 172 #define E1000_DEV_ID_82575GB_QUAD_COPPER        0x10D6
 173 #define E1000_DEV_ID_82580_COPPER               0x150E
 174 #define E1000_DEV_ID_82580_FIBER                0x150F
 175 #define E1000_DEV_ID_82580_SERDES               0x1510
 176 #define E1000_DEV_ID_82580_SGMII                0x1511
 177 #define E1000_DEV_ID_82580_COPPER_DUAL          0x1516
 178 #define E1000_DEV_ID_82580_QUAD_FIBER           0x1527
 179 #define E1000_DEV_ID_I350_COPPER                0x1521
 180 #define E1000_DEV_ID_I350_FIBER                 0x1522
 181 #define E1000_DEV_ID_I350_SERDES                0x1523
 182 #define E1000_DEV_ID_I350_SGMII                 0x1524
 183 #define E1000_DEV_ID_I350_DA4                   0x1546
 184 #define E1000_DEV_ID_I210_COPPER                0x1533
 185 #define E1000_DEV_ID_I210_COPPER_OEM1           0x1534
 186 #define E1000_DEV_ID_I210_COPPER_IT             0x1535
 187 #define E1000_DEV_ID_I210_FIBER                 0x1536
 188 #define E1000_DEV_ID_I210_SERDES                0x1537
 189 #define E1000_DEV_ID_I210_SGMII                 0x1538
 190 #define E1000_DEV_ID_I210_COPPER_FLASHLESS      0x157B
 191 #define E1000_DEV_ID_I210_SERDES_FLASHLESS      0x157C
 192 #define E1000_DEV_ID_I211_COPPER                0x1539
 193 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS       0x1F40
 194 #define E1000_DEV_ID_I354_SGMII                 0x1F41
 195 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS     0x1F45
 196 #define E1000_DEV_ID_DH89XXCC_SGMII             0x0438
 197 #define E1000_DEV_ID_DH89XXCC_SERDES            0x043A
 198 #define E1000_DEV_ID_DH89XXCC_BACKPLANE         0x043C
 199 #define E1000_DEV_ID_DH89XXCC_SFP               0x0440
 200
 201 #define E1000_REVISION_0        0
 202 #define E1000_REVISION_1        1
 203 #define E1000_REVISION_2        2
 204 #define E1000_REVISION_3        3
 205 #define E1000_REVISION_4        4
 206
 207 #define E1000_FUNC_0            0
 208 #define E1000_FUNC_1            1
 209 #define E1000_FUNC_2            2
 210 #define E1000_FUNC_3            3
 211
 212 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0       0
 213 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1       3
 214 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2       6
 215 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3       9
 216
 217 enum e1000_mac_type {
 218         e1000_undefined = 0,
 219         e1000_82542,
 220         e1000_82543,
 221         e1000_82544,
 222         e1000_82540,
 223         e1000_82545,
 224         e1000_82545_rev_3,
 225         e1000_82546,
 226         e1000_82546_rev_3,
 227         e1000_82541,
 228         e1000_82541_rev_2,
 229         e1000_82547,
 230         e1000_82547_rev_2,
 231         e1000_82571,
 232         e1000_82572,
 233         e1000_82573,
 234         e1000_82574,
 235         e1000_82583,
 236         e1000_80003es2lan,
 237         e1000_ich8lan,
 238         e1000_ich9lan,
 239         e1000_ich10lan,
 240         e1000_pchlan,
 241         e1000_pch2lan,
 242         e1000_pch_lpt,
 243         e1000_pch_spt,
 244         e1000_pch_cnp,
 245         e1000_82575,
 246         e1000_82576,
 247         e1000_82580,
 248         e1000_i350,
 249         e1000_i354,
 250         e1000_i210,
 251         e1000_i211,
 252         e1000_vfadapt,
 253         e1000_vfadapt_i350,
 254         e1000_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
 255 };
 256
 257 enum e1000_media_type {
 258         e1000_media_type_unknown = 0,
 259         e1000_media_type_copper = 1,
 260         e1000_media_type_fiber = 2,
 261         e1000_media_type_internal_serdes = 3,
 262         e1000_num_media_types
 263 };
 264
 265 enum e1000_nvm_type {
 266         e1000_nvm_unknown = 0,
 267         e1000_nvm_none,
 268         e1000_nvm_eeprom_spi,
 269         e1000_nvm_eeprom_microwire,
 270         e1000_nvm_flash_hw,
 271         e1000_nvm_invm,
 272         e1000_nvm_flash_sw
 273 };
 274
 275 enum e1000_nvm_override {
 276         e1000_nvm_override_none = 0,
 277         e1000_nvm_override_spi_small,
 278         e1000_nvm_override_spi_large,
 279         e1000_nvm_override_microwire_small,
 280         e1000_nvm_override_microwire_large
 281 };
 282
 283 enum e1000_phy_type {
 284         e1000_phy_unknown = 0,
 285         e1000_phy_none,
 286         e1000_phy_m88,
 287         e1000_phy_igp,
 288         e1000_phy_igp_2,
 289         e1000_phy_gg82563,
 290         e1000_phy_igp_3,
 291         e1000_phy_ife,
 292         e1000_phy_bm,
 293         e1000_phy_82578,
 294         e1000_phy_82577,
 295         e1000_phy_82579,
 296         e1000_phy_i217,
 297         e1000_phy_82580,
 298         e1000_phy_vf,
 299         e1000_phy_i210,
 300 };
 301
 302 enum e1000_bus_type {
 303         e1000_bus_type_unknown = 0,
 304         e1000_bus_type_pci,
 305         e1000_bus_type_pcix,
 306         e1000_bus_type_pci_express,
 307         e1000_bus_type_reserved
 308 };
 309
 310 enum e1000_bus_speed {
 311         e1000_bus_speed_unknown = 0,
 312         e1000_bus_speed_33,
 313         e1000_bus_speed_66,
 314         e1000_bus_speed_100,
 315         e1000_bus_speed_120,
 316         e1000_bus_speed_133,
 317         e1000_bus_speed_2500,
 318         e1000_bus_speed_5000,
 319         e1000_bus_speed_reserved
 320 };
 321
 322 enum e1000_bus_width {
 323         e1000_bus_width_unknown = 0,
 324         e1000_bus_width_pcie_x1,
 325         e1000_bus_width_pcie_x2,
 326         e1000_bus_width_pcie_x4 = 4,
 327         e1000_bus_width_pcie_x8 = 8,
 328         e1000_bus_width_32,
 329         e1000_bus_width_64,
 330         e1000_bus_width_reserved
 331 };
 332
 333 enum e1000_1000t_rx_status {
 334         e1000_1000t_rx_status_not_ok = 0,
 335         e1000_1000t_rx_status_ok,
 336         e1000_1000t_rx_status_undefined = 0xFF
 337 };
 338
 339 enum e1000_rev_polarity {
 340         e1000_rev_polarity_normal = 0,
 341         e1000_rev_polarity_reversed,
 342         e1000_rev_polarity_undefined = 0xFF
 343 };
 344
 345 enum e1000_fc_mode {
 346         e1000_fc_none = 0,
 347         e1000_fc_rx_pause,
 348         e1000_fc_tx_pause,
 349         e1000_fc_full,
 350         e1000_fc_default = 0xFF
 351 };
 352
 353 enum e1000_ffe_config {
 354         e1000_ffe_config_enabled = 0,
 355         e1000_ffe_config_active,
 356         e1000_ffe_config_blocked
 357 };
 358
 359 enum e1000_dsp_config {
 360         e1000_dsp_config_disabled = 0,
 361         e1000_dsp_config_enabled,
 362         e1000_dsp_config_activated,
 363         e1000_dsp_config_undefined = 0xFF
 364 };
 365
 366 enum e1000_ms_type {
 367         e1000_ms_hw_default = 0,
 368         e1000_ms_force_master,
 369         e1000_ms_force_slave,
 370         e1000_ms_auto
 371 };
 372
 373 enum e1000_smart_speed {
 374         e1000_smart_speed_default = 0,
 375         e1000_smart_speed_on,
 376         e1000_smart_speed_off
 377 };
 378
 379 enum e1000_serdes_link_state {
 380         e1000_serdes_link_down = 0,
 381         e1000_serdes_link_autoneg_progress,
 382         e1000_serdes_link_autoneg_complete,
 383         e1000_serdes_link_forced_up
 384 };
 385
 386 #define __le16 u16
 387 #define __le32 u32
 388 #define __le64 u64
 389 /* Receive Descriptor */
 390 struct e1000_rx_desc {
 391         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 392         __le16 length;      /* Length of data DMAed into data buffer */
 393         __le16 csum; /* Packet checksum */
 394         u8  status;  /* Descriptor status */
 395         u8  errors;  /* Descriptor Errors */
 396         __le16 special;
 397 };
 398
 399 /* Receive Descriptor - Extended */
 400 union e1000_rx_desc_extended {
 401         struct {
 402                 __le64 buffer_addr;
 403                 __le64 reserved;
 404         } read;
 405         struct {
 406                 struct {
 407                         __le32 mrq; /* Multiple Rx Queues */
 408                         union {
 409                                 __le32 rss; /* RSS Hash */
 410                                 struct {
 411                                         __le16 ip_id;  /* IP id */
 412                                         __le16 csum;   /* Packet Checksum */
 413                                 } csum_ip;
 414                         } hi_dword;
 415                 } lower;
 416                 struct {
 417                         __le32 status_error;  /* ext status/error */
 418                         __le16 length;
 419                         __le16 vlan; /* VLAN tag */
 420                 } upper;
 421         } wb;  /* writeback */
 422 };
 423
 424 #define MAX_PS_BUFFERS 4
 425
 426 /* Number of packet split data buffers (not including the header buffer) */
 427 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
 428
 429 /* Receive Descriptor - Packet Split */
 430 union e1000_rx_desc_packet_split {
 431         struct {
 432                 /* one buffer for protocol header(s), three data buffers */
 433                 __le64 buffer_addr[MAX_PS_BUFFERS];
 434         } read;
 435         struct {
 436                 struct {
 437                         __le32 mrq;  /* Multiple Rx Queues */
 438                         union {
 439                                 __le32 rss; /* RSS Hash */
 440                                 struct {
 441                                         __le16 ip_id;    /* IP id */
 442                                         __le16 csum;     /* Packet Checksum */
 443                                 } csum_ip;
 444                         } hi_dword;
 445                 } lower;
 446                 struct {
 447                         __le32 status_error;  /* ext status/error */
 448                         __le16 length0;  /* length of buffer 0 */
 449                         __le16 vlan;  /* VLAN tag */
 450                 } middle;
 451                 struct {
 452                         __le16 header_status;
 453                         /* length of buffers 1-3 */
 454                         __le16 length[PS_PAGE_BUFFERS];
 455                 } upper;
 456                 __le64 reserved;
 457         } wb; /* writeback */
 458 };
 459
 460 /* Transmit Descriptor */
 461 struct e1000_tx_desc {
 462         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 463         union {
 464                 __le32 data;
 465                 struct {
 466                         __le16 length;  /* Data buffer length */
 467                         u8 cso;  /* Checksum offset */
 468                         u8 cmd;  /* Descriptor control */
 469                 } flags;
 470         } lower;
 471         union {
 472                 __le32 data;
 473                 struct {
 474                         u8 status; /* Descriptor status */
 475                         u8 css;  /* Checksum start */
 476                         __le16 special;
 477                 } fields;
 478         } upper;
 479 };
 480
 481 /* Offload Context Descriptor */
 482 struct e1000_context_desc {
 483         union {
 484                 __le32 ip_config;
 485                 struct {
 486                         u8 ipcss;  /* IP checksum start */
 487                         u8 ipcso;  /* IP checksum offset */
 488                         __le16 ipcse;  /* IP checksum end */
 489                 } ip_fields;
 490         } lower_setup;
 491         union {
 492                 __le32 tcp_config;
 493                 struct {
 494                         u8 tucss;  /* TCP checksum start */
 495                         u8 tucso;  /* TCP checksum offset */
 496                         __le16 tucse;  /* TCP checksum end */
 497                 } tcp_fields;
 498         } upper_setup;
 499         __le32 cmd_and_length;
 500         union {
 501                 __le32 data;
 502                 struct {
 503                         u8 status;  /* Descriptor status */
 504                         u8 hdr_len;  /* Header length */
 505                         __le16 mss;  /* Maximum segment size */
 506                 } fields;
 507         } tcp_seg_setup;
 508 };
 509
 510 /* Offload data descriptor */
 511 struct e1000_data_desc {
 512         __le64 buffer_addr;  /* Address of the descriptor's buffer address */
 513         union {
 514                 __le32 data;
 515                 struct {
 516                         __le16 length;  /* Data buffer length */
 517                         u8 typ_len_ext;
 518                         u8 cmd;
 519                 } flags;
 520         } lower;
 521         union {
 522                 __le32 data;
 523                 struct {
 524                         u8 status;  /* Descriptor status */
 525                         u8 popts;  /* Packet Options */
 526                         __le16 special;
 527                 } fields;
 528         } upper;
 529 };
 530
 531 /* Statistics counters collected by the MAC */
 532 struct e1000_hw_stats {
 533         u64 crcerrs;
 534         u64 algnerrc;
 535         u64 symerrs;
 536         u64 rxerrc;
 537         u64 mpc;
 538         u64 scc;
 539         u64 ecol;
 540         u64 mcc;
 541         u64 latecol;
 542         u64 colc;
 543         u64 dc;
 544         u64 tncrs;
 545         u64 sec;
 546         u64 cexterr;
 547         u64 rlec;
 548         u64 xonrxc;
 549         u64 xontxc;
 550         u64 xoffrxc;
 551         u64 xofftxc;
 552         u64 fcruc;
 553         u64 prc64;
 554         u64 prc127;
 555         u64 prc255;
 556         u64 prc511;
 557         u64 prc1023;
 558         u64 prc1522;
 559         u64 gprc;
 560         u64 bprc;
 561         u64 mprc;
 562         u64 gptc;
 563         u64 gorc;
 564         u64 gotc;
 565         u64 rnbc;
 566         u64 ruc;
 567         u64 rfc;
 568         u64 roc;
 569         u64 rjc;
 570         u64 mgprc;
 571         u64 mgpdc;
 572         u64 mgptc;
 573         u64 tor;
 574         u64 tot;
 575         u64 tpr;
 576         u64 tpt;
 577         u64 ptc64;
 578         u64 ptc127;
 579         u64 ptc255;
 580         u64 ptc511;
 581         u64 ptc1023;
 582         u64 ptc1522;
 583         u64 mptc;
 584         u64 bptc;
 585         u64 tsctc;
 586         u64 tsctfc;
 587         u64 iac;
 588         u64 icrxptc;
 589         u64 icrxatc;
 590         u64 ictxptc;
 591         u64 ictxatc;
 592         u64 ictxqec;
 593         u64 ictxqmtc;
 594         u64 icrxdmtc;
 595         u64 icrxoc;
 596         u64 cbtmpc;
 597         u64 htdpmc;
 598         u64 cbrdpc;
 599         u64 cbrmpc;
 600         u64 rpthc;
 601         u64 hgptc;
 602         u64 htcbdpc;
 603         u64 hgorc;
 604         u64 hgotc;
 605         u64 lenerrs;
 606         u64 scvpc;
 607         u64 hrmpc;
 608         u64 doosync;
 609         u64 o2bgptc;
 610         u64 o2bspc;
 611         u64 b2ospc;
 612         u64 b2ogprc;
 613 };
 614
 615 struct e1000_vf_stats {
 616         u64 base_gprc;
 617         u64 base_gptc;
 618         u64 base_gorc;
 619         u64 base_gotc;
 620         u64 base_mprc;
 621         u64 base_gotlbc;
 622         u64 base_gptlbc;
 623         u64 base_gorlbc;
 624         u64 base_gprlbc;
 625
 626         u32 last_gprc;
 627         u32 last_gptc;
 628         u32 last_gorc;
 629         u32 last_gotc;
 630         u32 last_mprc;
 631         u32 last_gotlbc;
 632         u32 last_gptlbc;
 633         u32 last_gorlbc;
 634         u32 last_gprlbc;
 635
 636         u64 gprc;
 637         u64 gptc;
 638         u64 gorc;
 639         u64 gotc;
 640         u64 mprc;
 641         u64 gotlbc;
 642         u64 gptlbc;
 643         u64 gorlbc;
 644         u64 gprlbc;
 645 };
 646
 647 struct e1000_phy_stats {
 648         u32 idle_errors;
 649         u32 receive_errors;
 650 };
 651
 652 struct e1000_host_mng_dhcp_cookie {
 653         u32 signature;
 654         u8  status;
 655         u8  reserved0;
 656         u16 vlan_id;
 657         u32 reserved1;
 658         u16 reserved2;
 659         u8  reserved3;
 660         u8  checksum;
 661 };
 662
 663 /* Host Interface "Rev 1" */
 664 struct e1000_host_command_header {
 665         u8 command_id;
 666         u8 command_length;
 667         u8 command_options;
 668         u8 checksum;
 669 };
 670
 671 #define E1000_HI_MAX_DATA_LENGTH        252
 672 struct e1000_host_command_info {
 673         struct e1000_host_command_header command_header;
 674         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 675 };
 676
 677 /* Host Interface "Rev 2" */
 678 struct e1000_host_mng_command_header {
 679         u8  command_id;
 680         u8  checksum;
 681         u16 reserved1;
 682         u16 reserved2;
 683         u16 command_length;
 684 };
 685
 686 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
 687 struct e1000_host_mng_command_info {
 688         struct e1000_host_mng_command_header command_header;
 689         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 690 };
 691
 692 #include "e1000_mac.h"
 693 #include "e1000_phy.h"
 694 #include "e1000_nvm.h"
 695 #include "e1000_manage.h"
 696 #include "e1000_mbx.h"
 697
 698 /* Function pointers for the MAC. */
 699 struct e1000_mac_operations {
 700         s32  (*init_params)(struct e1000_hw *);
 701         s32  (*id_led_init)(struct e1000_hw *);
 702         s32  (*blink_led)(struct e1000_hw *);
 703         bool (*check_mng_mode)(struct e1000_hw *);
 704         s32  (*check_for_link)(struct e1000_hw *);
 705         s32  (*cleanup_led)(struct e1000_hw *);
 706         void (*clear_hw_cntrs)(struct e1000_hw *);
 707         void (*clear_vfta)(struct e1000_hw *);
 708         s32  (*get_bus_info)(struct e1000_hw *);
 709         void (*set_lan_id)(struct e1000_hw *);
 710         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 711         s32  (*led_on)(struct e1000_hw *);
 712         s32  (*led_off)(struct e1000_hw *);
 713         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 714         s32  (*reset_hw)(struct e1000_hw *);
 715         s32  (*init_hw)(struct e1000_hw *);
 716         void (*shutdown_serdes)(struct e1000_hw *);
 717         void (*power_up_serdes)(struct e1000_hw *);
 718         s32  (*setup_link)(struct e1000_hw *);
 719         s32  (*setup_physical_interface)(struct e1000_hw *);
 720         s32  (*setup_led)(struct e1000_hw *);
 721         void (*write_vfta)(struct e1000_hw *, u32, u32);
 722         void (*config_collision_dist)(struct e1000_hw *);
 723         int  (*rar_set)(struct e1000_hw *, u8*, u32);
 724         s32  (*read_mac_addr)(struct e1000_hw *);
 725         s32  (*validate_mdi_setting)(struct e1000_hw *);
 726         s32  (*set_obff_timer)(struct e1000_hw *, u32);
 727         s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
 728         void (*release_swfw_sync)(struct e1000_hw *, u16);
 729 };
 730
 731 /* When to use various PHY register access functions:
 732  *
 733  *                 Func   Caller
 734  *   Function      Does   Does    When to use
 735  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 736  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 737  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 738  *                                on different pages
 739  *   X_reg_page    A      L,P     for multiple accesses of different regs
 740  *                                on the same page
 741  *
 742  * Where X=[read|write], L=locking, P=sets page, A=register access
 743  *
 744  */
 745 struct e1000_phy_operations {
 746         s32  (*init_params)(struct e1000_hw *);
 747         s32  (*acquire)(struct e1000_hw *);
 748         s32  (*cfg_on_link_up)(struct e1000_hw *);
 749         s32  (*check_polarity)(struct e1000_hw *);
 750         s32  (*check_reset_block)(struct e1000_hw *);
 751         s32  (*commit)(struct e1000_hw *);
 752         s32  (*force_speed_duplex)(struct e1000_hw *);
 753         s32  (*get_cfg_done)(struct e1000_hw *hw);
 754         s32  (*get_cable_length)(struct e1000_hw *);
 755         s32  (*get_info)(struct e1000_hw *);
 756         s32  (*set_page)(struct e1000_hw *, u16);
 757         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 758         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 759         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 760         void (*release)(struct e1000_hw *);
 761         s32  (*reset)(struct e1000_hw *);
 762         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 763         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 764         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 765         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 766         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 767         void (*power_up)(struct e1000_hw *);
 768         void (*power_down)(struct e1000_hw *);
 769         s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
 770         s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
 771 };
 772
 773 /* Function pointers for the NVM. */
 774 struct e1000_nvm_operations {
 775         s32  (*init_params)(struct e1000_hw *);
 776         s32  (*acquire)(struct e1000_hw *);
 777         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 778         void (*release)(struct e1000_hw *);
 779         void (*reload)(struct e1000_hw *);
 780         s32  (*update)(struct e1000_hw *);
 781         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 782         s32  (*validate)(struct e1000_hw *);
 783         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 784 };
 785
 786 struct e1000_mac_info {
 787         struct e1000_mac_operations ops;
 788         u8 addr[ETH_ADDR_LEN];
 789         u8 perm_addr[ETH_ADDR_LEN];
 790
 791         enum e1000_mac_type type;
 792
 793         u32 collision_delta;
 794         u32 ledctl_default;
 795         u32 ledctl_mode1;
 796         u32 ledctl_mode2;
 797         u32 mc_filter_type;
 798         u32 tx_packet_delta;
 799         u32 txcw;
 800
 801         u16 current_ifs_val;
 802         u16 ifs_max_val;
 803         u16 ifs_min_val;
 804         u16 ifs_ratio;
 805         u16 ifs_step_size;
 806         u16 mta_reg_count;
 807         u16 uta_reg_count;
 808
 809         /* Maximum size of the MTA register table in all supported adapters */
 810 #define MAX_MTA_REG 128
 811         u32 mta_shadow[MAX_MTA_REG];
 812         u16 rar_entry_count;
 813
 814         u8  forced_speed_duplex;
 815
 816         bool adaptive_ifs;
 817         bool has_fwsm;
 818         bool arc_subsystem_valid;
 819         bool asf_firmware_present;
 820         bool autoneg;
 821         bool autoneg_failed;
 822         bool get_link_status;
 823         bool in_ifs_mode;
 824         bool report_tx_early;
 825         enum e1000_serdes_link_state serdes_link_state;
 826         bool serdes_has_link;
 827         bool tx_pkt_filtering;
 828         u32  max_frame_size;
 829 };
 830
 831 struct e1000_phy_info {
 832         struct e1000_phy_operations ops;
 833         enum e1000_phy_type type;
 834
 835         enum e1000_1000t_rx_status local_rx;
 836         enum e1000_1000t_rx_status remote_rx;
 837         enum e1000_ms_type ms_type;
 838         enum e1000_ms_type original_ms_type;
 839         enum e1000_rev_polarity cable_polarity;
 840         enum e1000_smart_speed smart_speed;
 841
 842         u32 addr;
 843         u32 id;
 844         u32 reset_delay_us; /* in usec */
 845         u32 revision;
 846
 847         enum e1000_media_type media_type;
 848
 849         u16 autoneg_advertised;
 850         u16 autoneg_mask;
 851         u16 cable_length;
 852         u16 max_cable_length;
 853         u16 min_cable_length;
 854
 855         u8 mdix;
 856
 857         bool disable_polarity_correction;
 858         bool is_mdix;
 859         bool polarity_correction;
 860         bool speed_downgraded;
 861         bool autoneg_wait_to_complete;
 862 };
 863
 864 struct e1000_nvm_info {
 865         struct e1000_nvm_operations ops;
 866         enum e1000_nvm_type type;
 867         enum e1000_nvm_override override;
 868
 869         u32 flash_bank_size;
 870         u32 flash_base_addr;
 871
 872         u16 word_size;
 873         u16 delay_usec;
 874         u16 address_bits;
 875         u16 opcode_bits;
 876         u16 page_size;
 877 };
 878
 879 struct e1000_bus_info {
 880         enum e1000_bus_type type;
 881         enum e1000_bus_speed speed;
 882         enum e1000_bus_width width;
 883
 884         u16 func;
 885         u16 pci_cmd_word;
 886 };
 887
 888 struct e1000_fc_info {
 889         u32 high_water;  /* Flow control high-water mark */
 890         u32 low_water;  /* Flow control low-water mark */
 891         u16 pause_time;  /* Flow control pause timer */
 892         u16 refresh_time;  /* Flow control refresh timer */
 893         bool send_xon;  /* Flow control send XON */
 894         bool strict_ieee;  /* Strict IEEE mode */
 895         enum e1000_fc_mode current_mode;  /* FC mode in effect */
 896         enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
 897 };
 898
 899 struct e1000_mbx_operations {
 900         s32 (*init_params)(struct e1000_hw *hw);
 901         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 902         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 903         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 904         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 905         s32 (*check_for_msg)(struct e1000_hw *, u16);
 906         s32 (*check_for_ack)(struct e1000_hw *, u16);
 907         s32 (*check_for_rst)(struct e1000_hw *, u16);
 908 };
 909
 910 struct e1000_mbx_stats {
 911         u32 msgs_tx;
 912         u32 msgs_rx;
 913
 914         u32 acks;
 915         u32 reqs;
 916         u32 rsts;
 917 };
 918
 919 struct e1000_mbx_info {
 920         struct e1000_mbx_operations ops;
 921         struct e1000_mbx_stats stats;
 922         u32 timeout;
 923         u32 usec_delay;
 924         u16 size;
 925 };
 926
 927 struct e1000_dev_spec_82541 {
 928         enum e1000_dsp_config dsp_config;
 929         enum e1000_ffe_config ffe_config;
 930         u16 spd_default;
 931         bool phy_init_script;
 932 };
 933
 934 struct e1000_dev_spec_82542 {
 935         bool dma_fairness;
 936 };
 937
 938 struct e1000_dev_spec_82543 {
 939         u32  tbi_compatibility;
 940         bool dma_fairness;
 941         bool init_phy_disabled;
 942 };
 943
 944 struct e1000_dev_spec_82571 {
 945         bool laa_is_present;
 946         u32 smb_counter;
 947 };
 948
 949 struct e1000_dev_spec_80003es2lan {
 950         bool  mdic_wa_enable;
 951 };
 952
 953 struct e1000_shadow_ram {
 954         u16  value;
 955         bool modified;
 956 };
 957
 958 #define E1000_SHADOW_RAM_WORDS          2048
 959
 960 /* I218 PHY Ultra Low Power (ULP) states */
 961 enum e1000_ulp_state {
 962         e1000_ulp_state_unknown,
 963         e1000_ulp_state_off,
 964         e1000_ulp_state_on,
 965 };
 966
 967 struct e1000_dev_spec_ich8lan {
 968         bool kmrn_lock_loss_workaround_enabled;
 969         struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
 970         bool nvm_k1_enabled;
 971         bool disable_k1_off;
 972         bool eee_disable;
 973         u16 eee_lp_ability;
 974         enum e1000_ulp_state ulp_state;
 975         bool ulp_capability_disabled;
 976         bool during_suspend_flow;
 977         bool during_dpg_exit;
 978 };
 979
 980 struct e1000_dev_spec_82575 {
 981         bool sgmii_active;
 982         bool global_device_reset;
 983         bool eee_disable;
 984         bool module_plugged;
 985         bool clear_semaphore_once;
 986         u32 mtu;
 987         struct sfp_e1000_flags eth_flags;
 988         u8 media_port;
 989         bool media_changed;
 990 };
 991
 992 struct e1000_dev_spec_vf {
 993         u32 vf_number;
 994         u32 v2p_mailbox;
 995 };
 996
 997 struct e1000_hw {
 998         void *back;
 999
1000         u8 *hw_addr;
1001         u8 *flash_address;
1002         unsigned long io_base;
1003
1004         struct e1000_mac_info  mac;
1005         struct e1000_fc_info   fc;
1006         struct e1000_phy_info  phy;
1007         struct e1000_nvm_info  nvm;
1008         struct e1000_bus_info  bus;
1009         struct e1000_mbx_info mbx;
1010         struct e1000_host_mng_dhcp_cookie mng_cookie;
1011
1012         union {
1013                 struct e1000_dev_spec_82541 _82541;
1014                 struct e1000_dev_spec_82542 _82542;
1015                 struct e1000_dev_spec_82543 _82543;
1016                 struct e1000_dev_spec_82571 _82571;
1017                 struct e1000_dev_spec_80003es2lan _80003es2lan;
1018                 struct e1000_dev_spec_ich8lan ich8lan;
1019                 struct e1000_dev_spec_82575 _82575;
1020                 struct e1000_dev_spec_vf vf;
1021         } dev_spec;
1022
1023         u16 device_id;
1024         u16 subsystem_vendor_id;
1025         u16 subsystem_device_id;
1026         u16 vendor_id;
1027
1028         u8  revision_id;
1029 };
1030
1031 #include "e1000_82541.h"
1032 #include "e1000_82543.h"
1033 #include "e1000_82571.h"
1034 #include "e1000_80003es2lan.h"
1035 #include "e1000_ich8lan.h"
1036 #include "e1000_82575.h"
1037 #include "e1000_i210.h"
1038
1039 /* These functions must be implemented by drivers */
1040 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1041 void e1000_pci_set_mwi(struct e1000_hw *hw);
1042 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1043 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1044 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1045 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1046
1047 #endif