1 /******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
38 #include "e1000_osdep.h"
39 #include "e1000_regs.h"
40 #include "e1000_defines.h"
44 #define E1000_DEV_ID_82542 0x1000
45 #define E1000_DEV_ID_82543GC_FIBER 0x1001
46 #define E1000_DEV_ID_82543GC_COPPER 0x1004
47 #define E1000_DEV_ID_82544EI_COPPER 0x1008
48 #define E1000_DEV_ID_82544EI_FIBER 0x1009
49 #define E1000_DEV_ID_82544GC_COPPER 0x100C
50 #define E1000_DEV_ID_82544GC_LOM 0x100D
51 #define E1000_DEV_ID_82540EM 0x100E
52 #define E1000_DEV_ID_82540EM_LOM 0x1015
53 #define E1000_DEV_ID_82540EP_LOM 0x1016
54 #define E1000_DEV_ID_82540EP 0x1017
55 #define E1000_DEV_ID_82540EP_LP 0x101E
56 #define E1000_DEV_ID_82545EM_COPPER 0x100F
57 #define E1000_DEV_ID_82545EM_FIBER 0x1011
58 #define E1000_DEV_ID_82545GM_COPPER 0x1026
59 #define E1000_DEV_ID_82545GM_FIBER 0x1027
60 #define E1000_DEV_ID_82545GM_SERDES 0x1028
61 #define E1000_DEV_ID_82546EB_COPPER 0x1010
62 #define E1000_DEV_ID_82546EB_FIBER 0x1012
63 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
64 #define E1000_DEV_ID_82546GB_COPPER 0x1079
65 #define E1000_DEV_ID_82546GB_FIBER 0x107A
66 #define E1000_DEV_ID_82546GB_SERDES 0x107B
67 #define E1000_DEV_ID_82546GB_PCIE 0x108A
68 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
70 #define E1000_DEV_ID_82541EI 0x1013
71 #define E1000_DEV_ID_82541EI_MOBILE 0x1018
72 #define E1000_DEV_ID_82541ER_LOM 0x1014
73 #define E1000_DEV_ID_82541ER 0x1078
74 #define E1000_DEV_ID_82541GI 0x1076
75 #define E1000_DEV_ID_82541GI_LF 0x107C
76 #define E1000_DEV_ID_82541GI_MOBILE 0x1077
77 #define E1000_DEV_ID_82547EI 0x1019
78 #define E1000_DEV_ID_82547EI_MOBILE 0x101A
79 #define E1000_DEV_ID_82547GI 0x1075
80 #define E1000_DEV_ID_82571EB_COPPER 0x105E
81 #define E1000_DEV_ID_82571EB_FIBER 0x105F
82 #define E1000_DEV_ID_82571EB_SERDES 0x1060
83 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
84 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
85 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
86 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
87 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
89 #define E1000_DEV_ID_82572EI_COPPER 0x107D
90 #define E1000_DEV_ID_82572EI_FIBER 0x107E
91 #define E1000_DEV_ID_82572EI_SERDES 0x107F
92 #define E1000_DEV_ID_82572EI 0x10B9
93 #define E1000_DEV_ID_82573E 0x108B
94 #define E1000_DEV_ID_82573E_IAMT 0x108C
95 #define E1000_DEV_ID_82573L 0x109A
96 #define E1000_DEV_ID_82574L 0x10D3
97 #define E1000_DEV_ID_82574LA 0x10F6
98 #define E1000_DEV_ID_82583V 0x150C
99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
103 #define E1000_DEV_ID_ICH8_82567V_3 0x1501
104 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
105 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
106 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
107 #define E1000_DEV_ID_ICH8_IFE 0x104C
108 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
109 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
110 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
111 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF
112 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
113 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
114 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
115 #define E1000_DEV_ID_ICH9_BM 0x10E5
116 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
117 #define E1000_DEV_ID_ICH9_IFE 0x10C0
118 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
119 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
120 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
121 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
122 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
123 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
124 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
125 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525
126 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
127 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
128 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
129 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
130 #define E1000_DEV_ID_PCH2_LV_LM 0x1502
131 #define E1000_DEV_ID_PCH2_LV_V 0x1503
132 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
133 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
134 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
135 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
136 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0
137 #define E1000_DEV_ID_PCH_I218_V2 0x15A1
138 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */
139 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */
140 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */
141 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */
142 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */
143 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */
144 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */
145 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7
146 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8
147 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3
148 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6
149 #define E1000_DEV_ID_82576 0x10C9
150 #define E1000_DEV_ID_82576_FIBER 0x10E6
151 #define E1000_DEV_ID_82576_SERDES 0x10E7
152 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
153 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
154 #define E1000_DEV_ID_82576_NS 0x150A
155 #define E1000_DEV_ID_82576_NS_SERDES 0x1518
156 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
157 #define E1000_DEV_ID_82576_VF 0x10CA
158 #define E1000_DEV_ID_82576_VF_HV 0x152D
159 #define E1000_DEV_ID_I350_VF 0x1520
160 #define E1000_DEV_ID_I350_VF_HV 0x152F
161 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
162 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
163 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
164 #define E1000_DEV_ID_82580_COPPER 0x150E
165 #define E1000_DEV_ID_82580_FIBER 0x150F
166 #define E1000_DEV_ID_82580_SERDES 0x1510
167 #define E1000_DEV_ID_82580_SGMII 0x1511
168 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
169 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
170 #define E1000_DEV_ID_I350_COPPER 0x1521
171 #define E1000_DEV_ID_I350_FIBER 0x1522
172 #define E1000_DEV_ID_I350_SERDES 0x1523
173 #define E1000_DEV_ID_I350_SGMII 0x1524
174 #define E1000_DEV_ID_I350_DA4 0x1546
175 #define E1000_DEV_ID_I210_COPPER 0x1533
176 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534
177 #define E1000_DEV_ID_I210_COPPER_IT 0x1535
178 #define E1000_DEV_ID_I210_FIBER 0x1536
179 #define E1000_DEV_ID_I210_SERDES 0x1537
180 #define E1000_DEV_ID_I210_SGMII 0x1538
181 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B
182 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C
183 #define E1000_DEV_ID_I211_COPPER 0x1539
184 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40
185 #define E1000_DEV_ID_I354_SGMII 0x1F41
186 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45
187 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
188 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
189 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
190 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440
192 #define E1000_REVISION_0 0
193 #define E1000_REVISION_1 1
194 #define E1000_REVISION_2 2
195 #define E1000_REVISION_3 3
196 #define E1000_REVISION_4 4
198 #define E1000_FUNC_0 0
199 #define E1000_FUNC_1 1
200 #define E1000_FUNC_2 2
201 #define E1000_FUNC_3 3
203 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
204 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
205 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
206 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
208 enum e1000_mac_type {
244 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
247 enum e1000_media_type {
248 e1000_media_type_unknown = 0,
249 e1000_media_type_copper = 1,
250 e1000_media_type_fiber = 2,
251 e1000_media_type_internal_serdes = 3,
252 e1000_num_media_types
255 enum e1000_nvm_type {
256 e1000_nvm_unknown = 0,
258 e1000_nvm_eeprom_spi,
259 e1000_nvm_eeprom_microwire,
265 enum e1000_nvm_override {
266 e1000_nvm_override_none = 0,
267 e1000_nvm_override_spi_small,
268 e1000_nvm_override_spi_large,
269 e1000_nvm_override_microwire_small,
270 e1000_nvm_override_microwire_large
273 enum e1000_phy_type {
274 e1000_phy_unknown = 0,
292 enum e1000_bus_type {
293 e1000_bus_type_unknown = 0,
296 e1000_bus_type_pci_express,
297 e1000_bus_type_reserved
300 enum e1000_bus_speed {
301 e1000_bus_speed_unknown = 0,
307 e1000_bus_speed_2500,
308 e1000_bus_speed_5000,
309 e1000_bus_speed_reserved
312 enum e1000_bus_width {
313 e1000_bus_width_unknown = 0,
314 e1000_bus_width_pcie_x1,
315 e1000_bus_width_pcie_x2,
316 e1000_bus_width_pcie_x4 = 4,
317 e1000_bus_width_pcie_x8 = 8,
320 e1000_bus_width_reserved
323 enum e1000_1000t_rx_status {
324 e1000_1000t_rx_status_not_ok = 0,
325 e1000_1000t_rx_status_ok,
326 e1000_1000t_rx_status_undefined = 0xFF
329 enum e1000_rev_polarity {
330 e1000_rev_polarity_normal = 0,
331 e1000_rev_polarity_reversed,
332 e1000_rev_polarity_undefined = 0xFF
340 e1000_fc_default = 0xFF
343 enum e1000_ffe_config {
344 e1000_ffe_config_enabled = 0,
345 e1000_ffe_config_active,
346 e1000_ffe_config_blocked
349 enum e1000_dsp_config {
350 e1000_dsp_config_disabled = 0,
351 e1000_dsp_config_enabled,
352 e1000_dsp_config_activated,
353 e1000_dsp_config_undefined = 0xFF
357 e1000_ms_hw_default = 0,
358 e1000_ms_force_master,
359 e1000_ms_force_slave,
363 enum e1000_smart_speed {
364 e1000_smart_speed_default = 0,
365 e1000_smart_speed_on,
366 e1000_smart_speed_off
369 enum e1000_serdes_link_state {
370 e1000_serdes_link_down = 0,
371 e1000_serdes_link_autoneg_progress,
372 e1000_serdes_link_autoneg_complete,
373 e1000_serdes_link_forced_up
379 /* Receive Descriptor */
380 struct e1000_rx_desc {
381 __le64 buffer_addr; /* Address of the descriptor's data buffer */
382 __le16 length; /* Length of data DMAed into data buffer */
383 __le16 csum; /* Packet checksum */
384 u8 status; /* Descriptor status */
385 u8 errors; /* Descriptor Errors */
389 /* Receive Descriptor - Extended */
390 union e1000_rx_desc_extended {
397 __le32 mrq; /* Multiple Rx Queues */
399 __le32 rss; /* RSS Hash */
401 __le16 ip_id; /* IP id */
402 __le16 csum; /* Packet Checksum */
407 __le32 status_error; /* ext status/error */
409 __le16 vlan; /* VLAN tag */
411 } wb; /* writeback */
414 #define MAX_PS_BUFFERS 4
416 /* Number of packet split data buffers (not including the header buffer) */
417 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
419 /* Receive Descriptor - Packet Split */
420 union e1000_rx_desc_packet_split {
422 /* one buffer for protocol header(s), three data buffers */
423 __le64 buffer_addr[MAX_PS_BUFFERS];
427 __le32 mrq; /* Multiple Rx Queues */
429 __le32 rss; /* RSS Hash */
431 __le16 ip_id; /* IP id */
432 __le16 csum; /* Packet Checksum */
437 __le32 status_error; /* ext status/error */
438 __le16 length0; /* length of buffer 0 */
439 __le16 vlan; /* VLAN tag */
442 __le16 header_status;
443 /* length of buffers 1-3 */
444 __le16 length[PS_PAGE_BUFFERS];
447 } wb; /* writeback */
450 /* Transmit Descriptor */
451 struct e1000_tx_desc {
452 __le64 buffer_addr; /* Address of the descriptor's data buffer */
456 __le16 length; /* Data buffer length */
457 u8 cso; /* Checksum offset */
458 u8 cmd; /* Descriptor control */
464 u8 status; /* Descriptor status */
465 u8 css; /* Checksum start */
471 /* Offload Context Descriptor */
472 struct e1000_context_desc {
476 u8 ipcss; /* IP checksum start */
477 u8 ipcso; /* IP checksum offset */
478 __le16 ipcse; /* IP checksum end */
484 u8 tucss; /* TCP checksum start */
485 u8 tucso; /* TCP checksum offset */
486 __le16 tucse; /* TCP checksum end */
489 __le32 cmd_and_length;
493 u8 status; /* Descriptor status */
494 u8 hdr_len; /* Header length */
495 __le16 mss; /* Maximum segment size */
500 /* Offload data descriptor */
501 struct e1000_data_desc {
502 __le64 buffer_addr; /* Address of the descriptor's buffer address */
506 __le16 length; /* Data buffer length */
514 u8 status; /* Descriptor status */
515 u8 popts; /* Packet Options */
521 /* Statistics counters collected by the MAC */
522 struct e1000_hw_stats {
605 struct e1000_vf_stats {
637 struct e1000_phy_stats {
642 struct e1000_host_mng_dhcp_cookie {
653 /* Host Interface "Rev 1" */
654 struct e1000_host_command_header {
661 #define E1000_HI_MAX_DATA_LENGTH 252
662 struct e1000_host_command_info {
663 struct e1000_host_command_header command_header;
664 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
667 /* Host Interface "Rev 2" */
668 struct e1000_host_mng_command_header {
676 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
677 struct e1000_host_mng_command_info {
678 struct e1000_host_mng_command_header command_header;
679 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
682 #include "e1000_mac.h"
683 #include "e1000_phy.h"
684 #include "e1000_nvm.h"
685 #include "e1000_manage.h"
686 #include "e1000_mbx.h"
688 /* Function pointers for the MAC. */
689 struct e1000_mac_operations {
690 s32 (*init_params)(struct e1000_hw *);
691 s32 (*id_led_init)(struct e1000_hw *);
692 s32 (*blink_led)(struct e1000_hw *);
693 bool (*check_mng_mode)(struct e1000_hw *);
694 s32 (*check_for_link)(struct e1000_hw *);
695 s32 (*cleanup_led)(struct e1000_hw *);
696 void (*clear_hw_cntrs)(struct e1000_hw *);
697 void (*clear_vfta)(struct e1000_hw *);
698 s32 (*get_bus_info)(struct e1000_hw *);
699 void (*set_lan_id)(struct e1000_hw *);
700 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
701 s32 (*led_on)(struct e1000_hw *);
702 s32 (*led_off)(struct e1000_hw *);
703 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
704 s32 (*reset_hw)(struct e1000_hw *);
705 s32 (*init_hw)(struct e1000_hw *);
706 void (*shutdown_serdes)(struct e1000_hw *);
707 void (*power_up_serdes)(struct e1000_hw *);
708 s32 (*setup_link)(struct e1000_hw *);
709 s32 (*setup_physical_interface)(struct e1000_hw *);
710 s32 (*setup_led)(struct e1000_hw *);
711 void (*write_vfta)(struct e1000_hw *, u32, u32);
712 void (*config_collision_dist)(struct e1000_hw *);
713 int (*rar_set)(struct e1000_hw *, u8*, u32);
714 s32 (*read_mac_addr)(struct e1000_hw *);
715 s32 (*validate_mdi_setting)(struct e1000_hw *);
716 s32 (*set_obff_timer)(struct e1000_hw *, u32);
717 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);
718 void (*release_swfw_sync)(struct e1000_hw *, u16);
721 /* When to use various PHY register access functions:
724 * Function Does Does When to use
725 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
726 * X_reg L,P,A n/a for simple PHY reg accesses
727 * X_reg_locked P,A L for multiple accesses of different regs
729 * X_reg_page A L,P for multiple accesses of different regs
732 * Where X=[read|write], L=locking, P=sets page, A=register access
735 struct e1000_phy_operations {
736 s32 (*init_params)(struct e1000_hw *);
737 s32 (*acquire)(struct e1000_hw *);
738 s32 (*cfg_on_link_up)(struct e1000_hw *);
739 s32 (*check_polarity)(struct e1000_hw *);
740 s32 (*check_reset_block)(struct e1000_hw *);
741 s32 (*commit)(struct e1000_hw *);
742 s32 (*force_speed_duplex)(struct e1000_hw *);
743 s32 (*get_cfg_done)(struct e1000_hw *hw);
744 s32 (*get_cable_length)(struct e1000_hw *);
745 s32 (*get_info)(struct e1000_hw *);
746 s32 (*set_page)(struct e1000_hw *, u16);
747 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
748 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
749 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
750 void (*release)(struct e1000_hw *);
751 s32 (*reset)(struct e1000_hw *);
752 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
753 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
754 s32 (*write_reg)(struct e1000_hw *, u32, u16);
755 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
756 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
757 void (*power_up)(struct e1000_hw *);
758 void (*power_down)(struct e1000_hw *);
759 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
760 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
763 /* Function pointers for the NVM. */
764 struct e1000_nvm_operations {
765 s32 (*init_params)(struct e1000_hw *);
766 s32 (*acquire)(struct e1000_hw *);
767 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
768 void (*release)(struct e1000_hw *);
769 void (*reload)(struct e1000_hw *);
770 s32 (*update)(struct e1000_hw *);
771 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
772 s32 (*validate)(struct e1000_hw *);
773 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
776 struct e1000_mac_info {
777 struct e1000_mac_operations ops;
778 u8 addr[ETH_ADDR_LEN];
779 u8 perm_addr[ETH_ADDR_LEN];
781 enum e1000_mac_type type;
799 /* Maximum size of the MTA register table in all supported adapters */
800 #define MAX_MTA_REG 128
801 u32 mta_shadow[MAX_MTA_REG];
804 u8 forced_speed_duplex;
808 bool arc_subsystem_valid;
809 bool asf_firmware_present;
812 bool get_link_status;
814 bool report_tx_early;
815 enum e1000_serdes_link_state serdes_link_state;
816 bool serdes_has_link;
817 bool tx_pkt_filtering;
821 struct e1000_phy_info {
822 struct e1000_phy_operations ops;
823 enum e1000_phy_type type;
825 enum e1000_1000t_rx_status local_rx;
826 enum e1000_1000t_rx_status remote_rx;
827 enum e1000_ms_type ms_type;
828 enum e1000_ms_type original_ms_type;
829 enum e1000_rev_polarity cable_polarity;
830 enum e1000_smart_speed smart_speed;
834 u32 reset_delay_us; /* in usec */
837 enum e1000_media_type media_type;
839 u16 autoneg_advertised;
842 u16 max_cable_length;
843 u16 min_cable_length;
847 bool disable_polarity_correction;
849 bool polarity_correction;
850 bool speed_downgraded;
851 bool autoneg_wait_to_complete;
854 struct e1000_nvm_info {
855 struct e1000_nvm_operations ops;
856 enum e1000_nvm_type type;
857 enum e1000_nvm_override override;
869 struct e1000_bus_info {
870 enum e1000_bus_type type;
871 enum e1000_bus_speed speed;
872 enum e1000_bus_width width;
878 struct e1000_fc_info {
879 u32 high_water; /* Flow control high-water mark */
880 u32 low_water; /* Flow control low-water mark */
881 u16 pause_time; /* Flow control pause timer */
882 u16 refresh_time; /* Flow control refresh timer */
883 bool send_xon; /* Flow control send XON */
884 bool strict_ieee; /* Strict IEEE mode */
885 enum e1000_fc_mode current_mode; /* FC mode in effect */
886 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
889 struct e1000_mbx_operations {
890 s32 (*init_params)(struct e1000_hw *hw);
891 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
892 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
893 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
894 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
895 s32 (*check_for_msg)(struct e1000_hw *, u16);
896 s32 (*check_for_ack)(struct e1000_hw *, u16);
897 s32 (*check_for_rst)(struct e1000_hw *, u16);
900 struct e1000_mbx_stats {
909 struct e1000_mbx_info {
910 struct e1000_mbx_operations ops;
911 struct e1000_mbx_stats stats;
917 struct e1000_dev_spec_82541 {
918 enum e1000_dsp_config dsp_config;
919 enum e1000_ffe_config ffe_config;
921 bool phy_init_script;
924 struct e1000_dev_spec_82542 {
928 struct e1000_dev_spec_82543 {
929 u32 tbi_compatibility;
931 bool init_phy_disabled;
934 struct e1000_dev_spec_82571 {
937 E1000_MUTEX swflag_mutex;
940 struct e1000_dev_spec_80003es2lan {
944 struct e1000_shadow_ram {
949 #define E1000_SHADOW_RAM_WORDS 2048
951 /* I218 PHY Ultra Low Power (ULP) states */
952 enum e1000_ulp_state {
953 e1000_ulp_state_unknown,
958 struct e1000_dev_spec_ich8lan {
959 bool kmrn_lock_loss_workaround_enabled;
960 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
961 E1000_MUTEX nvm_mutex;
962 E1000_MUTEX swflag_mutex;
967 enum e1000_ulp_state ulp_state;
968 bool ulp_capability_disabled;
969 bool during_suspend_flow;
970 bool during_dpg_exit;
973 struct e1000_dev_spec_82575 {
975 bool global_device_reset;
978 bool clear_semaphore_once;
980 struct sfp_e1000_flags eth_flags;
985 struct e1000_dev_spec_vf {
995 unsigned long io_base;
997 struct e1000_mac_info mac;
998 struct e1000_fc_info fc;
999 struct e1000_phy_info phy;
1000 struct e1000_nvm_info nvm;
1001 struct e1000_bus_info bus;
1002 struct e1000_mbx_info mbx;
1003 struct e1000_host_mng_dhcp_cookie mng_cookie;
1006 struct e1000_dev_spec_82541 _82541;
1007 struct e1000_dev_spec_82542 _82542;
1008 struct e1000_dev_spec_82543 _82543;
1009 struct e1000_dev_spec_82571 _82571;
1010 struct e1000_dev_spec_80003es2lan _80003es2lan;
1011 struct e1000_dev_spec_ich8lan ich8lan;
1012 struct e1000_dev_spec_82575 _82575;
1013 struct e1000_dev_spec_vf vf;
1017 u16 subsystem_vendor_id;
1018 u16 subsystem_device_id;
1024 #include "e1000_82541.h"
1025 #include "e1000_82543.h"
1026 #include "e1000_82571.h"
1027 #include "e1000_80003es2lan.h"
1028 #include "e1000_ich8lan.h"
1029 #include "e1000_82575.h"
1030 #include "e1000_i210.h"
1032 /* These functions must be implemented by drivers */
1033 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1034 void e1000_pci_set_mwi(struct e1000_hw *hw);
1035 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1036 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1037 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1038 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);