1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2015, Intel Corporation
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8 modification, are permitted provided that the following conditions are met:
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33 ******************************************************************************/
36 #include "e1000_api.h"
39 static s32 e1000_acquire_nvm_i210(struct e1000_hw *hw);
40 static void e1000_release_nvm_i210(struct e1000_hw *hw);
41 static s32 e1000_get_hw_semaphore_i210(struct e1000_hw *hw);
42 static s32 e1000_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words,
44 static s32 e1000_pool_flash_update_done_i210(struct e1000_hw *hw);
45 static s32 e1000_valid_led_default_i210(struct e1000_hw *hw, u16 *data);
48 * e1000_acquire_nvm_i210 - Request for access to EEPROM
49 * @hw: pointer to the HW structure
51 * Acquire the necessary semaphores for exclusive access to the EEPROM.
52 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
53 * Return successful if access grant bit set, else clear the request for
54 * EEPROM access and return -E1000_ERR_NVM (-1).
56 static s32 e1000_acquire_nvm_i210(struct e1000_hw *hw)
60 DEBUGFUNC("e1000_acquire_nvm_i210");
62 ret_val = e1000_acquire_swfw_sync_i210(hw, E1000_SWFW_EEP_SM);
68 * e1000_release_nvm_i210 - Release exclusive access to EEPROM
69 * @hw: pointer to the HW structure
71 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
72 * then release the semaphores acquired.
74 static void e1000_release_nvm_i210(struct e1000_hw *hw)
76 DEBUGFUNC("e1000_release_nvm_i210");
78 e1000_release_swfw_sync_i210(hw, E1000_SWFW_EEP_SM);
82 * e1000_acquire_swfw_sync_i210 - Acquire SW/FW semaphore
83 * @hw: pointer to the HW structure
84 * @mask: specifies which semaphore to acquire
86 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
87 * will also specify which port we're acquiring the lock for.
89 s32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask)
93 u32 fwmask = mask << 16;
94 s32 ret_val = E1000_SUCCESS;
95 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
97 DEBUGFUNC("e1000_acquire_swfw_sync_i210");
100 if (e1000_get_hw_semaphore_i210(hw)) {
101 ret_val = -E1000_ERR_SWFW_SYNC;
105 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
106 if (!(swfw_sync & (fwmask | swmask)))
110 * Firmware currently using resource (fwmask)
111 * or other software thread using resource (swmask)
113 e1000_put_hw_semaphore_generic(hw);
119 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
120 ret_val = -E1000_ERR_SWFW_SYNC;
125 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
127 e1000_put_hw_semaphore_generic(hw);
134 * e1000_release_swfw_sync_i210 - Release SW/FW semaphore
135 * @hw: pointer to the HW structure
136 * @mask: specifies which semaphore to acquire
138 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
139 * will also specify which port we're releasing the lock for.
141 void e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask)
145 DEBUGFUNC("e1000_release_swfw_sync_i210");
147 while (e1000_get_hw_semaphore_i210(hw) != E1000_SUCCESS)
150 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
152 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
154 e1000_put_hw_semaphore_generic(hw);
158 * e1000_get_hw_semaphore_i210 - Acquire hardware semaphore
159 * @hw: pointer to the HW structure
161 * Acquire the HW semaphore to access the PHY or NVM
163 static s32 e1000_get_hw_semaphore_i210(struct e1000_hw *hw)
166 s32 timeout = hw->nvm.word_size + 1;
169 DEBUGFUNC("e1000_get_hw_semaphore_i210");
171 /* Get the SW semaphore */
172 while (i < timeout) {
173 swsm = E1000_READ_REG(hw, E1000_SWSM);
174 if (!(swsm & E1000_SWSM_SMBI))
182 /* In rare circumstances, the SW semaphore may already be held
183 * unintentionally. Clear the semaphore once before giving up.
185 if (hw->dev_spec._82575.clear_semaphore_once) {
186 hw->dev_spec._82575.clear_semaphore_once = FALSE;
187 e1000_put_hw_semaphore_generic(hw);
188 for (i = 0; i < timeout; i++) {
189 swsm = E1000_READ_REG(hw, E1000_SWSM);
190 if (!(swsm & E1000_SWSM_SMBI))
197 /* If we do not have the semaphore here, we have to give up. */
199 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
200 return -E1000_ERR_NVM;
204 /* Get the FW semaphore. */
205 for (i = 0; i < timeout; i++) {
206 swsm = E1000_READ_REG(hw, E1000_SWSM);
207 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
209 /* Semaphore acquired if bit latched */
210 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
217 /* Release semaphores */
218 e1000_put_hw_semaphore_generic(hw);
219 DEBUGOUT("Driver can't access the NVM\n");
220 return -E1000_ERR_NVM;
223 return E1000_SUCCESS;
227 * e1000_read_nvm_srrd_i210 - Reads Shadow Ram using EERD register
228 * @hw: pointer to the HW structure
229 * @offset: offset of word in the Shadow Ram to read
230 * @words: number of words to read
231 * @data: word read from the Shadow Ram
233 * Reads a 16 bit word from the Shadow Ram using the EERD register.
234 * Uses necessary synchronization semaphores.
236 s32 e1000_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words,
239 s32 status = E1000_SUCCESS;
242 DEBUGFUNC("e1000_read_nvm_srrd_i210");
244 /* We cannot hold synchronization semaphores for too long,
245 * because of forceful takeover procedure. However it is more efficient
246 * to read in bursts than synchronizing access for each word. */
247 for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {
248 count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?
249 E1000_EERD_EEWR_MAX_COUNT : (words - i);
250 if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
251 status = e1000_read_nvm_eerd(hw, offset, count,
253 hw->nvm.ops.release(hw);
255 status = E1000_ERR_SWFW_SYNC;
258 if (status != E1000_SUCCESS)
266 * e1000_write_nvm_srwr_i210 - Write to Shadow RAM using EEWR
267 * @hw: pointer to the HW structure
268 * @offset: offset within the Shadow RAM to be written to
269 * @words: number of words to write
270 * @data: 16 bit word(s) to be written to the Shadow RAM
272 * Writes data to Shadow RAM at offset using EEWR register.
274 * If e1000_update_nvm_checksum is not called after this function , the
275 * data will not be committed to FLASH and also Shadow RAM will most likely
276 * contain an invalid checksum.
278 * If error code is returned, data and Shadow RAM may be inconsistent - buffer
281 s32 e1000_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words,
284 s32 status = E1000_SUCCESS;
287 DEBUGFUNC("e1000_write_nvm_srwr_i210");
289 /* We cannot hold synchronization semaphores for too long,
290 * because of forceful takeover procedure. However it is more efficient
291 * to write in bursts than synchronizing access for each word. */
292 for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {
293 count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?
294 E1000_EERD_EEWR_MAX_COUNT : (words - i);
295 if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
296 status = e1000_write_nvm_srwr(hw, offset, count,
298 hw->nvm.ops.release(hw);
300 status = E1000_ERR_SWFW_SYNC;
303 if (status != E1000_SUCCESS)
311 * e1000_write_nvm_srwr - Write to Shadow Ram using EEWR
312 * @hw: pointer to the HW structure
313 * @offset: offset within the Shadow Ram to be written to
314 * @words: number of words to write
315 * @data: 16 bit word(s) to be written to the Shadow Ram
317 * Writes data to Shadow Ram at offset using EEWR register.
319 * If e1000_update_nvm_checksum is not called after this function , the
320 * Shadow Ram will most likely contain an invalid checksum.
322 static s32 e1000_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words,
325 struct e1000_nvm_info *nvm = &hw->nvm;
327 u32 attempts = 100000;
328 s32 ret_val = E1000_SUCCESS;
330 DEBUGFUNC("e1000_write_nvm_srwr");
333 * A check for invalid values: offset too large, too many words,
334 * too many words for the offset, and not enough words.
336 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
338 DEBUGOUT("nvm parameter(s) out of bounds\n");
339 ret_val = -E1000_ERR_NVM;
343 for (i = 0; i < words; i++) {
344 eewr = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
345 (data[i] << E1000_NVM_RW_REG_DATA) |
346 E1000_NVM_RW_REG_START;
348 E1000_WRITE_REG(hw, E1000_SRWR, eewr);
350 for (k = 0; k < attempts; k++) {
351 if (E1000_NVM_RW_REG_DONE &
352 E1000_READ_REG(hw, E1000_SRWR)) {
353 ret_val = E1000_SUCCESS;
359 if (ret_val != E1000_SUCCESS) {
360 DEBUGOUT("Shadow RAM write EEWR timed out\n");
369 /** e1000_read_invm_word_i210 - Reads OTP
370 * @hw: pointer to the HW structure
371 * @address: the word address (aka eeprom offset) to read
372 * @data: pointer to the data read
374 * Reads 16-bit words from the OTP. Return error when the word is not
377 static s32 e1000_read_invm_word_i210(struct e1000_hw *hw, u8 address, u16 *data)
379 s32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND;
382 u8 record_type, word_address;
384 DEBUGFUNC("e1000_read_invm_word_i210");
386 for (i = 0; i < E1000_INVM_SIZE; i++) {
387 invm_dword = E1000_READ_REG(hw, E1000_INVM_DATA_REG(i));
388 /* Get record type */
389 record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword);
390 if (record_type == E1000_INVM_UNINITIALIZED_STRUCTURE)
392 if (record_type == E1000_INVM_CSR_AUTOLOAD_STRUCTURE)
393 i += E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS;
394 if (record_type == E1000_INVM_RSA_KEY_SHA256_STRUCTURE)
395 i += E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS;
396 if (record_type == E1000_INVM_WORD_AUTOLOAD_STRUCTURE) {
397 word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword);
398 if (word_address == address) {
399 *data = INVM_DWORD_TO_WORD_DATA(invm_dword);
400 DEBUGOUT2("Read INVM Word 0x%02x = %x",
402 status = E1000_SUCCESS;
407 if (status != E1000_SUCCESS)
408 DEBUGOUT1("Requested word 0x%02x not found in OTP\n", address);
412 /** e1000_read_invm_i210 - Read invm wrapper function for I210/I211
413 * @hw: pointer to the HW structure
414 * @address: the word address (aka eeprom offset) to read
415 * @data: pointer to the data read
417 * Wrapper function to return data formerly found in the NVM.
419 static s32 e1000_read_invm_i210(struct e1000_hw *hw, u16 offset,
420 u16 E1000_UNUSEDARG words, u16 *data)
422 s32 ret_val = E1000_SUCCESS;
424 DEBUGFUNC("e1000_read_invm_i210");
426 /* Only the MAC addr is required to be present in the iNVM */
429 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, &data[0]);
430 ret_val |= e1000_read_invm_word_i210(hw, (u8)offset+1,
432 ret_val |= e1000_read_invm_word_i210(hw, (u8)offset+2,
434 if (ret_val != E1000_SUCCESS)
435 DEBUGOUT("MAC Addr not found in iNVM\n");
437 case NVM_INIT_CTRL_2:
438 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
439 if (ret_val != E1000_SUCCESS) {
440 *data = NVM_INIT_CTRL_2_DEFAULT_I211;
441 ret_val = E1000_SUCCESS;
444 case NVM_INIT_CTRL_4:
445 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
446 if (ret_val != E1000_SUCCESS) {
447 *data = NVM_INIT_CTRL_4_DEFAULT_I211;
448 ret_val = E1000_SUCCESS;
452 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
453 if (ret_val != E1000_SUCCESS) {
454 *data = NVM_LED_1_CFG_DEFAULT_I211;
455 ret_val = E1000_SUCCESS;
458 case NVM_LED_0_2_CFG:
459 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
460 if (ret_val != E1000_SUCCESS) {
461 *data = NVM_LED_0_2_CFG_DEFAULT_I211;
462 ret_val = E1000_SUCCESS;
465 case NVM_ID_LED_SETTINGS:
466 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
467 if (ret_val != E1000_SUCCESS) {
468 *data = ID_LED_RESERVED_FFFF;
469 ret_val = E1000_SUCCESS;
473 *data = hw->subsystem_device_id;
476 *data = hw->subsystem_vendor_id;
479 *data = hw->device_id;
482 *data = hw->vendor_id;
485 DEBUGOUT1("NVM word 0x%02x is not mapped.\n", offset);
486 *data = NVM_RESERVED_WORD;
493 * e1000_validate_nvm_checksum_i210 - Validate EEPROM checksum
494 * @hw: pointer to the HW structure
496 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
497 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
499 s32 e1000_validate_nvm_checksum_i210(struct e1000_hw *hw)
501 s32 status = E1000_SUCCESS;
502 s32 (*read_op_ptr)(struct e1000_hw *, u16, u16, u16 *);
504 DEBUGFUNC("e1000_validate_nvm_checksum_i210");
506 if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
509 * Replace the read function with semaphore grabbing with
510 * the one that skips this for a while.
511 * We have semaphore taken already here.
513 read_op_ptr = hw->nvm.ops.read;
514 hw->nvm.ops.read = e1000_read_nvm_eerd;
516 status = e1000_validate_nvm_checksum_generic(hw);
518 /* Revert original read operation. */
519 hw->nvm.ops.read = read_op_ptr;
521 hw->nvm.ops.release(hw);
523 status = E1000_ERR_SWFW_SYNC;
531 * e1000_update_nvm_checksum_i210 - Update EEPROM checksum
532 * @hw: pointer to the HW structure
534 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
535 * up to the checksum. Then calculates the EEPROM checksum and writes the
536 * value to the EEPROM. Next commit EEPROM data onto the Flash.
538 s32 e1000_update_nvm_checksum_i210(struct e1000_hw *hw)
544 DEBUGFUNC("e1000_update_nvm_checksum_i210");
547 * Read the first word from the EEPROM. If this times out or fails, do
548 * not continue or we could be in for a very long wait while every
551 ret_val = e1000_read_nvm_eerd(hw, 0, 1, &nvm_data);
552 if (ret_val != E1000_SUCCESS) {
553 DEBUGOUT("EEPROM read failed\n");
557 if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
559 * Do not use hw->nvm.ops.write, hw->nvm.ops.read
560 * because we do not want to take the synchronization
561 * semaphores twice here.
564 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
565 ret_val = e1000_read_nvm_eerd(hw, i, 1, &nvm_data);
567 hw->nvm.ops.release(hw);
568 DEBUGOUT("NVM Read Error while updating checksum.\n");
571 checksum += nvm_data;
573 checksum = (u16) NVM_SUM - checksum;
574 ret_val = e1000_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1,
576 if (ret_val != E1000_SUCCESS) {
577 hw->nvm.ops.release(hw);
578 DEBUGOUT("NVM Write Error while updating checksum.\n");
582 hw->nvm.ops.release(hw);
584 ret_val = e1000_update_flash_i210(hw);
586 ret_val = E1000_ERR_SWFW_SYNC;
593 * e1000_get_flash_presence_i210 - Check if flash device is detected.
594 * @hw: pointer to the HW structure
597 bool e1000_get_flash_presence_i210(struct e1000_hw *hw)
600 bool ret_val = FALSE;
602 DEBUGFUNC("e1000_get_flash_presence_i210");
604 eec = E1000_READ_REG(hw, E1000_EECD);
606 if (eec & E1000_EECD_FLASH_DETECTED_I210)
613 * e1000_update_flash_i210 - Commit EEPROM to the flash
614 * @hw: pointer to the HW structure
617 s32 e1000_update_flash_i210(struct e1000_hw *hw)
622 DEBUGFUNC("e1000_update_flash_i210");
624 ret_val = e1000_pool_flash_update_done_i210(hw);
625 if (ret_val == -E1000_ERR_NVM) {
626 DEBUGOUT("Flash update time out\n");
630 flup = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD_I210;
631 E1000_WRITE_REG(hw, E1000_EECD, flup);
633 ret_val = e1000_pool_flash_update_done_i210(hw);
634 if (ret_val == E1000_SUCCESS)
635 DEBUGOUT("Flash update complete\n");
637 DEBUGOUT("Flash update time out\n");
644 * e1000_pool_flash_update_done_i210 - Pool FLUDONE status.
645 * @hw: pointer to the HW structure
648 s32 e1000_pool_flash_update_done_i210(struct e1000_hw *hw)
650 s32 ret_val = -E1000_ERR_NVM;
653 DEBUGFUNC("e1000_pool_flash_update_done_i210");
655 for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
656 reg = E1000_READ_REG(hw, E1000_EECD);
657 if (reg & E1000_EECD_FLUDONE_I210) {
658 ret_val = E1000_SUCCESS;
668 * e1000_init_nvm_params_i210 - Initialize i210 NVM function pointers
669 * @hw: pointer to the HW structure
671 * Initialize the i210/i211 NVM parameters and function pointers.
673 static s32 e1000_init_nvm_params_i210(struct e1000_hw *hw)
676 struct e1000_nvm_info *nvm = &hw->nvm;
678 DEBUGFUNC("e1000_init_nvm_params_i210");
680 ret_val = e1000_init_nvm_params_82575(hw);
681 nvm->ops.acquire = e1000_acquire_nvm_i210;
682 nvm->ops.release = e1000_release_nvm_i210;
683 nvm->ops.valid_led_default = e1000_valid_led_default_i210;
684 if (e1000_get_flash_presence_i210(hw)) {
685 hw->nvm.type = e1000_nvm_flash_hw;
686 nvm->ops.read = e1000_read_nvm_srrd_i210;
687 nvm->ops.write = e1000_write_nvm_srwr_i210;
688 nvm->ops.validate = e1000_validate_nvm_checksum_i210;
689 nvm->ops.update = e1000_update_nvm_checksum_i210;
691 hw->nvm.type = e1000_nvm_invm;
692 nvm->ops.read = e1000_read_invm_i210;
693 nvm->ops.write = e1000_null_write_nvm;
694 nvm->ops.validate = e1000_null_ops_generic;
695 nvm->ops.update = e1000_null_ops_generic;
701 * e1000_init_function_pointers_i210 - Init func ptrs.
702 * @hw: pointer to the HW structure
704 * Called to initialize all function pointers and parameters.
706 void e1000_init_function_pointers_i210(struct e1000_hw *hw)
708 e1000_init_function_pointers_82575(hw);
709 hw->nvm.ops.init_params = e1000_init_nvm_params_i210;
715 * e1000_valid_led_default_i210 - Verify a valid default LED config
716 * @hw: pointer to the HW structure
717 * @data: pointer to the NVM (EEPROM)
719 * Read the EEPROM for the current default LED configuration. If the
720 * LED configuration is not valid, set to a valid LED configuration.
722 static s32 e1000_valid_led_default_i210(struct e1000_hw *hw, u16 *data)
726 DEBUGFUNC("e1000_valid_led_default_i210");
728 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
730 DEBUGOUT("NVM Read Error\n");
734 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
735 switch (hw->phy.media_type) {
736 case e1000_media_type_internal_serdes:
737 *data = ID_LED_DEFAULT_I210_SERDES;
739 case e1000_media_type_copper:
741 *data = ID_LED_DEFAULT_I210;
750 * __e1000_access_xmdio_reg - Read/write XMDIO register
751 * @hw: pointer to the HW structure
752 * @address: XMDIO address to program
753 * @dev_addr: device address to program
754 * @data: pointer to value to read/write from/to the XMDIO address
755 * @read: boolean flag to indicate read or write
757 static s32 __e1000_access_xmdio_reg(struct e1000_hw *hw, u16 address,
758 u8 dev_addr, u16 *data, bool read)
762 DEBUGFUNC("__e1000_access_xmdio_reg");
764 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);
768 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address);
772 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA |
778 ret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data);
780 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data);
784 /* Recalibrate the device back to 0 */
785 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0);
793 * e1000_read_xmdio_reg - Read XMDIO register
794 * @hw: pointer to the HW structure
795 * @addr: XMDIO address to program
796 * @dev_addr: device address to program
797 * @data: value to be read from the EMI address
799 s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data)
801 DEBUGFUNC("e1000_read_xmdio_reg");
803 return __e1000_access_xmdio_reg(hw, addr, dev_addr, data, TRUE);
807 * e1000_write_xmdio_reg - Write XMDIO register
808 * @hw: pointer to the HW structure
809 * @addr: XMDIO address to program
810 * @dev_addr: device address to program
811 * @data: value to be written to the XMDIO address
813 s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data)
815 DEBUGFUNC("e1000_read_xmdio_reg");
817 return __e1000_access_xmdio_reg(hw, addr, dev_addr, &data, FALSE);
821 * e1000_pll_workaround_i210
822 * @hw: pointer to the HW structure
824 * Works around an errata in the PLL circuit where it occasionally
825 * provides the wrong clock frequency after power up.
827 static s32 e1000_pll_workaround_i210(struct e1000_hw *hw)
830 u32 wuc, mdicnfg, ctrl, ctrl_ext, reg_val;
831 u16 nvm_word, phy_word, pci_word, tmp_nvm;
834 /* Get and set needed register values */
835 wuc = E1000_READ_REG(hw, E1000_WUC);
836 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
837 reg_val = mdicnfg & ~E1000_MDICNFG_EXT_MDIO;
838 E1000_WRITE_REG(hw, E1000_MDICNFG, reg_val);
840 /* Get data from NVM, or set default */
841 ret_val = e1000_read_invm_word_i210(hw, E1000_INVM_AUTOLOAD,
843 if (ret_val != E1000_SUCCESS)
844 nvm_word = E1000_INVM_DEFAULT_AL;
845 tmp_nvm = nvm_word | E1000_INVM_PLL_WO_VAL;
846 for (i = 0; i < E1000_MAX_PLL_TRIES; i++) {
847 /* check current state directly from internal PHY */
848 e1000_read_phy_reg_gs40g(hw, (E1000_PHY_PLL_FREQ_PAGE |
849 E1000_PHY_PLL_FREQ_REG), &phy_word);
850 if ((phy_word & E1000_PHY_PLL_UNCONF)
851 != E1000_PHY_PLL_UNCONF) {
852 ret_val = E1000_SUCCESS;
855 ret_val = -E1000_ERR_PHY;
857 /* directly reset the internal PHY */
858 ctrl = E1000_READ_REG(hw, E1000_CTRL);
859 E1000_WRITE_REG(hw, E1000_CTRL, ctrl|E1000_CTRL_PHY_RST);
861 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
862 ctrl_ext |= (E1000_CTRL_EXT_PHYPDEN | E1000_CTRL_EXT_SDLPE);
863 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
865 E1000_WRITE_REG(hw, E1000_WUC, 0);
866 reg_val = (E1000_INVM_AUTOLOAD << 4) | (tmp_nvm << 16);
867 E1000_WRITE_REG(hw, E1000_EEARBC_I210, reg_val);
869 e1000_read_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word);
870 pci_word |= E1000_PCI_PMCSR_D3;
871 e1000_write_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word);
873 pci_word &= ~E1000_PCI_PMCSR_D3;
874 e1000_write_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word);
875 reg_val = (E1000_INVM_AUTOLOAD << 4) | (nvm_word << 16);
876 E1000_WRITE_REG(hw, E1000_EEARBC_I210, reg_val);
878 /* restore WUC register */
879 E1000_WRITE_REG(hw, E1000_WUC, wuc);
881 /* restore MDICNFG setting */
882 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
887 * e1000_get_cfg_done_i210 - Read config done bit
888 * @hw: pointer to the HW structure
890 * Read the management control register for the config done bit for
891 * completion status. NOTE: silicon which is EEPROM-less will fail trying
892 * to read the config done bit, so an error is *ONLY* logged and returns
893 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
894 * would not be able to be reset or change link.
896 static s32 e1000_get_cfg_done_i210(struct e1000_hw *hw)
898 s32 timeout = PHY_CFG_TIMEOUT;
899 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
901 DEBUGFUNC("e1000_get_cfg_done_i210");
904 if (E1000_READ_REG(hw, E1000_EEMNGCTL_I210) & mask)
910 DEBUGOUT("MNG configuration cycle has not completed.\n");
912 return E1000_SUCCESS;
916 * e1000_init_hw_i210 - Init hw for I210/I211
917 * @hw: pointer to the HW structure
919 * Called to initialize hw for i210 hw family.
921 s32 e1000_init_hw_i210(struct e1000_hw *hw)
925 DEBUGFUNC("e1000_init_hw_i210");
926 if ((hw->mac.type >= e1000_i210) &&
927 !(e1000_get_flash_presence_i210(hw))) {
928 ret_val = e1000_pll_workaround_i210(hw);
929 if (ret_val != E1000_SUCCESS)
932 hw->phy.ops.get_cfg_done = e1000_get_cfg_done_i210;
933 ret_val = e1000_init_hw_82575(hw);