sys/dev/e1000/e1000_ich8lan.c

   1 /******************************************************************************
   2   SPDX-License-Identifier: BSD-3-Clause
   3
   4   Copyright (c) 2001-2015, Intel Corporation
   5   All rights reserved.
   6
   7   Redistribution and use in source and binary forms, with or without
   8   modification, are permitted provided that the following conditions are met:
   9
  10    1. Redistributions of source code must retain the above copyright notice,
  11       this list of conditions and the following disclaimer.
  12
  13    2. Redistributions in binary form must reproduce the above copyright
  14       notice, this list of conditions and the following disclaimer in the
  15       documentation and/or other materials provided with the distribution.
  16
  17    3. Neither the name of the Intel Corporation nor the names of its
  18       contributors may be used to endorse or promote products derived from
  19       this software without specific prior written permission.
  20
  21   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31   POSSIBILITY OF SUCH DAMAGE.
  32
  33 ******************************************************************************/
  34 /*$FreeBSD$*/
  35
  36 /* 82562G 10/100 Network Connection
  37  * 82562G-2 10/100 Network Connection
  38  * 82562GT 10/100 Network Connection
  39  * 82562GT-2 10/100 Network Connection
  40  * 82562V 10/100 Network Connection
  41  * 82562V-2 10/100 Network Connection
  42  * 82566DC-2 Gigabit Network Connection
  43  * 82566DC Gigabit Network Connection
  44  * 82566DM-2 Gigabit Network Connection
  45  * 82566DM Gigabit Network Connection
  46  * 82566MC Gigabit Network Connection
  47  * 82566MM Gigabit Network Connection
  48  * 82567LM Gigabit Network Connection
  49  * 82567LF Gigabit Network Connection
  50  * 82567V Gigabit Network Connection
  51  * 82567LM-2 Gigabit Network Connection
  52  * 82567LF-2 Gigabit Network Connection
  53  * 82567V-2 Gigabit Network Connection
  54  * 82567LF-3 Gigabit Network Connection
  55  * 82567LM-3 Gigabit Network Connection
  56  * 82567LM-4 Gigabit Network Connection
  57  * 82577LM Gigabit Network Connection
  58  * 82577LC Gigabit Network Connection
  59  * 82578DM Gigabit Network Connection
  60  * 82578DC Gigabit Network Connection
  61  * 82579LM Gigabit Network Connection
  62  * 82579V Gigabit Network Connection
  63  * Ethernet Connection I217-LM
  64  * Ethernet Connection I217-V
  65  * Ethernet Connection I218-V
  66  * Ethernet Connection I218-LM
  67  * Ethernet Connection (2) I218-LM
  68  * Ethernet Connection (2) I218-V
  69  * Ethernet Connection (3) I218-LM
  70  * Ethernet Connection (3) I218-V
  71  */
  72
  73 #include "e1000_api.h"
  74
  75 static s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
  76 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
  77 static s32  e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
  78 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
  79 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
  80 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
  81 static int  e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
  82 static int  e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
  83 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
  84 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
  85                                               u8 *mc_addr_list,
  86                                               u32 mc_addr_count);
  87 static s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
  88 static s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
  89 static s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
  90 static s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
  91                                             bool active);
  92 static s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
  93                                             bool active);
  94 static s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  95                                    u16 words, u16 *data);
  96 static s32  e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
  97                                u16 *data);
  98 static s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  99                                     u16 words, u16 *data);
 100 static s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
 101 static s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
 102 static s32  e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
 103 static s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
 104                                             u16 *data);
 105 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 106 static s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
 107 static s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
 108 static s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
 109 static s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
 110 static s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 111 static s32  e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 112 static s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
 113                                            u16 *speed, u16 *duplex);
 114 static s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 115 static s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
 116 static s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
 117 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 118 static s32  e1000_setup_led_pchlan(struct e1000_hw *hw);
 119 static s32  e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 120 static s32  e1000_led_on_pchlan(struct e1000_hw *hw);
 121 static s32  e1000_led_off_pchlan(struct e1000_hw *hw);
 122 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 123 static s32  e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 124 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 125 static s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 126 static s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
 127                                           u32 offset, u8 *data);
 128 static s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 129                                           u8 size, u16 *data);
 130 static s32  e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
 131                                             u32 *data);
 132 static s32  e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
 133                                            u32 offset, u32 *data);
 134 static s32  e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
 135                                              u32 offset, u32 data);
 136 static s32  e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
 137                                                   u32 offset, u32 dword);
 138 static s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
 139                                           u32 offset, u16 *data);
 140 static s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 141                                                  u32 offset, u8 byte);
 142 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 143 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 144 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
 145 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 146 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 147 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 148 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr);
 149
 150 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 151 /* Offset 04h HSFSTS */
 152 union ich8_hws_flash_status {
 153         struct ich8_hsfsts {
 154                 u16 flcdone:1; /* bit 0 Flash Cycle Done */
 155                 u16 flcerr:1; /* bit 1 Flash Cycle Error */
 156                 u16 dael:1; /* bit 2 Direct Access error Log */
 157                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
 158                 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
 159                 u16 reserved1:2; /* bit 13:6 Reserved */
 160                 u16 reserved2:6; /* bit 13:6 Reserved */
 161                 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
 162                 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
 163         } hsf_status;
 164         u16 regval;
 165 };
 166
 167 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 168 /* Offset 06h FLCTL */
 169 union ich8_hws_flash_ctrl {
 170         struct ich8_hsflctl {
 171                 u16 flcgo:1;   /* 0 Flash Cycle Go */
 172                 u16 flcycle:2;   /* 2:1 Flash Cycle */
 173                 u16 reserved:5;   /* 7:3 Reserved  */
 174                 u16 fldbcount:2;   /* 9:8 Flash Data Byte Count */
 175                 u16 flockdn:6;   /* 15:10 Reserved */
 176         } hsf_ctrl;
 177         u16 regval;
 178 };
 179
 180 /* ICH Flash Region Access Permissions */
 181 union ich8_hws_flash_regacc {
 182         struct ich8_flracc {
 183                 u32 grra:8; /* 0:7 GbE region Read Access */
 184                 u32 grwa:8; /* 8:15 GbE region Write Access */
 185                 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
 186                 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
 187         } hsf_flregacc;
 188         u16 regval;
 189 };
 190
 191 /**
 192  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 193  *  @hw: pointer to the HW structure
 194  *
 195  *  Test access to the PHY registers by reading the PHY ID registers.  If
 196  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 197  *  otherwise assume the read PHY ID is correct if it is valid.
 198  *
 199  *  Assumes the sw/fw/hw semaphore is already acquired.
 200  **/
 201 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 202 {
 203         u16 phy_reg = 0;
 204         u32 phy_id = 0;
 205         s32 ret_val = 0;
 206         u16 retry_count;
 207         u32 mac_reg = 0;
 208
 209         for (retry_count = 0; retry_count < 2; retry_count++) {
 210                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
 211                 if (ret_val || (phy_reg == 0xFFFF))
 212                         continue;
 213                 phy_id = (u32)(phy_reg << 16);
 214
 215                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
 216                 if (ret_val || (phy_reg == 0xFFFF)) {
 217                         phy_id = 0;
 218                         continue;
 219                 }
 220                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 221                 break;
 222         }
 223
 224         if (hw->phy.id) {
 225                 if  (hw->phy.id == phy_id)
 226                         goto out;
 227         } else if (phy_id) {
 228                 hw->phy.id = phy_id;
 229                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 230                 goto out;
 231         }
 232
 233         /* In case the PHY needs to be in mdio slow mode,
 234          * set slow mode and try to get the PHY id again.
 235          */
 236         if (hw->mac.type < e1000_pch_lpt) {
 237                 hw->phy.ops.release(hw);
 238                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 239                 if (!ret_val)
 240                         ret_val = e1000_get_phy_id(hw);
 241                 hw->phy.ops.acquire(hw);
 242         }
 243
 244         if (ret_val)
 245                 return FALSE;
 246 out:
 247         if (hw->mac.type >= e1000_pch_lpt) {
 248                 /* Only unforce SMBus if ME is not active */
 249                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
 250                     E1000_ICH_FWSM_FW_VALID)) {
 251                         /* Unforce SMBus mode in PHY */
 252                         hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
 253                         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 254                         hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
 255
 256                         /* Unforce SMBus mode in MAC */
 257                         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 258                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 259                         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 260                 }
 261         }
 262
 263         return TRUE;
 264 }
 265
 266 /**
 267  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 268  *  @hw: pointer to the HW structure
 269  *
 270  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 271  *  used to reset the PHY to a quiescent state when necessary.
 272  **/
 273 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 274 {
 275         u32 mac_reg;
 276
 277         DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
 278
 279         /* Set Phy Config Counter to 50msec */
 280         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
 281         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 282         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 283         E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
 284
 285         /* Toggle LANPHYPC Value bit */
 286         mac_reg = E1000_READ_REG(hw, E1000_CTRL);
 287         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 288         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 289         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 290         E1000_WRITE_FLUSH(hw);
 291         msec_delay(1);
 292         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 293         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 294         E1000_WRITE_FLUSH(hw);
 295
 296         if (hw->mac.type < e1000_pch_lpt) {
 297                 msec_delay(50);
 298         } else {
 299                 u16 count = 20;
 300
 301                 do {
 302                         msec_delay(5);
 303                 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
 304                            E1000_CTRL_EXT_LPCD) && count--);
 305
 306                 msec_delay(30);
 307         }
 308 }
 309
 310 /**
 311  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 312  *  @hw: pointer to the HW structure
 313  *
 314  *  Workarounds/flow necessary for PHY initialization during driver load
 315  *  and resume paths.
 316  **/
 317 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 318 {
 319         u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
 320         s32 ret_val;
 321
 322         DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
 323
 324         /* Gate automatic PHY configuration by hardware on managed and
 325          * non-managed 82579 and newer adapters.
 326          */
 327         e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
 328
 329         /* It is not possible to be certain of the current state of ULP
 330          * so forcibly disable it.
 331          */
 332         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 333         e1000_disable_ulp_lpt_lp(hw, TRUE);
 334
 335         ret_val = hw->phy.ops.acquire(hw);
 336         if (ret_val) {
 337                 DEBUGOUT("Failed to initialize PHY flow\n");
 338                 goto out;
 339         }
 340
 341         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 342          * inaccessible and resetting the PHY is not blocked, toggle the
 343          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 344          */
 345         switch (hw->mac.type) {
 346         case e1000_pch_lpt:
 347         case e1000_pch_spt:
 348         case e1000_pch_cnp:
 349                 if (e1000_phy_is_accessible_pchlan(hw))
 350                         break;
 351
 352                 /* Before toggling LANPHYPC, see if PHY is accessible by
 353                  * forcing MAC to SMBus mode first.
 354                  */
 355                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 356                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 357                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 358
 359                 /* Wait 50 milliseconds for MAC to finish any retries
 360                  * that it might be trying to perform from previous
 361                  * attempts to acknowledge any phy read requests.
 362                  */
 363                  msec_delay(50);
 364
 365                 /* fall-through */
 366         case e1000_pch2lan:
 367                 if (e1000_phy_is_accessible_pchlan(hw))
 368                         break;
 369
 370                 /* fall-through */
 371         case e1000_pchlan:
 372                 if ((hw->mac.type == e1000_pchlan) &&
 373                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 374                         break;
 375
 376                 if (hw->phy.ops.check_reset_block(hw)) {
 377                         DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
 378                         ret_val = -E1000_ERR_PHY;
 379                         break;
 380                 }
 381
 382                 /* Toggle LANPHYPC Value bit */
 383                 e1000_toggle_lanphypc_pch_lpt(hw);
 384                 if (hw->mac.type >= e1000_pch_lpt) {
 385                         if (e1000_phy_is_accessible_pchlan(hw))
 386                                 break;
 387
 388                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 389                          * so ensure that the MAC is also out of SMBus mode
 390                          */
 391                         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 392                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 393                         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 394
 395                         if (e1000_phy_is_accessible_pchlan(hw))
 396                                 break;
 397
 398                         ret_val = -E1000_ERR_PHY;
 399                 }
 400                 break;
 401         default:
 402                 break;
 403         }
 404
 405         hw->phy.ops.release(hw);
 406         if (!ret_val) {
 407
 408                 /* Check to see if able to reset PHY.  Print error if not */
 409                 if (hw->phy.ops.check_reset_block(hw)) {
 410                         ERROR_REPORT("Reset blocked by ME\n");
 411                         goto out;
 412                 }
 413
 414                 /* Reset the PHY before any access to it.  Doing so, ensures
 415                  * that the PHY is in a known good state before we read/write
 416                  * PHY registers.  The generic reset is sufficient here,
 417                  * because we haven't determined the PHY type yet.
 418                  */
 419                 ret_val = e1000_phy_hw_reset_generic(hw);
 420                 if (ret_val)
 421                         goto out;
 422
 423                 /* On a successful reset, possibly need to wait for the PHY
 424                  * to quiesce to an accessible state before returning control
 425                  * to the calling function.  If the PHY does not quiesce, then
 426                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 427                  *  the PHY is in.
 428                  */
 429                 ret_val = hw->phy.ops.check_reset_block(hw);
 430                 if (ret_val)
 431                         ERROR_REPORT("ME blocked access to PHY after reset\n");
 432         }
 433
 434 out:
 435         /* Ungate automatic PHY configuration on non-managed 82579 */
 436         if ((hw->mac.type == e1000_pch2lan) &&
 437             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 438                 msec_delay(10);
 439                 e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
 440         }
 441
 442         return ret_val;
 443 }
 444
 445 /**
 446  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 447  *  @hw: pointer to the HW structure
 448  *
 449  *  Initialize family-specific PHY parameters and function pointers.
 450  **/
 451 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 452 {
 453         struct e1000_phy_info *phy = &hw->phy;
 454         s32 ret_val;
 455
 456         DEBUGFUNC("e1000_init_phy_params_pchlan");
 457
 458         phy->addr               = 1;
 459         phy->reset_delay_us     = 100;
 460
 461         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 462         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 463         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 464         phy->ops.set_page       = e1000_set_page_igp;
 465         phy->ops.read_reg       = e1000_read_phy_reg_hv;
 466         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 467         phy->ops.read_reg_page  = e1000_read_phy_reg_page_hv;
 468         phy->ops.release        = e1000_release_swflag_ich8lan;
 469         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 470         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 471         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 472         phy->ops.write_reg      = e1000_write_phy_reg_hv;
 473         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 474         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 475         phy->ops.power_up       = e1000_power_up_phy_copper;
 476         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 477         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 478
 479         phy->id = e1000_phy_unknown;
 480
 481         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 482         if (ret_val)
 483                 return ret_val;
 484
 485         if (phy->id == e1000_phy_unknown)
 486                 switch (hw->mac.type) {
 487                 default:
 488                         ret_val = e1000_get_phy_id(hw);
 489                         if (ret_val)
 490                                 return ret_val;
 491                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 492                                 break;
 493                         /* fall-through */
 494                 case e1000_pch2lan:
 495                 case e1000_pch_lpt:
 496                 case e1000_pch_spt:
 497                 case e1000_pch_cnp:
 498                         /* In case the PHY needs to be in mdio slow mode,
 499                          * set slow mode and try to get the PHY id again.
 500                          */
 501                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 502                         if (ret_val)
 503                                 return ret_val;
 504                         ret_val = e1000_get_phy_id(hw);
 505                         if (ret_val)
 506                                 return ret_val;
 507                         break;
 508                 }
 509         phy->type = e1000_get_phy_type_from_id(phy->id);
 510
 511         switch (phy->type) {
 512         case e1000_phy_82577:
 513         case e1000_phy_82579:
 514         case e1000_phy_i217:
 515                 phy->ops.check_polarity = e1000_check_polarity_82577;
 516                 phy->ops.force_speed_duplex =
 517                         e1000_phy_force_speed_duplex_82577;
 518                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 519                 phy->ops.get_info = e1000_get_phy_info_82577;
 520                 phy->ops.commit = e1000_phy_sw_reset_generic;
 521                 break;
 522         case e1000_phy_82578:
 523                 phy->ops.check_polarity = e1000_check_polarity_m88;
 524                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 525                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 526                 phy->ops.get_info = e1000_get_phy_info_m88;
 527                 break;
 528         default:
 529                 ret_val = -E1000_ERR_PHY;
 530                 break;
 531         }
 532
 533         return ret_val;
 534 }
 535
 536 /**
 537  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 538  *  @hw: pointer to the HW structure
 539  *
 540  *  Initialize family-specific PHY parameters and function pointers.
 541  **/
 542 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 543 {
 544         struct e1000_phy_info *phy = &hw->phy;
 545         s32 ret_val;
 546         u16 i = 0;
 547
 548         DEBUGFUNC("e1000_init_phy_params_ich8lan");
 549
 550         phy->addr               = 1;
 551         phy->reset_delay_us     = 100;
 552
 553         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 554         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 555         phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 556         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 557         phy->ops.read_reg       = e1000_read_phy_reg_igp;
 558         phy->ops.release        = e1000_release_swflag_ich8lan;
 559         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 560         phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
 561         phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
 562         phy->ops.write_reg      = e1000_write_phy_reg_igp;
 563         phy->ops.power_up       = e1000_power_up_phy_copper;
 564         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 565
 566         /* We may need to do this twice - once for IGP and if that fails,
 567          * we'll set BM func pointers and try again
 568          */
 569         ret_val = e1000_determine_phy_address(hw);
 570         if (ret_val) {
 571                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 572                 phy->ops.read_reg  = e1000_read_phy_reg_bm;
 573                 ret_val = e1000_determine_phy_address(hw);
 574                 if (ret_val) {
 575                         DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
 576                         return ret_val;
 577                 }
 578         }
 579
 580         phy->id = 0;
 581         while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
 582                (i++ < 100)) {
 583                 msec_delay(1);
 584                 ret_val = e1000_get_phy_id(hw);
 585                 if (ret_val)
 586                         return ret_val;
 587         }
 588
 589         /* Verify phy id */
 590         switch (phy->id) {
 591         case IGP03E1000_E_PHY_ID:
 592                 phy->type = e1000_phy_igp_3;
 593                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 594                 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
 595                 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
 596                 phy->ops.get_info = e1000_get_phy_info_igp;
 597                 phy->ops.check_polarity = e1000_check_polarity_igp;
 598                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 599                 break;
 600         case IFE_E_PHY_ID:
 601         case IFE_PLUS_E_PHY_ID:
 602         case IFE_C_E_PHY_ID:
 603                 phy->type = e1000_phy_ife;
 604                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 605                 phy->ops.get_info = e1000_get_phy_info_ife;
 606                 phy->ops.check_polarity = e1000_check_polarity_ife;
 607                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 608                 break;
 609         case BME1000_E_PHY_ID:
 610                 phy->type = e1000_phy_bm;
 611                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 612                 phy->ops.read_reg = e1000_read_phy_reg_bm;
 613                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 614                 phy->ops.commit = e1000_phy_sw_reset_generic;
 615                 phy->ops.get_info = e1000_get_phy_info_m88;
 616                 phy->ops.check_polarity = e1000_check_polarity_m88;
 617                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 618                 break;
 619         default:
 620                 return -E1000_ERR_PHY;
 621                 break;
 622         }
 623
 624         return E1000_SUCCESS;
 625 }
 626
 627 /**
 628  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 629  *  @hw: pointer to the HW structure
 630  *
 631  *  Initialize family-specific NVM parameters and function
 632  *  pointers.
 633  **/
 634 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 635 {
 636         struct e1000_nvm_info *nvm = &hw->nvm;
 637         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 638         u32 gfpreg, sector_base_addr, sector_end_addr;
 639         u16 i;
 640         u32 nvm_size;
 641
 642         DEBUGFUNC("e1000_init_nvm_params_ich8lan");
 643
 644         nvm->type = e1000_nvm_flash_sw;
 645
 646         if (hw->mac.type >= e1000_pch_spt) {
 647                 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
 648                  * STRAP register. This is because in SPT the GbE Flash region
 649                  * is no longer accessed through the flash registers. Instead,
 650                  * the mechanism has changed, and the Flash region access
 651                  * registers are now implemented in GbE memory space.
 652                  */
 653                 nvm->flash_base_addr = 0;
 654                 nvm_size =
 655                     (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
 656                     * NVM_SIZE_MULTIPLIER;
 657                 nvm->flash_bank_size = nvm_size / 2;
 658                 /* Adjust to word count */
 659                 nvm->flash_bank_size /= sizeof(u16);
 660                 /* Set the base address for flash register access */
 661                 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
 662         } else {
 663                 /* Can't read flash registers if register set isn't mapped. */
 664                 if (!hw->flash_address) {
 665                         DEBUGOUT("ERROR: Flash registers not mapped\n");
 666                         return -E1000_ERR_CONFIG;
 667                 }
 668
 669                 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
 670
 671                 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 672                  * Add 1 to sector_end_addr since this sector is included in
 673                  * the overall size.
 674                  */
 675                 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 676                 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 677
 678                 /* flash_base_addr is byte-aligned */
 679                 nvm->flash_base_addr = sector_base_addr
 680                                        << FLASH_SECTOR_ADDR_SHIFT;
 681
 682                 /* find total size of the NVM, then cut in half since the total
 683                  * size represents two separate NVM banks.
 684                  */
 685                 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 686                                         << FLASH_SECTOR_ADDR_SHIFT);
 687                 nvm->flash_bank_size /= 2;
 688                 /* Adjust to word count */
 689                 nvm->flash_bank_size /= sizeof(u16);
 690         }
 691
 692         nvm->word_size = E1000_SHADOW_RAM_WORDS;
 693
 694         /* Clear shadow ram */
 695         for (i = 0; i < nvm->word_size; i++) {
 696                 dev_spec->shadow_ram[i].modified = FALSE;
 697                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 698         }
 699
 700         E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
 701         E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
 702
 703         /* Function Pointers */
 704         nvm->ops.acquire        = e1000_acquire_nvm_ich8lan;
 705         nvm->ops.release        = e1000_release_nvm_ich8lan;
 706         if (hw->mac.type >= e1000_pch_spt) {
 707                 nvm->ops.read   = e1000_read_nvm_spt;
 708                 nvm->ops.update = e1000_update_nvm_checksum_spt;
 709         } else {
 710                 nvm->ops.read   = e1000_read_nvm_ich8lan;
 711                 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
 712         }
 713         nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
 714         nvm->ops.validate       = e1000_validate_nvm_checksum_ich8lan;
 715         nvm->ops.write          = e1000_write_nvm_ich8lan;
 716
 717         return E1000_SUCCESS;
 718 }
 719
 720 /**
 721  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 722  *  @hw: pointer to the HW structure
 723  *
 724  *  Initialize family-specific MAC parameters and function
 725  *  pointers.
 726  **/
 727 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 728 {
 729         struct e1000_mac_info *mac = &hw->mac;
 730
 731         DEBUGFUNC("e1000_init_mac_params_ich8lan");
 732
 733         /* Set media type function pointer */
 734         hw->phy.media_type = e1000_media_type_copper;
 735
 736         /* Set mta register count */
 737         mac->mta_reg_count = 32;
 738         /* Set rar entry count */
 739         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 740         if (mac->type == e1000_ich8lan)
 741                 mac->rar_entry_count--;
 742         /* Set if part includes ASF firmware */
 743         mac->asf_firmware_present = TRUE;
 744         /* FWSM register */
 745         mac->has_fwsm = TRUE;
 746         /* ARC subsystem not supported */
 747         mac->arc_subsystem_valid = FALSE;
 748         /* Adaptive IFS supported */
 749         mac->adaptive_ifs = TRUE;
 750
 751         /* Function pointers */
 752
 753         /* bus type/speed/width */
 754         mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
 755         /* function id */
 756         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 757         /* reset */
 758         mac->ops.reset_hw = e1000_reset_hw_ich8lan;
 759         /* hw initialization */
 760         mac->ops.init_hw = e1000_init_hw_ich8lan;
 761         /* link setup */
 762         mac->ops.setup_link = e1000_setup_link_ich8lan;
 763         /* physical interface setup */
 764         mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
 765         /* check for link */
 766         mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
 767         /* link info */
 768         mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
 769         /* multicast address update */
 770         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 771         /* clear hardware counters */
 772         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
 773
 774         /* LED and other operations */
 775         switch (mac->type) {
 776         case e1000_ich8lan:
 777         case e1000_ich9lan:
 778         case e1000_ich10lan:
 779                 /* check management mode */
 780                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 781                 /* ID LED init */
 782                 mac->ops.id_led_init = e1000_id_led_init_generic;
 783                 /* blink LED */
 784                 mac->ops.blink_led = e1000_blink_led_generic;
 785                 /* setup LED */
 786                 mac->ops.setup_led = e1000_setup_led_generic;
 787                 /* cleanup LED */
 788                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 789                 /* turn on/off LED */
 790                 mac->ops.led_on = e1000_led_on_ich8lan;
 791                 mac->ops.led_off = e1000_led_off_ich8lan;
 792                 break;
 793         case e1000_pch2lan:
 794                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 795                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 796                 /* fall-through */
 797         case e1000_pch_lpt:
 798         case e1000_pch_spt:
 799         case e1000_pch_cnp:
 800                 /* multicast address update for pch2 */
 801                 mac->ops.update_mc_addr_list =
 802                         e1000_update_mc_addr_list_pch2lan;
 803                 /* fall-through */
 804         case e1000_pchlan:
 805                 /* check management mode */
 806                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 807                 /* ID LED init */
 808                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 809                 /* setup LED */
 810                 mac->ops.setup_led = e1000_setup_led_pchlan;
 811                 /* cleanup LED */
 812                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 813                 /* turn on/off LED */
 814                 mac->ops.led_on = e1000_led_on_pchlan;
 815                 mac->ops.led_off = e1000_led_off_pchlan;
 816                 break;
 817         default:
 818                 break;
 819         }
 820
 821         if (mac->type >= e1000_pch_lpt) {
 822                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 823                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 824                 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
 825                 mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt;
 826         }
 827
 828         /* Enable PCS Lock-loss workaround for ICH8 */
 829         if (mac->type == e1000_ich8lan)
 830                 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
 831
 832         return E1000_SUCCESS;
 833 }
 834
 835 /**
 836  *  __e1000_access_emi_reg_locked - Read/write EMI register
 837  *  @hw: pointer to the HW structure
 838  *  @addr: EMI address to program
 839  *  @data: pointer to value to read/write from/to the EMI address
 840  *  @read: boolean flag to indicate read or write
 841  *
 842  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 843  **/
 844 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 845                                          u16 *data, bool read)
 846 {
 847         s32 ret_val;
 848
 849         DEBUGFUNC("__e1000_access_emi_reg_locked");
 850
 851         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
 852         if (ret_val)
 853                 return ret_val;
 854
 855         if (read)
 856                 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
 857                                                       data);
 858         else
 859                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
 860                                                        *data);
 861
 862         return ret_val;
 863 }
 864
 865 /**
 866  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 867  *  @hw: pointer to the HW structure
 868  *  @addr: EMI address to program
 869  *  @data: value to be read from the EMI address
 870  *
 871  *  Assumes the SW/FW/HW Semaphore is already acquired.
 872  **/
 873 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 874 {
 875         DEBUGFUNC("e1000_read_emi_reg_locked");
 876
 877         return __e1000_access_emi_reg_locked(hw, addr, data, TRUE);
 878 }
 879
 880 /**
 881  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 882  *  @hw: pointer to the HW structure
 883  *  @addr: EMI address to program
 884  *  @data: value to be written to the EMI address
 885  *
 886  *  Assumes the SW/FW/HW Semaphore is already acquired.
 887  **/
 888 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 889 {
 890         DEBUGFUNC("e1000_read_emi_reg_locked");
 891
 892         return __e1000_access_emi_reg_locked(hw, addr, &data, FALSE);
 893 }
 894
 895 /**
 896  *  e1000_set_eee_pchlan - Enable/disable EEE support
 897  *  @hw: pointer to the HW structure
 898  *
 899  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 900  *  the link and the EEE capabilities of the link partner.  The LPI Control
 901  *  register bits will remain set only if/when link is up.
 902  *
 903  *  EEE LPI must not be asserted earlier than one second after link is up.
 904  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 905  *  can be link issues with some switches.  Other devices can have EEE LPI
 906  *  enabled immediately upon link up since they have a timer in hardware which
 907  *  prevents LPI from being asserted too early.
 908  **/
 909 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 910 {
 911         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 912         s32 ret_val;
 913         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 914
 915         DEBUGFUNC("e1000_set_eee_pchlan");
 916
 917         switch (hw->phy.type) {
 918         case e1000_phy_82579:
 919                 lpa = I82579_EEE_LP_ABILITY;
 920                 pcs_status = I82579_EEE_PCS_STATUS;
 921                 adv_addr = I82579_EEE_ADVERTISEMENT;
 922                 break;
 923         case e1000_phy_i217:
 924                 lpa = I217_EEE_LP_ABILITY;
 925                 pcs_status = I217_EEE_PCS_STATUS;
 926                 adv_addr = I217_EEE_ADVERTISEMENT;
 927                 break;
 928         default:
 929                 return E1000_SUCCESS;
 930         }
 931
 932         ret_val = hw->phy.ops.acquire(hw);
 933         if (ret_val)
 934                 return ret_val;
 935
 936         ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 937         if (ret_val)
 938                 goto release;
 939
 940         /* Clear bits that enable EEE in various speeds */
 941         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 942
 943         /* Enable EEE if not disabled by user */
 944         if (!dev_spec->eee_disable) {
 945                 /* Save off link partner's EEE ability */
 946                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 947                                                     &dev_spec->eee_lp_ability);
 948                 if (ret_val)
 949                         goto release;
 950
 951                 /* Read EEE advertisement */
 952                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 953                 if (ret_val)
 954                         goto release;
 955
 956                 /* Enable EEE only for speeds in which the link partner is
 957                  * EEE capable and for which we advertise EEE.
 958                  */
 959                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 960                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 961
 962                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 963                         hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
 964                         if (data & NWAY_LPAR_100TX_FD_CAPS)
 965                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 966                         else
 967                                 /* EEE is not supported in 100Half, so ignore
 968                                  * partner's EEE in 100 ability if full-duplex
 969                                  * is not advertised.
 970                                  */
 971                                 dev_spec->eee_lp_ability &=
 972                                     ~I82579_EEE_100_SUPPORTED;
 973                 }
 974         }
 975
 976         if (hw->phy.type == e1000_phy_82579) {
 977                 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 978                                                     &data);
 979                 if (ret_val)
 980                         goto release;
 981
 982                 data &= ~I82579_LPI_100_PLL_SHUT;
 983                 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 984                                                      data);
 985         }
 986
 987         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 988         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 989         if (ret_val)
 990                 goto release;
 991
 992         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 993 release:
 994         hw->phy.ops.release(hw);
 995
 996         return ret_val;
 997 }
 998
 999 /**
1000  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
1001  *  @hw:   pointer to the HW structure
1002  *  @link: link up bool flag
1003  *
1004  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
1005  *  preventing further DMA write requests.  Workaround the issue by disabling
1006  *  the de-assertion of the clock request when in 1Gpbs mode.
1007  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
1008  *  speeds in order to avoid Tx hangs.
1009  **/
1010 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
1011 {
1012         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1013         u32 status = E1000_READ_REG(hw, E1000_STATUS);
1014         s32 ret_val = E1000_SUCCESS;
1015         u16 reg;
1016
1017         if (link && (status & E1000_STATUS_SPEED_1000)) {
1018                 ret_val = hw->phy.ops.acquire(hw);
1019                 if (ret_val)
1020                         return ret_val;
1021
1022                 ret_val =
1023                     e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1024                                                &reg);
1025                 if (ret_val)
1026                         goto release;
1027
1028                 ret_val =
1029                     e1000_write_kmrn_reg_locked(hw,
1030                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
1031                                                 reg &
1032                                                 ~E1000_KMRNCTRLSTA_K1_ENABLE);
1033                 if (ret_val)
1034                         goto release;
1035
1036                 usec_delay(10);
1037
1038                 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1039                                 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1040
1041                 ret_val =
1042                     e1000_write_kmrn_reg_locked(hw,
1043                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
1044                                                 reg);
1045 release:
1046                 hw->phy.ops.release(hw);
1047         } else {
1048                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1049                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1050
1051                 if ((hw->phy.revision > 5) || !link ||
1052                     ((status & E1000_STATUS_SPEED_100) &&
1053                      (status & E1000_STATUS_FD)))
1054                         goto update_fextnvm6;
1055
1056                 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);
1057                 if (ret_val)
1058                         return ret_val;
1059
1060                 /* Clear link status transmit timeout */
1061                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1062
1063                 if (status & E1000_STATUS_SPEED_100) {
1064                         /* Set inband Tx timeout to 5x10us for 100Half */
1065                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1066
1067                         /* Do not extend the K1 entry latency for 100Half */
1068                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1069                 } else {
1070                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
1071                         reg |= 50 <<
1072                                I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1073
1074                         /* Extend the K1 entry latency for 10 Mbps */
1075                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1076                 }
1077
1078                 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1079                 if (ret_val)
1080                         return ret_val;
1081
1082 update_fextnvm6:
1083                 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1084         }
1085
1086         return ret_val;
1087 }
1088
1089 static u64 e1000_ltr2ns(u16 ltr)
1090 {
1091         u32 value, scale;
1092
1093         /* Determine the latency in nsec based on the LTR value & scale */
1094         value = ltr & E1000_LTRV_VALUE_MASK;
1095         scale = (ltr & E1000_LTRV_SCALE_MASK) >> E1000_LTRV_SCALE_SHIFT;
1096
1097         return value * (1 << (scale * E1000_LTRV_SCALE_FACTOR));
1098 }
1099
1100 /**
1101  *  e1000_platform_pm_pch_lpt - Set platform power management values
1102  *  @hw: pointer to the HW structure
1103  *  @link: bool indicating link status
1104  *
1105  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
1106  *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
1107  *  when link is up (which must not exceed the maximum latency supported
1108  *  by the platform), otherwise specify there is no LTR requirement.
1109  *  Unlike TRUE-PCIe devices which set the LTR maximum snoop/no-snoop
1110  *  latencies in the LTR Extended Capability Structure in the PCIe Extended
1111  *  Capability register set, on this device LTR is set by writing the
1112  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1113  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1114  *  message to the PMC.
1115  *
1116  *  Use the LTR value to calculate the Optimized Buffer Flush/Fill (OBFF)
1117  *  high-water mark.
1118  **/
1119 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1120 {
1121         u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1122                   link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1123         u16 lat_enc = 0;        /* latency encoded */
1124         s32 obff_hwm = 0;
1125
1126         DEBUGFUNC("e1000_platform_pm_pch_lpt");
1127
1128         if (link) {
1129                 u16 speed, duplex, scale = 0;
1130                 u16 max_snoop, max_nosnoop;
1131                 u16 max_ltr_enc;        /* max LTR latency encoded */
1132                 s64 lat_ns;
1133                 s64 value;
1134                 u32 rxa;
1135
1136                 if (!hw->mac.max_frame_size) {
1137                         DEBUGOUT("max_frame_size not set.\n");
1138                         return -E1000_ERR_CONFIG;
1139                 }
1140
1141                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1142                 if (!speed) {
1143                         DEBUGOUT("Speed not set.\n");
1144                         return -E1000_ERR_CONFIG;
1145                 }
1146
1147                 /* Rx Packet Buffer Allocation size (KB) */
1148                 rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK;
1149
1150                 /* Determine the maximum latency tolerated by the device.
1151                  *
1152                  * Per the PCIe spec, the tolerated latencies are encoded as
1153                  * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1154                  * a 10-bit value (0-1023) to provide a range from 1 ns to
1155                  * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
1156                  * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1157                  */
1158                 lat_ns = ((s64)rxa * 1024 -
1159                           (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000;
1160                 if (lat_ns < 0)
1161                         lat_ns = 0;
1162                 else
1163                         lat_ns /= speed;
1164                 value = lat_ns;
1165
1166                 while (value > E1000_LTRV_VALUE_MASK) {
1167                         scale++;
1168                         value = E1000_DIVIDE_ROUND_UP(value, (1 << 5));
1169                 }
1170                 if (scale > E1000_LTRV_SCALE_MAX) {
1171                         DEBUGOUT1("Invalid LTR latency scale %d\n", scale);
1172                         return -E1000_ERR_CONFIG;
1173                 }
1174                 lat_enc = (u16)((scale << E1000_LTRV_SCALE_SHIFT) | value);
1175
1176                 /* Determine the maximum latency tolerated by the platform */
1177                 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop);
1178                 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1179                 max_ltr_enc = E1000_MAX(max_snoop, max_nosnoop);
1180
1181                 if (lat_enc > max_ltr_enc) {
1182                         lat_enc = max_ltr_enc;
1183                         lat_ns = e1000_ltr2ns(max_ltr_enc);
1184                 }
1185
1186                 if (lat_ns) {
1187                         lat_ns *= speed * 1000;
1188                         lat_ns /= 8;
1189                         lat_ns /= 1000000000;
1190                         obff_hwm = (s32)(rxa - lat_ns);
1191                 }
1192                 if ((obff_hwm < 0) || (obff_hwm > E1000_SVT_OFF_HWM_MASK)) {
1193                         DEBUGOUT1("Invalid high water mark %d\n", obff_hwm);
1194                         return -E1000_ERR_CONFIG;
1195                 }
1196         }
1197
1198         /* Set Snoop and No-Snoop latencies the same */
1199         reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1200         E1000_WRITE_REG(hw, E1000_LTRV, reg);
1201
1202         /* Set OBFF high water mark */
1203         reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK;
1204         reg |= obff_hwm;
1205         E1000_WRITE_REG(hw, E1000_SVT, reg);
1206
1207         /* Enable OBFF */
1208         reg = E1000_READ_REG(hw, E1000_SVCR);
1209         reg |= E1000_SVCR_OFF_EN;
1210         /* Always unblock interrupts to the CPU even when the system is
1211          * in OBFF mode. This ensures that small round-robin traffic
1212          * (like ping) does not get dropped or experience long latency.
1213          */
1214         reg |= E1000_SVCR_OFF_MASKINT;
1215         E1000_WRITE_REG(hw, E1000_SVCR, reg);
1216
1217         return E1000_SUCCESS;
1218 }
1219
1220 /**
1221  *  e1000_set_obff_timer_pch_lpt - Update Optimized Buffer Flush/Fill timer
1222  *  @hw: pointer to the HW structure
1223  *  @itr: interrupt throttling rate
1224  *
1225  *  Configure OBFF with the updated interrupt rate.
1226  **/
1227 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr)
1228 {
1229         u32 svcr;
1230         s32 timer;
1231
1232         DEBUGFUNC("e1000_set_obff_timer_pch_lpt");
1233
1234         /* Convert ITR value into microseconds for OBFF timer */
1235         timer = itr & E1000_ITR_MASK;
1236         timer = (timer * E1000_ITR_MULT) / 1000;
1237
1238         if ((timer < 0) || (timer > E1000_ITR_MASK)) {
1239                 DEBUGOUT1("Invalid OBFF timer %d\n", timer);
1240                 return -E1000_ERR_CONFIG;
1241         }
1242
1243         svcr = E1000_READ_REG(hw, E1000_SVCR);
1244         svcr &= ~E1000_SVCR_OFF_TIMER_MASK;
1245         svcr |= timer << E1000_SVCR_OFF_TIMER_SHIFT;
1246         E1000_WRITE_REG(hw, E1000_SVCR, svcr);
1247
1248         return E1000_SUCCESS;
1249 }
1250
1251 /**
1252  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1253  *  @hw: pointer to the HW structure
1254  *  @to_sx: boolean indicating a system power state transition to Sx
1255  *
1256  *  When link is down, configure ULP mode to significantly reduce the power
1257  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1258  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1259  *  system, configure the ULP mode by software.
1260  */
1261 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1262 {
1263         u32 mac_reg;
1264         s32 ret_val = E1000_SUCCESS;
1265         u16 phy_reg;
1266         u16 oem_reg = 0;
1267
1268         if ((hw->mac.type < e1000_pch_lpt) ||
1269             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1270             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1271             (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1272             (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1273             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1274                 return 0;
1275
1276         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1277                 /* Request ME configure ULP mode in the PHY */
1278                 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1279                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1280                 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1281
1282                 goto out;
1283         }
1284
1285         if (!to_sx) {
1286                 int i = 0;
1287
1288                 /* Poll up to 5 seconds for Cable Disconnected indication */
1289                 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1290                          E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1291                         /* Bail if link is re-acquired */
1292                         if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1293                                 return -E1000_ERR_PHY;
1294
1295                         if (i++ == 100)
1296                                 break;
1297
1298                         msec_delay(50);
1299                 }
1300                 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1301                          (E1000_READ_REG(hw, E1000_FEXT) &
1302                           E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1303                          i * 50);
1304         }
1305
1306         ret_val = hw->phy.ops.acquire(hw);
1307         if (ret_val)
1308                 goto out;
1309
1310         /* Force SMBus mode in PHY */
1311         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1312         if (ret_val)
1313                 goto release;
1314         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1315         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1316
1317         /* Force SMBus mode in MAC */
1318         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1319         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1320         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1321
1322         /* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable
1323          * LPLU and disable Gig speed when entering ULP
1324          */
1325         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1326                 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1327                                                        &oem_reg);
1328                 if (ret_val)
1329                         goto release;
1330
1331                 phy_reg = oem_reg;
1332                 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1333
1334                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1335                                                         phy_reg);
1336
1337                 if (ret_val)
1338                         goto release;
1339         }
1340
1341         /* Set Inband ULP Exit, Reset to SMBus mode and
1342          * Disable SMBus Release on PERST# in PHY
1343          */
1344         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1345         if (ret_val)
1346                 goto release;
1347         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1348                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1349         if (to_sx) {
1350                 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1351                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1352                 else
1353                         phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1354
1355                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1356                 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1357         } else {
1358                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1359                 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1360                 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1361         }
1362         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1363
1364         /* Set Disable SMBus Release on PERST# in MAC */
1365         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1366         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1367         E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1368
1369         /* Commit ULP changes in PHY by starting auto ULP configuration */
1370         phy_reg |= I218_ULP_CONFIG1_START;
1371         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1372
1373         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1374             to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1375                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1376                                                         oem_reg);
1377                 if (ret_val)
1378                         goto release;
1379         }
1380
1381 release:
1382         hw->phy.ops.release(hw);
1383 out:
1384         if (ret_val)
1385                 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1386         else
1387                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1388
1389         return ret_val;
1390 }
1391
1392 /**
1393  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1394  *  @hw: pointer to the HW structure
1395  *  @force: boolean indicating whether or not to force disabling ULP
1396  *
1397  *  Un-configure ULP mode when link is up, the system is transitioned from
1398  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1399  *  system, poll for an indication from ME that ULP has been un-configured.
1400  *  If not on an ME enabled system, un-configure the ULP mode by software.
1401  *
1402  *  During nominal operation, this function is called when link is acquired
1403  *  to disable ULP mode (force=FALSE); otherwise, for example when unloading
1404  *  the driver or during Sx->S0 transitions, this is called with force=TRUE
1405  *  to forcibly disable ULP.
1406  */
1407 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1408 {
1409         s32 ret_val = E1000_SUCCESS;
1410         u32 mac_reg;
1411         u16 phy_reg;
1412         int i = 0;
1413
1414         if ((hw->mac.type < e1000_pch_lpt) ||
1415             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1416             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1417             (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1418             (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1419             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1420                 return 0;
1421
1422         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1423                 if (force) {
1424                         /* Request ME un-configure ULP mode in the PHY */
1425                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1426                         mac_reg &= ~E1000_H2ME_ULP;
1427                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1428                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1429                 }
1430
1431                 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1432                 while (E1000_READ_REG(hw, E1000_FWSM) &
1433                        E1000_FWSM_ULP_CFG_DONE) {
1434                         if (i++ == 30) {
1435                                 ret_val = -E1000_ERR_PHY;
1436                                 goto out;
1437                         }
1438
1439                         msec_delay(10);
1440                 }
1441                 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1442
1443                 if (force) {
1444                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1445                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1446                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1447                 } else {
1448                         /* Clear H2ME.ULP after ME ULP configuration */
1449                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1450                         mac_reg &= ~E1000_H2ME_ULP;
1451                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1452                 }
1453
1454                 goto out;
1455         }
1456
1457         ret_val = hw->phy.ops.acquire(hw);
1458         if (ret_val)
1459                 goto out;
1460
1461         if (force)
1462                 /* Toggle LANPHYPC Value bit */
1463                 e1000_toggle_lanphypc_pch_lpt(hw);
1464
1465         /* Unforce SMBus mode in PHY */
1466         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1467         if (ret_val) {
1468                 /* The MAC might be in PCIe mode, so temporarily force to
1469                  * SMBus mode in order to access the PHY.
1470                  */
1471                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1472                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1473                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1474
1475                 msec_delay(50);
1476
1477                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1478                                                        &phy_reg);
1479                 if (ret_val)
1480                         goto release;
1481         }
1482         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1483         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1484
1485         /* Unforce SMBus mode in MAC */
1486         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1487         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1488         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1489
1490         /* When ULP mode was previously entered, K1 was disabled by the
1491          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1492          */
1493         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1494         if (ret_val)
1495                 goto release;
1496         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1497         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1498
1499         /* Clear ULP enabled configuration */
1500         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1501         if (ret_val)
1502                 goto release;
1503         phy_reg &= ~(I218_ULP_CONFIG1_IND |
1504                      I218_ULP_CONFIG1_STICKY_ULP |
1505                      I218_ULP_CONFIG1_RESET_TO_SMBUS |
1506                      I218_ULP_CONFIG1_WOL_HOST |
1507                      I218_ULP_CONFIG1_INBAND_EXIT |
1508                      I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1509                      I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1510                      I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1511         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1512
1513         /* Commit ULP changes by starting auto ULP configuration */
1514         phy_reg |= I218_ULP_CONFIG1_START;
1515         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1516
1517         /* Clear Disable SMBus Release on PERST# in MAC */
1518         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1519         mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1520         E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1521
1522 release:
1523         hw->phy.ops.release(hw);
1524         if (force) {
1525                 hw->phy.ops.reset(hw);
1526                 msec_delay(50);
1527         }
1528 out:
1529         if (ret_val)
1530                 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1531         else
1532                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1533
1534         return ret_val;
1535 }
1536
1537 /**
1538  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1539  *  @hw: pointer to the HW structure
1540  *
1541  *  Checks to see of the link status of the hardware has changed.  If a
1542  *  change in link status has been detected, then we read the PHY registers
1543  *  to get the current speed/duplex if link exists.
1544  **/
1545 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1546 {
1547         struct e1000_mac_info *mac = &hw->mac;
1548         s32 ret_val, tipg_reg = 0;
1549         u16 emi_addr, emi_val = 0;
1550         bool link;
1551         u16 phy_reg;
1552
1553         DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1554
1555         /* We only want to go out to the PHY registers to see if Auto-Neg
1556          * has completed and/or if our link status has changed.  The
1557          * get_link_status flag is set upon receiving a Link Status
1558          * Change or Rx Sequence Error interrupt.
1559          */
1560         if (!mac->get_link_status)
1561                 return E1000_SUCCESS;
1562
1563         /* First we want to see if the MII Status Register reports
1564          * link.  If so, then we want to get the current speed/duplex
1565          * of the PHY.
1566          */
1567         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1568         if (ret_val)
1569                 return ret_val;
1570
1571         if (hw->mac.type == e1000_pchlan) {
1572                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1573                 if (ret_val)
1574                         return ret_val;
1575         }
1576
1577         /* When connected at 10Mbps half-duplex, some parts are excessively
1578          * aggressive resulting in many collisions. To avoid this, increase
1579          * the IPG and reduce Rx latency in the PHY.
1580          */
1581         if ((hw->mac.type >= e1000_pch2lan) && link) {
1582                 u16 speed, duplex;
1583
1584                 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1585                 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1586                 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1587
1588                 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1589                         tipg_reg |= 0xFF;
1590                         /* Reduce Rx latency in analog PHY */
1591                         emi_val = 0;
1592                 } else if (hw->mac.type >= e1000_pch_spt &&
1593                            duplex == FULL_DUPLEX && speed != SPEED_1000) {
1594                         tipg_reg |= 0xC;
1595                         emi_val = 1;
1596                 } else {
1597                         /* Roll back the default values */
1598                         tipg_reg |= 0x08;
1599                         emi_val = 1;
1600                 }
1601
1602                 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1603
1604                 ret_val = hw->phy.ops.acquire(hw);
1605                 if (ret_val)
1606                         return ret_val;
1607
1608                 if (hw->mac.type == e1000_pch2lan)
1609                         emi_addr = I82579_RX_CONFIG;
1610                 else
1611                         emi_addr = I217_RX_CONFIG;
1612                 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1613
1614
1615                 if (hw->mac.type >= e1000_pch_lpt) {
1616                         u16 phy_reg;
1617
1618                         hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1619                                                     &phy_reg);
1620                         phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1621                         if (speed == SPEED_100 || speed == SPEED_10)
1622                                 phy_reg |= 0x3E8;
1623                         else
1624                                 phy_reg |= 0xFA;
1625                         hw->phy.ops.write_reg_locked(hw,
1626                                                      I217_PLL_CLOCK_GATE_REG,
1627                                                      phy_reg);
1628
1629                         if (speed == SPEED_1000) {
1630                                 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1631                                                             &phy_reg);
1632
1633                                 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1634
1635                                 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1636                                                              phy_reg);
1637                                 }
1638                  }
1639                 hw->phy.ops.release(hw);
1640
1641                 if (ret_val)
1642                         return ret_val;
1643
1644                 if (hw->mac.type >= e1000_pch_spt) {
1645                         u16 data;
1646                         u16 ptr_gap;
1647
1648                         if (speed == SPEED_1000) {
1649                                 ret_val = hw->phy.ops.acquire(hw);
1650                                 if (ret_val)
1651                                         return ret_val;
1652
1653                                 ret_val = hw->phy.ops.read_reg_locked(hw,
1654                                                               PHY_REG(776, 20),
1655                                                               &data);
1656                                 if (ret_val) {
1657                                         hw->phy.ops.release(hw);
1658                                         return ret_val;
1659                                 }
1660
1661                                 ptr_gap = (data & (0x3FF << 2)) >> 2;
1662                                 if (ptr_gap < 0x18) {
1663                                         data &= ~(0x3FF << 2);
1664                                         data |= (0x18 << 2);
1665                                         ret_val =
1666                                                 hw->phy.ops.write_reg_locked(hw,
1667                                                         PHY_REG(776, 20), data);
1668                                 }
1669                                 hw->phy.ops.release(hw);
1670                                 if (ret_val)
1671                                         return ret_val;
1672                         } else {
1673                                 ret_val = hw->phy.ops.acquire(hw);
1674                                 if (ret_val)
1675                                         return ret_val;
1676
1677                                 ret_val = hw->phy.ops.write_reg_locked(hw,
1678                                                              PHY_REG(776, 20),
1679                                                              0xC023);
1680                                 hw->phy.ops.release(hw);
1681                                 if (ret_val)
1682                                         return ret_val;
1683
1684                         }
1685                 }
1686         }
1687
1688         /* I217 Packet Loss issue:
1689          * ensure that FEXTNVM4 Beacon Duration is set correctly
1690          * on power up.
1691          * Set the Beacon Duration for I217 to 8 usec
1692          */
1693         if (hw->mac.type >= e1000_pch_lpt) {
1694                 u32 mac_reg;
1695
1696                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1697                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1698                 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1699                 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1700         }
1701
1702         /* Work-around I218 hang issue */
1703         if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1704             (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1705             (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1706             (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1707                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1708                 if (ret_val)
1709                         return ret_val;
1710         }
1711         if (hw->mac.type >= e1000_pch_lpt) {
1712                 /* Set platform power management values for
1713                  * Latency Tolerance Reporting (LTR)
1714                  * Optimized Buffer Flush/Fill (OBFF)
1715                  */
1716                 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1717                 if (ret_val)
1718                         return ret_val;
1719         }
1720
1721         /* Clear link partner's EEE ability */
1722         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1723
1724         if (hw->mac.type >= e1000_pch_lpt) {
1725                 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1726
1727                 if (hw->mac.type == e1000_pch_spt) {
1728                         /* FEXTNVM6 K1-off workaround - for SPT only */
1729                         u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
1730
1731                         if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1732                                 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1733                         else
1734                                 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1735                 }
1736
1737                 if (hw->dev_spec.ich8lan.disable_k1_off == TRUE)
1738                         fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1739
1740                 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1741         }
1742
1743         if (!link)
1744                 return E1000_SUCCESS; /* No link detected */
1745
1746         mac->get_link_status = FALSE;
1747
1748         switch (hw->mac.type) {
1749         case e1000_pch2lan:
1750                 ret_val = e1000_k1_workaround_lv(hw);
1751                 if (ret_val)
1752                         return ret_val;
1753                 /* fall-thru */
1754         case e1000_pchlan:
1755                 if (hw->phy.type == e1000_phy_82578) {
1756                         ret_val = e1000_link_stall_workaround_hv(hw);
1757                         if (ret_val)
1758                                 return ret_val;
1759                 }
1760
1761                 /* Workaround for PCHx parts in half-duplex:
1762                  * Set the number of preambles removed from the packet
1763                  * when it is passed from the PHY to the MAC to prevent
1764                  * the MAC from misinterpreting the packet type.
1765                  */
1766                 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1767                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1768
1769                 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1770                     E1000_STATUS_FD)
1771                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1772
1773                 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1774                 break;
1775         default:
1776                 break;
1777         }
1778
1779         /* Check if there was DownShift, must be checked
1780          * immediately after link-up
1781          */
1782         e1000_check_downshift_generic(hw);
1783
1784         /* Enable/Disable EEE after link up */
1785         if (hw->phy.type > e1000_phy_82579) {
1786                 ret_val = e1000_set_eee_pchlan(hw);
1787                 if (ret_val)
1788                         return ret_val;
1789         }
1790
1791         /* If we are forcing speed/duplex, then we simply return since
1792          * we have already determined whether we have link or not.
1793          */
1794         if (!mac->autoneg)
1795                 return -E1000_ERR_CONFIG;
1796
1797         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1798          * of MAC speed/duplex configuration.  So we only need to
1799          * configure Collision Distance in the MAC.
1800          */
1801         mac->ops.config_collision_dist(hw);
1802
1803         /* Configure Flow Control now that Auto-Neg has completed.
1804          * First, we need to restore the desired flow control
1805          * settings because we may have had to re-autoneg with a
1806          * different link partner.
1807          */
1808         ret_val = e1000_config_fc_after_link_up_generic(hw);
1809         if (ret_val)
1810                 DEBUGOUT("Error configuring flow control\n");
1811
1812         return ret_val;
1813 }
1814
1815 /**
1816  *  e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1817  *  @hw: pointer to the HW structure
1818  *
1819  *  Initialize family-specific function pointers for PHY, MAC, and NVM.
1820  **/
1821 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1822 {
1823         DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1824
1825         hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1826         hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1827         switch (hw->mac.type) {
1828         case e1000_ich8lan:
1829         case e1000_ich9lan:
1830         case e1000_ich10lan:
1831                 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1832                 break;
1833         case e1000_pchlan:
1834         case e1000_pch2lan:
1835         case e1000_pch_lpt:
1836         case e1000_pch_spt:
1837         case e1000_pch_cnp:
1838                 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1839                 break;
1840         default:
1841                 break;
1842         }
1843 }
1844
1845 /**
1846  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1847  *  @hw: pointer to the HW structure
1848  *
1849  *  Acquires the mutex for performing NVM operations.
1850  **/
1851 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1852 {
1853         DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1854
1855         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1856
1857         return E1000_SUCCESS;
1858 }
1859
1860 /**
1861  *  e1000_release_nvm_ich8lan - Release NVM mutex
1862  *  @hw: pointer to the HW structure
1863  *
1864  *  Releases the mutex used while performing NVM operations.
1865  **/
1866 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1867 {
1868         DEBUGFUNC("e1000_release_nvm_ich8lan");
1869
1870         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1871
1872         return;
1873 }
1874
1875 /**
1876  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1877  *  @hw: pointer to the HW structure
1878  *
1879  *  Acquires the software control flag for performing PHY and select
1880  *  MAC CSR accesses.
1881  **/
1882 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1883 {
1884         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1885         s32 ret_val = E1000_SUCCESS;
1886
1887         DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1888
1889         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1890
1891         while (timeout) {
1892                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1893                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1894                         break;
1895
1896                 msec_delay_irq(1);
1897                 timeout--;
1898         }
1899
1900         if (!timeout) {
1901                 DEBUGOUT("SW has already locked the resource.\n");
1902                 ret_val = -E1000_ERR_CONFIG;
1903                 goto out;
1904         }
1905
1906         timeout = SW_FLAG_TIMEOUT;
1907
1908         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1909         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1910
1911         while (timeout) {
1912                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1913                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1914                         break;
1915
1916                 msec_delay_irq(1);
1917                 timeout--;
1918         }
1919
1920         if (!timeout) {
1921                 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1922                           E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1923                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1924                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1925                 ret_val = -E1000_ERR_CONFIG;
1926                 goto out;
1927         }
1928
1929 out:
1930         if (ret_val)
1931                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1932
1933         return ret_val;
1934 }
1935
1936 /**
1937  *  e1000_release_swflag_ich8lan - Release software control flag
1938  *  @hw: pointer to the HW structure
1939  *
1940  *  Releases the software control flag for performing PHY and select
1941  *  MAC CSR accesses.
1942  **/
1943 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1944 {
1945         u32 extcnf_ctrl;
1946
1947         DEBUGFUNC("e1000_release_swflag_ich8lan");
1948
1949         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1950
1951         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1952                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1953                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1954         } else {
1955                 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1956         }
1957
1958         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1959
1960         return;
1961 }
1962
1963 /**
1964  *  e1000_check_mng_mode_ich8lan - Checks management mode
1965  *  @hw: pointer to the HW structure
1966  *
1967  *  This checks if the adapter has any manageability enabled.
1968  *  This is a function pointer entry point only called by read/write
1969  *  routines for the PHY and NVM parts.
1970  **/
1971 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1972 {
1973         u32 fwsm;
1974
1975         DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1976
1977         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1978
1979         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1980                ((fwsm & E1000_FWSM_MODE_MASK) ==
1981                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1982 }
1983
1984 /**
1985  *  e1000_check_mng_mode_pchlan - Checks management mode
1986  *  @hw: pointer to the HW structure
1987  *
1988  *  This checks if the adapter has iAMT enabled.
1989  *  This is a function pointer entry point only called by read/write
1990  *  routines for the PHY and NVM parts.
1991  **/
1992 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1993 {
1994         u32 fwsm;
1995
1996         DEBUGFUNC("e1000_check_mng_mode_pchlan");
1997
1998         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1999
2000         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
2001                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
2002 }
2003
2004 /**
2005  *  e1000_rar_set_pch2lan - Set receive address register
2006  *  @hw: pointer to the HW structure
2007  *  @addr: pointer to the receive address
2008  *  @index: receive address array register
2009  *
2010  *  Sets the receive address array register at index to the address passed
2011  *  in by addr.  For 82579, RAR[0] is the base address register that is to
2012  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
2013  *  Use SHRA[0-3] in place of those reserved for ME.
2014  **/
2015 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
2016 {
2017         u32 rar_low, rar_high;
2018
2019         DEBUGFUNC("e1000_rar_set_pch2lan");
2020
2021         /* HW expects these in little endian so we reverse the byte order
2022          * from network order (big endian) to little endian
2023          */
2024         rar_low = ((u32) addr[0] |
2025                    ((u32) addr[1] << 8) |
2026                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
2027
2028         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
2029
2030         /* If MAC address zero, no need to set the AV bit */
2031         if (rar_low || rar_high)
2032                 rar_high |= E1000_RAH_AV;
2033
2034         if (index == 0) {
2035                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2036                 E1000_WRITE_FLUSH(hw);
2037                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2038                 E1000_WRITE_FLUSH(hw);
2039                 return E1000_SUCCESS;
2040         }
2041
2042         /* RAR[1-6] are owned by manageability.  Skip those and program the
2043          * next address into the SHRA register array.
2044          */
2045         if (index < (u32) (hw->mac.rar_entry_count)) {
2046                 s32 ret_val;
2047
2048                 ret_val = e1000_acquire_swflag_ich8lan(hw);
2049                 if (ret_val)
2050                         goto out;
2051
2052                 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
2053                 E1000_WRITE_FLUSH(hw);
2054                 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
2055                 E1000_WRITE_FLUSH(hw);
2056
2057                 e1000_release_swflag_ich8lan(hw);
2058
2059                 /* verify the register updates */
2060                 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
2061                     (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
2062                         return E1000_SUCCESS;
2063
2064                 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
2065                          (index - 1), E1000_READ_REG(hw, E1000_FWSM));
2066         }
2067
2068 out:
2069         DEBUGOUT1("Failed to write receive address at index %d\n", index);
2070         return -E1000_ERR_CONFIG;
2071 }
2072
2073 /**
2074  *  e1000_rar_set_pch_lpt - Set receive address registers
2075  *  @hw: pointer to the HW structure
2076  *  @addr: pointer to the receive address
2077  *  @index: receive address array register
2078  *
2079  *  Sets the receive address register array at index to the address passed
2080  *  in by addr. For LPT, RAR[0] is the base address register that is to
2081  *  contain the MAC address. SHRA[0-10] are the shared receive address
2082  *  registers that are shared between the Host and manageability engine (ME).
2083  **/
2084 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
2085 {
2086         u32 rar_low, rar_high;
2087         u32 wlock_mac;
2088
2089         DEBUGFUNC("e1000_rar_set_pch_lpt");
2090
2091         /* HW expects these in little endian so we reverse the byte order
2092          * from network order (big endian) to little endian
2093          */
2094         rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
2095                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
2096
2097         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
2098
2099         /* If MAC address zero, no need to set the AV bit */
2100         if (rar_low || rar_high)
2101                 rar_high |= E1000_RAH_AV;
2102
2103         if (index == 0) {
2104                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2105                 E1000_WRITE_FLUSH(hw);
2106                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2107                 E1000_WRITE_FLUSH(hw);
2108                 return E1000_SUCCESS;
2109         }
2110
2111         /* The manageability engine (ME) can lock certain SHRAR registers that
2112          * it is using - those registers are unavailable for use.
2113          */
2114         if (index < hw->mac.rar_entry_count) {
2115                 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
2116                             E1000_FWSM_WLOCK_MAC_MASK;
2117                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2118
2119                 /* Check if all SHRAR registers are locked */
2120                 if (wlock_mac == 1)
2121                         goto out;
2122
2123                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2124                         s32 ret_val;
2125
2126                         ret_val = e1000_acquire_swflag_ich8lan(hw);
2127
2128                         if (ret_val)
2129                                 goto out;
2130
2131                         E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
2132                                         rar_low);
2133                         E1000_WRITE_FLUSH(hw);
2134                         E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
2135                                         rar_high);
2136                         E1000_WRITE_FLUSH(hw);
2137
2138                         e1000_release_swflag_ich8lan(hw);
2139
2140                         /* verify the register updates */
2141                         if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2142                             (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
2143                                 return E1000_SUCCESS;
2144                 }
2145         }
2146
2147 out:
2148         DEBUGOUT1("Failed to write receive address at index %d\n", index);
2149         return -E1000_ERR_CONFIG;
2150 }
2151
2152 /**
2153  *  e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
2154  *  @hw: pointer to the HW structure
2155  *  @mc_addr_list: array of multicast addresses to program
2156  *  @mc_addr_count: number of multicast addresses to program
2157  *
2158  *  Updates entire Multicast Table Array of the PCH2 MAC and PHY.
2159  *  The caller must have a packed mc_addr_list of multicast addresses.
2160  **/
2161 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
2162                                               u8 *mc_addr_list,
2163                                               u32 mc_addr_count)
2164 {
2165         u16 phy_reg = 0;
2166         int i;
2167         s32 ret_val;
2168
2169         DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
2170
2171         e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
2172
2173         ret_val = hw->phy.ops.acquire(hw);
2174         if (ret_val)
2175                 return;
2176
2177         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2178         if (ret_val)
2179                 goto release;
2180
2181         for (i = 0; i < hw->mac.mta_reg_count; i++) {
2182                 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
2183                                            (u16)(hw->mac.mta_shadow[i] &
2184                                                  0xFFFF));
2185                 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
2186                                            (u16)((hw->mac.mta_shadow[i] >> 16) &
2187                                                  0xFFFF));
2188         }
2189
2190         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2191
2192 release:
2193         hw->phy.ops.release(hw);
2194 }
2195
2196 /**
2197  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2198  *  @hw: pointer to the HW structure
2199  *
2200  *  Checks if firmware is blocking the reset of the PHY.
2201  *  This is a function pointer entry point only called by
2202  *  reset routines.
2203  **/
2204 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2205 {
2206         u32 fwsm;
2207         bool blocked = FALSE;
2208         int i = 0;
2209
2210         DEBUGFUNC("e1000_check_reset_block_ich8lan");
2211
2212         do {
2213                 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2214                 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2215                         blocked = TRUE;
2216                         msec_delay(10);
2217                         continue;
2218                 }
2219                 blocked = FALSE;
2220         } while (blocked && (i++ < 30));
2221         return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2222 }
2223
2224 /**
2225  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2226  *  @hw: pointer to the HW structure
2227  *
2228  *  Assumes semaphore already acquired.
2229  *
2230  **/
2231 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2232 {
2233         u16 phy_data;
2234         u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2235         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2236                 E1000_STRAP_SMT_FREQ_SHIFT;
2237         s32 ret_val;
2238
2239         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2240
2241         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2242         if (ret_val)
2243                 return ret_val;
2244
2245         phy_data &= ~HV_SMB_ADDR_MASK;
2246         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2247         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2248
2249         if (hw->phy.type == e1000_phy_i217) {
2250                 /* Restore SMBus frequency */
2251                 if (freq--) {
2252                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2253                         phy_data |= (freq & (1 << 0)) <<
2254                                 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2255                         phy_data |= (freq & (1 << 1)) <<
2256                                 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2257                 } else {
2258                         DEBUGOUT("Unsupported SMB frequency in PHY\n");
2259                 }
2260         }
2261
2262         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2263 }
2264
2265 /**
2266  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2267  *  @hw:   pointer to the HW structure
2268  *
2269  *  SW should configure the LCD from the NVM extended configuration region
2270  *  as a workaround for certain parts.
2271  **/
2272 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2273 {
2274         struct e1000_phy_info *phy = &hw->phy;
2275         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2276         s32 ret_val = E1000_SUCCESS;
2277         u16 word_addr, reg_data, reg_addr, phy_page = 0;
2278
2279         DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2280
2281         /* Initialize the PHY from the NVM on ICH platforms.  This
2282          * is needed due to an issue where the NVM configuration is
2283          * not properly autoloaded after power transitions.
2284          * Therefore, after each PHY reset, we will load the
2285          * configuration data out of the NVM manually.
2286          */
2287         switch (hw->mac.type) {
2288         case e1000_ich8lan:
2289                 if (phy->type != e1000_phy_igp_3)
2290                         return ret_val;
2291
2292                 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2293                     (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2294                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2295                         break;
2296                 }
2297                 /* Fall-thru */
2298         case e1000_pchlan:
2299         case e1000_pch2lan:
2300         case e1000_pch_lpt:
2301         case e1000_pch_spt:
2302         case e1000_pch_cnp:
2303                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2304                 break;
2305         default:
2306                 return ret_val;
2307         }
2308
2309         ret_val = hw->phy.ops.acquire(hw);
2310         if (ret_val)
2311                 return ret_val;
2312
2313         data = E1000_READ_REG(hw, E1000_FEXTNVM);
2314         if (!(data & sw_cfg_mask))
2315                 goto release;
2316
2317         /* Make sure HW does not configure LCD from PHY
2318          * extended configuration before SW configuration
2319          */
2320         data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2321         if ((hw->mac.type < e1000_pch2lan) &&
2322             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2323                         goto release;
2324
2325         cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2326         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2327         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2328         if (!cnf_size)
2329                 goto release;
2330
2331         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2332         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2333
2334         if (((hw->mac.type == e1000_pchlan) &&
2335              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2336             (hw->mac.type > e1000_pchlan)) {
2337                 /* HW configures the SMBus address and LEDs when the
2338                  * OEM and LCD Write Enable bits are set in the NVM.
2339                  * When both NVM bits are cleared, SW will configure
2340                  * them instead.
2341                  */
2342                 ret_val = e1000_write_smbus_addr(hw);
2343                 if (ret_val)
2344                         goto release;
2345
2346                 data = E1000_READ_REG(hw, E1000_LEDCTL);
2347                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2348                                                         (u16)data);
2349                 if (ret_val)
2350                         goto release;
2351         }
2352
2353         /* Configure LCD from extended configuration region. */
2354
2355         /* cnf_base_addr is in DWORD */
2356         word_addr = (u16)(cnf_base_addr << 1);
2357
2358         for (i = 0; i < cnf_size; i++) {
2359                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2360                                            &reg_data);
2361                 if (ret_val)
2362                         goto release;
2363
2364                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2365                                            1, &reg_addr);
2366                 if (ret_val)
2367                         goto release;
2368
2369                 /* Save off the PHY page for future writes. */
2370                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2371                         phy_page = reg_data;
2372                         continue;
2373                 }
2374
2375                 reg_addr &= PHY_REG_MASK;
2376                 reg_addr |= phy_page;
2377
2378                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2379                                                     reg_data);
2380                 if (ret_val)
2381                         goto release;
2382         }
2383
2384 release:
2385         hw->phy.ops.release(hw);
2386         return ret_val;
2387 }
2388
2389 /**
2390  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2391  *  @hw:   pointer to the HW structure
2392  *  @link: link up bool flag
2393  *
2394  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2395  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2396  *  If link is down, the function will restore the default K1 setting located
2397  *  in the NVM.
2398  **/
2399 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2400 {
2401         s32 ret_val = E1000_SUCCESS;
2402         u16 status_reg = 0;
2403         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2404
2405         DEBUGFUNC("e1000_k1_gig_workaround_hv");
2406
2407         if (hw->mac.type != e1000_pchlan)
2408                 return E1000_SUCCESS;
2409
2410         /* Wrap the whole flow with the sw flag */
2411         ret_val = hw->phy.ops.acquire(hw);
2412         if (ret_val)
2413                 return ret_val;
2414
2415         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2416         if (link) {
2417                 if (hw->phy.type == e1000_phy_82578) {
2418                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2419                                                               &status_reg);
2420                         if (ret_val)
2421                                 goto release;
2422
2423                         status_reg &= (BM_CS_STATUS_LINK_UP |
2424                                        BM_CS_STATUS_RESOLVED |
2425                                        BM_CS_STATUS_SPEED_MASK);
2426
2427                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2428                                            BM_CS_STATUS_RESOLVED |
2429                                            BM_CS_STATUS_SPEED_1000))
2430                                 k1_enable = FALSE;
2431                 }
2432
2433                 if (hw->phy.type == e1000_phy_82577) {
2434                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2435                                                               &status_reg);
2436                         if (ret_val)
2437                                 goto release;
2438
2439                         status_reg &= (HV_M_STATUS_LINK_UP |
2440                                        HV_M_STATUS_AUTONEG_COMPLETE |
2441                                        HV_M_STATUS_SPEED_MASK);
2442
2443                         if (status_reg == (HV_M_STATUS_LINK_UP |
2444                                            HV_M_STATUS_AUTONEG_COMPLETE |
2445                                            HV_M_STATUS_SPEED_1000))
2446                                 k1_enable = FALSE;
2447                 }
2448
2449                 /* Link stall fix for link up */
2450                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2451                                                        0x0100);
2452                 if (ret_val)
2453                         goto release;
2454
2455         } else {
2456                 /* Link stall fix for link down */
2457                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2458                                                        0x4100);
2459                 if (ret_val)
2460                         goto release;
2461         }
2462
2463         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2464
2465 release:
2466         hw->phy.ops.release(hw);
2467
2468         return ret_val;
2469 }
2470
2471 /**
2472  *  e1000_configure_k1_ich8lan - Configure K1 power state
2473  *  @hw: pointer to the HW structure
2474  *  @enable: K1 state to configure
2475  *
2476  *  Configure the K1 power state based on the provided parameter.
2477  *  Assumes semaphore already acquired.
2478  *
2479  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2480  **/
2481 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2482 {
2483         s32 ret_val;
2484         u32 ctrl_reg = 0;
2485         u32 ctrl_ext = 0;
2486         u32 reg = 0;
2487         u16 kmrn_reg = 0;
2488
2489         DEBUGFUNC("e1000_configure_k1_ich8lan");
2490
2491         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2492                                              &kmrn_reg);
2493         if (ret_val)
2494                 return ret_val;
2495
2496         if (k1_enable)
2497                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2498         else
2499                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2500
2501         ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2502                                               kmrn_reg);
2503         if (ret_val)
2504                 return ret_val;
2505
2506         usec_delay(20);
2507         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2508         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2509
2510         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2511         reg |= E1000_CTRL_FRCSPD;
2512         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2513
2514         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2515         E1000_WRITE_FLUSH(hw);
2516         usec_delay(20);
2517         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2518         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2519         E1000_WRITE_FLUSH(hw);
2520         usec_delay(20);
2521
2522         return E1000_SUCCESS;
2523 }
2524
2525 /**
2526  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2527  *  @hw:       pointer to the HW structure
2528  *  @d0_state: boolean if entering d0 or d3 device state
2529  *
2530  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2531  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2532  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2533  **/
2534 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2535 {
2536         s32 ret_val = 0;
2537         u32 mac_reg;
2538         u16 oem_reg;
2539
2540         DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2541
2542         if (hw->mac.type < e1000_pchlan)
2543                 return ret_val;
2544
2545         ret_val = hw->phy.ops.acquire(hw);
2546         if (ret_val)
2547                 return ret_val;
2548
2549         if (hw->mac.type == e1000_pchlan) {
2550                 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2551                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2552                         goto release;
2553         }
2554
2555         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2556         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2557                 goto release;
2558
2559         mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2560
2561         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2562         if (ret_val)
2563                 goto release;
2564
2565         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2566
2567         if (d0_state) {
2568                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2569                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2570
2571                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2572                         oem_reg |= HV_OEM_BITS_LPLU;
2573         } else {
2574                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2575                     E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2576                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2577
2578                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2579                     E1000_PHY_CTRL_NOND0A_LPLU))
2580                         oem_reg |= HV_OEM_BITS_LPLU;
2581         }
2582
2583         /* Set Restart auto-neg to activate the bits */
2584         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2585             !hw->phy.ops.check_reset_block(hw))
2586                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2587
2588         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2589
2590 release:
2591         hw->phy.ops.release(hw);
2592
2593         return ret_val;
2594 }
2595
2596
2597 /**
2598  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2599  *  @hw:   pointer to the HW structure
2600  **/
2601 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2602 {
2603         s32 ret_val;
2604         u16 data;
2605
2606         DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2607
2608         ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2609         if (ret_val)
2610                 return ret_val;
2611
2612         data |= HV_KMRN_MDIO_SLOW;
2613
2614         ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2615
2616         return ret_val;
2617 }
2618
2619 /**
2620  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2621  *  done after every PHY reset.
2622  **/
2623 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2624 {
2625         s32 ret_val = E1000_SUCCESS;
2626         u16 phy_data;
2627
2628         DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2629
2630         if (hw->mac.type != e1000_pchlan)
2631                 return E1000_SUCCESS;
2632
2633         /* Set MDIO slow mode before any other MDIO access */
2634         if (hw->phy.type == e1000_phy_82577) {
2635                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2636                 if (ret_val)
2637                         return ret_val;
2638         }
2639
2640         if (((hw->phy.type == e1000_phy_82577) &&
2641              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2642             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2643                 /* Disable generation of early preamble */
2644                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2645                 if (ret_val)
2646                         return ret_val;
2647
2648                 /* Preamble tuning for SSC */
2649                 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2650                                                 0xA204);
2651                 if (ret_val)
2652                         return ret_val;
2653         }
2654
2655         if (hw->phy.type == e1000_phy_82578) {
2656                 /* Return registers to default by doing a soft reset then
2657                  * writing 0x3140 to the control register.
2658                  */
2659                 if (hw->phy.revision < 2) {
2660                         e1000_phy_sw_reset_generic(hw);
2661                         ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2662                                                         0x3140);
2663                         if (ret_val)
2664                                 return ret_val;
2665                 }
2666         }
2667
2668         /* Select page 0 */
2669         ret_val = hw->phy.ops.acquire(hw);
2670         if (ret_val)
2671                 return ret_val;
2672
2673         hw->phy.addr = 1;
2674         ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2675         hw->phy.ops.release(hw);
2676         if (ret_val)
2677                 return ret_val;
2678
2679         /* Configure the K1 Si workaround during phy reset assuming there is
2680          * link so that it disables K1 if link is in 1Gbps.
2681          */
2682         ret_val = e1000_k1_gig_workaround_hv(hw, TRUE);
2683         if (ret_val)
2684                 return ret_val;
2685
2686         /* Workaround for link disconnects on a busy hub in half duplex */
2687         ret_val = hw->phy.ops.acquire(hw);
2688         if (ret_val)
2689                 return ret_val;
2690         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2691         if (ret_val)
2692                 goto release;
2693         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2694                                                phy_data & 0x00FF);
2695         if (ret_val)
2696                 goto release;
2697
2698         /* set MSE higher to enable link to stay up when noise is high */
2699         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2700 release:
2701         hw->phy.ops.release(hw);
2702
2703         return ret_val;
2704 }
2705
2706 /**
2707  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2708  *  @hw:   pointer to the HW structure
2709  **/
2710 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2711 {
2712         u32 mac_reg;
2713         u16 i, phy_reg = 0;
2714         s32 ret_val;
2715
2716         DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2717
2718         ret_val = hw->phy.ops.acquire(hw);
2719         if (ret_val)
2720                 return;
2721         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2722         if (ret_val)
2723                 goto release;
2724
2725         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2726         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2727                 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2728                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2729                                            (u16)(mac_reg & 0xFFFF));
2730                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2731                                            (u16)((mac_reg >> 16) & 0xFFFF));
2732
2733                 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2734                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2735                                            (u16)(mac_reg & 0xFFFF));
2736                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2737                                            (u16)((mac_reg & E1000_RAH_AV)
2738                                                  >> 16));
2739         }
2740
2741         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2742
2743 release:
2744         hw->phy.ops.release(hw);
2745 }
2746
2747 static u32 e1000_calc_rx_da_crc(u8 mac[])
2748 {
2749         u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
2750         u32 i, j, mask, crc;
2751
2752         DEBUGFUNC("e1000_calc_rx_da_crc");
2753
2754         crc = 0xffffffff;
2755         for (i = 0; i < 6; i++) {
2756                 crc = crc ^ mac[i];
2757                 for (j = 8; j > 0; j--) {
2758                         mask = (crc & 1) * (-1);
2759                         crc = (crc >> 1) ^ (poly & mask);
2760                 }
2761         }
2762         return ~crc;
2763 }
2764
2765 /**
2766  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2767  *  with 82579 PHY
2768  *  @hw: pointer to the HW structure
2769  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2770  **/
2771 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2772 {
2773         s32 ret_val = E1000_SUCCESS;
2774         u16 phy_reg, data;
2775         u32 mac_reg;
2776         u16 i;
2777
2778         DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2779
2780         if (hw->mac.type < e1000_pch2lan)
2781                 return E1000_SUCCESS;
2782
2783         /* disable Rx path while enabling/disabling workaround */
2784         hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2785         ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2786                                         phy_reg | (1 << 14));
2787         if (ret_val)
2788                 return ret_val;
2789
2790         if (enable) {
2791                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2792                  * SHRAL/H) and initial CRC values to the MAC
2793                  */
2794                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2795                         u8 mac_addr[ETH_ADDR_LEN] = {0};
2796                         u32 addr_high, addr_low;
2797
2798                         addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2799                         if (!(addr_high & E1000_RAH_AV))
2800                                 continue;
2801                         addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2802                         mac_addr[0] = (addr_low & 0xFF);
2803                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2804                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2805                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2806                         mac_addr[4] = (addr_high & 0xFF);
2807                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2808
2809                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2810                                         e1000_calc_rx_da_crc(mac_addr));
2811                 }
2812
2813                 /* Write Rx addresses to the PHY */
2814                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2815
2816                 /* Enable jumbo frame workaround in the MAC */
2817                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2818                 mac_reg &= ~(1 << 14);
2819                 mac_reg |= (7 << 15);
2820                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2821
2822                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2823                 mac_reg |= E1000_RCTL_SECRC;
2824                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2825
2826                 ret_val = e1000_read_kmrn_reg_generic(hw,
2827                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2828                                                 &data);
2829                 if (ret_val)
2830                         return ret_val;
2831                 ret_val = e1000_write_kmrn_reg_generic(hw,
2832                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2833                                                 data | (1 << 0));
2834                 if (ret_val)
2835                         return ret_val;
2836                 ret_val = e1000_read_kmrn_reg_generic(hw,
2837                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2838                                                 &data);
2839                 if (ret_val)
2840                         return ret_val;
2841                 data &= ~(0xF << 8);
2842                 data |= (0xB << 8);
2843                 ret_val = e1000_write_kmrn_reg_generic(hw,
2844                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2845                                                 data);
2846                 if (ret_val)
2847                         return ret_val;
2848
2849                 /* Enable jumbo frame workaround in the PHY */
2850                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2851                 data &= ~(0x7F << 5);
2852                 data |= (0x37 << 5);
2853                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2854                 if (ret_val)
2855                         return ret_val;
2856                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2857                 data &= ~(1 << 13);
2858                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2859                 if (ret_val)
2860                         return ret_val;
2861                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2862                 data &= ~(0x3FF << 2);
2863                 data |= (E1000_TX_PTR_GAP << 2);
2864                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2865                 if (ret_val)
2866                         return ret_val;
2867                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2868                 if (ret_val)
2869                         return ret_val;
2870                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2871                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2872                                                 (1 << 10));
2873                 if (ret_val)
2874                         return ret_val;
2875         } else {
2876                 /* Write MAC register values back to h/w defaults */
2877                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2878                 mac_reg &= ~(0xF << 14);
2879                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2880
2881                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2882                 mac_reg &= ~E1000_RCTL_SECRC;
2883                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2884
2885                 ret_val = e1000_read_kmrn_reg_generic(hw,
2886                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2887                                                 &data);
2888                 if (ret_val)
2889                         return ret_val;
2890                 ret_val = e1000_write_kmrn_reg_generic(hw,
2891                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2892                                                 data & ~(1 << 0));
2893                 if (ret_val)
2894                         return ret_val;
2895                 ret_val = e1000_read_kmrn_reg_generic(hw,
2896                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2897                                                 &data);
2898                 if (ret_val)
2899                         return ret_val;
2900                 data &= ~(0xF << 8);
2901                 data |= (0xB << 8);
2902                 ret_val = e1000_write_kmrn_reg_generic(hw,
2903                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2904                                                 data);
2905                 if (ret_val)
2906                         return ret_val;
2907
2908                 /* Write PHY register values back to h/w defaults */
2909                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2910                 data &= ~(0x7F << 5);
2911                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2912                 if (ret_val)
2913                         return ret_val;
2914                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2915                 data |= (1 << 13);
2916                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2917                 if (ret_val)
2918                         return ret_val;
2919                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2920                 data &= ~(0x3FF << 2);
2921                 data |= (0x8 << 2);
2922                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2923                 if (ret_val)
2924                         return ret_val;
2925                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2926                 if (ret_val)
2927                         return ret_val;
2928                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2929                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2930                                                 ~(1 << 10));
2931                 if (ret_val)
2932                         return ret_val;
2933         }
2934
2935         /* re-enable Rx path after enabling/disabling workaround */
2936         return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2937                                      ~(1 << 14));
2938 }
2939
2940 /**
2941  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2942  *  done after every PHY reset.
2943  **/
2944 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2945 {
2946         s32 ret_val = E1000_SUCCESS;
2947
2948         DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2949
2950         if (hw->mac.type != e1000_pch2lan)
2951                 return E1000_SUCCESS;
2952
2953         /* Set MDIO slow mode before any other MDIO access */
2954         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2955         if (ret_val)
2956                 return ret_val;
2957
2958         ret_val = hw->phy.ops.acquire(hw);
2959         if (ret_val)
2960                 return ret_val;
2961         /* set MSE higher to enable link to stay up when noise is high */
2962         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2963         if (ret_val)
2964                 goto release;
2965         /* drop link after 5 times MSE threshold was reached */
2966         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2967 release:
2968         hw->phy.ops.release(hw);
2969
2970         return ret_val;
2971 }
2972
2973 /**
2974  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2975  *  @hw:   pointer to the HW structure
2976  *
2977  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2978  *  Disable K1 for 1000 and 100 speeds
2979  **/
2980 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2981 {
2982         s32 ret_val = E1000_SUCCESS;
2983         u16 status_reg = 0;
2984
2985         DEBUGFUNC("e1000_k1_workaround_lv");
2986
2987         if (hw->mac.type != e1000_pch2lan)
2988                 return E1000_SUCCESS;
2989
2990         /* Set K1 beacon duration based on 10Mbs speed */
2991         ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2992         if (ret_val)
2993                 return ret_val;
2994
2995         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2996             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2997                 if (status_reg &
2998                     (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2999                         u16 pm_phy_reg;
3000
3001                         /* LV 1G/100 Packet drop issue wa  */
3002                         ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
3003                                                        &pm_phy_reg);
3004                         if (ret_val)
3005                                 return ret_val;
3006                         pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
3007                         ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
3008                                                         pm_phy_reg);
3009                         if (ret_val)
3010                                 return ret_val;
3011                 } else {
3012                         u32 mac_reg;
3013                         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
3014                         mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
3015                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
3016                         E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
3017                 }
3018         }
3019
3020         return ret_val;
3021 }
3022
3023 /**
3024  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
3025  *  @hw:   pointer to the HW structure
3026  *  @gate: boolean set to TRUE to gate, FALSE to ungate
3027  *
3028  *  Gate/ungate the automatic PHY configuration via hardware; perform
3029  *  the configuration via software instead.
3030  **/
3031 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
3032 {
3033         u32 extcnf_ctrl;
3034
3035         DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
3036
3037         if (hw->mac.type < e1000_pch2lan)
3038                 return;
3039
3040         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
3041
3042         if (gate)
3043                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
3044         else
3045                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
3046
3047         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
3048 }
3049
3050 /**
3051  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
3052  *  @hw: pointer to the HW structure
3053  *
3054  *  Check the appropriate indication the MAC has finished configuring the
3055  *  PHY after a software reset.
3056  **/
3057 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
3058 {
3059         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
3060
3061         DEBUGFUNC("e1000_lan_init_done_ich8lan");
3062
3063         /* Wait for basic configuration completes before proceeding */
3064         do {
3065                 data = E1000_READ_REG(hw, E1000_STATUS);
3066                 data &= E1000_STATUS_LAN_INIT_DONE;
3067                 usec_delay(100);
3068         } while ((!data) && --loop);
3069
3070         /* If basic configuration is incomplete before the above loop
3071          * count reaches 0, loading the configuration from NVM will
3072          * leave the PHY in a bad state possibly resulting in no link.
3073          */
3074         if (loop == 0)
3075                 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
3076
3077         /* Clear the Init Done bit for the next init event */
3078         data = E1000_READ_REG(hw, E1000_STATUS);
3079         data &= ~E1000_STATUS_LAN_INIT_DONE;
3080         E1000_WRITE_REG(hw, E1000_STATUS, data);
3081 }
3082
3083 /**
3084  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
3085  *  @hw: pointer to the HW structure
3086  **/
3087 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
3088 {
3089         s32 ret_val = E1000_SUCCESS;
3090         u16 reg;
3091
3092         DEBUGFUNC("e1000_post_phy_reset_ich8lan");
3093
3094         if (hw->phy.ops.check_reset_block(hw))
3095                 return E1000_SUCCESS;
3096
3097         /* Allow time for h/w to get to quiescent state after reset */
3098         msec_delay(10);
3099
3100         /* Perform any necessary post-reset workarounds */
3101         switch (hw->mac.type) {
3102         case e1000_pchlan:
3103                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
3104                 if (ret_val)
3105                         return ret_val;
3106                 break;
3107         case e1000_pch2lan:
3108                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
3109                 if (ret_val)
3110                         return ret_val;
3111                 break;
3112         default:
3113                 break;
3114         }
3115
3116         /* Clear the host wakeup bit after lcd reset */
3117         if (hw->mac.type >= e1000_pchlan) {
3118                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);
3119                 reg &= ~BM_WUC_HOST_WU_BIT;
3120                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
3121         }
3122
3123         /* Configure the LCD with the extended configuration region in NVM */
3124         ret_val = e1000_sw_lcd_config_ich8lan(hw);
3125         if (ret_val)
3126                 return ret_val;
3127
3128         /* Configure the LCD with the OEM bits in NVM */
3129         ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE);
3130
3131         if (hw->mac.type == e1000_pch2lan) {
3132                 /* Ungate automatic PHY configuration on non-managed 82579 */
3133                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
3134                     E1000_ICH_FWSM_FW_VALID)) {
3135                         msec_delay(10);
3136                         e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
3137                 }
3138
3139                 /* Set EEE LPI Update Timer to 200usec */
3140                 ret_val = hw->phy.ops.acquire(hw);
3141                 if (ret_val)
3142                         return ret_val;
3143                 ret_val = e1000_write_emi_reg_locked(hw,
3144                                                      I82579_LPI_UPDATE_TIMER,
3145                                                      0x1387);
3146                 hw->phy.ops.release(hw);
3147         }
3148
3149         return ret_val;
3150 }
3151
3152 /**
3153  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
3154  *  @hw: pointer to the HW structure
3155  *
3156  *  Resets the PHY
3157  *  This is a function pointer entry point called by drivers
3158  *  or other shared routines.
3159  **/
3160 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
3161 {
3162         s32 ret_val = E1000_SUCCESS;
3163
3164         DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
3165
3166         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
3167         if ((hw->mac.type == e1000_pch2lan) &&
3168             !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3169                 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
3170
3171         ret_val = e1000_phy_hw_reset_generic(hw);
3172         if (ret_val)
3173                 return ret_val;
3174
3175         return e1000_post_phy_reset_ich8lan(hw);
3176 }
3177
3178 /**
3179  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
3180  *  @hw: pointer to the HW structure
3181  *  @active: TRUE to enable LPLU, FALSE to disable
3182  *
3183  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
3184  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
3185  *  the phy speed. This function will manually set the LPLU bit and restart
3186  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
3187  *  since it configures the same bit.
3188  **/
3189 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
3190 {
3191         s32 ret_val;
3192         u16 oem_reg;
3193
3194         DEBUGFUNC("e1000_set_lplu_state_pchlan");
3195         ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3196         if (ret_val)
3197                 return ret_val;
3198
3199         if (active)
3200                 oem_reg |= HV_OEM_BITS_LPLU;
3201         else
3202                 oem_reg &= ~HV_OEM_BITS_LPLU;
3203
3204         if (!hw->phy.ops.check_reset_block(hw))
3205                 oem_reg |= HV_OEM_BITS_RESTART_AN;
3206
3207         return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3208 }
3209
3210 /**
3211  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3212  *  @hw: pointer to the HW structure
3213  *  @active: TRUE to enable LPLU, FALSE to disable
3214  *
3215  *  Sets the LPLU D0 state according to the active flag.  When
3216  *  activating LPLU this function also disables smart speed
3217  *  and vice versa.  LPLU will not be activated unless the
3218  *  device autonegotiation advertisement meets standards of
3219  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3220  *  This is a function pointer entry point only called by
3221  *  PHY setup routines.
3222  **/
3223 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3224 {
3225         struct e1000_phy_info *phy = &hw->phy;
3226         u32 phy_ctrl;
3227         s32 ret_val = E1000_SUCCESS;
3228         u16 data;
3229
3230         DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3231
3232         if (phy->type == e1000_phy_ife)
3233                 return E1000_SUCCESS;
3234
3235         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3236
3237         if (active) {
3238                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3239                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3240
3241                 if (phy->type != e1000_phy_igp_3)
3242                         return E1000_SUCCESS;
3243
3244                 /* Call gig speed drop workaround on LPLU before accessing
3245                  * any PHY registers
3246                  */
3247                 if (hw->mac.type == e1000_ich8lan)
3248                         e1000_gig_downshift_workaround_ich8lan(hw);
3249
3250                 /* When LPLU is enabled, we should disable SmartSpeed */
3251                 ret_val = phy->ops.read_reg(hw,
3252                                             IGP01E1000_PHY_PORT_CONFIG,
3253                                             &data);
3254                 if (ret_val)
3255                         return ret_val;
3256                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3257                 ret_val = phy->ops.write_reg(hw,
3258                                              IGP01E1000_PHY_PORT_CONFIG,
3259                                              data);
3260                 if (ret_val)
3261                         return ret_val;
3262         } else {
3263                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3264                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3265
3266                 if (phy->type != e1000_phy_igp_3)
3267                         return E1000_SUCCESS;
3268
3269                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3270                  * during Dx states where the power conservation is most
3271                  * important.  During driver activity we should enable
3272                  * SmartSpeed, so performance is maintained.
3273                  */
3274                 if (phy->smart_speed == e1000_smart_speed_on) {
3275                         ret_val = phy->ops.read_reg(hw,
3276                                                     IGP01E1000_PHY_PORT_CONFIG,
3277                                                     &data);
3278                         if (ret_val)
3279                                 return ret_val;
3280
3281                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3282                         ret_val = phy->ops.write_reg(hw,
3283                                                      IGP01E1000_PHY_PORT_CONFIG,
3284                                                      data);
3285                         if (ret_val)
3286                                 return ret_val;
3287                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3288                         ret_val = phy->ops.read_reg(hw,
3289                                                     IGP01E1000_PHY_PORT_CONFIG,
3290                                                     &data);
3291                         if (ret_val)
3292                                 return ret_val;
3293
3294                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3295                         ret_val = phy->ops.write_reg(hw,
3296                                                      IGP01E1000_PHY_PORT_CONFIG,
3297                                                      data);
3298                         if (ret_val)
3299                                 return ret_val;
3300                 }
3301         }
3302
3303         return E1000_SUCCESS;
3304 }
3305
3306 /**
3307  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3308  *  @hw: pointer to the HW structure
3309  *  @active: TRUE to enable LPLU, FALSE to disable
3310  *
3311  *  Sets the LPLU D3 state according to the active flag.  When
3312  *  activating LPLU this function also disables smart speed
3313  *  and vice versa.  LPLU will not be activated unless the
3314  *  device autonegotiation advertisement meets standards of
3315  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3316  *  This is a function pointer entry point only called by
3317  *  PHY setup routines.
3318  **/
3319 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3320 {
3321         struct e1000_phy_info *phy = &hw->phy;
3322         u32 phy_ctrl;
3323         s32 ret_val = E1000_SUCCESS;
3324         u16 data;
3325
3326         DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3327
3328         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3329
3330         if (!active) {
3331                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3332                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3333
3334                 if (phy->type != e1000_phy_igp_3)
3335                         return E1000_SUCCESS;
3336
3337                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3338                  * during Dx states where the power conservation is most
3339                  * important.  During driver activity we should enable
3340                  * SmartSpeed, so performance is maintained.
3341                  */
3342                 if (phy->smart_speed == e1000_smart_speed_on) {
3343                         ret_val = phy->ops.read_reg(hw,
3344                                                     IGP01E1000_PHY_PORT_CONFIG,
3345                                                     &data);
3346                         if (ret_val)
3347                                 return ret_val;
3348
3349                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3350                         ret_val = phy->ops.write_reg(hw,
3351                                                      IGP01E1000_PHY_PORT_CONFIG,
3352                                                      data);
3353                         if (ret_val)
3354                                 return ret_val;
3355                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3356                         ret_val = phy->ops.read_reg(hw,
3357                                                     IGP01E1000_PHY_PORT_CONFIG,
3358                                                     &data);
3359                         if (ret_val)
3360                                 return ret_val;
3361
3362                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3363                         ret_val = phy->ops.write_reg(hw,
3364                                                      IGP01E1000_PHY_PORT_CONFIG,
3365                                                      data);
3366                         if (ret_val)
3367                                 return ret_val;
3368                 }
3369         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3370                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3371                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3372                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3373                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3374
3375                 if (phy->type != e1000_phy_igp_3)
3376                         return E1000_SUCCESS;
3377
3378                 /* Call gig speed drop workaround on LPLU before accessing
3379                  * any PHY registers
3380                  */
3381                 if (hw->mac.type == e1000_ich8lan)
3382                         e1000_gig_downshift_workaround_ich8lan(hw);
3383
3384                 /* When LPLU is enabled, we should disable SmartSpeed */
3385                 ret_val = phy->ops.read_reg(hw,
3386                                             IGP01E1000_PHY_PORT_CONFIG,
3387                                             &data);
3388                 if (ret_val)
3389                         return ret_val;
3390
3391                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3392                 ret_val = phy->ops.write_reg(hw,
3393                                              IGP01E1000_PHY_PORT_CONFIG,
3394                                              data);
3395         }
3396
3397         return ret_val;
3398 }
3399
3400 /**
3401  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3402  *  @hw: pointer to the HW structure
3403  *  @bank:  pointer to the variable that returns the active bank
3404  *
3405  *  Reads signature byte from the NVM using the flash access registers.
3406  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3407  **/
3408 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3409 {
3410         u32 eecd;
3411         struct e1000_nvm_info *nvm = &hw->nvm;
3412         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3413         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3414         u32 nvm_dword = 0;
3415         u8 sig_byte = 0;
3416         s32 ret_val;
3417
3418         DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3419
3420         switch (hw->mac.type) {
3421         case e1000_pch_spt:
3422         case e1000_pch_cnp:
3423                 bank1_offset = nvm->flash_bank_size;
3424                 act_offset = E1000_ICH_NVM_SIG_WORD;
3425
3426                 /* set bank to 0 in case flash read fails */
3427                 *bank = 0;
3428
3429                 /* Check bank 0 */
3430                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3431                                                          &nvm_dword);
3432                 if (ret_val)
3433                         return ret_val;
3434                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3435                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3436                     E1000_ICH_NVM_SIG_VALUE) {
3437                         *bank = 0;
3438                         return E1000_SUCCESS;
3439                 }
3440
3441                 /* Check bank 1 */
3442                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3443                                                          bank1_offset,
3444                                                          &nvm_dword);
3445                 if (ret_val)
3446                         return ret_val;
3447                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3448                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3449                     E1000_ICH_NVM_SIG_VALUE) {
3450                         *bank = 1;
3451                         return E1000_SUCCESS;
3452                 }
3453
3454                 DEBUGOUT("ERROR: No valid NVM bank present\n");
3455                 return -E1000_ERR_NVM;
3456         case e1000_ich8lan:
3457         case e1000_ich9lan:
3458                 eecd = E1000_READ_REG(hw, E1000_EECD);
3459                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3460                     E1000_EECD_SEC1VAL_VALID_MASK) {
3461                         if (eecd & E1000_EECD_SEC1VAL)
3462                                 *bank = 1;
3463                         else
3464                                 *bank = 0;
3465
3466                         return E1000_SUCCESS;
3467                 }
3468                 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3469                 /* fall-thru */
3470         default:
3471                 /* set bank to 0 in case flash read fails */
3472                 *bank = 0;
3473
3474                 /* Check bank 0 */
3475                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3476                                                         &sig_byte);
3477                 if (ret_val)
3478                         return ret_val;
3479                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3480                     E1000_ICH_NVM_SIG_VALUE) {
3481                         *bank = 0;
3482                         return E1000_SUCCESS;
3483                 }
3484
3485                 /* Check bank 1 */
3486                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3487                                                         bank1_offset,
3488                                                         &sig_byte);
3489                 if (ret_val)
3490                         return ret_val;
3491                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3492                     E1000_ICH_NVM_SIG_VALUE) {
3493                         *bank = 1;
3494                         return E1000_SUCCESS;
3495                 }
3496
3497                 DEBUGOUT("ERROR: No valid NVM bank present\n");
3498                 return -E1000_ERR_NVM;
3499         }
3500 }
3501
3502 /**
3503  *  e1000_read_nvm_spt - NVM access for SPT
3504  *  @hw: pointer to the HW structure
3505  *  @offset: The offset (in bytes) of the word(s) to read.
3506  *  @words: Size of data to read in words.
3507  *  @data: pointer to the word(s) to read at offset.
3508  *
3509  *  Reads a word(s) from the NVM
3510  **/
3511 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3512                               u16 *data)
3513 {
3514         struct e1000_nvm_info *nvm = &hw->nvm;
3515         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3516         u32 act_offset;
3517         s32 ret_val = E1000_SUCCESS;
3518         u32 bank = 0;
3519         u32 dword = 0;
3520         u16 offset_to_read;
3521         u16 i;
3522
3523         DEBUGFUNC("e1000_read_nvm_spt");
3524
3525         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3526             (words == 0)) {
3527                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3528                 ret_val = -E1000_ERR_NVM;
3529                 goto out;
3530         }
3531
3532         nvm->ops.acquire(hw);
3533
3534         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3535         if (ret_val != E1000_SUCCESS) {
3536                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3537                 bank = 0;
3538         }
3539
3540         act_offset = (bank) ? nvm->flash_bank_size : 0;
3541         act_offset += offset;
3542
3543         ret_val = E1000_SUCCESS;
3544
3545         for (i = 0; i < words; i += 2) {
3546                 if (words - i == 1) {
3547                         if (dev_spec->shadow_ram[offset+i].modified) {
3548                                 data[i] = dev_spec->shadow_ram[offset+i].value;
3549                         } else {
3550                                 offset_to_read = act_offset + i -
3551                                                  ((act_offset + i) % 2);
3552                                 ret_val =
3553                                    e1000_read_flash_dword_ich8lan(hw,
3554                                                                  offset_to_read,
3555                                                                  &dword);
3556                                 if (ret_val)
3557                                         break;
3558                                 if ((act_offset + i) % 2 == 0)
3559                                         data[i] = (u16)(dword & 0xFFFF);
3560                                 else
3561                                         data[i] = (u16)((dword >> 16) & 0xFFFF);
3562                         }
3563                 } else {
3564                         offset_to_read = act_offset + i;
3565                         if (!(dev_spec->shadow_ram[offset+i].modified) ||
3566                             !(dev_spec->shadow_ram[offset+i+1].modified)) {
3567                                 ret_val =
3568                                    e1000_read_flash_dword_ich8lan(hw,
3569                                                                  offset_to_read,
3570                                                                  &dword);
3571                                 if (ret_val)
3572                                         break;
3573                         }
3574                         if (dev_spec->shadow_ram[offset+i].modified)
3575                                 data[i] = dev_spec->shadow_ram[offset+i].value;
3576                         else
3577                                 data[i] = (u16) (dword & 0xFFFF);
3578                         if (dev_spec->shadow_ram[offset+i].modified)
3579                                 data[i+1] =
3580                                    dev_spec->shadow_ram[offset+i+1].value;
3581                         else
3582                                 data[i+1] = (u16) (dword >> 16 & 0xFFFF);
3583                 }
3584         }
3585
3586         nvm->ops.release(hw);
3587
3588 out:
3589         if (ret_val)
3590                 DEBUGOUT1("NVM read error: %d\n", ret_val);
3591
3592         return ret_val;
3593 }
3594
3595 /**
3596  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3597  *  @hw: pointer to the HW structure
3598  *  @offset: The offset (in bytes) of the word(s) to read.
3599  *  @words: Size of data to read in words
3600  *  @data: Pointer to the word(s) to read at offset.
3601  *
3602  *  Reads a word(s) from the NVM using the flash access registers.
3603  **/
3604 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3605                                   u16 *data)
3606 {
3607         struct e1000_nvm_info *nvm = &hw->nvm;
3608         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3609         u32 act_offset;
3610         s32 ret_val = E1000_SUCCESS;
3611         u32 bank = 0;
3612         u16 i, word;
3613
3614         DEBUGFUNC("e1000_read_nvm_ich8lan");
3615
3616         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3617             (words == 0)) {
3618                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3619                 ret_val = -E1000_ERR_NVM;
3620                 goto out;
3621         }
3622
3623         nvm->ops.acquire(hw);
3624
3625         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3626         if (ret_val != E1000_SUCCESS) {
3627                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3628                 bank = 0;
3629         }
3630
3631         act_offset = (bank) ? nvm->flash_bank_size : 0;
3632         act_offset += offset;
3633
3634         ret_val = E1000_SUCCESS;
3635         for (i = 0; i < words; i++) {
3636                 if (dev_spec->shadow_ram[offset+i].modified) {
3637                         data[i] = dev_spec->shadow_ram[offset+i].value;
3638                 } else {
3639                         ret_val = e1000_read_flash_word_ich8lan(hw,
3640                                                                 act_offset + i,
3641                                                                 &word);
3642                         if (ret_val)
3643                                 break;
3644                         data[i] = word;
3645                 }
3646         }
3647
3648         nvm->ops.release(hw);
3649
3650 out:
3651         if (ret_val)
3652                 DEBUGOUT1("NVM read error: %d\n", ret_val);
3653
3654         return ret_val;
3655 }
3656
3657 /**
3658  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3659  *  @hw: pointer to the HW structure
3660  *
3661  *  This function does initial flash setup so that a new read/write/erase cycle
3662  *  can be started.
3663  **/
3664 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3665 {
3666         union ich8_hws_flash_status hsfsts;
3667         s32 ret_val = -E1000_ERR_NVM;
3668
3669         DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3670
3671         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3672
3673         /* Check if the flash descriptor is valid */
3674         if (!hsfsts.hsf_status.fldesvalid) {
3675                 DEBUGOUT("Flash descriptor invalid.  SW Sequencing must be used.\n");
3676                 return -E1000_ERR_NVM;
3677         }
3678
3679         /* Clear FCERR and DAEL in hw status by writing 1 */
3680         hsfsts.hsf_status.flcerr = 1;
3681         hsfsts.hsf_status.dael = 1;
3682         if (hw->mac.type >= e1000_pch_spt)
3683                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3684                                       hsfsts.regval & 0xFFFF);
3685         else
3686                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3687
3688         /* Either we should have a hardware SPI cycle in progress
3689          * bit to check against, in order to start a new cycle or
3690          * FDONE bit should be changed in the hardware so that it
3691          * is 1 after hardware reset, which can then be used as an
3692          * indication whether a cycle is in progress or has been
3693          * completed.
3694          */
3695
3696         if (!hsfsts.hsf_status.flcinprog) {
3697                 /* There is no cycle running at present,
3698                  * so we can start a cycle.
3699                  * Begin by setting Flash Cycle Done.
3700                  */
3701                 hsfsts.hsf_status.flcdone = 1;
3702                 if (hw->mac.type >= e1000_pch_spt)
3703                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3704                                               hsfsts.regval & 0xFFFF);
3705                 else
3706                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3707                                                 hsfsts.regval);
3708                 ret_val = E1000_SUCCESS;
3709         } else {
3710                 s32 i;
3711
3712                 /* Otherwise poll for sometime so the current
3713                  * cycle has a chance to end before giving up.
3714                  */
3715                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3716                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3717                                                               ICH_FLASH_HSFSTS);
3718                         if (!hsfsts.hsf_status.flcinprog) {
3719                                 ret_val = E1000_SUCCESS;
3720                                 break;
3721                         }
3722                         usec_delay(1);
3723                 }
3724                 if (ret_val == E1000_SUCCESS) {
3725                         /* Successful in waiting for previous cycle to timeout,
3726                          * now set the Flash Cycle Done.
3727                          */
3728                         hsfsts.hsf_status.flcdone = 1;
3729                         if (hw->mac.type >= e1000_pch_spt)
3730                                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3731                                                       hsfsts.regval & 0xFFFF);
3732                         else
3733                                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3734                                                         hsfsts.regval);
3735                 } else {
3736                         DEBUGOUT("Flash controller busy, cannot get access\n");
3737                 }
3738         }
3739
3740         return ret_val;
3741 }
3742
3743 /**
3744  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3745  *  @hw: pointer to the HW structure
3746  *  @timeout: maximum time to wait for completion
3747  *
3748  *  This function starts a flash cycle and waits for its completion.
3749  **/
3750 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3751 {
3752         union ich8_hws_flash_ctrl hsflctl;
3753         union ich8_hws_flash_status hsfsts;
3754         u32 i = 0;
3755
3756         DEBUGFUNC("e1000_flash_cycle_ich8lan");
3757
3758         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3759         if (hw->mac.type >= e1000_pch_spt)
3760                 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3761         else
3762                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3763         hsflctl.hsf_ctrl.flcgo = 1;
3764
3765         if (hw->mac.type >= e1000_pch_spt)
3766                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3767                                       hsflctl.regval << 16);
3768         else
3769                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3770
3771         /* wait till FDONE bit is set to 1 */
3772         do {
3773                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3774                 if (hsfsts.hsf_status.flcdone)
3775                         break;
3776                 usec_delay(1);
3777         } while (i++ < timeout);
3778
3779         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3780                 return E1000_SUCCESS;
3781
3782         return -E1000_ERR_NVM;
3783 }
3784
3785 /**
3786  *  e1000_read_flash_dword_ich8lan - Read dword from flash
3787  *  @hw: pointer to the HW structure
3788  *  @offset: offset to data location
3789  *  @data: pointer to the location for storing the data
3790  *
3791  *  Reads the flash dword at offset into data.  Offset is converted
3792  *  to bytes before read.
3793  **/
3794 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3795                                           u32 *data)
3796 {
3797         DEBUGFUNC("e1000_read_flash_dword_ich8lan");
3798
3799         if (!data)
3800                 return -E1000_ERR_NVM;
3801
3802         /* Must convert word offset into bytes. */
3803         offset <<= 1;
3804
3805         return e1000_read_flash_data32_ich8lan(hw, offset, data);
3806 }
3807
3808 /**
3809  *  e1000_read_flash_word_ich8lan - Read word from flash
3810  *  @hw: pointer to the HW structure
3811  *  @offset: offset to data location
3812  *  @data: pointer to the location for storing the data
3813  *
3814  *  Reads the flash word at offset into data.  Offset is converted
3815  *  to bytes before read.
3816  **/
3817 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3818                                          u16 *data)
3819 {
3820         DEBUGFUNC("e1000_read_flash_word_ich8lan");
3821
3822         if (!data)
3823                 return -E1000_ERR_NVM;
3824
3825         /* Must convert offset into bytes. */
3826         offset <<= 1;
3827
3828         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3829 }
3830
3831 /**
3832  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3833  *  @hw: pointer to the HW structure
3834  *  @offset: The offset of the byte to read.
3835  *  @data: Pointer to a byte to store the value read.
3836  *
3837  *  Reads a single byte from the NVM using the flash access registers.
3838  **/
3839 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3840                                          u8 *data)
3841 {
3842         s32 ret_val;
3843         u16 word = 0;
3844
3845         /* In SPT, only 32 bits access is supported,
3846          * so this function should not be called.
3847          */
3848         if (hw->mac.type >= e1000_pch_spt)
3849                 return -E1000_ERR_NVM;
3850         else
3851                 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3852
3853         if (ret_val)
3854                 return ret_val;
3855
3856         *data = (u8)word;
3857
3858         return E1000_SUCCESS;
3859 }
3860
3861 /**
3862  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3863  *  @hw: pointer to the HW structure
3864  *  @offset: The offset (in bytes) of the byte or word to read.
3865  *  @size: Size of data to read, 1=byte 2=word
3866  *  @data: Pointer to the word to store the value read.
3867  *
3868  *  Reads a byte or word from the NVM using the flash access registers.
3869  **/
3870 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3871                                          u8 size, u16 *data)
3872 {
3873         union ich8_hws_flash_status hsfsts;
3874         union ich8_hws_flash_ctrl hsflctl;
3875         u32 flash_linear_addr;
3876         u32 flash_data = 0;
3877         s32 ret_val = -E1000_ERR_NVM;
3878         u8 count = 0;
3879
3880         DEBUGFUNC("e1000_read_flash_data_ich8lan");
3881
3882         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3883                 return -E1000_ERR_NVM;
3884         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3885                              hw->nvm.flash_base_addr);
3886
3887         do {
3888                 usec_delay(1);
3889                 /* Steps */
3890                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3891                 if (ret_val != E1000_SUCCESS)
3892                         break;
3893                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3894
3895                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3896                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3897                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3898                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3899                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3900
3901                 ret_val = e1000_flash_cycle_ich8lan(hw,
3902                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
3903
3904                 /* Check if FCERR is set to 1, if set to 1, clear it
3905                  * and try the whole sequence a few more times, else
3906                  * read in (shift in) the Flash Data0, the order is
3907                  * least significant byte first msb to lsb
3908                  */
3909                 if (ret_val == E1000_SUCCESS) {
3910                         flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3911                         if (size == 1)
3912                                 *data = (u8)(flash_data & 0x000000FF);
3913                         else if (size == 2)
3914                                 *data = (u16)(flash_data & 0x0000FFFF);
3915                         break;
3916                 } else {
3917                         /* If we've gotten here, then things are probably
3918                          * completely hosed, but if the error condition is
3919                          * detected, it won't hurt to give it another try...
3920                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3921                          */
3922                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3923                                                               ICH_FLASH_HSFSTS);
3924                         if (hsfsts.hsf_status.flcerr) {
3925                                 /* Repeat for some time before giving up. */
3926                                 continue;
3927                         } else if (!hsfsts.hsf_status.flcdone) {
3928                                 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3929                                 break;
3930                         }
3931                 }
3932         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3933
3934         return ret_val;
3935 }
3936
3937 /**
3938  *  e1000_read_flash_data32_ich8lan - Read dword from NVM
3939  *  @hw: pointer to the HW structure
3940  *  @offset: The offset (in bytes) of the dword to read.
3941  *  @data: Pointer to the dword to store the value read.
3942  *
3943  *  Reads a byte or word from the NVM using the flash access registers.
3944  **/
3945 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3946                                            u32 *data)
3947 {
3948         union ich8_hws_flash_status hsfsts;
3949         union ich8_hws_flash_ctrl hsflctl;
3950         u32 flash_linear_addr;
3951         s32 ret_val = -E1000_ERR_NVM;
3952         u8 count = 0;
3953
3954         DEBUGFUNC("e1000_read_flash_data_ich8lan");
3955
3956                 if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3957                     hw->mac.type < e1000_pch_spt)
3958                         return -E1000_ERR_NVM;
3959         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3960                              hw->nvm.flash_base_addr);
3961
3962         do {
3963                 usec_delay(1);
3964                 /* Steps */
3965                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3966                 if (ret_val != E1000_SUCCESS)
3967                         break;
3968                 /* In SPT, This register is in Lan memory space, not flash.
3969                  * Therefore, only 32 bit access is supported
3970                  */
3971                 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3972
3973                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3974                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3975                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3976                 /* In SPT, This register is in Lan memory space, not flash.
3977                  * Therefore, only 32 bit access is supported
3978                  */
3979                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3980                                       (u32)hsflctl.regval << 16);
3981                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3982
3983                 ret_val = e1000_flash_cycle_ich8lan(hw,
3984                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
3985
3986                 /* Check if FCERR is set to 1, if set to 1, clear it
3987                  * and try the whole sequence a few more times, else
3988                  * read in (shift in) the Flash Data0, the order is
3989                  * least significant byte first msb to lsb
3990                  */
3991                 if (ret_val == E1000_SUCCESS) {
3992                         *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3993                         break;
3994                 } else {
3995                         /* If we've gotten here, then things are probably
3996                          * completely hosed, but if the error condition is
3997                          * detected, it won't hurt to give it another try...
3998                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3999                          */
4000                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4001                                                               ICH_FLASH_HSFSTS);
4002                         if (hsfsts.hsf_status.flcerr) {
4003                                 /* Repeat for some time before giving up. */
4004                                 continue;
4005                         } else if (!hsfsts.hsf_status.flcdone) {
4006                                 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4007                                 break;
4008                         }
4009                 }
4010         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4011
4012         return ret_val;
4013 }
4014
4015 /**
4016  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
4017  *  @hw: pointer to the HW structure
4018  *  @offset: The offset (in bytes) of the word(s) to write.
4019  *  @words: Size of data to write in words
4020  *  @data: Pointer to the word(s) to write at offset.
4021  *
4022  *  Writes a byte or word to the NVM using the flash access registers.
4023  **/
4024 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
4025                                    u16 *data)
4026 {
4027         struct e1000_nvm_info *nvm = &hw->nvm;
4028         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4029         u16 i;
4030
4031         DEBUGFUNC("e1000_write_nvm_ich8lan");
4032
4033         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
4034             (words == 0)) {
4035                 DEBUGOUT("nvm parameter(s) out of bounds\n");
4036                 return -E1000_ERR_NVM;
4037         }
4038
4039         nvm->ops.acquire(hw);
4040
4041         for (i = 0; i < words; i++) {
4042                 dev_spec->shadow_ram[offset+i].modified = TRUE;
4043                 dev_spec->shadow_ram[offset+i].value = data[i];
4044         }
4045
4046         nvm->ops.release(hw);
4047
4048         return E1000_SUCCESS;
4049 }
4050
4051 /**
4052  *  e1000_update_nvm_checksum_spt - Update the checksum for NVM
4053  *  @hw: pointer to the HW structure
4054  *
4055  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
4056  *  which writes the checksum to the shadow ram.  The changes in the shadow
4057  *  ram are then committed to the EEPROM by processing each bank at a time
4058  *  checking for the modified bit and writing only the pending changes.
4059  *  After a successful commit, the shadow ram is cleared and is ready for
4060  *  future writes.
4061  **/
4062 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
4063 {
4064         struct e1000_nvm_info *nvm = &hw->nvm;
4065         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4066         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4067         s32 ret_val;
4068         u32 dword = 0;
4069
4070         DEBUGFUNC("e1000_update_nvm_checksum_spt");
4071
4072         ret_val = e1000_update_nvm_checksum_generic(hw);
4073         if (ret_val)
4074                 goto out;
4075
4076         if (nvm->type != e1000_nvm_flash_sw)
4077                 goto out;
4078
4079         nvm->ops.acquire(hw);
4080
4081         /* We're writing to the opposite bank so if we're on bank 1,
4082          * write to bank 0 etc.  We also need to erase the segment that
4083          * is going to be written
4084          */
4085         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4086         if (ret_val != E1000_SUCCESS) {
4087                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4088                 bank = 0;
4089         }
4090
4091         if (bank == 0) {
4092                 new_bank_offset = nvm->flash_bank_size;
4093                 old_bank_offset = 0;
4094                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4095                 if (ret_val)
4096                         goto release;
4097         } else {
4098                 old_bank_offset = nvm->flash_bank_size;
4099                 new_bank_offset = 0;
4100                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4101                 if (ret_val)
4102                         goto release;
4103         }
4104         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) {
4105                 /* Determine whether to write the value stored
4106                  * in the other NVM bank or a modified value stored
4107                  * in the shadow RAM
4108                  */
4109                 ret_val = e1000_read_flash_dword_ich8lan(hw,
4110                                                          i + old_bank_offset,
4111                                                          &dword);
4112
4113                 if (dev_spec->shadow_ram[i].modified) {
4114                         dword &= 0xffff0000;
4115                         dword |= (dev_spec->shadow_ram[i].value & 0xffff);
4116                 }
4117                 if (dev_spec->shadow_ram[i + 1].modified) {
4118                         dword &= 0x0000ffff;
4119                         dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
4120                                   << 16);
4121                 }
4122                 if (ret_val)
4123                         break;
4124
4125                 /* If the word is 0x13, then make sure the signature bits
4126                  * (15:14) are 11b until the commit has completed.
4127                  * This will allow us to write 10b which indicates the
4128                  * signature is valid.  We want to do this after the write
4129                  * has completed so that we don't mark the segment valid
4130                  * while the write is still in progress
4131                  */
4132                 if (i == E1000_ICH_NVM_SIG_WORD - 1)
4133                         dword |= E1000_ICH_NVM_SIG_MASK << 16;
4134
4135                 /* Convert offset to bytes. */
4136                 act_offset = (i + new_bank_offset) << 1;
4137
4138                 usec_delay(100);
4139
4140                 /* Write the data to the new bank. Offset in words*/
4141                 act_offset = i + new_bank_offset;
4142                 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4143                                                                 dword);
4144                 if (ret_val)
4145                         break;
4146          }
4147
4148         /* Don't bother writing the segment valid bits if sector
4149          * programming failed.
4150          */
4151         if (ret_val) {
4152                 DEBUGOUT("Flash commit failed.\n");
4153                 goto release;
4154         }
4155
4156         /* Finally validate the new segment by setting bit 15:14
4157          * to 10b in word 0x13 , this can be done without an
4158          * erase as well since these bits are 11 to start with
4159          * and we need to change bit 14 to 0b
4160          */
4161         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4162
4163         /*offset in words but we read dword*/
4164         --act_offset;
4165         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4166
4167         if (ret_val)
4168                 goto release;
4169
4170         dword &= 0xBFFFFFFF;
4171         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4172
4173         if (ret_val)
4174                 goto release;
4175
4176         /* And invalidate the previously valid segment by setting
4177          * its signature word (0x13) high_byte to 0b. This can be
4178          * done without an erase because flash erase sets all bits
4179          * to 1's. We can write 1's to 0's without an erase
4180          */
4181         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4182
4183         /* offset in words but we read dword*/
4184         act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
4185         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4186
4187         if (ret_val)
4188                 goto release;
4189
4190         dword &= 0x00FFFFFF;
4191         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4192
4193         if (ret_val)
4194                 goto release;
4195
4196         /* Great!  Everything worked, we can now clear the cached entries. */
4197         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4198                 dev_spec->shadow_ram[i].modified = FALSE;
4199                 dev_spec->shadow_ram[i].value = 0xFFFF;
4200         }
4201
4202 release:
4203         nvm->ops.release(hw);
4204
4205         /* Reload the EEPROM, or else modifications will not appear
4206          * until after the next adapter reset.
4207          */
4208         if (!ret_val) {
4209                 nvm->ops.reload(hw);
4210                 msec_delay(10);
4211         }
4212
4213 out:
4214         if (ret_val)
4215                 DEBUGOUT1("NVM update error: %d\n", ret_val);
4216
4217         return ret_val;
4218 }
4219
4220 /**
4221  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
4222  *  @hw: pointer to the HW structure
4223  *
4224  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
4225  *  which writes the checksum to the shadow ram.  The changes in the shadow
4226  *  ram are then committed to the EEPROM by processing each bank at a time
4227  *  checking for the modified bit and writing only the pending changes.
4228  *  After a successful commit, the shadow ram is cleared and is ready for
4229  *  future writes.
4230  **/
4231 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
4232 {
4233         struct e1000_nvm_info *nvm = &hw->nvm;
4234         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4235         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4236         s32 ret_val;
4237         u16 data = 0;
4238
4239         DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
4240
4241         ret_val = e1000_update_nvm_checksum_generic(hw);
4242         if (ret_val)
4243                 goto out;
4244
4245         if (nvm->type != e1000_nvm_flash_sw)
4246                 goto out;
4247
4248         nvm->ops.acquire(hw);
4249
4250         /* We're writing to the opposite bank so if we're on bank 1,
4251          * write to bank 0 etc.  We also need to erase the segment that
4252          * is going to be written
4253          */
4254         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4255         if (ret_val != E1000_SUCCESS) {
4256                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4257                 bank = 0;
4258         }
4259
4260         if (bank == 0) {
4261                 new_bank_offset = nvm->flash_bank_size;
4262                 old_bank_offset = 0;
4263                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4264                 if (ret_val)
4265                         goto release;
4266         } else {
4267                 old_bank_offset = nvm->flash_bank_size;
4268                 new_bank_offset = 0;
4269                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4270                 if (ret_val)
4271                         goto release;
4272         }
4273         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4274                 if (dev_spec->shadow_ram[i].modified) {
4275                         data = dev_spec->shadow_ram[i].value;
4276                 } else {
4277                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
4278                                                                 old_bank_offset,
4279                                                                 &data);
4280                         if (ret_val)
4281                                 break;
4282                 }
4283                 /* If the word is 0x13, then make sure the signature bits
4284                  * (15:14) are 11b until the commit has completed.
4285                  * This will allow us to write 10b which indicates the
4286                  * signature is valid.  We want to do this after the write
4287                  * has completed so that we don't mark the segment valid
4288                  * while the write is still in progress
4289                  */
4290                 if (i == E1000_ICH_NVM_SIG_WORD)
4291                         data |= E1000_ICH_NVM_SIG_MASK;
4292
4293                 /* Convert offset to bytes. */
4294                 act_offset = (i + new_bank_offset) << 1;
4295
4296                 usec_delay(100);
4297
4298                 /* Write the bytes to the new bank. */
4299                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4300                                                                act_offset,
4301                                                                (u8)data);
4302                 if (ret_val)
4303                         break;
4304
4305                 usec_delay(100);
4306                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4307                                                           act_offset + 1,
4308                                                           (u8)(data >> 8));
4309                 if (ret_val)
4310                         break;
4311          }
4312
4313         /* Don't bother writing the segment valid bits if sector
4314          * programming failed.
4315          */
4316         if (ret_val) {
4317                 DEBUGOUT("Flash commit failed.\n");
4318                 goto release;
4319         }
4320
4321         /* Finally validate the new segment by setting bit 15:14
4322          * to 10b in word 0x13 , this can be done without an
4323          * erase as well since these bits are 11 to start with
4324          * and we need to change bit 14 to 0b
4325          */
4326         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4327         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4328         if (ret_val)
4329                 goto release;
4330
4331         data &= 0xBFFF;
4332         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
4333                                                        (u8)(data >> 8));
4334         if (ret_val)
4335                 goto release;
4336
4337         /* And invalidate the previously valid segment by setting
4338          * its signature word (0x13) high_byte to 0b. This can be
4339          * done without an erase because flash erase sets all bits
4340          * to 1's. We can write 1's to 0's without an erase
4341          */
4342         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4343
4344         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4345
4346         if (ret_val)
4347                 goto release;
4348
4349         /* Great!  Everything worked, we can now clear the cached entries. */
4350         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4351                 dev_spec->shadow_ram[i].modified = FALSE;
4352                 dev_spec->shadow_ram[i].value = 0xFFFF;
4353         }
4354
4355 release:
4356         nvm->ops.release(hw);
4357
4358         /* Reload the EEPROM, or else modifications will not appear
4359          * until after the next adapter reset.
4360          */
4361         if (!ret_val) {
4362                 nvm->ops.reload(hw);
4363                 msec_delay(10);
4364         }
4365
4366 out:
4367         if (ret_val)
4368                 DEBUGOUT1("NVM update error: %d\n", ret_val);
4369
4370         return ret_val;
4371 }
4372
4373 /**
4374  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4375  *  @hw: pointer to the HW structure
4376  *
4377  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4378  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
4379  *  calculated, in which case we need to calculate the checksum and set bit 6.
4380  **/
4381 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4382 {
4383         s32 ret_val;
4384         u16 data;
4385         u16 word;
4386         u16 valid_csum_mask;
4387
4388         DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
4389
4390         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
4391          * the checksum needs to be fixed.  This bit is an indication that
4392          * the NVM was prepared by OEM software and did not calculate
4393          * the checksum...a likely scenario.
4394          */
4395         switch (hw->mac.type) {
4396         case e1000_pch_lpt:
4397         case e1000_pch_spt:
4398         case e1000_pch_cnp:
4399                 word = NVM_COMPAT;
4400                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4401                 break;
4402         default:
4403                 word = NVM_FUTURE_INIT_WORD1;
4404                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4405                 break;
4406         }
4407
4408         ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4409         if (ret_val)
4410                 return ret_val;
4411
4412         if (!(data & valid_csum_mask)) {
4413                 data |= valid_csum_mask;
4414                 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4415                 if (ret_val)
4416                         return ret_val;
4417                 ret_val = hw->nvm.ops.update(hw);
4418                 if (ret_val)
4419                         return ret_val;
4420         }
4421
4422         return e1000_validate_nvm_checksum_generic(hw);
4423 }
4424
4425 /**
4426  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4427  *  @hw: pointer to the HW structure
4428  *  @offset: The offset (in bytes) of the byte/word to read.
4429  *  @size: Size of data to read, 1=byte 2=word
4430  *  @data: The byte(s) to write to the NVM.
4431  *
4432  *  Writes one/two bytes to the NVM using the flash access registers.
4433  **/
4434 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4435                                           u8 size, u16 data)
4436 {
4437         union ich8_hws_flash_status hsfsts;
4438         union ich8_hws_flash_ctrl hsflctl;
4439         u32 flash_linear_addr;
4440         u32 flash_data = 0;
4441         s32 ret_val;
4442         u8 count = 0;
4443
4444         DEBUGFUNC("e1000_write_ich8_data");
4445
4446         if (hw->mac.type >= e1000_pch_spt) {
4447                 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4448                         return -E1000_ERR_NVM;
4449         } else {
4450                 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4451                         return -E1000_ERR_NVM;
4452         }
4453
4454         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4455                              hw->nvm.flash_base_addr);
4456
4457         do {
4458                 usec_delay(1);
4459                 /* Steps */
4460                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4461                 if (ret_val != E1000_SUCCESS)
4462                         break;
4463                 /* In SPT, This register is in Lan memory space, not
4464                  * flash.  Therefore, only 32 bit access is supported
4465                  */
4466                 if (hw->mac.type >= e1000_pch_spt)
4467                         hsflctl.regval =
4468                             E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
4469                 else
4470                         hsflctl.regval =
4471                             E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4472
4473                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4474                 hsflctl.hsf_ctrl.fldbcount = size - 1;
4475                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4476                 /* In SPT, This register is in Lan memory space,
4477                  * not flash.  Therefore, only 32 bit access is
4478                  * supported
4479                  */
4480                 if (hw->mac.type >= e1000_pch_spt)
4481                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4482                                               hsflctl.regval << 16);
4483                 else
4484                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4485                                                 hsflctl.regval);
4486
4487                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4488
4489                 if (size == 1)
4490                         flash_data = (u32)data & 0x00FF;
4491                 else
4492                         flash_data = (u32)data;
4493
4494                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
4495
4496                 /* check if FCERR is set to 1 , if set to 1, clear it
4497                  * and try the whole sequence a few more times else done
4498                  */
4499                 ret_val =
4500                     e1000_flash_cycle_ich8lan(hw,
4501                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4502                 if (ret_val == E1000_SUCCESS)
4503                         break;
4504
4505                 /* If we're here, then things are most likely
4506                  * completely hosed, but if the error condition
4507                  * is detected, it won't hurt to give it another
4508                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4509                  */
4510                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4511                 if (hsfsts.hsf_status.flcerr)
4512                         /* Repeat for some time before giving up. */
4513                         continue;
4514                 if (!hsfsts.hsf_status.flcdone) {
4515                         DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4516                         break;
4517                 }
4518         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4519
4520         return ret_val;
4521 }
4522
4523 /**
4524 *  e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4525 *  @hw: pointer to the HW structure
4526 *  @offset: The offset (in bytes) of the dwords to read.
4527 *  @data: The 4 bytes to write to the NVM.
4528 *
4529 *  Writes one/two/four bytes to the NVM using the flash access registers.
4530 **/
4531 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4532                                             u32 data)
4533 {
4534         union ich8_hws_flash_status hsfsts;
4535         union ich8_hws_flash_ctrl hsflctl;
4536         u32 flash_linear_addr;
4537         s32 ret_val;
4538         u8 count = 0;
4539
4540         DEBUGFUNC("e1000_write_flash_data32_ich8lan");
4541
4542         if (hw->mac.type >= e1000_pch_spt) {
4543                 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4544                         return -E1000_ERR_NVM;
4545         }
4546         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4547                              hw->nvm.flash_base_addr);
4548         do {
4549                 usec_delay(1);
4550                 /* Steps */
4551                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4552                 if (ret_val != E1000_SUCCESS)
4553                         break;
4554
4555                 /* In SPT, This register is in Lan memory space, not
4556                  * flash.  Therefore, only 32 bit access is supported
4557                  */
4558                 if (hw->mac.type >= e1000_pch_spt)
4559                         hsflctl.regval = E1000_READ_FLASH_REG(hw,
4560                                                               ICH_FLASH_HSFSTS)
4561                                          >> 16;
4562                 else
4563                         hsflctl.regval = E1000_READ_FLASH_REG16(hw,
4564                                                               ICH_FLASH_HSFCTL);
4565
4566                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4567                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4568
4569                 /* In SPT, This register is in Lan memory space,
4570                  * not flash.  Therefore, only 32 bit access is
4571                  * supported
4572                  */
4573                 if (hw->mac.type >= e1000_pch_spt)
4574                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4575                                               hsflctl.regval << 16);
4576                 else
4577                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4578                                                 hsflctl.regval);
4579
4580                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4581
4582                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);
4583
4584                 /* check if FCERR is set to 1 , if set to 1, clear it
4585                  * and try the whole sequence a few more times else done
4586                  */
4587                 ret_val = e1000_flash_cycle_ich8lan(hw,
4588                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4589
4590                 if (ret_val == E1000_SUCCESS)
4591                         break;
4592
4593                 /* If we're here, then things are most likely
4594                  * completely hosed, but if the error condition
4595                  * is detected, it won't hurt to give it another
4596                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4597                  */
4598                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4599
4600                 if (hsfsts.hsf_status.flcerr)
4601                         /* Repeat for some time before giving up. */
4602                         continue;
4603                 if (!hsfsts.hsf_status.flcdone) {
4604                         DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4605                         break;
4606                 }
4607         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4608
4609         return ret_val;
4610 }
4611
4612 /**
4613  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4614  *  @hw: pointer to the HW structure
4615  *  @offset: The index of the byte to read.
4616  *  @data: The byte to write to the NVM.
4617  *
4618  *  Writes a single byte to the NVM using the flash access registers.
4619  **/
4620 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4621                                           u8 data)
4622 {
4623         u16 word = (u16)data;
4624
4625         DEBUGFUNC("e1000_write_flash_byte_ich8lan");
4626
4627         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4628 }
4629
4630 /**
4631 *  e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4632 *  @hw: pointer to the HW structure
4633 *  @offset: The offset of the word to write.
4634 *  @dword: The dword to write to the NVM.
4635 *
4636 *  Writes a single dword to the NVM using the flash access registers.
4637 *  Goes through a retry algorithm before giving up.
4638 **/
4639 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4640                                                  u32 offset, u32 dword)
4641 {
4642         s32 ret_val;
4643         u16 program_retries;
4644
4645         DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan");
4646
4647         /* Must convert word offset into bytes. */
4648         offset <<= 1;
4649
4650         ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4651
4652         if (!ret_val)
4653                 return ret_val;
4654         for (program_retries = 0; program_retries < 100; program_retries++) {
4655                 DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset);
4656                 usec_delay(100);
4657                 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4658                 if (ret_val == E1000_SUCCESS)
4659                         break;
4660         }
4661         if (program_retries == 100)
4662                 return -E1000_ERR_NVM;
4663
4664         return E1000_SUCCESS;
4665 }
4666
4667 /**
4668  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4669  *  @hw: pointer to the HW structure
4670  *  @offset: The offset of the byte to write.
4671  *  @byte: The byte to write to the NVM.
4672  *
4673  *  Writes a single byte to the NVM using the flash access registers.
4674  *  Goes through a retry algorithm before giving up.
4675  **/
4676 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4677                                                 u32 offset, u8 byte)
4678 {
4679         s32 ret_val;
4680         u16 program_retries;
4681
4682         DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
4683
4684         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4685         if (!ret_val)
4686                 return ret_val;
4687
4688         for (program_retries = 0; program_retries < 100; program_retries++) {
4689                 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
4690                 usec_delay(100);
4691                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4692                 if (ret_val == E1000_SUCCESS)
4693                         break;
4694         }
4695         if (program_retries == 100)
4696                 return -E1000_ERR_NVM;
4697
4698         return E1000_SUCCESS;
4699 }
4700
4701 /**
4702  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4703  *  @hw: pointer to the HW structure
4704  *  @bank: 0 for first bank, 1 for second bank, etc.
4705  *
4706  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4707  *  bank N is 4096 * N + flash_reg_addr.
4708  **/
4709 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4710 {
4711         struct e1000_nvm_info *nvm = &hw->nvm;
4712         union ich8_hws_flash_status hsfsts;
4713         union ich8_hws_flash_ctrl hsflctl;
4714         u32 flash_linear_addr;
4715         /* bank size is in 16bit words - adjust to bytes */
4716         u32 flash_bank_size = nvm->flash_bank_size * 2;
4717         s32 ret_val;
4718         s32 count = 0;
4719         s32 j, iteration, sector_size;
4720
4721         DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
4722
4723         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4724
4725         /* Determine HW Sector size: Read BERASE bits of hw flash status
4726          * register
4727          * 00: The Hw sector is 256 bytes, hence we need to erase 16
4728          *     consecutive sectors.  The start index for the nth Hw sector
4729          *     can be calculated as = bank * 4096 + n * 256
4730          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4731          *     The start index for the nth Hw sector can be calculated
4732          *     as = bank * 4096
4733          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4734          *     (ich9 only, otherwise error condition)
4735          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4736          */
4737         switch (hsfsts.hsf_status.berasesz) {
4738         case 0:
4739                 /* Hw sector size 256 */
4740                 sector_size = ICH_FLASH_SEG_SIZE_256;
4741                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4742                 break;
4743         case 1:
4744                 sector_size = ICH_FLASH_SEG_SIZE_4K;
4745                 iteration = 1;
4746                 break;
4747         case 2:
4748                 sector_size = ICH_FLASH_SEG_SIZE_8K;
4749                 iteration = 1;
4750                 break;
4751         case 3:
4752                 sector_size = ICH_FLASH_SEG_SIZE_64K;
4753                 iteration = 1;
4754                 break;
4755         default:
4756                 return -E1000_ERR_NVM;
4757         }
4758
4759         /* Start with the base address, then add the sector offset. */
4760         flash_linear_addr = hw->nvm.flash_base_addr;
4761         flash_linear_addr += (bank) ? flash_bank_size : 0;
4762
4763         for (j = 0; j < iteration; j++) {
4764                 do {
4765                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4766
4767                         /* Steps */
4768                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
4769                         if (ret_val)
4770                                 return ret_val;
4771
4772                         /* Write a value 11 (block Erase) in Flash
4773                          * Cycle field in hw flash control
4774                          */
4775                         if (hw->mac.type >= e1000_pch_spt)
4776                                 hsflctl.regval =
4777                                     E1000_READ_FLASH_REG(hw,
4778                                                          ICH_FLASH_HSFSTS)>>16;
4779                         else
4780                                 hsflctl.regval =
4781                                     E1000_READ_FLASH_REG16(hw,
4782                                                            ICH_FLASH_HSFCTL);
4783
4784                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4785                         if (hw->mac.type >= e1000_pch_spt)
4786                                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4787                                                       hsflctl.regval << 16);
4788                         else
4789                                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4790                                                         hsflctl.regval);
4791
4792                         /* Write the last 24 bits of an index within the
4793                          * block into Flash Linear address field in Flash
4794                          * Address.
4795                          */
4796                         flash_linear_addr += (j * sector_size);
4797                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4798                                               flash_linear_addr);
4799
4800                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4801                         if (ret_val == E1000_SUCCESS)
4802                                 break;
4803
4804                         /* Check if FCERR is set to 1.  If 1,
4805                          * clear it and try the whole sequence
4806                          * a few more times else Done
4807                          */
4808                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4809                                                       ICH_FLASH_HSFSTS);
4810                         if (hsfsts.hsf_status.flcerr)
4811                                 /* repeat for some time before giving up */
4812                                 continue;
4813                         else if (!hsfsts.hsf_status.flcdone)
4814                                 return ret_val;
4815                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4816         }
4817
4818         return E1000_SUCCESS;
4819 }
4820
4821 /**
4822  *  e1000_valid_led_default_ich8lan - Set the default LED settings
4823  *  @hw: pointer to the HW structure
4824  *  @data: Pointer to the LED settings
4825  *
4826  *  Reads the LED default settings from the NVM to data.  If the NVM LED
4827  *  settings is all 0's or F's, set the LED default to a valid LED default
4828  *  setting.
4829  **/
4830 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4831 {
4832         s32 ret_val;
4833
4834         DEBUGFUNC("e1000_valid_led_default_ich8lan");
4835
4836         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4837         if (ret_val) {
4838                 DEBUGOUT("NVM Read Error\n");
4839                 return ret_val;
4840         }
4841
4842         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4843                 *data = ID_LED_DEFAULT_ICH8LAN;
4844
4845         return E1000_SUCCESS;
4846 }
4847
4848 /**
4849  *  e1000_id_led_init_pchlan - store LED configurations
4850  *  @hw: pointer to the HW structure
4851  *
4852  *  PCH does not control LEDs via the LEDCTL register, rather it uses
4853  *  the PHY LED configuration register.
4854  *
4855  *  PCH also does not have an "always on" or "always off" mode which
4856  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4857  *  in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4858  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4859  *  link based on logic in e1000_led_[on|off]_pchlan().
4860  **/
4861 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4862 {
4863         struct e1000_mac_info *mac = &hw->mac;
4864         s32 ret_val;
4865         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4866         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4867         u16 data, i, temp, shift;
4868
4869         DEBUGFUNC("e1000_id_led_init_pchlan");
4870
4871         /* Get default ID LED modes */
4872         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4873         if (ret_val)
4874                 return ret_val;
4875
4876         mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4877         mac->ledctl_mode1 = mac->ledctl_default;
4878         mac->ledctl_mode2 = mac->ledctl_default;
4879
4880         for (i = 0; i < 4; i++) {
4881                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4882                 shift = (i * 5);
4883                 switch (temp) {
4884                 case ID_LED_ON1_DEF2:
4885                 case ID_LED_ON1_ON2:
4886                 case ID_LED_ON1_OFF2:
4887                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4888                         mac->ledctl_mode1 |= (ledctl_on << shift);
4889                         break;
4890                 case ID_LED_OFF1_DEF2:
4891                 case ID_LED_OFF1_ON2:
4892                 case ID_LED_OFF1_OFF2:
4893                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4894                         mac->ledctl_mode1 |= (ledctl_off << shift);
4895                         break;
4896                 default:
4897                         /* Do nothing */
4898                         break;
4899                 }
4900                 switch (temp) {
4901                 case ID_LED_DEF1_ON2:
4902                 case ID_LED_ON1_ON2:
4903                 case ID_LED_OFF1_ON2:
4904                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4905                         mac->ledctl_mode2 |= (ledctl_on << shift);
4906                         break;
4907                 case ID_LED_DEF1_OFF2:
4908                 case ID_LED_ON1_OFF2:
4909                 case ID_LED_OFF1_OFF2:
4910                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4911                         mac->ledctl_mode2 |= (ledctl_off << shift);
4912                         break;
4913                 default:
4914                         /* Do nothing */
4915                         break;
4916                 }
4917         }
4918
4919         return E1000_SUCCESS;
4920 }
4921
4922 /**
4923  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4924  *  @hw: pointer to the HW structure
4925  *
4926  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4927  *  register, so the bus width is hard coded.
4928  **/
4929 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4930 {
4931         struct e1000_bus_info *bus = &hw->bus;
4932         s32 ret_val;
4933
4934         DEBUGFUNC("e1000_get_bus_info_ich8lan");
4935
4936         ret_val = e1000_get_bus_info_pcie_generic(hw);
4937
4938         /* ICH devices are "PCI Express"-ish.  They have
4939          * a configuration space, but do not contain
4940          * PCI Express Capability registers, so bus width
4941          * must be hardcoded.
4942          */
4943         if (bus->width == e1000_bus_width_unknown)
4944                 bus->width = e1000_bus_width_pcie_x1;
4945
4946         return ret_val;
4947 }
4948
4949 /**
4950  *  e1000_reset_hw_ich8lan - Reset the hardware
4951  *  @hw: pointer to the HW structure
4952  *
4953  *  Does a full reset of the hardware which includes a reset of the PHY and
4954  *  MAC.
4955  **/
4956 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4957 {
4958         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4959         u16 kum_cfg;
4960         u32 ctrl, reg;
4961         s32 ret_val;
4962
4963         DEBUGFUNC("e1000_reset_hw_ich8lan");
4964
4965         /* Prevent the PCI-E bus from sticking if there is no TLP connection
4966          * on the last TLP read/write transaction when MAC is reset.
4967          */
4968         ret_val = e1000_disable_pcie_master_generic(hw);
4969         if (ret_val)
4970                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4971
4972         DEBUGOUT("Masking off all interrupts\n");
4973         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4974
4975         /* Disable the Transmit and Receive units.  Then delay to allow
4976          * any pending transactions to complete before we hit the MAC
4977          * with the global reset.
4978          */
4979         E1000_WRITE_REG(hw, E1000_RCTL, 0);
4980         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4981         E1000_WRITE_FLUSH(hw);
4982
4983         msec_delay(10);
4984
4985         /* Workaround for ICH8 bit corruption issue in FIFO memory */
4986         if (hw->mac.type == e1000_ich8lan) {
4987                 /* Set Tx and Rx buffer allocation to 8k apiece. */
4988                 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4989                 /* Set Packet Buffer Size to 16k. */
4990                 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4991         }
4992
4993         if (hw->mac.type == e1000_pchlan) {
4994                 /* Save the NVM K1 bit setting*/
4995                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4996                 if (ret_val)
4997                         return ret_val;
4998
4999                 if (kum_cfg & E1000_NVM_K1_ENABLE)
5000                         dev_spec->nvm_k1_enabled = TRUE;
5001                 else
5002                         dev_spec->nvm_k1_enabled = FALSE;
5003         }
5004
5005         ctrl = E1000_READ_REG(hw, E1000_CTRL);
5006
5007         if (!hw->phy.ops.check_reset_block(hw)) {
5008                 /* Full-chip reset requires MAC and PHY reset at the same
5009                  * time to make sure the interface between MAC and the
5010                  * external PHY is reset.
5011                  */
5012                 ctrl |= E1000_CTRL_PHY_RST;
5013
5014                 /* Gate automatic PHY configuration by hardware on
5015                  * non-managed 82579
5016                  */
5017                 if ((hw->mac.type == e1000_pch2lan) &&
5018                     !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
5019                         e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
5020         }
5021         ret_val = e1000_acquire_swflag_ich8lan(hw);
5022         DEBUGOUT("Issuing a global reset to ich8lan\n");
5023         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
5024         /* cannot issue a flush here because it hangs the hardware */
5025         msec_delay(20);
5026
5027         /* Set Phy Config Counter to 50msec */
5028         if (hw->mac.type == e1000_pch2lan) {
5029                 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
5030                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
5031                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
5032                 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
5033         }
5034
5035         if (!ret_val)
5036                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
5037
5038         if (ctrl & E1000_CTRL_PHY_RST) {
5039                 ret_val = hw->phy.ops.get_cfg_done(hw);
5040                 if (ret_val)
5041                         return ret_val;
5042
5043                 ret_val = e1000_post_phy_reset_ich8lan(hw);
5044                 if (ret_val)
5045                         return ret_val;
5046         }
5047
5048         /* For PCH, this write will make sure that any noise
5049          * will be detected as a CRC error and be dropped rather than show up
5050          * as a bad packet to the DMA engine.
5051          */
5052         if (hw->mac.type == e1000_pchlan)
5053                 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
5054
5055         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
5056         E1000_READ_REG(hw, E1000_ICR);
5057
5058         reg = E1000_READ_REG(hw, E1000_KABGTXD);
5059         reg |= E1000_KABGTXD_BGSQLBIAS;
5060         E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
5061
5062         return E1000_SUCCESS;
5063 }
5064
5065 /**
5066  *  e1000_init_hw_ich8lan - Initialize the hardware
5067  *  @hw: pointer to the HW structure
5068  *
5069  *  Prepares the hardware for transmit and receive by doing the following:
5070  *   - initialize hardware bits
5071  *   - initialize LED identification
5072  *   - setup receive address registers
5073  *   - setup flow control
5074  *   - setup transmit descriptors
5075  *   - clear statistics
5076  **/
5077 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
5078 {
5079         struct e1000_mac_info *mac = &hw->mac;
5080         u32 ctrl_ext, txdctl, snoop;
5081         s32 ret_val;
5082         u16 i;
5083
5084         DEBUGFUNC("e1000_init_hw_ich8lan");
5085
5086         e1000_initialize_hw_bits_ich8lan(hw);
5087
5088         /* Initialize identification LED */
5089         ret_val = mac->ops.id_led_init(hw);
5090         /* An error is not fatal and we should not stop init due to this */
5091         if (ret_val)
5092                 DEBUGOUT("Error initializing identification LED\n");
5093
5094         /* Setup the receive address. */
5095         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
5096
5097         /* Zero out the Multicast HASH table */
5098         DEBUGOUT("Zeroing the MTA\n");
5099         for (i = 0; i < mac->mta_reg_count; i++)
5100                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
5101
5102         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
5103          * the ME.  Disable wakeup by clearing the host wakeup bit.
5104          * Reset the phy after disabling host wakeup to reset the Rx buffer.
5105          */
5106         if (hw->phy.type == e1000_phy_82578) {
5107                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
5108                 i &= ~BM_WUC_HOST_WU_BIT;
5109                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
5110                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
5111                 if (ret_val)
5112                         return ret_val;
5113         }
5114
5115         /* Setup link and flow control */
5116         ret_val = mac->ops.setup_link(hw);
5117
5118         /* Set the transmit descriptor write-back policy for both queues */
5119         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
5120         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5121                   E1000_TXDCTL_FULL_TX_DESC_WB);
5122         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5123                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5124         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
5125         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
5126         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5127                   E1000_TXDCTL_FULL_TX_DESC_WB);
5128         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5129                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5130         E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
5131
5132         /* ICH8 has opposite polarity of no_snoop bits.
5133          * By default, we should use snoop behavior.
5134          */
5135         if (mac->type == e1000_ich8lan)
5136                 snoop = PCIE_ICH8_SNOOP_ALL;
5137         else
5138                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
5139         e1000_set_pcie_no_snoop_generic(hw, snoop);
5140
5141         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5142         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
5143         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5144
5145         /* Clear all of the statistics registers (clear on read).  It is
5146          * important that we do this after we have tried to establish link
5147          * because the symbol error count will increment wildly if there
5148          * is no link.
5149          */
5150         e1000_clear_hw_cntrs_ich8lan(hw);
5151
5152         return ret_val;
5153 }
5154
5155 /**
5156  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
5157  *  @hw: pointer to the HW structure
5158  *
5159  *  Sets/Clears required hardware bits necessary for correctly setting up the
5160  *  hardware for transmit and receive.
5161  **/
5162 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
5163 {
5164         u32 reg;
5165
5166         DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
5167
5168         /* Extended Device Control */
5169         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
5170         reg |= (1 << 22);
5171         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
5172         if (hw->mac.type >= e1000_pchlan)
5173                 reg |= E1000_CTRL_EXT_PHYPDEN;
5174         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
5175
5176         /* Transmit Descriptor Control 0 */
5177         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
5178         reg |= (1 << 22);
5179         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
5180
5181         /* Transmit Descriptor Control 1 */
5182         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
5183         reg |= (1 << 22);
5184         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
5185
5186         /* Transmit Arbitration Control 0 */
5187         reg = E1000_READ_REG(hw, E1000_TARC(0));
5188         if (hw->mac.type == e1000_ich8lan)
5189                 reg |= (1 << 28) | (1 << 29);
5190         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
5191         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
5192
5193         /* Transmit Arbitration Control 1 */
5194         reg = E1000_READ_REG(hw, E1000_TARC(1));
5195         if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
5196                 reg &= ~(1 << 28);
5197         else
5198                 reg |= (1 << 28);
5199         reg |= (1 << 24) | (1 << 26) | (1 << 30);
5200         E1000_WRITE_REG(hw, E1000_TARC(1), reg);
5201
5202         /* Device Status */
5203         if (hw->mac.type == e1000_ich8lan) {
5204                 reg = E1000_READ_REG(hw, E1000_STATUS);
5205                 reg &= ~(1 << 31);
5206                 E1000_WRITE_REG(hw, E1000_STATUS, reg);
5207         }
5208
5209         /* work-around descriptor data corruption issue during nfs v2 udp
5210          * traffic, just disable the nfs filtering capability
5211          */
5212         reg = E1000_READ_REG(hw, E1000_RFCTL);
5213         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
5214
5215         /* Disable IPv6 extension header parsing because some malformed
5216          * IPv6 headers can hang the Rx.
5217          */
5218         if (hw->mac.type == e1000_ich8lan)
5219                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
5220         E1000_WRITE_REG(hw, E1000_RFCTL, reg);
5221
5222         /* Enable ECC on Lynxpoint */
5223         if (hw->mac.type >= e1000_pch_lpt) {
5224                 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
5225                 reg |= E1000_PBECCSTS_ECC_ENABLE;
5226                 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
5227
5228                 reg = E1000_READ_REG(hw, E1000_CTRL);
5229                 reg |= E1000_CTRL_MEHE;
5230                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
5231         }
5232
5233         return;
5234 }
5235
5236 /**
5237  *  e1000_setup_link_ich8lan - Setup flow control and link settings
5238  *  @hw: pointer to the HW structure
5239  *
5240  *  Determines which flow control settings to use, then configures flow
5241  *  control.  Calls the appropriate media-specific link configuration
5242  *  function.  Assuming the adapter has a valid link partner, a valid link
5243  *  should be established.  Assumes the hardware has previously been reset
5244  *  and the transmitter and receiver are not enabled.
5245  **/
5246 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
5247 {
5248         s32 ret_val;
5249
5250         DEBUGFUNC("e1000_setup_link_ich8lan");
5251
5252         if (hw->phy.ops.check_reset_block(hw))
5253                 return E1000_SUCCESS;
5254
5255         /* ICH parts do not have a word in the NVM to determine
5256          * the default flow control setting, so we explicitly
5257          * set it to full.
5258          */
5259         if (hw->fc.requested_mode == e1000_fc_default)
5260                 hw->fc.requested_mode = e1000_fc_full;
5261
5262         /* Save off the requested flow control mode for use later.  Depending
5263          * on the link partner's capabilities, we may or may not use this mode.
5264          */
5265         hw->fc.current_mode = hw->fc.requested_mode;
5266
5267         DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
5268                 hw->fc.current_mode);
5269
5270         /* Continue to configure the copper link. */
5271         ret_val = hw->mac.ops.setup_physical_interface(hw);
5272         if (ret_val)
5273                 return ret_val;
5274
5275         E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
5276         if ((hw->phy.type == e1000_phy_82578) ||
5277             (hw->phy.type == e1000_phy_82579) ||
5278             (hw->phy.type == e1000_phy_i217) ||
5279             (hw->phy.type == e1000_phy_82577)) {
5280                 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
5281
5282                 ret_val = hw->phy.ops.write_reg(hw,
5283                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
5284                                              hw->fc.pause_time);
5285                 if (ret_val)
5286                         return ret_val;
5287         }
5288
5289         return e1000_set_fc_watermarks_generic(hw);
5290 }
5291
5292 /**
5293  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5294  *  @hw: pointer to the HW structure
5295  *
5296  *  Configures the kumeran interface to the PHY to wait the appropriate time
5297  *  when polling the PHY, then call the generic setup_copper_link to finish
5298  *  configuring the copper link.
5299  **/
5300 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5301 {
5302         u32 ctrl;
5303         s32 ret_val;
5304         u16 reg_data;
5305
5306         DEBUGFUNC("e1000_setup_copper_link_ich8lan");
5307
5308         ctrl = E1000_READ_REG(hw, E1000_CTRL);
5309         ctrl |= E1000_CTRL_SLU;
5310         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5311         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5312
5313         /* Set the mac to wait the maximum time between each iteration
5314          * and increase the max iterations when polling the phy;
5315          * this fixes erroneous timeouts at 10Mbps.
5316          */
5317         ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
5318                                                0xFFFF);
5319         if (ret_val)
5320                 return ret_val;
5321         ret_val = e1000_read_kmrn_reg_generic(hw,
5322                                               E1000_KMRNCTRLSTA_INBAND_PARAM,
5323                                               &reg_data);
5324         if (ret_val)
5325                 return ret_val;
5326         reg_data |= 0x3F;
5327         ret_val = e1000_write_kmrn_reg_generic(hw,
5328                                                E1000_KMRNCTRLSTA_INBAND_PARAM,
5329                                                reg_data);
5330         if (ret_val)
5331                 return ret_val;
5332
5333         switch (hw->phy.type) {
5334         case e1000_phy_igp_3:
5335                 ret_val = e1000_copper_link_setup_igp(hw);
5336                 if (ret_val)
5337                         return ret_val;
5338                 break;
5339         case e1000_phy_bm:
5340         case e1000_phy_82578:
5341                 ret_val = e1000_copper_link_setup_m88(hw);
5342                 if (ret_val)
5343                         return ret_val;
5344                 break;
5345         case e1000_phy_82577:
5346         case e1000_phy_82579:
5347                 ret_val = e1000_copper_link_setup_82577(hw);
5348                 if (ret_val)
5349                         return ret_val;
5350                 break;
5351         case e1000_phy_ife:
5352                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
5353                                                &reg_data);
5354                 if (ret_val)
5355                         return ret_val;
5356
5357                 reg_data &= ~IFE_PMC_AUTO_MDIX;
5358
5359                 switch (hw->phy.mdix) {
5360                 case 1:
5361                         reg_data &= ~IFE_PMC_FORCE_MDIX;
5362                         break;
5363                 case 2:
5364                         reg_data |= IFE_PMC_FORCE_MDIX;
5365                         break;
5366                 case 0:
5367                 default:
5368                         reg_data |= IFE_PMC_AUTO_MDIX;
5369                         break;
5370                 }
5371                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
5372                                                 reg_data);
5373                 if (ret_val)
5374                         return ret_val;
5375                 break;
5376         default:
5377                 break;
5378         }
5379
5380         return e1000_setup_copper_link_generic(hw);
5381 }
5382
5383 /**
5384  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5385  *  @hw: pointer to the HW structure
5386  *
5387  *  Calls the PHY specific link setup function and then calls the
5388  *  generic setup_copper_link to finish configuring the link for
5389  *  Lynxpoint PCH devices
5390  **/
5391 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5392 {
5393         u32 ctrl;
5394         s32 ret_val;
5395
5396         DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
5397
5398         ctrl = E1000_READ_REG(hw, E1000_CTRL);
5399         ctrl |= E1000_CTRL_SLU;
5400         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5401         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5402
5403         ret_val = e1000_copper_link_setup_82577(hw);
5404         if (ret_val)
5405                 return ret_val;
5406
5407         return e1000_setup_copper_link_generic(hw);
5408 }
5409
5410 /**
5411  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5412  *  @hw: pointer to the HW structure
5413  *  @speed: pointer to store current link speed
5414  *  @duplex: pointer to store the current link duplex
5415  *
5416  *  Calls the generic get_speed_and_duplex to retrieve the current link
5417  *  information and then calls the Kumeran lock loss workaround for links at
5418  *  gigabit speeds.
5419  **/
5420 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5421                                           u16 *duplex)
5422 {
5423         s32 ret_val;
5424
5425         DEBUGFUNC("e1000_get_link_up_info_ich8lan");
5426
5427         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
5428         if (ret_val)
5429                 return ret_val;
5430
5431         if ((hw->mac.type == e1000_ich8lan) &&
5432             (hw->phy.type == e1000_phy_igp_3) &&
5433             (*speed == SPEED_1000)) {
5434                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5435         }
5436
5437         return ret_val;
5438 }
5439
5440 /**
5441  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5442  *  @hw: pointer to the HW structure
5443  *
5444  *  Work-around for 82566 Kumeran PCS lock loss:
5445  *  On link status change (i.e. PCI reset, speed change) and link is up and
5446  *  speed is gigabit-
5447  *    0) if workaround is optionally disabled do nothing
5448  *    1) wait 1ms for Kumeran link to come up
5449  *    2) check Kumeran Diagnostic register PCS lock loss bit
5450  *    3) if not set the link is locked (all is good), otherwise...
5451  *    4) reset the PHY
5452  *    5) repeat up to 10 times
5453  *  Note: this is only called for IGP3 copper when speed is 1gb.
5454  **/
5455 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5456 {
5457         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5458         u32 phy_ctrl;
5459         s32 ret_val;
5460         u16 i, data;
5461         bool link;
5462
5463         DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
5464
5465         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5466                 return E1000_SUCCESS;
5467
5468         /* Make sure link is up before proceeding.  If not just return.
5469          * Attempting this while link is negotiating fouled up link
5470          * stability
5471          */
5472         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
5473         if (!link)
5474                 return E1000_SUCCESS;
5475
5476         for (i = 0; i < 10; i++) {
5477                 /* read once to clear */
5478                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5479                 if (ret_val)
5480                         return ret_val;
5481                 /* and again to get new status */
5482                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5483                 if (ret_val)
5484                         return ret_val;
5485
5486                 /* check for PCS lock */
5487                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5488                         return E1000_SUCCESS;
5489
5490                 /* Issue PHY reset */
5491                 hw->phy.ops.reset(hw);
5492                 msec_delay_irq(5);
5493         }
5494         /* Disable GigE link negotiation */
5495         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5496         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5497                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5498         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5499
5500         /* Call gig speed drop workaround on Gig disable before accessing
5501          * any PHY registers
5502          */
5503         e1000_gig_downshift_workaround_ich8lan(hw);
5504
5505         /* unable to acquire PCS lock */
5506         return -E1000_ERR_PHY;
5507 }
5508
5509 /**
5510  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5511  *  @hw: pointer to the HW structure
5512  *  @state: boolean value used to set the current Kumeran workaround state
5513  *
5514  *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
5515  *  /disabled - FALSE).
5516  **/
5517 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5518                                                  bool state)
5519 {
5520         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5521
5522         DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
5523
5524         if (hw->mac.type != e1000_ich8lan) {
5525                 DEBUGOUT("Workaround applies to ICH8 only.\n");
5526                 return;
5527         }
5528
5529         dev_spec->kmrn_lock_loss_workaround_enabled = state;
5530
5531         return;
5532 }
5533
5534 /**
5535  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5536  *  @hw: pointer to the HW structure
5537  *
5538  *  Workaround for 82566 power-down on D3 entry:
5539  *    1) disable gigabit link
5540  *    2) write VR power-down enable
5541  *    3) read it back
5542  *  Continue if successful, else issue LCD reset and repeat
5543  **/
5544 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5545 {
5546         u32 reg;
5547         u16 data;
5548         u8  retry = 0;
5549
5550         DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
5551
5552         if (hw->phy.type != e1000_phy_igp_3)
5553                 return;
5554
5555         /* Try the workaround twice (if needed) */
5556         do {
5557                 /* Disable link */
5558                 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
5559                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5560                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5561                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
5562
5563                 /* Call gig speed drop workaround on Gig disable before
5564                  * accessing any PHY registers
5565                  */
5566                 if (hw->mac.type == e1000_ich8lan)
5567                         e1000_gig_downshift_workaround_ich8lan(hw);
5568
5569                 /* Write VR power-down enable */
5570                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5571                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5572                 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
5573                                       data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5574
5575                 /* Read it back and test */
5576                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5577                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5578                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5579                         break;
5580
5581                 /* Issue PHY reset and repeat at most one more time */
5582                 reg = E1000_READ_REG(hw, E1000_CTRL);
5583                 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
5584                 retry++;
5585         } while (retry);
5586 }
5587
5588 /**
5589  *  e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5590  *  @hw: pointer to the HW structure
5591  *
5592  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5593  *  LPLU, Gig disable, MDIC PHY reset):
5594  *    1) Set Kumeran Near-end loopback
5595  *    2) Clear Kumeran Near-end loopback
5596  *  Should only be called for ICH8[m] devices with any 1G Phy.
5597  **/
5598 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5599 {
5600         s32 ret_val;
5601         u16 reg_data;
5602
5603         DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
5604
5605         if ((hw->mac.type != e1000_ich8lan) ||
5606             (hw->phy.type == e1000_phy_ife))
5607                 return;
5608
5609         ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5610                                               &reg_data);
5611         if (ret_val)
5612                 return;
5613         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5614         ret_val = e1000_write_kmrn_reg_generic(hw,
5615                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
5616                                                reg_data);
5617         if (ret_val)
5618                 return;
5619         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5620         e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5621                                      reg_data);
5622 }
5623
5624 /**
5625  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5626  *  @hw: pointer to the HW structure
5627  *
5628  *  During S0 to Sx transition, it is possible the link remains at gig
5629  *  instead of negotiating to a lower speed.  Before going to Sx, set
5630  *  'Gig Disable' to force link speed negotiation to a lower speed based on
5631  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
5632  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5633  *  needs to be written.
5634  *  Parts that support (and are linked to a partner which support) EEE in
5635  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5636  *  than 10Mbps w/o EEE.
5637  **/
5638 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5639 {
5640         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5641         u32 phy_ctrl;
5642         s32 ret_val;
5643
5644         DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
5645
5646         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5647         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5648
5649         if (hw->phy.type == e1000_phy_i217) {
5650                 u16 phy_reg, device_id = hw->device_id;
5651
5652                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5653                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5654                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5655                     (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5656                     (hw->mac.type >= e1000_pch_spt)) {
5657                         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
5658
5659                         E1000_WRITE_REG(hw, E1000_FEXTNVM6,
5660                                         fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5661                 }
5662
5663                 ret_val = hw->phy.ops.acquire(hw);
5664                 if (ret_val)
5665                         goto out;
5666
5667                 if (!dev_spec->eee_disable) {
5668                         u16 eee_advert;
5669
5670                         ret_val =
5671                             e1000_read_emi_reg_locked(hw,
5672                                                       I217_EEE_ADVERTISEMENT,
5673                                                       &eee_advert);
5674                         if (ret_val)
5675                                 goto release;
5676
5677                         /* Disable LPLU if both link partners support 100BaseT
5678                          * EEE and 100Full is advertised on both ends of the
5679                          * link, and enable Auto Enable LPI since there will
5680                          * be no driver to enable LPI while in Sx.
5681                          */
5682                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5683                             (dev_spec->eee_lp_ability &
5684                              I82579_EEE_100_SUPPORTED) &&
5685                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5686                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5687                                               E1000_PHY_CTRL_NOND0A_LPLU);
5688
5689                                 /* Set Auto Enable LPI after link up */
5690                                 hw->phy.ops.read_reg_locked(hw,
5691                                                             I217_LPI_GPIO_CTRL,
5692                                                             &phy_reg);
5693                                 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5694                                 hw->phy.ops.write_reg_locked(hw,
5695                                                              I217_LPI_GPIO_CTRL,
5696                                                              phy_reg);
5697                         }
5698                 }
5699
5700                 /* For i217 Intel Rapid Start Technology support,
5701                  * when the system is going into Sx and no manageability engine
5702                  * is present, the driver must configure proxy to reset only on
5703                  * power good.  LPI (Low Power Idle) state must also reset only
5704                  * on power good, as well as the MTA (Multicast table array).
5705                  * The SMBus release must also be disabled on LCD reset.
5706                  */
5707                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5708                       E1000_ICH_FWSM_FW_VALID)) {
5709                         /* Enable proxy to reset only on power good. */
5710                         hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
5711                                                     &phy_reg);
5712                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5713                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
5714                                                      phy_reg);
5715
5716                         /* Set bit enable LPI (EEE) to reset only on
5717                          * power good.
5718                         */
5719                         hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
5720                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5721                         hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
5722
5723                         /* Disable the SMB release on LCD reset. */
5724                         hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
5725                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5726                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5727                 }
5728
5729                 /* Enable MTA to reset for Intel Rapid Start Technology
5730                  * Support
5731                  */
5732                 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
5733                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5734                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5735
5736 release:
5737                 hw->phy.ops.release(hw);
5738         }
5739 out:
5740         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5741
5742         if (hw->mac.type == e1000_ich8lan)
5743                 e1000_gig_downshift_workaround_ich8lan(hw);
5744
5745         if (hw->mac.type >= e1000_pchlan) {
5746                 e1000_oem_bits_config_ich8lan(hw, FALSE);
5747
5748                 /* Reset PHY to activate OEM bits on 82577/8 */
5749                 if (hw->mac.type == e1000_pchlan)
5750                         e1000_phy_hw_reset_generic(hw);
5751
5752                 ret_val = hw->phy.ops.acquire(hw);
5753                 if (ret_val)
5754                         return;
5755                 e1000_write_smbus_addr(hw);
5756                 hw->phy.ops.release(hw);
5757         }
5758
5759         return;
5760 }
5761
5762 /**
5763  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5764  *  @hw: pointer to the HW structure
5765  *
5766  *  During Sx to S0 transitions on non-managed devices or managed devices
5767  *  on which PHY resets are not blocked, if the PHY registers cannot be
5768  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
5769  *  the PHY.
5770  *  On i217, setup Intel Rapid Start Technology.
5771  **/
5772 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5773 {
5774         s32 ret_val;
5775
5776         DEBUGFUNC("e1000_resume_workarounds_pchlan");
5777         if (hw->mac.type < e1000_pch2lan)
5778                 return E1000_SUCCESS;
5779
5780         ret_val = e1000_init_phy_workarounds_pchlan(hw);
5781         if (ret_val) {
5782                 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5783                 return ret_val;
5784         }
5785
5786         /* For i217 Intel Rapid Start Technology support when the system
5787          * is transitioning from Sx and no manageability engine is present
5788          * configure SMBus to restore on reset, disable proxy, and enable
5789          * the reset on MTA (Multicast table array).
5790          */
5791         if (hw->phy.type == e1000_phy_i217) {
5792                 u16 phy_reg;
5793
5794                 ret_val = hw->phy.ops.acquire(hw);
5795                 if (ret_val) {
5796                         DEBUGOUT("Failed to setup iRST\n");
5797                         return ret_val;
5798                 }
5799
5800                 /* Clear Auto Enable LPI after link up */
5801                 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5802                 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5803                 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5804
5805                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5806                     E1000_ICH_FWSM_FW_VALID)) {
5807                         /* Restore clear on SMB if no manageability engine
5808                          * is present
5809                          */
5810                         ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5811                                                               &phy_reg);
5812                         if (ret_val)
5813                                 goto release;
5814                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5815                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5816
5817                         /* Disable Proxy */
5818                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5819                 }
5820                 /* Enable reset on MTA */
5821                 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5822                                                       &phy_reg);
5823                 if (ret_val)
5824                         goto release;
5825                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5826                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5827 release:
5828                 if (ret_val)
5829                         DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5830                 hw->phy.ops.release(hw);
5831                 return ret_val;
5832         }
5833         return E1000_SUCCESS;
5834 }
5835
5836 /**
5837  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
5838  *  @hw: pointer to the HW structure
5839  *
5840  *  Return the LED back to the default configuration.
5841  **/
5842 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5843 {
5844         DEBUGFUNC("e1000_cleanup_led_ich8lan");
5845
5846         if (hw->phy.type == e1000_phy_ife)
5847                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5848                                              0);
5849
5850         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5851         return E1000_SUCCESS;
5852 }
5853
5854 /**
5855  *  e1000_led_on_ich8lan - Turn LEDs on
5856  *  @hw: pointer to the HW structure
5857  *
5858  *  Turn on the LEDs.
5859  **/
5860 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5861 {
5862         DEBUGFUNC("e1000_led_on_ich8lan");
5863
5864         if (hw->phy.type == e1000_phy_ife)
5865                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5866                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5867
5868         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5869         return E1000_SUCCESS;
5870 }
5871
5872 /**
5873  *  e1000_led_off_ich8lan - Turn LEDs off
5874  *  @hw: pointer to the HW structure
5875  *
5876  *  Turn off the LEDs.
5877  **/
5878 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5879 {
5880         DEBUGFUNC("e1000_led_off_ich8lan");
5881
5882         if (hw->phy.type == e1000_phy_ife)
5883                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5884                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5885
5886         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5887         return E1000_SUCCESS;
5888 }
5889
5890 /**
5891  *  e1000_setup_led_pchlan - Configures SW controllable LED
5892  *  @hw: pointer to the HW structure
5893  *
5894  *  This prepares the SW controllable LED for use.
5895  **/
5896 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5897 {
5898         DEBUGFUNC("e1000_setup_led_pchlan");
5899
5900         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5901                                      (u16)hw->mac.ledctl_mode1);
5902 }
5903
5904 /**
5905  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5906  *  @hw: pointer to the HW structure
5907  *
5908  *  Return the LED back to the default configuration.
5909  **/
5910 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5911 {
5912         DEBUGFUNC("e1000_cleanup_led_pchlan");
5913
5914         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5915                                      (u16)hw->mac.ledctl_default);
5916 }
5917
5918 /**
5919  *  e1000_led_on_pchlan - Turn LEDs on
5920  *  @hw: pointer to the HW structure
5921  *
5922  *  Turn on the LEDs.
5923  **/
5924 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5925 {
5926         u16 data = (u16)hw->mac.ledctl_mode2;
5927         u32 i, led;
5928
5929         DEBUGFUNC("e1000_led_on_pchlan");
5930
5931         /* If no link, then turn LED on by setting the invert bit
5932          * for each LED that's mode is "link_up" in ledctl_mode2.
5933          */
5934         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5935                 for (i = 0; i < 3; i++) {
5936                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5937                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5938                             E1000_LEDCTL_MODE_LINK_UP)
5939                                 continue;
5940                         if (led & E1000_PHY_LED0_IVRT)
5941                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5942                         else
5943                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5944                 }
5945         }
5946
5947         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5948 }
5949
5950 /**
5951  *  e1000_led_off_pchlan - Turn LEDs off
5952  *  @hw: pointer to the HW structure
5953  *
5954  *  Turn off the LEDs.
5955  **/
5956 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5957 {
5958         u16 data = (u16)hw->mac.ledctl_mode1;
5959         u32 i, led;
5960
5961         DEBUGFUNC("e1000_led_off_pchlan");
5962
5963         /* If no link, then turn LED off by clearing the invert bit
5964          * for each LED that's mode is "link_up" in ledctl_mode1.
5965          */
5966         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5967                 for (i = 0; i < 3; i++) {
5968                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5969                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5970                             E1000_LEDCTL_MODE_LINK_UP)
5971                                 continue;
5972                         if (led & E1000_PHY_LED0_IVRT)
5973                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5974                         else
5975                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5976                 }
5977         }
5978
5979         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5980 }
5981
5982 /**
5983  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5984  *  @hw: pointer to the HW structure
5985  *
5986  *  Read appropriate register for the config done bit for completion status
5987  *  and configure the PHY through s/w for EEPROM-less parts.
5988  *
5989  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5990  *  config done bit, so only an error is logged and continues.  If we were
5991  *  to return with error, EEPROM-less silicon would not be able to be reset
5992  *  or change link.
5993  **/
5994 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5995 {
5996         s32 ret_val = E1000_SUCCESS;
5997         u32 bank = 0;
5998         u32 status;
5999
6000         DEBUGFUNC("e1000_get_cfg_done_ich8lan");
6001
6002         e1000_get_cfg_done_generic(hw);
6003
6004         /* Wait for indication from h/w that it has completed basic config */
6005         if (hw->mac.type >= e1000_ich10lan) {
6006                 e1000_lan_init_done_ich8lan(hw);
6007         } else {
6008                 ret_val = e1000_get_auto_rd_done_generic(hw);
6009                 if (ret_val) {
6010                         /* When auto config read does not complete, do not
6011                          * return with an error. This can happen in situations
6012                          * where there is no eeprom and prevents getting link.
6013                          */
6014                         DEBUGOUT("Auto Read Done did not complete\n");
6015                         ret_val = E1000_SUCCESS;
6016                 }
6017         }
6018
6019         /* Clear PHY Reset Asserted bit */
6020         status = E1000_READ_REG(hw, E1000_STATUS);
6021         if (status & E1000_STATUS_PHYRA)
6022                 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
6023         else
6024                 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
6025
6026         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
6027         if (hw->mac.type <= e1000_ich9lan) {
6028                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
6029                     (hw->phy.type == e1000_phy_igp_3)) {
6030                         e1000_phy_init_script_igp3(hw);
6031                 }
6032         } else {
6033                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
6034                         /* Maybe we should do a basic PHY config */
6035                         DEBUGOUT("EEPROM not present\n");
6036                         ret_val = -E1000_ERR_CONFIG;
6037                 }
6038         }
6039
6040         return ret_val;
6041 }
6042
6043 /**
6044  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
6045  * @hw: pointer to the HW structure
6046  *
6047  * In the case of a PHY power down to save power, or to turn off link during a
6048  * driver unload, or wake on lan is not enabled, remove the link.
6049  **/
6050 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
6051 {
6052         /* If the management interface is not enabled, then power down */
6053         if (!(hw->mac.ops.check_mng_mode(hw) ||
6054               hw->phy.ops.check_reset_block(hw)))
6055                 e1000_power_down_phy_copper(hw);
6056
6057         return;
6058 }
6059
6060 /**
6061  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
6062  *  @hw: pointer to the HW structure
6063  *
6064  *  Clears hardware counters specific to the silicon family and calls
6065  *  clear_hw_cntrs_generic to clear all general purpose counters.
6066  **/
6067 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
6068 {
6069         u16 phy_data;
6070         s32 ret_val;
6071
6072         DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
6073
6074         e1000_clear_hw_cntrs_base_generic(hw);
6075
6076         E1000_READ_REG(hw, E1000_ALGNERRC);
6077         E1000_READ_REG(hw, E1000_RXERRC);
6078         E1000_READ_REG(hw, E1000_TNCRS);
6079         E1000_READ_REG(hw, E1000_CEXTERR);
6080         E1000_READ_REG(hw, E1000_TSCTC);
6081         E1000_READ_REG(hw, E1000_TSCTFC);
6082
6083         E1000_READ_REG(hw, E1000_MGTPRC);
6084         E1000_READ_REG(hw, E1000_MGTPDC);
6085         E1000_READ_REG(hw, E1000_MGTPTC);
6086
6087         E1000_READ_REG(hw, E1000_IAC);
6088         E1000_READ_REG(hw, E1000_ICRXOC);
6089
6090         /* Clear PHY statistics registers */
6091         if ((hw->phy.type == e1000_phy_82578) ||
6092             (hw->phy.type == e1000_phy_82579) ||
6093             (hw->phy.type == e1000_phy_i217) ||
6094             (hw->phy.type == e1000_phy_82577)) {
6095                 ret_val = hw->phy.ops.acquire(hw);
6096                 if (ret_val)
6097                         return;
6098                 ret_val = hw->phy.ops.set_page(hw,
6099                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
6100                 if (ret_val)
6101                         goto release;
6102                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
6103                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
6104                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
6105                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
6106                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
6107                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
6108                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
6109                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
6110                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
6111                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
6112                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
6113                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
6114                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
6115                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
6116 release:
6117                 hw->phy.ops.release(hw);
6118         }
6119 }
6120