1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2015, Intel Corporation
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
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14 notice, this list of conditions and the following disclaimer in the
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19 this software without specific prior written permission.
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22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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33 ******************************************************************************/
36 /* 82562G 10/100 Network Connection
37 * 82562G-2 10/100 Network Connection
38 * 82562GT 10/100 Network Connection
39 * 82562GT-2 10/100 Network Connection
40 * 82562V 10/100 Network Connection
41 * 82562V-2 10/100 Network Connection
42 * 82566DC-2 Gigabit Network Connection
43 * 82566DC Gigabit Network Connection
44 * 82566DM-2 Gigabit Network Connection
45 * 82566DM Gigabit Network Connection
46 * 82566MC Gigabit Network Connection
47 * 82566MM Gigabit Network Connection
48 * 82567LM Gigabit Network Connection
49 * 82567LF Gigabit Network Connection
50 * 82567V Gigabit Network Connection
51 * 82567LM-2 Gigabit Network Connection
52 * 82567LF-2 Gigabit Network Connection
53 * 82567V-2 Gigabit Network Connection
54 * 82567LF-3 Gigabit Network Connection
55 * 82567LM-3 Gigabit Network Connection
56 * 82567LM-4 Gigabit Network Connection
57 * 82577LM Gigabit Network Connection
58 * 82577LC Gigabit Network Connection
59 * 82578DM Gigabit Network Connection
60 * 82578DC Gigabit Network Connection
61 * 82579LM Gigabit Network Connection
62 * 82579V Gigabit Network Connection
63 * Ethernet Connection I217-LM
64 * Ethernet Connection I217-V
65 * Ethernet Connection I218-V
66 * Ethernet Connection I218-LM
67 * Ethernet Connection (2) I218-LM
68 * Ethernet Connection (2) I218-V
69 * Ethernet Connection (3) I218-LM
70 * Ethernet Connection (3) I218-V
73 #include "e1000_api.h"
75 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
76 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
77 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
78 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
79 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
80 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
81 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
82 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
83 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
84 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
87 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
88 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
89 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
90 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
92 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
94 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
95 u16 words, u16 *data);
96 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
98 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
99 u16 words, u16 *data);
100 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
101 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
102 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
103 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
105 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
106 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
107 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
108 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
109 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
110 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
111 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
112 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
113 u16 *speed, u16 *duplex);
114 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
115 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
116 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
117 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
118 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
119 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
120 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
121 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
122 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
123 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
124 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
125 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
126 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
127 u32 offset, u8 *data);
128 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
130 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
132 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
133 u32 offset, u32 *data);
134 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
135 u32 offset, u32 data);
136 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
137 u32 offset, u32 dword);
138 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
139 u32 offset, u16 *data);
140 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
141 u32 offset, u8 byte);
142 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
143 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
144 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
145 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
146 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
147 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
148 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr);
150 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
151 /* Offset 04h HSFSTS */
152 union ich8_hws_flash_status {
154 u16 flcdone:1; /* bit 0 Flash Cycle Done */
155 u16 flcerr:1; /* bit 1 Flash Cycle Error */
156 u16 dael:1; /* bit 2 Direct Access error Log */
157 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
158 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
159 u16 reserved1:2; /* bit 13:6 Reserved */
160 u16 reserved2:6; /* bit 13:6 Reserved */
161 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
162 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
167 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
168 /* Offset 06h FLCTL */
169 union ich8_hws_flash_ctrl {
170 struct ich8_hsflctl {
171 u16 flcgo:1; /* 0 Flash Cycle Go */
172 u16 flcycle:2; /* 2:1 Flash Cycle */
173 u16 reserved:5; /* 7:3 Reserved */
174 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
175 u16 flockdn:6; /* 15:10 Reserved */
180 /* ICH Flash Region Access Permissions */
181 union ich8_hws_flash_regacc {
183 u32 grra:8; /* 0:7 GbE region Read Access */
184 u32 grwa:8; /* 8:15 GbE region Write Access */
185 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
186 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
192 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
193 * @hw: pointer to the HW structure
195 * Test access to the PHY registers by reading the PHY ID registers. If
196 * the PHY ID is already known (e.g. resume path) compare it with known ID,
197 * otherwise assume the read PHY ID is correct if it is valid.
199 * Assumes the sw/fw/hw semaphore is already acquired.
201 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
209 for (retry_count = 0; retry_count < 2; retry_count++) {
210 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
211 if (ret_val || (phy_reg == 0xFFFF))
213 phy_id = (u32)(phy_reg << 16);
215 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
216 if (ret_val || (phy_reg == 0xFFFF)) {
220 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
225 if (hw->phy.id == phy_id)
229 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
233 /* In case the PHY needs to be in mdio slow mode,
234 * set slow mode and try to get the PHY id again.
236 if (hw->mac.type < e1000_pch_lpt) {
237 hw->phy.ops.release(hw);
238 ret_val = e1000_set_mdio_slow_mode_hv(hw);
240 ret_val = e1000_get_phy_id(hw);
241 hw->phy.ops.acquire(hw);
247 if (hw->mac.type >= e1000_pch_lpt) {
248 /* Only unforce SMBus if ME is not active */
249 if (!(E1000_READ_REG(hw, E1000_FWSM) &
250 E1000_ICH_FWSM_FW_VALID)) {
251 /* Unforce SMBus mode in PHY */
252 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
253 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
254 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
256 /* Unforce SMBus mode in MAC */
257 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
258 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
259 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
267 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
268 * @hw: pointer to the HW structure
270 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
271 * used to reset the PHY to a quiescent state when necessary.
273 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
277 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
279 /* Set Phy Config Counter to 50msec */
280 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
281 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
282 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
283 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
285 /* Toggle LANPHYPC Value bit */
286 mac_reg = E1000_READ_REG(hw, E1000_CTRL);
287 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
288 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
289 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
290 E1000_WRITE_FLUSH(hw);
292 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
293 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
294 E1000_WRITE_FLUSH(hw);
296 if (hw->mac.type < e1000_pch_lpt) {
303 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
304 E1000_CTRL_EXT_LPCD) && count--);
311 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
312 * @hw: pointer to the HW structure
314 * Workarounds/flow necessary for PHY initialization during driver load
317 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
319 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
322 DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
324 /* Gate automatic PHY configuration by hardware on managed and
325 * non-managed 82579 and newer adapters.
327 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
329 /* It is not possible to be certain of the current state of ULP
330 * so forcibly disable it.
332 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
333 e1000_disable_ulp_lpt_lp(hw, TRUE);
335 ret_val = hw->phy.ops.acquire(hw);
337 DEBUGOUT("Failed to initialize PHY flow\n");
341 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
342 * inaccessible and resetting the PHY is not blocked, toggle the
343 * LANPHYPC Value bit to force the interconnect to PCIe mode.
345 switch (hw->mac.type) {
348 if (e1000_phy_is_accessible_pchlan(hw))
351 /* Before toggling LANPHYPC, see if PHY is accessible by
352 * forcing MAC to SMBus mode first.
354 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
355 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
356 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
358 /* Wait 50 milliseconds for MAC to finish any retries
359 * that it might be trying to perform from previous
360 * attempts to acknowledge any phy read requests.
366 if (e1000_phy_is_accessible_pchlan(hw))
371 if ((hw->mac.type == e1000_pchlan) &&
372 (fwsm & E1000_ICH_FWSM_FW_VALID))
375 if (hw->phy.ops.check_reset_block(hw)) {
376 DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
377 ret_val = -E1000_ERR_PHY;
381 /* Toggle LANPHYPC Value bit */
382 e1000_toggle_lanphypc_pch_lpt(hw);
383 if (hw->mac.type >= e1000_pch_lpt) {
384 if (e1000_phy_is_accessible_pchlan(hw))
387 /* Toggling LANPHYPC brings the PHY out of SMBus mode
388 * so ensure that the MAC is also out of SMBus mode
390 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
391 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
392 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
394 if (e1000_phy_is_accessible_pchlan(hw))
397 ret_val = -E1000_ERR_PHY;
404 hw->phy.ops.release(hw);
407 /* Check to see if able to reset PHY. Print error if not */
408 if (hw->phy.ops.check_reset_block(hw)) {
409 ERROR_REPORT("Reset blocked by ME\n");
413 /* Reset the PHY before any access to it. Doing so, ensures
414 * that the PHY is in a known good state before we read/write
415 * PHY registers. The generic reset is sufficient here,
416 * because we haven't determined the PHY type yet.
418 ret_val = e1000_phy_hw_reset_generic(hw);
422 /* On a successful reset, possibly need to wait for the PHY
423 * to quiesce to an accessible state before returning control
424 * to the calling function. If the PHY does not quiesce, then
425 * return E1000E_BLK_PHY_RESET, as this is the condition that
428 ret_val = hw->phy.ops.check_reset_block(hw);
430 ERROR_REPORT("ME blocked access to PHY after reset\n");
434 /* Ungate automatic PHY configuration on non-managed 82579 */
435 if ((hw->mac.type == e1000_pch2lan) &&
436 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
438 e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
445 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
446 * @hw: pointer to the HW structure
448 * Initialize family-specific PHY parameters and function pointers.
450 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
452 struct e1000_phy_info *phy = &hw->phy;
455 DEBUGFUNC("e1000_init_phy_params_pchlan");
458 phy->reset_delay_us = 100;
460 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
461 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
462 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
463 phy->ops.set_page = e1000_set_page_igp;
464 phy->ops.read_reg = e1000_read_phy_reg_hv;
465 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
466 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
467 phy->ops.release = e1000_release_swflag_ich8lan;
468 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
469 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
470 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
471 phy->ops.write_reg = e1000_write_phy_reg_hv;
472 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
473 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
474 phy->ops.power_up = e1000_power_up_phy_copper;
475 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
476 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
478 phy->id = e1000_phy_unknown;
480 ret_val = e1000_init_phy_workarounds_pchlan(hw);
484 if (phy->id == e1000_phy_unknown)
485 switch (hw->mac.type) {
487 ret_val = e1000_get_phy_id(hw);
490 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
496 /* In case the PHY needs to be in mdio slow mode,
497 * set slow mode and try to get the PHY id again.
499 ret_val = e1000_set_mdio_slow_mode_hv(hw);
502 ret_val = e1000_get_phy_id(hw);
507 phy->type = e1000_get_phy_type_from_id(phy->id);
510 case e1000_phy_82577:
511 case e1000_phy_82579:
513 phy->ops.check_polarity = e1000_check_polarity_82577;
514 phy->ops.force_speed_duplex =
515 e1000_phy_force_speed_duplex_82577;
516 phy->ops.get_cable_length = e1000_get_cable_length_82577;
517 phy->ops.get_info = e1000_get_phy_info_82577;
518 phy->ops.commit = e1000_phy_sw_reset_generic;
520 case e1000_phy_82578:
521 phy->ops.check_polarity = e1000_check_polarity_m88;
522 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
523 phy->ops.get_cable_length = e1000_get_cable_length_m88;
524 phy->ops.get_info = e1000_get_phy_info_m88;
527 ret_val = -E1000_ERR_PHY;
535 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
536 * @hw: pointer to the HW structure
538 * Initialize family-specific PHY parameters and function pointers.
540 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
542 struct e1000_phy_info *phy = &hw->phy;
546 DEBUGFUNC("e1000_init_phy_params_ich8lan");
549 phy->reset_delay_us = 100;
551 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
552 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
553 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
554 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
555 phy->ops.read_reg = e1000_read_phy_reg_igp;
556 phy->ops.release = e1000_release_swflag_ich8lan;
557 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
558 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
559 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
560 phy->ops.write_reg = e1000_write_phy_reg_igp;
561 phy->ops.power_up = e1000_power_up_phy_copper;
562 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
564 /* We may need to do this twice - once for IGP and if that fails,
565 * we'll set BM func pointers and try again
567 ret_val = e1000_determine_phy_address(hw);
569 phy->ops.write_reg = e1000_write_phy_reg_bm;
570 phy->ops.read_reg = e1000_read_phy_reg_bm;
571 ret_val = e1000_determine_phy_address(hw);
573 DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
579 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
582 ret_val = e1000_get_phy_id(hw);
589 case IGP03E1000_E_PHY_ID:
590 phy->type = e1000_phy_igp_3;
591 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
592 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
593 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
594 phy->ops.get_info = e1000_get_phy_info_igp;
595 phy->ops.check_polarity = e1000_check_polarity_igp;
596 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
599 case IFE_PLUS_E_PHY_ID:
601 phy->type = e1000_phy_ife;
602 phy->autoneg_mask = E1000_ALL_NOT_GIG;
603 phy->ops.get_info = e1000_get_phy_info_ife;
604 phy->ops.check_polarity = e1000_check_polarity_ife;
605 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
607 case BME1000_E_PHY_ID:
608 phy->type = e1000_phy_bm;
609 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
610 phy->ops.read_reg = e1000_read_phy_reg_bm;
611 phy->ops.write_reg = e1000_write_phy_reg_bm;
612 phy->ops.commit = e1000_phy_sw_reset_generic;
613 phy->ops.get_info = e1000_get_phy_info_m88;
614 phy->ops.check_polarity = e1000_check_polarity_m88;
615 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
618 return -E1000_ERR_PHY;
622 return E1000_SUCCESS;
626 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
627 * @hw: pointer to the HW structure
629 * Initialize family-specific NVM parameters and function
632 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
634 struct e1000_nvm_info *nvm = &hw->nvm;
635 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
636 u32 gfpreg, sector_base_addr, sector_end_addr;
640 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
642 nvm->type = e1000_nvm_flash_sw;
644 if (hw->mac.type >= e1000_pch_spt) {
645 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
646 * STRAP register. This is because in SPT the GbE Flash region
647 * is no longer accessed through the flash registers. Instead,
648 * the mechanism has changed, and the Flash region access
649 * registers are now implemented in GbE memory space.
651 nvm->flash_base_addr = 0;
653 (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
654 * NVM_SIZE_MULTIPLIER;
655 nvm->flash_bank_size = nvm_size / 2;
656 /* Adjust to word count */
657 nvm->flash_bank_size /= sizeof(u16);
658 /* Set the base address for flash register access */
659 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
661 /* Can't read flash registers if register set isn't mapped. */
662 if (!hw->flash_address) {
663 DEBUGOUT("ERROR: Flash registers not mapped\n");
664 return -E1000_ERR_CONFIG;
667 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
669 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
670 * Add 1 to sector_end_addr since this sector is included in
673 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
674 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
676 /* flash_base_addr is byte-aligned */
677 nvm->flash_base_addr = sector_base_addr
678 << FLASH_SECTOR_ADDR_SHIFT;
680 /* find total size of the NVM, then cut in half since the total
681 * size represents two separate NVM banks.
683 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
684 << FLASH_SECTOR_ADDR_SHIFT);
685 nvm->flash_bank_size /= 2;
686 /* Adjust to word count */
687 nvm->flash_bank_size /= sizeof(u16);
690 nvm->word_size = E1000_SHADOW_RAM_WORDS;
692 /* Clear shadow ram */
693 for (i = 0; i < nvm->word_size; i++) {
694 dev_spec->shadow_ram[i].modified = FALSE;
695 dev_spec->shadow_ram[i].value = 0xFFFF;
698 E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
699 E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
701 /* Function Pointers */
702 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
703 nvm->ops.release = e1000_release_nvm_ich8lan;
704 if (hw->mac.type >= e1000_pch_spt) {
705 nvm->ops.read = e1000_read_nvm_spt;
706 nvm->ops.update = e1000_update_nvm_checksum_spt;
708 nvm->ops.read = e1000_read_nvm_ich8lan;
709 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
711 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
712 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
713 nvm->ops.write = e1000_write_nvm_ich8lan;
715 return E1000_SUCCESS;
719 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
720 * @hw: pointer to the HW structure
722 * Initialize family-specific MAC parameters and function
725 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
727 struct e1000_mac_info *mac = &hw->mac;
729 DEBUGFUNC("e1000_init_mac_params_ich8lan");
731 /* Set media type function pointer */
732 hw->phy.media_type = e1000_media_type_copper;
734 /* Set mta register count */
735 mac->mta_reg_count = 32;
736 /* Set rar entry count */
737 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
738 if (mac->type == e1000_ich8lan)
739 mac->rar_entry_count--;
740 /* Set if part includes ASF firmware */
741 mac->asf_firmware_present = TRUE;
743 mac->has_fwsm = TRUE;
744 /* ARC subsystem not supported */
745 mac->arc_subsystem_valid = FALSE;
746 /* Adaptive IFS supported */
747 mac->adaptive_ifs = TRUE;
749 /* Function pointers */
751 /* bus type/speed/width */
752 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
754 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
756 mac->ops.reset_hw = e1000_reset_hw_ich8lan;
757 /* hw initialization */
758 mac->ops.init_hw = e1000_init_hw_ich8lan;
760 mac->ops.setup_link = e1000_setup_link_ich8lan;
761 /* physical interface setup */
762 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
764 mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
766 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
767 /* multicast address update */
768 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
769 /* clear hardware counters */
770 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
772 /* LED and other operations */
777 /* check management mode */
778 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
780 mac->ops.id_led_init = e1000_id_led_init_generic;
782 mac->ops.blink_led = e1000_blink_led_generic;
784 mac->ops.setup_led = e1000_setup_led_generic;
786 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
787 /* turn on/off LED */
788 mac->ops.led_on = e1000_led_on_ich8lan;
789 mac->ops.led_off = e1000_led_off_ich8lan;
792 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
793 mac->ops.rar_set = e1000_rar_set_pch2lan;
797 /* multicast address update for pch2 */
798 mac->ops.update_mc_addr_list =
799 e1000_update_mc_addr_list_pch2lan;
802 /* check management mode */
803 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
805 mac->ops.id_led_init = e1000_id_led_init_pchlan;
807 mac->ops.setup_led = e1000_setup_led_pchlan;
809 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
810 /* turn on/off LED */
811 mac->ops.led_on = e1000_led_on_pchlan;
812 mac->ops.led_off = e1000_led_off_pchlan;
818 if (mac->type >= e1000_pch_lpt) {
819 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
820 mac->ops.rar_set = e1000_rar_set_pch_lpt;
821 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
822 mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt;
825 /* Enable PCS Lock-loss workaround for ICH8 */
826 if (mac->type == e1000_ich8lan)
827 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
829 return E1000_SUCCESS;
833 * __e1000_access_emi_reg_locked - Read/write EMI register
834 * @hw: pointer to the HW structure
835 * @addr: EMI address to program
836 * @data: pointer to value to read/write from/to the EMI address
837 * @read: boolean flag to indicate read or write
839 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
841 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
842 u16 *data, bool read)
846 DEBUGFUNC("__e1000_access_emi_reg_locked");
848 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
853 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
856 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
863 * e1000_read_emi_reg_locked - Read Extended Management Interface register
864 * @hw: pointer to the HW structure
865 * @addr: EMI address to program
866 * @data: value to be read from the EMI address
868 * Assumes the SW/FW/HW Semaphore is already acquired.
870 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
872 DEBUGFUNC("e1000_read_emi_reg_locked");
874 return __e1000_access_emi_reg_locked(hw, addr, data, TRUE);
878 * e1000_write_emi_reg_locked - Write Extended Management Interface register
879 * @hw: pointer to the HW structure
880 * @addr: EMI address to program
881 * @data: value to be written to the EMI address
883 * Assumes the SW/FW/HW Semaphore is already acquired.
885 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
887 DEBUGFUNC("e1000_read_emi_reg_locked");
889 return __e1000_access_emi_reg_locked(hw, addr, &data, FALSE);
893 * e1000_set_eee_pchlan - Enable/disable EEE support
894 * @hw: pointer to the HW structure
896 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
897 * the link and the EEE capabilities of the link partner. The LPI Control
898 * register bits will remain set only if/when link is up.
900 * EEE LPI must not be asserted earlier than one second after link is up.
901 * On 82579, EEE LPI should not be enabled until such time otherwise there
902 * can be link issues with some switches. Other devices can have EEE LPI
903 * enabled immediately upon link up since they have a timer in hardware which
904 * prevents LPI from being asserted too early.
906 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
908 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
910 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
912 DEBUGFUNC("e1000_set_eee_pchlan");
914 switch (hw->phy.type) {
915 case e1000_phy_82579:
916 lpa = I82579_EEE_LP_ABILITY;
917 pcs_status = I82579_EEE_PCS_STATUS;
918 adv_addr = I82579_EEE_ADVERTISEMENT;
921 lpa = I217_EEE_LP_ABILITY;
922 pcs_status = I217_EEE_PCS_STATUS;
923 adv_addr = I217_EEE_ADVERTISEMENT;
926 return E1000_SUCCESS;
929 ret_val = hw->phy.ops.acquire(hw);
933 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
937 /* Clear bits that enable EEE in various speeds */
938 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
940 /* Enable EEE if not disabled by user */
941 if (!dev_spec->eee_disable) {
942 /* Save off link partner's EEE ability */
943 ret_val = e1000_read_emi_reg_locked(hw, lpa,
944 &dev_spec->eee_lp_ability);
948 /* Read EEE advertisement */
949 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
953 /* Enable EEE only for speeds in which the link partner is
954 * EEE capable and for which we advertise EEE.
956 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
957 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
959 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
960 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
961 if (data & NWAY_LPAR_100TX_FD_CAPS)
962 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
964 /* EEE is not supported in 100Half, so ignore
965 * partner's EEE in 100 ability if full-duplex
968 dev_spec->eee_lp_ability &=
969 ~I82579_EEE_100_SUPPORTED;
973 if (hw->phy.type == e1000_phy_82579) {
974 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
979 data &= ~I82579_LPI_100_PLL_SHUT;
980 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
984 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
985 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
989 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
991 hw->phy.ops.release(hw);
997 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
998 * @hw: pointer to the HW structure
999 * @link: link up bool flag
1001 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
1002 * preventing further DMA write requests. Workaround the issue by disabling
1003 * the de-assertion of the clock request when in 1Gpbs mode.
1004 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
1005 * speeds in order to avoid Tx hangs.
1007 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
1009 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1010 u32 status = E1000_READ_REG(hw, E1000_STATUS);
1011 s32 ret_val = E1000_SUCCESS;
1014 if (link && (status & E1000_STATUS_SPEED_1000)) {
1015 ret_val = hw->phy.ops.acquire(hw);
1020 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1026 e1000_write_kmrn_reg_locked(hw,
1027 E1000_KMRNCTRLSTA_K1_CONFIG,
1029 ~E1000_KMRNCTRLSTA_K1_ENABLE);
1035 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1036 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1039 e1000_write_kmrn_reg_locked(hw,
1040 E1000_KMRNCTRLSTA_K1_CONFIG,
1043 hw->phy.ops.release(hw);
1045 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1046 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1048 if ((hw->phy.revision > 5) || !link ||
1049 ((status & E1000_STATUS_SPEED_100) &&
1050 (status & E1000_STATUS_FD)))
1051 goto update_fextnvm6;
1053 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
1057 /* Clear link status transmit timeout */
1058 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1060 if (status & E1000_STATUS_SPEED_100) {
1061 /* Set inband Tx timeout to 5x10us for 100Half */
1062 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1064 /* Do not extend the K1 entry latency for 100Half */
1065 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1067 /* Set inband Tx timeout to 50x10us for 10Full/Half */
1069 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1071 /* Extend the K1 entry latency for 10 Mbps */
1072 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1075 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1080 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1086 static u64 e1000_ltr2ns(u16 ltr)
1090 /* Determine the latency in nsec based on the LTR value & scale */
1091 value = ltr & E1000_LTRV_VALUE_MASK;
1092 scale = (ltr & E1000_LTRV_SCALE_MASK) >> E1000_LTRV_SCALE_SHIFT;
1094 return value * (1 << (scale * E1000_LTRV_SCALE_FACTOR));
1098 * e1000_platform_pm_pch_lpt - Set platform power management values
1099 * @hw: pointer to the HW structure
1100 * @link: bool indicating link status
1102 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
1103 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
1104 * when link is up (which must not exceed the maximum latency supported
1105 * by the platform), otherwise specify there is no LTR requirement.
1106 * Unlike TRUE-PCIe devices which set the LTR maximum snoop/no-snoop
1107 * latencies in the LTR Extended Capability Structure in the PCIe Extended
1108 * Capability register set, on this device LTR is set by writing the
1109 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1110 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1111 * message to the PMC.
1113 * Use the LTR value to calculate the Optimized Buffer Flush/Fill (OBFF)
1116 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1118 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1119 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1120 u16 lat_enc = 0; /* latency encoded */
1123 DEBUGFUNC("e1000_platform_pm_pch_lpt");
1126 u16 speed, duplex, scale = 0;
1127 u16 max_snoop, max_nosnoop;
1128 u16 max_ltr_enc; /* max LTR latency encoded */
1133 if (!hw->mac.max_frame_size) {
1134 DEBUGOUT("max_frame_size not set.\n");
1135 return -E1000_ERR_CONFIG;
1138 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1140 DEBUGOUT("Speed not set.\n");
1141 return -E1000_ERR_CONFIG;
1144 /* Rx Packet Buffer Allocation size (KB) */
1145 rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK;
1147 /* Determine the maximum latency tolerated by the device.
1149 * Per the PCIe spec, the tolerated latencies are encoded as
1150 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1151 * a 10-bit value (0-1023) to provide a range from 1 ns to
1152 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
1153 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1155 lat_ns = ((s64)rxa * 1024 -
1156 (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000;
1163 while (value > E1000_LTRV_VALUE_MASK) {
1165 value = E1000_DIVIDE_ROUND_UP(value, (1 << 5));
1167 if (scale > E1000_LTRV_SCALE_MAX) {
1168 DEBUGOUT1("Invalid LTR latency scale %d\n", scale);
1169 return -E1000_ERR_CONFIG;
1171 lat_enc = (u16)((scale << E1000_LTRV_SCALE_SHIFT) | value);
1173 /* Determine the maximum latency tolerated by the platform */
1174 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop);
1175 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1176 max_ltr_enc = E1000_MAX(max_snoop, max_nosnoop);
1178 if (lat_enc > max_ltr_enc) {
1179 lat_enc = max_ltr_enc;
1180 lat_ns = e1000_ltr2ns(max_ltr_enc);
1184 lat_ns *= speed * 1000;
1186 lat_ns /= 1000000000;
1187 obff_hwm = (s32)(rxa - lat_ns);
1189 if ((obff_hwm < 0) || (obff_hwm > E1000_SVT_OFF_HWM_MASK)) {
1190 DEBUGOUT1("Invalid high water mark %d\n", obff_hwm);
1191 return -E1000_ERR_CONFIG;
1195 /* Set Snoop and No-Snoop latencies the same */
1196 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1197 E1000_WRITE_REG(hw, E1000_LTRV, reg);
1199 /* Set OBFF high water mark */
1200 reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK;
1202 E1000_WRITE_REG(hw, E1000_SVT, reg);
1205 reg = E1000_READ_REG(hw, E1000_SVCR);
1206 reg |= E1000_SVCR_OFF_EN;
1207 /* Always unblock interrupts to the CPU even when the system is
1208 * in OBFF mode. This ensures that small round-robin traffic
1209 * (like ping) does not get dropped or experience long latency.
1211 reg |= E1000_SVCR_OFF_MASKINT;
1212 E1000_WRITE_REG(hw, E1000_SVCR, reg);
1214 return E1000_SUCCESS;
1218 * e1000_set_obff_timer_pch_lpt - Update Optimized Buffer Flush/Fill timer
1219 * @hw: pointer to the HW structure
1220 * @itr: interrupt throttling rate
1222 * Configure OBFF with the updated interrupt rate.
1224 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr)
1229 DEBUGFUNC("e1000_set_obff_timer_pch_lpt");
1231 /* Convert ITR value into microseconds for OBFF timer */
1232 timer = itr & E1000_ITR_MASK;
1233 timer = (timer * E1000_ITR_MULT) / 1000;
1235 if ((timer < 0) || (timer > E1000_ITR_MASK)) {
1236 DEBUGOUT1("Invalid OBFF timer %d\n", timer);
1237 return -E1000_ERR_CONFIG;
1240 svcr = E1000_READ_REG(hw, E1000_SVCR);
1241 svcr &= ~E1000_SVCR_OFF_TIMER_MASK;
1242 svcr |= timer << E1000_SVCR_OFF_TIMER_SHIFT;
1243 E1000_WRITE_REG(hw, E1000_SVCR, svcr);
1245 return E1000_SUCCESS;
1249 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1250 * @hw: pointer to the HW structure
1251 * @to_sx: boolean indicating a system power state transition to Sx
1253 * When link is down, configure ULP mode to significantly reduce the power
1254 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1255 * ME firmware to start the ULP configuration. If not on an ME enabled
1256 * system, configure the ULP mode by software.
1258 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1261 s32 ret_val = E1000_SUCCESS;
1265 if ((hw->mac.type < e1000_pch_lpt) ||
1266 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1267 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1268 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1269 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1270 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1273 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1274 /* Request ME configure ULP mode in the PHY */
1275 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1276 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1277 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1285 /* Poll up to 5 seconds for Cable Disconnected indication */
1286 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1287 E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1288 /* Bail if link is re-acquired */
1289 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1290 return -E1000_ERR_PHY;
1297 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1298 (E1000_READ_REG(hw, E1000_FEXT) &
1299 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1303 ret_val = hw->phy.ops.acquire(hw);
1307 /* Force SMBus mode in PHY */
1308 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1311 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1312 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1314 /* Force SMBus mode in MAC */
1315 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1316 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1317 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1319 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1320 * LPLU and disable Gig speed when entering ULP
1322 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1323 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1329 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1331 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1338 /* Set Inband ULP Exit, Reset to SMBus mode and
1339 * Disable SMBus Release on PERST# in PHY
1341 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1344 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1345 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1347 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1348 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1350 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1352 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1353 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1355 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1356 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1357 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1359 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1361 /* Set Disable SMBus Release on PERST# in MAC */
1362 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1363 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1364 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1366 /* Commit ULP changes in PHY by starting auto ULP configuration */
1367 phy_reg |= I218_ULP_CONFIG1_START;
1368 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1370 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1371 to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1372 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1379 hw->phy.ops.release(hw);
1382 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1384 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1390 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1391 * @hw: pointer to the HW structure
1392 * @force: boolean indicating whether or not to force disabling ULP
1394 * Un-configure ULP mode when link is up, the system is transitioned from
1395 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1396 * system, poll for an indication from ME that ULP has been un-configured.
1397 * If not on an ME enabled system, un-configure the ULP mode by software.
1399 * During nominal operation, this function is called when link is acquired
1400 * to disable ULP mode (force=FALSE); otherwise, for example when unloading
1401 * the driver or during Sx->S0 transitions, this is called with force=TRUE
1402 * to forcibly disable ULP.
1404 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1406 s32 ret_val = E1000_SUCCESS;
1411 if ((hw->mac.type < e1000_pch_lpt) ||
1412 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1413 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1414 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1415 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1416 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1419 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1421 /* Request ME un-configure ULP mode in the PHY */
1422 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1423 mac_reg &= ~E1000_H2ME_ULP;
1424 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1425 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1428 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1429 while (E1000_READ_REG(hw, E1000_FWSM) &
1430 E1000_FWSM_ULP_CFG_DONE) {
1432 ret_val = -E1000_ERR_PHY;
1438 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1441 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1442 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1443 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1445 /* Clear H2ME.ULP after ME ULP configuration */
1446 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1447 mac_reg &= ~E1000_H2ME_ULP;
1448 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1454 ret_val = hw->phy.ops.acquire(hw);
1459 /* Toggle LANPHYPC Value bit */
1460 e1000_toggle_lanphypc_pch_lpt(hw);
1462 /* Unforce SMBus mode in PHY */
1463 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1465 /* The MAC might be in PCIe mode, so temporarily force to
1466 * SMBus mode in order to access the PHY.
1468 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1469 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1470 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1474 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1479 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1480 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1482 /* Unforce SMBus mode in MAC */
1483 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1484 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1485 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1487 /* When ULP mode was previously entered, K1 was disabled by the
1488 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1490 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1493 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1494 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1496 /* Clear ULP enabled configuration */
1497 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1500 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1501 I218_ULP_CONFIG1_STICKY_ULP |
1502 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1503 I218_ULP_CONFIG1_WOL_HOST |
1504 I218_ULP_CONFIG1_INBAND_EXIT |
1505 I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1506 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1507 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1508 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1510 /* Commit ULP changes by starting auto ULP configuration */
1511 phy_reg |= I218_ULP_CONFIG1_START;
1512 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1514 /* Clear Disable SMBus Release on PERST# in MAC */
1515 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1516 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1517 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1520 hw->phy.ops.release(hw);
1522 hw->phy.ops.reset(hw);
1527 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1529 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1535 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1536 * @hw: pointer to the HW structure
1538 * Checks to see of the link status of the hardware has changed. If a
1539 * change in link status has been detected, then we read the PHY registers
1540 * to get the current speed/duplex if link exists.
1542 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1544 struct e1000_mac_info *mac = &hw->mac;
1545 s32 ret_val, tipg_reg = 0;
1546 u16 emi_addr, emi_val = 0;
1550 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1552 /* We only want to go out to the PHY registers to see if Auto-Neg
1553 * has completed and/or if our link status has changed. The
1554 * get_link_status flag is set upon receiving a Link Status
1555 * Change or Rx Sequence Error interrupt.
1557 if (!mac->get_link_status)
1558 return E1000_SUCCESS;
1560 /* First we want to see if the MII Status Register reports
1561 * link. If so, then we want to get the current speed/duplex
1564 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1568 if (hw->mac.type == e1000_pchlan) {
1569 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1574 /* When connected at 10Mbps half-duplex, some parts are excessively
1575 * aggressive resulting in many collisions. To avoid this, increase
1576 * the IPG and reduce Rx latency in the PHY.
1578 if ((hw->mac.type >= e1000_pch2lan) && link) {
1581 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1582 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1583 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1585 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1587 /* Reduce Rx latency in analog PHY */
1589 } else if (hw->mac.type >= e1000_pch_spt &&
1590 duplex == FULL_DUPLEX && speed != SPEED_1000) {
1594 /* Roll back the default values */
1599 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1601 ret_val = hw->phy.ops.acquire(hw);
1605 if (hw->mac.type == e1000_pch2lan)
1606 emi_addr = I82579_RX_CONFIG;
1608 emi_addr = I217_RX_CONFIG;
1609 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1612 if (hw->mac.type >= e1000_pch_lpt) {
1615 hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1617 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1618 if (speed == SPEED_100 || speed == SPEED_10)
1622 hw->phy.ops.write_reg_locked(hw,
1623 I217_PLL_CLOCK_GATE_REG,
1626 if (speed == SPEED_1000) {
1627 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1630 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1632 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1636 hw->phy.ops.release(hw);
1641 if (hw->mac.type >= e1000_pch_spt) {
1645 if (speed == SPEED_1000) {
1646 ret_val = hw->phy.ops.acquire(hw);
1650 ret_val = hw->phy.ops.read_reg_locked(hw,
1654 hw->phy.ops.release(hw);
1658 ptr_gap = (data & (0x3FF << 2)) >> 2;
1659 if (ptr_gap < 0x18) {
1660 data &= ~(0x3FF << 2);
1661 data |= (0x18 << 2);
1663 hw->phy.ops.write_reg_locked(hw,
1664 PHY_REG(776, 20), data);
1666 hw->phy.ops.release(hw);
1670 ret_val = hw->phy.ops.acquire(hw);
1674 ret_val = hw->phy.ops.write_reg_locked(hw,
1677 hw->phy.ops.release(hw);
1685 /* I217 Packet Loss issue:
1686 * ensure that FEXTNVM4 Beacon Duration is set correctly
1688 * Set the Beacon Duration for I217 to 8 usec
1690 if (hw->mac.type >= e1000_pch_lpt) {
1693 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1694 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1695 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1696 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1699 /* Work-around I218 hang issue */
1700 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1701 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1702 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1703 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1704 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1708 if (hw->mac.type >= e1000_pch_lpt) {
1709 /* Set platform power management values for
1710 * Latency Tolerance Reporting (LTR)
1711 * Optimized Buffer Flush/Fill (OBFF)
1713 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1718 /* Clear link partner's EEE ability */
1719 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1721 if (hw->mac.type >= e1000_pch_lpt) {
1722 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1724 if (hw->mac.type == e1000_pch_spt) {
1725 /* FEXTNVM6 K1-off workaround - for SPT only */
1726 u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
1728 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1729 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1731 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1734 if (hw->dev_spec.ich8lan.disable_k1_off == TRUE)
1735 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1737 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1741 return E1000_SUCCESS; /* No link detected */
1743 mac->get_link_status = FALSE;
1745 switch (hw->mac.type) {
1747 ret_val = e1000_k1_workaround_lv(hw);
1752 if (hw->phy.type == e1000_phy_82578) {
1753 ret_val = e1000_link_stall_workaround_hv(hw);
1758 /* Workaround for PCHx parts in half-duplex:
1759 * Set the number of preambles removed from the packet
1760 * when it is passed from the PHY to the MAC to prevent
1761 * the MAC from misinterpreting the packet type.
1763 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1764 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1766 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1768 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1770 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1776 /* Check if there was DownShift, must be checked
1777 * immediately after link-up
1779 e1000_check_downshift_generic(hw);
1781 /* Enable/Disable EEE after link up */
1782 if (hw->phy.type > e1000_phy_82579) {
1783 ret_val = e1000_set_eee_pchlan(hw);
1788 /* If we are forcing speed/duplex, then we simply return since
1789 * we have already determined whether we have link or not.
1792 return -E1000_ERR_CONFIG;
1794 /* Auto-Neg is enabled. Auto Speed Detection takes care
1795 * of MAC speed/duplex configuration. So we only need to
1796 * configure Collision Distance in the MAC.
1798 mac->ops.config_collision_dist(hw);
1800 /* Configure Flow Control now that Auto-Neg has completed.
1801 * First, we need to restore the desired flow control
1802 * settings because we may have had to re-autoneg with a
1803 * different link partner.
1805 ret_val = e1000_config_fc_after_link_up_generic(hw);
1807 DEBUGOUT("Error configuring flow control\n");
1813 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1814 * @hw: pointer to the HW structure
1816 * Initialize family-specific function pointers for PHY, MAC, and NVM.
1818 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1820 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1822 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1823 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1824 switch (hw->mac.type) {
1827 case e1000_ich10lan:
1828 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1834 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1842 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1843 * @hw: pointer to the HW structure
1845 * Acquires the mutex for performing NVM operations.
1847 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1849 DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1851 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1853 return E1000_SUCCESS;
1857 * e1000_release_nvm_ich8lan - Release NVM mutex
1858 * @hw: pointer to the HW structure
1860 * Releases the mutex used while performing NVM operations.
1862 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1864 DEBUGFUNC("e1000_release_nvm_ich8lan");
1866 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1872 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1873 * @hw: pointer to the HW structure
1875 * Acquires the software control flag for performing PHY and select
1878 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1880 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1881 s32 ret_val = E1000_SUCCESS;
1883 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1885 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1888 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1889 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1897 DEBUGOUT("SW has already locked the resource.\n");
1898 ret_val = -E1000_ERR_CONFIG;
1902 timeout = SW_FLAG_TIMEOUT;
1904 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1905 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1908 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1909 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1917 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1918 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1919 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1920 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1921 ret_val = -E1000_ERR_CONFIG;
1927 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1933 * e1000_release_swflag_ich8lan - Release software control flag
1934 * @hw: pointer to the HW structure
1936 * Releases the software control flag for performing PHY and select
1939 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1943 DEBUGFUNC("e1000_release_swflag_ich8lan");
1945 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1947 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1948 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1949 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1951 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1954 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1960 * e1000_check_mng_mode_ich8lan - Checks management mode
1961 * @hw: pointer to the HW structure
1963 * This checks if the adapter has any manageability enabled.
1964 * This is a function pointer entry point only called by read/write
1965 * routines for the PHY and NVM parts.
1967 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1971 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1973 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1975 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1976 ((fwsm & E1000_FWSM_MODE_MASK) ==
1977 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1981 * e1000_check_mng_mode_pchlan - Checks management mode
1982 * @hw: pointer to the HW structure
1984 * This checks if the adapter has iAMT enabled.
1985 * This is a function pointer entry point only called by read/write
1986 * routines for the PHY and NVM parts.
1988 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1992 DEBUGFUNC("e1000_check_mng_mode_pchlan");
1994 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1996 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1997 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
2001 * e1000_rar_set_pch2lan - Set receive address register
2002 * @hw: pointer to the HW structure
2003 * @addr: pointer to the receive address
2004 * @index: receive address array register
2006 * Sets the receive address array register at index to the address passed
2007 * in by addr. For 82579, RAR[0] is the base address register that is to
2008 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
2009 * Use SHRA[0-3] in place of those reserved for ME.
2011 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
2013 u32 rar_low, rar_high;
2015 DEBUGFUNC("e1000_rar_set_pch2lan");
2017 /* HW expects these in little endian so we reverse the byte order
2018 * from network order (big endian) to little endian
2020 rar_low = ((u32) addr[0] |
2021 ((u32) addr[1] << 8) |
2022 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
2024 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
2026 /* If MAC address zero, no need to set the AV bit */
2027 if (rar_low || rar_high)
2028 rar_high |= E1000_RAH_AV;
2031 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2032 E1000_WRITE_FLUSH(hw);
2033 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2034 E1000_WRITE_FLUSH(hw);
2035 return E1000_SUCCESS;
2038 /* RAR[1-6] are owned by manageability. Skip those and program the
2039 * next address into the SHRA register array.
2041 if (index < (u32) (hw->mac.rar_entry_count)) {
2044 ret_val = e1000_acquire_swflag_ich8lan(hw);
2048 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
2049 E1000_WRITE_FLUSH(hw);
2050 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
2051 E1000_WRITE_FLUSH(hw);
2053 e1000_release_swflag_ich8lan(hw);
2055 /* verify the register updates */
2056 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
2057 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
2058 return E1000_SUCCESS;
2060 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
2061 (index - 1), E1000_READ_REG(hw, E1000_FWSM));
2065 DEBUGOUT1("Failed to write receive address at index %d\n", index);
2066 return -E1000_ERR_CONFIG;
2070 * e1000_rar_set_pch_lpt - Set receive address registers
2071 * @hw: pointer to the HW structure
2072 * @addr: pointer to the receive address
2073 * @index: receive address array register
2075 * Sets the receive address register array at index to the address passed
2076 * in by addr. For LPT, RAR[0] is the base address register that is to
2077 * contain the MAC address. SHRA[0-10] are the shared receive address
2078 * registers that are shared between the Host and manageability engine (ME).
2080 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
2082 u32 rar_low, rar_high;
2085 DEBUGFUNC("e1000_rar_set_pch_lpt");
2087 /* HW expects these in little endian so we reverse the byte order
2088 * from network order (big endian) to little endian
2090 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
2091 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
2093 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
2095 /* If MAC address zero, no need to set the AV bit */
2096 if (rar_low || rar_high)
2097 rar_high |= E1000_RAH_AV;
2100 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2101 E1000_WRITE_FLUSH(hw);
2102 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2103 E1000_WRITE_FLUSH(hw);
2104 return E1000_SUCCESS;
2107 /* The manageability engine (ME) can lock certain SHRAR registers that
2108 * it is using - those registers are unavailable for use.
2110 if (index < hw->mac.rar_entry_count) {
2111 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
2112 E1000_FWSM_WLOCK_MAC_MASK;
2113 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2115 /* Check if all SHRAR registers are locked */
2119 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2122 ret_val = e1000_acquire_swflag_ich8lan(hw);
2127 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
2129 E1000_WRITE_FLUSH(hw);
2130 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
2132 E1000_WRITE_FLUSH(hw);
2134 e1000_release_swflag_ich8lan(hw);
2136 /* verify the register updates */
2137 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2138 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
2139 return E1000_SUCCESS;
2144 DEBUGOUT1("Failed to write receive address at index %d\n", index);
2145 return -E1000_ERR_CONFIG;
2149 * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
2150 * @hw: pointer to the HW structure
2151 * @mc_addr_list: array of multicast addresses to program
2152 * @mc_addr_count: number of multicast addresses to program
2154 * Updates entire Multicast Table Array of the PCH2 MAC and PHY.
2155 * The caller must have a packed mc_addr_list of multicast addresses.
2157 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
2165 DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
2167 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
2169 ret_val = hw->phy.ops.acquire(hw);
2173 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2177 for (i = 0; i < hw->mac.mta_reg_count; i++) {
2178 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
2179 (u16)(hw->mac.mta_shadow[i] &
2181 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
2182 (u16)((hw->mac.mta_shadow[i] >> 16) &
2186 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2189 hw->phy.ops.release(hw);
2193 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2194 * @hw: pointer to the HW structure
2196 * Checks if firmware is blocking the reset of the PHY.
2197 * This is a function pointer entry point only called by
2200 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2203 bool blocked = FALSE;
2206 DEBUGFUNC("e1000_check_reset_block_ich8lan");
2209 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2210 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2216 } while (blocked && (i++ < 30));
2217 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2221 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2222 * @hw: pointer to the HW structure
2224 * Assumes semaphore already acquired.
2227 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2230 u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2231 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2232 E1000_STRAP_SMT_FREQ_SHIFT;
2235 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2237 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2241 phy_data &= ~HV_SMB_ADDR_MASK;
2242 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2243 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2245 if (hw->phy.type == e1000_phy_i217) {
2246 /* Restore SMBus frequency */
2248 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2249 phy_data |= (freq & (1 << 0)) <<
2250 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2251 phy_data |= (freq & (1 << 1)) <<
2252 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2254 DEBUGOUT("Unsupported SMB frequency in PHY\n");
2258 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2262 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2263 * @hw: pointer to the HW structure
2265 * SW should configure the LCD from the NVM extended configuration region
2266 * as a workaround for certain parts.
2268 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2270 struct e1000_phy_info *phy = &hw->phy;
2271 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2272 s32 ret_val = E1000_SUCCESS;
2273 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2275 DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2277 /* Initialize the PHY from the NVM on ICH platforms. This
2278 * is needed due to an issue where the NVM configuration is
2279 * not properly autoloaded after power transitions.
2280 * Therefore, after each PHY reset, we will load the
2281 * configuration data out of the NVM manually.
2283 switch (hw->mac.type) {
2285 if (phy->type != e1000_phy_igp_3)
2288 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2289 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2290 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2298 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2304 ret_val = hw->phy.ops.acquire(hw);
2308 data = E1000_READ_REG(hw, E1000_FEXTNVM);
2309 if (!(data & sw_cfg_mask))
2312 /* Make sure HW does not configure LCD from PHY
2313 * extended configuration before SW configuration
2315 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2316 if ((hw->mac.type < e1000_pch2lan) &&
2317 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2320 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2321 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2322 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2326 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2327 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2329 if (((hw->mac.type == e1000_pchlan) &&
2330 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2331 (hw->mac.type > e1000_pchlan)) {
2332 /* HW configures the SMBus address and LEDs when the
2333 * OEM and LCD Write Enable bits are set in the NVM.
2334 * When both NVM bits are cleared, SW will configure
2337 ret_val = e1000_write_smbus_addr(hw);
2341 data = E1000_READ_REG(hw, E1000_LEDCTL);
2342 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2348 /* Configure LCD from extended configuration region. */
2350 /* cnf_base_addr is in DWORD */
2351 word_addr = (u16)(cnf_base_addr << 1);
2353 for (i = 0; i < cnf_size; i++) {
2354 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2359 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2364 /* Save off the PHY page for future writes. */
2365 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2366 phy_page = reg_data;
2370 reg_addr &= PHY_REG_MASK;
2371 reg_addr |= phy_page;
2373 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2380 hw->phy.ops.release(hw);
2385 * e1000_k1_gig_workaround_hv - K1 Si workaround
2386 * @hw: pointer to the HW structure
2387 * @link: link up bool flag
2389 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2390 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2391 * If link is down, the function will restore the default K1 setting located
2394 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2396 s32 ret_val = E1000_SUCCESS;
2398 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2400 DEBUGFUNC("e1000_k1_gig_workaround_hv");
2402 if (hw->mac.type != e1000_pchlan)
2403 return E1000_SUCCESS;
2405 /* Wrap the whole flow with the sw flag */
2406 ret_val = hw->phy.ops.acquire(hw);
2410 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2412 if (hw->phy.type == e1000_phy_82578) {
2413 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2418 status_reg &= (BM_CS_STATUS_LINK_UP |
2419 BM_CS_STATUS_RESOLVED |
2420 BM_CS_STATUS_SPEED_MASK);
2422 if (status_reg == (BM_CS_STATUS_LINK_UP |
2423 BM_CS_STATUS_RESOLVED |
2424 BM_CS_STATUS_SPEED_1000))
2428 if (hw->phy.type == e1000_phy_82577) {
2429 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2434 status_reg &= (HV_M_STATUS_LINK_UP |
2435 HV_M_STATUS_AUTONEG_COMPLETE |
2436 HV_M_STATUS_SPEED_MASK);
2438 if (status_reg == (HV_M_STATUS_LINK_UP |
2439 HV_M_STATUS_AUTONEG_COMPLETE |
2440 HV_M_STATUS_SPEED_1000))
2444 /* Link stall fix for link up */
2445 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2451 /* Link stall fix for link down */
2452 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2458 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2461 hw->phy.ops.release(hw);
2467 * e1000_configure_k1_ich8lan - Configure K1 power state
2468 * @hw: pointer to the HW structure
2469 * @enable: K1 state to configure
2471 * Configure the K1 power state based on the provided parameter.
2472 * Assumes semaphore already acquired.
2474 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2476 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2484 DEBUGFUNC("e1000_configure_k1_ich8lan");
2486 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2492 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2494 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2496 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2502 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2503 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2505 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2506 reg |= E1000_CTRL_FRCSPD;
2507 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2509 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2510 E1000_WRITE_FLUSH(hw);
2512 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2513 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2514 E1000_WRITE_FLUSH(hw);
2517 return E1000_SUCCESS;
2521 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2522 * @hw: pointer to the HW structure
2523 * @d0_state: boolean if entering d0 or d3 device state
2525 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2526 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2527 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2529 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2535 DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2537 if (hw->mac.type < e1000_pchlan)
2540 ret_val = hw->phy.ops.acquire(hw);
2544 if (hw->mac.type == e1000_pchlan) {
2545 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2546 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2550 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2551 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2554 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2556 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2560 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2563 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2564 oem_reg |= HV_OEM_BITS_GBE_DIS;
2566 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2567 oem_reg |= HV_OEM_BITS_LPLU;
2569 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2570 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2571 oem_reg |= HV_OEM_BITS_GBE_DIS;
2573 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2574 E1000_PHY_CTRL_NOND0A_LPLU))
2575 oem_reg |= HV_OEM_BITS_LPLU;
2578 /* Set Restart auto-neg to activate the bits */
2579 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2580 !hw->phy.ops.check_reset_block(hw))
2581 oem_reg |= HV_OEM_BITS_RESTART_AN;
2583 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2586 hw->phy.ops.release(hw);
2593 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2594 * @hw: pointer to the HW structure
2596 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2601 DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2603 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2607 data |= HV_KMRN_MDIO_SLOW;
2609 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2615 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2616 * done after every PHY reset.
2618 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2620 s32 ret_val = E1000_SUCCESS;
2623 DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2625 if (hw->mac.type != e1000_pchlan)
2626 return E1000_SUCCESS;
2628 /* Set MDIO slow mode before any other MDIO access */
2629 if (hw->phy.type == e1000_phy_82577) {
2630 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2635 if (((hw->phy.type == e1000_phy_82577) &&
2636 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2637 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2638 /* Disable generation of early preamble */
2639 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2643 /* Preamble tuning for SSC */
2644 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2650 if (hw->phy.type == e1000_phy_82578) {
2651 /* Return registers to default by doing a soft reset then
2652 * writing 0x3140 to the control register.
2654 if (hw->phy.revision < 2) {
2655 e1000_phy_sw_reset_generic(hw);
2656 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2662 ret_val = hw->phy.ops.acquire(hw);
2667 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2668 hw->phy.ops.release(hw);
2672 /* Configure the K1 Si workaround during phy reset assuming there is
2673 * link so that it disables K1 if link is in 1Gbps.
2675 ret_val = e1000_k1_gig_workaround_hv(hw, TRUE);
2679 /* Workaround for link disconnects on a busy hub in half duplex */
2680 ret_val = hw->phy.ops.acquire(hw);
2683 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2686 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2691 /* set MSE higher to enable link to stay up when noise is high */
2692 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2694 hw->phy.ops.release(hw);
2700 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2701 * @hw: pointer to the HW structure
2703 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2709 DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2711 ret_val = hw->phy.ops.acquire(hw);
2714 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2718 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2719 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2720 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2721 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2722 (u16)(mac_reg & 0xFFFF));
2723 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2724 (u16)((mac_reg >> 16) & 0xFFFF));
2726 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2727 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2728 (u16)(mac_reg & 0xFFFF));
2729 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2730 (u16)((mac_reg & E1000_RAH_AV)
2734 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2737 hw->phy.ops.release(hw);
2740 static u32 e1000_calc_rx_da_crc(u8 mac[])
2742 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
2743 u32 i, j, mask, crc;
2745 DEBUGFUNC("e1000_calc_rx_da_crc");
2748 for (i = 0; i < 6; i++) {
2750 for (j = 8; j > 0; j--) {
2751 mask = (crc & 1) * (-1);
2752 crc = (crc >> 1) ^ (poly & mask);
2759 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2761 * @hw: pointer to the HW structure
2762 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2764 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2766 s32 ret_val = E1000_SUCCESS;
2771 DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2773 if (hw->mac.type < e1000_pch2lan)
2774 return E1000_SUCCESS;
2776 /* disable Rx path while enabling/disabling workaround */
2777 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2778 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2779 phy_reg | (1 << 14));
2784 /* Write Rx addresses (rar_entry_count for RAL/H, and
2785 * SHRAL/H) and initial CRC values to the MAC
2787 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2788 u8 mac_addr[ETH_ADDR_LEN] = {0};
2789 u32 addr_high, addr_low;
2791 addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2792 if (!(addr_high & E1000_RAH_AV))
2794 addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2795 mac_addr[0] = (addr_low & 0xFF);
2796 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2797 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2798 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2799 mac_addr[4] = (addr_high & 0xFF);
2800 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2802 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2803 e1000_calc_rx_da_crc(mac_addr));
2806 /* Write Rx addresses to the PHY */
2807 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2809 /* Enable jumbo frame workaround in the MAC */
2810 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2811 mac_reg &= ~(1 << 14);
2812 mac_reg |= (7 << 15);
2813 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2815 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2816 mac_reg |= E1000_RCTL_SECRC;
2817 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2819 ret_val = e1000_read_kmrn_reg_generic(hw,
2820 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2824 ret_val = e1000_write_kmrn_reg_generic(hw,
2825 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2829 ret_val = e1000_read_kmrn_reg_generic(hw,
2830 E1000_KMRNCTRLSTA_HD_CTRL,
2834 data &= ~(0xF << 8);
2836 ret_val = e1000_write_kmrn_reg_generic(hw,
2837 E1000_KMRNCTRLSTA_HD_CTRL,
2842 /* Enable jumbo frame workaround in the PHY */
2843 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2844 data &= ~(0x7F << 5);
2845 data |= (0x37 << 5);
2846 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2849 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2851 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2854 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2855 data &= ~(0x3FF << 2);
2856 data |= (E1000_TX_PTR_GAP << 2);
2857 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2860 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2863 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2864 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2869 /* Write MAC register values back to h/w defaults */
2870 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2871 mac_reg &= ~(0xF << 14);
2872 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2874 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2875 mac_reg &= ~E1000_RCTL_SECRC;
2876 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2878 ret_val = e1000_read_kmrn_reg_generic(hw,
2879 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2883 ret_val = e1000_write_kmrn_reg_generic(hw,
2884 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2888 ret_val = e1000_read_kmrn_reg_generic(hw,
2889 E1000_KMRNCTRLSTA_HD_CTRL,
2893 data &= ~(0xF << 8);
2895 ret_val = e1000_write_kmrn_reg_generic(hw,
2896 E1000_KMRNCTRLSTA_HD_CTRL,
2901 /* Write PHY register values back to h/w defaults */
2902 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2903 data &= ~(0x7F << 5);
2904 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2907 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2909 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2912 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2913 data &= ~(0x3FF << 2);
2915 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2918 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2921 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2922 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2928 /* re-enable Rx path after enabling/disabling workaround */
2929 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2934 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2935 * done after every PHY reset.
2937 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2939 s32 ret_val = E1000_SUCCESS;
2941 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2943 if (hw->mac.type != e1000_pch2lan)
2944 return E1000_SUCCESS;
2946 /* Set MDIO slow mode before any other MDIO access */
2947 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2951 ret_val = hw->phy.ops.acquire(hw);
2954 /* set MSE higher to enable link to stay up when noise is high */
2955 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2958 /* drop link after 5 times MSE threshold was reached */
2959 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2961 hw->phy.ops.release(hw);
2967 * e1000_k1_gig_workaround_lv - K1 Si workaround
2968 * @hw: pointer to the HW structure
2970 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2971 * Disable K1 for 1000 and 100 speeds
2973 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2975 s32 ret_val = E1000_SUCCESS;
2978 DEBUGFUNC("e1000_k1_workaround_lv");
2980 if (hw->mac.type != e1000_pch2lan)
2981 return E1000_SUCCESS;
2983 /* Set K1 beacon duration based on 10Mbs speed */
2984 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2988 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2989 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2991 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2994 /* LV 1G/100 Packet drop issue wa */
2995 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2999 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
3000 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
3006 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
3007 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
3008 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
3009 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
3017 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
3018 * @hw: pointer to the HW structure
3019 * @gate: boolean set to TRUE to gate, FALSE to ungate
3021 * Gate/ungate the automatic PHY configuration via hardware; perform
3022 * the configuration via software instead.
3024 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
3028 DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
3030 if (hw->mac.type < e1000_pch2lan)
3033 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
3036 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
3038 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
3040 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
3044 * e1000_lan_init_done_ich8lan - Check for PHY config completion
3045 * @hw: pointer to the HW structure
3047 * Check the appropriate indication the MAC has finished configuring the
3048 * PHY after a software reset.
3050 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
3052 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
3054 DEBUGFUNC("e1000_lan_init_done_ich8lan");
3056 /* Wait for basic configuration completes before proceeding */
3058 data = E1000_READ_REG(hw, E1000_STATUS);
3059 data &= E1000_STATUS_LAN_INIT_DONE;
3061 } while ((!data) && --loop);
3063 /* If basic configuration is incomplete before the above loop
3064 * count reaches 0, loading the configuration from NVM will
3065 * leave the PHY in a bad state possibly resulting in no link.
3068 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
3070 /* Clear the Init Done bit for the next init event */
3071 data = E1000_READ_REG(hw, E1000_STATUS);
3072 data &= ~E1000_STATUS_LAN_INIT_DONE;
3073 E1000_WRITE_REG(hw, E1000_STATUS, data);
3077 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
3078 * @hw: pointer to the HW structure
3080 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
3082 s32 ret_val = E1000_SUCCESS;
3085 DEBUGFUNC("e1000_post_phy_reset_ich8lan");
3087 if (hw->phy.ops.check_reset_block(hw))
3088 return E1000_SUCCESS;
3090 /* Allow time for h/w to get to quiescent state after reset */
3093 /* Perform any necessary post-reset workarounds */
3094 switch (hw->mac.type) {
3096 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
3101 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
3109 /* Clear the host wakeup bit after lcd reset */
3110 if (hw->mac.type >= e1000_pchlan) {
3111 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®);
3112 reg &= ~BM_WUC_HOST_WU_BIT;
3113 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
3116 /* Configure the LCD with the extended configuration region in NVM */
3117 ret_val = e1000_sw_lcd_config_ich8lan(hw);
3121 /* Configure the LCD with the OEM bits in NVM */
3122 ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE);
3124 if (hw->mac.type == e1000_pch2lan) {
3125 /* Ungate automatic PHY configuration on non-managed 82579 */
3126 if (!(E1000_READ_REG(hw, E1000_FWSM) &
3127 E1000_ICH_FWSM_FW_VALID)) {
3129 e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
3132 /* Set EEE LPI Update Timer to 200usec */
3133 ret_val = hw->phy.ops.acquire(hw);
3136 ret_val = e1000_write_emi_reg_locked(hw,
3137 I82579_LPI_UPDATE_TIMER,
3139 hw->phy.ops.release(hw);
3146 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
3147 * @hw: pointer to the HW structure
3150 * This is a function pointer entry point called by drivers
3151 * or other shared routines.
3153 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
3155 s32 ret_val = E1000_SUCCESS;
3157 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
3159 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
3160 if ((hw->mac.type == e1000_pch2lan) &&
3161 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3162 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
3164 ret_val = e1000_phy_hw_reset_generic(hw);
3168 return e1000_post_phy_reset_ich8lan(hw);
3172 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
3173 * @hw: pointer to the HW structure
3174 * @active: TRUE to enable LPLU, FALSE to disable
3176 * Sets the LPLU state according to the active flag. For PCH, if OEM write
3177 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
3178 * the phy speed. This function will manually set the LPLU bit and restart
3179 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
3180 * since it configures the same bit.
3182 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
3187 DEBUGFUNC("e1000_set_lplu_state_pchlan");
3188 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3193 oem_reg |= HV_OEM_BITS_LPLU;
3195 oem_reg &= ~HV_OEM_BITS_LPLU;
3197 if (!hw->phy.ops.check_reset_block(hw))
3198 oem_reg |= HV_OEM_BITS_RESTART_AN;
3200 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3204 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3205 * @hw: pointer to the HW structure
3206 * @active: TRUE to enable LPLU, FALSE to disable
3208 * Sets the LPLU D0 state according to the active flag. When
3209 * activating LPLU this function also disables smart speed
3210 * and vice versa. LPLU will not be activated unless the
3211 * device autonegotiation advertisement meets standards of
3212 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3213 * This is a function pointer entry point only called by
3214 * PHY setup routines.
3216 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3218 struct e1000_phy_info *phy = &hw->phy;
3220 s32 ret_val = E1000_SUCCESS;
3223 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3225 if (phy->type == e1000_phy_ife)
3226 return E1000_SUCCESS;
3228 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3231 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3232 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3234 if (phy->type != e1000_phy_igp_3)
3235 return E1000_SUCCESS;
3237 /* Call gig speed drop workaround on LPLU before accessing
3240 if (hw->mac.type == e1000_ich8lan)
3241 e1000_gig_downshift_workaround_ich8lan(hw);
3243 /* When LPLU is enabled, we should disable SmartSpeed */
3244 ret_val = phy->ops.read_reg(hw,
3245 IGP01E1000_PHY_PORT_CONFIG,
3249 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3250 ret_val = phy->ops.write_reg(hw,
3251 IGP01E1000_PHY_PORT_CONFIG,
3256 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3257 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3259 if (phy->type != e1000_phy_igp_3)
3260 return E1000_SUCCESS;
3262 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3263 * during Dx states where the power conservation is most
3264 * important. During driver activity we should enable
3265 * SmartSpeed, so performance is maintained.
3267 if (phy->smart_speed == e1000_smart_speed_on) {
3268 ret_val = phy->ops.read_reg(hw,
3269 IGP01E1000_PHY_PORT_CONFIG,
3274 data |= IGP01E1000_PSCFR_SMART_SPEED;
3275 ret_val = phy->ops.write_reg(hw,
3276 IGP01E1000_PHY_PORT_CONFIG,
3280 } else if (phy->smart_speed == e1000_smart_speed_off) {
3281 ret_val = phy->ops.read_reg(hw,
3282 IGP01E1000_PHY_PORT_CONFIG,
3287 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3288 ret_val = phy->ops.write_reg(hw,
3289 IGP01E1000_PHY_PORT_CONFIG,
3296 return E1000_SUCCESS;
3300 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3301 * @hw: pointer to the HW structure
3302 * @active: TRUE to enable LPLU, FALSE to disable
3304 * Sets the LPLU D3 state according to the active flag. When
3305 * activating LPLU this function also disables smart speed
3306 * and vice versa. LPLU will not be activated unless the
3307 * device autonegotiation advertisement meets standards of
3308 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3309 * This is a function pointer entry point only called by
3310 * PHY setup routines.
3312 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3314 struct e1000_phy_info *phy = &hw->phy;
3316 s32 ret_val = E1000_SUCCESS;
3319 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3321 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3324 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3325 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3327 if (phy->type != e1000_phy_igp_3)
3328 return E1000_SUCCESS;
3330 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3331 * during Dx states where the power conservation is most
3332 * important. During driver activity we should enable
3333 * SmartSpeed, so performance is maintained.
3335 if (phy->smart_speed == e1000_smart_speed_on) {
3336 ret_val = phy->ops.read_reg(hw,
3337 IGP01E1000_PHY_PORT_CONFIG,
3342 data |= IGP01E1000_PSCFR_SMART_SPEED;
3343 ret_val = phy->ops.write_reg(hw,
3344 IGP01E1000_PHY_PORT_CONFIG,
3348 } else if (phy->smart_speed == e1000_smart_speed_off) {
3349 ret_val = phy->ops.read_reg(hw,
3350 IGP01E1000_PHY_PORT_CONFIG,
3355 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3356 ret_val = phy->ops.write_reg(hw,
3357 IGP01E1000_PHY_PORT_CONFIG,
3362 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3363 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3364 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3365 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3366 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3368 if (phy->type != e1000_phy_igp_3)
3369 return E1000_SUCCESS;
3371 /* Call gig speed drop workaround on LPLU before accessing
3374 if (hw->mac.type == e1000_ich8lan)
3375 e1000_gig_downshift_workaround_ich8lan(hw);
3377 /* When LPLU is enabled, we should disable SmartSpeed */
3378 ret_val = phy->ops.read_reg(hw,
3379 IGP01E1000_PHY_PORT_CONFIG,
3384 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3385 ret_val = phy->ops.write_reg(hw,
3386 IGP01E1000_PHY_PORT_CONFIG,
3394 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3395 * @hw: pointer to the HW structure
3396 * @bank: pointer to the variable that returns the active bank
3398 * Reads signature byte from the NVM using the flash access registers.
3399 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3401 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3404 struct e1000_nvm_info *nvm = &hw->nvm;
3405 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3406 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3411 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3413 switch (hw->mac.type) {
3415 bank1_offset = nvm->flash_bank_size;
3416 act_offset = E1000_ICH_NVM_SIG_WORD;
3418 /* set bank to 0 in case flash read fails */
3422 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3426 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3427 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3428 E1000_ICH_NVM_SIG_VALUE) {
3430 return E1000_SUCCESS;
3434 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3439 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3440 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3441 E1000_ICH_NVM_SIG_VALUE) {
3443 return E1000_SUCCESS;
3446 DEBUGOUT("ERROR: No valid NVM bank present\n");
3447 return -E1000_ERR_NVM;
3450 eecd = E1000_READ_REG(hw, E1000_EECD);
3451 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3452 E1000_EECD_SEC1VAL_VALID_MASK) {
3453 if (eecd & E1000_EECD_SEC1VAL)
3458 return E1000_SUCCESS;
3460 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3463 /* set bank to 0 in case flash read fails */
3467 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3471 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3472 E1000_ICH_NVM_SIG_VALUE) {
3474 return E1000_SUCCESS;
3478 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3483 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3484 E1000_ICH_NVM_SIG_VALUE) {
3486 return E1000_SUCCESS;
3489 DEBUGOUT("ERROR: No valid NVM bank present\n");
3490 return -E1000_ERR_NVM;
3495 * e1000_read_nvm_spt - NVM access for SPT
3496 * @hw: pointer to the HW structure
3497 * @offset: The offset (in bytes) of the word(s) to read.
3498 * @words: Size of data to read in words.
3499 * @data: pointer to the word(s) to read at offset.
3501 * Reads a word(s) from the NVM
3503 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3506 struct e1000_nvm_info *nvm = &hw->nvm;
3507 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3509 s32 ret_val = E1000_SUCCESS;
3515 DEBUGFUNC("e1000_read_nvm_spt");
3517 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3519 DEBUGOUT("nvm parameter(s) out of bounds\n");
3520 ret_val = -E1000_ERR_NVM;
3524 nvm->ops.acquire(hw);
3526 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3527 if (ret_val != E1000_SUCCESS) {
3528 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3532 act_offset = (bank) ? nvm->flash_bank_size : 0;
3533 act_offset += offset;
3535 ret_val = E1000_SUCCESS;
3537 for (i = 0; i < words; i += 2) {
3538 if (words - i == 1) {
3539 if (dev_spec->shadow_ram[offset+i].modified) {
3540 data[i] = dev_spec->shadow_ram[offset+i].value;
3542 offset_to_read = act_offset + i -
3543 ((act_offset + i) % 2);
3545 e1000_read_flash_dword_ich8lan(hw,
3550 if ((act_offset + i) % 2 == 0)
3551 data[i] = (u16)(dword & 0xFFFF);
3553 data[i] = (u16)((dword >> 16) & 0xFFFF);
3556 offset_to_read = act_offset + i;
3557 if (!(dev_spec->shadow_ram[offset+i].modified) ||
3558 !(dev_spec->shadow_ram[offset+i+1].modified)) {
3560 e1000_read_flash_dword_ich8lan(hw,
3566 if (dev_spec->shadow_ram[offset+i].modified)
3567 data[i] = dev_spec->shadow_ram[offset+i].value;
3569 data[i] = (u16) (dword & 0xFFFF);
3570 if (dev_spec->shadow_ram[offset+i].modified)
3572 dev_spec->shadow_ram[offset+i+1].value;
3574 data[i+1] = (u16) (dword >> 16 & 0xFFFF);
3578 nvm->ops.release(hw);
3582 DEBUGOUT1("NVM read error: %d\n", ret_val);
3588 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3589 * @hw: pointer to the HW structure
3590 * @offset: The offset (in bytes) of the word(s) to read.
3591 * @words: Size of data to read in words
3592 * @data: Pointer to the word(s) to read at offset.
3594 * Reads a word(s) from the NVM using the flash access registers.
3596 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3599 struct e1000_nvm_info *nvm = &hw->nvm;
3600 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3602 s32 ret_val = E1000_SUCCESS;
3606 DEBUGFUNC("e1000_read_nvm_ich8lan");
3608 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3610 DEBUGOUT("nvm parameter(s) out of bounds\n");
3611 ret_val = -E1000_ERR_NVM;
3615 nvm->ops.acquire(hw);
3617 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3618 if (ret_val != E1000_SUCCESS) {
3619 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3623 act_offset = (bank) ? nvm->flash_bank_size : 0;
3624 act_offset += offset;
3626 ret_val = E1000_SUCCESS;
3627 for (i = 0; i < words; i++) {
3628 if (dev_spec->shadow_ram[offset+i].modified) {
3629 data[i] = dev_spec->shadow_ram[offset+i].value;
3631 ret_val = e1000_read_flash_word_ich8lan(hw,
3640 nvm->ops.release(hw);
3644 DEBUGOUT1("NVM read error: %d\n", ret_val);
3650 * e1000_flash_cycle_init_ich8lan - Initialize flash
3651 * @hw: pointer to the HW structure
3653 * This function does initial flash setup so that a new read/write/erase cycle
3656 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3658 union ich8_hws_flash_status hsfsts;
3659 s32 ret_val = -E1000_ERR_NVM;
3661 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3663 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3665 /* Check if the flash descriptor is valid */
3666 if (!hsfsts.hsf_status.fldesvalid) {
3667 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
3668 return -E1000_ERR_NVM;
3671 /* Clear FCERR and DAEL in hw status by writing 1 */
3672 hsfsts.hsf_status.flcerr = 1;
3673 hsfsts.hsf_status.dael = 1;
3674 if (hw->mac.type >= e1000_pch_spt)
3675 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3676 hsfsts.regval & 0xFFFF);
3678 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3680 /* Either we should have a hardware SPI cycle in progress
3681 * bit to check against, in order to start a new cycle or
3682 * FDONE bit should be changed in the hardware so that it
3683 * is 1 after hardware reset, which can then be used as an
3684 * indication whether a cycle is in progress or has been
3688 if (!hsfsts.hsf_status.flcinprog) {
3689 /* There is no cycle running at present,
3690 * so we can start a cycle.
3691 * Begin by setting Flash Cycle Done.
3693 hsfsts.hsf_status.flcdone = 1;
3694 if (hw->mac.type >= e1000_pch_spt)
3695 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3696 hsfsts.regval & 0xFFFF);
3698 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3700 ret_val = E1000_SUCCESS;
3704 /* Otherwise poll for sometime so the current
3705 * cycle has a chance to end before giving up.
3707 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3708 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3710 if (!hsfsts.hsf_status.flcinprog) {
3711 ret_val = E1000_SUCCESS;
3716 if (ret_val == E1000_SUCCESS) {
3717 /* Successful in waiting for previous cycle to timeout,
3718 * now set the Flash Cycle Done.
3720 hsfsts.hsf_status.flcdone = 1;
3721 if (hw->mac.type >= e1000_pch_spt)
3722 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3723 hsfsts.regval & 0xFFFF);
3725 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3728 DEBUGOUT("Flash controller busy, cannot get access\n");
3736 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3737 * @hw: pointer to the HW structure
3738 * @timeout: maximum time to wait for completion
3740 * This function starts a flash cycle and waits for its completion.
3742 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3744 union ich8_hws_flash_ctrl hsflctl;
3745 union ich8_hws_flash_status hsfsts;
3748 DEBUGFUNC("e1000_flash_cycle_ich8lan");
3750 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3751 if (hw->mac.type >= e1000_pch_spt)
3752 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3754 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3755 hsflctl.hsf_ctrl.flcgo = 1;
3757 if (hw->mac.type >= e1000_pch_spt)
3758 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3759 hsflctl.regval << 16);
3761 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3763 /* wait till FDONE bit is set to 1 */
3765 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3766 if (hsfsts.hsf_status.flcdone)
3769 } while (i++ < timeout);
3771 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3772 return E1000_SUCCESS;
3774 return -E1000_ERR_NVM;
3778 * e1000_read_flash_dword_ich8lan - Read dword from flash
3779 * @hw: pointer to the HW structure
3780 * @offset: offset to data location
3781 * @data: pointer to the location for storing the data
3783 * Reads the flash dword at offset into data. Offset is converted
3784 * to bytes before read.
3786 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3789 DEBUGFUNC("e1000_read_flash_dword_ich8lan");
3792 return -E1000_ERR_NVM;
3794 /* Must convert word offset into bytes. */
3797 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3801 * e1000_read_flash_word_ich8lan - Read word from flash
3802 * @hw: pointer to the HW structure
3803 * @offset: offset to data location
3804 * @data: pointer to the location for storing the data
3806 * Reads the flash word at offset into data. Offset is converted
3807 * to bytes before read.
3809 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3812 DEBUGFUNC("e1000_read_flash_word_ich8lan");
3815 return -E1000_ERR_NVM;
3817 /* Must convert offset into bytes. */
3820 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3824 * e1000_read_flash_byte_ich8lan - Read byte from flash
3825 * @hw: pointer to the HW structure
3826 * @offset: The offset of the byte to read.
3827 * @data: Pointer to a byte to store the value read.
3829 * Reads a single byte from the NVM using the flash access registers.
3831 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3837 /* In SPT, only 32 bits access is supported,
3838 * so this function should not be called.
3840 if (hw->mac.type >= e1000_pch_spt)
3841 return -E1000_ERR_NVM;
3843 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3850 return E1000_SUCCESS;
3854 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3855 * @hw: pointer to the HW structure
3856 * @offset: The offset (in bytes) of the byte or word to read.
3857 * @size: Size of data to read, 1=byte 2=word
3858 * @data: Pointer to the word to store the value read.
3860 * Reads a byte or word from the NVM using the flash access registers.
3862 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3865 union ich8_hws_flash_status hsfsts;
3866 union ich8_hws_flash_ctrl hsflctl;
3867 u32 flash_linear_addr;
3869 s32 ret_val = -E1000_ERR_NVM;
3872 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3874 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3875 return -E1000_ERR_NVM;
3876 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3877 hw->nvm.flash_base_addr);
3882 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3883 if (ret_val != E1000_SUCCESS)
3885 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3887 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3888 hsflctl.hsf_ctrl.fldbcount = size - 1;
3889 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3890 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3891 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3893 ret_val = e1000_flash_cycle_ich8lan(hw,
3894 ICH_FLASH_READ_COMMAND_TIMEOUT);
3896 /* Check if FCERR is set to 1, if set to 1, clear it
3897 * and try the whole sequence a few more times, else
3898 * read in (shift in) the Flash Data0, the order is
3899 * least significant byte first msb to lsb
3901 if (ret_val == E1000_SUCCESS) {
3902 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3904 *data = (u8)(flash_data & 0x000000FF);
3906 *data = (u16)(flash_data & 0x0000FFFF);
3909 /* If we've gotten here, then things are probably
3910 * completely hosed, but if the error condition is
3911 * detected, it won't hurt to give it another try...
3912 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3914 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3916 if (hsfsts.hsf_status.flcerr) {
3917 /* Repeat for some time before giving up. */
3919 } else if (!hsfsts.hsf_status.flcdone) {
3920 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3924 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3930 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3931 * @hw: pointer to the HW structure
3932 * @offset: The offset (in bytes) of the dword to read.
3933 * @data: Pointer to the dword to store the value read.
3935 * Reads a byte or word from the NVM using the flash access registers.
3937 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3940 union ich8_hws_flash_status hsfsts;
3941 union ich8_hws_flash_ctrl hsflctl;
3942 u32 flash_linear_addr;
3943 s32 ret_val = -E1000_ERR_NVM;
3946 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3948 if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3949 hw->mac.type < e1000_pch_spt)
3950 return -E1000_ERR_NVM;
3951 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3952 hw->nvm.flash_base_addr);
3957 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3958 if (ret_val != E1000_SUCCESS)
3960 /* In SPT, This register is in Lan memory space, not flash.
3961 * Therefore, only 32 bit access is supported
3963 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3965 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3966 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3967 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3968 /* In SPT, This register is in Lan memory space, not flash.
3969 * Therefore, only 32 bit access is supported
3971 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3972 (u32)hsflctl.regval << 16);
3973 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3975 ret_val = e1000_flash_cycle_ich8lan(hw,
3976 ICH_FLASH_READ_COMMAND_TIMEOUT);
3978 /* Check if FCERR is set to 1, if set to 1, clear it
3979 * and try the whole sequence a few more times, else
3980 * read in (shift in) the Flash Data0, the order is
3981 * least significant byte first msb to lsb
3983 if (ret_val == E1000_SUCCESS) {
3984 *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3987 /* If we've gotten here, then things are probably
3988 * completely hosed, but if the error condition is
3989 * detected, it won't hurt to give it another try...
3990 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3992 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3994 if (hsfsts.hsf_status.flcerr) {
3995 /* Repeat for some time before giving up. */
3997 } else if (!hsfsts.hsf_status.flcdone) {
3998 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4002 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4008 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
4009 * @hw: pointer to the HW structure
4010 * @offset: The offset (in bytes) of the word(s) to write.
4011 * @words: Size of data to write in words
4012 * @data: Pointer to the word(s) to write at offset.
4014 * Writes a byte or word to the NVM using the flash access registers.
4016 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
4019 struct e1000_nvm_info *nvm = &hw->nvm;
4020 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4023 DEBUGFUNC("e1000_write_nvm_ich8lan");
4025 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
4027 DEBUGOUT("nvm parameter(s) out of bounds\n");
4028 return -E1000_ERR_NVM;
4031 nvm->ops.acquire(hw);
4033 for (i = 0; i < words; i++) {
4034 dev_spec->shadow_ram[offset+i].modified = TRUE;
4035 dev_spec->shadow_ram[offset+i].value = data[i];
4038 nvm->ops.release(hw);
4040 return E1000_SUCCESS;
4044 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
4045 * @hw: pointer to the HW structure
4047 * The NVM checksum is updated by calling the generic update_nvm_checksum,
4048 * which writes the checksum to the shadow ram. The changes in the shadow
4049 * ram are then committed to the EEPROM by processing each bank at a time
4050 * checking for the modified bit and writing only the pending changes.
4051 * After a successful commit, the shadow ram is cleared and is ready for
4054 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
4056 struct e1000_nvm_info *nvm = &hw->nvm;
4057 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4058 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4062 DEBUGFUNC("e1000_update_nvm_checksum_spt");
4064 ret_val = e1000_update_nvm_checksum_generic(hw);
4068 if (nvm->type != e1000_nvm_flash_sw)
4071 nvm->ops.acquire(hw);
4073 /* We're writing to the opposite bank so if we're on bank 1,
4074 * write to bank 0 etc. We also need to erase the segment that
4075 * is going to be written
4077 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4078 if (ret_val != E1000_SUCCESS) {
4079 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4084 new_bank_offset = nvm->flash_bank_size;
4085 old_bank_offset = 0;
4086 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4090 old_bank_offset = nvm->flash_bank_size;
4091 new_bank_offset = 0;
4092 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4096 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) {
4097 /* Determine whether to write the value stored
4098 * in the other NVM bank or a modified value stored
4101 ret_val = e1000_read_flash_dword_ich8lan(hw,
4102 i + old_bank_offset,
4105 if (dev_spec->shadow_ram[i].modified) {
4106 dword &= 0xffff0000;
4107 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
4109 if (dev_spec->shadow_ram[i + 1].modified) {
4110 dword &= 0x0000ffff;
4111 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
4117 /* If the word is 0x13, then make sure the signature bits
4118 * (15:14) are 11b until the commit has completed.
4119 * This will allow us to write 10b which indicates the
4120 * signature is valid. We want to do this after the write
4121 * has completed so that we don't mark the segment valid
4122 * while the write is still in progress
4124 if (i == E1000_ICH_NVM_SIG_WORD - 1)
4125 dword |= E1000_ICH_NVM_SIG_MASK << 16;
4127 /* Convert offset to bytes. */
4128 act_offset = (i + new_bank_offset) << 1;
4132 /* Write the data to the new bank. Offset in words*/
4133 act_offset = i + new_bank_offset;
4134 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4140 /* Don't bother writing the segment valid bits if sector
4141 * programming failed.
4144 DEBUGOUT("Flash commit failed.\n");
4148 /* Finally validate the new segment by setting bit 15:14
4149 * to 10b in word 0x13 , this can be done without an
4150 * erase as well since these bits are 11 to start with
4151 * and we need to change bit 14 to 0b
4153 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4155 /*offset in words but we read dword*/
4157 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4162 dword &= 0xBFFFFFFF;
4163 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4168 /* And invalidate the previously valid segment by setting
4169 * its signature word (0x13) high_byte to 0b. This can be
4170 * done without an erase because flash erase sets all bits
4171 * to 1's. We can write 1's to 0's without an erase
4173 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4175 /* offset in words but we read dword*/
4176 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
4177 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4182 dword &= 0x00FFFFFF;
4183 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4188 /* Great! Everything worked, we can now clear the cached entries. */
4189 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4190 dev_spec->shadow_ram[i].modified = FALSE;
4191 dev_spec->shadow_ram[i].value = 0xFFFF;
4195 nvm->ops.release(hw);
4197 /* Reload the EEPROM, or else modifications will not appear
4198 * until after the next adapter reset.
4201 nvm->ops.reload(hw);
4207 DEBUGOUT1("NVM update error: %d\n", ret_val);
4213 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
4214 * @hw: pointer to the HW structure
4216 * The NVM checksum is updated by calling the generic update_nvm_checksum,
4217 * which writes the checksum to the shadow ram. The changes in the shadow
4218 * ram are then committed to the EEPROM by processing each bank at a time
4219 * checking for the modified bit and writing only the pending changes.
4220 * After a successful commit, the shadow ram is cleared and is ready for
4223 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
4225 struct e1000_nvm_info *nvm = &hw->nvm;
4226 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4227 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4231 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
4233 ret_val = e1000_update_nvm_checksum_generic(hw);
4237 if (nvm->type != e1000_nvm_flash_sw)
4240 nvm->ops.acquire(hw);
4242 /* We're writing to the opposite bank so if we're on bank 1,
4243 * write to bank 0 etc. We also need to erase the segment that
4244 * is going to be written
4246 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4247 if (ret_val != E1000_SUCCESS) {
4248 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4253 new_bank_offset = nvm->flash_bank_size;
4254 old_bank_offset = 0;
4255 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4259 old_bank_offset = nvm->flash_bank_size;
4260 new_bank_offset = 0;
4261 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4265 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4266 if (dev_spec->shadow_ram[i].modified) {
4267 data = dev_spec->shadow_ram[i].value;
4269 ret_val = e1000_read_flash_word_ich8lan(hw, i +
4275 /* If the word is 0x13, then make sure the signature bits
4276 * (15:14) are 11b until the commit has completed.
4277 * This will allow us to write 10b which indicates the
4278 * signature is valid. We want to do this after the write
4279 * has completed so that we don't mark the segment valid
4280 * while the write is still in progress
4282 if (i == E1000_ICH_NVM_SIG_WORD)
4283 data |= E1000_ICH_NVM_SIG_MASK;
4285 /* Convert offset to bytes. */
4286 act_offset = (i + new_bank_offset) << 1;
4290 /* Write the bytes to the new bank. */
4291 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4298 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4305 /* Don't bother writing the segment valid bits if sector
4306 * programming failed.
4309 DEBUGOUT("Flash commit failed.\n");
4313 /* Finally validate the new segment by setting bit 15:14
4314 * to 10b in word 0x13 , this can be done without an
4315 * erase as well since these bits are 11 to start with
4316 * and we need to change bit 14 to 0b
4318 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4319 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4324 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
4329 /* And invalidate the previously valid segment by setting
4330 * its signature word (0x13) high_byte to 0b. This can be
4331 * done without an erase because flash erase sets all bits
4332 * to 1's. We can write 1's to 0's without an erase
4334 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4336 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4341 /* Great! Everything worked, we can now clear the cached entries. */
4342 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4343 dev_spec->shadow_ram[i].modified = FALSE;
4344 dev_spec->shadow_ram[i].value = 0xFFFF;
4348 nvm->ops.release(hw);
4350 /* Reload the EEPROM, or else modifications will not appear
4351 * until after the next adapter reset.
4354 nvm->ops.reload(hw);
4360 DEBUGOUT1("NVM update error: %d\n", ret_val);
4366 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4367 * @hw: pointer to the HW structure
4369 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4370 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
4371 * calculated, in which case we need to calculate the checksum and set bit 6.
4373 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4378 u16 valid_csum_mask;
4380 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
4382 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4383 * the checksum needs to be fixed. This bit is an indication that
4384 * the NVM was prepared by OEM software and did not calculate
4385 * the checksum...a likely scenario.
4387 switch (hw->mac.type) {
4391 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4394 word = NVM_FUTURE_INIT_WORD1;
4395 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4399 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4403 if (!(data & valid_csum_mask)) {
4404 data |= valid_csum_mask;
4405 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4408 ret_val = hw->nvm.ops.update(hw);
4413 return e1000_validate_nvm_checksum_generic(hw);
4417 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4418 * @hw: pointer to the HW structure
4419 * @offset: The offset (in bytes) of the byte/word to read.
4420 * @size: Size of data to read, 1=byte 2=word
4421 * @data: The byte(s) to write to the NVM.
4423 * Writes one/two bytes to the NVM using the flash access registers.
4425 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4428 union ich8_hws_flash_status hsfsts;
4429 union ich8_hws_flash_ctrl hsflctl;
4430 u32 flash_linear_addr;
4435 DEBUGFUNC("e1000_write_ich8_data");
4437 if (hw->mac.type >= e1000_pch_spt) {
4438 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4439 return -E1000_ERR_NVM;
4441 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4442 return -E1000_ERR_NVM;
4445 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4446 hw->nvm.flash_base_addr);
4451 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4452 if (ret_val != E1000_SUCCESS)
4454 /* In SPT, This register is in Lan memory space, not
4455 * flash. Therefore, only 32 bit access is supported
4457 if (hw->mac.type >= e1000_pch_spt)
4459 E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
4462 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4464 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4465 hsflctl.hsf_ctrl.fldbcount = size - 1;
4466 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4467 /* In SPT, This register is in Lan memory space,
4468 * not flash. Therefore, only 32 bit access is
4471 if (hw->mac.type >= e1000_pch_spt)
4472 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4473 hsflctl.regval << 16);
4475 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4478 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4481 flash_data = (u32)data & 0x00FF;
4483 flash_data = (u32)data;
4485 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
4487 /* check if FCERR is set to 1 , if set to 1, clear it
4488 * and try the whole sequence a few more times else done
4491 e1000_flash_cycle_ich8lan(hw,
4492 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4493 if (ret_val == E1000_SUCCESS)
4496 /* If we're here, then things are most likely
4497 * completely hosed, but if the error condition
4498 * is detected, it won't hurt to give it another
4499 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4501 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4502 if (hsfsts.hsf_status.flcerr)
4503 /* Repeat for some time before giving up. */
4505 if (!hsfsts.hsf_status.flcdone) {
4506 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4509 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4515 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4516 * @hw: pointer to the HW structure
4517 * @offset: The offset (in bytes) of the dwords to read.
4518 * @data: The 4 bytes to write to the NVM.
4520 * Writes one/two/four bytes to the NVM using the flash access registers.
4522 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4525 union ich8_hws_flash_status hsfsts;
4526 union ich8_hws_flash_ctrl hsflctl;
4527 u32 flash_linear_addr;
4531 DEBUGFUNC("e1000_write_flash_data32_ich8lan");
4533 if (hw->mac.type >= e1000_pch_spt) {
4534 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4535 return -E1000_ERR_NVM;
4537 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4538 hw->nvm.flash_base_addr);
4542 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4543 if (ret_val != E1000_SUCCESS)
4546 /* In SPT, This register is in Lan memory space, not
4547 * flash. Therefore, only 32 bit access is supported
4549 if (hw->mac.type >= e1000_pch_spt)
4550 hsflctl.regval = E1000_READ_FLASH_REG(hw,
4554 hsflctl.regval = E1000_READ_FLASH_REG16(hw,
4557 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4558 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4560 /* In SPT, This register is in Lan memory space,
4561 * not flash. Therefore, only 32 bit access is
4564 if (hw->mac.type >= e1000_pch_spt)
4565 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4566 hsflctl.regval << 16);
4568 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4571 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4573 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);
4575 /* check if FCERR is set to 1 , if set to 1, clear it
4576 * and try the whole sequence a few more times else done
4578 ret_val = e1000_flash_cycle_ich8lan(hw,
4579 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4581 if (ret_val == E1000_SUCCESS)
4584 /* If we're here, then things are most likely
4585 * completely hosed, but if the error condition
4586 * is detected, it won't hurt to give it another
4587 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4589 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4591 if (hsfsts.hsf_status.flcerr)
4592 /* Repeat for some time before giving up. */
4594 if (!hsfsts.hsf_status.flcdone) {
4595 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4598 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4604 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4605 * @hw: pointer to the HW structure
4606 * @offset: The index of the byte to read.
4607 * @data: The byte to write to the NVM.
4609 * Writes a single byte to the NVM using the flash access registers.
4611 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4614 u16 word = (u16)data;
4616 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
4618 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4622 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4623 * @hw: pointer to the HW structure
4624 * @offset: The offset of the word to write.
4625 * @dword: The dword to write to the NVM.
4627 * Writes a single dword to the NVM using the flash access registers.
4628 * Goes through a retry algorithm before giving up.
4630 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4631 u32 offset, u32 dword)
4634 u16 program_retries;
4636 DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan");
4638 /* Must convert word offset into bytes. */
4641 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4645 for (program_retries = 0; program_retries < 100; program_retries++) {
4646 DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset);
4648 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4649 if (ret_val == E1000_SUCCESS)
4652 if (program_retries == 100)
4653 return -E1000_ERR_NVM;
4655 return E1000_SUCCESS;
4659 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4660 * @hw: pointer to the HW structure
4661 * @offset: The offset of the byte to write.
4662 * @byte: The byte to write to the NVM.
4664 * Writes a single byte to the NVM using the flash access registers.
4665 * Goes through a retry algorithm before giving up.
4667 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4668 u32 offset, u8 byte)
4671 u16 program_retries;
4673 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
4675 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4679 for (program_retries = 0; program_retries < 100; program_retries++) {
4680 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
4682 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4683 if (ret_val == E1000_SUCCESS)
4686 if (program_retries == 100)
4687 return -E1000_ERR_NVM;
4689 return E1000_SUCCESS;
4693 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4694 * @hw: pointer to the HW structure
4695 * @bank: 0 for first bank, 1 for second bank, etc.
4697 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4698 * bank N is 4096 * N + flash_reg_addr.
4700 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4702 struct e1000_nvm_info *nvm = &hw->nvm;
4703 union ich8_hws_flash_status hsfsts;
4704 union ich8_hws_flash_ctrl hsflctl;
4705 u32 flash_linear_addr;
4706 /* bank size is in 16bit words - adjust to bytes */
4707 u32 flash_bank_size = nvm->flash_bank_size * 2;
4710 s32 j, iteration, sector_size;
4712 DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
4714 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4716 /* Determine HW Sector size: Read BERASE bits of hw flash status
4718 * 00: The Hw sector is 256 bytes, hence we need to erase 16
4719 * consecutive sectors. The start index for the nth Hw sector
4720 * can be calculated as = bank * 4096 + n * 256
4721 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4722 * The start index for the nth Hw sector can be calculated
4724 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4725 * (ich9 only, otherwise error condition)
4726 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4728 switch (hsfsts.hsf_status.berasesz) {
4730 /* Hw sector size 256 */
4731 sector_size = ICH_FLASH_SEG_SIZE_256;
4732 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4735 sector_size = ICH_FLASH_SEG_SIZE_4K;
4739 sector_size = ICH_FLASH_SEG_SIZE_8K;
4743 sector_size = ICH_FLASH_SEG_SIZE_64K;
4747 return -E1000_ERR_NVM;
4750 /* Start with the base address, then add the sector offset. */
4751 flash_linear_addr = hw->nvm.flash_base_addr;
4752 flash_linear_addr += (bank) ? flash_bank_size : 0;
4754 for (j = 0; j < iteration; j++) {
4756 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4759 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4763 /* Write a value 11 (block Erase) in Flash
4764 * Cycle field in hw flash control
4766 if (hw->mac.type >= e1000_pch_spt)
4768 E1000_READ_FLASH_REG(hw,
4769 ICH_FLASH_HSFSTS)>>16;
4772 E1000_READ_FLASH_REG16(hw,
4775 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4776 if (hw->mac.type >= e1000_pch_spt)
4777 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4778 hsflctl.regval << 16);
4780 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4783 /* Write the last 24 bits of an index within the
4784 * block into Flash Linear address field in Flash
4787 flash_linear_addr += (j * sector_size);
4788 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4791 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4792 if (ret_val == E1000_SUCCESS)
4795 /* Check if FCERR is set to 1. If 1,
4796 * clear it and try the whole sequence
4797 * a few more times else Done
4799 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4801 if (hsfsts.hsf_status.flcerr)
4802 /* repeat for some time before giving up */
4804 else if (!hsfsts.hsf_status.flcdone)
4806 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4809 return E1000_SUCCESS;
4813 * e1000_valid_led_default_ich8lan - Set the default LED settings
4814 * @hw: pointer to the HW structure
4815 * @data: Pointer to the LED settings
4817 * Reads the LED default settings from the NVM to data. If the NVM LED
4818 * settings is all 0's or F's, set the LED default to a valid LED default
4821 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4825 DEBUGFUNC("e1000_valid_led_default_ich8lan");
4827 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4829 DEBUGOUT("NVM Read Error\n");
4833 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4834 *data = ID_LED_DEFAULT_ICH8LAN;
4836 return E1000_SUCCESS;
4840 * e1000_id_led_init_pchlan - store LED configurations
4841 * @hw: pointer to the HW structure
4843 * PCH does not control LEDs via the LEDCTL register, rather it uses
4844 * the PHY LED configuration register.
4846 * PCH also does not have an "always on" or "always off" mode which
4847 * complicates the ID feature. Instead of using the "on" mode to indicate
4848 * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4849 * use "link_up" mode. The LEDs will still ID on request if there is no
4850 * link based on logic in e1000_led_[on|off]_pchlan().
4852 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4854 struct e1000_mac_info *mac = &hw->mac;
4856 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4857 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4858 u16 data, i, temp, shift;
4860 DEBUGFUNC("e1000_id_led_init_pchlan");
4862 /* Get default ID LED modes */
4863 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4867 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4868 mac->ledctl_mode1 = mac->ledctl_default;
4869 mac->ledctl_mode2 = mac->ledctl_default;
4871 for (i = 0; i < 4; i++) {
4872 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4875 case ID_LED_ON1_DEF2:
4876 case ID_LED_ON1_ON2:
4877 case ID_LED_ON1_OFF2:
4878 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4879 mac->ledctl_mode1 |= (ledctl_on << shift);
4881 case ID_LED_OFF1_DEF2:
4882 case ID_LED_OFF1_ON2:
4883 case ID_LED_OFF1_OFF2:
4884 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4885 mac->ledctl_mode1 |= (ledctl_off << shift);
4892 case ID_LED_DEF1_ON2:
4893 case ID_LED_ON1_ON2:
4894 case ID_LED_OFF1_ON2:
4895 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4896 mac->ledctl_mode2 |= (ledctl_on << shift);
4898 case ID_LED_DEF1_OFF2:
4899 case ID_LED_ON1_OFF2:
4900 case ID_LED_OFF1_OFF2:
4901 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4902 mac->ledctl_mode2 |= (ledctl_off << shift);
4910 return E1000_SUCCESS;
4914 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4915 * @hw: pointer to the HW structure
4917 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4918 * register, so the bus width is hard coded.
4920 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4922 struct e1000_bus_info *bus = &hw->bus;
4925 DEBUGFUNC("e1000_get_bus_info_ich8lan");
4927 ret_val = e1000_get_bus_info_pcie_generic(hw);
4929 /* ICH devices are "PCI Express"-ish. They have
4930 * a configuration space, but do not contain
4931 * PCI Express Capability registers, so bus width
4932 * must be hardcoded.
4934 if (bus->width == e1000_bus_width_unknown)
4935 bus->width = e1000_bus_width_pcie_x1;
4941 * e1000_reset_hw_ich8lan - Reset the hardware
4942 * @hw: pointer to the HW structure
4944 * Does a full reset of the hardware which includes a reset of the PHY and
4947 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4949 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4954 DEBUGFUNC("e1000_reset_hw_ich8lan");
4956 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4957 * on the last TLP read/write transaction when MAC is reset.
4959 ret_val = e1000_disable_pcie_master_generic(hw);
4961 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4963 DEBUGOUT("Masking off all interrupts\n");
4964 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4966 /* Disable the Transmit and Receive units. Then delay to allow
4967 * any pending transactions to complete before we hit the MAC
4968 * with the global reset.
4970 E1000_WRITE_REG(hw, E1000_RCTL, 0);
4971 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4972 E1000_WRITE_FLUSH(hw);
4976 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4977 if (hw->mac.type == e1000_ich8lan) {
4978 /* Set Tx and Rx buffer allocation to 8k apiece. */
4979 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4980 /* Set Packet Buffer Size to 16k. */
4981 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4984 if (hw->mac.type == e1000_pchlan) {
4985 /* Save the NVM K1 bit setting*/
4986 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4990 if (kum_cfg & E1000_NVM_K1_ENABLE)
4991 dev_spec->nvm_k1_enabled = TRUE;
4993 dev_spec->nvm_k1_enabled = FALSE;
4996 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4998 if (!hw->phy.ops.check_reset_block(hw)) {
4999 /* Full-chip reset requires MAC and PHY reset at the same
5000 * time to make sure the interface between MAC and the
5001 * external PHY is reset.
5003 ctrl |= E1000_CTRL_PHY_RST;
5005 /* Gate automatic PHY configuration by hardware on
5008 if ((hw->mac.type == e1000_pch2lan) &&
5009 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
5010 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
5012 ret_val = e1000_acquire_swflag_ich8lan(hw);
5013 DEBUGOUT("Issuing a global reset to ich8lan\n");
5014 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
5015 /* cannot issue a flush here because it hangs the hardware */
5018 /* Set Phy Config Counter to 50msec */
5019 if (hw->mac.type == e1000_pch2lan) {
5020 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
5021 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
5022 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
5023 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
5027 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
5029 if (ctrl & E1000_CTRL_PHY_RST) {
5030 ret_val = hw->phy.ops.get_cfg_done(hw);
5034 ret_val = e1000_post_phy_reset_ich8lan(hw);
5039 /* For PCH, this write will make sure that any noise
5040 * will be detected as a CRC error and be dropped rather than show up
5041 * as a bad packet to the DMA engine.
5043 if (hw->mac.type == e1000_pchlan)
5044 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
5046 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
5047 E1000_READ_REG(hw, E1000_ICR);
5049 reg = E1000_READ_REG(hw, E1000_KABGTXD);
5050 reg |= E1000_KABGTXD_BGSQLBIAS;
5051 E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
5053 return E1000_SUCCESS;
5057 * e1000_init_hw_ich8lan - Initialize the hardware
5058 * @hw: pointer to the HW structure
5060 * Prepares the hardware for transmit and receive by doing the following:
5061 * - initialize hardware bits
5062 * - initialize LED identification
5063 * - setup receive address registers
5064 * - setup flow control
5065 * - setup transmit descriptors
5066 * - clear statistics
5068 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
5070 struct e1000_mac_info *mac = &hw->mac;
5071 u32 ctrl_ext, txdctl, snoop;
5075 DEBUGFUNC("e1000_init_hw_ich8lan");
5077 e1000_initialize_hw_bits_ich8lan(hw);
5079 /* Initialize identification LED */
5080 ret_val = mac->ops.id_led_init(hw);
5081 /* An error is not fatal and we should not stop init due to this */
5083 DEBUGOUT("Error initializing identification LED\n");
5085 /* Setup the receive address. */
5086 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
5088 /* Zero out the Multicast HASH table */
5089 DEBUGOUT("Zeroing the MTA\n");
5090 for (i = 0; i < mac->mta_reg_count; i++)
5091 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
5093 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
5094 * the ME. Disable wakeup by clearing the host wakeup bit.
5095 * Reset the phy after disabling host wakeup to reset the Rx buffer.
5097 if (hw->phy.type == e1000_phy_82578) {
5098 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
5099 i &= ~BM_WUC_HOST_WU_BIT;
5100 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
5101 ret_val = e1000_phy_hw_reset_ich8lan(hw);
5106 /* Setup link and flow control */
5107 ret_val = mac->ops.setup_link(hw);
5109 /* Set the transmit descriptor write-back policy for both queues */
5110 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
5111 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5112 E1000_TXDCTL_FULL_TX_DESC_WB);
5113 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5114 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5115 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
5116 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
5117 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5118 E1000_TXDCTL_FULL_TX_DESC_WB);
5119 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5120 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5121 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
5123 /* ICH8 has opposite polarity of no_snoop bits.
5124 * By default, we should use snoop behavior.
5126 if (mac->type == e1000_ich8lan)
5127 snoop = PCIE_ICH8_SNOOP_ALL;
5129 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
5130 e1000_set_pcie_no_snoop_generic(hw, snoop);
5132 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5133 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
5134 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5136 /* Clear all of the statistics registers (clear on read). It is
5137 * important that we do this after we have tried to establish link
5138 * because the symbol error count will increment wildly if there
5141 e1000_clear_hw_cntrs_ich8lan(hw);
5147 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
5148 * @hw: pointer to the HW structure
5150 * Sets/Clears required hardware bits necessary for correctly setting up the
5151 * hardware for transmit and receive.
5153 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
5157 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
5159 /* Extended Device Control */
5160 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
5162 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
5163 if (hw->mac.type >= e1000_pchlan)
5164 reg |= E1000_CTRL_EXT_PHYPDEN;
5165 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
5167 /* Transmit Descriptor Control 0 */
5168 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
5170 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
5172 /* Transmit Descriptor Control 1 */
5173 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
5175 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
5177 /* Transmit Arbitration Control 0 */
5178 reg = E1000_READ_REG(hw, E1000_TARC(0));
5179 if (hw->mac.type == e1000_ich8lan)
5180 reg |= (1 << 28) | (1 << 29);
5181 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
5182 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
5184 /* Transmit Arbitration Control 1 */
5185 reg = E1000_READ_REG(hw, E1000_TARC(1));
5186 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
5190 reg |= (1 << 24) | (1 << 26) | (1 << 30);
5191 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
5194 if (hw->mac.type == e1000_ich8lan) {
5195 reg = E1000_READ_REG(hw, E1000_STATUS);
5197 E1000_WRITE_REG(hw, E1000_STATUS, reg);
5200 /* work-around descriptor data corruption issue during nfs v2 udp
5201 * traffic, just disable the nfs filtering capability
5203 reg = E1000_READ_REG(hw, E1000_RFCTL);
5204 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
5206 /* Disable IPv6 extension header parsing because some malformed
5207 * IPv6 headers can hang the Rx.
5209 if (hw->mac.type == e1000_ich8lan)
5210 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
5211 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
5213 /* Enable ECC on Lynxpoint */
5214 if (hw->mac.type >= e1000_pch_lpt) {
5215 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
5216 reg |= E1000_PBECCSTS_ECC_ENABLE;
5217 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
5219 reg = E1000_READ_REG(hw, E1000_CTRL);
5220 reg |= E1000_CTRL_MEHE;
5221 E1000_WRITE_REG(hw, E1000_CTRL, reg);
5228 * e1000_setup_link_ich8lan - Setup flow control and link settings
5229 * @hw: pointer to the HW structure
5231 * Determines which flow control settings to use, then configures flow
5232 * control. Calls the appropriate media-specific link configuration
5233 * function. Assuming the adapter has a valid link partner, a valid link
5234 * should be established. Assumes the hardware has previously been reset
5235 * and the transmitter and receiver are not enabled.
5237 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
5241 DEBUGFUNC("e1000_setup_link_ich8lan");
5243 if (hw->phy.ops.check_reset_block(hw))
5244 return E1000_SUCCESS;
5246 /* ICH parts do not have a word in the NVM to determine
5247 * the default flow control setting, so we explicitly
5250 if (hw->fc.requested_mode == e1000_fc_default)
5251 hw->fc.requested_mode = e1000_fc_full;
5253 /* Save off the requested flow control mode for use later. Depending
5254 * on the link partner's capabilities, we may or may not use this mode.
5256 hw->fc.current_mode = hw->fc.requested_mode;
5258 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
5259 hw->fc.current_mode);
5261 /* Continue to configure the copper link. */
5262 ret_val = hw->mac.ops.setup_physical_interface(hw);
5266 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
5267 if ((hw->phy.type == e1000_phy_82578) ||
5268 (hw->phy.type == e1000_phy_82579) ||
5269 (hw->phy.type == e1000_phy_i217) ||
5270 (hw->phy.type == e1000_phy_82577)) {
5271 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
5273 ret_val = hw->phy.ops.write_reg(hw,
5274 PHY_REG(BM_PORT_CTRL_PAGE, 27),
5280 return e1000_set_fc_watermarks_generic(hw);
5284 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5285 * @hw: pointer to the HW structure
5287 * Configures the kumeran interface to the PHY to wait the appropriate time
5288 * when polling the PHY, then call the generic setup_copper_link to finish
5289 * configuring the copper link.
5291 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5297 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
5299 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5300 ctrl |= E1000_CTRL_SLU;
5301 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5302 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5304 /* Set the mac to wait the maximum time between each iteration
5305 * and increase the max iterations when polling the phy;
5306 * this fixes erroneous timeouts at 10Mbps.
5308 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
5312 ret_val = e1000_read_kmrn_reg_generic(hw,
5313 E1000_KMRNCTRLSTA_INBAND_PARAM,
5318 ret_val = e1000_write_kmrn_reg_generic(hw,
5319 E1000_KMRNCTRLSTA_INBAND_PARAM,
5324 switch (hw->phy.type) {
5325 case e1000_phy_igp_3:
5326 ret_val = e1000_copper_link_setup_igp(hw);
5331 case e1000_phy_82578:
5332 ret_val = e1000_copper_link_setup_m88(hw);
5336 case e1000_phy_82577:
5337 case e1000_phy_82579:
5338 ret_val = e1000_copper_link_setup_82577(hw);
5343 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
5348 reg_data &= ~IFE_PMC_AUTO_MDIX;
5350 switch (hw->phy.mdix) {
5352 reg_data &= ~IFE_PMC_FORCE_MDIX;
5355 reg_data |= IFE_PMC_FORCE_MDIX;
5359 reg_data |= IFE_PMC_AUTO_MDIX;
5362 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
5371 return e1000_setup_copper_link_generic(hw);
5375 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5376 * @hw: pointer to the HW structure
5378 * Calls the PHY specific link setup function and then calls the
5379 * generic setup_copper_link to finish configuring the link for
5380 * Lynxpoint PCH devices
5382 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5387 DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
5389 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5390 ctrl |= E1000_CTRL_SLU;
5391 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5392 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5394 ret_val = e1000_copper_link_setup_82577(hw);
5398 return e1000_setup_copper_link_generic(hw);
5402 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5403 * @hw: pointer to the HW structure
5404 * @speed: pointer to store current link speed
5405 * @duplex: pointer to store the current link duplex
5407 * Calls the generic get_speed_and_duplex to retrieve the current link
5408 * information and then calls the Kumeran lock loss workaround for links at
5411 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5416 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
5418 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
5422 if ((hw->mac.type == e1000_ich8lan) &&
5423 (hw->phy.type == e1000_phy_igp_3) &&
5424 (*speed == SPEED_1000)) {
5425 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5432 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5433 * @hw: pointer to the HW structure
5435 * Work-around for 82566 Kumeran PCS lock loss:
5436 * On link status change (i.e. PCI reset, speed change) and link is up and
5438 * 0) if workaround is optionally disabled do nothing
5439 * 1) wait 1ms for Kumeran link to come up
5440 * 2) check Kumeran Diagnostic register PCS lock loss bit
5441 * 3) if not set the link is locked (all is good), otherwise...
5443 * 5) repeat up to 10 times
5444 * Note: this is only called for IGP3 copper when speed is 1gb.
5446 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5448 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5454 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
5456 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5457 return E1000_SUCCESS;
5459 /* Make sure link is up before proceeding. If not just return.
5460 * Attempting this while link is negotiating fouled up link
5463 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
5465 return E1000_SUCCESS;
5467 for (i = 0; i < 10; i++) {
5468 /* read once to clear */
5469 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5472 /* and again to get new status */
5473 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5477 /* check for PCS lock */
5478 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5479 return E1000_SUCCESS;
5481 /* Issue PHY reset */
5482 hw->phy.ops.reset(hw);
5485 /* Disable GigE link negotiation */
5486 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5487 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5488 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5489 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5491 /* Call gig speed drop workaround on Gig disable before accessing
5494 e1000_gig_downshift_workaround_ich8lan(hw);
5496 /* unable to acquire PCS lock */
5497 return -E1000_ERR_PHY;
5501 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5502 * @hw: pointer to the HW structure
5503 * @state: boolean value used to set the current Kumeran workaround state
5505 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
5506 * /disabled - FALSE).
5508 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5511 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5513 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
5515 if (hw->mac.type != e1000_ich8lan) {
5516 DEBUGOUT("Workaround applies to ICH8 only.\n");
5520 dev_spec->kmrn_lock_loss_workaround_enabled = state;
5526 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5527 * @hw: pointer to the HW structure
5529 * Workaround for 82566 power-down on D3 entry:
5530 * 1) disable gigabit link
5531 * 2) write VR power-down enable
5533 * Continue if successful, else issue LCD reset and repeat
5535 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5541 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
5543 if (hw->phy.type != e1000_phy_igp_3)
5546 /* Try the workaround twice (if needed) */
5549 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
5550 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5551 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5552 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
5554 /* Call gig speed drop workaround on Gig disable before
5555 * accessing any PHY registers
5557 if (hw->mac.type == e1000_ich8lan)
5558 e1000_gig_downshift_workaround_ich8lan(hw);
5560 /* Write VR power-down enable */
5561 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5562 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5563 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
5564 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5566 /* Read it back and test */
5567 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5568 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5569 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5572 /* Issue PHY reset and repeat at most one more time */
5573 reg = E1000_READ_REG(hw, E1000_CTRL);
5574 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
5580 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5581 * @hw: pointer to the HW structure
5583 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5584 * LPLU, Gig disable, MDIC PHY reset):
5585 * 1) Set Kumeran Near-end loopback
5586 * 2) Clear Kumeran Near-end loopback
5587 * Should only be called for ICH8[m] devices with any 1G Phy.
5589 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5594 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
5596 if ((hw->mac.type != e1000_ich8lan) ||
5597 (hw->phy.type == e1000_phy_ife))
5600 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5604 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5605 ret_val = e1000_write_kmrn_reg_generic(hw,
5606 E1000_KMRNCTRLSTA_DIAG_OFFSET,
5610 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5611 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5616 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5617 * @hw: pointer to the HW structure
5619 * During S0 to Sx transition, it is possible the link remains at gig
5620 * instead of negotiating to a lower speed. Before going to Sx, set
5621 * 'Gig Disable' to force link speed negotiation to a lower speed based on
5622 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5623 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5624 * needs to be written.
5625 * Parts that support (and are linked to a partner which support) EEE in
5626 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5627 * than 10Mbps w/o EEE.
5629 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5631 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5635 DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
5637 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5638 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5640 if (hw->phy.type == e1000_phy_i217) {
5641 u16 phy_reg, device_id = hw->device_id;
5643 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5644 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5645 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5646 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5647 (hw->mac.type >= e1000_pch_spt)) {
5648 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
5650 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
5651 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5654 ret_val = hw->phy.ops.acquire(hw);
5658 if (!dev_spec->eee_disable) {
5662 e1000_read_emi_reg_locked(hw,
5663 I217_EEE_ADVERTISEMENT,
5668 /* Disable LPLU if both link partners support 100BaseT
5669 * EEE and 100Full is advertised on both ends of the
5670 * link, and enable Auto Enable LPI since there will
5671 * be no driver to enable LPI while in Sx.
5673 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5674 (dev_spec->eee_lp_ability &
5675 I82579_EEE_100_SUPPORTED) &&
5676 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5677 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5678 E1000_PHY_CTRL_NOND0A_LPLU);
5680 /* Set Auto Enable LPI after link up */
5681 hw->phy.ops.read_reg_locked(hw,
5684 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5685 hw->phy.ops.write_reg_locked(hw,
5691 /* For i217 Intel Rapid Start Technology support,
5692 * when the system is going into Sx and no manageability engine
5693 * is present, the driver must configure proxy to reset only on
5694 * power good. LPI (Low Power Idle) state must also reset only
5695 * on power good, as well as the MTA (Multicast table array).
5696 * The SMBus release must also be disabled on LCD reset.
5698 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5699 E1000_ICH_FWSM_FW_VALID)) {
5700 /* Enable proxy to reset only on power good. */
5701 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
5703 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5704 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
5707 /* Set bit enable LPI (EEE) to reset only on
5710 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
5711 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5712 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
5714 /* Disable the SMB release on LCD reset. */
5715 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
5716 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5717 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5720 /* Enable MTA to reset for Intel Rapid Start Technology
5723 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
5724 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5725 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5728 hw->phy.ops.release(hw);
5731 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5733 if (hw->mac.type == e1000_ich8lan)
5734 e1000_gig_downshift_workaround_ich8lan(hw);
5736 if (hw->mac.type >= e1000_pchlan) {
5737 e1000_oem_bits_config_ich8lan(hw, FALSE);
5739 /* Reset PHY to activate OEM bits on 82577/8 */
5740 if (hw->mac.type == e1000_pchlan)
5741 e1000_phy_hw_reset_generic(hw);
5743 ret_val = hw->phy.ops.acquire(hw);
5746 e1000_write_smbus_addr(hw);
5747 hw->phy.ops.release(hw);
5754 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5755 * @hw: pointer to the HW structure
5757 * During Sx to S0 transitions on non-managed devices or managed devices
5758 * on which PHY resets are not blocked, if the PHY registers cannot be
5759 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
5761 * On i217, setup Intel Rapid Start Technology.
5763 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5767 DEBUGFUNC("e1000_resume_workarounds_pchlan");
5768 if (hw->mac.type < e1000_pch2lan)
5769 return E1000_SUCCESS;
5771 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5773 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5777 /* For i217 Intel Rapid Start Technology support when the system
5778 * is transitioning from Sx and no manageability engine is present
5779 * configure SMBus to restore on reset, disable proxy, and enable
5780 * the reset on MTA (Multicast table array).
5782 if (hw->phy.type == e1000_phy_i217) {
5785 ret_val = hw->phy.ops.acquire(hw);
5787 DEBUGOUT("Failed to setup iRST\n");
5791 /* Clear Auto Enable LPI after link up */
5792 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5793 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5794 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5796 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5797 E1000_ICH_FWSM_FW_VALID)) {
5798 /* Restore clear on SMB if no manageability engine
5801 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5805 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5806 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5809 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5811 /* Enable reset on MTA */
5812 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5816 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5817 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5820 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5821 hw->phy.ops.release(hw);
5824 return E1000_SUCCESS;
5828 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5829 * @hw: pointer to the HW structure
5831 * Return the LED back to the default configuration.
5833 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5835 DEBUGFUNC("e1000_cleanup_led_ich8lan");
5837 if (hw->phy.type == e1000_phy_ife)
5838 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5841 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5842 return E1000_SUCCESS;
5846 * e1000_led_on_ich8lan - Turn LEDs on
5847 * @hw: pointer to the HW structure
5851 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5853 DEBUGFUNC("e1000_led_on_ich8lan");
5855 if (hw->phy.type == e1000_phy_ife)
5856 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5857 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5859 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5860 return E1000_SUCCESS;
5864 * e1000_led_off_ich8lan - Turn LEDs off
5865 * @hw: pointer to the HW structure
5867 * Turn off the LEDs.
5869 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5871 DEBUGFUNC("e1000_led_off_ich8lan");
5873 if (hw->phy.type == e1000_phy_ife)
5874 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5875 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5877 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5878 return E1000_SUCCESS;
5882 * e1000_setup_led_pchlan - Configures SW controllable LED
5883 * @hw: pointer to the HW structure
5885 * This prepares the SW controllable LED for use.
5887 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5889 DEBUGFUNC("e1000_setup_led_pchlan");
5891 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5892 (u16)hw->mac.ledctl_mode1);
5896 * e1000_cleanup_led_pchlan - Restore the default LED operation
5897 * @hw: pointer to the HW structure
5899 * Return the LED back to the default configuration.
5901 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5903 DEBUGFUNC("e1000_cleanup_led_pchlan");
5905 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5906 (u16)hw->mac.ledctl_default);
5910 * e1000_led_on_pchlan - Turn LEDs on
5911 * @hw: pointer to the HW structure
5915 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5917 u16 data = (u16)hw->mac.ledctl_mode2;
5920 DEBUGFUNC("e1000_led_on_pchlan");
5922 /* If no link, then turn LED on by setting the invert bit
5923 * for each LED that's mode is "link_up" in ledctl_mode2.
5925 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5926 for (i = 0; i < 3; i++) {
5927 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5928 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5929 E1000_LEDCTL_MODE_LINK_UP)
5931 if (led & E1000_PHY_LED0_IVRT)
5932 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5934 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5938 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5942 * e1000_led_off_pchlan - Turn LEDs off
5943 * @hw: pointer to the HW structure
5945 * Turn off the LEDs.
5947 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5949 u16 data = (u16)hw->mac.ledctl_mode1;
5952 DEBUGFUNC("e1000_led_off_pchlan");
5954 /* If no link, then turn LED off by clearing the invert bit
5955 * for each LED that's mode is "link_up" in ledctl_mode1.
5957 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5958 for (i = 0; i < 3; i++) {
5959 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5960 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5961 E1000_LEDCTL_MODE_LINK_UP)
5963 if (led & E1000_PHY_LED0_IVRT)
5964 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5966 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5970 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5974 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5975 * @hw: pointer to the HW structure
5977 * Read appropriate register for the config done bit for completion status
5978 * and configure the PHY through s/w for EEPROM-less parts.
5980 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5981 * config done bit, so only an error is logged and continues. If we were
5982 * to return with error, EEPROM-less silicon would not be able to be reset
5985 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5987 s32 ret_val = E1000_SUCCESS;
5991 DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5993 e1000_get_cfg_done_generic(hw);
5995 /* Wait for indication from h/w that it has completed basic config */
5996 if (hw->mac.type >= e1000_ich10lan) {
5997 e1000_lan_init_done_ich8lan(hw);
5999 ret_val = e1000_get_auto_rd_done_generic(hw);
6001 /* When auto config read does not complete, do not
6002 * return with an error. This can happen in situations
6003 * where there is no eeprom and prevents getting link.
6005 DEBUGOUT("Auto Read Done did not complete\n");
6006 ret_val = E1000_SUCCESS;
6010 /* Clear PHY Reset Asserted bit */
6011 status = E1000_READ_REG(hw, E1000_STATUS);
6012 if (status & E1000_STATUS_PHYRA)
6013 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
6015 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
6017 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
6018 if (hw->mac.type <= e1000_ich9lan) {
6019 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
6020 (hw->phy.type == e1000_phy_igp_3)) {
6021 e1000_phy_init_script_igp3(hw);
6024 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
6025 /* Maybe we should do a basic PHY config */
6026 DEBUGOUT("EEPROM not present\n");
6027 ret_val = -E1000_ERR_CONFIG;
6035 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
6036 * @hw: pointer to the HW structure
6038 * In the case of a PHY power down to save power, or to turn off link during a
6039 * driver unload, or wake on lan is not enabled, remove the link.
6041 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
6043 /* If the management interface is not enabled, then power down */
6044 if (!(hw->mac.ops.check_mng_mode(hw) ||
6045 hw->phy.ops.check_reset_block(hw)))
6046 e1000_power_down_phy_copper(hw);
6052 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
6053 * @hw: pointer to the HW structure
6055 * Clears hardware counters specific to the silicon family and calls
6056 * clear_hw_cntrs_generic to clear all general purpose counters.
6058 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
6063 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
6065 e1000_clear_hw_cntrs_base_generic(hw);
6067 E1000_READ_REG(hw, E1000_ALGNERRC);
6068 E1000_READ_REG(hw, E1000_RXERRC);
6069 E1000_READ_REG(hw, E1000_TNCRS);
6070 E1000_READ_REG(hw, E1000_CEXTERR);
6071 E1000_READ_REG(hw, E1000_TSCTC);
6072 E1000_READ_REG(hw, E1000_TSCTFC);
6074 E1000_READ_REG(hw, E1000_MGTPRC);
6075 E1000_READ_REG(hw, E1000_MGTPDC);
6076 E1000_READ_REG(hw, E1000_MGTPTC);
6078 E1000_READ_REG(hw, E1000_IAC);
6079 E1000_READ_REG(hw, E1000_ICRXOC);
6081 /* Clear PHY statistics registers */
6082 if ((hw->phy.type == e1000_phy_82578) ||
6083 (hw->phy.type == e1000_phy_82579) ||
6084 (hw->phy.type == e1000_phy_i217) ||
6085 (hw->phy.type == e1000_phy_82577)) {
6086 ret_val = hw->phy.ops.acquire(hw);
6089 ret_val = hw->phy.ops.set_page(hw,
6090 HV_STATS_PAGE << IGP_PAGE_SHIFT);
6093 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
6094 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
6095 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
6096 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
6097 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
6098 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
6099 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
6100 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
6101 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
6102 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
6103 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
6104 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
6105 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
6106 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
6108 hw->phy.ops.release(hw);