sys/dev/e1000/e1000_ich8lan.c

   1 /******************************************************************************
   2   SPDX-License-Identifier: BSD-3-Clause
   3
   4   Copyright (c) 2001-2015, Intel Corporation
   5   All rights reserved.
   6
   7   Redistribution and use in source and binary forms, with or without
   8   modification, are permitted provided that the following conditions are met:
   9
  10    1. Redistributions of source code must retain the above copyright notice,
  11       this list of conditions and the following disclaimer.
  12
  13    2. Redistributions in binary form must reproduce the above copyright
  14       notice, this list of conditions and the following disclaimer in the
  15       documentation and/or other materials provided with the distribution.
  16
  17    3. Neither the name of the Intel Corporation nor the names of its
  18       contributors may be used to endorse or promote products derived from
  19       this software without specific prior written permission.
  20
  21   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31   POSSIBILITY OF SUCH DAMAGE.
  32
  33 ******************************************************************************/
  34 /*$FreeBSD$*/
  35
  36 /* 82562G 10/100 Network Connection
  37  * 82562G-2 10/100 Network Connection
  38  * 82562GT 10/100 Network Connection
  39  * 82562GT-2 10/100 Network Connection
  40  * 82562V 10/100 Network Connection
  41  * 82562V-2 10/100 Network Connection
  42  * 82566DC-2 Gigabit Network Connection
  43  * 82566DC Gigabit Network Connection
  44  * 82566DM-2 Gigabit Network Connection
  45  * 82566DM Gigabit Network Connection
  46  * 82566MC Gigabit Network Connection
  47  * 82566MM Gigabit Network Connection
  48  * 82567LM Gigabit Network Connection
  49  * 82567LF Gigabit Network Connection
  50  * 82567V Gigabit Network Connection
  51  * 82567LM-2 Gigabit Network Connection
  52  * 82567LF-2 Gigabit Network Connection
  53  * 82567V-2 Gigabit Network Connection
  54  * 82567LF-3 Gigabit Network Connection
  55  * 82567LM-3 Gigabit Network Connection
  56  * 82567LM-4 Gigabit Network Connection
  57  * 82577LM Gigabit Network Connection
  58  * 82577LC Gigabit Network Connection
  59  * 82578DM Gigabit Network Connection
  60  * 82578DC Gigabit Network Connection
  61  * 82579LM Gigabit Network Connection
  62  * 82579V Gigabit Network Connection
  63  * Ethernet Connection I217-LM
  64  * Ethernet Connection I217-V
  65  * Ethernet Connection I218-V
  66  * Ethernet Connection I218-LM
  67  * Ethernet Connection (2) I218-LM
  68  * Ethernet Connection (2) I218-V
  69  * Ethernet Connection (3) I218-LM
  70  * Ethernet Connection (3) I218-V
  71  */
  72
  73 #include "e1000_api.h"
  74
  75 static s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
  76 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
  77 static s32  e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
  78 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
  79 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
  80 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
  81 static int  e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
  82 static int  e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
  83 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
  84 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
  85                                               u8 *mc_addr_list,
  86                                               u32 mc_addr_count);
  87 static s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
  88 static s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
  89 static s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
  90 static s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
  91                                             bool active);
  92 static s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
  93                                             bool active);
  94 static s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  95                                    u16 words, u16 *data);
  96 static s32  e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
  97                                u16 *data);
  98 static s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  99                                     u16 words, u16 *data);
 100 static s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
 101 static s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
 102 static s32  e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
 103 static s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
 104                                             u16 *data);
 105 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 106 static s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
 107 static s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
 108 static s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
 109 static s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
 110 static s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 111 static s32  e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 112 static s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
 113                                            u16 *speed, u16 *duplex);
 114 static s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 115 static s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
 116 static s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
 117 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 118 static s32  e1000_setup_led_pchlan(struct e1000_hw *hw);
 119 static s32  e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 120 static s32  e1000_led_on_pchlan(struct e1000_hw *hw);
 121 static s32  e1000_led_off_pchlan(struct e1000_hw *hw);
 122 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 123 static s32  e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 124 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 125 static s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 126 static s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
 127                                           u32 offset, u8 *data);
 128 static s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 129                                           u8 size, u16 *data);
 130 static s32  e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
 131                                             u32 *data);
 132 static s32  e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
 133                                            u32 offset, u32 *data);
 134 static s32  e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
 135                                              u32 offset, u32 data);
 136 static s32  e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
 137                                                   u32 offset, u32 dword);
 138 static s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
 139                                           u32 offset, u16 *data);
 140 static s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 141                                                  u32 offset, u8 byte);
 142 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 143 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 144 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
 145 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 146 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 147 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 148 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr);
 149
 150 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 151 /* Offset 04h HSFSTS */
 152 union ich8_hws_flash_status {
 153         struct ich8_hsfsts {
 154                 u16 flcdone:1; /* bit 0 Flash Cycle Done */
 155                 u16 flcerr:1; /* bit 1 Flash Cycle Error */
 156                 u16 dael:1; /* bit 2 Direct Access error Log */
 157                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
 158                 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
 159                 u16 reserved1:2; /* bit 13:6 Reserved */
 160                 u16 reserved2:6; /* bit 13:6 Reserved */
 161                 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
 162                 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
 163         } hsf_status;
 164         u16 regval;
 165 };
 166
 167 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 168 /* Offset 06h FLCTL */
 169 union ich8_hws_flash_ctrl {
 170         struct ich8_hsflctl {
 171                 u16 flcgo:1;   /* 0 Flash Cycle Go */
 172                 u16 flcycle:2;   /* 2:1 Flash Cycle */
 173                 u16 reserved:5;   /* 7:3 Reserved  */
 174                 u16 fldbcount:2;   /* 9:8 Flash Data Byte Count */
 175                 u16 flockdn:6;   /* 15:10 Reserved */
 176         } hsf_ctrl;
 177         u16 regval;
 178 };
 179
 180 /* ICH Flash Region Access Permissions */
 181 union ich8_hws_flash_regacc {
 182         struct ich8_flracc {
 183                 u32 grra:8; /* 0:7 GbE region Read Access */
 184                 u32 grwa:8; /* 8:15 GbE region Write Access */
 185                 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
 186                 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
 187         } hsf_flregacc;
 188         u16 regval;
 189 };
 190
 191 /**
 192  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 193  *  @hw: pointer to the HW structure
 194  *
 195  *  Test access to the PHY registers by reading the PHY ID registers.  If
 196  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 197  *  otherwise assume the read PHY ID is correct if it is valid.
 198  *
 199  *  Assumes the sw/fw/hw semaphore is already acquired.
 200  **/
 201 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 202 {
 203         u16 phy_reg = 0;
 204         u32 phy_id = 0;
 205         s32 ret_val = 0;
 206         u16 retry_count;
 207         u32 mac_reg = 0;
 208
 209         for (retry_count = 0; retry_count < 2; retry_count++) {
 210                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
 211                 if (ret_val || (phy_reg == 0xFFFF))
 212                         continue;
 213                 phy_id = (u32)(phy_reg << 16);
 214
 215                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
 216                 if (ret_val || (phy_reg == 0xFFFF)) {
 217                         phy_id = 0;
 218                         continue;
 219                 }
 220                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 221                 break;
 222         }
 223
 224         if (hw->phy.id) {
 225                 if  (hw->phy.id == phy_id)
 226                         goto out;
 227         } else if (phy_id) {
 228                 hw->phy.id = phy_id;
 229                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 230                 goto out;
 231         }
 232
 233         /* In case the PHY needs to be in mdio slow mode,
 234          * set slow mode and try to get the PHY id again.
 235          */
 236         if (hw->mac.type < e1000_pch_lpt) {
 237                 hw->phy.ops.release(hw);
 238                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 239                 if (!ret_val)
 240                         ret_val = e1000_get_phy_id(hw);
 241                 hw->phy.ops.acquire(hw);
 242         }
 243
 244         if (ret_val)
 245                 return FALSE;
 246 out:
 247         if (hw->mac.type >= e1000_pch_lpt) {
 248                 /* Only unforce SMBus if ME is not active */
 249                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
 250                     E1000_ICH_FWSM_FW_VALID)) {
 251                         /* Unforce SMBus mode in PHY */
 252                         hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
 253                         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 254                         hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
 255
 256                         /* Unforce SMBus mode in MAC */
 257                         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 258                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 259                         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 260                 }
 261         }
 262
 263         return TRUE;
 264 }
 265
 266 /**
 267  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 268  *  @hw: pointer to the HW structure
 269  *
 270  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 271  *  used to reset the PHY to a quiescent state when necessary.
 272  **/
 273 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 274 {
 275         u32 mac_reg;
 276
 277         DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
 278
 279         /* Set Phy Config Counter to 50msec */
 280         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
 281         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 282         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 283         E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
 284
 285         /* Toggle LANPHYPC Value bit */
 286         mac_reg = E1000_READ_REG(hw, E1000_CTRL);
 287         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 288         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 289         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 290         E1000_WRITE_FLUSH(hw);
 291         msec_delay(1);
 292         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 293         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 294         E1000_WRITE_FLUSH(hw);
 295
 296         if (hw->mac.type < e1000_pch_lpt) {
 297                 msec_delay(50);
 298         } else {
 299                 u16 count = 20;
 300
 301                 do {
 302                         msec_delay(5);
 303                 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
 304                            E1000_CTRL_EXT_LPCD) && count--);
 305
 306                 msec_delay(30);
 307         }
 308 }
 309
 310 /**
 311  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 312  *  @hw: pointer to the HW structure
 313  *
 314  *  Workarounds/flow necessary for PHY initialization during driver load
 315  *  and resume paths.
 316  **/
 317 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 318 {
 319         u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
 320         s32 ret_val;
 321
 322         DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
 323
 324         /* Gate automatic PHY configuration by hardware on managed and
 325          * non-managed 82579 and newer adapters.
 326          */
 327         e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
 328
 329         /* It is not possible to be certain of the current state of ULP
 330          * so forcibly disable it.
 331          */
 332         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 333         e1000_disable_ulp_lpt_lp(hw, TRUE);
 334
 335         ret_val = hw->phy.ops.acquire(hw);
 336         if (ret_val) {
 337                 DEBUGOUT("Failed to initialize PHY flow\n");
 338                 goto out;
 339         }
 340
 341         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 342          * inaccessible and resetting the PHY is not blocked, toggle the
 343          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 344          */
 345         switch (hw->mac.type) {
 346         case e1000_pch_lpt:
 347         case e1000_pch_spt:
 348         case e1000_pch_cnp:
 349                 if (e1000_phy_is_accessible_pchlan(hw))
 350                         break;
 351
 352                 /* Before toggling LANPHYPC, see if PHY is accessible by
 353                  * forcing MAC to SMBus mode first.
 354                  */
 355                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 356                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 357                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 358
 359                 /* Wait 50 milliseconds for MAC to finish any retries
 360                  * that it might be trying to perform from previous
 361                  * attempts to acknowledge any phy read requests.
 362                  */
 363                  msec_delay(50);
 364
 365                 /* fall-through */
 366         case e1000_pch2lan:
 367                 if (e1000_phy_is_accessible_pchlan(hw))
 368                         break;
 369
 370                 /* fall-through */
 371         case e1000_pchlan:
 372                 if ((hw->mac.type == e1000_pchlan) &&
 373                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 374                         break;
 375
 376                 if (hw->phy.ops.check_reset_block(hw)) {
 377                         DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
 378                         ret_val = -E1000_ERR_PHY;
 379                         break;
 380                 }
 381
 382                 /* Toggle LANPHYPC Value bit */
 383                 e1000_toggle_lanphypc_pch_lpt(hw);
 384                 if (hw->mac.type >= e1000_pch_lpt) {
 385                         if (e1000_phy_is_accessible_pchlan(hw))
 386                                 break;
 387
 388                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 389                          * so ensure that the MAC is also out of SMBus mode
 390                          */
 391                         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 392                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 393                         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 394
 395                         if (e1000_phy_is_accessible_pchlan(hw))
 396                                 break;
 397
 398                         ret_val = -E1000_ERR_PHY;
 399                 }
 400                 break;
 401         default:
 402                 break;
 403         }
 404
 405         hw->phy.ops.release(hw);
 406         if (!ret_val) {
 407
 408                 /* Check to see if able to reset PHY.  Print error if not */
 409                 if (hw->phy.ops.check_reset_block(hw)) {
 410                         ERROR_REPORT("Reset blocked by ME\n");
 411                         goto out;
 412                 }
 413
 414                 /* Reset the PHY before any access to it.  Doing so, ensures
 415                  * that the PHY is in a known good state before we read/write
 416                  * PHY registers.  The generic reset is sufficient here,
 417                  * because we haven't determined the PHY type yet.
 418                  */
 419                 ret_val = e1000_phy_hw_reset_generic(hw);
 420                 if (ret_val)
 421                         goto out;
 422
 423                 /* On a successful reset, possibly need to wait for the PHY
 424                  * to quiesce to an accessible state before returning control
 425                  * to the calling function.  If the PHY does not quiesce, then
 426                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 427                  *  the PHY is in.
 428                  */
 429                 ret_val = hw->phy.ops.check_reset_block(hw);
 430                 if (ret_val)
 431                         ERROR_REPORT("ME blocked access to PHY after reset\n");
 432         }
 433
 434 out:
 435         /* Ungate automatic PHY configuration on non-managed 82579 */
 436         if ((hw->mac.type == e1000_pch2lan) &&
 437             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 438                 msec_delay(10);
 439                 e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
 440         }
 441
 442         return ret_val;
 443 }
 444
 445 /**
 446  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 447  *  @hw: pointer to the HW structure
 448  *
 449  *  Initialize family-specific PHY parameters and function pointers.
 450  **/
 451 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 452 {
 453         struct e1000_phy_info *phy = &hw->phy;
 454         s32 ret_val;
 455
 456         DEBUGFUNC("e1000_init_phy_params_pchlan");
 457
 458         phy->addr               = 1;
 459         phy->reset_delay_us     = 100;
 460
 461         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 462         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 463         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 464         phy->ops.set_page       = e1000_set_page_igp;
 465         phy->ops.read_reg       = e1000_read_phy_reg_hv;
 466         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 467         phy->ops.read_reg_page  = e1000_read_phy_reg_page_hv;
 468         phy->ops.release        = e1000_release_swflag_ich8lan;
 469         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 470         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 471         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 472         phy->ops.write_reg      = e1000_write_phy_reg_hv;
 473         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 474         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 475         phy->ops.power_up       = e1000_power_up_phy_copper;
 476         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 477         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 478
 479         phy->id = e1000_phy_unknown;
 480
 481         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 482         if (ret_val)
 483                 return ret_val;
 484
 485         if (phy->id == e1000_phy_unknown)
 486                 switch (hw->mac.type) {
 487                 default:
 488                         ret_val = e1000_get_phy_id(hw);
 489                         if (ret_val)
 490                                 return ret_val;
 491                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 492                                 break;
 493                         /* fall-through */
 494                 case e1000_pch2lan:
 495                 case e1000_pch_lpt:
 496                 case e1000_pch_spt:
 497                 case e1000_pch_cnp:
 498                         /* In case the PHY needs to be in mdio slow mode,
 499                          * set slow mode and try to get the PHY id again.
 500                          */
 501                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 502                         if (ret_val)
 503                                 return ret_val;
 504                         ret_val = e1000_get_phy_id(hw);
 505                         if (ret_val)
 506                                 return ret_val;
 507                         break;
 508                 }
 509         phy->type = e1000_get_phy_type_from_id(phy->id);
 510
 511         switch (phy->type) {
 512         case e1000_phy_82577:
 513         case e1000_phy_82579:
 514         case e1000_phy_i217:
 515                 phy->ops.check_polarity = e1000_check_polarity_82577;
 516                 phy->ops.force_speed_duplex =
 517                         e1000_phy_force_speed_duplex_82577;
 518                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 519                 phy->ops.get_info = e1000_get_phy_info_82577;
 520                 phy->ops.commit = e1000_phy_sw_reset_generic;
 521                 break;
 522         case e1000_phy_82578:
 523                 phy->ops.check_polarity = e1000_check_polarity_m88;
 524                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 525                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 526                 phy->ops.get_info = e1000_get_phy_info_m88;
 527                 break;
 528         default:
 529                 ret_val = -E1000_ERR_PHY;
 530                 break;
 531         }
 532
 533         return ret_val;
 534 }
 535
 536 /**
 537  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 538  *  @hw: pointer to the HW structure
 539  *
 540  *  Initialize family-specific PHY parameters and function pointers.
 541  **/
 542 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 543 {
 544         struct e1000_phy_info *phy = &hw->phy;
 545         s32 ret_val;
 546         u16 i = 0;
 547
 548         DEBUGFUNC("e1000_init_phy_params_ich8lan");
 549
 550         phy->addr               = 1;
 551         phy->reset_delay_us     = 100;
 552
 553         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 554         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 555         phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 556         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 557         phy->ops.read_reg       = e1000_read_phy_reg_igp;
 558         phy->ops.release        = e1000_release_swflag_ich8lan;
 559         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 560         phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
 561         phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
 562         phy->ops.write_reg      = e1000_write_phy_reg_igp;
 563         phy->ops.power_up       = e1000_power_up_phy_copper;
 564         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 565
 566         /* We may need to do this twice - once for IGP and if that fails,
 567          * we'll set BM func pointers and try again
 568          */
 569         ret_val = e1000_determine_phy_address(hw);
 570         if (ret_val) {
 571                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 572                 phy->ops.read_reg  = e1000_read_phy_reg_bm;
 573                 ret_val = e1000_determine_phy_address(hw);
 574                 if (ret_val) {
 575                         DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
 576                         return ret_val;
 577                 }
 578         }
 579
 580         phy->id = 0;
 581         while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
 582                (i++ < 100)) {
 583                 msec_delay(1);
 584                 ret_val = e1000_get_phy_id(hw);
 585                 if (ret_val)
 586                         return ret_val;
 587         }
 588
 589         /* Verify phy id */
 590         switch (phy->id) {
 591         case IGP03E1000_E_PHY_ID:
 592                 phy->type = e1000_phy_igp_3;
 593                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 594                 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
 595                 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
 596                 phy->ops.get_info = e1000_get_phy_info_igp;
 597                 phy->ops.check_polarity = e1000_check_polarity_igp;
 598                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 599                 break;
 600         case IFE_E_PHY_ID:
 601         case IFE_PLUS_E_PHY_ID:
 602         case IFE_C_E_PHY_ID:
 603                 phy->type = e1000_phy_ife;
 604                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 605                 phy->ops.get_info = e1000_get_phy_info_ife;
 606                 phy->ops.check_polarity = e1000_check_polarity_ife;
 607                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 608                 break;
 609         case BME1000_E_PHY_ID:
 610                 phy->type = e1000_phy_bm;
 611                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 612                 phy->ops.read_reg = e1000_read_phy_reg_bm;
 613                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 614                 phy->ops.commit = e1000_phy_sw_reset_generic;
 615                 phy->ops.get_info = e1000_get_phy_info_m88;
 616                 phy->ops.check_polarity = e1000_check_polarity_m88;
 617                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 618                 break;
 619         default:
 620                 return -E1000_ERR_PHY;
 621                 break;
 622         }
 623
 624         return E1000_SUCCESS;
 625 }
 626
 627 /**
 628  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 629  *  @hw: pointer to the HW structure
 630  *
 631  *  Initialize family-specific NVM parameters and function
 632  *  pointers.
 633  **/
 634 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 635 {
 636         struct e1000_nvm_info *nvm = &hw->nvm;
 637         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 638         u32 gfpreg, sector_base_addr, sector_end_addr;
 639         u16 i;
 640         u32 nvm_size;
 641
 642         DEBUGFUNC("e1000_init_nvm_params_ich8lan");
 643
 644         nvm->type = e1000_nvm_flash_sw;
 645
 646         if (hw->mac.type >= e1000_pch_spt) {
 647                 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
 648                  * STRAP register. This is because in SPT the GbE Flash region
 649                  * is no longer accessed through the flash registers. Instead,
 650                  * the mechanism has changed, and the Flash region access
 651                  * registers are now implemented in GbE memory space.
 652                  */
 653                 nvm->flash_base_addr = 0;
 654                 nvm_size =
 655                     (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
 656                     * NVM_SIZE_MULTIPLIER;
 657                 nvm->flash_bank_size = nvm_size / 2;
 658                 /* Adjust to word count */
 659                 nvm->flash_bank_size /= sizeof(u16);
 660                 /* Set the base address for flash register access */
 661                 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
 662         } else {
 663                 /* Can't read flash registers if register set isn't mapped. */
 664                 if (!hw->flash_address) {
 665                         DEBUGOUT("ERROR: Flash registers not mapped\n");
 666                         return -E1000_ERR_CONFIG;
 667                 }
 668
 669                 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
 670
 671                 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 672                  * Add 1 to sector_end_addr since this sector is included in
 673                  * the overall size.
 674                  */
 675                 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 676                 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 677
 678                 /* flash_base_addr is byte-aligned */
 679                 nvm->flash_base_addr = sector_base_addr
 680                                        << FLASH_SECTOR_ADDR_SHIFT;
 681
 682                 /* find total size of the NVM, then cut in half since the total
 683                  * size represents two separate NVM banks.
 684                  */
 685                 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 686                                         << FLASH_SECTOR_ADDR_SHIFT);
 687                 nvm->flash_bank_size /= 2;
 688                 /* Adjust to word count */
 689                 nvm->flash_bank_size /= sizeof(u16);
 690         }
 691
 692         nvm->word_size = E1000_SHADOW_RAM_WORDS;
 693
 694         /* Clear shadow ram */
 695         for (i = 0; i < nvm->word_size; i++) {
 696                 dev_spec->shadow_ram[i].modified = FALSE;
 697                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 698         }
 699
 700         /* Function Pointers */
 701         nvm->ops.acquire        = e1000_acquire_nvm_ich8lan;
 702         nvm->ops.release        = e1000_release_nvm_ich8lan;
 703         if (hw->mac.type >= e1000_pch_spt) {
 704                 nvm->ops.read   = e1000_read_nvm_spt;
 705                 nvm->ops.update = e1000_update_nvm_checksum_spt;
 706         } else {
 707                 nvm->ops.read   = e1000_read_nvm_ich8lan;
 708                 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
 709         }
 710         nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
 711         nvm->ops.validate       = e1000_validate_nvm_checksum_ich8lan;
 712         nvm->ops.write          = e1000_write_nvm_ich8lan;
 713
 714         return E1000_SUCCESS;
 715 }
 716
 717 /**
 718  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 719  *  @hw: pointer to the HW structure
 720  *
 721  *  Initialize family-specific MAC parameters and function
 722  *  pointers.
 723  **/
 724 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 725 {
 726         struct e1000_mac_info *mac = &hw->mac;
 727
 728         DEBUGFUNC("e1000_init_mac_params_ich8lan");
 729
 730         /* Set media type function pointer */
 731         hw->phy.media_type = e1000_media_type_copper;
 732
 733         /* Set mta register count */
 734         mac->mta_reg_count = 32;
 735         /* Set rar entry count */
 736         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 737         if (mac->type == e1000_ich8lan)
 738                 mac->rar_entry_count--;
 739         /* Set if part includes ASF firmware */
 740         mac->asf_firmware_present = TRUE;
 741         /* FWSM register */
 742         mac->has_fwsm = TRUE;
 743         /* ARC subsystem not supported */
 744         mac->arc_subsystem_valid = FALSE;
 745         /* Adaptive IFS supported */
 746         mac->adaptive_ifs = TRUE;
 747
 748         /* Function pointers */
 749
 750         /* bus type/speed/width */
 751         mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
 752         /* function id */
 753         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 754         /* reset */
 755         mac->ops.reset_hw = e1000_reset_hw_ich8lan;
 756         /* hw initialization */
 757         mac->ops.init_hw = e1000_init_hw_ich8lan;
 758         /* link setup */
 759         mac->ops.setup_link = e1000_setup_link_ich8lan;
 760         /* physical interface setup */
 761         mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
 762         /* check for link */
 763         mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
 764         /* link info */
 765         mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
 766         /* multicast address update */
 767         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 768         /* clear hardware counters */
 769         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
 770
 771         /* LED and other operations */
 772         switch (mac->type) {
 773         case e1000_ich8lan:
 774         case e1000_ich9lan:
 775         case e1000_ich10lan:
 776                 /* check management mode */
 777                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 778                 /* ID LED init */
 779                 mac->ops.id_led_init = e1000_id_led_init_generic;
 780                 /* blink LED */
 781                 mac->ops.blink_led = e1000_blink_led_generic;
 782                 /* setup LED */
 783                 mac->ops.setup_led = e1000_setup_led_generic;
 784                 /* cleanup LED */
 785                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 786                 /* turn on/off LED */
 787                 mac->ops.led_on = e1000_led_on_ich8lan;
 788                 mac->ops.led_off = e1000_led_off_ich8lan;
 789                 break;
 790         case e1000_pch2lan:
 791                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 792                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 793                 /* fall-through */
 794         case e1000_pch_lpt:
 795         case e1000_pch_spt:
 796         case e1000_pch_cnp:
 797                 /* multicast address update for pch2 */
 798                 mac->ops.update_mc_addr_list =
 799                         e1000_update_mc_addr_list_pch2lan;
 800                 /* fall-through */
 801         case e1000_pchlan:
 802                 /* check management mode */
 803                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 804                 /* ID LED init */
 805                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 806                 /* setup LED */
 807                 mac->ops.setup_led = e1000_setup_led_pchlan;
 808                 /* cleanup LED */
 809                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 810                 /* turn on/off LED */
 811                 mac->ops.led_on = e1000_led_on_pchlan;
 812                 mac->ops.led_off = e1000_led_off_pchlan;
 813                 break;
 814         default:
 815                 break;
 816         }
 817
 818         if (mac->type >= e1000_pch_lpt) {
 819                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 820                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 821                 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
 822                 mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt;
 823         }
 824
 825         /* Enable PCS Lock-loss workaround for ICH8 */
 826         if (mac->type == e1000_ich8lan)
 827                 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
 828
 829         return E1000_SUCCESS;
 830 }
 831
 832 /**
 833  *  __e1000_access_emi_reg_locked - Read/write EMI register
 834  *  @hw: pointer to the HW structure
 835  *  @addr: EMI address to program
 836  *  @data: pointer to value to read/write from/to the EMI address
 837  *  @read: boolean flag to indicate read or write
 838  *
 839  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 840  **/
 841 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 842                                          u16 *data, bool read)
 843 {
 844         s32 ret_val;
 845
 846         DEBUGFUNC("__e1000_access_emi_reg_locked");
 847
 848         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
 849         if (ret_val)
 850                 return ret_val;
 851
 852         if (read)
 853                 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
 854                                                       data);
 855         else
 856                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
 857                                                        *data);
 858
 859         return ret_val;
 860 }
 861
 862 /**
 863  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 864  *  @hw: pointer to the HW structure
 865  *  @addr: EMI address to program
 866  *  @data: value to be read from the EMI address
 867  *
 868  *  Assumes the SW/FW/HW Semaphore is already acquired.
 869  **/
 870 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 871 {
 872         DEBUGFUNC("e1000_read_emi_reg_locked");
 873
 874         return __e1000_access_emi_reg_locked(hw, addr, data, TRUE);
 875 }
 876
 877 /**
 878  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 879  *  @hw: pointer to the HW structure
 880  *  @addr: EMI address to program
 881  *  @data: value to be written to the EMI address
 882  *
 883  *  Assumes the SW/FW/HW Semaphore is already acquired.
 884  **/
 885 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 886 {
 887         DEBUGFUNC("e1000_read_emi_reg_locked");
 888
 889         return __e1000_access_emi_reg_locked(hw, addr, &data, FALSE);
 890 }
 891
 892 /**
 893  *  e1000_set_eee_pchlan - Enable/disable EEE support
 894  *  @hw: pointer to the HW structure
 895  *
 896  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 897  *  the link and the EEE capabilities of the link partner.  The LPI Control
 898  *  register bits will remain set only if/when link is up.
 899  *
 900  *  EEE LPI must not be asserted earlier than one second after link is up.
 901  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 902  *  can be link issues with some switches.  Other devices can have EEE LPI
 903  *  enabled immediately upon link up since they have a timer in hardware which
 904  *  prevents LPI from being asserted too early.
 905  **/
 906 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 907 {
 908         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 909         s32 ret_val;
 910         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 911
 912         DEBUGFUNC("e1000_set_eee_pchlan");
 913
 914         switch (hw->phy.type) {
 915         case e1000_phy_82579:
 916                 lpa = I82579_EEE_LP_ABILITY;
 917                 pcs_status = I82579_EEE_PCS_STATUS;
 918                 adv_addr = I82579_EEE_ADVERTISEMENT;
 919                 break;
 920         case e1000_phy_i217:
 921                 lpa = I217_EEE_LP_ABILITY;
 922                 pcs_status = I217_EEE_PCS_STATUS;
 923                 adv_addr = I217_EEE_ADVERTISEMENT;
 924                 break;
 925         default:
 926                 return E1000_SUCCESS;
 927         }
 928
 929         ret_val = hw->phy.ops.acquire(hw);
 930         if (ret_val)
 931                 return ret_val;
 932
 933         ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 934         if (ret_val)
 935                 goto release;
 936
 937         /* Clear bits that enable EEE in various speeds */
 938         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 939
 940         /* Enable EEE if not disabled by user */
 941         if (!dev_spec->eee_disable) {
 942                 /* Save off link partner's EEE ability */
 943                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 944                                                     &dev_spec->eee_lp_ability);
 945                 if (ret_val)
 946                         goto release;
 947
 948                 /* Read EEE advertisement */
 949                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 950                 if (ret_val)
 951                         goto release;
 952
 953                 /* Enable EEE only for speeds in which the link partner is
 954                  * EEE capable and for which we advertise EEE.
 955                  */
 956                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 957                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 958
 959                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 960                         hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
 961                         if (data & NWAY_LPAR_100TX_FD_CAPS)
 962                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 963                         else
 964                                 /* EEE is not supported in 100Half, so ignore
 965                                  * partner's EEE in 100 ability if full-duplex
 966                                  * is not advertised.
 967                                  */
 968                                 dev_spec->eee_lp_ability &=
 969                                     ~I82579_EEE_100_SUPPORTED;
 970                 }
 971         }
 972
 973         if (hw->phy.type == e1000_phy_82579) {
 974                 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 975                                                     &data);
 976                 if (ret_val)
 977                         goto release;
 978
 979                 data &= ~I82579_LPI_100_PLL_SHUT;
 980                 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 981                                                      data);
 982         }
 983
 984         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 985         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 986         if (ret_val)
 987                 goto release;
 988
 989         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 990 release:
 991         hw->phy.ops.release(hw);
 992
 993         return ret_val;
 994 }
 995
 996 /**
 997  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 998  *  @hw:   pointer to the HW structure
 999  *  @link: link up bool flag
1000  *
1001  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
1002  *  preventing further DMA write requests.  Workaround the issue by disabling
1003  *  the de-assertion of the clock request when in 1Gpbs mode.
1004  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
1005  *  speeds in order to avoid Tx hangs.
1006  **/
1007 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
1008 {
1009         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1010         u32 status = E1000_READ_REG(hw, E1000_STATUS);
1011         s32 ret_val = E1000_SUCCESS;
1012         u16 reg;
1013
1014         if (link && (status & E1000_STATUS_SPEED_1000)) {
1015                 ret_val = hw->phy.ops.acquire(hw);
1016                 if (ret_val)
1017                         return ret_val;
1018
1019                 ret_val =
1020                     e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1021                                                &reg);
1022                 if (ret_val)
1023                         goto release;
1024
1025                 ret_val =
1026                     e1000_write_kmrn_reg_locked(hw,
1027                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
1028                                                 reg &
1029                                                 ~E1000_KMRNCTRLSTA_K1_ENABLE);
1030                 if (ret_val)
1031                         goto release;
1032
1033                 usec_delay(10);
1034
1035                 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1036                                 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1037
1038                 ret_val =
1039                     e1000_write_kmrn_reg_locked(hw,
1040                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
1041                                                 reg);
1042 release:
1043                 hw->phy.ops.release(hw);
1044         } else {
1045                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1046                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1047
1048                 if ((hw->phy.revision > 5) || !link ||
1049                     ((status & E1000_STATUS_SPEED_100) &&
1050                      (status & E1000_STATUS_FD)))
1051                         goto update_fextnvm6;
1052
1053                 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);
1054                 if (ret_val)
1055                         return ret_val;
1056
1057                 /* Clear link status transmit timeout */
1058                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1059
1060                 if (status & E1000_STATUS_SPEED_100) {
1061                         /* Set inband Tx timeout to 5x10us for 100Half */
1062                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1063
1064                         /* Do not extend the K1 entry latency for 100Half */
1065                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1066                 } else {
1067                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
1068                         reg |= 50 <<
1069                                I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1070
1071                         /* Extend the K1 entry latency for 10 Mbps */
1072                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1073                 }
1074
1075                 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1076                 if (ret_val)
1077                         return ret_val;
1078
1079 update_fextnvm6:
1080                 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1081         }
1082
1083         return ret_val;
1084 }
1085
1086 static u64 e1000_ltr2ns(u16 ltr)
1087 {
1088         u32 value, scale;
1089
1090         /* Determine the latency in nsec based on the LTR value & scale */
1091         value = ltr & E1000_LTRV_VALUE_MASK;
1092         scale = (ltr & E1000_LTRV_SCALE_MASK) >> E1000_LTRV_SCALE_SHIFT;
1093
1094         return value * (1ULL << (scale * E1000_LTRV_SCALE_FACTOR));
1095 }
1096
1097 /**
1098  *  e1000_platform_pm_pch_lpt - Set platform power management values
1099  *  @hw: pointer to the HW structure
1100  *  @link: bool indicating link status
1101  *
1102  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
1103  *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
1104  *  when link is up (which must not exceed the maximum latency supported
1105  *  by the platform), otherwise specify there is no LTR requirement.
1106  *  Unlike TRUE-PCIe devices which set the LTR maximum snoop/no-snoop
1107  *  latencies in the LTR Extended Capability Structure in the PCIe Extended
1108  *  Capability register set, on this device LTR is set by writing the
1109  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1110  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1111  *  message to the PMC.
1112  *
1113  *  Use the LTR value to calculate the Optimized Buffer Flush/Fill (OBFF)
1114  *  high-water mark.
1115  **/
1116 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1117 {
1118         u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1119                   link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1120         u16 lat_enc = 0;        /* latency encoded */
1121         s32 obff_hwm = 0;
1122
1123         DEBUGFUNC("e1000_platform_pm_pch_lpt");
1124
1125         if (link) {
1126                 u16 speed, duplex, scale = 0;
1127                 u16 max_snoop, max_nosnoop;
1128                 u16 max_ltr_enc;        /* max LTR latency encoded */
1129                 s64 lat_ns;
1130                 s64 value;
1131                 u32 rxa;
1132
1133                 if (!hw->mac.max_frame_size) {
1134                         DEBUGOUT("max_frame_size not set.\n");
1135                         return -E1000_ERR_CONFIG;
1136                 }
1137
1138                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1139                 if (!speed) {
1140                         DEBUGOUT("Speed not set.\n");
1141                         return -E1000_ERR_CONFIG;
1142                 }
1143
1144                 /* Rx Packet Buffer Allocation size (KB) */
1145                 rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK;
1146
1147                 /* Determine the maximum latency tolerated by the device.
1148                  *
1149                  * Per the PCIe spec, the tolerated latencies are encoded as
1150                  * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1151                  * a 10-bit value (0-1023) to provide a range from 1 ns to
1152                  * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
1153                  * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1154                  */
1155                 lat_ns = ((s64)rxa * 1024 -
1156                           (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000;
1157                 if (lat_ns < 0)
1158                         lat_ns = 0;
1159                 else
1160                         lat_ns /= speed;
1161                 value = lat_ns;
1162
1163                 while (value > E1000_LTRV_VALUE_MASK) {
1164                         scale++;
1165                         value = E1000_DIVIDE_ROUND_UP(value, (1 << 5));
1166                 }
1167                 if (scale > E1000_LTRV_SCALE_MAX) {
1168                         DEBUGOUT1("Invalid LTR latency scale %d\n", scale);
1169                         return -E1000_ERR_CONFIG;
1170                 }
1171                 lat_enc = (u16)((scale << E1000_LTRV_SCALE_SHIFT) | value);
1172
1173                 /* Determine the maximum latency tolerated by the platform */
1174                 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop);
1175                 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1176                 max_ltr_enc = E1000_MAX(max_snoop, max_nosnoop);
1177
1178                 if (lat_enc > max_ltr_enc) {
1179                         lat_enc = max_ltr_enc;
1180                         lat_ns = e1000_ltr2ns(max_ltr_enc);
1181                 }
1182
1183                 if (lat_ns) {
1184                         lat_ns *= speed * 1000;
1185                         lat_ns /= 8;
1186                         lat_ns /= 1000000000;
1187                         obff_hwm = (s32)(rxa - lat_ns);
1188                 }
1189                 if ((obff_hwm < 0) || (obff_hwm > E1000_SVT_OFF_HWM_MASK)) {
1190                         DEBUGOUT1("Invalid high water mark %d\n", obff_hwm);
1191                         return -E1000_ERR_CONFIG;
1192                 }
1193         }
1194
1195         /* Set Snoop and No-Snoop latencies the same */
1196         reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1197         E1000_WRITE_REG(hw, E1000_LTRV, reg);
1198
1199         /* Set OBFF high water mark */
1200         reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK;
1201         reg |= obff_hwm;
1202         E1000_WRITE_REG(hw, E1000_SVT, reg);
1203
1204         /* Enable OBFF */
1205         reg = E1000_READ_REG(hw, E1000_SVCR);
1206         reg |= E1000_SVCR_OFF_EN;
1207         /* Always unblock interrupts to the CPU even when the system is
1208          * in OBFF mode. This ensures that small round-robin traffic
1209          * (like ping) does not get dropped or experience long latency.
1210          */
1211         reg |= E1000_SVCR_OFF_MASKINT;
1212         E1000_WRITE_REG(hw, E1000_SVCR, reg);
1213
1214         return E1000_SUCCESS;
1215 }
1216
1217 /**
1218  *  e1000_set_obff_timer_pch_lpt - Update Optimized Buffer Flush/Fill timer
1219  *  @hw: pointer to the HW structure
1220  *  @itr: interrupt throttling rate
1221  *
1222  *  Configure OBFF with the updated interrupt rate.
1223  **/
1224 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr)
1225 {
1226         u32 svcr;
1227         s32 timer;
1228
1229         DEBUGFUNC("e1000_set_obff_timer_pch_lpt");
1230
1231         /* Convert ITR value into microseconds for OBFF timer */
1232         timer = itr & E1000_ITR_MASK;
1233         timer = (timer * E1000_ITR_MULT) / 1000;
1234
1235         if ((timer < 0) || (timer > E1000_ITR_MASK)) {
1236                 DEBUGOUT1("Invalid OBFF timer %d\n", timer);
1237                 return -E1000_ERR_CONFIG;
1238         }
1239
1240         svcr = E1000_READ_REG(hw, E1000_SVCR);
1241         svcr &= ~E1000_SVCR_OFF_TIMER_MASK;
1242         svcr |= timer << E1000_SVCR_OFF_TIMER_SHIFT;
1243         E1000_WRITE_REG(hw, E1000_SVCR, svcr);
1244
1245         return E1000_SUCCESS;
1246 }
1247
1248 /**
1249  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1250  *  @hw: pointer to the HW structure
1251  *  @to_sx: boolean indicating a system power state transition to Sx
1252  *
1253  *  When link is down, configure ULP mode to significantly reduce the power
1254  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1255  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1256  *  system, configure the ULP mode by software.
1257  */
1258 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1259 {
1260         u32 mac_reg;
1261         s32 ret_val = E1000_SUCCESS;
1262         u16 phy_reg;
1263         u16 oem_reg = 0;
1264
1265         if ((hw->mac.type < e1000_pch_lpt) ||
1266             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1267             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1268             (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1269             (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1270             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1271                 return 0;
1272
1273         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1274                 /* Request ME configure ULP mode in the PHY */
1275                 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1276                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1277                 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1278
1279                 goto out;
1280         }
1281
1282         if (!to_sx) {
1283                 int i = 0;
1284
1285                 /* Poll up to 5 seconds for Cable Disconnected indication */
1286                 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1287                          E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1288                         /* Bail if link is re-acquired */
1289                         if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1290                                 return -E1000_ERR_PHY;
1291
1292                         if (i++ == 100)
1293                                 break;
1294
1295                         msec_delay(50);
1296                 }
1297                 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1298                          (E1000_READ_REG(hw, E1000_FEXT) &
1299                           E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1300                          i * 50);
1301         }
1302
1303         ret_val = hw->phy.ops.acquire(hw);
1304         if (ret_val)
1305                 goto out;
1306
1307         /* Force SMBus mode in PHY */
1308         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1309         if (ret_val)
1310                 goto release;
1311         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1312         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1313
1314         /* Force SMBus mode in MAC */
1315         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1316         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1317         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1318
1319         /* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable
1320          * LPLU and disable Gig speed when entering ULP
1321          */
1322         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1323                 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1324                                                        &oem_reg);
1325                 if (ret_val)
1326                         goto release;
1327
1328                 phy_reg = oem_reg;
1329                 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1330
1331                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1332                                                         phy_reg);
1333
1334                 if (ret_val)
1335                         goto release;
1336         }
1337
1338         /* Set Inband ULP Exit, Reset to SMBus mode and
1339          * Disable SMBus Release on PERST# in PHY
1340          */
1341         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1342         if (ret_val)
1343                 goto release;
1344         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1345                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1346         if (to_sx) {
1347                 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1348                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1349                 else
1350                         phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1351
1352                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1353                 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1354         } else {
1355                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1356                 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1357                 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1358         }
1359         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1360
1361         /* Set Disable SMBus Release on PERST# in MAC */
1362         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1363         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1364         E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1365
1366         /* Commit ULP changes in PHY by starting auto ULP configuration */
1367         phy_reg |= I218_ULP_CONFIG1_START;
1368         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1369
1370         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1371             to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1372                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1373                                                         oem_reg);
1374                 if (ret_val)
1375                         goto release;
1376         }
1377
1378 release:
1379         hw->phy.ops.release(hw);
1380 out:
1381         if (ret_val)
1382                 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1383         else
1384                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1385
1386         return ret_val;
1387 }
1388
1389 /**
1390  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1391  *  @hw: pointer to the HW structure
1392  *  @force: boolean indicating whether or not to force disabling ULP
1393  *
1394  *  Un-configure ULP mode when link is up, the system is transitioned from
1395  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1396  *  system, poll for an indication from ME that ULP has been un-configured.
1397  *  If not on an ME enabled system, un-configure the ULP mode by software.
1398  *
1399  *  During nominal operation, this function is called when link is acquired
1400  *  to disable ULP mode (force=FALSE); otherwise, for example when unloading
1401  *  the driver or during Sx->S0 transitions, this is called with force=TRUE
1402  *  to forcibly disable ULP.
1403  */
1404 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1405 {
1406         s32 ret_val = E1000_SUCCESS;
1407         u32 mac_reg;
1408         u16 phy_reg;
1409         int i = 0;
1410
1411         if ((hw->mac.type < e1000_pch_lpt) ||
1412             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1413             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1414             (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1415             (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1416             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1417                 return 0;
1418
1419         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1420                 if (force) {
1421                         /* Request ME un-configure ULP mode in the PHY */
1422                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1423                         mac_reg &= ~E1000_H2ME_ULP;
1424                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1425                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1426                 }
1427
1428                 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1429                 while (E1000_READ_REG(hw, E1000_FWSM) &
1430                        E1000_FWSM_ULP_CFG_DONE) {
1431                         if (i++ == 30) {
1432                                 ret_val = -E1000_ERR_PHY;
1433                                 goto out;
1434                         }
1435
1436                         msec_delay(10);
1437                 }
1438                 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1439
1440                 if (force) {
1441                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1442                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1443                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1444                 } else {
1445                         /* Clear H2ME.ULP after ME ULP configuration */
1446                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1447                         mac_reg &= ~E1000_H2ME_ULP;
1448                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1449                 }
1450
1451                 goto out;
1452         }
1453
1454         ret_val = hw->phy.ops.acquire(hw);
1455         if (ret_val)
1456                 goto out;
1457
1458         if (force)
1459                 /* Toggle LANPHYPC Value bit */
1460                 e1000_toggle_lanphypc_pch_lpt(hw);
1461
1462         /* Unforce SMBus mode in PHY */
1463         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1464         if (ret_val) {
1465                 /* The MAC might be in PCIe mode, so temporarily force to
1466                  * SMBus mode in order to access the PHY.
1467                  */
1468                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1469                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1470                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1471
1472                 msec_delay(50);
1473
1474                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1475                                                        &phy_reg);
1476                 if (ret_val)
1477                         goto release;
1478         }
1479         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1480         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1481
1482         /* Unforce SMBus mode in MAC */
1483         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1484         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1485         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1486
1487         /* When ULP mode was previously entered, K1 was disabled by the
1488          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1489          */
1490         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1491         if (ret_val)
1492                 goto release;
1493         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1494         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1495
1496         /* Clear ULP enabled configuration */
1497         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1498         if (ret_val)
1499                 goto release;
1500         phy_reg &= ~(I218_ULP_CONFIG1_IND |
1501                      I218_ULP_CONFIG1_STICKY_ULP |
1502                      I218_ULP_CONFIG1_RESET_TO_SMBUS |
1503                      I218_ULP_CONFIG1_WOL_HOST |
1504                      I218_ULP_CONFIG1_INBAND_EXIT |
1505                      I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1506                      I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1507                      I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1508         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1509
1510         /* Commit ULP changes by starting auto ULP configuration */
1511         phy_reg |= I218_ULP_CONFIG1_START;
1512         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1513
1514         /* Clear Disable SMBus Release on PERST# in MAC */
1515         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1516         mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1517         E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1518
1519 release:
1520         hw->phy.ops.release(hw);
1521         if (force) {
1522                 hw->phy.ops.reset(hw);
1523                 msec_delay(50);
1524         }
1525 out:
1526         if (ret_val)
1527                 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1528         else
1529                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1530
1531         return ret_val;
1532 }
1533
1534 /**
1535  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1536  *  @hw: pointer to the HW structure
1537  *
1538  *  Checks to see of the link status of the hardware has changed.  If a
1539  *  change in link status has been detected, then we read the PHY registers
1540  *  to get the current speed/duplex if link exists.
1541  **/
1542 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1543 {
1544         struct e1000_mac_info *mac = &hw->mac;
1545         s32 ret_val, tipg_reg = 0;
1546         u16 emi_addr, emi_val = 0;
1547         bool link;
1548         u16 phy_reg;
1549
1550         DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1551
1552         /* We only want to go out to the PHY registers to see if Auto-Neg
1553          * has completed and/or if our link status has changed.  The
1554          * get_link_status flag is set upon receiving a Link Status
1555          * Change or Rx Sequence Error interrupt.
1556          */
1557         if (!mac->get_link_status)
1558                 return E1000_SUCCESS;
1559
1560         /* First we want to see if the MII Status Register reports
1561          * link.  If so, then we want to get the current speed/duplex
1562          * of the PHY.
1563          */
1564         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1565         if (ret_val)
1566                 return ret_val;
1567
1568         if (hw->mac.type == e1000_pchlan) {
1569                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1570                 if (ret_val)
1571                         return ret_val;
1572         }
1573
1574         /* When connected at 10Mbps half-duplex, some parts are excessively
1575          * aggressive resulting in many collisions. To avoid this, increase
1576          * the IPG and reduce Rx latency in the PHY.
1577          */
1578         if ((hw->mac.type >= e1000_pch2lan) && link) {
1579                 u16 speed, duplex;
1580
1581                 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1582                 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1583                 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1584
1585                 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1586                         tipg_reg |= 0xFF;
1587                         /* Reduce Rx latency in analog PHY */
1588                         emi_val = 0;
1589                 } else if (hw->mac.type >= e1000_pch_spt &&
1590                            duplex == FULL_DUPLEX && speed != SPEED_1000) {
1591                         tipg_reg |= 0xC;
1592                         emi_val = 1;
1593                 } else {
1594                         /* Roll back the default values */
1595                         tipg_reg |= 0x08;
1596                         emi_val = 1;
1597                 }
1598
1599                 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1600
1601                 ret_val = hw->phy.ops.acquire(hw);
1602                 if (ret_val)
1603                         return ret_val;
1604
1605                 if (hw->mac.type == e1000_pch2lan)
1606                         emi_addr = I82579_RX_CONFIG;
1607                 else
1608                         emi_addr = I217_RX_CONFIG;
1609                 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1610
1611
1612                 if (hw->mac.type >= e1000_pch_lpt) {
1613                         u16 phy_reg;
1614
1615                         hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1616                                                     &phy_reg);
1617                         phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1618                         if (speed == SPEED_100 || speed == SPEED_10)
1619                                 phy_reg |= 0x3E8;
1620                         else
1621                                 phy_reg |= 0xFA;
1622                         hw->phy.ops.write_reg_locked(hw,
1623                                                      I217_PLL_CLOCK_GATE_REG,
1624                                                      phy_reg);
1625
1626                         if (speed == SPEED_1000) {
1627                                 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1628                                                             &phy_reg);
1629
1630                                 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1631
1632                                 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1633                                                              phy_reg);
1634                                 }
1635                  }
1636                 hw->phy.ops.release(hw);
1637
1638                 if (ret_val)
1639                         return ret_val;
1640
1641                 if (hw->mac.type >= e1000_pch_spt) {
1642                         u16 data;
1643                         u16 ptr_gap;
1644
1645                         if (speed == SPEED_1000) {
1646                                 ret_val = hw->phy.ops.acquire(hw);
1647                                 if (ret_val)
1648                                         return ret_val;
1649
1650                                 ret_val = hw->phy.ops.read_reg_locked(hw,
1651                                                               PHY_REG(776, 20),
1652                                                               &data);
1653                                 if (ret_val) {
1654                                         hw->phy.ops.release(hw);
1655                                         return ret_val;
1656                                 }
1657
1658                                 ptr_gap = (data & (0x3FF << 2)) >> 2;
1659                                 if (ptr_gap < 0x18) {
1660                                         data &= ~(0x3FF << 2);
1661                                         data |= (0x18 << 2);
1662                                         ret_val =
1663                                                 hw->phy.ops.write_reg_locked(hw,
1664                                                         PHY_REG(776, 20), data);
1665                                 }
1666                                 hw->phy.ops.release(hw);
1667                                 if (ret_val)
1668                                         return ret_val;
1669                         } else {
1670                                 ret_val = hw->phy.ops.acquire(hw);
1671                                 if (ret_val)
1672                                         return ret_val;
1673
1674                                 ret_val = hw->phy.ops.write_reg_locked(hw,
1675                                                              PHY_REG(776, 20),
1676                                                              0xC023);
1677                                 hw->phy.ops.release(hw);
1678                                 if (ret_val)
1679                                         return ret_val;
1680
1681                         }
1682                 }
1683         }
1684
1685         /* I217 Packet Loss issue:
1686          * ensure that FEXTNVM4 Beacon Duration is set correctly
1687          * on power up.
1688          * Set the Beacon Duration for I217 to 8 usec
1689          */
1690         if (hw->mac.type >= e1000_pch_lpt) {
1691                 u32 mac_reg;
1692
1693                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1694                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1695                 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1696                 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1697         }
1698
1699         /* Work-around I218 hang issue */
1700         if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1701             (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1702             (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1703             (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1704                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1705                 if (ret_val)
1706                         return ret_val;
1707         }
1708         if (hw->mac.type >= e1000_pch_lpt) {
1709                 /* Set platform power management values for
1710                  * Latency Tolerance Reporting (LTR)
1711                  * Optimized Buffer Flush/Fill (OBFF)
1712                  */
1713                 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1714                 if (ret_val)
1715                         return ret_val;
1716         }
1717
1718         /* Clear link partner's EEE ability */
1719         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1720
1721         if (hw->mac.type >= e1000_pch_lpt) {
1722                 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1723
1724                 if (hw->mac.type == e1000_pch_spt) {
1725                         /* FEXTNVM6 K1-off workaround - for SPT only */
1726                         u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
1727
1728                         if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1729                                 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1730                         else
1731                                 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1732                 }
1733
1734                 if (hw->dev_spec.ich8lan.disable_k1_off == TRUE)
1735                         fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1736
1737                 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1738         }
1739
1740         if (!link)
1741                 return E1000_SUCCESS; /* No link detected */
1742
1743         mac->get_link_status = FALSE;
1744
1745         switch (hw->mac.type) {
1746         case e1000_pch2lan:
1747                 ret_val = e1000_k1_workaround_lv(hw);
1748                 if (ret_val)
1749                         return ret_val;
1750                 /* fall-thru */
1751         case e1000_pchlan:
1752                 if (hw->phy.type == e1000_phy_82578) {
1753                         ret_val = e1000_link_stall_workaround_hv(hw);
1754                         if (ret_val)
1755                                 return ret_val;
1756                 }
1757
1758                 /* Workaround for PCHx parts in half-duplex:
1759                  * Set the number of preambles removed from the packet
1760                  * when it is passed from the PHY to the MAC to prevent
1761                  * the MAC from misinterpreting the packet type.
1762                  */
1763                 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1764                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1765
1766                 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1767                     E1000_STATUS_FD)
1768                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1769
1770                 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1771                 break;
1772         default:
1773                 break;
1774         }
1775
1776         /* Check if there was DownShift, must be checked
1777          * immediately after link-up
1778          */
1779         e1000_check_downshift_generic(hw);
1780
1781         /* Enable/Disable EEE after link up */
1782         if (hw->phy.type > e1000_phy_82579) {
1783                 ret_val = e1000_set_eee_pchlan(hw);
1784                 if (ret_val)
1785                         return ret_val;
1786         }
1787
1788         /* If we are forcing speed/duplex, then we simply return since
1789          * we have already determined whether we have link or not.
1790          */
1791         if (!mac->autoneg)
1792                 return -E1000_ERR_CONFIG;
1793
1794         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1795          * of MAC speed/duplex configuration.  So we only need to
1796          * configure Collision Distance in the MAC.
1797          */
1798         mac->ops.config_collision_dist(hw);
1799
1800         /* Configure Flow Control now that Auto-Neg has completed.
1801          * First, we need to restore the desired flow control
1802          * settings because we may have had to re-autoneg with a
1803          * different link partner.
1804          */
1805         ret_val = e1000_config_fc_after_link_up_generic(hw);
1806         if (ret_val)
1807                 DEBUGOUT("Error configuring flow control\n");
1808
1809         return ret_val;
1810 }
1811
1812 /**
1813  *  e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1814  *  @hw: pointer to the HW structure
1815  *
1816  *  Initialize family-specific function pointers for PHY, MAC, and NVM.
1817  **/
1818 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1819 {
1820         DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1821
1822         hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1823         hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1824         switch (hw->mac.type) {
1825         case e1000_ich8lan:
1826         case e1000_ich9lan:
1827         case e1000_ich10lan:
1828                 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1829                 break;
1830         case e1000_pchlan:
1831         case e1000_pch2lan:
1832         case e1000_pch_lpt:
1833         case e1000_pch_spt:
1834         case e1000_pch_cnp:
1835                 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1836                 break;
1837         default:
1838                 break;
1839         }
1840 }
1841
1842 /**
1843  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1844  *  @hw: pointer to the HW structure
1845  *
1846  *  Acquires the mutex for performing NVM operations.
1847  **/
1848 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1849 {
1850         DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1851
1852         ASSERT_CTX_LOCK_HELD(hw);
1853
1854         return E1000_SUCCESS;
1855 }
1856
1857 /**
1858  *  e1000_release_nvm_ich8lan - Release NVM mutex
1859  *  @hw: pointer to the HW structure
1860  *
1861  *  Releases the mutex used while performing NVM operations.
1862  **/
1863 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1864 {
1865         DEBUGFUNC("e1000_release_nvm_ich8lan");
1866
1867         ASSERT_CTX_LOCK_HELD(hw);
1868 }
1869
1870 /**
1871  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1872  *  @hw: pointer to the HW structure
1873  *
1874  *  Acquires the software control flag for performing PHY and select
1875  *  MAC CSR accesses.
1876  **/
1877 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1878 {
1879         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1880         s32 ret_val = E1000_SUCCESS;
1881
1882         DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1883
1884         ASSERT_CTX_LOCK_HELD(hw);
1885
1886         while (timeout) {
1887                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1888                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1889                         break;
1890
1891                 msec_delay_irq(1);
1892                 timeout--;
1893         }
1894
1895         if (!timeout) {
1896                 DEBUGOUT("SW has already locked the resource.\n");
1897                 ret_val = -E1000_ERR_CONFIG;
1898                 goto out;
1899         }
1900
1901         timeout = SW_FLAG_TIMEOUT;
1902
1903         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1904         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1905
1906         while (timeout) {
1907                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1908                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1909                         break;
1910
1911                 msec_delay_irq(1);
1912                 timeout--;
1913         }
1914
1915         if (!timeout) {
1916                 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1917                           E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1918                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1919                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1920                 ret_val = -E1000_ERR_CONFIG;
1921                 goto out;
1922         }
1923
1924 out:
1925         return ret_val;
1926 }
1927
1928 /**
1929  *  e1000_release_swflag_ich8lan - Release software control flag
1930  *  @hw: pointer to the HW structure
1931  *
1932  *  Releases the software control flag for performing PHY and select
1933  *  MAC CSR accesses.
1934  **/
1935 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1936 {
1937         u32 extcnf_ctrl;
1938
1939         DEBUGFUNC("e1000_release_swflag_ich8lan");
1940
1941         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1942
1943         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1944                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1945                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1946         } else {
1947                 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1948         }
1949 }
1950
1951 /**
1952  *  e1000_check_mng_mode_ich8lan - Checks management mode
1953  *  @hw: pointer to the HW structure
1954  *
1955  *  This checks if the adapter has any manageability enabled.
1956  *  This is a function pointer entry point only called by read/write
1957  *  routines for the PHY and NVM parts.
1958  **/
1959 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1960 {
1961         u32 fwsm;
1962
1963         DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1964
1965         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1966
1967         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1968                ((fwsm & E1000_FWSM_MODE_MASK) ==
1969                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1970 }
1971
1972 /**
1973  *  e1000_check_mng_mode_pchlan - Checks management mode
1974  *  @hw: pointer to the HW structure
1975  *
1976  *  This checks if the adapter has iAMT enabled.
1977  *  This is a function pointer entry point only called by read/write
1978  *  routines for the PHY and NVM parts.
1979  **/
1980 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1981 {
1982         u32 fwsm;
1983
1984         DEBUGFUNC("e1000_check_mng_mode_pchlan");
1985
1986         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1987
1988         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1989                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1990 }
1991
1992 /**
1993  *  e1000_rar_set_pch2lan - Set receive address register
1994  *  @hw: pointer to the HW structure
1995  *  @addr: pointer to the receive address
1996  *  @index: receive address array register
1997  *
1998  *  Sets the receive address array register at index to the address passed
1999  *  in by addr.  For 82579, RAR[0] is the base address register that is to
2000  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
2001  *  Use SHRA[0-3] in place of those reserved for ME.
2002  **/
2003 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
2004 {
2005         u32 rar_low, rar_high;
2006
2007         DEBUGFUNC("e1000_rar_set_pch2lan");
2008
2009         /* HW expects these in little endian so we reverse the byte order
2010          * from network order (big endian) to little endian
2011          */
2012         rar_low = ((u32) addr[0] |
2013                    ((u32) addr[1] << 8) |
2014                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
2015
2016         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
2017
2018         /* If MAC address zero, no need to set the AV bit */
2019         if (rar_low || rar_high)
2020                 rar_high |= E1000_RAH_AV;
2021
2022         if (index == 0) {
2023                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2024                 E1000_WRITE_FLUSH(hw);
2025                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2026                 E1000_WRITE_FLUSH(hw);
2027                 return E1000_SUCCESS;
2028         }
2029
2030         /* RAR[1-6] are owned by manageability.  Skip those and program the
2031          * next address into the SHRA register array.
2032          */
2033         if (index < (u32) (hw->mac.rar_entry_count)) {
2034                 s32 ret_val;
2035
2036                 ret_val = e1000_acquire_swflag_ich8lan(hw);
2037                 if (ret_val)
2038                         goto out;
2039
2040                 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
2041                 E1000_WRITE_FLUSH(hw);
2042                 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
2043                 E1000_WRITE_FLUSH(hw);
2044
2045                 e1000_release_swflag_ich8lan(hw);
2046
2047                 /* verify the register updates */
2048                 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
2049                     (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
2050                         return E1000_SUCCESS;
2051
2052                 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
2053                          (index - 1), E1000_READ_REG(hw, E1000_FWSM));
2054         }
2055
2056 out:
2057         DEBUGOUT1("Failed to write receive address at index %d\n", index);
2058         return -E1000_ERR_CONFIG;
2059 }
2060
2061 /**
2062  *  e1000_rar_set_pch_lpt - Set receive address registers
2063  *  @hw: pointer to the HW structure
2064  *  @addr: pointer to the receive address
2065  *  @index: receive address array register
2066  *
2067  *  Sets the receive address register array at index to the address passed
2068  *  in by addr. For LPT, RAR[0] is the base address register that is to
2069  *  contain the MAC address. SHRA[0-10] are the shared receive address
2070  *  registers that are shared between the Host and manageability engine (ME).
2071  **/
2072 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
2073 {
2074         u32 rar_low, rar_high;
2075         u32 wlock_mac;
2076
2077         DEBUGFUNC("e1000_rar_set_pch_lpt");
2078
2079         /* HW expects these in little endian so we reverse the byte order
2080          * from network order (big endian) to little endian
2081          */
2082         rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
2083                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
2084
2085         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
2086
2087         /* If MAC address zero, no need to set the AV bit */
2088         if (rar_low || rar_high)
2089                 rar_high |= E1000_RAH_AV;
2090
2091         if (index == 0) {
2092                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2093                 E1000_WRITE_FLUSH(hw);
2094                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2095                 E1000_WRITE_FLUSH(hw);
2096                 return E1000_SUCCESS;
2097         }
2098
2099         /* The manageability engine (ME) can lock certain SHRAR registers that
2100          * it is using - those registers are unavailable for use.
2101          */
2102         if (index < hw->mac.rar_entry_count) {
2103                 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
2104                             E1000_FWSM_WLOCK_MAC_MASK;
2105                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2106
2107                 /* Check if all SHRAR registers are locked */
2108                 if (wlock_mac == 1)
2109                         goto out;
2110
2111                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2112                         s32 ret_val;
2113
2114                         ret_val = e1000_acquire_swflag_ich8lan(hw);
2115
2116                         if (ret_val)
2117                                 goto out;
2118
2119                         E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
2120                                         rar_low);
2121                         E1000_WRITE_FLUSH(hw);
2122                         E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
2123                                         rar_high);
2124                         E1000_WRITE_FLUSH(hw);
2125
2126                         e1000_release_swflag_ich8lan(hw);
2127
2128                         /* verify the register updates */
2129                         if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2130                             (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
2131                                 return E1000_SUCCESS;
2132                 }
2133         }
2134
2135 out:
2136         DEBUGOUT1("Failed to write receive address at index %d\n", index);
2137         return -E1000_ERR_CONFIG;
2138 }
2139
2140 /**
2141  *  e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
2142  *  @hw: pointer to the HW structure
2143  *  @mc_addr_list: array of multicast addresses to program
2144  *  @mc_addr_count: number of multicast addresses to program
2145  *
2146  *  Updates entire Multicast Table Array of the PCH2 MAC and PHY.
2147  *  The caller must have a packed mc_addr_list of multicast addresses.
2148  **/
2149 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
2150                                               u8 *mc_addr_list,
2151                                               u32 mc_addr_count)
2152 {
2153         u16 phy_reg = 0;
2154         int i;
2155         s32 ret_val;
2156
2157         DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
2158
2159         e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
2160
2161         ret_val = hw->phy.ops.acquire(hw);
2162         if (ret_val)
2163                 return;
2164
2165         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2166         if (ret_val)
2167                 goto release;
2168
2169         for (i = 0; i < hw->mac.mta_reg_count; i++) {
2170                 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
2171                                            (u16)(hw->mac.mta_shadow[i] &
2172                                                  0xFFFF));
2173                 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
2174                                            (u16)((hw->mac.mta_shadow[i] >> 16) &
2175                                                  0xFFFF));
2176         }
2177
2178         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2179
2180 release:
2181         hw->phy.ops.release(hw);
2182 }
2183
2184 /**
2185  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2186  *  @hw: pointer to the HW structure
2187  *
2188  *  Checks if firmware is blocking the reset of the PHY.
2189  *  This is a function pointer entry point only called by
2190  *  reset routines.
2191  **/
2192 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2193 {
2194         u32 fwsm;
2195         bool blocked = FALSE;
2196         int i = 0;
2197
2198         DEBUGFUNC("e1000_check_reset_block_ich8lan");
2199
2200         do {
2201                 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2202                 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2203                         blocked = TRUE;
2204                         msec_delay(10);
2205                         continue;
2206                 }
2207                 blocked = FALSE;
2208         } while (blocked && (i++ < 30));
2209         return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2210 }
2211
2212 /**
2213  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2214  *  @hw: pointer to the HW structure
2215  *
2216  *  Assumes semaphore already acquired.
2217  *
2218  **/
2219 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2220 {
2221         u16 phy_data;
2222         u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2223         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2224                 E1000_STRAP_SMT_FREQ_SHIFT;
2225         s32 ret_val;
2226
2227         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2228
2229         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2230         if (ret_val)
2231                 return ret_val;
2232
2233         phy_data &= ~HV_SMB_ADDR_MASK;
2234         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2235         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2236
2237         if (hw->phy.type == e1000_phy_i217) {
2238                 /* Restore SMBus frequency */
2239                 if (freq--) {
2240                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2241                         phy_data |= (freq & (1 << 0)) <<
2242                                 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2243                         phy_data |= (freq & (1 << 1)) <<
2244                                 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2245                 } else {
2246                         DEBUGOUT("Unsupported SMB frequency in PHY\n");
2247                 }
2248         }
2249
2250         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2251 }
2252
2253 /**
2254  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2255  *  @hw:   pointer to the HW structure
2256  *
2257  *  SW should configure the LCD from the NVM extended configuration region
2258  *  as a workaround for certain parts.
2259  **/
2260 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2261 {
2262         struct e1000_phy_info *phy = &hw->phy;
2263         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2264         s32 ret_val = E1000_SUCCESS;
2265         u16 word_addr, reg_data, reg_addr, phy_page = 0;
2266
2267         DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2268
2269         /* Initialize the PHY from the NVM on ICH platforms.  This
2270          * is needed due to an issue where the NVM configuration is
2271          * not properly autoloaded after power transitions.
2272          * Therefore, after each PHY reset, we will load the
2273          * configuration data out of the NVM manually.
2274          */
2275         switch (hw->mac.type) {
2276         case e1000_ich8lan:
2277                 if (phy->type != e1000_phy_igp_3)
2278                         return ret_val;
2279
2280                 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2281                     (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2282                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2283                         break;
2284                 }
2285                 /* Fall-thru */
2286         case e1000_pchlan:
2287         case e1000_pch2lan:
2288         case e1000_pch_lpt:
2289         case e1000_pch_spt:
2290         case e1000_pch_cnp:
2291                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2292                 break;
2293         default:
2294                 return ret_val;
2295         }
2296
2297         ret_val = hw->phy.ops.acquire(hw);
2298         if (ret_val)
2299                 return ret_val;
2300
2301         data = E1000_READ_REG(hw, E1000_FEXTNVM);
2302         if (!(data & sw_cfg_mask))
2303                 goto release;
2304
2305         /* Make sure HW does not configure LCD from PHY
2306          * extended configuration before SW configuration
2307          */
2308         data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2309         if ((hw->mac.type < e1000_pch2lan) &&
2310             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2311                         goto release;
2312
2313         cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2314         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2315         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2316         if (!cnf_size)
2317                 goto release;
2318
2319         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2320         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2321
2322         if (((hw->mac.type == e1000_pchlan) &&
2323              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2324             (hw->mac.type > e1000_pchlan)) {
2325                 /* HW configures the SMBus address and LEDs when the
2326                  * OEM and LCD Write Enable bits are set in the NVM.
2327                  * When both NVM bits are cleared, SW will configure
2328                  * them instead.
2329                  */
2330                 ret_val = e1000_write_smbus_addr(hw);
2331                 if (ret_val)
2332                         goto release;
2333
2334                 data = E1000_READ_REG(hw, E1000_LEDCTL);
2335                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2336                                                         (u16)data);
2337                 if (ret_val)
2338                         goto release;
2339         }
2340
2341         /* Configure LCD from extended configuration region. */
2342
2343         /* cnf_base_addr is in DWORD */
2344         word_addr = (u16)(cnf_base_addr << 1);
2345
2346         for (i = 0; i < cnf_size; i++) {
2347                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2348                                            &reg_data);
2349                 if (ret_val)
2350                         goto release;
2351
2352                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2353                                            1, &reg_addr);
2354                 if (ret_val)
2355                         goto release;
2356
2357                 /* Save off the PHY page for future writes. */
2358                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2359                         phy_page = reg_data;
2360                         continue;
2361                 }
2362
2363                 reg_addr &= PHY_REG_MASK;
2364                 reg_addr |= phy_page;
2365
2366                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2367                                                     reg_data);
2368                 if (ret_val)
2369                         goto release;
2370         }
2371
2372 release:
2373         hw->phy.ops.release(hw);
2374         return ret_val;
2375 }
2376
2377 /**
2378  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2379  *  @hw:   pointer to the HW structure
2380  *  @link: link up bool flag
2381  *
2382  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2383  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2384  *  If link is down, the function will restore the default K1 setting located
2385  *  in the NVM.
2386  **/
2387 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2388 {
2389         s32 ret_val = E1000_SUCCESS;
2390         u16 status_reg = 0;
2391         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2392
2393         DEBUGFUNC("e1000_k1_gig_workaround_hv");
2394
2395         if (hw->mac.type != e1000_pchlan)
2396                 return E1000_SUCCESS;
2397
2398         /* Wrap the whole flow with the sw flag */
2399         ret_val = hw->phy.ops.acquire(hw);
2400         if (ret_val)
2401                 return ret_val;
2402
2403         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2404         if (link) {
2405                 if (hw->phy.type == e1000_phy_82578) {
2406                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2407                                                               &status_reg);
2408                         if (ret_val)
2409                                 goto release;
2410
2411                         status_reg &= (BM_CS_STATUS_LINK_UP |
2412                                        BM_CS_STATUS_RESOLVED |
2413                                        BM_CS_STATUS_SPEED_MASK);
2414
2415                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2416                                            BM_CS_STATUS_RESOLVED |
2417                                            BM_CS_STATUS_SPEED_1000))
2418                                 k1_enable = FALSE;
2419                 }
2420
2421                 if (hw->phy.type == e1000_phy_82577) {
2422                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2423                                                               &status_reg);
2424                         if (ret_val)
2425                                 goto release;
2426
2427                         status_reg &= (HV_M_STATUS_LINK_UP |
2428                                        HV_M_STATUS_AUTONEG_COMPLETE |
2429                                        HV_M_STATUS_SPEED_MASK);
2430
2431                         if (status_reg == (HV_M_STATUS_LINK_UP |
2432                                            HV_M_STATUS_AUTONEG_COMPLETE |
2433                                            HV_M_STATUS_SPEED_1000))
2434                                 k1_enable = FALSE;
2435                 }
2436
2437                 /* Link stall fix for link up */
2438                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2439                                                        0x0100);
2440                 if (ret_val)
2441                         goto release;
2442
2443         } else {
2444                 /* Link stall fix for link down */
2445                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2446                                                        0x4100);
2447                 if (ret_val)
2448                         goto release;
2449         }
2450
2451         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2452
2453 release:
2454         hw->phy.ops.release(hw);
2455
2456         return ret_val;
2457 }
2458
2459 /**
2460  *  e1000_configure_k1_ich8lan - Configure K1 power state
2461  *  @hw: pointer to the HW structure
2462  *  @enable: K1 state to configure
2463  *
2464  *  Configure the K1 power state based on the provided parameter.
2465  *  Assumes semaphore already acquired.
2466  *
2467  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2468  **/
2469 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2470 {
2471         s32 ret_val;
2472         u32 ctrl_reg = 0;
2473         u32 ctrl_ext = 0;
2474         u32 reg = 0;
2475         u16 kmrn_reg = 0;
2476
2477         DEBUGFUNC("e1000_configure_k1_ich8lan");
2478
2479         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2480                                              &kmrn_reg);
2481         if (ret_val)
2482                 return ret_val;
2483
2484         if (k1_enable)
2485                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2486         else
2487                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2488
2489         ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2490                                               kmrn_reg);
2491         if (ret_val)
2492                 return ret_val;
2493
2494         usec_delay(20);
2495         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2496         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2497
2498         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2499         reg |= E1000_CTRL_FRCSPD;
2500         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2501
2502         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2503         E1000_WRITE_FLUSH(hw);
2504         usec_delay(20);
2505         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2506         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2507         E1000_WRITE_FLUSH(hw);
2508         usec_delay(20);
2509
2510         return E1000_SUCCESS;
2511 }
2512
2513 /**
2514  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2515  *  @hw:       pointer to the HW structure
2516  *  @d0_state: boolean if entering d0 or d3 device state
2517  *
2518  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2519  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2520  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2521  **/
2522 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2523 {
2524         s32 ret_val = 0;
2525         u32 mac_reg;
2526         u16 oem_reg;
2527
2528         DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2529
2530         if (hw->mac.type < e1000_pchlan)
2531                 return ret_val;
2532
2533         ret_val = hw->phy.ops.acquire(hw);
2534         if (ret_val)
2535                 return ret_val;
2536
2537         if (hw->mac.type == e1000_pchlan) {
2538                 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2539                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2540                         goto release;
2541         }
2542
2543         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2544         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2545                 goto release;
2546
2547         mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2548
2549         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2550         if (ret_val)
2551                 goto release;
2552
2553         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2554
2555         if (d0_state) {
2556                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2557                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2558
2559                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2560                         oem_reg |= HV_OEM_BITS_LPLU;
2561         } else {
2562                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2563                     E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2564                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2565
2566                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2567                     E1000_PHY_CTRL_NOND0A_LPLU))
2568                         oem_reg |= HV_OEM_BITS_LPLU;
2569         }
2570
2571         /* Set Restart auto-neg to activate the bits */
2572         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2573             !hw->phy.ops.check_reset_block(hw))
2574                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2575
2576         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2577
2578 release:
2579         hw->phy.ops.release(hw);
2580
2581         return ret_val;
2582 }
2583
2584
2585 /**
2586  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2587  *  @hw:   pointer to the HW structure
2588  **/
2589 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2590 {
2591         s32 ret_val;
2592         u16 data;
2593
2594         DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2595
2596         ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2597         if (ret_val)
2598                 return ret_val;
2599
2600         data |= HV_KMRN_MDIO_SLOW;
2601
2602         ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2603
2604         return ret_val;
2605 }
2606
2607 /**
2608  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2609  *  done after every PHY reset.
2610  **/
2611 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2612 {
2613         s32 ret_val = E1000_SUCCESS;
2614         u16 phy_data;
2615
2616         DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2617
2618         if (hw->mac.type != e1000_pchlan)
2619                 return E1000_SUCCESS;
2620
2621         /* Set MDIO slow mode before any other MDIO access */
2622         if (hw->phy.type == e1000_phy_82577) {
2623                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2624                 if (ret_val)
2625                         return ret_val;
2626         }
2627
2628         if (((hw->phy.type == e1000_phy_82577) &&
2629              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2630             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2631                 /* Disable generation of early preamble */
2632                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2633                 if (ret_val)
2634                         return ret_val;
2635
2636                 /* Preamble tuning for SSC */
2637                 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2638                                                 0xA204);
2639                 if (ret_val)
2640                         return ret_val;
2641         }
2642
2643         if (hw->phy.type == e1000_phy_82578) {
2644                 /* Return registers to default by doing a soft reset then
2645                  * writing 0x3140 to the control register.
2646                  */
2647                 if (hw->phy.revision < 2) {
2648                         e1000_phy_sw_reset_generic(hw);
2649                         ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2650                                                         0x3140);
2651                         if (ret_val)
2652                                 return ret_val;
2653                 }
2654         }
2655
2656         /* Select page 0 */
2657         ret_val = hw->phy.ops.acquire(hw);
2658         if (ret_val)
2659                 return ret_val;
2660
2661         hw->phy.addr = 1;
2662         ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2663         hw->phy.ops.release(hw);
2664         if (ret_val)
2665                 return ret_val;
2666
2667         /* Configure the K1 Si workaround during phy reset assuming there is
2668          * link so that it disables K1 if link is in 1Gbps.
2669          */
2670         ret_val = e1000_k1_gig_workaround_hv(hw, TRUE);
2671         if (ret_val)
2672                 return ret_val;
2673
2674         /* Workaround for link disconnects on a busy hub in half duplex */
2675         ret_val = hw->phy.ops.acquire(hw);
2676         if (ret_val)
2677                 return ret_val;
2678         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2679         if (ret_val)
2680                 goto release;
2681         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2682                                                phy_data & 0x00FF);
2683         if (ret_val)
2684                 goto release;
2685
2686         /* set MSE higher to enable link to stay up when noise is high */
2687         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2688 release:
2689         hw->phy.ops.release(hw);
2690
2691         return ret_val;
2692 }
2693
2694 /**
2695  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2696  *  @hw:   pointer to the HW structure
2697  **/
2698 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2699 {
2700         u32 mac_reg;
2701         u16 i, phy_reg = 0;
2702         s32 ret_val;
2703
2704         DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2705
2706         ret_val = hw->phy.ops.acquire(hw);
2707         if (ret_val)
2708                 return;
2709         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2710         if (ret_val)
2711                 goto release;
2712
2713         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2714         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2715                 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2716                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2717                                            (u16)(mac_reg & 0xFFFF));
2718                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2719                                            (u16)((mac_reg >> 16) & 0xFFFF));
2720
2721                 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2722                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2723                                            (u16)(mac_reg & 0xFFFF));
2724                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2725                                            (u16)((mac_reg & E1000_RAH_AV)
2726                                                  >> 16));
2727         }
2728
2729         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2730
2731 release:
2732         hw->phy.ops.release(hw);
2733 }
2734
2735 static u32 e1000_calc_rx_da_crc(u8 mac[])
2736 {
2737         u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
2738         u32 i, j, mask, crc;
2739
2740         DEBUGFUNC("e1000_calc_rx_da_crc");
2741
2742         crc = 0xffffffff;
2743         for (i = 0; i < 6; i++) {
2744                 crc = crc ^ mac[i];
2745                 for (j = 8; j > 0; j--) {
2746                         mask = (crc & 1) * (-1);
2747                         crc = (crc >> 1) ^ (poly & mask);
2748                 }
2749         }
2750         return ~crc;
2751 }
2752
2753 /**
2754  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2755  *  with 82579 PHY
2756  *  @hw: pointer to the HW structure
2757  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2758  **/
2759 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2760 {
2761         s32 ret_val = E1000_SUCCESS;
2762         u16 phy_reg, data;
2763         u32 mac_reg;
2764         u16 i;
2765
2766         DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2767
2768         if (hw->mac.type < e1000_pch2lan)
2769                 return E1000_SUCCESS;
2770
2771         /* disable Rx path while enabling/disabling workaround */
2772         hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2773         ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2774                                         phy_reg | (1 << 14));
2775         if (ret_val)
2776                 return ret_val;
2777
2778         if (enable) {
2779                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2780                  * SHRAL/H) and initial CRC values to the MAC
2781                  */
2782                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2783                         u8 mac_addr[ETHER_ADDR_LEN] = {0};
2784                         u32 addr_high, addr_low;
2785
2786                         addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2787                         if (!(addr_high & E1000_RAH_AV))
2788                                 continue;
2789                         addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2790                         mac_addr[0] = (addr_low & 0xFF);
2791                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2792                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2793                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2794                         mac_addr[4] = (addr_high & 0xFF);
2795                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2796
2797                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2798                                         e1000_calc_rx_da_crc(mac_addr));
2799                 }
2800
2801                 /* Write Rx addresses to the PHY */
2802                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2803
2804                 /* Enable jumbo frame workaround in the MAC */
2805                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2806                 mac_reg &= ~(1 << 14);
2807                 mac_reg |= (7 << 15);
2808                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2809
2810                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2811                 mac_reg |= E1000_RCTL_SECRC;
2812                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2813
2814                 ret_val = e1000_read_kmrn_reg_generic(hw,
2815                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2816                                                 &data);
2817                 if (ret_val)
2818                         return ret_val;
2819                 ret_val = e1000_write_kmrn_reg_generic(hw,
2820                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2821                                                 data | (1 << 0));
2822                 if (ret_val)
2823                         return ret_val;
2824                 ret_val = e1000_read_kmrn_reg_generic(hw,
2825                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2826                                                 &data);
2827                 if (ret_val)
2828                         return ret_val;
2829                 data &= ~(0xF << 8);
2830                 data |= (0xB << 8);
2831                 ret_val = e1000_write_kmrn_reg_generic(hw,
2832                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2833                                                 data);
2834                 if (ret_val)
2835                         return ret_val;
2836
2837                 /* Enable jumbo frame workaround in the PHY */
2838                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2839                 data &= ~(0x7F << 5);
2840                 data |= (0x37 << 5);
2841                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2842                 if (ret_val)
2843                         return ret_val;
2844                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2845                 data &= ~(1 << 13);
2846                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2847                 if (ret_val)
2848                         return ret_val;
2849                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2850                 data &= ~(0x3FF << 2);
2851                 data |= (E1000_TX_PTR_GAP << 2);
2852                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2853                 if (ret_val)
2854                         return ret_val;
2855                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2856                 if (ret_val)
2857                         return ret_val;
2858                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2859                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2860                                                 (1 << 10));
2861                 if (ret_val)
2862                         return ret_val;
2863         } else {
2864                 /* Write MAC register values back to h/w defaults */
2865                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2866                 mac_reg &= ~(0xF << 14);
2867                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2868
2869                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2870                 mac_reg &= ~E1000_RCTL_SECRC;
2871                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2872
2873                 ret_val = e1000_read_kmrn_reg_generic(hw,
2874                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2875                                                 &data);
2876                 if (ret_val)
2877                         return ret_val;
2878                 ret_val = e1000_write_kmrn_reg_generic(hw,
2879                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2880                                                 data & ~(1 << 0));
2881                 if (ret_val)
2882                         return ret_val;
2883                 ret_val = e1000_read_kmrn_reg_generic(hw,
2884                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2885                                                 &data);
2886                 if (ret_val)
2887                         return ret_val;
2888                 data &= ~(0xF << 8);
2889                 data |= (0xB << 8);
2890                 ret_val = e1000_write_kmrn_reg_generic(hw,
2891                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2892                                                 data);
2893                 if (ret_val)
2894                         return ret_val;
2895
2896                 /* Write PHY register values back to h/w defaults */
2897                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2898                 data &= ~(0x7F << 5);
2899                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2900                 if (ret_val)
2901                         return ret_val;
2902                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2903                 data |= (1 << 13);
2904                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2905                 if (ret_val)
2906                         return ret_val;
2907                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2908                 data &= ~(0x3FF << 2);
2909                 data |= (0x8 << 2);
2910                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2911                 if (ret_val)
2912                         return ret_val;
2913                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2914                 if (ret_val)
2915                         return ret_val;
2916                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2917                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2918                                                 ~(1 << 10));
2919                 if (ret_val)
2920                         return ret_val;
2921         }
2922
2923         /* re-enable Rx path after enabling/disabling workaround */
2924         return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2925                                      ~(1 << 14));
2926 }
2927
2928 /**
2929  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2930  *  done after every PHY reset.
2931  **/
2932 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2933 {
2934         s32 ret_val = E1000_SUCCESS;
2935
2936         DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2937
2938         if (hw->mac.type != e1000_pch2lan)
2939                 return E1000_SUCCESS;
2940
2941         /* Set MDIO slow mode before any other MDIO access */
2942         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2943         if (ret_val)
2944                 return ret_val;
2945
2946         ret_val = hw->phy.ops.acquire(hw);
2947         if (ret_val)
2948                 return ret_val;
2949         /* set MSE higher to enable link to stay up when noise is high */
2950         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2951         if (ret_val)
2952                 goto release;
2953         /* drop link after 5 times MSE threshold was reached */
2954         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2955 release:
2956         hw->phy.ops.release(hw);
2957
2958         return ret_val;
2959 }
2960
2961 /**
2962  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2963  *  @hw:   pointer to the HW structure
2964  *
2965  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2966  *  Disable K1 for 1000 and 100 speeds
2967  **/
2968 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2969 {
2970         s32 ret_val = E1000_SUCCESS;
2971         u16 status_reg = 0;
2972
2973         DEBUGFUNC("e1000_k1_workaround_lv");
2974
2975         if (hw->mac.type != e1000_pch2lan)
2976                 return E1000_SUCCESS;
2977
2978         /* Set K1 beacon duration based on 10Mbs speed */
2979         ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2980         if (ret_val)
2981                 return ret_val;
2982
2983         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2984             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2985                 if (status_reg &
2986                     (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2987                         u16 pm_phy_reg;
2988
2989                         /* LV 1G/100 Packet drop issue wa  */
2990                         ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2991                                                        &pm_phy_reg);
2992                         if (ret_val)
2993                                 return ret_val;
2994                         pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2995                         ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2996                                                         pm_phy_reg);
2997                         if (ret_val)
2998                                 return ret_val;
2999                 } else {
3000                         u32 mac_reg;
3001                         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
3002                         mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
3003                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
3004                         E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
3005                 }
3006         }
3007
3008         return ret_val;
3009 }
3010
3011 /**
3012  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
3013  *  @hw:   pointer to the HW structure
3014  *  @gate: boolean set to TRUE to gate, FALSE to ungate
3015  *
3016  *  Gate/ungate the automatic PHY configuration via hardware; perform
3017  *  the configuration via software instead.
3018  **/
3019 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
3020 {
3021         u32 extcnf_ctrl;
3022
3023         DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
3024
3025         if (hw->mac.type < e1000_pch2lan)
3026                 return;
3027
3028         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
3029
3030         if (gate)
3031                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
3032         else
3033                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
3034
3035         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
3036 }
3037
3038 /**
3039  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
3040  *  @hw: pointer to the HW structure
3041  *
3042  *  Check the appropriate indication the MAC has finished configuring the
3043  *  PHY after a software reset.
3044  **/
3045 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
3046 {
3047         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
3048
3049         DEBUGFUNC("e1000_lan_init_done_ich8lan");
3050
3051         /* Wait for basic configuration completes before proceeding */
3052         do {
3053                 data = E1000_READ_REG(hw, E1000_STATUS);
3054                 data &= E1000_STATUS_LAN_INIT_DONE;
3055                 usec_delay(100);
3056         } while ((!data) && --loop);
3057
3058         /* If basic configuration is incomplete before the above loop
3059          * count reaches 0, loading the configuration from NVM will
3060          * leave the PHY in a bad state possibly resulting in no link.
3061          */
3062         if (loop == 0)
3063                 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
3064
3065         /* Clear the Init Done bit for the next init event */
3066         data = E1000_READ_REG(hw, E1000_STATUS);
3067         data &= ~E1000_STATUS_LAN_INIT_DONE;
3068         E1000_WRITE_REG(hw, E1000_STATUS, data);
3069 }
3070
3071 /**
3072  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
3073  *  @hw: pointer to the HW structure
3074  **/
3075 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
3076 {
3077         s32 ret_val = E1000_SUCCESS;
3078         u16 reg;
3079
3080         DEBUGFUNC("e1000_post_phy_reset_ich8lan");
3081
3082         if (hw->phy.ops.check_reset_block(hw))
3083                 return E1000_SUCCESS;
3084
3085         /* Allow time for h/w to get to quiescent state after reset */
3086         msec_delay(10);
3087
3088         /* Perform any necessary post-reset workarounds */
3089         switch (hw->mac.type) {
3090         case e1000_pchlan:
3091                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
3092                 if (ret_val)
3093                         return ret_val;
3094                 break;
3095         case e1000_pch2lan:
3096                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
3097                 if (ret_val)
3098                         return ret_val;
3099                 break;
3100         default:
3101                 break;
3102         }
3103
3104         /* Clear the host wakeup bit after lcd reset */
3105         if (hw->mac.type >= e1000_pchlan) {
3106                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);
3107                 reg &= ~BM_WUC_HOST_WU_BIT;
3108                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
3109         }
3110
3111         /* Configure the LCD with the extended configuration region in NVM */
3112         ret_val = e1000_sw_lcd_config_ich8lan(hw);
3113         if (ret_val)
3114                 return ret_val;
3115
3116         /* Configure the LCD with the OEM bits in NVM */
3117         ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE);
3118
3119         if (hw->mac.type == e1000_pch2lan) {
3120                 /* Ungate automatic PHY configuration on non-managed 82579 */
3121                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
3122                     E1000_ICH_FWSM_FW_VALID)) {
3123                         msec_delay(10);
3124                         e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
3125                 }
3126
3127                 /* Set EEE LPI Update Timer to 200usec */
3128                 ret_val = hw->phy.ops.acquire(hw);
3129                 if (ret_val)
3130                         return ret_val;
3131                 ret_val = e1000_write_emi_reg_locked(hw,
3132                                                      I82579_LPI_UPDATE_TIMER,
3133                                                      0x1387);
3134                 hw->phy.ops.release(hw);
3135         }
3136
3137         return ret_val;
3138 }
3139
3140 /**
3141  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
3142  *  @hw: pointer to the HW structure
3143  *
3144  *  Resets the PHY
3145  *  This is a function pointer entry point called by drivers
3146  *  or other shared routines.
3147  **/
3148 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
3149 {
3150         s32 ret_val = E1000_SUCCESS;
3151
3152         DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
3153
3154         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
3155         if ((hw->mac.type == e1000_pch2lan) &&
3156             !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3157                 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
3158
3159         ret_val = e1000_phy_hw_reset_generic(hw);
3160         if (ret_val)
3161                 return ret_val;
3162
3163         return e1000_post_phy_reset_ich8lan(hw);
3164 }
3165
3166 /**
3167  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
3168  *  @hw: pointer to the HW structure
3169  *  @active: TRUE to enable LPLU, FALSE to disable
3170  *
3171  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
3172  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
3173  *  the phy speed. This function will manually set the LPLU bit and restart
3174  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
3175  *  since it configures the same bit.
3176  **/
3177 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
3178 {
3179         s32 ret_val;
3180         u16 oem_reg;
3181
3182         DEBUGFUNC("e1000_set_lplu_state_pchlan");
3183         ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3184         if (ret_val)
3185                 return ret_val;
3186
3187         if (active)
3188                 oem_reg |= HV_OEM_BITS_LPLU;
3189         else
3190                 oem_reg &= ~HV_OEM_BITS_LPLU;
3191
3192         if (!hw->phy.ops.check_reset_block(hw))
3193                 oem_reg |= HV_OEM_BITS_RESTART_AN;
3194
3195         return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3196 }
3197
3198 /**
3199  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3200  *  @hw: pointer to the HW structure
3201  *  @active: TRUE to enable LPLU, FALSE to disable
3202  *
3203  *  Sets the LPLU D0 state according to the active flag.  When
3204  *  activating LPLU this function also disables smart speed
3205  *  and vice versa.  LPLU will not be activated unless the
3206  *  device autonegotiation advertisement meets standards of
3207  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3208  *  This is a function pointer entry point only called by
3209  *  PHY setup routines.
3210  **/
3211 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3212 {
3213         struct e1000_phy_info *phy = &hw->phy;
3214         u32 phy_ctrl;
3215         s32 ret_val = E1000_SUCCESS;
3216         u16 data;
3217
3218         DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3219
3220         if (phy->type == e1000_phy_ife)
3221                 return E1000_SUCCESS;
3222
3223         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3224
3225         if (active) {
3226                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3227                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3228
3229                 if (phy->type != e1000_phy_igp_3)
3230                         return E1000_SUCCESS;
3231
3232                 /* Call gig speed drop workaround on LPLU before accessing
3233                  * any PHY registers
3234                  */
3235                 if (hw->mac.type == e1000_ich8lan)
3236                         e1000_gig_downshift_workaround_ich8lan(hw);
3237
3238                 /* When LPLU is enabled, we should disable SmartSpeed */
3239                 ret_val = phy->ops.read_reg(hw,
3240                                             IGP01E1000_PHY_PORT_CONFIG,
3241                                             &data);
3242                 if (ret_val)
3243                         return ret_val;
3244                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3245                 ret_val = phy->ops.write_reg(hw,
3246                                              IGP01E1000_PHY_PORT_CONFIG,
3247                                              data);
3248                 if (ret_val)
3249                         return ret_val;
3250         } else {
3251                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3252                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3253
3254                 if (phy->type != e1000_phy_igp_3)
3255                         return E1000_SUCCESS;
3256
3257                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3258                  * during Dx states where the power conservation is most
3259                  * important.  During driver activity we should enable
3260                  * SmartSpeed, so performance is maintained.
3261                  */
3262                 if (phy->smart_speed == e1000_smart_speed_on) {
3263                         ret_val = phy->ops.read_reg(hw,
3264                                                     IGP01E1000_PHY_PORT_CONFIG,
3265                                                     &data);
3266                         if (ret_val)
3267                                 return ret_val;
3268
3269                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3270                         ret_val = phy->ops.write_reg(hw,
3271                                                      IGP01E1000_PHY_PORT_CONFIG,
3272                                                      data);
3273                         if (ret_val)
3274                                 return ret_val;
3275                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3276                         ret_val = phy->ops.read_reg(hw,
3277                                                     IGP01E1000_PHY_PORT_CONFIG,
3278                                                     &data);
3279                         if (ret_val)
3280                                 return ret_val;
3281
3282                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3283                         ret_val = phy->ops.write_reg(hw,
3284                                                      IGP01E1000_PHY_PORT_CONFIG,
3285                                                      data);
3286                         if (ret_val)
3287                                 return ret_val;
3288                 }
3289         }
3290
3291         return E1000_SUCCESS;
3292 }
3293
3294 /**
3295  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3296  *  @hw: pointer to the HW structure
3297  *  @active: TRUE to enable LPLU, FALSE to disable
3298  *
3299  *  Sets the LPLU D3 state according to the active flag.  When
3300  *  activating LPLU this function also disables smart speed
3301  *  and vice versa.  LPLU will not be activated unless the
3302  *  device autonegotiation advertisement meets standards of
3303  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3304  *  This is a function pointer entry point only called by
3305  *  PHY setup routines.
3306  **/
3307 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3308 {
3309         struct e1000_phy_info *phy = &hw->phy;
3310         u32 phy_ctrl;
3311         s32 ret_val = E1000_SUCCESS;
3312         u16 data;
3313
3314         DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3315
3316         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3317
3318         if (!active) {
3319                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3320                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3321
3322                 if (phy->type != e1000_phy_igp_3)
3323                         return E1000_SUCCESS;
3324
3325                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3326                  * during Dx states where the power conservation is most
3327                  * important.  During driver activity we should enable
3328                  * SmartSpeed, so performance is maintained.
3329                  */
3330                 if (phy->smart_speed == e1000_smart_speed_on) {
3331                         ret_val = phy->ops.read_reg(hw,
3332                                                     IGP01E1000_PHY_PORT_CONFIG,
3333                                                     &data);
3334                         if (ret_val)
3335                                 return ret_val;
3336
3337                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3338                         ret_val = phy->ops.write_reg(hw,
3339                                                      IGP01E1000_PHY_PORT_CONFIG,
3340                                                      data);
3341                         if (ret_val)
3342                                 return ret_val;
3343                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3344                         ret_val = phy->ops.read_reg(hw,
3345                                                     IGP01E1000_PHY_PORT_CONFIG,
3346                                                     &data);
3347                         if (ret_val)
3348                                 return ret_val;
3349
3350                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3351                         ret_val = phy->ops.write_reg(hw,
3352                                                      IGP01E1000_PHY_PORT_CONFIG,
3353                                                      data);
3354                         if (ret_val)
3355                                 return ret_val;
3356                 }
3357         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3358                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3359                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3360                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3361                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3362
3363                 if (phy->type != e1000_phy_igp_3)
3364                         return E1000_SUCCESS;
3365
3366                 /* Call gig speed drop workaround on LPLU before accessing
3367                  * any PHY registers
3368                  */
3369                 if (hw->mac.type == e1000_ich8lan)
3370                         e1000_gig_downshift_workaround_ich8lan(hw);
3371
3372                 /* When LPLU is enabled, we should disable SmartSpeed */
3373                 ret_val = phy->ops.read_reg(hw,
3374                                             IGP01E1000_PHY_PORT_CONFIG,
3375                                             &data);
3376                 if (ret_val)
3377                         return ret_val;
3378
3379                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3380                 ret_val = phy->ops.write_reg(hw,
3381                                              IGP01E1000_PHY_PORT_CONFIG,
3382                                              data);
3383         }
3384
3385         return ret_val;
3386 }
3387
3388 /**
3389  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3390  *  @hw: pointer to the HW structure
3391  *  @bank:  pointer to the variable that returns the active bank
3392  *
3393  *  Reads signature byte from the NVM using the flash access registers.
3394  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3395  **/
3396 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3397 {
3398         u32 eecd;
3399         struct e1000_nvm_info *nvm = &hw->nvm;
3400         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3401         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3402         u32 nvm_dword = 0;
3403         u8 sig_byte = 0;
3404         s32 ret_val;
3405
3406         DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3407
3408         switch (hw->mac.type) {
3409         case e1000_pch_spt:
3410         case e1000_pch_cnp:
3411                 bank1_offset = nvm->flash_bank_size;
3412                 act_offset = E1000_ICH_NVM_SIG_WORD;
3413
3414                 /* set bank to 0 in case flash read fails */
3415                 *bank = 0;
3416
3417                 /* Check bank 0 */
3418                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3419                                                          &nvm_dword);
3420                 if (ret_val)
3421                         return ret_val;
3422                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3423                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3424                     E1000_ICH_NVM_SIG_VALUE) {
3425                         *bank = 0;
3426                         return E1000_SUCCESS;
3427                 }
3428
3429                 /* Check bank 1 */
3430                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3431                                                          bank1_offset,
3432                                                          &nvm_dword);
3433                 if (ret_val)
3434                         return ret_val;
3435                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3436                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3437                     E1000_ICH_NVM_SIG_VALUE) {
3438                         *bank = 1;
3439                         return E1000_SUCCESS;
3440                 }
3441
3442                 DEBUGOUT("ERROR: No valid NVM bank present\n");
3443                 return -E1000_ERR_NVM;
3444         case e1000_ich8lan:
3445         case e1000_ich9lan:
3446                 eecd = E1000_READ_REG(hw, E1000_EECD);
3447                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3448                     E1000_EECD_SEC1VAL_VALID_MASK) {
3449                         if (eecd & E1000_EECD_SEC1VAL)
3450                                 *bank = 1;
3451                         else
3452                                 *bank = 0;
3453
3454                         return E1000_SUCCESS;
3455                 }
3456                 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3457                 /* fall-thru */
3458         default:
3459                 /* set bank to 0 in case flash read fails */
3460                 *bank = 0;
3461
3462                 /* Check bank 0 */
3463                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3464                                                         &sig_byte);
3465                 if (ret_val)
3466                         return ret_val;
3467                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3468                     E1000_ICH_NVM_SIG_VALUE) {
3469                         *bank = 0;
3470                         return E1000_SUCCESS;
3471                 }
3472
3473                 /* Check bank 1 */
3474                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3475                                                         bank1_offset,
3476                                                         &sig_byte);
3477                 if (ret_val)
3478                         return ret_val;
3479                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3480                     E1000_ICH_NVM_SIG_VALUE) {
3481                         *bank = 1;
3482                         return E1000_SUCCESS;
3483                 }
3484
3485                 DEBUGOUT("ERROR: No valid NVM bank present\n");
3486                 return -E1000_ERR_NVM;
3487         }
3488 }
3489
3490 /**
3491  *  e1000_read_nvm_spt - NVM access for SPT
3492  *  @hw: pointer to the HW structure
3493  *  @offset: The offset (in bytes) of the word(s) to read.
3494  *  @words: Size of data to read in words.
3495  *  @data: pointer to the word(s) to read at offset.
3496  *
3497  *  Reads a word(s) from the NVM
3498  **/
3499 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3500                               u16 *data)
3501 {
3502         struct e1000_nvm_info *nvm = &hw->nvm;
3503         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3504         u32 act_offset;
3505         s32 ret_val = E1000_SUCCESS;
3506         u32 bank = 0;
3507         u32 dword = 0;
3508         u16 offset_to_read;
3509         u16 i;
3510
3511         DEBUGFUNC("e1000_read_nvm_spt");
3512
3513         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3514             (words == 0)) {
3515                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3516                 ret_val = -E1000_ERR_NVM;
3517                 goto out;
3518         }
3519
3520         nvm->ops.acquire(hw);
3521
3522         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3523         if (ret_val != E1000_SUCCESS) {
3524                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3525                 bank = 0;
3526         }
3527
3528         act_offset = (bank) ? nvm->flash_bank_size : 0;
3529         act_offset += offset;
3530
3531         ret_val = E1000_SUCCESS;
3532
3533         for (i = 0; i < words; i += 2) {
3534                 if (words - i == 1) {
3535                         if (dev_spec->shadow_ram[offset+i].modified) {
3536                                 data[i] = dev_spec->shadow_ram[offset+i].value;
3537                         } else {
3538                                 offset_to_read = act_offset + i -
3539                                                  ((act_offset + i) % 2);
3540                                 ret_val =
3541                                    e1000_read_flash_dword_ich8lan(hw,
3542                                                                  offset_to_read,
3543                                                                  &dword);
3544                                 if (ret_val)
3545                                         break;
3546                                 if ((act_offset + i) % 2 == 0)
3547                                         data[i] = (u16)(dword & 0xFFFF);
3548                                 else
3549                                         data[i] = (u16)((dword >> 16) & 0xFFFF);
3550                         }
3551                 } else {
3552                         offset_to_read = act_offset + i;
3553                         if (!(dev_spec->shadow_ram[offset+i].modified) ||
3554                             !(dev_spec->shadow_ram[offset+i+1].modified)) {
3555                                 ret_val =
3556                                    e1000_read_flash_dword_ich8lan(hw,
3557                                                                  offset_to_read,
3558                                                                  &dword);
3559                                 if (ret_val)
3560                                         break;
3561                         }
3562                         if (dev_spec->shadow_ram[offset+i].modified)
3563                                 data[i] = dev_spec->shadow_ram[offset+i].value;
3564                         else
3565                                 data[i] = (u16) (dword & 0xFFFF);
3566                         if (dev_spec->shadow_ram[offset+i].modified)
3567                                 data[i+1] =
3568                                    dev_spec->shadow_ram[offset+i+1].value;
3569                         else
3570                                 data[i+1] = (u16) (dword >> 16 & 0xFFFF);
3571                 }
3572         }
3573
3574         nvm->ops.release(hw);
3575
3576 out:
3577         if (ret_val)
3578                 DEBUGOUT1("NVM read error: %d\n", ret_val);
3579
3580         return ret_val;
3581 }
3582
3583 /**
3584  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3585  *  @hw: pointer to the HW structure
3586  *  @offset: The offset (in bytes) of the word(s) to read.
3587  *  @words: Size of data to read in words
3588  *  @data: Pointer to the word(s) to read at offset.
3589  *
3590  *  Reads a word(s) from the NVM using the flash access registers.
3591  **/
3592 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3593                                   u16 *data)
3594 {
3595         struct e1000_nvm_info *nvm = &hw->nvm;
3596         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3597         u32 act_offset;
3598         s32 ret_val = E1000_SUCCESS;
3599         u32 bank = 0;
3600         u16 i, word;
3601
3602         DEBUGFUNC("e1000_read_nvm_ich8lan");
3603
3604         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3605             (words == 0)) {
3606                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3607                 ret_val = -E1000_ERR_NVM;
3608                 goto out;
3609         }
3610
3611         nvm->ops.acquire(hw);
3612
3613         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3614         if (ret_val != E1000_SUCCESS) {
3615                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3616                 bank = 0;
3617         }
3618
3619         act_offset = (bank) ? nvm->flash_bank_size : 0;
3620         act_offset += offset;
3621
3622         ret_val = E1000_SUCCESS;
3623         for (i = 0; i < words; i++) {
3624                 if (dev_spec->shadow_ram[offset+i].modified) {
3625                         data[i] = dev_spec->shadow_ram[offset+i].value;
3626                 } else {
3627                         ret_val = e1000_read_flash_word_ich8lan(hw,
3628                                                                 act_offset + i,
3629                                                                 &word);
3630                         if (ret_val)
3631                                 break;
3632                         data[i] = word;
3633                 }
3634         }
3635
3636         nvm->ops.release(hw);
3637
3638 out:
3639         if (ret_val)
3640                 DEBUGOUT1("NVM read error: %d\n", ret_val);
3641
3642         return ret_val;
3643 }
3644
3645 /**
3646  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3647  *  @hw: pointer to the HW structure
3648  *
3649  *  This function does initial flash setup so that a new read/write/erase cycle
3650  *  can be started.
3651  **/
3652 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3653 {
3654         union ich8_hws_flash_status hsfsts;
3655         s32 ret_val = -E1000_ERR_NVM;
3656
3657         DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3658
3659         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3660
3661         /* Check if the flash descriptor is valid */
3662         if (!hsfsts.hsf_status.fldesvalid) {
3663                 DEBUGOUT("Flash descriptor invalid.  SW Sequencing must be used.\n");
3664                 return -E1000_ERR_NVM;
3665         }
3666
3667         /* Clear FCERR and DAEL in hw status by writing 1 */
3668         hsfsts.hsf_status.flcerr = 1;
3669         hsfsts.hsf_status.dael = 1;
3670         if (hw->mac.type >= e1000_pch_spt)
3671                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3672                                       hsfsts.regval & 0xFFFF);
3673         else
3674                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3675
3676         /* Either we should have a hardware SPI cycle in progress
3677          * bit to check against, in order to start a new cycle or
3678          * FDONE bit should be changed in the hardware so that it
3679          * is 1 after hardware reset, which can then be used as an
3680          * indication whether a cycle is in progress or has been
3681          * completed.
3682          */
3683
3684         if (!hsfsts.hsf_status.flcinprog) {
3685                 /* There is no cycle running at present,
3686                  * so we can start a cycle.
3687                  * Begin by setting Flash Cycle Done.
3688                  */
3689                 hsfsts.hsf_status.flcdone = 1;
3690                 if (hw->mac.type >= e1000_pch_spt)
3691                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3692                                               hsfsts.regval & 0xFFFF);
3693                 else
3694                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3695                                                 hsfsts.regval);
3696                 ret_val = E1000_SUCCESS;
3697         } else {
3698                 s32 i;
3699
3700                 /* Otherwise poll for sometime so the current
3701                  * cycle has a chance to end before giving up.
3702                  */
3703                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3704                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3705                                                               ICH_FLASH_HSFSTS);
3706                         if (!hsfsts.hsf_status.flcinprog) {
3707                                 ret_val = E1000_SUCCESS;
3708                                 break;
3709                         }
3710                         usec_delay(1);
3711                 }
3712                 if (ret_val == E1000_SUCCESS) {
3713                         /* Successful in waiting for previous cycle to timeout,
3714                          * now set the Flash Cycle Done.
3715                          */
3716                         hsfsts.hsf_status.flcdone = 1;
3717                         if (hw->mac.type >= e1000_pch_spt)
3718                                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3719                                                       hsfsts.regval & 0xFFFF);
3720                         else
3721                                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3722                                                         hsfsts.regval);
3723                 } else {
3724                         DEBUGOUT("Flash controller busy, cannot get access\n");
3725                 }
3726         }
3727
3728         return ret_val;
3729 }
3730
3731 /**
3732  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3733  *  @hw: pointer to the HW structure
3734  *  @timeout: maximum time to wait for completion
3735  *
3736  *  This function starts a flash cycle and waits for its completion.
3737  **/
3738 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3739 {
3740         union ich8_hws_flash_ctrl hsflctl;
3741         union ich8_hws_flash_status hsfsts;
3742         u32 i = 0;
3743
3744         DEBUGFUNC("e1000_flash_cycle_ich8lan");
3745
3746         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3747         if (hw->mac.type >= e1000_pch_spt)
3748                 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3749         else
3750                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3751         hsflctl.hsf_ctrl.flcgo = 1;
3752
3753         if (hw->mac.type >= e1000_pch_spt)
3754                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3755                                       hsflctl.regval << 16);
3756         else
3757                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3758
3759         /* wait till FDONE bit is set to 1 */
3760         do {
3761                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3762                 if (hsfsts.hsf_status.flcdone)
3763                         break;
3764                 usec_delay(1);
3765         } while (i++ < timeout);
3766
3767         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3768                 return E1000_SUCCESS;
3769
3770         return -E1000_ERR_NVM;
3771 }
3772
3773 /**
3774  *  e1000_read_flash_dword_ich8lan - Read dword from flash
3775  *  @hw: pointer to the HW structure
3776  *  @offset: offset to data location
3777  *  @data: pointer to the location for storing the data
3778  *
3779  *  Reads the flash dword at offset into data.  Offset is converted
3780  *  to bytes before read.
3781  **/
3782 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3783                                           u32 *data)
3784 {
3785         DEBUGFUNC("e1000_read_flash_dword_ich8lan");
3786
3787         if (!data)
3788                 return -E1000_ERR_NVM;
3789
3790         /* Must convert word offset into bytes. */
3791         offset <<= 1;
3792
3793         return e1000_read_flash_data32_ich8lan(hw, offset, data);
3794 }
3795
3796 /**
3797  *  e1000_read_flash_word_ich8lan - Read word from flash
3798  *  @hw: pointer to the HW structure
3799  *  @offset: offset to data location
3800  *  @data: pointer to the location for storing the data
3801  *
3802  *  Reads the flash word at offset into data.  Offset is converted
3803  *  to bytes before read.
3804  **/
3805 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3806                                          u16 *data)
3807 {
3808         DEBUGFUNC("e1000_read_flash_word_ich8lan");
3809
3810         if (!data)
3811                 return -E1000_ERR_NVM;
3812
3813         /* Must convert offset into bytes. */
3814         offset <<= 1;
3815
3816         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3817 }
3818
3819 /**
3820  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3821  *  @hw: pointer to the HW structure
3822  *  @offset: The offset of the byte to read.
3823  *  @data: Pointer to a byte to store the value read.
3824  *
3825  *  Reads a single byte from the NVM using the flash access registers.
3826  **/
3827 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3828                                          u8 *data)
3829 {
3830         s32 ret_val;
3831         u16 word = 0;
3832
3833         /* In SPT, only 32 bits access is supported,
3834          * so this function should not be called.
3835          */
3836         if (hw->mac.type >= e1000_pch_spt)
3837                 return -E1000_ERR_NVM;
3838         else
3839                 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3840
3841         if (ret_val)
3842                 return ret_val;
3843
3844         *data = (u8)word;
3845
3846         return E1000_SUCCESS;
3847 }
3848
3849 /**
3850  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3851  *  @hw: pointer to the HW structure
3852  *  @offset: The offset (in bytes) of the byte or word to read.
3853  *  @size: Size of data to read, 1=byte 2=word
3854  *  @data: Pointer to the word to store the value read.
3855  *
3856  *  Reads a byte or word from the NVM using the flash access registers.
3857  **/
3858 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3859                                          u8 size, u16 *data)
3860 {
3861         union ich8_hws_flash_status hsfsts;
3862         union ich8_hws_flash_ctrl hsflctl;
3863         u32 flash_linear_addr;
3864         u32 flash_data = 0;
3865         s32 ret_val = -E1000_ERR_NVM;
3866         u8 count = 0;
3867
3868         DEBUGFUNC("e1000_read_flash_data_ich8lan");
3869
3870         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3871                 return -E1000_ERR_NVM;
3872         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3873                              hw->nvm.flash_base_addr);
3874
3875         do {
3876                 usec_delay(1);
3877                 /* Steps */
3878                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3879                 if (ret_val != E1000_SUCCESS)
3880                         break;
3881                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3882
3883                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3884                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3885                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3886                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3887                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3888
3889                 ret_val = e1000_flash_cycle_ich8lan(hw,
3890                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
3891
3892                 /* Check if FCERR is set to 1, if set to 1, clear it
3893                  * and try the whole sequence a few more times, else
3894                  * read in (shift in) the Flash Data0, the order is
3895                  * least significant byte first msb to lsb
3896                  */
3897                 if (ret_val == E1000_SUCCESS) {
3898                         flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3899                         if (size == 1)
3900                                 *data = (u8)(flash_data & 0x000000FF);
3901                         else if (size == 2)
3902                                 *data = (u16)(flash_data & 0x0000FFFF);
3903                         break;
3904                 } else {
3905                         /* If we've gotten here, then things are probably
3906                          * completely hosed, but if the error condition is
3907                          * detected, it won't hurt to give it another try...
3908                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3909                          */
3910                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3911                                                               ICH_FLASH_HSFSTS);
3912                         if (hsfsts.hsf_status.flcerr) {
3913                                 /* Repeat for some time before giving up. */
3914                                 continue;
3915                         } else if (!hsfsts.hsf_status.flcdone) {
3916                                 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3917                                 break;
3918                         }
3919                 }
3920         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3921
3922         return ret_val;
3923 }
3924
3925 /**
3926  *  e1000_read_flash_data32_ich8lan - Read dword from NVM
3927  *  @hw: pointer to the HW structure
3928  *  @offset: The offset (in bytes) of the dword to read.
3929  *  @data: Pointer to the dword to store the value read.
3930  *
3931  *  Reads a byte or word from the NVM using the flash access registers.
3932  **/
3933 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3934                                            u32 *data)
3935 {
3936         union ich8_hws_flash_status hsfsts;
3937         union ich8_hws_flash_ctrl hsflctl;
3938         u32 flash_linear_addr;
3939         s32 ret_val = -E1000_ERR_NVM;
3940         u8 count = 0;
3941
3942         DEBUGFUNC("e1000_read_flash_data_ich8lan");
3943
3944                 if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3945                     hw->mac.type < e1000_pch_spt)
3946                         return -E1000_ERR_NVM;
3947         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3948                              hw->nvm.flash_base_addr);
3949
3950         do {
3951                 usec_delay(1);
3952                 /* Steps */
3953                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3954                 if (ret_val != E1000_SUCCESS)
3955                         break;
3956                 /* In SPT, This register is in Lan memory space, not flash.
3957                  * Therefore, only 32 bit access is supported
3958                  */
3959                 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3960
3961                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3962                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3963                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3964                 /* In SPT, This register is in Lan memory space, not flash.
3965                  * Therefore, only 32 bit access is supported
3966                  */
3967                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3968                                       (u32)hsflctl.regval << 16);
3969                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3970
3971                 ret_val = e1000_flash_cycle_ich8lan(hw,
3972                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
3973
3974                 /* Check if FCERR is set to 1, if set to 1, clear it
3975                  * and try the whole sequence a few more times, else
3976                  * read in (shift in) the Flash Data0, the order is
3977                  * least significant byte first msb to lsb
3978                  */
3979                 if (ret_val == E1000_SUCCESS) {
3980                         *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3981                         break;
3982                 } else {
3983                         /* If we've gotten here, then things are probably
3984                          * completely hosed, but if the error condition is
3985                          * detected, it won't hurt to give it another try...
3986                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3987                          */
3988                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3989                                                               ICH_FLASH_HSFSTS);
3990                         if (hsfsts.hsf_status.flcerr) {
3991                                 /* Repeat for some time before giving up. */
3992                                 continue;
3993                         } else if (!hsfsts.hsf_status.flcdone) {
3994                                 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3995                                 break;
3996                         }
3997                 }
3998         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3999
4000         return ret_val;
4001 }
4002
4003 /**
4004  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
4005  *  @hw: pointer to the HW structure
4006  *  @offset: The offset (in bytes) of the word(s) to write.
4007  *  @words: Size of data to write in words
4008  *  @data: Pointer to the word(s) to write at offset.
4009  *
4010  *  Writes a byte or word to the NVM using the flash access registers.
4011  **/
4012 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
4013                                    u16 *data)
4014 {
4015         struct e1000_nvm_info *nvm = &hw->nvm;
4016         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4017         u16 i;
4018
4019         DEBUGFUNC("e1000_write_nvm_ich8lan");
4020
4021         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
4022             (words == 0)) {
4023                 DEBUGOUT("nvm parameter(s) out of bounds\n");
4024                 return -E1000_ERR_NVM;
4025         }
4026
4027         nvm->ops.acquire(hw);
4028
4029         for (i = 0; i < words; i++) {
4030                 dev_spec->shadow_ram[offset+i].modified = TRUE;
4031                 dev_spec->shadow_ram[offset+i].value = data[i];
4032         }
4033
4034         nvm->ops.release(hw);
4035
4036         return E1000_SUCCESS;
4037 }
4038
4039 /**
4040  *  e1000_update_nvm_checksum_spt - Update the checksum for NVM
4041  *  @hw: pointer to the HW structure
4042  *
4043  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
4044  *  which writes the checksum to the shadow ram.  The changes in the shadow
4045  *  ram are then committed to the EEPROM by processing each bank at a time
4046  *  checking for the modified bit and writing only the pending changes.
4047  *  After a successful commit, the shadow ram is cleared and is ready for
4048  *  future writes.
4049  **/
4050 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
4051 {
4052         struct e1000_nvm_info *nvm = &hw->nvm;
4053         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4054         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4055         s32 ret_val;
4056         u32 dword = 0;
4057
4058         DEBUGFUNC("e1000_update_nvm_checksum_spt");
4059
4060         ret_val = e1000_update_nvm_checksum_generic(hw);
4061         if (ret_val)
4062                 goto out;
4063
4064         if (nvm->type != e1000_nvm_flash_sw)
4065                 goto out;
4066
4067         nvm->ops.acquire(hw);
4068
4069         /* We're writing to the opposite bank so if we're on bank 1,
4070          * write to bank 0 etc.  We also need to erase the segment that
4071          * is going to be written
4072          */
4073         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4074         if (ret_val != E1000_SUCCESS) {
4075                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4076                 bank = 0;
4077         }
4078
4079         if (bank == 0) {
4080                 new_bank_offset = nvm->flash_bank_size;
4081                 old_bank_offset = 0;
4082                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4083                 if (ret_val)
4084                         goto release;
4085         } else {
4086                 old_bank_offset = nvm->flash_bank_size;
4087                 new_bank_offset = 0;
4088                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4089                 if (ret_val)
4090                         goto release;
4091         }
4092         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) {
4093                 /* Determine whether to write the value stored
4094                  * in the other NVM bank or a modified value stored
4095                  * in the shadow RAM
4096                  */
4097                 ret_val = e1000_read_flash_dword_ich8lan(hw,
4098                                                          i + old_bank_offset,
4099                                                          &dword);
4100
4101                 if (dev_spec->shadow_ram[i].modified) {
4102                         dword &= 0xffff0000;
4103                         dword |= (dev_spec->shadow_ram[i].value & 0xffff);
4104                 }
4105                 if (dev_spec->shadow_ram[i + 1].modified) {
4106                         dword &= 0x0000ffff;
4107                         dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
4108                                   << 16);
4109                 }
4110                 if (ret_val)
4111                         break;
4112
4113                 /* If the word is 0x13, then make sure the signature bits
4114                  * (15:14) are 11b until the commit has completed.
4115                  * This will allow us to write 10b which indicates the
4116                  * signature is valid.  We want to do this after the write
4117                  * has completed so that we don't mark the segment valid
4118                  * while the write is still in progress
4119                  */
4120                 if (i == E1000_ICH_NVM_SIG_WORD - 1)
4121                         dword |= E1000_ICH_NVM_SIG_MASK << 16;
4122
4123                 /* Convert offset to bytes. */
4124                 act_offset = (i + new_bank_offset) << 1;
4125
4126                 usec_delay(100);
4127
4128                 /* Write the data to the new bank. Offset in words*/
4129                 act_offset = i + new_bank_offset;
4130                 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4131                                                                 dword);
4132                 if (ret_val)
4133                         break;
4134          }
4135
4136         /* Don't bother writing the segment valid bits if sector
4137          * programming failed.
4138          */
4139         if (ret_val) {
4140                 DEBUGOUT("Flash commit failed.\n");
4141                 goto release;
4142         }
4143
4144         /* Finally validate the new segment by setting bit 15:14
4145          * to 10b in word 0x13 , this can be done without an
4146          * erase as well since these bits are 11 to start with
4147          * and we need to change bit 14 to 0b
4148          */
4149         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4150
4151         /*offset in words but we read dword*/
4152         --act_offset;
4153         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4154
4155         if (ret_val)
4156                 goto release;
4157
4158         dword &= 0xBFFFFFFF;
4159         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4160
4161         if (ret_val)
4162                 goto release;
4163
4164         /* offset in words but we read dword*/
4165         act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
4166         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4167
4168         if (ret_val)
4169                 goto release;
4170
4171         dword &= 0x00FFFFFF;
4172         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4173
4174         if (ret_val)
4175                 goto release;
4176
4177         /* Great!  Everything worked, we can now clear the cached entries. */
4178         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4179                 dev_spec->shadow_ram[i].modified = FALSE;
4180                 dev_spec->shadow_ram[i].value = 0xFFFF;
4181         }
4182
4183 release:
4184         nvm->ops.release(hw);
4185
4186         /* Reload the EEPROM, or else modifications will not appear
4187          * until after the next adapter reset.
4188          */
4189         if (!ret_val) {
4190                 nvm->ops.reload(hw);
4191                 msec_delay(10);
4192         }
4193
4194 out:
4195         if (ret_val)
4196                 DEBUGOUT1("NVM update error: %d\n", ret_val);
4197
4198         return ret_val;
4199 }
4200
4201 /**
4202  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
4203  *  @hw: pointer to the HW structure
4204  *
4205  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
4206  *  which writes the checksum to the shadow ram.  The changes in the shadow
4207  *  ram are then committed to the EEPROM by processing each bank at a time
4208  *  checking for the modified bit and writing only the pending changes.
4209  *  After a successful commit, the shadow ram is cleared and is ready for
4210  *  future writes.
4211  **/
4212 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
4213 {
4214         struct e1000_nvm_info *nvm = &hw->nvm;
4215         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4216         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4217         s32 ret_val;
4218         u16 data = 0;
4219
4220         DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
4221
4222         ret_val = e1000_update_nvm_checksum_generic(hw);
4223         if (ret_val)
4224                 goto out;
4225
4226         if (nvm->type != e1000_nvm_flash_sw)
4227                 goto out;
4228
4229         nvm->ops.acquire(hw);
4230
4231         /* We're writing to the opposite bank so if we're on bank 1,
4232          * write to bank 0 etc.  We also need to erase the segment that
4233          * is going to be written
4234          */
4235         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4236         if (ret_val != E1000_SUCCESS) {
4237                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4238                 bank = 0;
4239         }
4240
4241         if (bank == 0) {
4242                 new_bank_offset = nvm->flash_bank_size;
4243                 old_bank_offset = 0;
4244                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4245                 if (ret_val)
4246                         goto release;
4247         } else {
4248                 old_bank_offset = nvm->flash_bank_size;
4249                 new_bank_offset = 0;
4250                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4251                 if (ret_val)
4252                         goto release;
4253         }
4254         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4255                 if (dev_spec->shadow_ram[i].modified) {
4256                         data = dev_spec->shadow_ram[i].value;
4257                 } else {
4258                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
4259                                                                 old_bank_offset,
4260                                                                 &data);
4261                         if (ret_val)
4262                                 break;
4263                 }
4264                 /* If the word is 0x13, then make sure the signature bits
4265                  * (15:14) are 11b until the commit has completed.
4266                  * This will allow us to write 10b which indicates the
4267                  * signature is valid.  We want to do this after the write
4268                  * has completed so that we don't mark the segment valid
4269                  * while the write is still in progress
4270                  */
4271                 if (i == E1000_ICH_NVM_SIG_WORD)
4272                         data |= E1000_ICH_NVM_SIG_MASK;
4273
4274                 /* Convert offset to bytes. */
4275                 act_offset = (i + new_bank_offset) << 1;
4276
4277                 usec_delay(100);
4278
4279                 /* Write the bytes to the new bank. */
4280                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4281                                                                act_offset,
4282                                                                (u8)data);
4283                 if (ret_val)
4284                         break;
4285
4286                 usec_delay(100);
4287                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4288                                                           act_offset + 1,
4289                                                           (u8)(data >> 8));
4290                 if (ret_val)
4291                         break;
4292          }
4293
4294         /* Don't bother writing the segment valid bits if sector
4295          * programming failed.
4296          */
4297         if (ret_val) {
4298                 DEBUGOUT("Flash commit failed.\n");
4299                 goto release;
4300         }
4301
4302         /* Finally validate the new segment by setting bit 15:14
4303          * to 10b in word 0x13 , this can be done without an
4304          * erase as well since these bits are 11 to start with
4305          * and we need to change bit 14 to 0b
4306          */
4307         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4308         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4309         if (ret_val)
4310                 goto release;
4311
4312         data &= 0xBFFF;
4313         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
4314                                                        (u8)(data >> 8));
4315         if (ret_val)
4316                 goto release;
4317
4318         /* And invalidate the previously valid segment by setting
4319          * its signature word (0x13) high_byte to 0b. This can be
4320          * done without an erase because flash erase sets all bits
4321          * to 1's. We can write 1's to 0's without an erase
4322          */
4323         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4324
4325         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4326
4327         if (ret_val)
4328                 goto release;
4329
4330         /* Great!  Everything worked, we can now clear the cached entries. */
4331         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4332                 dev_spec->shadow_ram[i].modified = FALSE;
4333                 dev_spec->shadow_ram[i].value = 0xFFFF;
4334         }
4335
4336 release:
4337         nvm->ops.release(hw);
4338
4339         /* Reload the EEPROM, or else modifications will not appear
4340          * until after the next adapter reset.
4341          */
4342         if (!ret_val) {
4343                 nvm->ops.reload(hw);
4344                 msec_delay(10);
4345         }
4346
4347 out:
4348         if (ret_val)
4349                 DEBUGOUT1("NVM update error: %d\n", ret_val);
4350
4351         return ret_val;
4352 }
4353
4354 /**
4355  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4356  *  @hw: pointer to the HW structure
4357  *
4358  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4359  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
4360  *  calculated, in which case we need to calculate the checksum and set bit 6.
4361  **/
4362 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4363 {
4364         s32 ret_val;
4365         u16 data;
4366         u16 word;
4367         u16 valid_csum_mask;
4368
4369         DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
4370
4371         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
4372          * the checksum needs to be fixed.  This bit is an indication that
4373          * the NVM was prepared by OEM software and did not calculate
4374          * the checksum...a likely scenario.
4375          */
4376         switch (hw->mac.type) {
4377         case e1000_pch_lpt:
4378         case e1000_pch_spt:
4379         case e1000_pch_cnp:
4380                 word = NVM_COMPAT;
4381                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4382                 break;
4383         default:
4384                 word = NVM_FUTURE_INIT_WORD1;
4385                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4386                 break;
4387         }
4388
4389         ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4390         if (ret_val)
4391                 return ret_val;
4392
4393         if (!(data & valid_csum_mask)) {
4394                 data |= valid_csum_mask;
4395                 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4396                 if (ret_val)
4397                         return ret_val;
4398                 ret_val = hw->nvm.ops.update(hw);
4399                 if (ret_val)
4400                         return ret_val;
4401         }
4402
4403         return e1000_validate_nvm_checksum_generic(hw);
4404 }
4405
4406 /**
4407  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4408  *  @hw: pointer to the HW structure
4409  *  @offset: The offset (in bytes) of the byte/word to read.
4410  *  @size: Size of data to read, 1=byte 2=word
4411  *  @data: The byte(s) to write to the NVM.
4412  *
4413  *  Writes one/two bytes to the NVM using the flash access registers.
4414  **/
4415 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4416                                           u8 size, u16 data)
4417 {
4418         union ich8_hws_flash_status hsfsts;
4419         union ich8_hws_flash_ctrl hsflctl;
4420         u32 flash_linear_addr;
4421         u32 flash_data = 0;
4422         s32 ret_val;
4423         u8 count = 0;
4424
4425         DEBUGFUNC("e1000_write_ich8_data");
4426
4427         if (hw->mac.type >= e1000_pch_spt) {
4428                 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4429                         return -E1000_ERR_NVM;
4430         } else {
4431                 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4432                         return -E1000_ERR_NVM;
4433         }
4434
4435         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4436                              hw->nvm.flash_base_addr);
4437
4438         do {
4439                 usec_delay(1);
4440                 /* Steps */
4441                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4442                 if (ret_val != E1000_SUCCESS)
4443                         break;
4444                 /* In SPT, This register is in Lan memory space, not
4445                  * flash.  Therefore, only 32 bit access is supported
4446                  */
4447                 if (hw->mac.type >= e1000_pch_spt)
4448                         hsflctl.regval =
4449                             E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
4450                 else
4451                         hsflctl.regval =
4452                             E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4453
4454                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4455                 hsflctl.hsf_ctrl.fldbcount = size - 1;
4456                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4457                 /* In SPT, This register is in Lan memory space,
4458                  * not flash.  Therefore, only 32 bit access is
4459                  * supported
4460                  */
4461                 if (hw->mac.type >= e1000_pch_spt)
4462                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4463                                               hsflctl.regval << 16);
4464                 else
4465                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4466                                                 hsflctl.regval);
4467
4468                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4469
4470                 if (size == 1)
4471                         flash_data = (u32)data & 0x00FF;
4472                 else
4473                         flash_data = (u32)data;
4474
4475                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
4476
4477                 /* check if FCERR is set to 1 , if set to 1, clear it
4478                  * and try the whole sequence a few more times else done
4479                  */
4480                 ret_val =
4481                     e1000_flash_cycle_ich8lan(hw,
4482                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4483                 if (ret_val == E1000_SUCCESS)
4484                         break;
4485
4486                 /* If we're here, then things are most likely
4487                  * completely hosed, but if the error condition
4488                  * is detected, it won't hurt to give it another
4489                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4490                  */
4491                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4492                 if (hsfsts.hsf_status.flcerr)
4493                         /* Repeat for some time before giving up. */
4494                         continue;
4495                 if (!hsfsts.hsf_status.flcdone) {
4496                         DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4497                         break;
4498                 }
4499         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4500
4501         return ret_val;
4502 }
4503
4504 /**
4505 *  e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4506 *  @hw: pointer to the HW structure
4507 *  @offset: The offset (in bytes) of the dwords to read.
4508 *  @data: The 4 bytes to write to the NVM.
4509 *
4510 *  Writes one/two/four bytes to the NVM using the flash access registers.
4511 **/
4512 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4513                                             u32 data)
4514 {
4515         union ich8_hws_flash_status hsfsts;
4516         union ich8_hws_flash_ctrl hsflctl;
4517         u32 flash_linear_addr;
4518         s32 ret_val;
4519         u8 count = 0;
4520
4521         DEBUGFUNC("e1000_write_flash_data32_ich8lan");
4522
4523         if (hw->mac.type >= e1000_pch_spt) {
4524                 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4525                         return -E1000_ERR_NVM;
4526         }
4527         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4528                              hw->nvm.flash_base_addr);
4529         do {
4530                 usec_delay(1);
4531                 /* Steps */
4532                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4533                 if (ret_val != E1000_SUCCESS)
4534                         break;
4535
4536                 /* In SPT, This register is in Lan memory space, not
4537                  * flash.  Therefore, only 32 bit access is supported
4538                  */
4539                 if (hw->mac.type >= e1000_pch_spt)
4540                         hsflctl.regval = E1000_READ_FLASH_REG(hw,
4541                                                               ICH_FLASH_HSFSTS)
4542                                          >> 16;
4543                 else
4544                         hsflctl.regval = E1000_READ_FLASH_REG16(hw,
4545                                                               ICH_FLASH_HSFCTL);
4546
4547                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4548                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4549
4550                 /* In SPT, This register is in Lan memory space,
4551                  * not flash.  Therefore, only 32 bit access is
4552                  * supported
4553                  */
4554                 if (hw->mac.type >= e1000_pch_spt)
4555                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4556                                               hsflctl.regval << 16);
4557                 else
4558                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4559                                                 hsflctl.regval);
4560
4561                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4562
4563                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);
4564
4565                 /* check if FCERR is set to 1 , if set to 1, clear it
4566                  * and try the whole sequence a few more times else done
4567                  */
4568                 ret_val = e1000_flash_cycle_ich8lan(hw,
4569                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4570
4571                 if (ret_val == E1000_SUCCESS)
4572                         break;
4573
4574                 /* If we're here, then things are most likely
4575                  * completely hosed, but if the error condition
4576                  * is detected, it won't hurt to give it another
4577                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4578                  */
4579                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4580
4581                 if (hsfsts.hsf_status.flcerr)
4582                         /* Repeat for some time before giving up. */
4583                         continue;
4584                 if (!hsfsts.hsf_status.flcdone) {
4585                         DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4586                         break;
4587                 }
4588         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4589
4590         return ret_val;
4591 }
4592
4593 /**
4594  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4595  *  @hw: pointer to the HW structure
4596  *  @offset: The index of the byte to read.
4597  *  @data: The byte to write to the NVM.
4598  *
4599  *  Writes a single byte to the NVM using the flash access registers.
4600  **/
4601 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4602                                           u8 data)
4603 {
4604         u16 word = (u16)data;
4605
4606         DEBUGFUNC("e1000_write_flash_byte_ich8lan");
4607
4608         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4609 }
4610
4611 /**
4612 *  e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4613 *  @hw: pointer to the HW structure
4614 *  @offset: The offset of the word to write.
4615 *  @dword: The dword to write to the NVM.
4616 *
4617 *  Writes a single dword to the NVM using the flash access registers.
4618 *  Goes through a retry algorithm before giving up.
4619 **/
4620 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4621                                                  u32 offset, u32 dword)
4622 {
4623         s32 ret_val;
4624         u16 program_retries;
4625
4626         DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan");
4627
4628         /* Must convert word offset into bytes. */
4629         offset <<= 1;
4630
4631         ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4632
4633         if (!ret_val)
4634                 return ret_val;
4635         for (program_retries = 0; program_retries < 100; program_retries++) {
4636                 DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset);
4637                 usec_delay(100);
4638                 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4639                 if (ret_val == E1000_SUCCESS)
4640                         break;
4641         }
4642         if (program_retries == 100)
4643                 return -E1000_ERR_NVM;
4644
4645         return E1000_SUCCESS;
4646 }
4647
4648 /**
4649  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4650  *  @hw: pointer to the HW structure
4651  *  @offset: The offset of the byte to write.
4652  *  @byte: The byte to write to the NVM.
4653  *
4654  *  Writes a single byte to the NVM using the flash access registers.
4655  *  Goes through a retry algorithm before giving up.
4656  **/
4657 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4658                                                 u32 offset, u8 byte)
4659 {
4660         s32 ret_val;
4661         u16 program_retries;
4662
4663         DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
4664
4665         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4666         if (!ret_val)
4667                 return ret_val;
4668
4669         for (program_retries = 0; program_retries < 100; program_retries++) {
4670                 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
4671                 usec_delay(100);
4672                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4673                 if (ret_val == E1000_SUCCESS)
4674                         break;
4675         }
4676         if (program_retries == 100)
4677                 return -E1000_ERR_NVM;
4678
4679         return E1000_SUCCESS;
4680 }
4681
4682 /**
4683  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4684  *  @hw: pointer to the HW structure
4685  *  @bank: 0 for first bank, 1 for second bank, etc.
4686  *
4687  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4688  *  bank N is 4096 * N + flash_reg_addr.
4689  **/
4690 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4691 {
4692         struct e1000_nvm_info *nvm = &hw->nvm;
4693         union ich8_hws_flash_status hsfsts;
4694         union ich8_hws_flash_ctrl hsflctl;
4695         u32 flash_linear_addr;
4696         /* bank size is in 16bit words - adjust to bytes */
4697         u32 flash_bank_size = nvm->flash_bank_size * 2;
4698         s32 ret_val;
4699         s32 count = 0;
4700         s32 j, iteration, sector_size;
4701
4702         DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
4703
4704         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4705
4706         /* Determine HW Sector size: Read BERASE bits of hw flash status
4707          * register
4708          * 00: The Hw sector is 256 bytes, hence we need to erase 16
4709          *     consecutive sectors.  The start index for the nth Hw sector
4710          *     can be calculated as = bank * 4096 + n * 256
4711          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4712          *     The start index for the nth Hw sector can be calculated
4713          *     as = bank * 4096
4714          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4715          *     (ich9 only, otherwise error condition)
4716          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4717          */
4718         switch (hsfsts.hsf_status.berasesz) {
4719         case 0:
4720                 /* Hw sector size 256 */
4721                 sector_size = ICH_FLASH_SEG_SIZE_256;
4722                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4723                 break;
4724         case 1:
4725                 sector_size = ICH_FLASH_SEG_SIZE_4K;
4726                 iteration = 1;
4727                 break;
4728         case 2:
4729                 sector_size = ICH_FLASH_SEG_SIZE_8K;
4730                 iteration = 1;
4731                 break;
4732         case 3:
4733                 sector_size = ICH_FLASH_SEG_SIZE_64K;
4734                 iteration = 1;
4735                 break;
4736         default:
4737                 return -E1000_ERR_NVM;
4738         }
4739
4740         /* Start with the base address, then add the sector offset. */
4741         flash_linear_addr = hw->nvm.flash_base_addr;
4742         flash_linear_addr += (bank) ? flash_bank_size : 0;
4743
4744         for (j = 0; j < iteration; j++) {
4745                 do {
4746                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4747
4748                         /* Steps */
4749                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
4750                         if (ret_val)
4751                                 return ret_val;
4752
4753                         /* Write a value 11 (block Erase) in Flash
4754                          * Cycle field in hw flash control
4755                          */
4756                         if (hw->mac.type >= e1000_pch_spt)
4757                                 hsflctl.regval =
4758                                     E1000_READ_FLASH_REG(hw,
4759                                                          ICH_FLASH_HSFSTS)>>16;
4760                         else
4761                                 hsflctl.regval =
4762                                     E1000_READ_FLASH_REG16(hw,
4763                                                            ICH_FLASH_HSFCTL);
4764
4765                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4766                         if (hw->mac.type >= e1000_pch_spt)
4767                                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4768                                                       hsflctl.regval << 16);
4769                         else
4770                                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4771                                                         hsflctl.regval);
4772
4773                         /* Write the last 24 bits of an index within the
4774                          * block into Flash Linear address field in Flash
4775                          * Address.
4776                          */
4777                         flash_linear_addr += (j * sector_size);
4778                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4779                                               flash_linear_addr);
4780
4781                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4782                         if (ret_val == E1000_SUCCESS)
4783                                 break;
4784
4785                         /* Check if FCERR is set to 1.  If 1,
4786                          * clear it and try the whole sequence
4787                          * a few more times else Done
4788                          */
4789                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4790                                                       ICH_FLASH_HSFSTS);
4791                         if (hsfsts.hsf_status.flcerr)
4792                                 /* repeat for some time before giving up */
4793                                 continue;
4794                         else if (!hsfsts.hsf_status.flcdone)
4795                                 return ret_val;
4796                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4797         }
4798
4799         return E1000_SUCCESS;
4800 }
4801
4802 /**
4803  *  e1000_valid_led_default_ich8lan - Set the default LED settings
4804  *  @hw: pointer to the HW structure
4805  *  @data: Pointer to the LED settings
4806  *
4807  *  Reads the LED default settings from the NVM to data.  If the NVM LED
4808  *  settings is all 0's or F's, set the LED default to a valid LED default
4809  *  setting.
4810  **/
4811 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4812 {
4813         s32 ret_val;
4814
4815         DEBUGFUNC("e1000_valid_led_default_ich8lan");
4816
4817         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4818         if (ret_val) {
4819                 DEBUGOUT("NVM Read Error\n");
4820                 return ret_val;
4821         }
4822
4823         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4824                 *data = ID_LED_DEFAULT_ICH8LAN;
4825
4826         return E1000_SUCCESS;
4827 }
4828
4829 /**
4830  *  e1000_id_led_init_pchlan - store LED configurations
4831  *  @hw: pointer to the HW structure
4832  *
4833  *  PCH does not control LEDs via the LEDCTL register, rather it uses
4834  *  the PHY LED configuration register.
4835  *
4836  *  PCH also does not have an "always on" or "always off" mode which
4837  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4838  *  in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4839  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4840  *  link based on logic in e1000_led_[on|off]_pchlan().
4841  **/
4842 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4843 {
4844         struct e1000_mac_info *mac = &hw->mac;
4845         s32 ret_val;
4846         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4847         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4848         u16 data, i, temp, shift;
4849
4850         DEBUGFUNC("e1000_id_led_init_pchlan");
4851
4852         /* Get default ID LED modes */
4853         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4854         if (ret_val)
4855                 return ret_val;
4856
4857         mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4858         mac->ledctl_mode1 = mac->ledctl_default;
4859         mac->ledctl_mode2 = mac->ledctl_default;
4860
4861         for (i = 0; i < 4; i++) {
4862                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4863                 shift = (i * 5);
4864                 switch (temp) {
4865                 case ID_LED_ON1_DEF2:
4866                 case ID_LED_ON1_ON2:
4867                 case ID_LED_ON1_OFF2:
4868                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4869                         mac->ledctl_mode1 |= (ledctl_on << shift);
4870                         break;
4871                 case ID_LED_OFF1_DEF2:
4872                 case ID_LED_OFF1_ON2:
4873                 case ID_LED_OFF1_OFF2:
4874                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4875                         mac->ledctl_mode1 |= (ledctl_off << shift);
4876                         break;
4877                 default:
4878                         /* Do nothing */
4879                         break;
4880                 }
4881                 switch (temp) {
4882                 case ID_LED_DEF1_ON2:
4883                 case ID_LED_ON1_ON2:
4884                 case ID_LED_OFF1_ON2:
4885                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4886                         mac->ledctl_mode2 |= (ledctl_on << shift);
4887                         break;
4888                 case ID_LED_DEF1_OFF2:
4889                 case ID_LED_ON1_OFF2:
4890                 case ID_LED_OFF1_OFF2:
4891                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4892                         mac->ledctl_mode2 |= (ledctl_off << shift);
4893                         break;
4894                 default:
4895                         /* Do nothing */
4896                         break;
4897                 }
4898         }
4899
4900         return E1000_SUCCESS;
4901 }
4902
4903 /**
4904  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4905  *  @hw: pointer to the HW structure
4906  *
4907  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4908  *  register, so the bus width is hard coded.
4909  **/
4910 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4911 {
4912         struct e1000_bus_info *bus = &hw->bus;
4913         s32 ret_val;
4914
4915         DEBUGFUNC("e1000_get_bus_info_ich8lan");
4916
4917         ret_val = e1000_get_bus_info_pcie_generic(hw);
4918
4919         /* ICH devices are "PCI Express"-ish.  They have
4920          * a configuration space, but do not contain
4921          * PCI Express Capability registers, so bus width
4922          * must be hardcoded.
4923          */
4924         if (bus->width == e1000_bus_width_unknown)
4925                 bus->width = e1000_bus_width_pcie_x1;
4926
4927         return ret_val;
4928 }
4929
4930 /**
4931  *  e1000_reset_hw_ich8lan - Reset the hardware
4932  *  @hw: pointer to the HW structure
4933  *
4934  *  Does a full reset of the hardware which includes a reset of the PHY and
4935  *  MAC.
4936  **/
4937 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4938 {
4939         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4940         u16 kum_cfg;
4941         u32 ctrl, reg;
4942         s32 ret_val;
4943
4944         DEBUGFUNC("e1000_reset_hw_ich8lan");
4945
4946         /* Prevent the PCI-E bus from sticking if there is no TLP connection
4947          * on the last TLP read/write transaction when MAC is reset.
4948          */
4949         ret_val = e1000_disable_pcie_master_generic(hw);
4950         if (ret_val)
4951                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4952
4953         DEBUGOUT("Masking off all interrupts\n");
4954         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4955
4956         /* Disable the Transmit and Receive units.  Then delay to allow
4957          * any pending transactions to complete before we hit the MAC
4958          * with the global reset.
4959          */
4960         E1000_WRITE_REG(hw, E1000_RCTL, 0);
4961         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4962         E1000_WRITE_FLUSH(hw);
4963
4964         msec_delay(10);
4965
4966         /* Workaround for ICH8 bit corruption issue in FIFO memory */
4967         if (hw->mac.type == e1000_ich8lan) {
4968                 /* Set Tx and Rx buffer allocation to 8k apiece. */
4969                 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4970                 /* Set Packet Buffer Size to 16k. */
4971                 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4972         }
4973
4974         if (hw->mac.type == e1000_pchlan) {
4975                 /* Save the NVM K1 bit setting*/
4976                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4977                 if (ret_val)
4978                         return ret_val;
4979
4980                 if (kum_cfg & E1000_NVM_K1_ENABLE)
4981                         dev_spec->nvm_k1_enabled = TRUE;
4982                 else
4983                         dev_spec->nvm_k1_enabled = FALSE;
4984         }
4985
4986         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4987
4988         if (!hw->phy.ops.check_reset_block(hw)) {
4989                 /* Full-chip reset requires MAC and PHY reset at the same
4990                  * time to make sure the interface between MAC and the
4991                  * external PHY is reset.
4992                  */
4993                 ctrl |= E1000_CTRL_PHY_RST;
4994
4995                 /* Gate automatic PHY configuration by hardware on
4996                  * non-managed 82579
4997                  */
4998                 if ((hw->mac.type == e1000_pch2lan) &&
4999                     !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
5000                         e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
5001         }
5002         ret_val = e1000_acquire_swflag_ich8lan(hw);
5003         DEBUGOUT("Issuing a global reset to ich8lan\n");
5004         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
5005         /* cannot issue a flush here because it hangs the hardware */
5006         msec_delay(20);
5007
5008         /* Set Phy Config Counter to 50msec */
5009         if (hw->mac.type == e1000_pch2lan) {
5010                 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
5011                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
5012                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
5013                 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
5014         }
5015
5016
5017         if (ctrl & E1000_CTRL_PHY_RST) {
5018                 ret_val = hw->phy.ops.get_cfg_done(hw);
5019                 if (ret_val)
5020                         return ret_val;
5021
5022                 ret_val = e1000_post_phy_reset_ich8lan(hw);
5023                 if (ret_val)
5024                         return ret_val;
5025         }
5026
5027         /* For PCH, this write will make sure that any noise
5028          * will be detected as a CRC error and be dropped rather than show up
5029          * as a bad packet to the DMA engine.
5030          */
5031         if (hw->mac.type == e1000_pchlan)
5032                 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
5033
5034         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
5035         E1000_READ_REG(hw, E1000_ICR);
5036
5037         reg = E1000_READ_REG(hw, E1000_KABGTXD);
5038         reg |= E1000_KABGTXD_BGSQLBIAS;
5039         E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
5040
5041         return E1000_SUCCESS;
5042 }
5043
5044 /**
5045  *  e1000_init_hw_ich8lan - Initialize the hardware
5046  *  @hw: pointer to the HW structure
5047  *
5048  *  Prepares the hardware for transmit and receive by doing the following:
5049  *   - initialize hardware bits
5050  *   - initialize LED identification
5051  *   - setup receive address registers
5052  *   - setup flow control
5053  *   - setup transmit descriptors
5054  *   - clear statistics
5055  **/
5056 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
5057 {
5058         struct e1000_mac_info *mac = &hw->mac;
5059         u32 ctrl_ext, txdctl, snoop;
5060         s32 ret_val;
5061         u16 i;
5062
5063         DEBUGFUNC("e1000_init_hw_ich8lan");
5064
5065         e1000_initialize_hw_bits_ich8lan(hw);
5066
5067         /* Initialize identification LED */
5068         ret_val = mac->ops.id_led_init(hw);
5069         /* An error is not fatal and we should not stop init due to this */
5070         if (ret_val)
5071                 DEBUGOUT("Error initializing identification LED\n");
5072
5073         /* Setup the receive address. */
5074         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
5075
5076         /* Zero out the Multicast HASH table */
5077         DEBUGOUT("Zeroing the MTA\n");
5078         for (i = 0; i < mac->mta_reg_count; i++)
5079                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
5080
5081         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
5082          * the ME.  Disable wakeup by clearing the host wakeup bit.
5083          * Reset the phy after disabling host wakeup to reset the Rx buffer.
5084          */
5085         if (hw->phy.type == e1000_phy_82578) {
5086                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
5087                 i &= ~BM_WUC_HOST_WU_BIT;
5088                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
5089                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
5090                 if (ret_val)
5091                         return ret_val;
5092         }
5093
5094         /* Setup link and flow control */
5095         ret_val = mac->ops.setup_link(hw);
5096
5097         /* Set the transmit descriptor write-back policy for both queues */
5098         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
5099         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5100                   E1000_TXDCTL_FULL_TX_DESC_WB);
5101         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5102                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5103         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
5104         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
5105         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5106                   E1000_TXDCTL_FULL_TX_DESC_WB);
5107         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5108                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5109         E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
5110
5111         /* ICH8 has opposite polarity of no_snoop bits.
5112          * By default, we should use snoop behavior.
5113          */
5114         if (mac->type == e1000_ich8lan)
5115                 snoop = PCIE_ICH8_SNOOP_ALL;
5116         else
5117                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
5118         e1000_set_pcie_no_snoop_generic(hw, snoop);
5119
5120         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5121         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
5122         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5123
5124         /* Clear all of the statistics registers (clear on read).  It is
5125          * important that we do this after we have tried to establish link
5126          * because the symbol error count will increment wildly if there
5127          * is no link.
5128          */
5129         e1000_clear_hw_cntrs_ich8lan(hw);
5130
5131         return ret_val;
5132 }
5133
5134 /**
5135  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
5136  *  @hw: pointer to the HW structure
5137  *
5138  *  Sets/Clears required hardware bits necessary for correctly setting up the
5139  *  hardware for transmit and receive.
5140  **/
5141 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
5142 {
5143         u32 reg;
5144
5145         DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
5146
5147         /* Extended Device Control */
5148         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
5149         reg |= (1 << 22);
5150         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
5151         if (hw->mac.type >= e1000_pchlan)
5152                 reg |= E1000_CTRL_EXT_PHYPDEN;
5153         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
5154
5155         /* Transmit Descriptor Control 0 */
5156         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
5157         reg |= (1 << 22);
5158         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
5159
5160         /* Transmit Descriptor Control 1 */
5161         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
5162         reg |= (1 << 22);
5163         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
5164
5165         /* Transmit Arbitration Control 0 */
5166         reg = E1000_READ_REG(hw, E1000_TARC(0));
5167         if (hw->mac.type == e1000_ich8lan)
5168                 reg |= (1 << 28) | (1 << 29);
5169         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
5170         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
5171
5172         /* Transmit Arbitration Control 1 */
5173         reg = E1000_READ_REG(hw, E1000_TARC(1));
5174         if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
5175                 reg &= ~(1 << 28);
5176         else
5177                 reg |= (1 << 28);
5178         reg |= (1 << 24) | (1 << 26) | (1 << 30);
5179         E1000_WRITE_REG(hw, E1000_TARC(1), reg);
5180
5181         /* Device Status */
5182         if (hw->mac.type == e1000_ich8lan) {
5183                 reg = E1000_READ_REG(hw, E1000_STATUS);
5184                 reg &= ~(1U << 31);
5185                 E1000_WRITE_REG(hw, E1000_STATUS, reg);
5186         }
5187
5188         /* work-around descriptor data corruption issue during nfs v2 udp
5189          * traffic, just disable the nfs filtering capability
5190          */
5191         reg = E1000_READ_REG(hw, E1000_RFCTL);
5192         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
5193
5194         /* Disable IPv6 extension header parsing because some malformed
5195          * IPv6 headers can hang the Rx.
5196          */
5197         if (hw->mac.type == e1000_ich8lan)
5198                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
5199         E1000_WRITE_REG(hw, E1000_RFCTL, reg);
5200
5201         /* Enable ECC on Lynxpoint */
5202         if (hw->mac.type >= e1000_pch_lpt) {
5203                 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
5204                 reg |= E1000_PBECCSTS_ECC_ENABLE;
5205                 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
5206
5207                 reg = E1000_READ_REG(hw, E1000_CTRL);
5208                 reg |= E1000_CTRL_MEHE;
5209                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
5210         }
5211
5212         return;
5213 }
5214
5215 /**
5216  *  e1000_setup_link_ich8lan - Setup flow control and link settings
5217  *  @hw: pointer to the HW structure
5218  *
5219  *  Determines which flow control settings to use, then configures flow
5220  *  control.  Calls the appropriate media-specific link configuration
5221  *  function.  Assuming the adapter has a valid link partner, a valid link
5222  *  should be established.  Assumes the hardware has previously been reset
5223  *  and the transmitter and receiver are not enabled.
5224  **/
5225 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
5226 {
5227         s32 ret_val;
5228
5229         DEBUGFUNC("e1000_setup_link_ich8lan");
5230
5231         /* ICH parts do not have a word in the NVM to determine
5232          * the default flow control setting, so we explicitly
5233          * set it to full.
5234          */
5235         if (hw->fc.requested_mode == e1000_fc_default)
5236                 hw->fc.requested_mode = e1000_fc_full;
5237
5238         /* Save off the requested flow control mode for use later.  Depending
5239          * on the link partner's capabilities, we may or may not use this mode.
5240          */
5241         hw->fc.current_mode = hw->fc.requested_mode;
5242
5243         DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
5244                 hw->fc.current_mode);
5245
5246         if (!hw->phy.ops.check_reset_block(hw)) {
5247                 /* Continue to configure the copper link. */
5248                 ret_val = hw->mac.ops.setup_physical_interface(hw);
5249                 if (ret_val)
5250                         return ret_val;
5251         }
5252
5253         E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
5254         if ((hw->phy.type == e1000_phy_82578) ||
5255             (hw->phy.type == e1000_phy_82579) ||
5256             (hw->phy.type == e1000_phy_i217) ||
5257             (hw->phy.type == e1000_phy_82577)) {
5258                 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
5259
5260                 ret_val = hw->phy.ops.write_reg(hw,
5261                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
5262                                              hw->fc.pause_time);
5263                 if (ret_val)
5264                         return ret_val;
5265         }
5266
5267         return e1000_set_fc_watermarks_generic(hw);
5268 }
5269
5270 /**
5271  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5272  *  @hw: pointer to the HW structure
5273  *
5274  *  Configures the kumeran interface to the PHY to wait the appropriate time
5275  *  when polling the PHY, then call the generic setup_copper_link to finish
5276  *  configuring the copper link.
5277  **/
5278 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5279 {
5280         u32 ctrl;
5281         s32 ret_val;
5282         u16 reg_data;
5283
5284         DEBUGFUNC("e1000_setup_copper_link_ich8lan");
5285
5286         ctrl = E1000_READ_REG(hw, E1000_CTRL);
5287         ctrl |= E1000_CTRL_SLU;
5288         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5289         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5290
5291         /* Set the mac to wait the maximum time between each iteration
5292          * and increase the max iterations when polling the phy;
5293          * this fixes erroneous timeouts at 10Mbps.
5294          */
5295         ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
5296                                                0xFFFF);
5297         if (ret_val)
5298                 return ret_val;
5299         ret_val = e1000_read_kmrn_reg_generic(hw,
5300                                               E1000_KMRNCTRLSTA_INBAND_PARAM,
5301                                               &reg_data);
5302         if (ret_val)
5303                 return ret_val;
5304         reg_data |= 0x3F;
5305         ret_val = e1000_write_kmrn_reg_generic(hw,
5306                                                E1000_KMRNCTRLSTA_INBAND_PARAM,
5307                                                reg_data);
5308         if (ret_val)
5309                 return ret_val;
5310
5311         switch (hw->phy.type) {
5312         case e1000_phy_igp_3:
5313                 ret_val = e1000_copper_link_setup_igp(hw);
5314                 if (ret_val)
5315                         return ret_val;
5316                 break;
5317         case e1000_phy_bm:
5318         case e1000_phy_82578:
5319                 ret_val = e1000_copper_link_setup_m88(hw);
5320                 if (ret_val)
5321                         return ret_val;
5322                 break;
5323         case e1000_phy_82577:
5324         case e1000_phy_82579:
5325                 ret_val = e1000_copper_link_setup_82577(hw);
5326                 if (ret_val)
5327                         return ret_val;
5328                 break;
5329         case e1000_phy_ife:
5330                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
5331                                                &reg_data);
5332                 if (ret_val)
5333                         return ret_val;
5334
5335                 reg_data &= ~IFE_PMC_AUTO_MDIX;
5336
5337                 switch (hw->phy.mdix) {
5338                 case 1:
5339                         reg_data &= ~IFE_PMC_FORCE_MDIX;
5340                         break;
5341                 case 2:
5342                         reg_data |= IFE_PMC_FORCE_MDIX;
5343                         break;
5344                 case 0:
5345                 default:
5346                         reg_data |= IFE_PMC_AUTO_MDIX;
5347                         break;
5348                 }
5349                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
5350                                                 reg_data);
5351                 if (ret_val)
5352                         return ret_val;
5353                 break;
5354         default:
5355                 break;
5356         }
5357
5358         return e1000_setup_copper_link_generic(hw);
5359 }
5360
5361 /**
5362  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5363  *  @hw: pointer to the HW structure
5364  *
5365  *  Calls the PHY specific link setup function and then calls the
5366  *  generic setup_copper_link to finish configuring the link for
5367  *  Lynxpoint PCH devices
5368  **/
5369 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5370 {
5371         u32 ctrl;
5372         s32 ret_val;
5373
5374         DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
5375
5376         ctrl = E1000_READ_REG(hw, E1000_CTRL);
5377         ctrl |= E1000_CTRL_SLU;
5378         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5379         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5380
5381         ret_val = e1000_copper_link_setup_82577(hw);
5382         if (ret_val)
5383                 return ret_val;
5384
5385         return e1000_setup_copper_link_generic(hw);
5386 }
5387
5388 /**
5389  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5390  *  @hw: pointer to the HW structure
5391  *  @speed: pointer to store current link speed
5392  *  @duplex: pointer to store the current link duplex
5393  *
5394  *  Calls the generic get_speed_and_duplex to retrieve the current link
5395  *  information and then calls the Kumeran lock loss workaround for links at
5396  *  gigabit speeds.
5397  **/
5398 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5399                                           u16 *duplex)
5400 {
5401         s32 ret_val;
5402
5403         DEBUGFUNC("e1000_get_link_up_info_ich8lan");
5404
5405         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
5406         if (ret_val)
5407                 return ret_val;
5408
5409         if ((hw->mac.type == e1000_ich8lan) &&
5410             (hw->phy.type == e1000_phy_igp_3) &&
5411             (*speed == SPEED_1000)) {
5412                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5413         }
5414
5415         return ret_val;
5416 }
5417
5418 /**
5419  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5420  *  @hw: pointer to the HW structure
5421  *
5422  *  Work-around for 82566 Kumeran PCS lock loss:
5423  *  On link status change (i.e. PCI reset, speed change) and link is up and
5424  *  speed is gigabit-
5425  *    0) if workaround is optionally disabled do nothing
5426  *    1) wait 1ms for Kumeran link to come up
5427  *    2) check Kumeran Diagnostic register PCS lock loss bit
5428  *    3) if not set the link is locked (all is good), otherwise...
5429  *    4) reset the PHY
5430  *    5) repeat up to 10 times
5431  *  Note: this is only called for IGP3 copper when speed is 1gb.
5432  **/
5433 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5434 {
5435         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5436         u32 phy_ctrl;
5437         s32 ret_val;
5438         u16 i, data;
5439         bool link;
5440
5441         DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
5442
5443         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5444                 return E1000_SUCCESS;
5445
5446         /* Make sure link is up before proceeding.  If not just return.
5447          * Attempting this while link is negotiating fouled up link
5448          * stability
5449          */
5450         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
5451         if (!link)
5452                 return E1000_SUCCESS;
5453
5454         for (i = 0; i < 10; i++) {
5455                 /* read once to clear */
5456                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5457                 if (ret_val)
5458                         return ret_val;
5459                 /* and again to get new status */
5460                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5461                 if (ret_val)
5462                         return ret_val;
5463
5464                 /* check for PCS lock */
5465                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5466                         return E1000_SUCCESS;
5467
5468                 /* Issue PHY reset */
5469                 hw->phy.ops.reset(hw);
5470                 msec_delay_irq(5);
5471         }
5472         /* Disable GigE link negotiation */
5473         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5474         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5475                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5476         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5477
5478         /* Call gig speed drop workaround on Gig disable before accessing
5479          * any PHY registers
5480          */
5481         e1000_gig_downshift_workaround_ich8lan(hw);
5482
5483         /* unable to acquire PCS lock */
5484         return -E1000_ERR_PHY;
5485 }
5486
5487 /**
5488  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5489  *  @hw: pointer to the HW structure
5490  *  @state: boolean value used to set the current Kumeran workaround state
5491  *
5492  *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
5493  *  /disabled - FALSE).
5494  **/
5495 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5496                                                  bool state)
5497 {
5498         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5499
5500         DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
5501
5502         if (hw->mac.type != e1000_ich8lan) {
5503                 DEBUGOUT("Workaround applies to ICH8 only.\n");
5504                 return;
5505         }
5506
5507         dev_spec->kmrn_lock_loss_workaround_enabled = state;
5508
5509         return;
5510 }
5511
5512 /**
5513  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5514  *  @hw: pointer to the HW structure
5515  *
5516  *  Workaround for 82566 power-down on D3 entry:
5517  *    1) disable gigabit link
5518  *    2) write VR power-down enable
5519  *    3) read it back
5520  *  Continue if successful, else issue LCD reset and repeat
5521  **/
5522 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5523 {
5524         u32 reg;
5525         u16 data;
5526         u8  retry = 0;
5527
5528         DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
5529
5530         if (hw->phy.type != e1000_phy_igp_3)
5531                 return;
5532
5533         /* Try the workaround twice (if needed) */
5534         do {
5535                 /* Disable link */
5536                 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
5537                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5538                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5539                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
5540
5541                 /* Call gig speed drop workaround on Gig disable before
5542                  * accessing any PHY registers
5543                  */
5544                 if (hw->mac.type == e1000_ich8lan)
5545                         e1000_gig_downshift_workaround_ich8lan(hw);
5546
5547                 /* Write VR power-down enable */
5548                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5549                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5550                 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
5551                                       data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5552
5553                 /* Read it back and test */
5554                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5555                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5556                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5557                         break;
5558
5559                 /* Issue PHY reset and repeat at most one more time */
5560                 reg = E1000_READ_REG(hw, E1000_CTRL);
5561                 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
5562                 retry++;
5563         } while (retry);
5564 }
5565
5566 /**
5567  *  e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5568  *  @hw: pointer to the HW structure
5569  *
5570  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5571  *  LPLU, Gig disable, MDIC PHY reset):
5572  *    1) Set Kumeran Near-end loopback
5573  *    2) Clear Kumeran Near-end loopback
5574  *  Should only be called for ICH8[m] devices with any 1G Phy.
5575  **/
5576 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5577 {
5578         s32 ret_val;
5579         u16 reg_data;
5580
5581         DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
5582
5583         if ((hw->mac.type != e1000_ich8lan) ||
5584             (hw->phy.type == e1000_phy_ife))
5585                 return;
5586
5587         ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5588                                               &reg_data);
5589         if (ret_val)
5590                 return;
5591         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5592         ret_val = e1000_write_kmrn_reg_generic(hw,
5593                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
5594                                                reg_data);
5595         if (ret_val)
5596                 return;
5597         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5598         e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5599                                      reg_data);
5600 }
5601
5602 /**
5603  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5604  *  @hw: pointer to the HW structure
5605  *
5606  *  During S0 to Sx transition, it is possible the link remains at gig
5607  *  instead of negotiating to a lower speed.  Before going to Sx, set
5608  *  'Gig Disable' to force link speed negotiation to a lower speed based on
5609  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
5610  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5611  *  needs to be written.
5612  *  Parts that support (and are linked to a partner which support) EEE in
5613  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5614  *  than 10Mbps w/o EEE.
5615  **/
5616 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5617 {
5618         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5619         u32 phy_ctrl;
5620         s32 ret_val;
5621
5622         DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
5623
5624         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5625         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5626
5627         if (hw->phy.type == e1000_phy_i217) {
5628                 u16 phy_reg, device_id = hw->device_id;
5629
5630                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5631                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5632                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5633                     (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5634                     (hw->mac.type >= e1000_pch_spt)) {
5635                         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
5636
5637                         E1000_WRITE_REG(hw, E1000_FEXTNVM6,
5638                                         fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5639                 }
5640
5641                 ret_val = hw->phy.ops.acquire(hw);
5642                 if (ret_val)
5643                         goto out;
5644
5645                 if (!dev_spec->eee_disable) {
5646                         u16 eee_advert;
5647
5648                         ret_val =
5649                             e1000_read_emi_reg_locked(hw,
5650                                                       I217_EEE_ADVERTISEMENT,
5651                                                       &eee_advert);
5652                         if (ret_val)
5653                                 goto release;
5654
5655                         /* Disable LPLU if both link partners support 100BaseT
5656                          * EEE and 100Full is advertised on both ends of the
5657                          * link, and enable Auto Enable LPI since there will
5658                          * be no driver to enable LPI while in Sx.
5659                          */
5660                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5661                             (dev_spec->eee_lp_ability &
5662                              I82579_EEE_100_SUPPORTED) &&
5663                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5664                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5665                                               E1000_PHY_CTRL_NOND0A_LPLU);
5666
5667                                 /* Set Auto Enable LPI after link up */
5668                                 hw->phy.ops.read_reg_locked(hw,
5669                                                             I217_LPI_GPIO_CTRL,
5670                                                             &phy_reg);
5671                                 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5672                                 hw->phy.ops.write_reg_locked(hw,
5673                                                              I217_LPI_GPIO_CTRL,
5674                                                              phy_reg);
5675                         }
5676                 }
5677
5678                 /* For i217 Intel Rapid Start Technology support,
5679                  * when the system is going into Sx and no manageability engine
5680                  * is present, the driver must configure proxy to reset only on
5681                  * power good.  LPI (Low Power Idle) state must also reset only
5682                  * on power good, as well as the MTA (Multicast table array).
5683                  * The SMBus release must also be disabled on LCD reset.
5684                  */
5685                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5686                       E1000_ICH_FWSM_FW_VALID)) {
5687                         /* Enable proxy to reset only on power good. */
5688                         hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
5689                                                     &phy_reg);
5690                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5691                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
5692                                                      phy_reg);
5693
5694                         /* Set bit enable LPI (EEE) to reset only on
5695                          * power good.
5696                         */
5697                         hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
5698                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5699                         hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
5700
5701                         /* Disable the SMB release on LCD reset. */
5702                         hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
5703                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5704                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5705                 }
5706
5707                 /* Enable MTA to reset for Intel Rapid Start Technology
5708                  * Support
5709                  */
5710                 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
5711                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5712                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5713
5714 release:
5715                 hw->phy.ops.release(hw);
5716         }
5717 out:
5718         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5719
5720         if (hw->mac.type == e1000_ich8lan)
5721                 e1000_gig_downshift_workaround_ich8lan(hw);
5722
5723         if (hw->mac.type >= e1000_pchlan) {
5724                 e1000_oem_bits_config_ich8lan(hw, FALSE);
5725
5726                 /* Reset PHY to activate OEM bits on 82577/8 */
5727                 if (hw->mac.type == e1000_pchlan)
5728                         e1000_phy_hw_reset_generic(hw);
5729
5730                 ret_val = hw->phy.ops.acquire(hw);
5731                 if (ret_val)
5732                         return;
5733                 e1000_write_smbus_addr(hw);
5734                 hw->phy.ops.release(hw);
5735         }
5736
5737         return;
5738 }
5739
5740 /**
5741  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5742  *  @hw: pointer to the HW structure
5743  *
5744  *  During Sx to S0 transitions on non-managed devices or managed devices
5745  *  on which PHY resets are not blocked, if the PHY registers cannot be
5746  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
5747  *  the PHY.
5748  *  On i217, setup Intel Rapid Start Technology.
5749  **/
5750 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5751 {
5752         s32 ret_val;
5753
5754         DEBUGFUNC("e1000_resume_workarounds_pchlan");
5755         if (hw->mac.type < e1000_pch2lan)
5756                 return E1000_SUCCESS;
5757
5758         ret_val = e1000_init_phy_workarounds_pchlan(hw);
5759         if (ret_val) {
5760                 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5761                 return ret_val;
5762         }
5763
5764         /* For i217 Intel Rapid Start Technology support when the system
5765          * is transitioning from Sx and no manageability engine is present
5766          * configure SMBus to restore on reset, disable proxy, and enable
5767          * the reset on MTA (Multicast table array).
5768          */
5769         if (hw->phy.type == e1000_phy_i217) {
5770                 u16 phy_reg;
5771
5772                 ret_val = hw->phy.ops.acquire(hw);
5773                 if (ret_val) {
5774                         DEBUGOUT("Failed to setup iRST\n");
5775                         return ret_val;
5776                 }
5777
5778                 /* Clear Auto Enable LPI after link up */
5779                 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5780                 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5781                 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5782
5783                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5784                     E1000_ICH_FWSM_FW_VALID)) {
5785                         /* Restore clear on SMB if no manageability engine
5786                          * is present
5787                          */
5788                         ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5789                                                               &phy_reg);
5790                         if (ret_val)
5791                                 goto release;
5792                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5793                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5794
5795                         /* Disable Proxy */
5796                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5797                 }
5798                 /* Enable reset on MTA */
5799                 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5800                                                       &phy_reg);
5801                 if (ret_val)
5802                         goto release;
5803                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5804                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5805 release:
5806                 if (ret_val)
5807                         DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5808                 hw->phy.ops.release(hw);
5809                 return ret_val;
5810         }
5811         return E1000_SUCCESS;
5812 }
5813
5814 /**
5815  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
5816  *  @hw: pointer to the HW structure
5817  *
5818  *  Return the LED back to the default configuration.
5819  **/
5820 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5821 {
5822         DEBUGFUNC("e1000_cleanup_led_ich8lan");
5823
5824         if (hw->phy.type == e1000_phy_ife)
5825                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5826                                              0);
5827
5828         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5829         return E1000_SUCCESS;
5830 }
5831
5832 /**
5833  *  e1000_led_on_ich8lan - Turn LEDs on
5834  *  @hw: pointer to the HW structure
5835  *
5836  *  Turn on the LEDs.
5837  **/
5838 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5839 {
5840         DEBUGFUNC("e1000_led_on_ich8lan");
5841
5842         if (hw->phy.type == e1000_phy_ife)
5843                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5844                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5845
5846         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5847         return E1000_SUCCESS;
5848 }
5849
5850 /**
5851  *  e1000_led_off_ich8lan - Turn LEDs off
5852  *  @hw: pointer to the HW structure
5853  *
5854  *  Turn off the LEDs.
5855  **/
5856 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5857 {
5858         DEBUGFUNC("e1000_led_off_ich8lan");
5859
5860         if (hw->phy.type == e1000_phy_ife)
5861                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5862                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5863
5864         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5865         return E1000_SUCCESS;
5866 }
5867
5868 /**
5869  *  e1000_setup_led_pchlan - Configures SW controllable LED
5870  *  @hw: pointer to the HW structure
5871  *
5872  *  This prepares the SW controllable LED for use.
5873  **/
5874 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5875 {
5876         DEBUGFUNC("e1000_setup_led_pchlan");
5877
5878         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5879                                      (u16)hw->mac.ledctl_mode1);
5880 }
5881
5882 /**
5883  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5884  *  @hw: pointer to the HW structure
5885  *
5886  *  Return the LED back to the default configuration.
5887  **/
5888 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5889 {
5890         DEBUGFUNC("e1000_cleanup_led_pchlan");
5891
5892         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5893                                      (u16)hw->mac.ledctl_default);
5894 }
5895
5896 /**
5897  *  e1000_led_on_pchlan - Turn LEDs on
5898  *  @hw: pointer to the HW structure
5899  *
5900  *  Turn on the LEDs.
5901  **/
5902 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5903 {
5904         u16 data = (u16)hw->mac.ledctl_mode2;
5905         u32 i, led;
5906
5907         DEBUGFUNC("e1000_led_on_pchlan");
5908
5909         /* If no link, then turn LED on by setting the invert bit
5910          * for each LED that's mode is "link_up" in ledctl_mode2.
5911          */
5912         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5913                 for (i = 0; i < 3; i++) {
5914                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5915                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5916                             E1000_LEDCTL_MODE_LINK_UP)
5917                                 continue;
5918                         if (led & E1000_PHY_LED0_IVRT)
5919                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5920                         else
5921                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5922                 }
5923         }
5924
5925         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5926 }
5927
5928 /**
5929  *  e1000_led_off_pchlan - Turn LEDs off
5930  *  @hw: pointer to the HW structure
5931  *
5932  *  Turn off the LEDs.
5933  **/
5934 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5935 {
5936         u16 data = (u16)hw->mac.ledctl_mode1;
5937         u32 i, led;
5938
5939         DEBUGFUNC("e1000_led_off_pchlan");
5940
5941         /* If no link, then turn LED off by clearing the invert bit
5942          * for each LED that's mode is "link_up" in ledctl_mode1.
5943          */
5944         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5945                 for (i = 0; i < 3; i++) {
5946                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5947                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5948                             E1000_LEDCTL_MODE_LINK_UP)
5949                                 continue;
5950                         if (led & E1000_PHY_LED0_IVRT)
5951                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5952                         else
5953                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5954                 }
5955         }
5956
5957         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5958 }
5959
5960 /**
5961  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5962  *  @hw: pointer to the HW structure
5963  *
5964  *  Read appropriate register for the config done bit for completion status
5965  *  and configure the PHY through s/w for EEPROM-less parts.
5966  *
5967  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5968  *  config done bit, so only an error is logged and continues.  If we were
5969  *  to return with error, EEPROM-less silicon would not be able to be reset
5970  *  or change link.
5971  **/
5972 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5973 {
5974         s32 ret_val = E1000_SUCCESS;
5975         u32 bank = 0;
5976         u32 status;
5977
5978         DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5979
5980         e1000_get_cfg_done_generic(hw);
5981
5982         /* Wait for indication from h/w that it has completed basic config */
5983         if (hw->mac.type >= e1000_ich10lan) {
5984                 e1000_lan_init_done_ich8lan(hw);
5985         } else {
5986                 ret_val = e1000_get_auto_rd_done_generic(hw);
5987                 if (ret_val) {
5988                         /* When auto config read does not complete, do not
5989                          * return with an error. This can happen in situations
5990                          * where there is no eeprom and prevents getting link.
5991                          */
5992                         DEBUGOUT("Auto Read Done did not complete\n");
5993                         ret_val = E1000_SUCCESS;
5994                 }
5995         }
5996
5997         /* Clear PHY Reset Asserted bit */
5998         status = E1000_READ_REG(hw, E1000_STATUS);
5999         if (status & E1000_STATUS_PHYRA)
6000                 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
6001         else
6002                 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
6003
6004         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
6005         if (hw->mac.type <= e1000_ich9lan) {
6006                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
6007                     (hw->phy.type == e1000_phy_igp_3)) {
6008                         e1000_phy_init_script_igp3(hw);
6009                 }
6010         } else {
6011                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
6012                         /* Maybe we should do a basic PHY config */
6013                         DEBUGOUT("EEPROM not present\n");
6014                         ret_val = -E1000_ERR_CONFIG;
6015                 }
6016         }
6017
6018         return ret_val;
6019 }
6020
6021 /**
6022  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
6023  * @hw: pointer to the HW structure
6024  *
6025  * In the case of a PHY power down to save power, or to turn off link during a
6026  * driver unload, or wake on lan is not enabled, remove the link.
6027  **/
6028 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
6029 {
6030         /* If the management interface is not enabled, then power down */
6031         if (!(hw->mac.ops.check_mng_mode(hw) ||
6032               hw->phy.ops.check_reset_block(hw)))
6033                 e1000_power_down_phy_copper(hw);
6034
6035         return;
6036 }
6037
6038 /**
6039  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
6040  *  @hw: pointer to the HW structure
6041  *
6042  *  Clears hardware counters specific to the silicon family and calls
6043  *  clear_hw_cntrs_generic to clear all general purpose counters.
6044  **/
6045 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
6046 {
6047         u16 phy_data;
6048         s32 ret_val;
6049
6050         DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
6051
6052         e1000_clear_hw_cntrs_base_generic(hw);
6053
6054         E1000_READ_REG(hw, E1000_ALGNERRC);
6055         E1000_READ_REG(hw, E1000_RXERRC);
6056         E1000_READ_REG(hw, E1000_TNCRS);
6057         E1000_READ_REG(hw, E1000_CEXTERR);
6058         E1000_READ_REG(hw, E1000_TSCTC);
6059         E1000_READ_REG(hw, E1000_TSCTFC);
6060
6061         E1000_READ_REG(hw, E1000_MGTPRC);
6062         E1000_READ_REG(hw, E1000_MGTPDC);
6063         E1000_READ_REG(hw, E1000_MGTPTC);
6064
6065         E1000_READ_REG(hw, E1000_IAC);
6066         E1000_READ_REG(hw, E1000_ICRXOC);
6067
6068         /* Clear PHY statistics registers */
6069         if ((hw->phy.type == e1000_phy_82578) ||
6070             (hw->phy.type == e1000_phy_82579) ||
6071             (hw->phy.type == e1000_phy_i217) ||
6072             (hw->phy.type == e1000_phy_82577)) {
6073                 ret_val = hw->phy.ops.acquire(hw);
6074                 if (ret_val)
6075                         return;
6076                 ret_val = hw->phy.ops.set_page(hw,
6077                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
6078                 if (ret_val)
6079                         goto release;
6080                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
6081                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
6082                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
6083                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
6084                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
6085                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
6086                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
6087                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
6088                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
6089                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
6090                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
6091                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
6092                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
6093                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
6094 release:
6095                 hw->phy.ops.release(hw);
6096         }
6097 }
6098