1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2015, Intel Corporation
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
33 ******************************************************************************/
36 #include "e1000_api.h"
38 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
39 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
40 static void e1000_config_collision_dist_generic(struct e1000_hw *hw);
41 static int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
44 * e1000_init_mac_ops_generic - Initialize MAC function pointers
45 * @hw: pointer to the HW structure
47 * Setups up the function pointers to no-op functions
49 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
51 struct e1000_mac_info *mac = &hw->mac;
52 DEBUGFUNC("e1000_init_mac_ops_generic");
55 mac->ops.init_params = e1000_null_ops_generic;
56 mac->ops.init_hw = e1000_null_ops_generic;
57 mac->ops.reset_hw = e1000_null_ops_generic;
58 mac->ops.setup_physical_interface = e1000_null_ops_generic;
59 mac->ops.get_bus_info = e1000_null_ops_generic;
60 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
61 mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
62 mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
63 mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
65 mac->ops.cleanup_led = e1000_null_ops_generic;
66 mac->ops.setup_led = e1000_null_ops_generic;
67 mac->ops.blink_led = e1000_null_ops_generic;
68 mac->ops.led_on = e1000_null_ops_generic;
69 mac->ops.led_off = e1000_null_ops_generic;
71 mac->ops.setup_link = e1000_null_ops_generic;
72 mac->ops.get_link_up_info = e1000_null_link_info;
73 mac->ops.check_for_link = e1000_null_ops_generic;
74 mac->ops.set_obff_timer = e1000_null_set_obff_timer;
76 mac->ops.check_mng_mode = e1000_null_mng_mode;
78 mac->ops.update_mc_addr_list = e1000_null_update_mc;
79 mac->ops.clear_vfta = e1000_null_mac_generic;
80 mac->ops.write_vfta = e1000_null_write_vfta;
81 mac->ops.rar_set = e1000_rar_set_generic;
82 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
86 * e1000_null_ops_generic - No-op function, returns 0
87 * @hw: pointer to the HW structure
89 s32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw)
91 DEBUGFUNC("e1000_null_ops_generic");
96 * e1000_null_mac_generic - No-op function, return void
97 * @hw: pointer to the HW structure
99 void e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw)
101 DEBUGFUNC("e1000_null_mac_generic");
106 * e1000_null_link_info - No-op function, return 0
107 * @hw: pointer to the HW structure
109 s32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw,
110 u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d)
112 DEBUGFUNC("e1000_null_link_info");
113 return E1000_SUCCESS;
117 * e1000_null_mng_mode - No-op function, return FALSE
118 * @hw: pointer to the HW structure
120 bool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw)
122 DEBUGFUNC("e1000_null_mng_mode");
127 * e1000_null_update_mc - No-op function, return void
128 * @hw: pointer to the HW structure
130 void e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw,
131 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)
133 DEBUGFUNC("e1000_null_update_mc");
138 * e1000_null_write_vfta - No-op function, return void
139 * @hw: pointer to the HW structure
141 void e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw,
142 u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b)
144 DEBUGFUNC("e1000_null_write_vfta");
149 * e1000_null_rar_set - No-op function, return 0
150 * @hw: pointer to the HW structure
152 int e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw,
153 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)
155 DEBUGFUNC("e1000_null_rar_set");
156 return E1000_SUCCESS;
160 * e1000_null_set_obff_timer - No-op function, return 0
161 * @hw: pointer to the HW structure
163 s32 e1000_null_set_obff_timer(struct e1000_hw E1000_UNUSEDARG *hw,
164 u32 E1000_UNUSEDARG a)
166 DEBUGFUNC("e1000_null_set_obff_timer");
167 return E1000_SUCCESS;
171 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information
172 * @hw: pointer to the HW structure
174 * Determines and stores the system bus information for a particular
175 * network interface. The following bus information is determined and stored:
176 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
178 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
180 struct e1000_mac_info *mac = &hw->mac;
181 struct e1000_bus_info *bus = &hw->bus;
182 u32 status = E1000_READ_REG(hw, E1000_STATUS);
183 s32 ret_val = E1000_SUCCESS;
185 DEBUGFUNC("e1000_get_bus_info_pci_generic");
188 bus->type = (status & E1000_STATUS_PCIX_MODE)
189 ? e1000_bus_type_pcix
190 : e1000_bus_type_pci;
193 if (bus->type == e1000_bus_type_pci) {
194 bus->speed = (status & E1000_STATUS_PCI66)
196 : e1000_bus_speed_33;
198 switch (status & E1000_STATUS_PCIX_SPEED) {
199 case E1000_STATUS_PCIX_SPEED_66:
200 bus->speed = e1000_bus_speed_66;
202 case E1000_STATUS_PCIX_SPEED_100:
203 bus->speed = e1000_bus_speed_100;
205 case E1000_STATUS_PCIX_SPEED_133:
206 bus->speed = e1000_bus_speed_133;
209 bus->speed = e1000_bus_speed_reserved;
215 bus->width = (status & E1000_STATUS_BUS64)
217 : e1000_bus_width_32;
219 /* Which PCI(-X) function? */
220 mac->ops.set_lan_id(hw);
226 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
227 * @hw: pointer to the HW structure
229 * Determines and stores the system bus information for a particular
230 * network interface. The following bus information is determined and stored:
231 * bus speed, bus width, type (PCIe), and PCIe function.
233 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
235 struct e1000_mac_info *mac = &hw->mac;
236 struct e1000_bus_info *bus = &hw->bus;
238 u16 pcie_link_status;
240 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
242 bus->type = e1000_bus_type_pci_express;
244 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
247 bus->width = e1000_bus_width_unknown;
248 bus->speed = e1000_bus_speed_unknown;
250 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
251 case PCIE_LINK_SPEED_2500:
252 bus->speed = e1000_bus_speed_2500;
254 case PCIE_LINK_SPEED_5000:
255 bus->speed = e1000_bus_speed_5000;
258 bus->speed = e1000_bus_speed_unknown;
262 bus->width = (enum e1000_bus_width)((pcie_link_status &
263 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT);
266 mac->ops.set_lan_id(hw);
268 return E1000_SUCCESS;
272 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
274 * @hw: pointer to the HW structure
276 * Determines the LAN function id by reading memory-mapped registers
277 * and swaps the port value if requested.
279 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
281 struct e1000_bus_info *bus = &hw->bus;
284 /* The status register reports the correct function number
285 * for the device regardless of function swap state.
287 reg = E1000_READ_REG(hw, E1000_STATUS);
288 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
292 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices
293 * @hw: pointer to the HW structure
295 * Determines the LAN function id by reading PCI config space.
297 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
299 struct e1000_bus_info *bus = &hw->bus;
303 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
304 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
305 status = E1000_READ_REG(hw, E1000_STATUS);
306 bus->func = (status & E1000_STATUS_FUNC_MASK)
307 >> E1000_STATUS_FUNC_SHIFT;
314 * e1000_set_lan_id_single_port - Set LAN id for a single port device
315 * @hw: pointer to the HW structure
317 * Sets the LAN function id to zero for a single port device.
319 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
321 struct e1000_bus_info *bus = &hw->bus;
327 * e1000_clear_vfta_generic - Clear VLAN filter table
328 * @hw: pointer to the HW structure
330 * Clears the register array which contains the VLAN filter table by
331 * setting all the values to 0.
333 void e1000_clear_vfta_generic(struct e1000_hw *hw)
337 DEBUGFUNC("e1000_clear_vfta_generic");
339 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
340 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
341 E1000_WRITE_FLUSH(hw);
346 * e1000_write_vfta_generic - Write value to VLAN filter table
347 * @hw: pointer to the HW structure
348 * @offset: register offset in VLAN filter table
349 * @value: register value written to VLAN filter table
351 * Writes value at the given offset in the register array which stores
352 * the VLAN filter table.
354 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
356 DEBUGFUNC("e1000_write_vfta_generic");
358 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
359 E1000_WRITE_FLUSH(hw);
363 * e1000_init_rx_addrs_generic - Initialize receive address's
364 * @hw: pointer to the HW structure
365 * @rar_count: receive address registers
367 * Setup the receive address registers by setting the base receive address
368 * register to the devices MAC address and clearing all the other receive
369 * address registers to 0.
371 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
374 u8 mac_addr[ETH_ADDR_LEN] = {0};
376 DEBUGFUNC("e1000_init_rx_addrs_generic");
378 /* Setup the receive address */
379 DEBUGOUT("Programming MAC Address into RAR[0]\n");
381 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
383 /* Zero out the other (rar_entry_count - 1) receive addresses */
384 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
385 for (i = 1; i < rar_count; i++)
386 hw->mac.ops.rar_set(hw, mac_addr, i);
390 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
391 * @hw: pointer to the HW structure
393 * Checks the nvm for an alternate MAC address. An alternate MAC address
394 * can be setup by pre-boot software and must be treated like a permanent
395 * address and must override the actual permanent MAC address. If an
396 * alternate MAC address is found it is programmed into RAR0, replacing
397 * the permanent address that was installed into RAR0 by the Si on reset.
398 * This function will return SUCCESS unless it encounters an error while
399 * reading the EEPROM.
401 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
405 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
406 u8 alt_mac_addr[ETH_ADDR_LEN];
408 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
410 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
414 /* not supported on older hardware or 82573 */
415 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573))
416 return E1000_SUCCESS;
418 /* Alternate MAC address is handled by the option ROM for 82580
419 * and newer. SW support not required.
421 if (hw->mac.type >= e1000_82580)
422 return E1000_SUCCESS;
424 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
425 &nvm_alt_mac_addr_offset);
427 DEBUGOUT("NVM Read Error\n");
431 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
432 (nvm_alt_mac_addr_offset == 0x0000))
433 /* There is no Alternate MAC Address */
434 return E1000_SUCCESS;
436 if (hw->bus.func == E1000_FUNC_1)
437 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
438 if (hw->bus.func == E1000_FUNC_2)
439 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
441 if (hw->bus.func == E1000_FUNC_3)
442 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
443 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
444 offset = nvm_alt_mac_addr_offset + (i >> 1);
445 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
447 DEBUGOUT("NVM Read Error\n");
451 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
452 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
455 /* if multicast bit is set, the alternate address will not be used */
456 if (alt_mac_addr[0] & 0x01) {
457 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
458 return E1000_SUCCESS;
461 /* We have a valid alternate MAC address, and we want to treat it the
462 * same as the normal permanent MAC address stored by the HW into the
463 * RAR. Do this by mapping this address into RAR0.
465 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
467 return E1000_SUCCESS;
471 * e1000_rar_set_generic - Set receive address register
472 * @hw: pointer to the HW structure
473 * @addr: pointer to the receive address
474 * @index: receive address array register
476 * Sets the receive address array register at index to the address passed
479 static int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
481 u32 rar_low, rar_high;
483 DEBUGFUNC("e1000_rar_set_generic");
485 /* HW expects these in little endian so we reverse the byte order
486 * from network order (big endian) to little endian
488 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
489 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
491 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
493 /* If MAC address zero, no need to set the AV bit */
494 if (rar_low || rar_high)
495 rar_high |= E1000_RAH_AV;
497 /* Some bridges will combine consecutive 32-bit writes into
498 * a single burst write, which will malfunction on some parts.
499 * The flushes avoid this.
501 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
502 E1000_WRITE_FLUSH(hw);
503 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
504 E1000_WRITE_FLUSH(hw);
506 return E1000_SUCCESS;
510 * e1000_hash_mc_addr_generic - Generate a multicast hash value
511 * @hw: pointer to the HW structure
512 * @mc_addr: pointer to a multicast address
514 * Generates a multicast address hash value which is used to determine
515 * the multicast filter table array address and new table value.
517 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
519 u32 hash_value, hash_mask;
522 DEBUGFUNC("e1000_hash_mc_addr_generic");
524 /* Register count multiplied by bits per register */
525 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
527 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
528 * where 0xFF would still fall within the hash mask.
530 while (hash_mask >> bit_shift != 0xFF)
533 /* The portion of the address that is used for the hash table
534 * is determined by the mc_filter_type setting.
535 * The algorithm is such that there is a total of 8 bits of shifting.
536 * The bit_shift for a mc_filter_type of 0 represents the number of
537 * left-shifts where the MSB of mc_addr[5] would still fall within
538 * the hash_mask. Case 0 does this exactly. Since there are a total
539 * of 8 bits of shifting, then mc_addr[4] will shift right the
540 * remaining number of bits. Thus 8 - bit_shift. The rest of the
541 * cases are a variation of this algorithm...essentially raising the
542 * number of bits to shift mc_addr[5] left, while still keeping the
543 * 8-bit shifting total.
545 * For example, given the following Destination MAC Address and an
546 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
547 * we can see that the bit_shift for case 0 is 4. These are the hash
548 * values resulting from each mc_filter_type...
549 * [0] [1] [2] [3] [4] [5]
553 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
554 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
555 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
556 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
558 switch (hw->mac.mc_filter_type) {
573 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
574 (((u16) mc_addr[5]) << bit_shift)));
580 * e1000_update_mc_addr_list_generic - Update Multicast addresses
581 * @hw: pointer to the HW structure
582 * @mc_addr_list: array of multicast addresses to program
583 * @mc_addr_count: number of multicast addresses to program
585 * Updates entire Multicast Table Array.
586 * The caller must have a packed mc_addr_list of multicast addresses.
588 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
589 u8 *mc_addr_list, u32 mc_addr_count)
591 u32 hash_value, hash_bit, hash_reg;
594 DEBUGFUNC("e1000_update_mc_addr_list_generic");
596 /* clear mta_shadow */
597 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
599 /* update mta_shadow from mc_addr_list */
600 for (i = 0; (u32) i < mc_addr_count; i++) {
601 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
603 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
604 hash_bit = hash_value & 0x1F;
606 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
607 mc_addr_list += (ETH_ADDR_LEN);
610 /* replace the entire MTA table */
611 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
612 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
613 E1000_WRITE_FLUSH(hw);
617 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
618 * @hw: pointer to the HW structure
620 * In certain situations, a system BIOS may report that the PCIx maximum
621 * memory read byte count (MMRBC) value is higher than than the actual
622 * value. We check the PCIx command register with the current PCIx status
625 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
629 u16 pcix_stat_hi_word;
632 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
634 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
635 if (hw->bus.type != e1000_bus_type_pcix)
638 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
639 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
640 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
641 PCIX_COMMAND_MMRBC_SHIFT;
642 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
643 PCIX_STATUS_HI_MMRBC_SHIFT;
644 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
645 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
646 if (cmd_mmrbc > stat_mmrbc) {
647 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
648 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
649 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
654 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
655 * @hw: pointer to the HW structure
657 * Clears the base hardware counters by reading the counter registers.
659 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
661 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
663 E1000_READ_REG(hw, E1000_CRCERRS);
664 E1000_READ_REG(hw, E1000_SYMERRS);
665 E1000_READ_REG(hw, E1000_MPC);
666 E1000_READ_REG(hw, E1000_SCC);
667 E1000_READ_REG(hw, E1000_ECOL);
668 E1000_READ_REG(hw, E1000_MCC);
669 E1000_READ_REG(hw, E1000_LATECOL);
670 E1000_READ_REG(hw, E1000_COLC);
671 E1000_READ_REG(hw, E1000_DC);
672 E1000_READ_REG(hw, E1000_SEC);
673 E1000_READ_REG(hw, E1000_RLEC);
674 E1000_READ_REG(hw, E1000_XONRXC);
675 E1000_READ_REG(hw, E1000_XONTXC);
676 E1000_READ_REG(hw, E1000_XOFFRXC);
677 E1000_READ_REG(hw, E1000_XOFFTXC);
678 E1000_READ_REG(hw, E1000_FCRUC);
679 E1000_READ_REG(hw, E1000_GPRC);
680 E1000_READ_REG(hw, E1000_BPRC);
681 E1000_READ_REG(hw, E1000_MPRC);
682 E1000_READ_REG(hw, E1000_GPTC);
683 E1000_READ_REG(hw, E1000_GORCL);
684 E1000_READ_REG(hw, E1000_GORCH);
685 E1000_READ_REG(hw, E1000_GOTCL);
686 E1000_READ_REG(hw, E1000_GOTCH);
687 E1000_READ_REG(hw, E1000_RNBC);
688 E1000_READ_REG(hw, E1000_RUC);
689 E1000_READ_REG(hw, E1000_RFC);
690 E1000_READ_REG(hw, E1000_ROC);
691 E1000_READ_REG(hw, E1000_RJC);
692 E1000_READ_REG(hw, E1000_TORL);
693 E1000_READ_REG(hw, E1000_TORH);
694 E1000_READ_REG(hw, E1000_TOTL);
695 E1000_READ_REG(hw, E1000_TOTH);
696 E1000_READ_REG(hw, E1000_TPR);
697 E1000_READ_REG(hw, E1000_TPT);
698 E1000_READ_REG(hw, E1000_MPTC);
699 E1000_READ_REG(hw, E1000_BPTC);
703 * e1000_check_for_copper_link_generic - Check for link (Copper)
704 * @hw: pointer to the HW structure
706 * Checks to see of the link status of the hardware has changed. If a
707 * change in link status has been detected, then we read the PHY registers
708 * to get the current speed/duplex if link exists.
710 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
712 struct e1000_mac_info *mac = &hw->mac;
716 DEBUGFUNC("e1000_check_for_copper_link");
718 /* We only want to go out to the PHY registers to see if Auto-Neg
719 * has completed and/or if our link status has changed. The
720 * get_link_status flag is set upon receiving a Link Status
721 * Change or Rx Sequence Error interrupt.
723 if (!mac->get_link_status)
724 return E1000_SUCCESS;
726 /* First we want to see if the MII Status Register reports
727 * link. If so, then we want to get the current speed/duplex
730 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
735 return E1000_SUCCESS; /* No link detected */
737 mac->get_link_status = FALSE;
739 /* Check if there was DownShift, must be checked
740 * immediately after link-up
742 e1000_check_downshift_generic(hw);
744 /* If we are forcing speed/duplex, then we simply return since
745 * we have already determined whether we have link or not.
748 return -E1000_ERR_CONFIG;
750 /* Auto-Neg is enabled. Auto Speed Detection takes care
751 * of MAC speed/duplex configuration. So we only need to
752 * configure Collision Distance in the MAC.
754 mac->ops.config_collision_dist(hw);
756 /* Configure Flow Control now that Auto-Neg has completed.
757 * First, we need to restore the desired flow control
758 * settings because we may have had to re-autoneg with a
759 * different link partner.
761 ret_val = e1000_config_fc_after_link_up_generic(hw);
763 DEBUGOUT("Error configuring flow control\n");
769 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
770 * @hw: pointer to the HW structure
772 * Checks for link up on the hardware. If link is not up and we have
773 * a signal, then we need to force link up.
775 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
777 struct e1000_mac_info *mac = &hw->mac;
783 DEBUGFUNC("e1000_check_for_fiber_link_generic");
785 ctrl = E1000_READ_REG(hw, E1000_CTRL);
786 status = E1000_READ_REG(hw, E1000_STATUS);
787 rxcw = E1000_READ_REG(hw, E1000_RXCW);
789 /* If we don't have link (auto-negotiation failed or link partner
790 * cannot auto-negotiate), the cable is plugged in (we have signal),
791 * and our link partner is not trying to auto-negotiate with us (we
792 * are receiving idles or data), we need to force link up. We also
793 * need to give auto-negotiation time to complete, in case the cable
794 * was just plugged in. The autoneg_failed flag does this.
796 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
797 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&
798 !(rxcw & E1000_RXCW_C)) {
799 if (!mac->autoneg_failed) {
800 mac->autoneg_failed = TRUE;
801 return E1000_SUCCESS;
803 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
805 /* Disable auto-negotiation in the TXCW register */
806 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
808 /* Force link-up and also force full-duplex. */
809 ctrl = E1000_READ_REG(hw, E1000_CTRL);
810 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
811 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
813 /* Configure Flow Control after forcing link up. */
814 ret_val = e1000_config_fc_after_link_up_generic(hw);
816 DEBUGOUT("Error configuring flow control\n");
819 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
820 /* If we are forcing link and we are receiving /C/ ordered
821 * sets, re-enable auto-negotiation in the TXCW register
822 * and disable forced link in the Device Control register
823 * in an attempt to auto-negotiate with our link partner.
825 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
826 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
827 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
829 mac->serdes_has_link = TRUE;
832 return E1000_SUCCESS;
836 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
837 * @hw: pointer to the HW structure
839 * Checks for link up on the hardware. If link is not up and we have
840 * a signal, then we need to force link up.
842 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
844 struct e1000_mac_info *mac = &hw->mac;
850 DEBUGFUNC("e1000_check_for_serdes_link_generic");
852 ctrl = E1000_READ_REG(hw, E1000_CTRL);
853 status = E1000_READ_REG(hw, E1000_STATUS);
854 rxcw = E1000_READ_REG(hw, E1000_RXCW);
856 /* If we don't have link (auto-negotiation failed or link partner
857 * cannot auto-negotiate), and our link partner is not trying to
858 * auto-negotiate with us (we are receiving idles or data),
859 * we need to force link up. We also need to give auto-negotiation
862 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
863 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {
864 if (!mac->autoneg_failed) {
865 mac->autoneg_failed = TRUE;
866 return E1000_SUCCESS;
868 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
870 /* Disable auto-negotiation in the TXCW register */
871 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
873 /* Force link-up and also force full-duplex. */
874 ctrl = E1000_READ_REG(hw, E1000_CTRL);
875 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
876 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
878 /* Configure Flow Control after forcing link up. */
879 ret_val = e1000_config_fc_after_link_up_generic(hw);
881 DEBUGOUT("Error configuring flow control\n");
884 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
885 /* If we are forcing link and we are receiving /C/ ordered
886 * sets, re-enable auto-negotiation in the TXCW register
887 * and disable forced link in the Device Control register
888 * in an attempt to auto-negotiate with our link partner.
890 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
891 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
892 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
894 mac->serdes_has_link = TRUE;
895 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
896 /* If we force link for non-auto-negotiation switch, check
897 * link status based on MAC synchronization for internal
900 /* SYNCH bit and IV bit are sticky. */
902 rxcw = E1000_READ_REG(hw, E1000_RXCW);
903 if (rxcw & E1000_RXCW_SYNCH) {
904 if (!(rxcw & E1000_RXCW_IV)) {
905 mac->serdes_has_link = TRUE;
906 DEBUGOUT("SERDES: Link up - forced.\n");
909 mac->serdes_has_link = FALSE;
910 DEBUGOUT("SERDES: Link down - force failed.\n");
914 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
915 status = E1000_READ_REG(hw, E1000_STATUS);
916 if (status & E1000_STATUS_LU) {
917 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
919 rxcw = E1000_READ_REG(hw, E1000_RXCW);
920 if (rxcw & E1000_RXCW_SYNCH) {
921 if (!(rxcw & E1000_RXCW_IV)) {
922 mac->serdes_has_link = TRUE;
923 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n");
925 mac->serdes_has_link = FALSE;
926 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n");
929 mac->serdes_has_link = FALSE;
930 DEBUGOUT("SERDES: Link down - no sync.\n");
933 mac->serdes_has_link = FALSE;
934 DEBUGOUT("SERDES: Link down - autoneg failed\n");
938 return E1000_SUCCESS;
942 * e1000_set_default_fc_generic - Set flow control default values
943 * @hw: pointer to the HW structure
945 * Read the EEPROM for the default values for flow control and store the
948 s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
954 DEBUGFUNC("e1000_set_default_fc_generic");
956 /* Read and store word 0x0F of the EEPROM. This word contains bits
957 * that determine the hardware's default PAUSE (flow control) mode,
958 * a bit that determines whether the HW defaults to enabling or
959 * disabling auto-negotiation, and the direction of the
960 * SW defined pins. If there is no SW over-ride of the flow
961 * control setting, then the variable hw->fc will
962 * be initialized based on a value in the EEPROM.
964 if (hw->mac.type == e1000_i350) {
965 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func);
966 ret_val = hw->nvm.ops.read(hw,
967 NVM_INIT_CONTROL2_REG +
971 ret_val = hw->nvm.ops.read(hw,
972 NVM_INIT_CONTROL2_REG,
978 DEBUGOUT("NVM Read Error\n");
982 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK))
983 hw->fc.requested_mode = e1000_fc_none;
984 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
986 hw->fc.requested_mode = e1000_fc_tx_pause;
988 hw->fc.requested_mode = e1000_fc_full;
990 return E1000_SUCCESS;
994 * e1000_setup_link_generic - Setup flow control and link settings
995 * @hw: pointer to the HW structure
997 * Determines which flow control settings to use, then configures flow
998 * control. Calls the appropriate media-specific link configuration
999 * function. Assuming the adapter has a valid link partner, a valid link
1000 * should be established. Assumes the hardware has previously been reset
1001 * and the transmitter and receiver are not enabled.
1003 s32 e1000_setup_link_generic(struct e1000_hw *hw)
1007 DEBUGFUNC("e1000_setup_link_generic");
1009 /* In the case of the phy reset being blocked, we already have a link.
1010 * We do not need to set it up again.
1012 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
1013 return E1000_SUCCESS;
1015 /* If requested flow control is set to default, set flow control
1016 * based on the EEPROM flow control settings.
1018 if (hw->fc.requested_mode == e1000_fc_default) {
1019 ret_val = e1000_set_default_fc_generic(hw);
1024 /* Save off the requested flow control mode for use later. Depending
1025 * on the link partner's capabilities, we may or may not use this mode.
1027 hw->fc.current_mode = hw->fc.requested_mode;
1029 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
1030 hw->fc.current_mode);
1032 /* Call the necessary media_type subroutine to configure the link. */
1033 ret_val = hw->mac.ops.setup_physical_interface(hw);
1037 /* Initialize the flow control address, type, and PAUSE timer
1038 * registers to their default values. This is done even if flow
1039 * control is disabled, because it does not hurt anything to
1040 * initialize these registers.
1042 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1043 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
1044 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1045 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1047 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1049 return e1000_set_fc_watermarks_generic(hw);
1053 * e1000_commit_fc_settings_generic - Configure flow control
1054 * @hw: pointer to the HW structure
1056 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1057 * base on the flow control settings in e1000_mac_info.
1059 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1061 struct e1000_mac_info *mac = &hw->mac;
1064 DEBUGFUNC("e1000_commit_fc_settings_generic");
1066 /* Check for a software override of the flow control settings, and
1067 * setup the device accordingly. If auto-negotiation is enabled, then
1068 * software will have to set the "PAUSE" bits to the correct value in
1069 * the Transmit Config Word Register (TXCW) and re-start auto-
1070 * negotiation. However, if auto-negotiation is disabled, then
1071 * software will have to manually configure the two flow control enable
1072 * bits in the CTRL register.
1074 * The possible values of the "fc" parameter are:
1075 * 0: Flow control is completely disabled
1076 * 1: Rx flow control is enabled (we can receive pause frames,
1077 * but not send pause frames).
1078 * 2: Tx flow control is enabled (we can send pause frames but we
1079 * do not support receiving pause frames).
1080 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1082 switch (hw->fc.current_mode) {
1084 /* Flow control completely disabled by a software over-ride. */
1085 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1087 case e1000_fc_rx_pause:
1088 /* Rx Flow control is enabled and Tx Flow control is disabled
1089 * by a software over-ride. Since there really isn't a way to
1090 * advertise that we are capable of Rx Pause ONLY, we will
1091 * advertise that we support both symmetric and asymmetric Rx
1092 * PAUSE. Later, we will disable the adapter's ability to send
1095 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1097 case e1000_fc_tx_pause:
1098 /* Tx Flow control is enabled, and Rx Flow control is disabled,
1099 * by a software over-ride.
1101 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1104 /* Flow control (both Rx and Tx) is enabled by a software
1107 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1110 DEBUGOUT("Flow control param set incorrectly\n");
1111 return -E1000_ERR_CONFIG;
1115 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1118 return E1000_SUCCESS;
1122 * e1000_poll_fiber_serdes_link_generic - Poll for link up
1123 * @hw: pointer to the HW structure
1125 * Polls for link up by reading the status register, if link fails to come
1126 * up with auto-negotiation, then the link is forced if a signal is detected.
1128 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1130 struct e1000_mac_info *mac = &hw->mac;
1134 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1136 /* If we have a signal (the cable is plugged in, or assumed TRUE for
1137 * serdes media) then poll for a "Link-Up" indication in the Device
1138 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1139 * seconds (Auto-negotiation should complete in less than 500
1140 * milliseconds even if the other end is doing it in SW).
1142 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1144 status = E1000_READ_REG(hw, E1000_STATUS);
1145 if (status & E1000_STATUS_LU)
1148 if (i == FIBER_LINK_UP_LIMIT) {
1149 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1150 mac->autoneg_failed = TRUE;
1151 /* AutoNeg failed to achieve a link, so we'll call
1152 * mac->check_for_link. This routine will force the
1153 * link up if we detect a signal. This will allow us to
1154 * communicate with non-autonegotiating link partners.
1156 ret_val = mac->ops.check_for_link(hw);
1158 DEBUGOUT("Error while checking for link\n");
1161 mac->autoneg_failed = FALSE;
1163 mac->autoneg_failed = FALSE;
1164 DEBUGOUT("Valid Link Found\n");
1167 return E1000_SUCCESS;
1171 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1172 * @hw: pointer to the HW structure
1174 * Configures collision distance and flow control for fiber and serdes
1175 * links. Upon successful setup, poll for link.
1177 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1182 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1184 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1186 /* Take the link out of reset */
1187 ctrl &= ~E1000_CTRL_LRST;
1189 hw->mac.ops.config_collision_dist(hw);
1191 ret_val = e1000_commit_fc_settings_generic(hw);
1195 /* Since auto-negotiation is enabled, take the link out of reset (the
1196 * link will be in reset, because we previously reset the chip). This
1197 * will restart auto-negotiation. If auto-negotiation is successful
1198 * then the link-up status bit will be set and the flow control enable
1199 * bits (RFCE and TFCE) will be set according to their negotiated value.
1201 DEBUGOUT("Auto-negotiation enabled\n");
1203 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1204 E1000_WRITE_FLUSH(hw);
1207 /* For these adapters, the SW definable pin 1 is set when the optics
1208 * detect a signal. If we have a signal, then poll for a "Link-Up"
1211 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1212 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1213 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1215 DEBUGOUT("No signal detected\n");
1222 * e1000_config_collision_dist_generic - Configure collision distance
1223 * @hw: pointer to the HW structure
1225 * Configures the collision distance to the default value and is used
1226 * during link setup.
1228 static void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1232 DEBUGFUNC("e1000_config_collision_dist_generic");
1234 tctl = E1000_READ_REG(hw, E1000_TCTL);
1236 tctl &= ~E1000_TCTL_COLD;
1237 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1239 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1240 E1000_WRITE_FLUSH(hw);
1244 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1245 * @hw: pointer to the HW structure
1247 * Sets the flow control high/low threshold (watermark) registers. If
1248 * flow control XON frame transmission is enabled, then set XON frame
1249 * transmission as well.
1251 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1253 u32 fcrtl = 0, fcrth = 0;
1255 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1257 /* Set the flow control receive threshold registers. Normally,
1258 * these registers will be set to a default threshold that may be
1259 * adjusted later by the driver's runtime code. However, if the
1260 * ability to transmit pause frames is not enabled, then these
1261 * registers will be set to 0.
1263 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1264 /* We need to set up the Receive Threshold high and low water
1265 * marks as well as (optionally) enabling the transmission of
1268 fcrtl = hw->fc.low_water;
1269 if (hw->fc.send_xon)
1270 fcrtl |= E1000_FCRTL_XONE;
1272 fcrth = hw->fc.high_water;
1274 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1275 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1277 return E1000_SUCCESS;
1281 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1282 * @hw: pointer to the HW structure
1284 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1285 * device control register to reflect the adapter settings. TFCE and RFCE
1286 * need to be explicitly set by software when a copper PHY is used because
1287 * autonegotiation is managed by the PHY rather than the MAC. Software must
1288 * also configure these bits when link is forced on a fiber connection.
1290 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1294 DEBUGFUNC("e1000_force_mac_fc_generic");
1296 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1298 /* Because we didn't get link via the internal auto-negotiation
1299 * mechanism (we either forced link or we got link via PHY
1300 * auto-neg), we have to manually enable/disable transmit an
1301 * receive flow control.
1303 * The "Case" statement below enables/disable flow control
1304 * according to the "hw->fc.current_mode" parameter.
1306 * The possible values of the "fc" parameter are:
1307 * 0: Flow control is completely disabled
1308 * 1: Rx flow control is enabled (we can receive pause
1309 * frames but not send pause frames).
1310 * 2: Tx flow control is enabled (we can send pause frames
1311 * frames but we do not receive pause frames).
1312 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1313 * other: No other values should be possible at this point.
1315 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1317 switch (hw->fc.current_mode) {
1319 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1321 case e1000_fc_rx_pause:
1322 ctrl &= (~E1000_CTRL_TFCE);
1323 ctrl |= E1000_CTRL_RFCE;
1325 case e1000_fc_tx_pause:
1326 ctrl &= (~E1000_CTRL_RFCE);
1327 ctrl |= E1000_CTRL_TFCE;
1330 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1333 DEBUGOUT("Flow control param set incorrectly\n");
1334 return -E1000_ERR_CONFIG;
1337 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1339 return E1000_SUCCESS;
1343 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1344 * @hw: pointer to the HW structure
1346 * Checks the status of auto-negotiation after link up to ensure that the
1347 * speed and duplex were not forced. If the link needed to be forced, then
1348 * flow control needs to be forced also. If auto-negotiation is enabled
1349 * and did not fail, then we configure flow control based on our link
1352 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1354 struct e1000_mac_info *mac = &hw->mac;
1355 s32 ret_val = E1000_SUCCESS;
1356 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
1357 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1360 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1362 /* Check for the case where we have fiber media and auto-neg failed
1363 * so we had to force link. In this case, we need to force the
1364 * configuration of the MAC to match the "fc" parameter.
1366 if (mac->autoneg_failed) {
1367 if (hw->phy.media_type == e1000_media_type_fiber ||
1368 hw->phy.media_type == e1000_media_type_internal_serdes)
1369 ret_val = e1000_force_mac_fc_generic(hw);
1371 if (hw->phy.media_type == e1000_media_type_copper)
1372 ret_val = e1000_force_mac_fc_generic(hw);
1376 DEBUGOUT("Error forcing flow control settings\n");
1380 /* Check for the case where we have copper media and auto-neg is
1381 * enabled. In this case, we need to check and see if Auto-Neg
1382 * has completed, and if so, how the PHY and link partner has
1383 * flow control configured.
1385 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1386 /* Read the MII Status Register and check to see if AutoNeg
1387 * has completed. We read this twice because this reg has
1388 * some "sticky" (latched) bits.
1390 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1393 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1397 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1398 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1402 /* The AutoNeg process has completed, so we now need to
1403 * read both the Auto Negotiation Advertisement
1404 * Register (Address 4) and the Auto_Negotiation Base
1405 * Page Ability Register (Address 5) to determine how
1406 * flow control was negotiated.
1408 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1412 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1413 &mii_nway_lp_ability_reg);
1417 /* Two bits in the Auto Negotiation Advertisement Register
1418 * (Address 4) and two bits in the Auto Negotiation Base
1419 * Page Ability Register (Address 5) determine flow control
1420 * for both the PHY and the link partner. The following
1421 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1422 * 1999, describes these PAUSE resolution bits and how flow
1423 * control is determined based upon these settings.
1424 * NOTE: DC = Don't Care
1426 * LOCAL DEVICE | LINK PARTNER
1427 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1428 *-------|---------|-------|---------|--------------------
1429 * 0 | 0 | DC | DC | e1000_fc_none
1430 * 0 | 1 | 0 | DC | e1000_fc_none
1431 * 0 | 1 | 1 | 0 | e1000_fc_none
1432 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1433 * 1 | 0 | 0 | DC | e1000_fc_none
1434 * 1 | DC | 1 | DC | e1000_fc_full
1435 * 1 | 1 | 0 | 0 | e1000_fc_none
1436 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1438 * Are both PAUSE bits set to 1? If so, this implies
1439 * Symmetric Flow Control is enabled at both ends. The
1440 * ASM_DIR bits are irrelevant per the spec.
1442 * For Symmetric Flow Control:
1444 * LOCAL DEVICE | LINK PARTNER
1445 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1446 *-------|---------|-------|---------|--------------------
1447 * 1 | DC | 1 | DC | E1000_fc_full
1450 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1451 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1452 /* Now we need to check if the user selected Rx ONLY
1453 * of pause frames. In this case, we had to advertise
1454 * FULL flow control because we could not advertise Rx
1455 * ONLY. Hence, we must now check to see if we need to
1456 * turn OFF the TRANSMISSION of PAUSE frames.
1458 if (hw->fc.requested_mode == e1000_fc_full) {
1459 hw->fc.current_mode = e1000_fc_full;
1460 DEBUGOUT("Flow Control = FULL.\n");
1462 hw->fc.current_mode = e1000_fc_rx_pause;
1463 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1466 /* For receiving PAUSE frames ONLY.
1468 * LOCAL DEVICE | LINK PARTNER
1469 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1470 *-------|---------|-------|---------|--------------------
1471 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1473 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1474 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1475 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1476 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1477 hw->fc.current_mode = e1000_fc_tx_pause;
1478 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1480 /* For transmitting PAUSE frames ONLY.
1482 * LOCAL DEVICE | LINK PARTNER
1483 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1484 *-------|---------|-------|---------|--------------------
1485 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1487 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1488 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1489 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1490 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1491 hw->fc.current_mode = e1000_fc_rx_pause;
1492 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1494 /* Per the IEEE spec, at this point flow control
1495 * should be disabled.
1497 hw->fc.current_mode = e1000_fc_none;
1498 DEBUGOUT("Flow Control = NONE.\n");
1501 /* Now we need to do one last check... If we auto-
1502 * negotiated to HALF DUPLEX, flow control should not be
1503 * enabled per IEEE 802.3 spec.
1505 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1507 DEBUGOUT("Error getting link speed and duplex\n");
1511 if (duplex == HALF_DUPLEX)
1512 hw->fc.current_mode = e1000_fc_none;
1514 /* Now we call a subroutine to actually force the MAC
1515 * controller to use the correct flow control settings.
1517 ret_val = e1000_force_mac_fc_generic(hw);
1519 DEBUGOUT("Error forcing flow control settings\n");
1524 /* Check for the case where we have SerDes media and auto-neg is
1525 * enabled. In this case, we need to check and see if Auto-Neg
1526 * has completed, and if so, how the PHY and link partner has
1527 * flow control configured.
1529 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
1531 /* Read the PCS_LSTS and check to see if AutoNeg
1534 pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1536 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
1537 DEBUGOUT("PCS Auto Neg has not completed.\n");
1541 /* The AutoNeg process has completed, so we now need to
1542 * read both the Auto Negotiation Advertisement
1543 * Register (PCS_ANADV) and the Auto_Negotiation Base
1544 * Page Ability Register (PCS_LPAB) to determine how
1545 * flow control was negotiated.
1547 pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1548 pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB);
1550 /* Two bits in the Auto Negotiation Advertisement Register
1551 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1552 * Page Ability Register (PCS_LPAB) determine flow control
1553 * for both the PHY and the link partner. The following
1554 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1555 * 1999, describes these PAUSE resolution bits and how flow
1556 * control is determined based upon these settings.
1557 * NOTE: DC = Don't Care
1559 * LOCAL DEVICE | LINK PARTNER
1560 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1561 *-------|---------|-------|---------|--------------------
1562 * 0 | 0 | DC | DC | e1000_fc_none
1563 * 0 | 1 | 0 | DC | e1000_fc_none
1564 * 0 | 1 | 1 | 0 | e1000_fc_none
1565 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1566 * 1 | 0 | 0 | DC | e1000_fc_none
1567 * 1 | DC | 1 | DC | e1000_fc_full
1568 * 1 | 1 | 0 | 0 | e1000_fc_none
1569 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1571 * Are both PAUSE bits set to 1? If so, this implies
1572 * Symmetric Flow Control is enabled at both ends. The
1573 * ASM_DIR bits are irrelevant per the spec.
1575 * For Symmetric Flow Control:
1577 * LOCAL DEVICE | LINK PARTNER
1578 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1579 *-------|---------|-------|---------|--------------------
1580 * 1 | DC | 1 | DC | e1000_fc_full
1583 if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1584 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
1585 /* Now we need to check if the user selected Rx ONLY
1586 * of pause frames. In this case, we had to advertise
1587 * FULL flow control because we could not advertise Rx
1588 * ONLY. Hence, we must now check to see if we need to
1589 * turn OFF the TRANSMISSION of PAUSE frames.
1591 if (hw->fc.requested_mode == e1000_fc_full) {
1592 hw->fc.current_mode = e1000_fc_full;
1593 DEBUGOUT("Flow Control = FULL.\n");
1595 hw->fc.current_mode = e1000_fc_rx_pause;
1596 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1599 /* For receiving PAUSE frames ONLY.
1601 * LOCAL DEVICE | LINK PARTNER
1602 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1603 *-------|---------|-------|---------|--------------------
1604 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1606 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
1607 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1608 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1609 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1610 hw->fc.current_mode = e1000_fc_tx_pause;
1611 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1613 /* For transmitting PAUSE frames ONLY.
1615 * LOCAL DEVICE | LINK PARTNER
1616 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1617 *-------|---------|-------|---------|--------------------
1618 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1620 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1621 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1622 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1623 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1624 hw->fc.current_mode = e1000_fc_rx_pause;
1625 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1627 /* Per the IEEE spec, at this point flow control
1628 * should be disabled.
1630 hw->fc.current_mode = e1000_fc_none;
1631 DEBUGOUT("Flow Control = NONE.\n");
1634 /* Now we call a subroutine to actually force the MAC
1635 * controller to use the correct flow control settings.
1637 pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1638 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1639 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg);
1641 ret_val = e1000_force_mac_fc_generic(hw);
1643 DEBUGOUT("Error forcing flow control settings\n");
1648 return E1000_SUCCESS;
1652 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1653 * @hw: pointer to the HW structure
1654 * @speed: stores the current speed
1655 * @duplex: stores the current duplex
1657 * Read the status register for the current speed/duplex and store the current
1658 * speed and duplex for copper connections.
1660 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1665 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1667 status = E1000_READ_REG(hw, E1000_STATUS);
1668 if (status & E1000_STATUS_SPEED_1000) {
1669 *speed = SPEED_1000;
1670 DEBUGOUT("1000 Mbs, ");
1671 } else if (status & E1000_STATUS_SPEED_100) {
1673 DEBUGOUT("100 Mbs, ");
1676 DEBUGOUT("10 Mbs, ");
1679 if (status & E1000_STATUS_FD) {
1680 *duplex = FULL_DUPLEX;
1681 DEBUGOUT("Full Duplex\n");
1683 *duplex = HALF_DUPLEX;
1684 DEBUGOUT("Half Duplex\n");
1687 return E1000_SUCCESS;
1691 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1692 * @hw: pointer to the HW structure
1693 * @speed: stores the current speed
1694 * @duplex: stores the current duplex
1696 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1697 * for fiber/serdes links.
1699 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw,
1700 u16 *speed, u16 *duplex)
1702 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1704 *speed = SPEED_1000;
1705 *duplex = FULL_DUPLEX;
1707 return E1000_SUCCESS;
1711 * e1000_get_auto_rd_done_generic - Check for auto read completion
1712 * @hw: pointer to the HW structure
1714 * Check EEPROM for Auto Read done bit.
1716 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1720 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1722 while (i < AUTO_READ_DONE_TIMEOUT) {
1723 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1729 if (i == AUTO_READ_DONE_TIMEOUT) {
1730 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1731 return -E1000_ERR_RESET;
1734 return E1000_SUCCESS;
1738 * e1000_valid_led_default_generic - Verify a valid default LED config
1739 * @hw: pointer to the HW structure
1740 * @data: pointer to the NVM (EEPROM)
1742 * Read the EEPROM for the current default LED configuration. If the
1743 * LED configuration is not valid, set to a valid LED configuration.
1745 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1749 DEBUGFUNC("e1000_valid_led_default_generic");
1751 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1753 DEBUGOUT("NVM Read Error\n");
1757 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1758 *data = ID_LED_DEFAULT;
1760 return E1000_SUCCESS;
1764 * e1000_id_led_init_generic -
1765 * @hw: pointer to the HW structure
1768 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1770 struct e1000_mac_info *mac = &hw->mac;
1772 const u32 ledctl_mask = 0x000000FF;
1773 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1774 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1776 const u16 led_mask = 0x0F;
1778 DEBUGFUNC("e1000_id_led_init_generic");
1780 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1784 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1785 mac->ledctl_mode1 = mac->ledctl_default;
1786 mac->ledctl_mode2 = mac->ledctl_default;
1788 for (i = 0; i < 4; i++) {
1789 temp = (data >> (i << 2)) & led_mask;
1791 case ID_LED_ON1_DEF2:
1792 case ID_LED_ON1_ON2:
1793 case ID_LED_ON1_OFF2:
1794 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1795 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1797 case ID_LED_OFF1_DEF2:
1798 case ID_LED_OFF1_ON2:
1799 case ID_LED_OFF1_OFF2:
1800 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1801 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1808 case ID_LED_DEF1_ON2:
1809 case ID_LED_ON1_ON2:
1810 case ID_LED_OFF1_ON2:
1811 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1812 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1814 case ID_LED_DEF1_OFF2:
1815 case ID_LED_ON1_OFF2:
1816 case ID_LED_OFF1_OFF2:
1817 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1818 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1826 return E1000_SUCCESS;
1830 * e1000_setup_led_generic - Configures SW controllable LED
1831 * @hw: pointer to the HW structure
1833 * This prepares the SW controllable LED for use and saves the current state
1834 * of the LED so it can be later restored.
1836 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1840 DEBUGFUNC("e1000_setup_led_generic");
1842 if (hw->mac.ops.setup_led != e1000_setup_led_generic)
1843 return -E1000_ERR_CONFIG;
1845 if (hw->phy.media_type == e1000_media_type_fiber) {
1846 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1847 hw->mac.ledctl_default = ledctl;
1849 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1850 E1000_LEDCTL_LED0_MODE_MASK);
1851 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1852 E1000_LEDCTL_LED0_MODE_SHIFT);
1853 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1854 } else if (hw->phy.media_type == e1000_media_type_copper) {
1855 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1858 return E1000_SUCCESS;
1862 * e1000_cleanup_led_generic - Set LED config to default operation
1863 * @hw: pointer to the HW structure
1865 * Remove the current LED configuration and set the LED configuration
1866 * to the default value, saved from the EEPROM.
1868 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1870 DEBUGFUNC("e1000_cleanup_led_generic");
1872 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1873 return E1000_SUCCESS;
1877 * e1000_blink_led_generic - Blink LED
1878 * @hw: pointer to the HW structure
1880 * Blink the LEDs which are set to be on.
1882 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1884 u32 ledctl_blink = 0;
1887 DEBUGFUNC("e1000_blink_led_generic");
1889 if (hw->phy.media_type == e1000_media_type_fiber) {
1890 /* always blink LED0 for PCI-E fiber */
1891 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1892 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1894 /* Set the blink bit for each LED that's "on" (0x0E)
1895 * (or "off" if inverted) in ledctl_mode2. The blink
1896 * logic in hardware only works when mode is set to "on"
1897 * so it must be changed accordingly when the mode is
1898 * "off" and inverted.
1900 ledctl_blink = hw->mac.ledctl_mode2;
1901 for (i = 0; i < 32; i += 8) {
1902 u32 mode = (hw->mac.ledctl_mode2 >> i) &
1903 E1000_LEDCTL_LED0_MODE_MASK;
1904 u32 led_default = hw->mac.ledctl_default >> i;
1906 if ((!(led_default & E1000_LEDCTL_LED0_IVRT) &&
1907 (mode == E1000_LEDCTL_MODE_LED_ON)) ||
1908 ((led_default & E1000_LEDCTL_LED0_IVRT) &&
1909 (mode == E1000_LEDCTL_MODE_LED_OFF))) {
1911 ~(E1000_LEDCTL_LED0_MODE_MASK << i);
1912 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK |
1913 E1000_LEDCTL_MODE_LED_ON) << i;
1918 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1920 return E1000_SUCCESS;
1924 * e1000_led_on_generic - Turn LED on
1925 * @hw: pointer to the HW structure
1929 s32 e1000_led_on_generic(struct e1000_hw *hw)
1933 DEBUGFUNC("e1000_led_on_generic");
1935 switch (hw->phy.media_type) {
1936 case e1000_media_type_fiber:
1937 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1938 ctrl &= ~E1000_CTRL_SWDPIN0;
1939 ctrl |= E1000_CTRL_SWDPIO0;
1940 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1942 case e1000_media_type_copper:
1943 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
1949 return E1000_SUCCESS;
1953 * e1000_led_off_generic - Turn LED off
1954 * @hw: pointer to the HW structure
1958 s32 e1000_led_off_generic(struct e1000_hw *hw)
1962 DEBUGFUNC("e1000_led_off_generic");
1964 switch (hw->phy.media_type) {
1965 case e1000_media_type_fiber:
1966 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1967 ctrl |= E1000_CTRL_SWDPIN0;
1968 ctrl |= E1000_CTRL_SWDPIO0;
1969 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1971 case e1000_media_type_copper:
1972 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1978 return E1000_SUCCESS;
1982 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
1983 * @hw: pointer to the HW structure
1984 * @no_snoop: bitmap of snoop events
1986 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1988 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
1992 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
1994 if (hw->bus.type != e1000_bus_type_pci_express)
1998 gcr = E1000_READ_REG(hw, E1000_GCR);
1999 gcr &= ~(PCIE_NO_SNOOP_ALL);
2001 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2006 * e1000_disable_pcie_master_generic - Disables PCI-express master access
2007 * @hw: pointer to the HW structure
2009 * Returns E1000_SUCCESS if successful, else returns -10
2010 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
2011 * the master requests to be disabled.
2013 * Disables PCI-Express master access and verifies there are no pending
2016 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
2019 s32 timeout = MASTER_DISABLE_TIMEOUT;
2021 DEBUGFUNC("e1000_disable_pcie_master_generic");
2023 if (hw->bus.type != e1000_bus_type_pci_express)
2024 return E1000_SUCCESS;
2026 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2027 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
2028 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2031 if (!(E1000_READ_REG(hw, E1000_STATUS) &
2032 E1000_STATUS_GIO_MASTER_ENABLE) ||
2033 E1000_REMOVED(hw->hw_addr))
2040 DEBUGOUT("Master requests are pending.\n");
2041 return -E1000_ERR_MASTER_REQUESTS_PENDING;
2044 return E1000_SUCCESS;
2048 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
2049 * @hw: pointer to the HW structure
2051 * Reset the Adaptive Interframe Spacing throttle to default values.
2053 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2055 struct e1000_mac_info *mac = &hw->mac;
2057 DEBUGFUNC("e1000_reset_adaptive_generic");
2059 if (!mac->adaptive_ifs) {
2060 DEBUGOUT("Not in Adaptive IFS mode!\n");
2064 mac->current_ifs_val = 0;
2065 mac->ifs_min_val = IFS_MIN;
2066 mac->ifs_max_val = IFS_MAX;
2067 mac->ifs_step_size = IFS_STEP;
2068 mac->ifs_ratio = IFS_RATIO;
2070 mac->in_ifs_mode = FALSE;
2071 E1000_WRITE_REG(hw, E1000_AIT, 0);
2075 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2076 * @hw: pointer to the HW structure
2078 * Update the Adaptive Interframe Spacing Throttle value based on the
2079 * time between transmitted packets and time between collisions.
2081 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2083 struct e1000_mac_info *mac = &hw->mac;
2085 DEBUGFUNC("e1000_update_adaptive_generic");
2087 if (!mac->adaptive_ifs) {
2088 DEBUGOUT("Not in Adaptive IFS mode!\n");
2092 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2093 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2094 mac->in_ifs_mode = TRUE;
2095 if (mac->current_ifs_val < mac->ifs_max_val) {
2096 if (!mac->current_ifs_val)
2097 mac->current_ifs_val = mac->ifs_min_val;
2099 mac->current_ifs_val +=
2101 E1000_WRITE_REG(hw, E1000_AIT,
2102 mac->current_ifs_val);
2106 if (mac->in_ifs_mode &&
2107 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2108 mac->current_ifs_val = 0;
2109 mac->in_ifs_mode = FALSE;
2110 E1000_WRITE_REG(hw, E1000_AIT, 0);
2116 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2117 * @hw: pointer to the HW structure
2119 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2120 * set, which is forced to MDI mode only.
2122 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2124 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2126 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2127 DEBUGOUT("Invalid MDI setting detected\n");
2129 return -E1000_ERR_CONFIG;
2132 return E1000_SUCCESS;
2136 * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings
2137 * @hw: pointer to the HW structure
2139 * Validate the MDI/MDIx setting, allowing for auto-crossover during forced
2142 s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2144 DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic");
2146 return E1000_SUCCESS;
2150 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
2151 * @hw: pointer to the HW structure
2152 * @reg: 32bit register offset such as E1000_SCTL
2153 * @offset: register offset to write to
2154 * @data: data to write at register offset
2156 * Writes an address/data control type register. There are several of these
2157 * and they all have the format address << 8 | data and bit 31 is polled for
2160 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2161 u32 offset, u8 data)
2163 u32 i, regvalue = 0;
2165 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2167 /* Set up the address and data */
2168 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
2169 E1000_WRITE_REG(hw, reg, regvalue);
2171 /* Poll the ready bit to see if the MDI read completed */
2172 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
2174 regvalue = E1000_READ_REG(hw, reg);
2175 if (regvalue & E1000_GEN_CTL_READY)
2178 if (!(regvalue & E1000_GEN_CTL_READY)) {
2179 DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
2180 return -E1000_ERR_PHY;
2183 return E1000_SUCCESS;
2187 * e1000_get_hw_semaphore - Acquire hardware semaphore
2188 * @hw: pointer to the HW structure
2190 * Acquire the HW semaphore to access the PHY or NVM
2192 s32 e1000_get_hw_semaphore(struct e1000_hw *hw)
2195 s32 fw_timeout = hw->nvm.word_size + 1;
2196 s32 sw_timeout = hw->nvm.word_size + 1;
2199 DEBUGFUNC("e1000_get_hw_semaphore");
2202 /* If we have timedout 3 times on trying to acquire
2203 * the inter-port SMBI semaphore, there is old code
2204 * operating on the other port, and it is not
2205 * releasing SMBI. Modify the number of times that
2206 * we try for the semaphore to interwork with this
2209 if (hw->dev_spec._82571.smb_counter > 2)
2213 /* Get the SW semaphore */
2214 while (i < sw_timeout) {
2215 swsm = E1000_READ_REG(hw, E1000_SWSM);
2216 if (!(swsm & E1000_SWSM_SMBI))
2223 if (i == sw_timeout) {
2224 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
2225 hw->dev_spec._82571.smb_counter++;
2228 /* In rare circumstances, the SW semaphore may already be held
2229 * unintentionally. Clear the semaphore once before giving up.
2231 if (hw->dev_spec._82575.clear_semaphore_once) {
2232 hw->dev_spec._82575.clear_semaphore_once = FALSE;
2233 e1000_put_hw_semaphore(hw);
2234 for (i = 0; i < fw_timeout; i++) {
2235 swsm = E1000_READ_REG(hw, E1000_SWSM);
2236 if (!(swsm & E1000_SWSM_SMBI))
2243 /* Get the FW semaphore. */
2244 for (i = 0; i < fw_timeout; i++) {
2245 swsm = E1000_READ_REG(hw, E1000_SWSM);
2246 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
2248 /* Semaphore acquired if bit latched */
2249 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
2255 if (i == fw_timeout) {
2256 /* Release semaphores */
2257 e1000_put_hw_semaphore(hw);
2258 DEBUGOUT("Driver can't access the NVM\n");
2259 return -E1000_ERR_NVM;
2262 return E1000_SUCCESS;
2266 * e1000_put_hw_semaphore - Release hardware semaphore
2267 * @hw: pointer to the HW structure
2269 * Release hardware semaphore used to access the PHY or NVM
2271 void e1000_put_hw_semaphore(struct e1000_hw *hw)
2275 DEBUGFUNC("e1000_put_hw_semaphore");
2277 swsm = E1000_READ_REG(hw, E1000_SWSM);
2279 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
2281 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
2286 * e1000_acquire_swfw_sync - Acquire SW/FW semaphore
2287 * @hw: pointer to the HW structure
2288 * @mask: specifies which semaphore to acquire
2290 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
2291 * will also specify which port we're acquiring the lock for.
2294 e1000_acquire_swfw_sync(struct e1000_hw *hw, u16 mask)
2298 u32 fwmask = mask << 16;
2299 s32 ret_val = E1000_SUCCESS;
2300 s32 i = 0, timeout = 200;
2302 DEBUGFUNC("e1000_acquire_swfw_sync");
2304 while (i < timeout) {
2305 if (e1000_get_hw_semaphore(hw)) {
2306 ret_val = -E1000_ERR_SWFW_SYNC;
2310 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
2311 if (!(swfw_sync & (fwmask | swmask)))
2315 * Firmware currently using resource (fwmask)
2316 * or other software thread using resource (swmask)
2318 e1000_put_hw_semaphore(hw);
2324 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
2325 ret_val = -E1000_ERR_SWFW_SYNC;
2329 swfw_sync |= swmask;
2330 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
2332 e1000_put_hw_semaphore(hw);
2339 * e1000_release_swfw_sync - Release SW/FW semaphore
2340 * @hw: pointer to the HW structure
2341 * @mask: specifies which semaphore to acquire
2343 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
2344 * will also specify which port we're releasing the lock for.
2347 e1000_release_swfw_sync(struct e1000_hw *hw, u16 mask)
2351 DEBUGFUNC("e1000_release_swfw_sync");
2353 while (e1000_get_hw_semaphore(hw) != E1000_SUCCESS)
2356 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
2358 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
2360 e1000_put_hw_semaphore(hw);