1 /******************************************************************************
3 Copyright (c) 2001-2011, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
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32 ******************************************************************************/
35 #include "e1000_api.h"
37 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
38 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
41 * e1000_init_mac_ops_generic - Initialize MAC function pointers
42 * @hw: pointer to the HW structure
44 * Setups up the function pointers to no-op functions
46 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
48 struct e1000_mac_info *mac = &hw->mac;
49 DEBUGFUNC("e1000_init_mac_ops_generic");
52 mac->ops.init_params = e1000_null_ops_generic;
53 mac->ops.init_hw = e1000_null_ops_generic;
54 mac->ops.reset_hw = e1000_null_ops_generic;
55 mac->ops.setup_physical_interface = e1000_null_ops_generic;
56 mac->ops.get_bus_info = e1000_null_ops_generic;
57 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
58 mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
59 mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
60 mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
62 mac->ops.cleanup_led = e1000_null_ops_generic;
63 mac->ops.setup_led = e1000_null_ops_generic;
64 mac->ops.blink_led = e1000_null_ops_generic;
65 mac->ops.led_on = e1000_null_ops_generic;
66 mac->ops.led_off = e1000_null_ops_generic;
68 mac->ops.setup_link = e1000_null_ops_generic;
69 mac->ops.get_link_up_info = e1000_null_link_info;
70 mac->ops.check_for_link = e1000_null_ops_generic;
71 mac->ops.wait_autoneg = e1000_wait_autoneg_generic;
73 mac->ops.check_mng_mode = e1000_null_mng_mode;
74 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic;
75 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic;
76 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic;
78 mac->ops.update_mc_addr_list = e1000_null_update_mc;
79 mac->ops.clear_vfta = e1000_null_mac_generic;
80 mac->ops.write_vfta = e1000_null_write_vfta;
81 mac->ops.rar_set = e1000_rar_set_generic;
82 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
86 * e1000_null_ops_generic - No-op function, returns 0
87 * @hw: pointer to the HW structure
89 s32 e1000_null_ops_generic(struct e1000_hw *hw)
91 DEBUGFUNC("e1000_null_ops_generic");
96 * e1000_null_mac_generic - No-op function, return void
97 * @hw: pointer to the HW structure
99 void e1000_null_mac_generic(struct e1000_hw *hw)
101 DEBUGFUNC("e1000_null_mac_generic");
106 * e1000_null_link_info - No-op function, return 0
107 * @hw: pointer to the HW structure
109 s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d)
111 DEBUGFUNC("e1000_null_link_info");
112 return E1000_SUCCESS;
116 * e1000_null_mng_mode - No-op function, return FALSE
117 * @hw: pointer to the HW structure
119 bool e1000_null_mng_mode(struct e1000_hw *hw)
121 DEBUGFUNC("e1000_null_mng_mode");
126 * e1000_null_update_mc - No-op function, return void
127 * @hw: pointer to the HW structure
129 void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a)
131 DEBUGFUNC("e1000_null_update_mc");
136 * e1000_null_write_vfta - No-op function, return void
137 * @hw: pointer to the HW structure
139 void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b)
141 DEBUGFUNC("e1000_null_write_vfta");
146 * e1000_null_rar_set - No-op function, return void
147 * @hw: pointer to the HW structure
149 void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a)
151 DEBUGFUNC("e1000_null_rar_set");
156 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information
157 * @hw: pointer to the HW structure
159 * Determines and stores the system bus information for a particular
160 * network interface. The following bus information is determined and stored:
161 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
163 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
165 struct e1000_mac_info *mac = &hw->mac;
166 struct e1000_bus_info *bus = &hw->bus;
167 u32 status = E1000_READ_REG(hw, E1000_STATUS);
168 s32 ret_val = E1000_SUCCESS;
170 DEBUGFUNC("e1000_get_bus_info_pci_generic");
173 bus->type = (status & E1000_STATUS_PCIX_MODE)
174 ? e1000_bus_type_pcix
175 : e1000_bus_type_pci;
178 if (bus->type == e1000_bus_type_pci) {
179 bus->speed = (status & E1000_STATUS_PCI66)
181 : e1000_bus_speed_33;
183 switch (status & E1000_STATUS_PCIX_SPEED) {
184 case E1000_STATUS_PCIX_SPEED_66:
185 bus->speed = e1000_bus_speed_66;
187 case E1000_STATUS_PCIX_SPEED_100:
188 bus->speed = e1000_bus_speed_100;
190 case E1000_STATUS_PCIX_SPEED_133:
191 bus->speed = e1000_bus_speed_133;
194 bus->speed = e1000_bus_speed_reserved;
200 bus->width = (status & E1000_STATUS_BUS64)
202 : e1000_bus_width_32;
204 /* Which PCI(-X) function? */
205 mac->ops.set_lan_id(hw);
211 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
212 * @hw: pointer to the HW structure
214 * Determines and stores the system bus information for a particular
215 * network interface. The following bus information is determined and stored:
216 * bus speed, bus width, type (PCIe), and PCIe function.
218 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
220 struct e1000_mac_info *mac = &hw->mac;
221 struct e1000_bus_info *bus = &hw->bus;
223 u16 pcie_link_status;
225 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
227 bus->type = e1000_bus_type_pci_express;
229 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
232 bus->width = e1000_bus_width_unknown;
233 bus->speed = e1000_bus_speed_unknown;
235 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
236 case PCIE_LINK_SPEED_2500:
237 bus->speed = e1000_bus_speed_2500;
239 case PCIE_LINK_SPEED_5000:
240 bus->speed = e1000_bus_speed_5000;
243 bus->speed = e1000_bus_speed_unknown;
247 bus->width = (enum e1000_bus_width)((pcie_link_status &
248 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT);
251 mac->ops.set_lan_id(hw);
253 return E1000_SUCCESS;
257 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
259 * @hw: pointer to the HW structure
261 * Determines the LAN function id by reading memory-mapped registers
262 * and swaps the port value if requested.
264 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
266 struct e1000_bus_info *bus = &hw->bus;
270 * The status register reports the correct function number
271 * for the device regardless of function swap state.
273 reg = E1000_READ_REG(hw, E1000_STATUS);
274 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
278 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices
279 * @hw: pointer to the HW structure
281 * Determines the LAN function id by reading PCI config space.
283 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
285 struct e1000_bus_info *bus = &hw->bus;
289 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
290 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
291 status = E1000_READ_REG(hw, E1000_STATUS);
292 bus->func = (status & E1000_STATUS_FUNC_MASK)
293 >> E1000_STATUS_FUNC_SHIFT;
300 * e1000_set_lan_id_single_port - Set LAN id for a single port device
301 * @hw: pointer to the HW structure
303 * Sets the LAN function id to zero for a single port device.
305 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
307 struct e1000_bus_info *bus = &hw->bus;
313 * e1000_clear_vfta_generic - Clear VLAN filter table
314 * @hw: pointer to the HW structure
316 * Clears the register array which contains the VLAN filter table by
317 * setting all the values to 0.
319 void e1000_clear_vfta_generic(struct e1000_hw *hw)
323 DEBUGFUNC("e1000_clear_vfta_generic");
325 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
326 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
327 E1000_WRITE_FLUSH(hw);
332 * e1000_write_vfta_generic - Write value to VLAN filter table
333 * @hw: pointer to the HW structure
334 * @offset: register offset in VLAN filter table
335 * @value: register value written to VLAN filter table
337 * Writes value at the given offset in the register array which stores
338 * the VLAN filter table.
340 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
342 DEBUGFUNC("e1000_write_vfta_generic");
344 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
345 E1000_WRITE_FLUSH(hw);
349 * e1000_init_rx_addrs_generic - Initialize receive address's
350 * @hw: pointer to the HW structure
351 * @rar_count: receive address registers
353 * Setup the receive address registers by setting the base receive address
354 * register to the devices MAC address and clearing all the other receive
355 * address registers to 0.
357 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
360 u8 mac_addr[ETH_ADDR_LEN] = {0};
362 DEBUGFUNC("e1000_init_rx_addrs_generic");
364 /* Setup the receive address */
365 DEBUGOUT("Programming MAC Address into RAR[0]\n");
367 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
369 /* Zero out the other (rar_entry_count - 1) receive addresses */
370 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
371 for (i = 1; i < rar_count; i++)
372 hw->mac.ops.rar_set(hw, mac_addr, i);
376 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
377 * @hw: pointer to the HW structure
379 * Checks the nvm for an alternate MAC address. An alternate MAC address
380 * can be setup by pre-boot software and must be treated like a permanent
381 * address and must override the actual permanent MAC address. If an
382 * alternate MAC address is found it is programmed into RAR0, replacing
383 * the permanent address that was installed into RAR0 by the Si on reset.
384 * This function will return SUCCESS unless it encounters an error while
385 * reading the EEPROM.
387 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
390 s32 ret_val = E1000_SUCCESS;
391 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
392 u8 alt_mac_addr[ETH_ADDR_LEN];
394 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
396 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
400 /* not supported on older hardware or 82573 */
401 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573))
405 * Alternate MAC address is handled by the option ROM for 82580
406 * and newer. SW support not required.
408 if (hw->mac.type >= e1000_82580)
411 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
412 &nvm_alt_mac_addr_offset);
414 DEBUGOUT("NVM Read Error\n");
418 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
419 (nvm_alt_mac_addr_offset == 0x0000))
420 /* There is no Alternate MAC Address */
423 if (hw->bus.func == E1000_FUNC_1)
424 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
425 if (hw->bus.func == E1000_FUNC_2)
426 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
428 if (hw->bus.func == E1000_FUNC_3)
429 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
430 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
431 offset = nvm_alt_mac_addr_offset + (i >> 1);
432 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
434 DEBUGOUT("NVM Read Error\n");
438 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
439 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
442 /* if multicast bit is set, the alternate address will not be used */
443 if (alt_mac_addr[0] & 0x01) {
444 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
449 * We have a valid alternate MAC address, and we want to treat it the
450 * same as the normal permanent MAC address stored by the HW into the
451 * RAR. Do this by mapping this address into RAR0.
453 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
460 * e1000_rar_set_generic - Set receive address register
461 * @hw: pointer to the HW structure
462 * @addr: pointer to the receive address
463 * @index: receive address array register
465 * Sets the receive address array register at index to the address passed
468 void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
470 u32 rar_low, rar_high;
472 DEBUGFUNC("e1000_rar_set_generic");
475 * HW expects these in little endian so we reverse the byte order
476 * from network order (big endian) to little endian
478 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
479 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
481 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
483 /* If MAC address zero, no need to set the AV bit */
484 if (rar_low || rar_high)
485 rar_high |= E1000_RAH_AV;
488 * Some bridges will combine consecutive 32-bit writes into
489 * a single burst write, which will malfunction on some parts.
490 * The flushes avoid this.
492 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
493 E1000_WRITE_FLUSH(hw);
494 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
495 E1000_WRITE_FLUSH(hw);
499 * e1000_update_mc_addr_list_generic - Update Multicast addresses
500 * @hw: pointer to the HW structure
501 * @mc_addr_list: array of multicast addresses to program
502 * @mc_addr_count: number of multicast addresses to program
504 * Updates entire Multicast Table Array.
505 * The caller must have a packed mc_addr_list of multicast addresses.
507 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
508 u8 *mc_addr_list, u32 mc_addr_count)
510 u32 hash_value, hash_bit, hash_reg;
513 DEBUGFUNC("e1000_update_mc_addr_list_generic");
515 /* clear mta_shadow */
516 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
518 /* update mta_shadow from mc_addr_list */
519 for (i = 0; (u32) i < mc_addr_count; i++) {
520 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
522 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
523 hash_bit = hash_value & 0x1F;
525 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
526 mc_addr_list += (ETH_ADDR_LEN);
529 /* replace the entire MTA table */
530 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
531 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
532 E1000_WRITE_FLUSH(hw);
536 * e1000_hash_mc_addr_generic - Generate a multicast hash value
537 * @hw: pointer to the HW structure
538 * @mc_addr: pointer to a multicast address
540 * Generates a multicast address hash value which is used to determine
541 * the multicast filter table array address and new table value.
543 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
545 u32 hash_value, hash_mask;
548 DEBUGFUNC("e1000_hash_mc_addr_generic");
550 /* Register count multiplied by bits per register */
551 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
554 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
555 * where 0xFF would still fall within the hash mask.
557 while (hash_mask >> bit_shift != 0xFF)
561 * The portion of the address that is used for the hash table
562 * is determined by the mc_filter_type setting.
563 * The algorithm is such that there is a total of 8 bits of shifting.
564 * The bit_shift for a mc_filter_type of 0 represents the number of
565 * left-shifts where the MSB of mc_addr[5] would still fall within
566 * the hash_mask. Case 0 does this exactly. Since there are a total
567 * of 8 bits of shifting, then mc_addr[4] will shift right the
568 * remaining number of bits. Thus 8 - bit_shift. The rest of the
569 * cases are a variation of this algorithm...essentially raising the
570 * number of bits to shift mc_addr[5] left, while still keeping the
571 * 8-bit shifting total.
573 * For example, given the following Destination MAC Address and an
574 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
575 * we can see that the bit_shift for case 0 is 4. These are the hash
576 * values resulting from each mc_filter_type...
577 * [0] [1] [2] [3] [4] [5]
581 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
582 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
583 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
584 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
586 switch (hw->mac.mc_filter_type) {
601 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
602 (((u16) mc_addr[5]) << bit_shift)));
608 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
609 * @hw: pointer to the HW structure
611 * In certain situations, a system BIOS may report that the PCIx maximum
612 * memory read byte count (MMRBC) value is higher than than the actual
613 * value. We check the PCIx command register with the current PCIx status
616 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
620 u16 pcix_stat_hi_word;
623 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
625 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
626 if (hw->bus.type != e1000_bus_type_pcix)
629 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
630 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
631 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
632 PCIX_COMMAND_MMRBC_SHIFT;
633 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
634 PCIX_STATUS_HI_MMRBC_SHIFT;
635 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
636 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
637 if (cmd_mmrbc > stat_mmrbc) {
638 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
639 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
640 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
645 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
646 * @hw: pointer to the HW structure
648 * Clears the base hardware counters by reading the counter registers.
650 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
652 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
654 E1000_READ_REG(hw, E1000_CRCERRS);
655 E1000_READ_REG(hw, E1000_SYMERRS);
656 E1000_READ_REG(hw, E1000_MPC);
657 E1000_READ_REG(hw, E1000_SCC);
658 E1000_READ_REG(hw, E1000_ECOL);
659 E1000_READ_REG(hw, E1000_MCC);
660 E1000_READ_REG(hw, E1000_LATECOL);
661 E1000_READ_REG(hw, E1000_COLC);
662 E1000_READ_REG(hw, E1000_DC);
663 E1000_READ_REG(hw, E1000_SEC);
664 E1000_READ_REG(hw, E1000_RLEC);
665 E1000_READ_REG(hw, E1000_XONRXC);
666 E1000_READ_REG(hw, E1000_XONTXC);
667 E1000_READ_REG(hw, E1000_XOFFRXC);
668 E1000_READ_REG(hw, E1000_XOFFTXC);
669 E1000_READ_REG(hw, E1000_FCRUC);
670 E1000_READ_REG(hw, E1000_GPRC);
671 E1000_READ_REG(hw, E1000_BPRC);
672 E1000_READ_REG(hw, E1000_MPRC);
673 E1000_READ_REG(hw, E1000_GPTC);
674 E1000_READ_REG(hw, E1000_GORCL);
675 E1000_READ_REG(hw, E1000_GORCH);
676 E1000_READ_REG(hw, E1000_GOTCL);
677 E1000_READ_REG(hw, E1000_GOTCH);
678 E1000_READ_REG(hw, E1000_RNBC);
679 E1000_READ_REG(hw, E1000_RUC);
680 E1000_READ_REG(hw, E1000_RFC);
681 E1000_READ_REG(hw, E1000_ROC);
682 E1000_READ_REG(hw, E1000_RJC);
683 E1000_READ_REG(hw, E1000_TORL);
684 E1000_READ_REG(hw, E1000_TORH);
685 E1000_READ_REG(hw, E1000_TOTL);
686 E1000_READ_REG(hw, E1000_TOTH);
687 E1000_READ_REG(hw, E1000_TPR);
688 E1000_READ_REG(hw, E1000_TPT);
689 E1000_READ_REG(hw, E1000_MPTC);
690 E1000_READ_REG(hw, E1000_BPTC);
694 * e1000_check_for_copper_link_generic - Check for link (Copper)
695 * @hw: pointer to the HW structure
697 * Checks to see of the link status of the hardware has changed. If a
698 * change in link status has been detected, then we read the PHY registers
699 * to get the current speed/duplex if link exists.
701 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
703 struct e1000_mac_info *mac = &hw->mac;
707 DEBUGFUNC("e1000_check_for_copper_link");
710 * We only want to go out to the PHY registers to see if Auto-Neg
711 * has completed and/or if our link status has changed. The
712 * get_link_status flag is set upon receiving a Link Status
713 * Change or Rx Sequence Error interrupt.
715 if (!mac->get_link_status) {
716 ret_val = E1000_SUCCESS;
721 * First we want to see if the MII Status Register reports
722 * link. If so, then we want to get the current speed/duplex
725 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
730 goto out; /* No link detected */
732 mac->get_link_status = FALSE;
735 * Check if there was DownShift, must be checked
736 * immediately after link-up
738 e1000_check_downshift_generic(hw);
741 * If we are forcing speed/duplex, then we simply return since
742 * we have already determined whether we have link or not.
745 ret_val = -E1000_ERR_CONFIG;
750 * Auto-Neg is enabled. Auto Speed Detection takes care
751 * of MAC speed/duplex configuration. So we only need to
752 * configure Collision Distance in the MAC.
754 mac->ops.config_collision_dist(hw);
757 * Configure Flow Control now that Auto-Neg has completed.
758 * First, we need to restore the desired flow control
759 * settings because we may have had to re-autoneg with a
760 * different link partner.
762 ret_val = e1000_config_fc_after_link_up_generic(hw);
764 DEBUGOUT("Error configuring flow control\n");
771 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
772 * @hw: pointer to the HW structure
774 * Checks for link up on the hardware. If link is not up and we have
775 * a signal, then we need to force link up.
777 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
779 struct e1000_mac_info *mac = &hw->mac;
783 s32 ret_val = E1000_SUCCESS;
785 DEBUGFUNC("e1000_check_for_fiber_link_generic");
787 ctrl = E1000_READ_REG(hw, E1000_CTRL);
788 status = E1000_READ_REG(hw, E1000_STATUS);
789 rxcw = E1000_READ_REG(hw, E1000_RXCW);
792 * If we don't have link (auto-negotiation failed or link partner
793 * cannot auto-negotiate), the cable is plugged in (we have signal),
794 * and our link partner is not trying to auto-negotiate with us (we
795 * are receiving idles or data), we need to force link up. We also
796 * need to give auto-negotiation time to complete, in case the cable
797 * was just plugged in. The autoneg_failed flag does this.
799 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
800 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
801 (!(rxcw & E1000_RXCW_C))) {
802 if (mac->autoneg_failed == 0) {
803 mac->autoneg_failed = 1;
806 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
808 /* Disable auto-negotiation in the TXCW register */
809 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
811 /* Force link-up and also force full-duplex. */
812 ctrl = E1000_READ_REG(hw, E1000_CTRL);
813 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
814 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
816 /* Configure Flow Control after forcing link up. */
817 ret_val = e1000_config_fc_after_link_up_generic(hw);
819 DEBUGOUT("Error configuring flow control\n");
822 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
824 * If we are forcing link and we are receiving /C/ ordered
825 * sets, re-enable auto-negotiation in the TXCW register
826 * and disable forced link in the Device Control register
827 * in an attempt to auto-negotiate with our link partner.
829 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
830 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
831 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
833 mac->serdes_has_link = TRUE;
841 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
842 * @hw: pointer to the HW structure
844 * Checks for link up on the hardware. If link is not up and we have
845 * a signal, then we need to force link up.
847 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
849 struct e1000_mac_info *mac = &hw->mac;
853 s32 ret_val = E1000_SUCCESS;
855 DEBUGFUNC("e1000_check_for_serdes_link_generic");
857 ctrl = E1000_READ_REG(hw, E1000_CTRL);
858 status = E1000_READ_REG(hw, E1000_STATUS);
859 rxcw = E1000_READ_REG(hw, E1000_RXCW);
862 * If we don't have link (auto-negotiation failed or link partner
863 * cannot auto-negotiate), and our link partner is not trying to
864 * auto-negotiate with us (we are receiving idles or data),
865 * we need to force link up. We also need to give auto-negotiation
868 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
869 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
870 if (mac->autoneg_failed == 0) {
871 mac->autoneg_failed = 1;
874 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
876 /* Disable auto-negotiation in the TXCW register */
877 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
879 /* Force link-up and also force full-duplex. */
880 ctrl = E1000_READ_REG(hw, E1000_CTRL);
881 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
882 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
884 /* Configure Flow Control after forcing link up. */
885 ret_val = e1000_config_fc_after_link_up_generic(hw);
887 DEBUGOUT("Error configuring flow control\n");
890 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
892 * If we are forcing link and we are receiving /C/ ordered
893 * sets, re-enable auto-negotiation in the TXCW register
894 * and disable forced link in the Device Control register
895 * in an attempt to auto-negotiate with our link partner.
897 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
898 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
899 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
901 mac->serdes_has_link = TRUE;
902 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
904 * If we force link for non-auto-negotiation switch, check
905 * link status based on MAC synchronization for internal
908 /* SYNCH bit and IV bit are sticky. */
910 rxcw = E1000_READ_REG(hw, E1000_RXCW);
911 if (rxcw & E1000_RXCW_SYNCH) {
912 if (!(rxcw & E1000_RXCW_IV)) {
913 mac->serdes_has_link = TRUE;
914 DEBUGOUT("SERDES: Link up - forced.\n");
917 mac->serdes_has_link = FALSE;
918 DEBUGOUT("SERDES: Link down - force failed.\n");
922 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
923 status = E1000_READ_REG(hw, E1000_STATUS);
924 if (status & E1000_STATUS_LU) {
925 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
927 rxcw = E1000_READ_REG(hw, E1000_RXCW);
928 if (rxcw & E1000_RXCW_SYNCH) {
929 if (!(rxcw & E1000_RXCW_IV)) {
930 mac->serdes_has_link = TRUE;
931 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n");
933 mac->serdes_has_link = FALSE;
934 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n");
937 mac->serdes_has_link = FALSE;
938 DEBUGOUT("SERDES: Link down - no sync.\n");
941 mac->serdes_has_link = FALSE;
942 DEBUGOUT("SERDES: Link down - autoneg failed\n");
951 * e1000_setup_link_generic - Setup flow control and link settings
952 * @hw: pointer to the HW structure
954 * Determines which flow control settings to use, then configures flow
955 * control. Calls the appropriate media-specific link configuration
956 * function. Assuming the adapter has a valid link partner, a valid link
957 * should be established. Assumes the hardware has previously been reset
958 * and the transmitter and receiver are not enabled.
960 s32 e1000_setup_link_generic(struct e1000_hw *hw)
962 s32 ret_val = E1000_SUCCESS;
964 DEBUGFUNC("e1000_setup_link_generic");
967 * In the case of the phy reset being blocked, we already have a link.
968 * We do not need to set it up again.
970 if (e1000_check_reset_block(hw))
974 * If requested flow control is set to default, set flow control
975 * based on the EEPROM flow control settings.
977 if (hw->fc.requested_mode == e1000_fc_default) {
978 ret_val = e1000_set_default_fc_generic(hw);
984 * Save off the requested flow control mode for use later. Depending
985 * on the link partner's capabilities, we may or may not use this mode.
987 hw->fc.current_mode = hw->fc.requested_mode;
989 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
990 hw->fc.current_mode);
992 /* Call the necessary media_type subroutine to configure the link. */
993 ret_val = hw->mac.ops.setup_physical_interface(hw);
998 * Initialize the flow control address, type, and PAUSE timer
999 * registers to their default values. This is done even if flow
1000 * control is disabled, because it does not hurt anything to
1001 * initialize these registers.
1003 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1004 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
1005 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1006 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1008 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1010 ret_val = e1000_set_fc_watermarks_generic(hw);
1017 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1018 * @hw: pointer to the HW structure
1020 * Configures collision distance and flow control for fiber and serdes
1021 * links. Upon successful setup, poll for link.
1023 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1025 struct e1000_mac_info *mac = &hw->mac;
1027 s32 ret_val = E1000_SUCCESS;
1029 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1031 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1033 /* Take the link out of reset */
1034 ctrl &= ~E1000_CTRL_LRST;
1036 mac->ops.config_collision_dist(hw);
1038 ret_val = e1000_commit_fc_settings_generic(hw);
1043 * Since auto-negotiation is enabled, take the link out of reset (the
1044 * link will be in reset, because we previously reset the chip). This
1045 * will restart auto-negotiation. If auto-negotiation is successful
1046 * then the link-up status bit will be set and the flow control enable
1047 * bits (RFCE and TFCE) will be set according to their negotiated value.
1049 DEBUGOUT("Auto-negotiation enabled\n");
1051 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1052 E1000_WRITE_FLUSH(hw);
1056 * For these adapters, the SW definable pin 1 is set when the optics
1057 * detect a signal. If we have a signal, then poll for a "Link-Up"
1060 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1061 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1062 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1064 DEBUGOUT("No signal detected\n");
1072 * e1000_config_collision_dist_generic - Configure collision distance
1073 * @hw: pointer to the HW structure
1075 * Configures the collision distance to the default value and is used
1076 * during link setup.
1078 void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1082 DEBUGFUNC("e1000_config_collision_dist_generic");
1084 tctl = E1000_READ_REG(hw, E1000_TCTL);
1086 tctl &= ~E1000_TCTL_COLD;
1087 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1089 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1090 E1000_WRITE_FLUSH(hw);
1094 * e1000_poll_fiber_serdes_link_generic - Poll for link up
1095 * @hw: pointer to the HW structure
1097 * Polls for link up by reading the status register, if link fails to come
1098 * up with auto-negotiation, then the link is forced if a signal is detected.
1100 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1102 struct e1000_mac_info *mac = &hw->mac;
1104 s32 ret_val = E1000_SUCCESS;
1106 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1109 * If we have a signal (the cable is plugged in, or assumed TRUE for
1110 * serdes media) then poll for a "Link-Up" indication in the Device
1111 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1112 * seconds (Auto-negotiation should complete in less than 500
1113 * milliseconds even if the other end is doing it in SW).
1115 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1117 status = E1000_READ_REG(hw, E1000_STATUS);
1118 if (status & E1000_STATUS_LU)
1121 if (i == FIBER_LINK_UP_LIMIT) {
1122 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1123 mac->autoneg_failed = 1;
1125 * AutoNeg failed to achieve a link, so we'll call
1126 * mac->check_for_link. This routine will force the
1127 * link up if we detect a signal. This will allow us to
1128 * communicate with non-autonegotiating link partners.
1130 ret_val = mac->ops.check_for_link(hw);
1132 DEBUGOUT("Error while checking for link\n");
1135 mac->autoneg_failed = 0;
1137 mac->autoneg_failed = 0;
1138 DEBUGOUT("Valid Link Found\n");
1146 * e1000_commit_fc_settings_generic - Configure flow control
1147 * @hw: pointer to the HW structure
1149 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1150 * base on the flow control settings in e1000_mac_info.
1152 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1154 struct e1000_mac_info *mac = &hw->mac;
1156 s32 ret_val = E1000_SUCCESS;
1158 DEBUGFUNC("e1000_commit_fc_settings_generic");
1161 * Check for a software override of the flow control settings, and
1162 * setup the device accordingly. If auto-negotiation is enabled, then
1163 * software will have to set the "PAUSE" bits to the correct value in
1164 * the Transmit Config Word Register (TXCW) and re-start auto-
1165 * negotiation. However, if auto-negotiation is disabled, then
1166 * software will have to manually configure the two flow control enable
1167 * bits in the CTRL register.
1169 * The possible values of the "fc" parameter are:
1170 * 0: Flow control is completely disabled
1171 * 1: Rx flow control is enabled (we can receive pause frames,
1172 * but not send pause frames).
1173 * 2: Tx flow control is enabled (we can send pause frames but we
1174 * do not support receiving pause frames).
1175 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1177 switch (hw->fc.current_mode) {
1179 /* Flow control completely disabled by a software over-ride. */
1180 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1182 case e1000_fc_rx_pause:
1184 * Rx Flow control is enabled and Tx Flow control is disabled
1185 * by a software over-ride. Since there really isn't a way to
1186 * advertise that we are capable of Rx Pause ONLY, we will
1187 * advertise that we support both symmetric and asymmetric Rx
1188 * PAUSE. Later, we will disable the adapter's ability to send
1191 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1193 case e1000_fc_tx_pause:
1195 * Tx Flow control is enabled, and Rx Flow control is disabled,
1196 * by a software over-ride.
1198 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1202 * Flow control (both Rx and Tx) is enabled by a software
1205 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1208 DEBUGOUT("Flow control param set incorrectly\n");
1209 ret_val = -E1000_ERR_CONFIG;
1214 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1222 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1223 * @hw: pointer to the HW structure
1225 * Sets the flow control high/low threshold (watermark) registers. If
1226 * flow control XON frame transmission is enabled, then set XON frame
1227 * transmission as well.
1229 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1231 u32 fcrtl = 0, fcrth = 0;
1233 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1236 * Set the flow control receive threshold registers. Normally,
1237 * these registers will be set to a default threshold that may be
1238 * adjusted later by the driver's runtime code. However, if the
1239 * ability to transmit pause frames is not enabled, then these
1240 * registers will be set to 0.
1242 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1244 * We need to set up the Receive Threshold high and low water
1245 * marks as well as (optionally) enabling the transmission of
1248 fcrtl = hw->fc.low_water;
1249 if (hw->fc.send_xon)
1250 fcrtl |= E1000_FCRTL_XONE;
1252 fcrth = hw->fc.high_water;
1254 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1255 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1257 return E1000_SUCCESS;
1261 * e1000_set_default_fc_generic - Set flow control default values
1262 * @hw: pointer to the HW structure
1264 * Read the EEPROM for the default values for flow control and store the
1267 s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
1269 s32 ret_val = E1000_SUCCESS;
1272 DEBUGFUNC("e1000_set_default_fc_generic");
1275 * Read and store word 0x0F of the EEPROM. This word contains bits
1276 * that determine the hardware's default PAUSE (flow control) mode,
1277 * a bit that determines whether the HW defaults to enabling or
1278 * disabling auto-negotiation, and the direction of the
1279 * SW defined pins. If there is no SW over-ride of the flow
1280 * control setting, then the variable hw->fc will
1281 * be initialized based on a value in the EEPROM.
1283 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
1286 DEBUGOUT("NVM Read Error\n");
1290 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
1291 hw->fc.requested_mode = e1000_fc_none;
1292 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
1294 hw->fc.requested_mode = e1000_fc_tx_pause;
1296 hw->fc.requested_mode = e1000_fc_full;
1303 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1304 * @hw: pointer to the HW structure
1306 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1307 * device control register to reflect the adapter settings. TFCE and RFCE
1308 * need to be explicitly set by software when a copper PHY is used because
1309 * autonegotiation is managed by the PHY rather than the MAC. Software must
1310 * also configure these bits when link is forced on a fiber connection.
1312 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1315 s32 ret_val = E1000_SUCCESS;
1317 DEBUGFUNC("e1000_force_mac_fc_generic");
1319 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1322 * Because we didn't get link via the internal auto-negotiation
1323 * mechanism (we either forced link or we got link via PHY
1324 * auto-neg), we have to manually enable/disable transmit an
1325 * receive flow control.
1327 * The "Case" statement below enables/disable flow control
1328 * according to the "hw->fc.current_mode" parameter.
1330 * The possible values of the "fc" parameter are:
1331 * 0: Flow control is completely disabled
1332 * 1: Rx flow control is enabled (we can receive pause
1333 * frames but not send pause frames).
1334 * 2: Tx flow control is enabled (we can send pause frames
1335 * frames but we do not receive pause frames).
1336 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1337 * other: No other values should be possible at this point.
1339 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1341 switch (hw->fc.current_mode) {
1343 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1345 case e1000_fc_rx_pause:
1346 ctrl &= (~E1000_CTRL_TFCE);
1347 ctrl |= E1000_CTRL_RFCE;
1349 case e1000_fc_tx_pause:
1350 ctrl &= (~E1000_CTRL_RFCE);
1351 ctrl |= E1000_CTRL_TFCE;
1354 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1357 DEBUGOUT("Flow control param set incorrectly\n");
1358 ret_val = -E1000_ERR_CONFIG;
1362 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1369 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1370 * @hw: pointer to the HW structure
1372 * Checks the status of auto-negotiation after link up to ensure that the
1373 * speed and duplex were not forced. If the link needed to be forced, then
1374 * flow control needs to be forced also. If auto-negotiation is enabled
1375 * and did not fail, then we configure flow control based on our link
1378 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1380 struct e1000_mac_info *mac = &hw->mac;
1381 s32 ret_val = E1000_SUCCESS;
1382 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1385 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1388 * Check for the case where we have fiber media and auto-neg failed
1389 * so we had to force link. In this case, we need to force the
1390 * configuration of the MAC to match the "fc" parameter.
1392 if (mac->autoneg_failed) {
1393 if (hw->phy.media_type == e1000_media_type_fiber ||
1394 hw->phy.media_type == e1000_media_type_internal_serdes)
1395 ret_val = e1000_force_mac_fc_generic(hw);
1397 if (hw->phy.media_type == e1000_media_type_copper)
1398 ret_val = e1000_force_mac_fc_generic(hw);
1402 DEBUGOUT("Error forcing flow control settings\n");
1407 * Check for the case where we have copper media and auto-neg is
1408 * enabled. In this case, we need to check and see if Auto-Neg
1409 * has completed, and if so, how the PHY and link partner has
1410 * flow control configured.
1412 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1414 * Read the MII Status Register and check to see if AutoNeg
1415 * has completed. We read this twice because this reg has
1416 * some "sticky" (latched) bits.
1418 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1421 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1425 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1426 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1431 * The AutoNeg process has completed, so we now need to
1432 * read both the Auto Negotiation Advertisement
1433 * Register (Address 4) and the Auto_Negotiation Base
1434 * Page Ability Register (Address 5) to determine how
1435 * flow control was negotiated.
1437 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1441 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1442 &mii_nway_lp_ability_reg);
1447 * Two bits in the Auto Negotiation Advertisement Register
1448 * (Address 4) and two bits in the Auto Negotiation Base
1449 * Page Ability Register (Address 5) determine flow control
1450 * for both the PHY and the link partner. The following
1451 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1452 * 1999, describes these PAUSE resolution bits and how flow
1453 * control is determined based upon these settings.
1454 * NOTE: DC = Don't Care
1456 * LOCAL DEVICE | LINK PARTNER
1457 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1458 *-------|---------|-------|---------|--------------------
1459 * 0 | 0 | DC | DC | e1000_fc_none
1460 * 0 | 1 | 0 | DC | e1000_fc_none
1461 * 0 | 1 | 1 | 0 | e1000_fc_none
1462 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1463 * 1 | 0 | 0 | DC | e1000_fc_none
1464 * 1 | DC | 1 | DC | e1000_fc_full
1465 * 1 | 1 | 0 | 0 | e1000_fc_none
1466 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1468 * Are both PAUSE bits set to 1? If so, this implies
1469 * Symmetric Flow Control is enabled at both ends. The
1470 * ASM_DIR bits are irrelevant per the spec.
1472 * For Symmetric Flow Control:
1474 * LOCAL DEVICE | LINK PARTNER
1475 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1476 *-------|---------|-------|---------|--------------------
1477 * 1 | DC | 1 | DC | E1000_fc_full
1480 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1481 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1483 * Now we need to check if the user selected Rx ONLY
1484 * of pause frames. In this case, we had to advertise
1485 * FULL flow control because we could not advertise Rx
1486 * ONLY. Hence, we must now check to see if we need to
1487 * turn OFF the TRANSMISSION of PAUSE frames.
1489 if (hw->fc.requested_mode == e1000_fc_full) {
1490 hw->fc.current_mode = e1000_fc_full;
1491 DEBUGOUT("Flow Control = FULL.\n");
1493 hw->fc.current_mode = e1000_fc_rx_pause;
1494 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1498 * For receiving PAUSE frames ONLY.
1500 * LOCAL DEVICE | LINK PARTNER
1501 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1502 *-------|---------|-------|---------|--------------------
1503 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1505 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1506 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1507 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1508 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1509 hw->fc.current_mode = e1000_fc_tx_pause;
1510 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1513 * For transmitting PAUSE frames ONLY.
1515 * LOCAL DEVICE | LINK PARTNER
1516 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1517 *-------|---------|-------|---------|--------------------
1518 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1520 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1521 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1522 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1523 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1524 hw->fc.current_mode = e1000_fc_rx_pause;
1525 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1528 * Per the IEEE spec, at this point flow control
1529 * should be disabled.
1531 hw->fc.current_mode = e1000_fc_none;
1532 DEBUGOUT("Flow Control = NONE.\n");
1536 * Now we need to do one last check... If we auto-
1537 * negotiated to HALF DUPLEX, flow control should not be
1538 * enabled per IEEE 802.3 spec.
1540 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1542 DEBUGOUT("Error getting link speed and duplex\n");
1546 if (duplex == HALF_DUPLEX)
1547 hw->fc.current_mode = e1000_fc_none;
1550 * Now we call a subroutine to actually force the MAC
1551 * controller to use the correct flow control settings.
1553 ret_val = e1000_force_mac_fc_generic(hw);
1555 DEBUGOUT("Error forcing flow control settings\n");
1565 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1566 * @hw: pointer to the HW structure
1567 * @speed: stores the current speed
1568 * @duplex: stores the current duplex
1570 * Read the status register for the current speed/duplex and store the current
1571 * speed and duplex for copper connections.
1573 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1578 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1580 status = E1000_READ_REG(hw, E1000_STATUS);
1581 if (status & E1000_STATUS_SPEED_1000) {
1582 *speed = SPEED_1000;
1583 DEBUGOUT("1000 Mbs, ");
1584 } else if (status & E1000_STATUS_SPEED_100) {
1586 DEBUGOUT("100 Mbs, ");
1589 DEBUGOUT("10 Mbs, ");
1592 if (status & E1000_STATUS_FD) {
1593 *duplex = FULL_DUPLEX;
1594 DEBUGOUT("Full Duplex\n");
1596 *duplex = HALF_DUPLEX;
1597 DEBUGOUT("Half Duplex\n");
1600 return E1000_SUCCESS;
1604 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1605 * @hw: pointer to the HW structure
1606 * @speed: stores the current speed
1607 * @duplex: stores the current duplex
1609 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1610 * for fiber/serdes links.
1612 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
1613 u16 *speed, u16 *duplex)
1615 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1617 *speed = SPEED_1000;
1618 *duplex = FULL_DUPLEX;
1620 return E1000_SUCCESS;
1624 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1625 * @hw: pointer to the HW structure
1627 * Acquire the HW semaphore to access the PHY or NVM
1629 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1632 s32 ret_val = E1000_SUCCESS;
1633 s32 timeout = hw->nvm.word_size + 1;
1636 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1638 /* Get the SW semaphore */
1639 while (i < timeout) {
1640 swsm = E1000_READ_REG(hw, E1000_SWSM);
1641 if (!(swsm & E1000_SWSM_SMBI))
1649 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1650 ret_val = -E1000_ERR_NVM;
1654 /* Get the FW semaphore. */
1655 for (i = 0; i < timeout; i++) {
1656 swsm = E1000_READ_REG(hw, E1000_SWSM);
1657 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1659 /* Semaphore acquired if bit latched */
1660 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1667 /* Release semaphores */
1668 e1000_put_hw_semaphore_generic(hw);
1669 DEBUGOUT("Driver can't access the NVM\n");
1670 ret_val = -E1000_ERR_NVM;
1679 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1680 * @hw: pointer to the HW structure
1682 * Release hardware semaphore used to access the PHY or NVM
1684 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1688 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1690 swsm = E1000_READ_REG(hw, E1000_SWSM);
1692 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1694 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1698 * e1000_get_auto_rd_done_generic - Check for auto read completion
1699 * @hw: pointer to the HW structure
1701 * Check EEPROM for Auto Read done bit.
1703 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1706 s32 ret_val = E1000_SUCCESS;
1708 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1710 while (i < AUTO_READ_DONE_TIMEOUT) {
1711 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1717 if (i == AUTO_READ_DONE_TIMEOUT) {
1718 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1719 ret_val = -E1000_ERR_RESET;
1728 * e1000_valid_led_default_generic - Verify a valid default LED config
1729 * @hw: pointer to the HW structure
1730 * @data: pointer to the NVM (EEPROM)
1732 * Read the EEPROM for the current default LED configuration. If the
1733 * LED configuration is not valid, set to a valid LED configuration.
1735 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1739 DEBUGFUNC("e1000_valid_led_default_generic");
1741 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1743 DEBUGOUT("NVM Read Error\n");
1747 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1748 *data = ID_LED_DEFAULT;
1755 * e1000_id_led_init_generic -
1756 * @hw: pointer to the HW structure
1759 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1761 struct e1000_mac_info *mac = &hw->mac;
1763 const u32 ledctl_mask = 0x000000FF;
1764 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1765 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1767 const u16 led_mask = 0x0F;
1769 DEBUGFUNC("e1000_id_led_init_generic");
1771 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1775 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1776 mac->ledctl_mode1 = mac->ledctl_default;
1777 mac->ledctl_mode2 = mac->ledctl_default;
1779 for (i = 0; i < 4; i++) {
1780 temp = (data >> (i << 2)) & led_mask;
1782 case ID_LED_ON1_DEF2:
1783 case ID_LED_ON1_ON2:
1784 case ID_LED_ON1_OFF2:
1785 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1786 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1788 case ID_LED_OFF1_DEF2:
1789 case ID_LED_OFF1_ON2:
1790 case ID_LED_OFF1_OFF2:
1791 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1792 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1799 case ID_LED_DEF1_ON2:
1800 case ID_LED_ON1_ON2:
1801 case ID_LED_OFF1_ON2:
1802 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1803 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1805 case ID_LED_DEF1_OFF2:
1806 case ID_LED_ON1_OFF2:
1807 case ID_LED_OFF1_OFF2:
1808 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1809 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1822 * e1000_setup_led_generic - Configures SW controllable LED
1823 * @hw: pointer to the HW structure
1825 * This prepares the SW controllable LED for use and saves the current state
1826 * of the LED so it can be later restored.
1828 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1831 s32 ret_val = E1000_SUCCESS;
1833 DEBUGFUNC("e1000_setup_led_generic");
1835 if (hw->mac.ops.setup_led != e1000_setup_led_generic) {
1836 ret_val = -E1000_ERR_CONFIG;
1840 if (hw->phy.media_type == e1000_media_type_fiber) {
1841 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1842 hw->mac.ledctl_default = ledctl;
1844 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1845 E1000_LEDCTL_LED0_MODE_MASK);
1846 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1847 E1000_LEDCTL_LED0_MODE_SHIFT);
1848 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1849 } else if (hw->phy.media_type == e1000_media_type_copper) {
1850 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1858 * e1000_cleanup_led_generic - Set LED config to default operation
1859 * @hw: pointer to the HW structure
1861 * Remove the current LED configuration and set the LED configuration
1862 * to the default value, saved from the EEPROM.
1864 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1866 DEBUGFUNC("e1000_cleanup_led_generic");
1868 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1869 return E1000_SUCCESS;
1873 * e1000_blink_led_generic - Blink LED
1874 * @hw: pointer to the HW structure
1876 * Blink the LEDs which are set to be on.
1878 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1880 u32 ledctl_blink = 0;
1883 DEBUGFUNC("e1000_blink_led_generic");
1885 if (hw->phy.media_type == e1000_media_type_fiber) {
1886 /* always blink LED0 for PCI-E fiber */
1887 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1888 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1891 * set the blink bit for each LED that's "on" (0x0E)
1894 ledctl_blink = hw->mac.ledctl_mode2;
1895 for (i = 0; i < 4; i++)
1896 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1897 E1000_LEDCTL_MODE_LED_ON)
1898 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1902 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1904 return E1000_SUCCESS;
1908 * e1000_led_on_generic - Turn LED on
1909 * @hw: pointer to the HW structure
1913 s32 e1000_led_on_generic(struct e1000_hw *hw)
1917 DEBUGFUNC("e1000_led_on_generic");
1919 switch (hw->phy.media_type) {
1920 case e1000_media_type_fiber:
1921 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1922 ctrl &= ~E1000_CTRL_SWDPIN0;
1923 ctrl |= E1000_CTRL_SWDPIO0;
1924 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1926 case e1000_media_type_copper:
1927 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
1933 return E1000_SUCCESS;
1937 * e1000_led_off_generic - Turn LED off
1938 * @hw: pointer to the HW structure
1942 s32 e1000_led_off_generic(struct e1000_hw *hw)
1946 DEBUGFUNC("e1000_led_off_generic");
1948 switch (hw->phy.media_type) {
1949 case e1000_media_type_fiber:
1950 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1951 ctrl |= E1000_CTRL_SWDPIN0;
1952 ctrl |= E1000_CTRL_SWDPIO0;
1953 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1955 case e1000_media_type_copper:
1956 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1962 return E1000_SUCCESS;
1966 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
1967 * @hw: pointer to the HW structure
1968 * @no_snoop: bitmap of snoop events
1970 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1972 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
1976 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
1978 if (hw->bus.type != e1000_bus_type_pci_express)
1982 gcr = E1000_READ_REG(hw, E1000_GCR);
1983 gcr &= ~(PCIE_NO_SNOOP_ALL);
1985 E1000_WRITE_REG(hw, E1000_GCR, gcr);
1992 * e1000_disable_pcie_master_generic - Disables PCI-express master access
1993 * @hw: pointer to the HW structure
1995 * Returns E1000_SUCCESS if successful, else returns -10
1996 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1997 * the master requests to be disabled.
1999 * Disables PCI-Express master access and verifies there are no pending
2002 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
2005 s32 timeout = MASTER_DISABLE_TIMEOUT;
2006 s32 ret_val = E1000_SUCCESS;
2008 DEBUGFUNC("e1000_disable_pcie_master_generic");
2010 if (hw->bus.type != e1000_bus_type_pci_express)
2013 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2014 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
2015 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2018 if (!(E1000_READ_REG(hw, E1000_STATUS) &
2019 E1000_STATUS_GIO_MASTER_ENABLE))
2026 DEBUGOUT("Master requests are pending.\n");
2027 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
2035 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
2036 * @hw: pointer to the HW structure
2038 * Reset the Adaptive Interframe Spacing throttle to default values.
2040 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2042 struct e1000_mac_info *mac = &hw->mac;
2044 DEBUGFUNC("e1000_reset_adaptive_generic");
2046 if (!mac->adaptive_ifs) {
2047 DEBUGOUT("Not in Adaptive IFS mode!\n");
2051 mac->current_ifs_val = 0;
2052 mac->ifs_min_val = IFS_MIN;
2053 mac->ifs_max_val = IFS_MAX;
2054 mac->ifs_step_size = IFS_STEP;
2055 mac->ifs_ratio = IFS_RATIO;
2057 mac->in_ifs_mode = FALSE;
2058 E1000_WRITE_REG(hw, E1000_AIT, 0);
2064 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2065 * @hw: pointer to the HW structure
2067 * Update the Adaptive Interframe Spacing Throttle value based on the
2068 * time between transmitted packets and time between collisions.
2070 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2072 struct e1000_mac_info *mac = &hw->mac;
2074 DEBUGFUNC("e1000_update_adaptive_generic");
2076 if (!mac->adaptive_ifs) {
2077 DEBUGOUT("Not in Adaptive IFS mode!\n");
2081 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2082 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2083 mac->in_ifs_mode = TRUE;
2084 if (mac->current_ifs_val < mac->ifs_max_val) {
2085 if (!mac->current_ifs_val)
2086 mac->current_ifs_val = mac->ifs_min_val;
2088 mac->current_ifs_val +=
2090 E1000_WRITE_REG(hw, E1000_AIT,
2091 mac->current_ifs_val);
2095 if (mac->in_ifs_mode &&
2096 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2097 mac->current_ifs_val = 0;
2098 mac->in_ifs_mode = FALSE;
2099 E1000_WRITE_REG(hw, E1000_AIT, 0);
2107 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2108 * @hw: pointer to the HW structure
2110 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2111 * set, which is forced to MDI mode only.
2113 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2115 s32 ret_val = E1000_SUCCESS;
2117 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2119 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2120 DEBUGOUT("Invalid MDI setting detected\n");
2122 ret_val = -E1000_ERR_CONFIG;
2131 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
2132 * @hw: pointer to the HW structure
2133 * @reg: 32bit register offset such as E1000_SCTL
2134 * @offset: register offset to write to
2135 * @data: data to write at register offset
2137 * Writes an address/data control type register. There are several of these
2138 * and they all have the format address << 8 | data and bit 31 is polled for
2141 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2142 u32 offset, u8 data)
2144 u32 i, regvalue = 0;
2145 s32 ret_val = E1000_SUCCESS;
2147 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2149 /* Set up the address and data */
2150 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
2151 E1000_WRITE_REG(hw, reg, regvalue);
2153 /* Poll the ready bit to see if the MDI read completed */
2154 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
2156 regvalue = E1000_READ_REG(hw, reg);
2157 if (regvalue & E1000_GEN_CTL_READY)
2160 if (!(regvalue & E1000_GEN_CTL_READY)) {
2161 DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
2162 ret_val = -E1000_ERR_PHY;