1 /******************************************************************************
3 Copyright (c) 2001-2008, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ******************************************************************************/
35 #include "e1000_api.h"
38 * e1000_init_nvm_ops_generic - Initialize NVM function pointers
39 * @hw: pointer to the HW structure
41 * Setups up the function pointers to no-op functions
43 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
45 struct e1000_nvm_info *nvm = &hw->nvm;
46 DEBUGFUNC("e1000_init_nvm_ops_generic");
48 /* Initialize function pointers */
49 nvm->ops.init_params = e1000_null_ops_generic;
50 nvm->ops.acquire = e1000_null_ops_generic;
51 nvm->ops.read = e1000_null_read_nvm;
52 nvm->ops.release = e1000_null_nvm_generic;
53 nvm->ops.reload = e1000_reload_nvm_generic;
54 nvm->ops.update = e1000_null_ops_generic;
55 nvm->ops.valid_led_default = e1000_null_led_default;
56 nvm->ops.validate = e1000_null_ops_generic;
57 nvm->ops.write = e1000_null_write_nvm;
61 * e1000_null_nvm_read - No-op function, return 0
62 * @hw: pointer to the HW structure
64 s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
66 DEBUGFUNC("e1000_null_read_nvm");
71 * e1000_null_nvm_generic - No-op function, return void
72 * @hw: pointer to the HW structure
74 void e1000_null_nvm_generic(struct e1000_hw *hw)
76 DEBUGFUNC("e1000_null_nvm_generic");
81 * e1000_null_led_default - No-op function, return 0
82 * @hw: pointer to the HW structure
84 s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data)
86 DEBUGFUNC("e1000_null_led_default");
91 * e1000_null_write_nvm - No-op function, return 0
92 * @hw: pointer to the HW structure
94 s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
96 DEBUGFUNC("e1000_null_write_nvm");
101 * e1000_raise_eec_clk - Raise EEPROM clock
102 * @hw: pointer to the HW structure
103 * @eecd: pointer to the EEPROM
105 * Enable/Raise the EEPROM clock bit.
107 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
109 *eecd = *eecd | E1000_EECD_SK;
110 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
111 E1000_WRITE_FLUSH(hw);
112 usec_delay(hw->nvm.delay_usec);
116 * e1000_lower_eec_clk - Lower EEPROM clock
117 * @hw: pointer to the HW structure
118 * @eecd: pointer to the EEPROM
120 * Clear/Lower the EEPROM clock bit.
122 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
124 *eecd = *eecd & ~E1000_EECD_SK;
125 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
126 E1000_WRITE_FLUSH(hw);
127 usec_delay(hw->nvm.delay_usec);
131 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
132 * @hw: pointer to the HW structure
133 * @data: data to send to the EEPROM
134 * @count: number of bits to shift out
136 * We need to shift 'count' bits out to the EEPROM. So, the value in the
137 * "data" parameter will be shifted out to the EEPROM one bit at a time.
138 * In order to do this, "data" must be broken down into bits.
140 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
142 struct e1000_nvm_info *nvm = &hw->nvm;
143 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
146 DEBUGFUNC("e1000_shift_out_eec_bits");
148 mask = 0x01 << (count - 1);
149 if (nvm->type == e1000_nvm_eeprom_microwire)
150 eecd &= ~E1000_EECD_DO;
151 else if (nvm->type == e1000_nvm_eeprom_spi)
152 eecd |= E1000_EECD_DO;
155 eecd &= ~E1000_EECD_DI;
158 eecd |= E1000_EECD_DI;
160 E1000_WRITE_REG(hw, E1000_EECD, eecd);
161 E1000_WRITE_FLUSH(hw);
163 usec_delay(nvm->delay_usec);
165 e1000_raise_eec_clk(hw, &eecd);
166 e1000_lower_eec_clk(hw, &eecd);
171 eecd &= ~E1000_EECD_DI;
172 E1000_WRITE_REG(hw, E1000_EECD, eecd);
176 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
177 * @hw: pointer to the HW structure
178 * @count: number of bits to shift in
180 * In order to read a register from the EEPROM, we need to shift 'count' bits
181 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
182 * the EEPROM (setting the SK bit), and then reading the value of the data out
183 * "DO" bit. During this "shifting in" process the data in "DI" bit should
186 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
192 DEBUGFUNC("e1000_shift_in_eec_bits");
194 eecd = E1000_READ_REG(hw, E1000_EECD);
196 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
199 for (i = 0; i < count; i++) {
201 e1000_raise_eec_clk(hw, &eecd);
203 eecd = E1000_READ_REG(hw, E1000_EECD);
205 eecd &= ~E1000_EECD_DI;
206 if (eecd & E1000_EECD_DO)
209 e1000_lower_eec_clk(hw, &eecd);
216 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
217 * @hw: pointer to the HW structure
218 * @ee_reg: EEPROM flag for polling
220 * Polls the EEPROM status bit for either read or write completion based
221 * upon the value of 'ee_reg'.
223 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
225 u32 attempts = 100000;
227 s32 ret_val = -E1000_ERR_NVM;
229 DEBUGFUNC("e1000_poll_eerd_eewr_done");
231 for (i = 0; i < attempts; i++) {
232 if (ee_reg == E1000_NVM_POLL_READ)
233 reg = E1000_READ_REG(hw, E1000_EERD);
235 reg = E1000_READ_REG(hw, E1000_EEWR);
237 if (reg & E1000_NVM_RW_REG_DONE) {
238 ret_val = E1000_SUCCESS;
249 * e1000_acquire_nvm_generic - Generic request for access to EEPROM
250 * @hw: pointer to the HW structure
252 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
253 * Return successful if access grant bit set, else clear the request for
254 * EEPROM access and return -E1000_ERR_NVM (-1).
256 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
258 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
259 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
260 s32 ret_val = E1000_SUCCESS;
262 DEBUGFUNC("e1000_acquire_nvm_generic");
264 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
265 eecd = E1000_READ_REG(hw, E1000_EECD);
268 if (eecd & E1000_EECD_GNT)
271 eecd = E1000_READ_REG(hw, E1000_EECD);
276 eecd &= ~E1000_EECD_REQ;
277 E1000_WRITE_REG(hw, E1000_EECD, eecd);
278 DEBUGOUT("Could not acquire NVM grant\n");
279 ret_val = -E1000_ERR_NVM;
286 * e1000_standby_nvm - Return EEPROM to standby state
287 * @hw: pointer to the HW structure
289 * Return the EEPROM to a standby state.
291 static void e1000_standby_nvm(struct e1000_hw *hw)
293 struct e1000_nvm_info *nvm = &hw->nvm;
294 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
296 DEBUGFUNC("e1000_standby_nvm");
298 if (nvm->type == e1000_nvm_eeprom_microwire) {
299 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
300 E1000_WRITE_REG(hw, E1000_EECD, eecd);
301 E1000_WRITE_FLUSH(hw);
302 usec_delay(nvm->delay_usec);
304 e1000_raise_eec_clk(hw, &eecd);
307 eecd |= E1000_EECD_CS;
308 E1000_WRITE_REG(hw, E1000_EECD, eecd);
309 E1000_WRITE_FLUSH(hw);
310 usec_delay(nvm->delay_usec);
312 e1000_lower_eec_clk(hw, &eecd);
313 } else if (nvm->type == e1000_nvm_eeprom_spi) {
314 /* Toggle CS to flush commands */
315 eecd |= E1000_EECD_CS;
316 E1000_WRITE_REG(hw, E1000_EECD, eecd);
317 E1000_WRITE_FLUSH(hw);
318 usec_delay(nvm->delay_usec);
319 eecd &= ~E1000_EECD_CS;
320 E1000_WRITE_REG(hw, E1000_EECD, eecd);
321 E1000_WRITE_FLUSH(hw);
322 usec_delay(nvm->delay_usec);
327 * e1000_stop_nvm - Terminate EEPROM command
328 * @hw: pointer to the HW structure
330 * Terminates the current command by inverting the EEPROM's chip select pin.
332 void e1000_stop_nvm(struct e1000_hw *hw)
336 DEBUGFUNC("e1000_stop_nvm");
338 eecd = E1000_READ_REG(hw, E1000_EECD);
339 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
341 eecd |= E1000_EECD_CS;
342 e1000_lower_eec_clk(hw, &eecd);
343 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
344 /* CS on Microwire is active-high */
345 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
346 E1000_WRITE_REG(hw, E1000_EECD, eecd);
347 e1000_raise_eec_clk(hw, &eecd);
348 e1000_lower_eec_clk(hw, &eecd);
353 * e1000_release_nvm_generic - Release exclusive access to EEPROM
354 * @hw: pointer to the HW structure
356 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
358 void e1000_release_nvm_generic(struct e1000_hw *hw)
362 DEBUGFUNC("e1000_release_nvm_generic");
366 eecd = E1000_READ_REG(hw, E1000_EECD);
367 eecd &= ~E1000_EECD_REQ;
368 E1000_WRITE_REG(hw, E1000_EECD, eecd);
372 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
373 * @hw: pointer to the HW structure
375 * Setups the EEPROM for reading and writing.
377 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
379 struct e1000_nvm_info *nvm = &hw->nvm;
380 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
381 s32 ret_val = E1000_SUCCESS;
385 DEBUGFUNC("e1000_ready_nvm_eeprom");
387 if (nvm->type == e1000_nvm_eeprom_microwire) {
388 /* Clear SK and DI */
389 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
390 E1000_WRITE_REG(hw, E1000_EECD, eecd);
392 eecd |= E1000_EECD_CS;
393 E1000_WRITE_REG(hw, E1000_EECD, eecd);
394 } else if (nvm->type == e1000_nvm_eeprom_spi) {
395 /* Clear SK and CS */
396 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
397 E1000_WRITE_REG(hw, E1000_EECD, eecd);
399 timeout = NVM_MAX_RETRY_SPI;
402 * Read "Status Register" repeatedly until the LSB is cleared.
403 * The EEPROM will signal that the command has been completed
404 * by clearing bit 0 of the internal status register. If it's
405 * not cleared within 'timeout', then error out.
408 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
409 hw->nvm.opcode_bits);
410 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
411 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
415 e1000_standby_nvm(hw);
420 DEBUGOUT("SPI NVM Status error\n");
421 ret_val = -E1000_ERR_NVM;
431 * e1000_read_nvm_spi - Read EEPROM's using SPI
432 * @hw: pointer to the HW structure
433 * @offset: offset of word in the EEPROM to read
434 * @words: number of words to read
435 * @data: word read from the EEPROM
437 * Reads a 16 bit word from the EEPROM.
439 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
441 struct e1000_nvm_info *nvm = &hw->nvm;
445 u8 read_opcode = NVM_READ_OPCODE_SPI;
447 DEBUGFUNC("e1000_read_nvm_spi");
450 * A check for invalid values: offset too large, too many words,
451 * and not enough words.
453 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
455 DEBUGOUT("nvm parameter(s) out of bounds\n");
456 ret_val = -E1000_ERR_NVM;
460 ret_val = nvm->ops.acquire(hw);
464 ret_val = e1000_ready_nvm_eeprom(hw);
468 e1000_standby_nvm(hw);
470 if ((nvm->address_bits == 8) && (offset >= 128))
471 read_opcode |= NVM_A8_OPCODE_SPI;
473 /* Send the READ command (opcode + addr) */
474 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
475 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
478 * Read the data. SPI NVMs increment the address with each byte
479 * read and will roll over if reading beyond the end. This allows
480 * us to read the whole NVM from any offset
482 for (i = 0; i < words; i++) {
483 word_in = e1000_shift_in_eec_bits(hw, 16);
484 data[i] = (word_in >> 8) | (word_in << 8);
488 nvm->ops.release(hw);
495 * e1000_read_nvm_microwire - Reads EEPROM's using microwire
496 * @hw: pointer to the HW structure
497 * @offset: offset of word in the EEPROM to read
498 * @words: number of words to read
499 * @data: word read from the EEPROM
501 * Reads a 16 bit word from the EEPROM.
503 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
506 struct e1000_nvm_info *nvm = &hw->nvm;
509 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
511 DEBUGFUNC("e1000_read_nvm_microwire");
514 * A check for invalid values: offset too large, too many words,
515 * and not enough words.
517 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
519 DEBUGOUT("nvm parameter(s) out of bounds\n");
520 ret_val = -E1000_ERR_NVM;
524 ret_val = nvm->ops.acquire(hw);
528 ret_val = e1000_ready_nvm_eeprom(hw);
532 for (i = 0; i < words; i++) {
533 /* Send the READ command (opcode + addr) */
534 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
535 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
539 * Read the data. For microwire, each word requires the
540 * overhead of setup and tear-down.
542 data[i] = e1000_shift_in_eec_bits(hw, 16);
543 e1000_standby_nvm(hw);
547 nvm->ops.release(hw);
554 * e1000_read_nvm_eerd - Reads EEPROM using EERD register
555 * @hw: pointer to the HW structure
556 * @offset: offset of word in the EEPROM to read
557 * @words: number of words to read
558 * @data: word read from the EEPROM
560 * Reads a 16 bit word from the EEPROM using the EERD register.
562 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
564 struct e1000_nvm_info *nvm = &hw->nvm;
566 s32 ret_val = E1000_SUCCESS;
568 DEBUGFUNC("e1000_read_nvm_eerd");
571 * A check for invalid values: offset too large, too many words,
572 * too many words for the offset, and not enough words.
574 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
576 DEBUGOUT("nvm parameter(s) out of bounds\n");
577 ret_val = -E1000_ERR_NVM;
581 for (i = 0; i < words; i++) {
582 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
583 E1000_NVM_RW_REG_START;
585 E1000_WRITE_REG(hw, E1000_EERD, eerd);
586 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
590 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
591 E1000_NVM_RW_REG_DATA);
599 * e1000_write_nvm_spi - Write to EEPROM using SPI
600 * @hw: pointer to the HW structure
601 * @offset: offset within the EEPROM to be written to
602 * @words: number of words to write
603 * @data: 16 bit word(s) to be written to the EEPROM
605 * Writes data to EEPROM at offset using SPI interface.
607 * If e1000_update_nvm_checksum is not called after this function , the
608 * EEPROM will most likely contain an invalid checksum.
610 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
612 struct e1000_nvm_info *nvm = &hw->nvm;
616 DEBUGFUNC("e1000_write_nvm_spi");
619 * A check for invalid values: offset too large, too many words,
620 * and not enough words.
622 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
624 DEBUGOUT("nvm parameter(s) out of bounds\n");
625 ret_val = -E1000_ERR_NVM;
629 ret_val = nvm->ops.acquire(hw);
633 while (widx < words) {
634 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
636 ret_val = e1000_ready_nvm_eeprom(hw);
640 e1000_standby_nvm(hw);
642 /* Send the WRITE ENABLE command (8 bit opcode) */
643 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
646 e1000_standby_nvm(hw);
649 * Some SPI eeproms use the 8th address bit embedded in the
652 if ((nvm->address_bits == 8) && (offset >= 128))
653 write_opcode |= NVM_A8_OPCODE_SPI;
655 /* Send the Write command (8-bit opcode + addr) */
656 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
657 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
660 /* Loop to allow for up to whole page write of eeprom */
661 while (widx < words) {
662 u16 word_out = data[widx];
663 word_out = (word_out >> 8) | (word_out << 8);
664 e1000_shift_out_eec_bits(hw, word_out, 16);
667 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
668 e1000_standby_nvm(hw);
674 msec_delay(nvm->semaphore_delay);
676 nvm->ops.release(hw);
683 * e1000_write_nvm_microwire - Writes EEPROM using microwire
684 * @hw: pointer to the HW structure
685 * @offset: offset within the EEPROM to be written to
686 * @words: number of words to write
687 * @data: 16 bit word(s) to be written to the EEPROM
689 * Writes data to EEPROM at offset using microwire interface.
691 * If e1000_update_nvm_checksum is not called after this function , the
692 * EEPROM will most likely contain an invalid checksum.
694 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
697 struct e1000_nvm_info *nvm = &hw->nvm;
700 u16 words_written = 0;
703 DEBUGFUNC("e1000_write_nvm_microwire");
706 * A check for invalid values: offset too large, too many words,
707 * and not enough words.
709 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
711 DEBUGOUT("nvm parameter(s) out of bounds\n");
712 ret_val = -E1000_ERR_NVM;
716 ret_val = nvm->ops.acquire(hw);
720 ret_val = e1000_ready_nvm_eeprom(hw);
724 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
725 (u16)(nvm->opcode_bits + 2));
727 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
729 e1000_standby_nvm(hw);
731 while (words_written < words) {
732 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
735 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
738 e1000_shift_out_eec_bits(hw, data[words_written], 16);
740 e1000_standby_nvm(hw);
742 for (widx = 0; widx < 200; widx++) {
743 eecd = E1000_READ_REG(hw, E1000_EECD);
744 if (eecd & E1000_EECD_DO)
750 DEBUGOUT("NVM Write did not complete\n");
751 ret_val = -E1000_ERR_NVM;
755 e1000_standby_nvm(hw);
760 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
761 (u16)(nvm->opcode_bits + 2));
763 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
766 nvm->ops.release(hw);
773 * e1000_read_pba_num_generic - Read device part number
774 * @hw: pointer to the HW structure
775 * @pba_num: pointer to device part number
777 * Reads the product board assembly (PBA) number from the EEPROM and stores
778 * the value in pba_num.
780 s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
785 DEBUGFUNC("e1000_read_pba_num_generic");
787 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
789 DEBUGOUT("NVM Read Error\n");
792 *pba_num = (u32)(nvm_data << 16);
794 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
796 DEBUGOUT("NVM Read Error\n");
799 *pba_num |= nvm_data;
806 * e1000_read_mac_addr_generic - Read device MAC address
807 * @hw: pointer to the HW structure
809 * Reads the device MAC address from the EEPROM and stores the value.
810 * Since devices with two ports use the same EEPROM, we increment the
811 * last bit in the MAC address for the second port.
813 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
815 s32 ret_val = E1000_SUCCESS;
816 u16 offset, nvm_data, i;
818 DEBUGFUNC("e1000_read_mac_addr");
820 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
822 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
824 DEBUGOUT("NVM Read Error\n");
827 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
828 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
831 /* Flip last bit of mac address if we're on second port */
832 if (hw->bus.func == E1000_FUNC_1)
833 hw->mac.perm_addr[5] ^= 1;
835 for (i = 0; i < ETH_ADDR_LEN; i++)
836 hw->mac.addr[i] = hw->mac.perm_addr[i];
843 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
844 * @hw: pointer to the HW structure
846 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
847 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
849 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
851 s32 ret_val = E1000_SUCCESS;
855 DEBUGFUNC("e1000_validate_nvm_checksum_generic");
857 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
858 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
860 DEBUGOUT("NVM Read Error\n");
863 checksum += nvm_data;
866 if (checksum != (u16) NVM_SUM) {
867 DEBUGOUT("NVM Checksum Invalid\n");
868 ret_val = -E1000_ERR_NVM;
877 * e1000_update_nvm_checksum_generic - Update EEPROM checksum
878 * @hw: pointer to the HW structure
880 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
881 * up to the checksum. Then calculates the EEPROM checksum and writes the
882 * value to the EEPROM.
884 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
890 DEBUGFUNC("e1000_update_nvm_checksum");
892 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
893 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
895 DEBUGOUT("NVM Read Error while updating checksum.\n");
898 checksum += nvm_data;
900 checksum = (u16) NVM_SUM - checksum;
901 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
903 DEBUGOUT("NVM Write Error while updating checksum.\n");
911 * e1000_reload_nvm_generic - Reloads EEPROM
912 * @hw: pointer to the HW structure
914 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
915 * extended control register.
917 void e1000_reload_nvm_generic(struct e1000_hw *hw)
921 DEBUGFUNC("e1000_reload_nvm_generic");
924 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
925 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
926 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
927 E1000_WRITE_FLUSH(hw);