1 /******************************************************************************
3 Copyright (c) 2001-2013, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "e1000_api.h"
37 static void e1000_reload_nvm_generic(struct e1000_hw *hw);
40 * e1000_init_nvm_ops_generic - Initialize NVM function pointers
41 * @hw: pointer to the HW structure
43 * Setups up the function pointers to no-op functions
45 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
47 struct e1000_nvm_info *nvm = &hw->nvm;
48 DEBUGFUNC("e1000_init_nvm_ops_generic");
50 /* Initialize function pointers */
51 nvm->ops.init_params = e1000_null_ops_generic;
52 nvm->ops.acquire = e1000_null_ops_generic;
53 nvm->ops.read = e1000_null_read_nvm;
54 nvm->ops.release = e1000_null_nvm_generic;
55 nvm->ops.reload = e1000_reload_nvm_generic;
56 nvm->ops.update = e1000_null_ops_generic;
57 nvm->ops.valid_led_default = e1000_null_led_default;
58 nvm->ops.validate = e1000_null_ops_generic;
59 nvm->ops.write = e1000_null_write_nvm;
63 * e1000_null_nvm_read - No-op function, return 0
64 * @hw: pointer to the HW structure
66 s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
68 DEBUGFUNC("e1000_null_read_nvm");
73 * e1000_null_nvm_generic - No-op function, return void
74 * @hw: pointer to the HW structure
76 void e1000_null_nvm_generic(struct e1000_hw *hw)
78 DEBUGFUNC("e1000_null_nvm_generic");
83 * e1000_null_led_default - No-op function, return 0
84 * @hw: pointer to the HW structure
86 s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data)
88 DEBUGFUNC("e1000_null_led_default");
93 * e1000_null_write_nvm - No-op function, return 0
94 * @hw: pointer to the HW structure
96 s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
98 DEBUGFUNC("e1000_null_write_nvm");
103 * e1000_raise_eec_clk - Raise EEPROM clock
104 * @hw: pointer to the HW structure
105 * @eecd: pointer to the EEPROM
107 * Enable/Raise the EEPROM clock bit.
109 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
111 *eecd = *eecd | E1000_EECD_SK;
112 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
113 E1000_WRITE_FLUSH(hw);
114 usec_delay(hw->nvm.delay_usec);
118 * e1000_lower_eec_clk - Lower EEPROM clock
119 * @hw: pointer to the HW structure
120 * @eecd: pointer to the EEPROM
122 * Clear/Lower the EEPROM clock bit.
124 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
126 *eecd = *eecd & ~E1000_EECD_SK;
127 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
128 E1000_WRITE_FLUSH(hw);
129 usec_delay(hw->nvm.delay_usec);
133 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
134 * @hw: pointer to the HW structure
135 * @data: data to send to the EEPROM
136 * @count: number of bits to shift out
138 * We need to shift 'count' bits out to the EEPROM. So, the value in the
139 * "data" parameter will be shifted out to the EEPROM one bit at a time.
140 * In order to do this, "data" must be broken down into bits.
142 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
144 struct e1000_nvm_info *nvm = &hw->nvm;
145 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
148 DEBUGFUNC("e1000_shift_out_eec_bits");
150 mask = 0x01 << (count - 1);
151 if (nvm->type == e1000_nvm_eeprom_microwire)
152 eecd &= ~E1000_EECD_DO;
154 if (nvm->type == e1000_nvm_eeprom_spi)
155 eecd |= E1000_EECD_DO;
158 eecd &= ~E1000_EECD_DI;
161 eecd |= E1000_EECD_DI;
163 E1000_WRITE_REG(hw, E1000_EECD, eecd);
164 E1000_WRITE_FLUSH(hw);
166 usec_delay(nvm->delay_usec);
168 e1000_raise_eec_clk(hw, &eecd);
169 e1000_lower_eec_clk(hw, &eecd);
174 eecd &= ~E1000_EECD_DI;
175 E1000_WRITE_REG(hw, E1000_EECD, eecd);
179 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
180 * @hw: pointer to the HW structure
181 * @count: number of bits to shift in
183 * In order to read a register from the EEPROM, we need to shift 'count' bits
184 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
185 * the EEPROM (setting the SK bit), and then reading the value of the data out
186 * "DO" bit. During this "shifting in" process the data in "DI" bit should
189 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
195 DEBUGFUNC("e1000_shift_in_eec_bits");
197 eecd = E1000_READ_REG(hw, E1000_EECD);
199 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
202 for (i = 0; i < count; i++) {
204 e1000_raise_eec_clk(hw, &eecd);
206 eecd = E1000_READ_REG(hw, E1000_EECD);
208 eecd &= ~E1000_EECD_DI;
209 if (eecd & E1000_EECD_DO)
212 e1000_lower_eec_clk(hw, &eecd);
219 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
220 * @hw: pointer to the HW structure
221 * @ee_reg: EEPROM flag for polling
223 * Polls the EEPROM status bit for either read or write completion based
224 * upon the value of 'ee_reg'.
226 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
228 u32 attempts = 100000;
231 DEBUGFUNC("e1000_poll_eerd_eewr_done");
233 for (i = 0; i < attempts; i++) {
234 if (ee_reg == E1000_NVM_POLL_READ)
235 reg = E1000_READ_REG(hw, E1000_EERD);
237 reg = E1000_READ_REG(hw, E1000_EEWR);
239 if (reg & E1000_NVM_RW_REG_DONE)
240 return E1000_SUCCESS;
245 return -E1000_ERR_NVM;
249 * e1000_acquire_nvm_generic - Generic request for access to EEPROM
250 * @hw: pointer to the HW structure
252 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
253 * Return successful if access grant bit set, else clear the request for
254 * EEPROM access and return -E1000_ERR_NVM (-1).
256 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
258 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
259 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
261 DEBUGFUNC("e1000_acquire_nvm_generic");
263 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
264 eecd = E1000_READ_REG(hw, E1000_EECD);
267 if (eecd & E1000_EECD_GNT)
270 eecd = E1000_READ_REG(hw, E1000_EECD);
275 eecd &= ~E1000_EECD_REQ;
276 E1000_WRITE_REG(hw, E1000_EECD, eecd);
277 DEBUGOUT("Could not acquire NVM grant\n");
278 return -E1000_ERR_NVM;
281 return E1000_SUCCESS;
285 * e1000_standby_nvm - Return EEPROM to standby state
286 * @hw: pointer to the HW structure
288 * Return the EEPROM to a standby state.
290 static void e1000_standby_nvm(struct e1000_hw *hw)
292 struct e1000_nvm_info *nvm = &hw->nvm;
293 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
295 DEBUGFUNC("e1000_standby_nvm");
297 if (nvm->type == e1000_nvm_eeprom_microwire) {
298 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
299 E1000_WRITE_REG(hw, E1000_EECD, eecd);
300 E1000_WRITE_FLUSH(hw);
301 usec_delay(nvm->delay_usec);
303 e1000_raise_eec_clk(hw, &eecd);
306 eecd |= E1000_EECD_CS;
307 E1000_WRITE_REG(hw, E1000_EECD, eecd);
308 E1000_WRITE_FLUSH(hw);
309 usec_delay(nvm->delay_usec);
311 e1000_lower_eec_clk(hw, &eecd);
312 } else if (nvm->type == e1000_nvm_eeprom_spi) {
313 /* Toggle CS to flush commands */
314 eecd |= E1000_EECD_CS;
315 E1000_WRITE_REG(hw, E1000_EECD, eecd);
316 E1000_WRITE_FLUSH(hw);
317 usec_delay(nvm->delay_usec);
318 eecd &= ~E1000_EECD_CS;
319 E1000_WRITE_REG(hw, E1000_EECD, eecd);
320 E1000_WRITE_FLUSH(hw);
321 usec_delay(nvm->delay_usec);
326 * e1000_stop_nvm - Terminate EEPROM command
327 * @hw: pointer to the HW structure
329 * Terminates the current command by inverting the EEPROM's chip select pin.
331 void e1000_stop_nvm(struct e1000_hw *hw)
335 DEBUGFUNC("e1000_stop_nvm");
337 eecd = E1000_READ_REG(hw, E1000_EECD);
338 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
340 eecd |= E1000_EECD_CS;
341 e1000_lower_eec_clk(hw, &eecd);
342 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
343 /* CS on Microwire is active-high */
344 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
345 E1000_WRITE_REG(hw, E1000_EECD, eecd);
346 e1000_raise_eec_clk(hw, &eecd);
347 e1000_lower_eec_clk(hw, &eecd);
352 * e1000_release_nvm_generic - Release exclusive access to EEPROM
353 * @hw: pointer to the HW structure
355 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
357 void e1000_release_nvm_generic(struct e1000_hw *hw)
361 DEBUGFUNC("e1000_release_nvm_generic");
365 eecd = E1000_READ_REG(hw, E1000_EECD);
366 eecd &= ~E1000_EECD_REQ;
367 E1000_WRITE_REG(hw, E1000_EECD, eecd);
371 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
372 * @hw: pointer to the HW structure
374 * Setups the EEPROM for reading and writing.
376 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
378 struct e1000_nvm_info *nvm = &hw->nvm;
379 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
382 DEBUGFUNC("e1000_ready_nvm_eeprom");
384 if (nvm->type == e1000_nvm_eeprom_microwire) {
385 /* Clear SK and DI */
386 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
387 E1000_WRITE_REG(hw, E1000_EECD, eecd);
389 eecd |= E1000_EECD_CS;
390 E1000_WRITE_REG(hw, E1000_EECD, eecd);
391 } else if (nvm->type == e1000_nvm_eeprom_spi) {
392 u16 timeout = NVM_MAX_RETRY_SPI;
394 /* Clear SK and CS */
395 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
396 E1000_WRITE_REG(hw, E1000_EECD, eecd);
397 E1000_WRITE_FLUSH(hw);
400 /* Read "Status Register" repeatedly until the LSB is cleared.
401 * The EEPROM will signal that the command has been completed
402 * by clearing bit 0 of the internal status register. If it's
403 * not cleared within 'timeout', then error out.
406 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
407 hw->nvm.opcode_bits);
408 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
409 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
413 e1000_standby_nvm(hw);
418 DEBUGOUT("SPI NVM Status error\n");
419 return -E1000_ERR_NVM;
423 return E1000_SUCCESS;
427 * e1000_read_nvm_spi - Read EEPROM's using SPI
428 * @hw: pointer to the HW structure
429 * @offset: offset of word in the EEPROM to read
430 * @words: number of words to read
431 * @data: word read from the EEPROM
433 * Reads a 16 bit word from the EEPROM.
435 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
437 struct e1000_nvm_info *nvm = &hw->nvm;
441 u8 read_opcode = NVM_READ_OPCODE_SPI;
443 DEBUGFUNC("e1000_read_nvm_spi");
445 /* A check for invalid values: offset too large, too many words,
446 * and not enough words.
448 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
450 DEBUGOUT("nvm parameter(s) out of bounds\n");
451 return -E1000_ERR_NVM;
454 ret_val = nvm->ops.acquire(hw);
458 ret_val = e1000_ready_nvm_eeprom(hw);
462 e1000_standby_nvm(hw);
464 if ((nvm->address_bits == 8) && (offset >= 128))
465 read_opcode |= NVM_A8_OPCODE_SPI;
467 /* Send the READ command (opcode + addr) */
468 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
469 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
471 /* Read the data. SPI NVMs increment the address with each byte
472 * read and will roll over if reading beyond the end. This allows
473 * us to read the whole NVM from any offset
475 for (i = 0; i < words; i++) {
476 word_in = e1000_shift_in_eec_bits(hw, 16);
477 data[i] = (word_in >> 8) | (word_in << 8);
481 nvm->ops.release(hw);
487 * e1000_read_nvm_microwire - Reads EEPROM's using microwire
488 * @hw: pointer to the HW structure
489 * @offset: offset of word in the EEPROM to read
490 * @words: number of words to read
491 * @data: word read from the EEPROM
493 * Reads a 16 bit word from the EEPROM.
495 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
498 struct e1000_nvm_info *nvm = &hw->nvm;
501 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
503 DEBUGFUNC("e1000_read_nvm_microwire");
505 /* A check for invalid values: offset too large, too many words,
506 * and not enough words.
508 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
510 DEBUGOUT("nvm parameter(s) out of bounds\n");
511 return -E1000_ERR_NVM;
514 ret_val = nvm->ops.acquire(hw);
518 ret_val = e1000_ready_nvm_eeprom(hw);
522 for (i = 0; i < words; i++) {
523 /* Send the READ command (opcode + addr) */
524 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
525 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
528 /* Read the data. For microwire, each word requires the
529 * overhead of setup and tear-down.
531 data[i] = e1000_shift_in_eec_bits(hw, 16);
532 e1000_standby_nvm(hw);
536 nvm->ops.release(hw);
542 * e1000_read_nvm_eerd - Reads EEPROM using EERD register
543 * @hw: pointer to the HW structure
544 * @offset: offset of word in the EEPROM to read
545 * @words: number of words to read
546 * @data: word read from the EEPROM
548 * Reads a 16 bit word from the EEPROM using the EERD register.
550 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
552 struct e1000_nvm_info *nvm = &hw->nvm;
554 s32 ret_val = E1000_SUCCESS;
556 DEBUGFUNC("e1000_read_nvm_eerd");
558 /* A check for invalid values: offset too large, too many words,
559 * too many words for the offset, and not enough words.
561 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
563 DEBUGOUT("nvm parameter(s) out of bounds\n");
564 return -E1000_ERR_NVM;
567 for (i = 0; i < words; i++) {
568 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
569 E1000_NVM_RW_REG_START;
571 E1000_WRITE_REG(hw, E1000_EERD, eerd);
572 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
576 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
577 E1000_NVM_RW_REG_DATA);
584 * e1000_write_nvm_spi - Write to EEPROM using SPI
585 * @hw: pointer to the HW structure
586 * @offset: offset within the EEPROM to be written to
587 * @words: number of words to write
588 * @data: 16 bit word(s) to be written to the EEPROM
590 * Writes data to EEPROM at offset using SPI interface.
592 * If e1000_update_nvm_checksum is not called after this function , the
593 * EEPROM will most likely contain an invalid checksum.
595 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
597 struct e1000_nvm_info *nvm = &hw->nvm;
598 s32 ret_val = -E1000_ERR_NVM;
601 DEBUGFUNC("e1000_write_nvm_spi");
603 /* A check for invalid values: offset too large, too many words,
604 * and not enough words.
606 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
608 DEBUGOUT("nvm parameter(s) out of bounds\n");
609 return -E1000_ERR_NVM;
612 while (widx < words) {
613 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
615 ret_val = nvm->ops.acquire(hw);
619 ret_val = e1000_ready_nvm_eeprom(hw);
621 nvm->ops.release(hw);
625 e1000_standby_nvm(hw);
627 /* Send the WRITE ENABLE command (8 bit opcode) */
628 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
631 e1000_standby_nvm(hw);
633 /* Some SPI eeproms use the 8th address bit embedded in the
636 if ((nvm->address_bits == 8) && (offset >= 128))
637 write_opcode |= NVM_A8_OPCODE_SPI;
639 /* Send the Write command (8-bit opcode + addr) */
640 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
641 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
644 /* Loop to allow for up to whole page write of eeprom */
645 while (widx < words) {
646 u16 word_out = data[widx];
647 word_out = (word_out >> 8) | (word_out << 8);
648 e1000_shift_out_eec_bits(hw, word_out, 16);
651 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
652 e1000_standby_nvm(hw);
657 nvm->ops.release(hw);
664 * e1000_write_nvm_microwire - Writes EEPROM using microwire
665 * @hw: pointer to the HW structure
666 * @offset: offset within the EEPROM to be written to
667 * @words: number of words to write
668 * @data: 16 bit word(s) to be written to the EEPROM
670 * Writes data to EEPROM at offset using microwire interface.
672 * If e1000_update_nvm_checksum is not called after this function , the
673 * EEPROM will most likely contain an invalid checksum.
675 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
678 struct e1000_nvm_info *nvm = &hw->nvm;
681 u16 words_written = 0;
684 DEBUGFUNC("e1000_write_nvm_microwire");
686 /* A check for invalid values: offset too large, too many words,
687 * and not enough words.
689 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
691 DEBUGOUT("nvm parameter(s) out of bounds\n");
692 return -E1000_ERR_NVM;
695 ret_val = nvm->ops.acquire(hw);
699 ret_val = e1000_ready_nvm_eeprom(hw);
703 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
704 (u16)(nvm->opcode_bits + 2));
706 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
708 e1000_standby_nvm(hw);
710 while (words_written < words) {
711 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
714 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
717 e1000_shift_out_eec_bits(hw, data[words_written], 16);
719 e1000_standby_nvm(hw);
721 for (widx = 0; widx < 200; widx++) {
722 eecd = E1000_READ_REG(hw, E1000_EECD);
723 if (eecd & E1000_EECD_DO)
729 DEBUGOUT("NVM Write did not complete\n");
730 ret_val = -E1000_ERR_NVM;
734 e1000_standby_nvm(hw);
739 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
740 (u16)(nvm->opcode_bits + 2));
742 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
745 nvm->ops.release(hw);
751 * e1000_read_pba_string_generic - Read device part number
752 * @hw: pointer to the HW structure
753 * @pba_num: pointer to device part number
754 * @pba_num_size: size of part number buffer
756 * Reads the product board assembly (PBA) number from the EEPROM and stores
757 * the value in pba_num.
759 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
768 DEBUGFUNC("e1000_read_pba_string_generic");
770 if (pba_num == NULL) {
771 DEBUGOUT("PBA string buffer was null\n");
772 return -E1000_ERR_INVALID_ARGUMENT;
775 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
777 DEBUGOUT("NVM Read Error\n");
781 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
783 DEBUGOUT("NVM Read Error\n");
787 /* if nvm_data is not ptr guard the PBA must be in legacy format which
788 * means pba_ptr is actually our second data word for the PBA number
789 * and we can decode it into an ascii string
791 if (nvm_data != NVM_PBA_PTR_GUARD) {
792 DEBUGOUT("NVM PBA number is not stored as string\n");
794 /* make sure callers buffer is big enough to store the PBA */
795 if (pba_num_size < E1000_PBANUM_LENGTH) {
796 DEBUGOUT("PBA string buffer too small\n");
797 return E1000_ERR_NO_SPACE;
800 /* extract hex string from data and pba_ptr */
801 pba_num[0] = (nvm_data >> 12) & 0xF;
802 pba_num[1] = (nvm_data >> 8) & 0xF;
803 pba_num[2] = (nvm_data >> 4) & 0xF;
804 pba_num[3] = nvm_data & 0xF;
805 pba_num[4] = (pba_ptr >> 12) & 0xF;
806 pba_num[5] = (pba_ptr >> 8) & 0xF;
809 pba_num[8] = (pba_ptr >> 4) & 0xF;
810 pba_num[9] = pba_ptr & 0xF;
812 /* put a null character on the end of our string */
815 /* switch all the data but the '-' to hex char */
816 for (offset = 0; offset < 10; offset++) {
817 if (pba_num[offset] < 0xA)
818 pba_num[offset] += '0';
819 else if (pba_num[offset] < 0x10)
820 pba_num[offset] += 'A' - 0xA;
823 return E1000_SUCCESS;
826 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
828 DEBUGOUT("NVM Read Error\n");
832 if (length == 0xFFFF || length == 0) {
833 DEBUGOUT("NVM PBA number section invalid length\n");
834 return -E1000_ERR_NVM_PBA_SECTION;
836 /* check if pba_num buffer is big enough */
837 if (pba_num_size < (((u32)length * 2) - 1)) {
838 DEBUGOUT("PBA string buffer too small\n");
839 return -E1000_ERR_NO_SPACE;
842 /* trim pba length from start of string */
846 for (offset = 0; offset < length; offset++) {
847 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
849 DEBUGOUT("NVM Read Error\n");
852 pba_num[offset * 2] = (u8)(nvm_data >> 8);
853 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
855 pba_num[offset * 2] = '\0';
857 return E1000_SUCCESS;
861 * e1000_read_pba_length_generic - Read device part number length
862 * @hw: pointer to the HW structure
863 * @pba_num_size: size of part number buffer
865 * Reads the product board assembly (PBA) number length from the EEPROM and
866 * stores the value in pba_num_size.
868 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
875 DEBUGFUNC("e1000_read_pba_length_generic");
877 if (pba_num_size == NULL) {
878 DEBUGOUT("PBA buffer size was null\n");
879 return -E1000_ERR_INVALID_ARGUMENT;
882 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
884 DEBUGOUT("NVM Read Error\n");
888 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
890 DEBUGOUT("NVM Read Error\n");
894 /* if data is not ptr guard the PBA must be in legacy format */
895 if (nvm_data != NVM_PBA_PTR_GUARD) {
896 *pba_num_size = E1000_PBANUM_LENGTH;
897 return E1000_SUCCESS;
900 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
902 DEBUGOUT("NVM Read Error\n");
906 if (length == 0xFFFF || length == 0) {
907 DEBUGOUT("NVM PBA number section invalid length\n");
908 return -E1000_ERR_NVM_PBA_SECTION;
911 /* Convert from length in u16 values to u8 chars, add 1 for NULL,
912 * and subtract 2 because length field is included in length.
914 *pba_num_size = ((u32)length * 2) - 1;
916 return E1000_SUCCESS;
922 * @hw: pointer to the HW structure
923 * @eeprom_buf: optional pointer to EEPROM image
924 * @eeprom_buf_size: size of EEPROM image in words
925 * @max_pba_block_size: PBA block size limit
926 * @pba: pointer to output PBA structure
928 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
929 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
932 s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
933 u32 eeprom_buf_size, u16 max_pba_block_size,
934 struct e1000_pba *pba)
940 return -E1000_ERR_PARAM;
942 if (eeprom_buf == NULL) {
943 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2,
948 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
949 pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
950 pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
952 return -E1000_ERR_PARAM;
956 if (pba->word[0] == NVM_PBA_PTR_GUARD) {
957 if (pba->pba_block == NULL)
958 return -E1000_ERR_PARAM;
960 ret_val = e1000_get_pba_block_size(hw, eeprom_buf,
966 if (pba_block_size > max_pba_block_size)
967 return -E1000_ERR_PARAM;
969 if (eeprom_buf == NULL) {
970 ret_val = e1000_read_nvm(hw, pba->word[1],
976 if (eeprom_buf_size > (u32)(pba->word[1] +
977 pba->pba_block[0])) {
978 memcpy(pba->pba_block,
979 &eeprom_buf[pba->word[1]],
980 pba_block_size * sizeof(u16));
982 return -E1000_ERR_PARAM;
987 return E1000_SUCCESS;
991 * e1000_write_pba_raw
992 * @hw: pointer to the HW structure
993 * @eeprom_buf: optional pointer to EEPROM image
994 * @eeprom_buf_size: size of EEPROM image in words
995 * @pba: pointer to PBA structure
997 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
998 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
1001 s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
1002 u32 eeprom_buf_size, struct e1000_pba *pba)
1007 return -E1000_ERR_PARAM;
1009 if (eeprom_buf == NULL) {
1010 ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2,
1015 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1016 eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];
1017 eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];
1019 return -E1000_ERR_PARAM;
1023 if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1024 if (pba->pba_block == NULL)
1025 return -E1000_ERR_PARAM;
1027 if (eeprom_buf == NULL) {
1028 ret_val = e1000_write_nvm(hw, pba->word[1],
1034 if (eeprom_buf_size > (u32)(pba->word[1] +
1035 pba->pba_block[0])) {
1036 memcpy(&eeprom_buf[pba->word[1]],
1038 pba->pba_block[0] * sizeof(u16));
1040 return -E1000_ERR_PARAM;
1045 return E1000_SUCCESS;
1049 * e1000_get_pba_block_size
1050 * @hw: pointer to the HW structure
1051 * @eeprom_buf: optional pointer to EEPROM image
1052 * @eeprom_buf_size: size of EEPROM image in words
1053 * @pba_data_size: pointer to output variable
1055 * Returns the size of the PBA block in words. Function operates on EEPROM
1056 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
1060 s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,
1061 u32 eeprom_buf_size, u16 *pba_block_size)
1067 DEBUGFUNC("e1000_get_pba_block_size");
1069 if (eeprom_buf == NULL) {
1070 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);
1074 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1075 pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
1076 pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1078 return -E1000_ERR_PARAM;
1082 if (pba_word[0] == NVM_PBA_PTR_GUARD) {
1083 if (eeprom_buf == NULL) {
1084 ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1,
1089 if (eeprom_buf_size > pba_word[1])
1090 length = eeprom_buf[pba_word[1] + 0];
1092 return -E1000_ERR_PARAM;
1095 if (length == 0xFFFF || length == 0)
1096 return -E1000_ERR_NVM_PBA_SECTION;
1098 /* PBA number in legacy format, there is no PBA Block. */
1102 if (pba_block_size != NULL)
1103 *pba_block_size = length;
1105 return E1000_SUCCESS;
1109 * e1000_read_mac_addr_generic - Read device MAC address
1110 * @hw: pointer to the HW structure
1112 * Reads the device MAC address from the EEPROM and stores the value.
1113 * Since devices with two ports use the same EEPROM, we increment the
1114 * last bit in the MAC address for the second port.
1116 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
1122 rar_high = E1000_READ_REG(hw, E1000_RAH(0));
1123 rar_low = E1000_READ_REG(hw, E1000_RAL(0));
1125 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
1126 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
1128 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
1129 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
1131 for (i = 0; i < ETH_ADDR_LEN; i++)
1132 hw->mac.addr[i] = hw->mac.perm_addr[i];
1134 return E1000_SUCCESS;
1138 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
1139 * @hw: pointer to the HW structure
1141 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1142 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
1144 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
1150 DEBUGFUNC("e1000_validate_nvm_checksum_generic");
1152 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1153 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1155 DEBUGOUT("NVM Read Error\n");
1158 checksum += nvm_data;
1161 if (checksum != (u16) NVM_SUM) {
1162 DEBUGOUT("NVM Checksum Invalid\n");
1163 return -E1000_ERR_NVM;
1166 return E1000_SUCCESS;
1170 * e1000_update_nvm_checksum_generic - Update EEPROM checksum
1171 * @hw: pointer to the HW structure
1173 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
1174 * up to the checksum. Then calculates the EEPROM checksum and writes the
1175 * value to the EEPROM.
1177 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1183 DEBUGFUNC("e1000_update_nvm_checksum");
1185 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1186 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1188 DEBUGOUT("NVM Read Error while updating checksum.\n");
1191 checksum += nvm_data;
1193 checksum = (u16) NVM_SUM - checksum;
1194 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1196 DEBUGOUT("NVM Write Error while updating checksum.\n");
1202 * e1000_reload_nvm_generic - Reloads EEPROM
1203 * @hw: pointer to the HW structure
1205 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1206 * extended control register.
1208 static void e1000_reload_nvm_generic(struct e1000_hw *hw)
1212 DEBUGFUNC("e1000_reload_nvm_generic");
1215 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1216 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1217 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1218 E1000_WRITE_FLUSH(hw);