1 /******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "e1000_api.h"
37 static void e1000_reload_nvm_generic(struct e1000_hw *hw);
40 * e1000_init_nvm_ops_generic - Initialize NVM function pointers
41 * @hw: pointer to the HW structure
43 * Setups up the function pointers to no-op functions
45 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
47 struct e1000_nvm_info *nvm = &hw->nvm;
48 DEBUGFUNC("e1000_init_nvm_ops_generic");
50 /* Initialize function pointers */
51 nvm->ops.init_params = e1000_null_ops_generic;
52 nvm->ops.acquire = e1000_null_ops_generic;
53 nvm->ops.read = e1000_null_read_nvm;
54 nvm->ops.release = e1000_null_nvm_generic;
55 nvm->ops.reload = e1000_reload_nvm_generic;
56 nvm->ops.update = e1000_null_ops_generic;
57 nvm->ops.valid_led_default = e1000_null_led_default;
58 nvm->ops.validate = e1000_null_ops_generic;
59 nvm->ops.write = e1000_null_write_nvm;
63 * e1000_null_nvm_read - No-op function, return 0
64 * @hw: pointer to the HW structure
66 s32 e1000_null_read_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
67 u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
68 u16 E1000_UNUSEDARG *c)
70 DEBUGFUNC("e1000_null_read_nvm");
75 * e1000_null_nvm_generic - No-op function, return void
76 * @hw: pointer to the HW structure
78 void e1000_null_nvm_generic(struct e1000_hw E1000_UNUSEDARG *hw)
80 DEBUGFUNC("e1000_null_nvm_generic");
85 * e1000_null_led_default - No-op function, return 0
86 * @hw: pointer to the HW structure
88 s32 e1000_null_led_default(struct e1000_hw E1000_UNUSEDARG *hw,
89 u16 E1000_UNUSEDARG *data)
91 DEBUGFUNC("e1000_null_led_default");
96 * e1000_null_write_nvm - No-op function, return 0
97 * @hw: pointer to the HW structure
99 s32 e1000_null_write_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
100 u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
101 u16 E1000_UNUSEDARG *c)
103 DEBUGFUNC("e1000_null_write_nvm");
104 return E1000_SUCCESS;
108 * e1000_raise_eec_clk - Raise EEPROM clock
109 * @hw: pointer to the HW structure
110 * @eecd: pointer to the EEPROM
112 * Enable/Raise the EEPROM clock bit.
114 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
116 *eecd = *eecd | E1000_EECD_SK;
117 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
118 E1000_WRITE_FLUSH(hw);
119 usec_delay(hw->nvm.delay_usec);
123 * e1000_lower_eec_clk - Lower EEPROM clock
124 * @hw: pointer to the HW structure
125 * @eecd: pointer to the EEPROM
127 * Clear/Lower the EEPROM clock bit.
129 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
131 *eecd = *eecd & ~E1000_EECD_SK;
132 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
133 E1000_WRITE_FLUSH(hw);
134 usec_delay(hw->nvm.delay_usec);
138 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
139 * @hw: pointer to the HW structure
140 * @data: data to send to the EEPROM
141 * @count: number of bits to shift out
143 * We need to shift 'count' bits out to the EEPROM. So, the value in the
144 * "data" parameter will be shifted out to the EEPROM one bit at a time.
145 * In order to do this, "data" must be broken down into bits.
147 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
149 struct e1000_nvm_info *nvm = &hw->nvm;
150 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
153 DEBUGFUNC("e1000_shift_out_eec_bits");
155 mask = 0x01 << (count - 1);
156 if (nvm->type == e1000_nvm_eeprom_microwire)
157 eecd &= ~E1000_EECD_DO;
159 if (nvm->type == e1000_nvm_eeprom_spi)
160 eecd |= E1000_EECD_DO;
163 eecd &= ~E1000_EECD_DI;
166 eecd |= E1000_EECD_DI;
168 E1000_WRITE_REG(hw, E1000_EECD, eecd);
169 E1000_WRITE_FLUSH(hw);
171 usec_delay(nvm->delay_usec);
173 e1000_raise_eec_clk(hw, &eecd);
174 e1000_lower_eec_clk(hw, &eecd);
179 eecd &= ~E1000_EECD_DI;
180 E1000_WRITE_REG(hw, E1000_EECD, eecd);
184 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
185 * @hw: pointer to the HW structure
186 * @count: number of bits to shift in
188 * In order to read a register from the EEPROM, we need to shift 'count' bits
189 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
190 * the EEPROM (setting the SK bit), and then reading the value of the data out
191 * "DO" bit. During this "shifting in" process the data in "DI" bit should
194 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
200 DEBUGFUNC("e1000_shift_in_eec_bits");
202 eecd = E1000_READ_REG(hw, E1000_EECD);
204 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
207 for (i = 0; i < count; i++) {
209 e1000_raise_eec_clk(hw, &eecd);
211 eecd = E1000_READ_REG(hw, E1000_EECD);
213 eecd &= ~E1000_EECD_DI;
214 if (eecd & E1000_EECD_DO)
217 e1000_lower_eec_clk(hw, &eecd);
224 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
225 * @hw: pointer to the HW structure
226 * @ee_reg: EEPROM flag for polling
228 * Polls the EEPROM status bit for either read or write completion based
229 * upon the value of 'ee_reg'.
231 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
233 u32 attempts = 100000;
236 DEBUGFUNC("e1000_poll_eerd_eewr_done");
238 for (i = 0; i < attempts; i++) {
239 if (ee_reg == E1000_NVM_POLL_READ)
240 reg = E1000_READ_REG(hw, E1000_EERD);
242 reg = E1000_READ_REG(hw, E1000_EEWR);
244 if (reg & E1000_NVM_RW_REG_DONE)
245 return E1000_SUCCESS;
250 return -E1000_ERR_NVM;
254 * e1000_acquire_nvm_generic - Generic request for access to EEPROM
255 * @hw: pointer to the HW structure
257 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
258 * Return successful if access grant bit set, else clear the request for
259 * EEPROM access and return -E1000_ERR_NVM (-1).
261 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
263 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
264 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
266 DEBUGFUNC("e1000_acquire_nvm_generic");
268 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
269 eecd = E1000_READ_REG(hw, E1000_EECD);
272 if (eecd & E1000_EECD_GNT)
275 eecd = E1000_READ_REG(hw, E1000_EECD);
280 eecd &= ~E1000_EECD_REQ;
281 E1000_WRITE_REG(hw, E1000_EECD, eecd);
282 DEBUGOUT("Could not acquire NVM grant\n");
283 return -E1000_ERR_NVM;
286 return E1000_SUCCESS;
290 * e1000_standby_nvm - Return EEPROM to standby state
291 * @hw: pointer to the HW structure
293 * Return the EEPROM to a standby state.
295 static void e1000_standby_nvm(struct e1000_hw *hw)
297 struct e1000_nvm_info *nvm = &hw->nvm;
298 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
300 DEBUGFUNC("e1000_standby_nvm");
302 if (nvm->type == e1000_nvm_eeprom_microwire) {
303 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
304 E1000_WRITE_REG(hw, E1000_EECD, eecd);
305 E1000_WRITE_FLUSH(hw);
306 usec_delay(nvm->delay_usec);
308 e1000_raise_eec_clk(hw, &eecd);
311 eecd |= E1000_EECD_CS;
312 E1000_WRITE_REG(hw, E1000_EECD, eecd);
313 E1000_WRITE_FLUSH(hw);
314 usec_delay(nvm->delay_usec);
316 e1000_lower_eec_clk(hw, &eecd);
317 } else if (nvm->type == e1000_nvm_eeprom_spi) {
318 /* Toggle CS to flush commands */
319 eecd |= E1000_EECD_CS;
320 E1000_WRITE_REG(hw, E1000_EECD, eecd);
321 E1000_WRITE_FLUSH(hw);
322 usec_delay(nvm->delay_usec);
323 eecd &= ~E1000_EECD_CS;
324 E1000_WRITE_REG(hw, E1000_EECD, eecd);
325 E1000_WRITE_FLUSH(hw);
326 usec_delay(nvm->delay_usec);
331 * e1000_stop_nvm - Terminate EEPROM command
332 * @hw: pointer to the HW structure
334 * Terminates the current command by inverting the EEPROM's chip select pin.
336 void e1000_stop_nvm(struct e1000_hw *hw)
340 DEBUGFUNC("e1000_stop_nvm");
342 eecd = E1000_READ_REG(hw, E1000_EECD);
343 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
345 eecd |= E1000_EECD_CS;
346 e1000_lower_eec_clk(hw, &eecd);
347 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
348 /* CS on Microwire is active-high */
349 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
350 E1000_WRITE_REG(hw, E1000_EECD, eecd);
351 e1000_raise_eec_clk(hw, &eecd);
352 e1000_lower_eec_clk(hw, &eecd);
357 * e1000_release_nvm_generic - Release exclusive access to EEPROM
358 * @hw: pointer to the HW structure
360 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
362 void e1000_release_nvm_generic(struct e1000_hw *hw)
366 DEBUGFUNC("e1000_release_nvm_generic");
370 eecd = E1000_READ_REG(hw, E1000_EECD);
371 eecd &= ~E1000_EECD_REQ;
372 E1000_WRITE_REG(hw, E1000_EECD, eecd);
376 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
377 * @hw: pointer to the HW structure
379 * Setups the EEPROM for reading and writing.
381 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
383 struct e1000_nvm_info *nvm = &hw->nvm;
384 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
387 DEBUGFUNC("e1000_ready_nvm_eeprom");
389 if (nvm->type == e1000_nvm_eeprom_microwire) {
390 /* Clear SK and DI */
391 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
392 E1000_WRITE_REG(hw, E1000_EECD, eecd);
394 eecd |= E1000_EECD_CS;
395 E1000_WRITE_REG(hw, E1000_EECD, eecd);
396 } else if (nvm->type == e1000_nvm_eeprom_spi) {
397 u16 timeout = NVM_MAX_RETRY_SPI;
399 /* Clear SK and CS */
400 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
401 E1000_WRITE_REG(hw, E1000_EECD, eecd);
402 E1000_WRITE_FLUSH(hw);
405 /* Read "Status Register" repeatedly until the LSB is cleared.
406 * The EEPROM will signal that the command has been completed
407 * by clearing bit 0 of the internal status register. If it's
408 * not cleared within 'timeout', then error out.
411 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
412 hw->nvm.opcode_bits);
413 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
414 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
418 e1000_standby_nvm(hw);
423 DEBUGOUT("SPI NVM Status error\n");
424 return -E1000_ERR_NVM;
428 return E1000_SUCCESS;
432 * e1000_read_nvm_spi - Read EEPROM's using SPI
433 * @hw: pointer to the HW structure
434 * @offset: offset of word in the EEPROM to read
435 * @words: number of words to read
436 * @data: word read from the EEPROM
438 * Reads a 16 bit word from the EEPROM.
440 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
442 struct e1000_nvm_info *nvm = &hw->nvm;
446 u8 read_opcode = NVM_READ_OPCODE_SPI;
448 DEBUGFUNC("e1000_read_nvm_spi");
450 /* A check for invalid values: offset too large, too many words,
451 * and not enough words.
453 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
455 DEBUGOUT("nvm parameter(s) out of bounds\n");
456 return -E1000_ERR_NVM;
459 ret_val = nvm->ops.acquire(hw);
463 ret_val = e1000_ready_nvm_eeprom(hw);
467 e1000_standby_nvm(hw);
469 if ((nvm->address_bits == 8) && (offset >= 128))
470 read_opcode |= NVM_A8_OPCODE_SPI;
472 /* Send the READ command (opcode + addr) */
473 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
474 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
476 /* Read the data. SPI NVMs increment the address with each byte
477 * read and will roll over if reading beyond the end. This allows
478 * us to read the whole NVM from any offset
480 for (i = 0; i < words; i++) {
481 word_in = e1000_shift_in_eec_bits(hw, 16);
482 data[i] = (word_in >> 8) | (word_in << 8);
486 nvm->ops.release(hw);
492 * e1000_read_nvm_microwire - Reads EEPROM's using microwire
493 * @hw: pointer to the HW structure
494 * @offset: offset of word in the EEPROM to read
495 * @words: number of words to read
496 * @data: word read from the EEPROM
498 * Reads a 16 bit word from the EEPROM.
500 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
503 struct e1000_nvm_info *nvm = &hw->nvm;
506 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
508 DEBUGFUNC("e1000_read_nvm_microwire");
510 /* A check for invalid values: offset too large, too many words,
511 * and not enough words.
513 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
515 DEBUGOUT("nvm parameter(s) out of bounds\n");
516 return -E1000_ERR_NVM;
519 ret_val = nvm->ops.acquire(hw);
523 ret_val = e1000_ready_nvm_eeprom(hw);
527 for (i = 0; i < words; i++) {
528 /* Send the READ command (opcode + addr) */
529 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
530 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
533 /* Read the data. For microwire, each word requires the
534 * overhead of setup and tear-down.
536 data[i] = e1000_shift_in_eec_bits(hw, 16);
537 e1000_standby_nvm(hw);
541 nvm->ops.release(hw);
547 * e1000_read_nvm_eerd - Reads EEPROM using EERD register
548 * @hw: pointer to the HW structure
549 * @offset: offset of word in the EEPROM to read
550 * @words: number of words to read
551 * @data: word read from the EEPROM
553 * Reads a 16 bit word from the EEPROM using the EERD register.
555 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
557 struct e1000_nvm_info *nvm = &hw->nvm;
559 s32 ret_val = E1000_SUCCESS;
561 DEBUGFUNC("e1000_read_nvm_eerd");
563 /* A check for invalid values: offset too large, too many words,
564 * too many words for the offset, and not enough words.
566 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
568 DEBUGOUT("nvm parameter(s) out of bounds\n");
569 return -E1000_ERR_NVM;
572 for (i = 0; i < words; i++) {
573 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
574 E1000_NVM_RW_REG_START;
576 E1000_WRITE_REG(hw, E1000_EERD, eerd);
577 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
581 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
582 E1000_NVM_RW_REG_DATA);
586 DEBUGOUT1("NVM read error: %d\n", ret_val);
592 * e1000_write_nvm_spi - Write to EEPROM using SPI
593 * @hw: pointer to the HW structure
594 * @offset: offset within the EEPROM to be written to
595 * @words: number of words to write
596 * @data: 16 bit word(s) to be written to the EEPROM
598 * Writes data to EEPROM at offset using SPI interface.
600 * If e1000_update_nvm_checksum is not called after this function , the
601 * EEPROM will most likely contain an invalid checksum.
603 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
605 struct e1000_nvm_info *nvm = &hw->nvm;
606 s32 ret_val = -E1000_ERR_NVM;
609 DEBUGFUNC("e1000_write_nvm_spi");
611 /* A check for invalid values: offset too large, too many words,
612 * and not enough words.
614 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
616 DEBUGOUT("nvm parameter(s) out of bounds\n");
617 return -E1000_ERR_NVM;
620 while (widx < words) {
621 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
623 ret_val = nvm->ops.acquire(hw);
627 ret_val = e1000_ready_nvm_eeprom(hw);
629 nvm->ops.release(hw);
633 e1000_standby_nvm(hw);
635 /* Send the WRITE ENABLE command (8 bit opcode) */
636 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
639 e1000_standby_nvm(hw);
641 /* Some SPI eeproms use the 8th address bit embedded in the
644 if ((nvm->address_bits == 8) && (offset >= 128))
645 write_opcode |= NVM_A8_OPCODE_SPI;
647 /* Send the Write command (8-bit opcode + addr) */
648 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
649 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
652 /* Loop to allow for up to whole page write of eeprom */
653 while (widx < words) {
654 u16 word_out = data[widx];
655 word_out = (word_out >> 8) | (word_out << 8);
656 e1000_shift_out_eec_bits(hw, word_out, 16);
659 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
660 e1000_standby_nvm(hw);
665 nvm->ops.release(hw);
672 * e1000_write_nvm_microwire - Writes EEPROM using microwire
673 * @hw: pointer to the HW structure
674 * @offset: offset within the EEPROM to be written to
675 * @words: number of words to write
676 * @data: 16 bit word(s) to be written to the EEPROM
678 * Writes data to EEPROM at offset using microwire interface.
680 * If e1000_update_nvm_checksum is not called after this function , the
681 * EEPROM will most likely contain an invalid checksum.
683 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
686 struct e1000_nvm_info *nvm = &hw->nvm;
689 u16 words_written = 0;
692 DEBUGFUNC("e1000_write_nvm_microwire");
694 /* A check for invalid values: offset too large, too many words,
695 * and not enough words.
697 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
699 DEBUGOUT("nvm parameter(s) out of bounds\n");
700 return -E1000_ERR_NVM;
703 ret_val = nvm->ops.acquire(hw);
707 ret_val = e1000_ready_nvm_eeprom(hw);
711 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
712 (u16)(nvm->opcode_bits + 2));
714 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
716 e1000_standby_nvm(hw);
718 while (words_written < words) {
719 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
722 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
725 e1000_shift_out_eec_bits(hw, data[words_written], 16);
727 e1000_standby_nvm(hw);
729 for (widx = 0; widx < 200; widx++) {
730 eecd = E1000_READ_REG(hw, E1000_EECD);
731 if (eecd & E1000_EECD_DO)
737 DEBUGOUT("NVM Write did not complete\n");
738 ret_val = -E1000_ERR_NVM;
742 e1000_standby_nvm(hw);
747 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
748 (u16)(nvm->opcode_bits + 2));
750 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
753 nvm->ops.release(hw);
759 * e1000_read_pba_string_generic - Read device part number
760 * @hw: pointer to the HW structure
761 * @pba_num: pointer to device part number
762 * @pba_num_size: size of part number buffer
764 * Reads the product board assembly (PBA) number from the EEPROM and stores
765 * the value in pba_num.
767 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
776 DEBUGFUNC("e1000_read_pba_string_generic");
778 if ((hw->mac.type >= e1000_i210) &&
779 !e1000_get_flash_presence_i210(hw)) {
780 DEBUGOUT("Flashless no PBA string\n");
781 return -E1000_ERR_NVM_PBA_SECTION;
784 if (pba_num == NULL) {
785 DEBUGOUT("PBA string buffer was null\n");
786 return -E1000_ERR_INVALID_ARGUMENT;
789 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
791 DEBUGOUT("NVM Read Error\n");
795 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
797 DEBUGOUT("NVM Read Error\n");
801 /* if nvm_data is not ptr guard the PBA must be in legacy format which
802 * means pba_ptr is actually our second data word for the PBA number
803 * and we can decode it into an ascii string
805 if (nvm_data != NVM_PBA_PTR_GUARD) {
806 DEBUGOUT("NVM PBA number is not stored as string\n");
808 /* make sure callers buffer is big enough to store the PBA */
809 if (pba_num_size < E1000_PBANUM_LENGTH) {
810 DEBUGOUT("PBA string buffer too small\n");
811 return E1000_ERR_NO_SPACE;
814 /* extract hex string from data and pba_ptr */
815 pba_num[0] = (nvm_data >> 12) & 0xF;
816 pba_num[1] = (nvm_data >> 8) & 0xF;
817 pba_num[2] = (nvm_data >> 4) & 0xF;
818 pba_num[3] = nvm_data & 0xF;
819 pba_num[4] = (pba_ptr >> 12) & 0xF;
820 pba_num[5] = (pba_ptr >> 8) & 0xF;
823 pba_num[8] = (pba_ptr >> 4) & 0xF;
824 pba_num[9] = pba_ptr & 0xF;
826 /* put a null character on the end of our string */
829 /* switch all the data but the '-' to hex char */
830 for (offset = 0; offset < 10; offset++) {
831 if (pba_num[offset] < 0xA)
832 pba_num[offset] += '0';
833 else if (pba_num[offset] < 0x10)
834 pba_num[offset] += 'A' - 0xA;
837 return E1000_SUCCESS;
840 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
842 DEBUGOUT("NVM Read Error\n");
846 if (length == 0xFFFF || length == 0) {
847 DEBUGOUT("NVM PBA number section invalid length\n");
848 return -E1000_ERR_NVM_PBA_SECTION;
850 /* check if pba_num buffer is big enough */
851 if (pba_num_size < (((u32)length * 2) - 1)) {
852 DEBUGOUT("PBA string buffer too small\n");
853 return -E1000_ERR_NO_SPACE;
856 /* trim pba length from start of string */
860 for (offset = 0; offset < length; offset++) {
861 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
863 DEBUGOUT("NVM Read Error\n");
866 pba_num[offset * 2] = (u8)(nvm_data >> 8);
867 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
869 pba_num[offset * 2] = '\0';
871 return E1000_SUCCESS;
875 * e1000_read_pba_length_generic - Read device part number length
876 * @hw: pointer to the HW structure
877 * @pba_num_size: size of part number buffer
879 * Reads the product board assembly (PBA) number length from the EEPROM and
880 * stores the value in pba_num_size.
882 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
889 DEBUGFUNC("e1000_read_pba_length_generic");
891 if (pba_num_size == NULL) {
892 DEBUGOUT("PBA buffer size was null\n");
893 return -E1000_ERR_INVALID_ARGUMENT;
896 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
898 DEBUGOUT("NVM Read Error\n");
902 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
904 DEBUGOUT("NVM Read Error\n");
908 /* if data is not ptr guard the PBA must be in legacy format */
909 if (nvm_data != NVM_PBA_PTR_GUARD) {
910 *pba_num_size = E1000_PBANUM_LENGTH;
911 return E1000_SUCCESS;
914 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
916 DEBUGOUT("NVM Read Error\n");
920 if (length == 0xFFFF || length == 0) {
921 DEBUGOUT("NVM PBA number section invalid length\n");
922 return -E1000_ERR_NVM_PBA_SECTION;
925 /* Convert from length in u16 values to u8 chars, add 1 for NULL,
926 * and subtract 2 because length field is included in length.
928 *pba_num_size = ((u32)length * 2) - 1;
930 return E1000_SUCCESS;
936 * @hw: pointer to the HW structure
937 * @eeprom_buf: optional pointer to EEPROM image
938 * @eeprom_buf_size: size of EEPROM image in words
939 * @max_pba_block_size: PBA block size limit
940 * @pba: pointer to output PBA structure
942 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
943 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
946 s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
947 u32 eeprom_buf_size, u16 max_pba_block_size,
948 struct e1000_pba *pba)
954 return -E1000_ERR_PARAM;
956 if (eeprom_buf == NULL) {
957 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2,
962 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
963 pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
964 pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
966 return -E1000_ERR_PARAM;
970 if (pba->word[0] == NVM_PBA_PTR_GUARD) {
971 if (pba->pba_block == NULL)
972 return -E1000_ERR_PARAM;
974 ret_val = e1000_get_pba_block_size(hw, eeprom_buf,
980 if (pba_block_size > max_pba_block_size)
981 return -E1000_ERR_PARAM;
983 if (eeprom_buf == NULL) {
984 ret_val = e1000_read_nvm(hw, pba->word[1],
990 if (eeprom_buf_size > (u32)(pba->word[1] +
992 memcpy(pba->pba_block,
993 &eeprom_buf[pba->word[1]],
994 pba_block_size * sizeof(u16));
996 return -E1000_ERR_PARAM;
1001 return E1000_SUCCESS;
1005 * e1000_write_pba_raw
1006 * @hw: pointer to the HW structure
1007 * @eeprom_buf: optional pointer to EEPROM image
1008 * @eeprom_buf_size: size of EEPROM image in words
1009 * @pba: pointer to PBA structure
1011 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
1012 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
1015 s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
1016 u32 eeprom_buf_size, struct e1000_pba *pba)
1021 return -E1000_ERR_PARAM;
1023 if (eeprom_buf == NULL) {
1024 ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2,
1029 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1030 eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];
1031 eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];
1033 return -E1000_ERR_PARAM;
1037 if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1038 if (pba->pba_block == NULL)
1039 return -E1000_ERR_PARAM;
1041 if (eeprom_buf == NULL) {
1042 ret_val = e1000_write_nvm(hw, pba->word[1],
1048 if (eeprom_buf_size > (u32)(pba->word[1] +
1049 pba->pba_block[0])) {
1050 memcpy(&eeprom_buf[pba->word[1]],
1052 pba->pba_block[0] * sizeof(u16));
1054 return -E1000_ERR_PARAM;
1059 return E1000_SUCCESS;
1063 * e1000_get_pba_block_size
1064 * @hw: pointer to the HW structure
1065 * @eeprom_buf: optional pointer to EEPROM image
1066 * @eeprom_buf_size: size of EEPROM image in words
1067 * @pba_data_size: pointer to output variable
1069 * Returns the size of the PBA block in words. Function operates on EEPROM
1070 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
1074 s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,
1075 u32 eeprom_buf_size, u16 *pba_block_size)
1081 DEBUGFUNC("e1000_get_pba_block_size");
1083 if (eeprom_buf == NULL) {
1084 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);
1088 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1089 pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
1090 pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1092 return -E1000_ERR_PARAM;
1096 if (pba_word[0] == NVM_PBA_PTR_GUARD) {
1097 if (eeprom_buf == NULL) {
1098 ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1,
1103 if (eeprom_buf_size > pba_word[1])
1104 length = eeprom_buf[pba_word[1] + 0];
1106 return -E1000_ERR_PARAM;
1109 if (length == 0xFFFF || length == 0)
1110 return -E1000_ERR_NVM_PBA_SECTION;
1112 /* PBA number in legacy format, there is no PBA Block. */
1116 if (pba_block_size != NULL)
1117 *pba_block_size = length;
1119 return E1000_SUCCESS;
1123 * e1000_read_mac_addr_generic - Read device MAC address
1124 * @hw: pointer to the HW structure
1126 * Reads the device MAC address from the EEPROM and stores the value.
1127 * Since devices with two ports use the same EEPROM, we increment the
1128 * last bit in the MAC address for the second port.
1130 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
1136 rar_high = E1000_READ_REG(hw, E1000_RAH(0));
1137 rar_low = E1000_READ_REG(hw, E1000_RAL(0));
1139 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
1140 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
1142 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
1143 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
1145 for (i = 0; i < ETH_ADDR_LEN; i++)
1146 hw->mac.addr[i] = hw->mac.perm_addr[i];
1148 return E1000_SUCCESS;
1152 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
1153 * @hw: pointer to the HW structure
1155 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1156 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
1158 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
1164 DEBUGFUNC("e1000_validate_nvm_checksum_generic");
1166 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1167 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1169 DEBUGOUT("NVM Read Error\n");
1172 checksum += nvm_data;
1175 if (checksum != (u16) NVM_SUM) {
1176 DEBUGOUT("NVM Checksum Invalid\n");
1177 return -E1000_ERR_NVM;
1180 return E1000_SUCCESS;
1184 * e1000_update_nvm_checksum_generic - Update EEPROM checksum
1185 * @hw: pointer to the HW structure
1187 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
1188 * up to the checksum. Then calculates the EEPROM checksum and writes the
1189 * value to the EEPROM.
1191 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1197 DEBUGFUNC("e1000_update_nvm_checksum");
1199 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1200 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1202 DEBUGOUT("NVM Read Error while updating checksum.\n");
1205 checksum += nvm_data;
1207 checksum = (u16) NVM_SUM - checksum;
1208 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1210 DEBUGOUT("NVM Write Error while updating checksum.\n");
1216 * e1000_reload_nvm_generic - Reloads EEPROM
1217 * @hw: pointer to the HW structure
1219 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1220 * extended control register.
1222 static void e1000_reload_nvm_generic(struct e1000_hw *hw)
1226 DEBUGFUNC("e1000_reload_nvm_generic");
1229 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1230 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1231 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1232 E1000_WRITE_FLUSH(hw);