1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
10 1. Redistributions of source code must retain the above copyright notice,
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14 notice, this list of conditions and the following disclaimer in the
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19 this software without specific prior written permission.
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33 ******************************************************************************/
36 #include "e1000_api.h"
38 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
39 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
40 u16 *data, bool read, bool page_set);
41 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
42 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
43 u16 *data, bool read);
45 /* Cable length tables */
46 static const u16 e1000_m88_cable_length_table[] = {
47 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
48 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
49 (sizeof(e1000_m88_cable_length_table) / \
50 sizeof(e1000_m88_cable_length_table[0]))
52 static const u16 e1000_igp_2_cable_length_table[] = {
53 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
54 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
55 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
56 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
57 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
58 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
59 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
61 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
62 (sizeof(e1000_igp_2_cable_length_table) / \
63 sizeof(e1000_igp_2_cable_length_table[0]))
66 * e1000_init_phy_ops_generic - Initialize PHY function pointers
67 * @hw: pointer to the HW structure
69 * Setups up the function pointers to no-op functions
71 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
73 struct e1000_phy_info *phy = &hw->phy;
74 DEBUGFUNC("e1000_init_phy_ops_generic");
76 /* Initialize function pointers */
77 phy->ops.init_params = e1000_null_ops_generic;
78 phy->ops.acquire = e1000_null_ops_generic;
79 phy->ops.check_polarity = e1000_null_ops_generic;
80 phy->ops.check_reset_block = e1000_null_ops_generic;
81 phy->ops.commit = e1000_null_ops_generic;
82 phy->ops.force_speed_duplex = e1000_null_ops_generic;
83 phy->ops.get_cfg_done = e1000_null_ops_generic;
84 phy->ops.get_cable_length = e1000_null_ops_generic;
85 phy->ops.get_info = e1000_null_ops_generic;
86 phy->ops.set_page = e1000_null_set_page;
87 phy->ops.read_reg = e1000_null_read_reg;
88 phy->ops.read_reg_locked = e1000_null_read_reg;
89 phy->ops.read_reg_page = e1000_null_read_reg;
90 phy->ops.release = e1000_null_phy_generic;
91 phy->ops.reset = e1000_null_ops_generic;
92 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
93 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
94 phy->ops.write_reg = e1000_null_write_reg;
95 phy->ops.write_reg_locked = e1000_null_write_reg;
96 phy->ops.write_reg_page = e1000_null_write_reg;
97 phy->ops.power_up = e1000_null_phy_generic;
98 phy->ops.power_down = e1000_null_phy_generic;
99 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
100 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
101 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
105 * e1000_null_set_page - No-op function, return 0
106 * @hw: pointer to the HW structure
107 * @data: dummy variable
109 s32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw,
110 u16 E1000_UNUSEDARG data)
112 DEBUGFUNC("e1000_null_set_page");
113 return E1000_SUCCESS;
117 * e1000_null_read_reg - No-op function, return 0
118 * @hw: pointer to the HW structure
119 * @offset: dummy variable
120 * @data: dummy variable
122 s32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw,
123 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data)
125 DEBUGFUNC("e1000_null_read_reg");
126 return E1000_SUCCESS;
130 * e1000_null_phy_generic - No-op function, return void
131 * @hw: pointer to the HW structure
133 void e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw)
135 DEBUGFUNC("e1000_null_phy_generic");
140 * e1000_null_lplu_state - No-op function, return 0
141 * @hw: pointer to the HW structure
142 * @active: dummy variable
144 s32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw,
145 bool E1000_UNUSEDARG active)
147 DEBUGFUNC("e1000_null_lplu_state");
148 return E1000_SUCCESS;
152 * e1000_null_write_reg - No-op function, return 0
153 * @hw: pointer to the HW structure
154 * @offset: dummy variable
155 * @data: dummy variable
157 s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw,
158 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data)
160 DEBUGFUNC("e1000_null_write_reg");
161 return E1000_SUCCESS;
165 * e1000_read_i2c_byte_null - No-op function, return 0
166 * @hw: pointer to hardware structure
167 * @byte_offset: byte offset to write
168 * @dev_addr: device address
169 * @data: data value read
172 s32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
173 u8 E1000_UNUSEDARG byte_offset,
174 u8 E1000_UNUSEDARG dev_addr,
175 u8 E1000_UNUSEDARG *data)
177 DEBUGFUNC("e1000_read_i2c_byte_null");
178 return E1000_SUCCESS;
182 * e1000_write_i2c_byte_null - No-op function, return 0
183 * @hw: pointer to hardware structure
184 * @byte_offset: byte offset to write
185 * @dev_addr: device address
186 * @data: data value to write
189 s32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
190 u8 E1000_UNUSEDARG byte_offset,
191 u8 E1000_UNUSEDARG dev_addr,
192 u8 E1000_UNUSEDARG data)
194 DEBUGFUNC("e1000_write_i2c_byte_null");
195 return E1000_SUCCESS;
199 * e1000_check_reset_block_generic - Check if PHY reset is blocked
200 * @hw: pointer to the HW structure
202 * Read the PHY management control register and check whether a PHY reset
203 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
204 * return E1000_BLK_PHY_RESET (12).
206 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
210 DEBUGFUNC("e1000_check_reset_block");
212 manc = E1000_READ_REG(hw, E1000_MANC);
214 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
215 E1000_BLK_PHY_RESET : E1000_SUCCESS;
219 * e1000_get_phy_id - Retrieve the PHY ID and revision
220 * @hw: pointer to the HW structure
222 * Reads the PHY registers and stores the PHY ID and possibly the PHY
223 * revision in the hardware structure.
225 s32 e1000_get_phy_id(struct e1000_hw *hw)
227 struct e1000_phy_info *phy = &hw->phy;
228 s32 ret_val = E1000_SUCCESS;
232 DEBUGFUNC("e1000_get_phy_id");
234 if (!phy->ops.read_reg)
235 return E1000_SUCCESS;
237 while (retry_count < 2) {
238 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
242 phy->id = (u32)(phy_id << 16);
244 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
248 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
249 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
251 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
252 return E1000_SUCCESS;
257 return E1000_SUCCESS;
261 * e1000_phy_reset_dsp_generic - Reset PHY DSP
262 * @hw: pointer to the HW structure
264 * Reset the digital signal processor.
266 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
270 DEBUGFUNC("e1000_phy_reset_dsp_generic");
272 if (!hw->phy.ops.write_reg)
273 return E1000_SUCCESS;
275 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
279 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
283 * e1000_read_phy_reg_mdic - Read MDI control register
284 * @hw: pointer to the HW structure
285 * @offset: register offset to be read
286 * @data: pointer to the read data
288 * Reads the MDI control register in the PHY at offset and stores the
289 * information read to data.
291 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
293 struct e1000_phy_info *phy = &hw->phy;
296 DEBUGFUNC("e1000_read_phy_reg_mdic");
298 if (offset > MAX_PHY_REG_ADDRESS) {
299 DEBUGOUT1("PHY Address %d is out of range\n", offset);
300 return -E1000_ERR_PARAM;
303 /* Set up Op-code, Phy Address, and register offset in the MDI
304 * Control register. The MAC will take care of interfacing with the
305 * PHY to retrieve the desired data.
307 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
308 (phy->addr << E1000_MDIC_PHY_SHIFT) |
309 (E1000_MDIC_OP_READ));
311 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
313 /* Poll the ready bit to see if the MDI read completed
314 * Increasing the time out as testing showed failures with
317 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
319 mdic = E1000_READ_REG(hw, E1000_MDIC);
320 if (mdic & E1000_MDIC_READY)
323 if (!(mdic & E1000_MDIC_READY)) {
324 DEBUGOUT("MDI Read did not complete\n");
325 return -E1000_ERR_PHY;
327 if (mdic & E1000_MDIC_ERROR) {
328 DEBUGOUT("MDI Error\n");
329 return -E1000_ERR_PHY;
331 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
332 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n",
334 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
335 return -E1000_ERR_PHY;
339 /* Allow some time after each MDIC transaction to avoid
340 * reading duplicate data in the next MDIC transaction.
342 if (hw->mac.type == e1000_pch2lan)
345 return E1000_SUCCESS;
349 * e1000_write_phy_reg_mdic - Write MDI control register
350 * @hw: pointer to the HW structure
351 * @offset: register offset to write to
352 * @data: data to write to register at offset
354 * Writes data to MDI control register in the PHY at offset.
356 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
358 struct e1000_phy_info *phy = &hw->phy;
361 DEBUGFUNC("e1000_write_phy_reg_mdic");
363 if (offset > MAX_PHY_REG_ADDRESS) {
364 DEBUGOUT1("PHY Address %d is out of range\n", offset);
365 return -E1000_ERR_PARAM;
368 /* Set up Op-code, Phy Address, and register offset in the MDI
369 * Control register. The MAC will take care of interfacing with the
370 * PHY to retrieve the desired data.
372 mdic = (((u32)data) |
373 (offset << E1000_MDIC_REG_SHIFT) |
374 (phy->addr << E1000_MDIC_PHY_SHIFT) |
375 (E1000_MDIC_OP_WRITE));
377 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
379 /* Poll the ready bit to see if the MDI read completed
380 * Increasing the time out as testing showed failures with
383 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
385 mdic = E1000_READ_REG(hw, E1000_MDIC);
386 if (mdic & E1000_MDIC_READY)
389 if (!(mdic & E1000_MDIC_READY)) {
390 DEBUGOUT("MDI Write did not complete\n");
391 return -E1000_ERR_PHY;
393 if (mdic & E1000_MDIC_ERROR) {
394 DEBUGOUT("MDI Error\n");
395 return -E1000_ERR_PHY;
397 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
398 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n",
400 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
401 return -E1000_ERR_PHY;
404 /* Allow some time after each MDIC transaction to avoid
405 * reading duplicate data in the next MDIC transaction.
407 if (hw->mac.type == e1000_pch2lan)
410 return E1000_SUCCESS;
414 * e1000_read_phy_reg_i2c - Read PHY register using i2c
415 * @hw: pointer to the HW structure
416 * @offset: register offset to be read
417 * @data: pointer to the read data
419 * Reads the PHY register at offset using the i2c interface and stores the
420 * retrieved information in data.
422 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
424 struct e1000_phy_info *phy = &hw->phy;
427 DEBUGFUNC("e1000_read_phy_reg_i2c");
429 /* Set up Op-code, Phy Address, and register address in the I2CCMD
430 * register. The MAC will take care of interfacing with the
431 * PHY to retrieve the desired data.
433 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
434 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
435 (E1000_I2CCMD_OPCODE_READ));
437 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
439 /* Poll the ready bit to see if the I2C read completed */
440 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
442 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
443 if (i2ccmd & E1000_I2CCMD_READY)
446 if (!(i2ccmd & E1000_I2CCMD_READY)) {
447 DEBUGOUT("I2CCMD Read did not complete\n");
448 return -E1000_ERR_PHY;
450 if (i2ccmd & E1000_I2CCMD_ERROR) {
451 DEBUGOUT("I2CCMD Error bit set\n");
452 return -E1000_ERR_PHY;
455 /* Need to byte-swap the 16-bit value. */
456 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
458 return E1000_SUCCESS;
462 * e1000_write_phy_reg_i2c - Write PHY register using i2c
463 * @hw: pointer to the HW structure
464 * @offset: register offset to write to
465 * @data: data to write at register offset
467 * Writes the data to PHY register at the offset using the i2c interface.
469 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
471 struct e1000_phy_info *phy = &hw->phy;
473 u16 phy_data_swapped;
475 DEBUGFUNC("e1000_write_phy_reg_i2c");
477 /* Prevent overwriting SFP I2C EEPROM which is at A0 address.*/
478 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
479 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
481 return -E1000_ERR_CONFIG;
484 /* Swap the data bytes for the I2C interface */
485 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
487 /* Set up Op-code, Phy Address, and register address in the I2CCMD
488 * register. The MAC will take care of interfacing with the
489 * PHY to retrieve the desired data.
491 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
492 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
493 E1000_I2CCMD_OPCODE_WRITE |
496 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
498 /* Poll the ready bit to see if the I2C read completed */
499 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
501 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
502 if (i2ccmd & E1000_I2CCMD_READY)
505 if (!(i2ccmd & E1000_I2CCMD_READY)) {
506 DEBUGOUT("I2CCMD Write did not complete\n");
507 return -E1000_ERR_PHY;
509 if (i2ccmd & E1000_I2CCMD_ERROR) {
510 DEBUGOUT("I2CCMD Error bit set\n");
511 return -E1000_ERR_PHY;
514 return E1000_SUCCESS;
518 * e1000_read_sfp_data_byte - Reads SFP module data.
519 * @hw: pointer to the HW structure
520 * @offset: byte location offset to be read
521 * @data: read data buffer pointer
523 * Reads one byte from SFP module data stored
524 * in SFP resided EEPROM memory or SFP diagnostic area.
525 * Function should be called with
526 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
527 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
530 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
536 DEBUGFUNC("e1000_read_sfp_data_byte");
538 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
539 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
540 return -E1000_ERR_PHY;
543 /* Set up Op-code, EEPROM Address,in the I2CCMD
544 * register. The MAC will take care of interfacing with the
545 * EEPROM to retrieve the desired data.
547 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
548 E1000_I2CCMD_OPCODE_READ);
550 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
552 /* Poll the ready bit to see if the I2C read completed */
553 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
555 data_local = E1000_READ_REG(hw, E1000_I2CCMD);
556 if (data_local & E1000_I2CCMD_READY)
559 if (!(data_local & E1000_I2CCMD_READY)) {
560 DEBUGOUT("I2CCMD Read did not complete\n");
561 return -E1000_ERR_PHY;
563 if (data_local & E1000_I2CCMD_ERROR) {
564 DEBUGOUT("I2CCMD Error bit set\n");
565 return -E1000_ERR_PHY;
567 *data = (u8) data_local & 0xFF;
569 return E1000_SUCCESS;
573 * e1000_write_sfp_data_byte - Writes SFP module data.
574 * @hw: pointer to the HW structure
575 * @offset: byte location offset to write to
576 * @data: data to write
578 * Writes one byte to SFP module data stored
579 * in SFP resided EEPROM memory or SFP diagnostic area.
580 * Function should be called with
581 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
582 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
585 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
591 DEBUGFUNC("e1000_write_sfp_data_byte");
593 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
594 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
595 return -E1000_ERR_PHY;
597 /* The programming interface is 16 bits wide
598 * so we need to read the whole word first
599 * then update appropriate byte lane and write
600 * the updated word back.
602 /* Set up Op-code, EEPROM Address,in the I2CCMD
603 * register. The MAC will take care of interfacing
604 * with an EEPROM to write the data given.
606 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
607 E1000_I2CCMD_OPCODE_READ);
608 /* Set a command to read single word */
609 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
610 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
612 /* Poll the ready bit to see if lastly
613 * launched I2C operation completed
615 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
616 if (i2ccmd & E1000_I2CCMD_READY) {
617 /* Check if this is READ or WRITE phase */
618 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
619 E1000_I2CCMD_OPCODE_READ) {
620 /* Write the selected byte
621 * lane and update whole word
623 data_local = i2ccmd & 0xFF00;
624 data_local |= (u32)data;
626 E1000_I2CCMD_REG_ADDR_SHIFT) |
627 E1000_I2CCMD_OPCODE_WRITE | data_local);
628 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
634 if (!(i2ccmd & E1000_I2CCMD_READY)) {
635 DEBUGOUT("I2CCMD Write did not complete\n");
636 return -E1000_ERR_PHY;
638 if (i2ccmd & E1000_I2CCMD_ERROR) {
639 DEBUGOUT("I2CCMD Error bit set\n");
640 return -E1000_ERR_PHY;
642 return E1000_SUCCESS;
646 * e1000_read_phy_reg_m88 - Read m88 PHY register
647 * @hw: pointer to the HW structure
648 * @offset: register offset to be read
649 * @data: pointer to the read data
651 * Acquires semaphore, if necessary, then reads the PHY register at offset
652 * and storing the retrieved information in data. Release any acquired
653 * semaphores before exiting.
655 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
659 DEBUGFUNC("e1000_read_phy_reg_m88");
661 if (!hw->phy.ops.acquire)
662 return E1000_SUCCESS;
664 ret_val = hw->phy.ops.acquire(hw);
668 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
671 hw->phy.ops.release(hw);
677 * e1000_write_phy_reg_m88 - Write m88 PHY register
678 * @hw: pointer to the HW structure
679 * @offset: register offset to write to
680 * @data: data to write at register offset
682 * Acquires semaphore, if necessary, then writes the data to PHY register
683 * at the offset. Release any acquired semaphores before exiting.
685 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
689 DEBUGFUNC("e1000_write_phy_reg_m88");
691 if (!hw->phy.ops.acquire)
692 return E1000_SUCCESS;
694 ret_val = hw->phy.ops.acquire(hw);
698 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
701 hw->phy.ops.release(hw);
707 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
708 * @hw: pointer to the HW structure
709 * @page: page to set (shifted left when necessary)
711 * Sets PHY page required for PHY register access. Assumes semaphore is
712 * already acquired. Note, this function sets phy.addr to 1 so the caller
713 * must set it appropriately (if necessary) after this function returns.
715 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
717 DEBUGFUNC("e1000_set_page_igp");
719 DEBUGOUT1("Setting page 0x%x\n", page);
723 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
727 * __e1000_read_phy_reg_igp - Read igp PHY register
728 * @hw: pointer to the HW structure
729 * @offset: register offset to be read
730 * @data: pointer to the read data
731 * @locked: semaphore has already been acquired or not
733 * Acquires semaphore, if necessary, then reads the PHY register at offset
734 * and stores the retrieved information in data. Release any acquired
735 * semaphores before exiting.
737 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
740 s32 ret_val = E1000_SUCCESS;
742 DEBUGFUNC("__e1000_read_phy_reg_igp");
745 if (!hw->phy.ops.acquire)
746 return E1000_SUCCESS;
748 ret_val = hw->phy.ops.acquire(hw);
753 if (offset > MAX_PHY_MULTI_PAGE_REG)
754 ret_val = e1000_write_phy_reg_mdic(hw,
755 IGP01E1000_PHY_PAGE_SELECT,
758 ret_val = e1000_read_phy_reg_mdic(hw,
759 MAX_PHY_REG_ADDRESS & offset,
762 hw->phy.ops.release(hw);
768 * e1000_read_phy_reg_igp - Read igp PHY register
769 * @hw: pointer to the HW structure
770 * @offset: register offset to be read
771 * @data: pointer to the read data
773 * Acquires semaphore then reads the PHY register at offset and stores the
774 * retrieved information in data.
775 * Release the acquired semaphore before exiting.
777 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
779 return __e1000_read_phy_reg_igp(hw, offset, data, false);
783 * e1000_read_phy_reg_igp_locked - Read igp PHY register
784 * @hw: pointer to the HW structure
785 * @offset: register offset to be read
786 * @data: pointer to the read data
788 * Reads the PHY register at offset and stores the retrieved information
789 * in data. Assumes semaphore already acquired.
791 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
793 return __e1000_read_phy_reg_igp(hw, offset, data, true);
797 * e1000_write_phy_reg_igp - Write igp PHY register
798 * @hw: pointer to the HW structure
799 * @offset: register offset to write to
800 * @data: data to write at register offset
801 * @locked: semaphore has already been acquired or not
803 * Acquires semaphore, if necessary, then writes the data to PHY register
804 * at the offset. Release any acquired semaphores before exiting.
806 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
809 s32 ret_val = E1000_SUCCESS;
811 DEBUGFUNC("e1000_write_phy_reg_igp");
814 if (!hw->phy.ops.acquire)
815 return E1000_SUCCESS;
817 ret_val = hw->phy.ops.acquire(hw);
822 if (offset > MAX_PHY_MULTI_PAGE_REG)
823 ret_val = e1000_write_phy_reg_mdic(hw,
824 IGP01E1000_PHY_PAGE_SELECT,
827 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
831 hw->phy.ops.release(hw);
837 * e1000_write_phy_reg_igp - Write igp PHY register
838 * @hw: pointer to the HW structure
839 * @offset: register offset to write to
840 * @data: data to write at register offset
842 * Acquires semaphore then writes the data to PHY register
843 * at the offset. Release any acquired semaphores before exiting.
845 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
847 return __e1000_write_phy_reg_igp(hw, offset, data, false);
851 * e1000_write_phy_reg_igp_locked - Write igp PHY register
852 * @hw: pointer to the HW structure
853 * @offset: register offset to write to
854 * @data: data to write at register offset
856 * Writes the data to PHY register at the offset.
857 * Assumes semaphore already acquired.
859 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
861 return __e1000_write_phy_reg_igp(hw, offset, data, true);
865 * __e1000_read_kmrn_reg - Read kumeran register
866 * @hw: pointer to the HW structure
867 * @offset: register offset to be read
868 * @data: pointer to the read data
869 * @locked: semaphore has already been acquired or not
871 * Acquires semaphore, if necessary. Then reads the PHY register at offset
872 * using the kumeran interface. The information retrieved is stored in data.
873 * Release any acquired semaphores before exiting.
875 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
880 DEBUGFUNC("__e1000_read_kmrn_reg");
883 s32 ret_val = E1000_SUCCESS;
885 if (!hw->phy.ops.acquire)
886 return E1000_SUCCESS;
888 ret_val = hw->phy.ops.acquire(hw);
893 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
894 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
895 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
896 E1000_WRITE_FLUSH(hw);
900 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
901 *data = (u16)kmrnctrlsta;
904 hw->phy.ops.release(hw);
906 return E1000_SUCCESS;
910 * e1000_read_kmrn_reg_generic - Read kumeran register
911 * @hw: pointer to the HW structure
912 * @offset: register offset to be read
913 * @data: pointer to the read data
915 * Acquires semaphore then reads the PHY register at offset using the
916 * kumeran interface. The information retrieved is stored in data.
917 * Release the acquired semaphore before exiting.
919 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
921 return __e1000_read_kmrn_reg(hw, offset, data, false);
925 * e1000_read_kmrn_reg_locked - Read kumeran register
926 * @hw: pointer to the HW structure
927 * @offset: register offset to be read
928 * @data: pointer to the read data
930 * Reads the PHY register at offset using the kumeran interface. The
931 * information retrieved is stored in data.
932 * Assumes semaphore already acquired.
934 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
936 return __e1000_read_kmrn_reg(hw, offset, data, true);
940 * __e1000_write_kmrn_reg - Write kumeran register
941 * @hw: pointer to the HW structure
942 * @offset: register offset to write to
943 * @data: data to write at register offset
944 * @locked: semaphore has already been acquired or not
946 * Acquires semaphore, if necessary. Then write the data to PHY register
947 * at the offset using the kumeran interface. Release any acquired semaphores
950 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
955 DEBUGFUNC("e1000_write_kmrn_reg_generic");
958 s32 ret_val = E1000_SUCCESS;
960 if (!hw->phy.ops.acquire)
961 return E1000_SUCCESS;
963 ret_val = hw->phy.ops.acquire(hw);
968 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
969 E1000_KMRNCTRLSTA_OFFSET) | data;
970 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
971 E1000_WRITE_FLUSH(hw);
976 hw->phy.ops.release(hw);
978 return E1000_SUCCESS;
982 * e1000_write_kmrn_reg_generic - Write kumeran register
983 * @hw: pointer to the HW structure
984 * @offset: register offset to write to
985 * @data: data to write at register offset
987 * Acquires semaphore then writes the data to the PHY register at the offset
988 * using the kumeran interface. Release the acquired semaphore before exiting.
990 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
992 return __e1000_write_kmrn_reg(hw, offset, data, false);
996 * e1000_write_kmrn_reg_locked - Write kumeran register
997 * @hw: pointer to the HW structure
998 * @offset: register offset to write to
999 * @data: data to write at register offset
1001 * Write the data to PHY register at the offset using the kumeran interface.
1002 * Assumes semaphore already acquired.
1004 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
1006 return __e1000_write_kmrn_reg(hw, offset, data, true);
1010 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
1011 * @hw: pointer to the HW structure
1013 * Sets up Master/slave mode
1015 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
1020 /* Resolve Master/Slave mode */
1021 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1025 /* load defaults for future use */
1026 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1027 ((phy_data & CR_1000T_MS_VALUE) ?
1028 e1000_ms_force_master :
1029 e1000_ms_force_slave) : e1000_ms_auto;
1031 switch (hw->phy.ms_type) {
1032 case e1000_ms_force_master:
1033 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1035 case e1000_ms_force_slave:
1036 phy_data |= CR_1000T_MS_ENABLE;
1037 phy_data &= ~(CR_1000T_MS_VALUE);
1040 phy_data &= ~CR_1000T_MS_ENABLE;
1046 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1050 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
1051 * @hw: pointer to the HW structure
1053 * Sets up Carrier-sense on Transmit and downshift values.
1055 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
1060 DEBUGFUNC("e1000_copper_link_setup_82577");
1062 if (hw->phy.type == e1000_phy_82580) {
1063 ret_val = hw->phy.ops.reset(hw);
1065 DEBUGOUT("Error resetting the PHY.\n");
1070 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1071 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1075 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1077 /* Enable downshift */
1078 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1080 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1084 /* Set MDI/MDIX mode */
1085 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1088 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
1090 * 0 - Auto (default)
1094 switch (hw->phy.mdix) {
1098 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
1103 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
1106 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1110 return e1000_set_master_slave_mode(hw);
1114 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1115 * @hw: pointer to the HW structure
1117 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1118 * and downshift values are set also.
1120 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1122 struct e1000_phy_info *phy = &hw->phy;
1126 DEBUGFUNC("e1000_copper_link_setup_m88");
1129 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1130 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1134 /* For BM PHY this bit is downshift enable */
1135 if (phy->type != e1000_phy_bm)
1136 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1139 * MDI/MDI-X = 0 (default)
1140 * 0 - Auto for all speeds
1143 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1145 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1147 switch (phy->mdix) {
1149 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1152 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1155 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1160 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1165 * disable_polarity_correction = 0 (default)
1166 * Automatic Correction for Reversed Cable Polarity
1170 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1171 if (phy->disable_polarity_correction)
1172 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1174 /* Enable downshift on BM (disabled by default) */
1175 if (phy->type == e1000_phy_bm) {
1176 /* For 82574/82583, first disable then enable downshift */
1177 if (phy->id == BME1000_E_PHY_ID_R2) {
1178 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
1179 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1183 /* Commit the changes. */
1184 ret_val = phy->ops.commit(hw);
1186 DEBUGOUT("Error committing the PHY changes\n");
1191 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
1194 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1198 if ((phy->type == e1000_phy_m88) &&
1199 (phy->revision < E1000_REVISION_4) &&
1200 (phy->id != BME1000_E_PHY_ID_R2)) {
1201 /* Force TX_CLK in the Extended PHY Specific Control Register
1204 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1209 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1211 if ((phy->revision == E1000_REVISION_2) &&
1212 (phy->id == M88E1111_I_PHY_ID)) {
1213 /* 82573L PHY - set the downshift counter to 5x. */
1214 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1215 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1217 /* Configure Master and Slave downshift values */
1218 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1219 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1220 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1221 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1223 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1229 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1230 /* Set PHY page 0, register 29 to 0x0003 */
1231 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1235 /* Set PHY page 0, register 30 to 0x0000 */
1236 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1241 /* Commit the changes. */
1242 ret_val = phy->ops.commit(hw);
1244 DEBUGOUT("Error committing the PHY changes\n");
1248 if (phy->type == e1000_phy_82578) {
1249 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1254 /* 82578 PHY - set the downshift count to 1x. */
1255 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
1256 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
1257 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1263 return E1000_SUCCESS;
1267 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1268 * @hw: pointer to the HW structure
1270 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1271 * Also enables and sets the downshift parameters.
1273 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1275 struct e1000_phy_info *phy = &hw->phy;
1279 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1282 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1283 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1288 * MDI/MDI-X = 0 (default)
1289 * 0 - Auto for all speeds
1292 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1294 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1296 switch (phy->mdix) {
1298 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1301 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1304 /* M88E1112 does not support this mode) */
1305 if (phy->id != M88E1112_E_PHY_ID) {
1306 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1313 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1318 * disable_polarity_correction = 0 (default)
1319 * Automatic Correction for Reversed Cable Polarity
1323 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1324 if (phy->disable_polarity_correction)
1325 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1327 /* Enable downshift and setting it to X6 */
1328 if (phy->id == M88E1543_E_PHY_ID) {
1329 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
1331 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1335 ret_val = phy->ops.commit(hw);
1337 DEBUGOUT("Error committing the PHY changes\n");
1342 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1343 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1344 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1346 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1350 /* Commit the changes. */
1351 ret_val = phy->ops.commit(hw);
1353 DEBUGOUT("Error committing the PHY changes\n");
1357 ret_val = e1000_set_master_slave_mode(hw);
1361 return E1000_SUCCESS;
1365 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1366 * @hw: pointer to the HW structure
1368 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1371 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1373 struct e1000_phy_info *phy = &hw->phy;
1377 DEBUGFUNC("e1000_copper_link_setup_igp");
1380 ret_val = hw->phy.ops.reset(hw);
1382 DEBUGOUT("Error resetting the PHY.\n");
1386 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1387 * timeout issues when LFS is enabled.
1391 /* The NVM settings will configure LPLU in D3 for
1394 if (phy->type == e1000_phy_igp) {
1395 /* disable lplu d3 during driver init */
1396 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
1398 DEBUGOUT("Error Disabling LPLU D3\n");
1403 /* disable lplu d0 during driver init */
1404 if (hw->phy.ops.set_d0_lplu_state) {
1405 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
1407 DEBUGOUT("Error Disabling LPLU D0\n");
1411 /* Configure mdi-mdix settings */
1412 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1416 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1418 switch (phy->mdix) {
1420 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1423 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1428 data |= IGP01E1000_PSCR_AUTO_MDIX;
1431 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1435 /* set auto-master slave resolution settings */
1436 if (hw->mac.autoneg) {
1437 /* when autonegotiation advertisement is only 1000Mbps then we
1438 * should disable SmartSpeed and enable Auto MasterSlave
1439 * resolution as hardware default.
1441 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1442 /* Disable SmartSpeed */
1443 ret_val = phy->ops.read_reg(hw,
1444 IGP01E1000_PHY_PORT_CONFIG,
1449 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1450 ret_val = phy->ops.write_reg(hw,
1451 IGP01E1000_PHY_PORT_CONFIG,
1456 /* Set auto Master/Slave resolution process */
1457 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1461 data &= ~CR_1000T_MS_ENABLE;
1462 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1467 ret_val = e1000_set_master_slave_mode(hw);
1474 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1475 * @hw: pointer to the HW structure
1477 * Reads the MII auto-neg advertisement register and/or the 1000T control
1478 * register and if the PHY is already setup for auto-negotiation, then
1479 * return successful. Otherwise, setup advertisement and flow control to
1480 * the appropriate values for the wanted auto-negotiation.
1482 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1484 struct e1000_phy_info *phy = &hw->phy;
1486 u16 mii_autoneg_adv_reg;
1487 u16 mii_1000t_ctrl_reg = 0;
1489 DEBUGFUNC("e1000_phy_setup_autoneg");
1491 phy->autoneg_advertised &= phy->autoneg_mask;
1493 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1494 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1498 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1499 /* Read the MII 1000Base-T Control Register (Address 9). */
1500 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1501 &mii_1000t_ctrl_reg);
1506 /* Need to parse both autoneg_advertised and fc and set up
1507 * the appropriate PHY registers. First we will parse for
1508 * autoneg_advertised software override. Since we can advertise
1509 * a plethora of combinations, we need to check each bit
1513 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1514 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1515 * the 1000Base-T Control Register (Address 9).
1517 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1518 NWAY_AR_100TX_HD_CAPS |
1519 NWAY_AR_10T_FD_CAPS |
1520 NWAY_AR_10T_HD_CAPS);
1521 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1523 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1525 /* Do we want to advertise 10 Mb Half Duplex? */
1526 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1527 DEBUGOUT("Advertise 10mb Half duplex\n");
1528 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1531 /* Do we want to advertise 10 Mb Full Duplex? */
1532 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1533 DEBUGOUT("Advertise 10mb Full duplex\n");
1534 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1537 /* Do we want to advertise 100 Mb Half Duplex? */
1538 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1539 DEBUGOUT("Advertise 100mb Half duplex\n");
1540 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1543 /* Do we want to advertise 100 Mb Full Duplex? */
1544 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1545 DEBUGOUT("Advertise 100mb Full duplex\n");
1546 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1549 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1550 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1551 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1553 /* Do we want to advertise 1000 Mb Full Duplex? */
1554 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1555 DEBUGOUT("Advertise 1000mb Full duplex\n");
1556 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1559 /* Check for a software override of the flow control settings, and
1560 * setup the PHY advertisement registers accordingly. If
1561 * auto-negotiation is enabled, then software will have to set the
1562 * "PAUSE" bits to the correct value in the Auto-Negotiation
1563 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1566 * The possible values of the "fc" parameter are:
1567 * 0: Flow control is completely disabled
1568 * 1: Rx flow control is enabled (we can receive pause frames
1569 * but not send pause frames).
1570 * 2: Tx flow control is enabled (we can send pause frames
1571 * but we do not support receiving pause frames).
1572 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1573 * other: No software override. The flow control configuration
1574 * in the EEPROM is used.
1576 switch (hw->fc.current_mode) {
1578 /* Flow control (Rx & Tx) is completely disabled by a
1579 * software over-ride.
1581 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1583 case e1000_fc_rx_pause:
1584 /* Rx Flow control is enabled, and Tx Flow control is
1585 * disabled, by a software over-ride.
1587 * Since there really isn't a way to advertise that we are
1588 * capable of Rx Pause ONLY, we will advertise that we
1589 * support both symmetric and asymmetric Rx PAUSE. Later
1590 * (in e1000_config_fc_after_link_up) we will disable the
1591 * hw's ability to send PAUSE frames.
1593 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1595 case e1000_fc_tx_pause:
1596 /* Tx Flow control is enabled, and Rx Flow control is
1597 * disabled, by a software over-ride.
1599 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1600 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1603 /* Flow control (both Rx and Tx) is enabled by a software
1606 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1609 DEBUGOUT("Flow control param set incorrectly\n");
1610 return -E1000_ERR_CONFIG;
1613 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1617 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1619 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1620 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1621 mii_1000t_ctrl_reg);
1627 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1628 * @hw: pointer to the HW structure
1630 * Performs initial bounds checking on autoneg advertisement parameter, then
1631 * configure to advertise the full capability. Setup the PHY to autoneg
1632 * and restart the negotiation process between the link partner. If
1633 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1635 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1637 struct e1000_phy_info *phy = &hw->phy;
1641 DEBUGFUNC("e1000_copper_link_autoneg");
1643 /* Perform some bounds checking on the autoneg advertisement
1646 phy->autoneg_advertised &= phy->autoneg_mask;
1648 /* If autoneg_advertised is zero, we assume it was not defaulted
1649 * by the calling code so we set to advertise full capability.
1651 if (!phy->autoneg_advertised)
1652 phy->autoneg_advertised = phy->autoneg_mask;
1654 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1655 ret_val = e1000_phy_setup_autoneg(hw);
1657 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1660 DEBUGOUT("Restarting Auto-Neg\n");
1662 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1663 * the Auto Neg Restart bit in the PHY control register.
1665 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1669 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1670 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1674 /* Does the user want to wait for Auto-Neg to complete here, or
1675 * check at a later time (for example, callback routine).
1677 if (phy->autoneg_wait_to_complete) {
1678 ret_val = e1000_wait_autoneg(hw);
1680 DEBUGOUT("Error while waiting for autoneg to complete\n");
1685 hw->mac.get_link_status = true;
1691 * e1000_setup_copper_link_generic - Configure copper link settings
1692 * @hw: pointer to the HW structure
1694 * Calls the appropriate function to configure the link for auto-neg or forced
1695 * speed and duplex. Then we check for link, once link is established calls
1696 * to configure collision distance and flow control are called. If link is
1697 * not established, we return -E1000_ERR_PHY (-2).
1699 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1704 DEBUGFUNC("e1000_setup_copper_link_generic");
1706 if (hw->mac.autoneg) {
1707 /* Setup autoneg and flow control advertisement and perform
1710 ret_val = e1000_copper_link_autoneg(hw);
1714 /* PHY will be set to 10H, 10F, 100H or 100F
1715 * depending on user settings.
1717 DEBUGOUT("Forcing Speed and Duplex\n");
1718 ret_val = hw->phy.ops.force_speed_duplex(hw);
1720 DEBUGOUT("Error Forcing Speed and Duplex\n");
1725 /* Check link status. Wait up to 100 microseconds for link to become
1728 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1734 DEBUGOUT("Valid link established!!!\n");
1735 hw->mac.ops.config_collision_dist(hw);
1736 ret_val = e1000_config_fc_after_link_up_generic(hw);
1738 DEBUGOUT("Unable to establish link!!!\n");
1745 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1746 * @hw: pointer to the HW structure
1748 * Calls the PHY setup function to force speed and duplex. Clears the
1749 * auto-crossover to force MDI manually. Waits for link and returns
1750 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1752 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1754 struct e1000_phy_info *phy = &hw->phy;
1759 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1761 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1765 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1767 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1771 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1772 * forced whenever speed and duplex are forced.
1774 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1778 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1779 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1781 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1785 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1789 if (phy->autoneg_wait_to_complete) {
1790 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1792 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1798 DEBUGOUT("Link taking longer than expected.\n");
1801 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1809 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1810 * @hw: pointer to the HW structure
1812 * Calls the PHY setup function to force speed and duplex. Clears the
1813 * auto-crossover to force MDI manually. Resets the PHY to commit the
1814 * changes. If time expires while waiting for link up, we reset the DSP.
1815 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1816 * successful completion, else return corresponding error code.
1818 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1820 struct e1000_phy_info *phy = &hw->phy;
1825 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1827 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1828 if (phy->type != e1000_phy_i210) {
1829 /* Clear Auto-Crossover to force MDI manually. M88E1000
1830 * requires MDI forced whenever speed and duplex are forced.
1832 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1837 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1838 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1843 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1846 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1850 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1852 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1856 /* Reset the phy to commit changes. */
1857 ret_val = hw->phy.ops.commit(hw);
1861 if (phy->autoneg_wait_to_complete) {
1862 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1864 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1870 bool reset_dsp = true;
1872 switch (hw->phy.id) {
1873 case I347AT4_E_PHY_ID:
1874 case M88E1340M_E_PHY_ID:
1875 case M88E1112_E_PHY_ID:
1876 case M88E1543_E_PHY_ID:
1877 case M88E1512_E_PHY_ID:
1882 if (hw->phy.type != e1000_phy_m88)
1888 DEBUGOUT("Link taking longer than expected.\n");
1890 /* We didn't get link.
1891 * Reset the DSP and cross our fingers.
1893 ret_val = phy->ops.write_reg(hw,
1894 M88E1000_PHY_PAGE_SELECT,
1898 ret_val = e1000_phy_reset_dsp_generic(hw);
1905 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1911 if (hw->phy.type != e1000_phy_m88)
1912 return E1000_SUCCESS;
1914 if (hw->phy.id == I347AT4_E_PHY_ID ||
1915 hw->phy.id == M88E1340M_E_PHY_ID ||
1916 hw->phy.id == M88E1112_E_PHY_ID)
1917 return E1000_SUCCESS;
1918 if (hw->phy.id == I210_I_PHY_ID)
1919 return E1000_SUCCESS;
1920 if ((hw->phy.id == M88E1543_E_PHY_ID) ||
1921 (hw->phy.id == M88E1512_E_PHY_ID))
1922 return E1000_SUCCESS;
1923 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1927 /* Resetting the phy means we need to re-force TX_CLK in the
1928 * Extended PHY Specific Control Register to 25MHz clock from
1929 * the reset value of 2.5MHz.
1931 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1932 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1936 /* In addition, we must re-enable CRS on Tx for both half and full
1939 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1943 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1944 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1950 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1951 * @hw: pointer to the HW structure
1953 * Forces the speed and duplex settings of the PHY.
1954 * This is a function pointer entry point only called by
1955 * PHY setup routines.
1957 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1959 struct e1000_phy_info *phy = &hw->phy;
1964 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1966 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1970 e1000_phy_force_speed_duplex_setup(hw, &data);
1972 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1976 /* Disable MDI-X support for 10/100 */
1977 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1981 data &= ~IFE_PMC_AUTO_MDIX;
1982 data &= ~IFE_PMC_FORCE_MDIX;
1984 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1988 DEBUGOUT1("IFE PMC: %X\n", data);
1992 if (phy->autoneg_wait_to_complete) {
1993 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1995 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
2001 DEBUGOUT("Link taking longer than expected.\n");
2004 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
2010 return E1000_SUCCESS;
2014 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
2015 * @hw: pointer to the HW structure
2016 * @phy_ctrl: pointer to current value of PHY_CONTROL
2018 * Forces speed and duplex on the PHY by doing the following: disable flow
2019 * control, force speed/duplex on the MAC, disable auto speed detection,
2020 * disable auto-negotiation, configure duplex, configure speed, configure
2021 * the collision distance, write configuration to CTRL register. The
2022 * caller must write to the PHY_CONTROL register for these settings to
2025 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
2027 struct e1000_mac_info *mac = &hw->mac;
2030 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
2032 /* Turn off flow control when forcing speed/duplex */
2033 hw->fc.current_mode = e1000_fc_none;
2035 /* Force speed/duplex on the mac */
2036 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2037 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2038 ctrl &= ~E1000_CTRL_SPD_SEL;
2040 /* Disable Auto Speed Detection */
2041 ctrl &= ~E1000_CTRL_ASDE;
2043 /* Disable autoneg on the phy */
2044 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
2046 /* Forcing Full or Half Duplex? */
2047 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
2048 ctrl &= ~E1000_CTRL_FD;
2049 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
2050 DEBUGOUT("Half Duplex\n");
2052 ctrl |= E1000_CTRL_FD;
2053 *phy_ctrl |= MII_CR_FULL_DUPLEX;
2054 DEBUGOUT("Full Duplex\n");
2057 /* Forcing 10mb or 100mb? */
2058 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
2059 ctrl |= E1000_CTRL_SPD_100;
2060 *phy_ctrl |= MII_CR_SPEED_100;
2061 *phy_ctrl &= ~MII_CR_SPEED_1000;
2062 DEBUGOUT("Forcing 100mb\n");
2064 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2065 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2066 DEBUGOUT("Forcing 10mb\n");
2069 hw->mac.ops.config_collision_dist(hw);
2071 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2075 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
2076 * @hw: pointer to the HW structure
2077 * @active: boolean used to enable/disable lplu
2079 * Success returns 0, Failure returns 1
2081 * The low power link up (lplu) state is set to the power management level D3
2082 * and SmartSpeed is disabled when active is true, else clear lplu for D3
2083 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2084 * is used during Dx states where the power conservation is most important.
2085 * During driver activity, SmartSpeed should be enabled so performance is
2088 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
2090 struct e1000_phy_info *phy = &hw->phy;
2094 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
2096 if (!hw->phy.ops.read_reg)
2097 return E1000_SUCCESS;
2099 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2104 data &= ~IGP02E1000_PM_D3_LPLU;
2105 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2109 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2110 * during Dx states where the power conservation is most
2111 * important. During driver activity we should enable
2112 * SmartSpeed, so performance is maintained.
2114 if (phy->smart_speed == e1000_smart_speed_on) {
2115 ret_val = phy->ops.read_reg(hw,
2116 IGP01E1000_PHY_PORT_CONFIG,
2121 data |= IGP01E1000_PSCFR_SMART_SPEED;
2122 ret_val = phy->ops.write_reg(hw,
2123 IGP01E1000_PHY_PORT_CONFIG,
2127 } else if (phy->smart_speed == e1000_smart_speed_off) {
2128 ret_val = phy->ops.read_reg(hw,
2129 IGP01E1000_PHY_PORT_CONFIG,
2134 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2135 ret_val = phy->ops.write_reg(hw,
2136 IGP01E1000_PHY_PORT_CONFIG,
2141 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2142 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2143 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2144 data |= IGP02E1000_PM_D3_LPLU;
2145 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2150 /* When LPLU is enabled, we should disable SmartSpeed */
2151 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2156 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2157 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2165 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
2166 * @hw: pointer to the HW structure
2168 * Success returns 0, Failure returns 1
2170 * A downshift is detected by querying the PHY link health.
2172 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
2174 struct e1000_phy_info *phy = &hw->phy;
2176 u16 phy_data, offset, mask;
2178 DEBUGFUNC("e1000_check_downshift_generic");
2180 switch (phy->type) {
2181 case e1000_phy_i210:
2183 case e1000_phy_gg82563:
2185 case e1000_phy_82578:
2186 offset = M88E1000_PHY_SPEC_STATUS;
2187 mask = M88E1000_PSSR_DOWNSHIFT;
2190 case e1000_phy_igp_2:
2191 case e1000_phy_igp_3:
2192 offset = IGP01E1000_PHY_LINK_HEALTH;
2193 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
2196 /* speed downshift not supported */
2197 phy->speed_downgraded = false;
2198 return E1000_SUCCESS;
2201 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2204 phy->speed_downgraded = !!(phy_data & mask);
2210 * e1000_check_polarity_m88 - Checks the polarity.
2211 * @hw: pointer to the HW structure
2213 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2215 * Polarity is determined based on the PHY specific status register.
2217 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2219 struct e1000_phy_info *phy = &hw->phy;
2223 DEBUGFUNC("e1000_check_polarity_m88");
2225 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2228 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
2229 ? e1000_rev_polarity_reversed
2230 : e1000_rev_polarity_normal);
2236 * e1000_check_polarity_igp - Checks the polarity.
2237 * @hw: pointer to the HW structure
2239 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2241 * Polarity is determined based on the PHY port status register, and the
2242 * current speed (since there is no polarity at 100Mbps).
2244 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2246 struct e1000_phy_info *phy = &hw->phy;
2248 u16 data, offset, mask;
2250 DEBUGFUNC("e1000_check_polarity_igp");
2252 /* Polarity is determined based on the speed of
2255 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2259 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2260 IGP01E1000_PSSR_SPEED_1000MBPS) {
2261 offset = IGP01E1000_PHY_PCS_INIT_REG;
2262 mask = IGP01E1000_PHY_POLARITY_MASK;
2264 /* This really only applies to 10Mbps since
2265 * there is no polarity for 100Mbps (always 0).
2267 offset = IGP01E1000_PHY_PORT_STATUS;
2268 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
2271 ret_val = phy->ops.read_reg(hw, offset, &data);
2274 phy->cable_polarity = ((data & mask)
2275 ? e1000_rev_polarity_reversed
2276 : e1000_rev_polarity_normal);
2282 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2283 * @hw: pointer to the HW structure
2285 * Polarity is determined on the polarity reversal feature being enabled.
2287 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2289 struct e1000_phy_info *phy = &hw->phy;
2291 u16 phy_data, offset, mask;
2293 DEBUGFUNC("e1000_check_polarity_ife");
2295 /* Polarity is determined based on the reversal feature being enabled.
2297 if (phy->polarity_correction) {
2298 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2299 mask = IFE_PESC_POLARITY_REVERSED;
2301 offset = IFE_PHY_SPECIAL_CONTROL;
2302 mask = IFE_PSC_FORCE_POLARITY;
2305 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2308 phy->cable_polarity = ((phy_data & mask)
2309 ? e1000_rev_polarity_reversed
2310 : e1000_rev_polarity_normal);
2316 * e1000_wait_autoneg - Wait for auto-neg completion
2317 * @hw: pointer to the HW structure
2319 * Waits for auto-negotiation to complete or for the auto-negotiation time
2320 * limit to expire, which ever happens first.
2322 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2324 s32 ret_val = E1000_SUCCESS;
2327 DEBUGFUNC("e1000_wait_autoneg");
2329 if (!hw->phy.ops.read_reg)
2330 return E1000_SUCCESS;
2332 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2333 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2334 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2337 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2340 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2345 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2352 * e1000_phy_has_link_generic - Polls PHY for link
2353 * @hw: pointer to the HW structure
2354 * @iterations: number of times to poll for link
2355 * @usec_interval: delay between polling attempts
2356 * @success: pointer to whether polling was successful or not
2358 * Polls the PHY status register for link, 'iterations' number of times.
2360 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2361 u32 usec_interval, bool *success)
2363 s32 ret_val = E1000_SUCCESS;
2366 DEBUGFUNC("e1000_phy_has_link_generic");
2368 if (!hw->phy.ops.read_reg)
2369 return E1000_SUCCESS;
2371 for (i = 0; i < iterations; i++) {
2372 /* Some PHYs require the PHY_STATUS register to be read
2373 * twice due to the link bit being sticky. No harm doing
2374 * it across the board.
2376 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2378 /* If the first read fails, another entity may have
2379 * ownership of the resources, wait and try again to
2380 * see if they have relinquished the resources yet.
2382 if (usec_interval >= 1000)
2383 msec_delay(usec_interval/1000);
2385 usec_delay(usec_interval);
2387 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2390 if (phy_status & MII_SR_LINK_STATUS)
2392 if (usec_interval >= 1000)
2393 msec_delay(usec_interval/1000);
2395 usec_delay(usec_interval);
2398 *success = (i < iterations);
2404 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2405 * @hw: pointer to the HW structure
2407 * Reads the PHY specific status register to retrieve the cable length
2408 * information. The cable length is determined by averaging the minimum and
2409 * maximum values to get the "average" cable length. The m88 PHY has four
2410 * possible cable length values, which are:
2411 * Register Value Cable Length
2415 * 3 110 - 140 meters
2418 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2420 struct e1000_phy_info *phy = &hw->phy;
2422 u16 phy_data, index;
2424 DEBUGFUNC("e1000_get_cable_length_m88");
2426 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2430 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2431 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2433 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2434 return -E1000_ERR_PHY;
2436 phy->min_cable_length = e1000_m88_cable_length_table[index];
2437 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2439 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2441 return E1000_SUCCESS;
2444 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2446 struct e1000_phy_info *phy = &hw->phy;
2448 u16 phy_data, phy_data2, is_cm;
2449 u16 index, default_page;
2451 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2453 switch (hw->phy.id) {
2455 /* Get cable length from PHY Cable Diagnostics Control Reg */
2456 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2457 (I347AT4_PCDL + phy->addr),
2462 /* Check if the unit of cable length is meters or cm */
2463 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2464 I347AT4_PCDC, &phy_data2);
2468 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2470 /* Populate the phy structure with cable length in meters */
2471 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2472 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2473 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2475 case M88E1543_E_PHY_ID:
2476 case M88E1512_E_PHY_ID:
2477 case M88E1340M_E_PHY_ID:
2478 case I347AT4_E_PHY_ID:
2479 /* Remember the original page select and set it to 7 */
2480 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2485 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2489 /* Get cable length from PHY Cable Diagnostics Control Reg */
2490 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2495 /* Check if the unit of cable length is meters or cm */
2496 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2500 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2502 /* Populate the phy structure with cable length in meters */
2503 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2504 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2505 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2507 /* Reset the page select to its original value */
2508 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2514 case M88E1112_E_PHY_ID:
2515 /* Remember the original page select and set it to 5 */
2516 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2521 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2525 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2530 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2531 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2533 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2534 return -E1000_ERR_PHY;
2536 phy->min_cable_length = e1000_m88_cable_length_table[index];
2537 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2539 phy->cable_length = (phy->min_cable_length +
2540 phy->max_cable_length) / 2;
2542 /* Reset the page select to its original value */
2543 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2550 return -E1000_ERR_PHY;
2557 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2558 * @hw: pointer to the HW structure
2560 * The automatic gain control (agc) normalizes the amplitude of the
2561 * received signal, adjusting for the attenuation produced by the
2562 * cable. By reading the AGC registers, which represent the
2563 * combination of coarse and fine gain value, the value can be put
2564 * into a lookup table to obtain the approximate cable length
2567 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2569 struct e1000_phy_info *phy = &hw->phy;
2571 u16 phy_data, i, agc_value = 0;
2572 u16 cur_agc_index, max_agc_index = 0;
2573 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2574 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2575 IGP02E1000_PHY_AGC_A,
2576 IGP02E1000_PHY_AGC_B,
2577 IGP02E1000_PHY_AGC_C,
2578 IGP02E1000_PHY_AGC_D
2581 DEBUGFUNC("e1000_get_cable_length_igp_2");
2583 /* Read the AGC registers for all channels */
2584 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2585 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2589 /* Getting bits 15:9, which represent the combination of
2590 * coarse and fine gain values. The result is a number
2591 * that can be put into the lookup table to obtain the
2592 * approximate cable length.
2594 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2595 IGP02E1000_AGC_LENGTH_MASK);
2597 /* Array index bound check. */
2598 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2599 (cur_agc_index == 0))
2600 return -E1000_ERR_PHY;
2602 /* Remove min & max AGC values from calculation. */
2603 if (e1000_igp_2_cable_length_table[min_agc_index] >
2604 e1000_igp_2_cable_length_table[cur_agc_index])
2605 min_agc_index = cur_agc_index;
2606 if (e1000_igp_2_cable_length_table[max_agc_index] <
2607 e1000_igp_2_cable_length_table[cur_agc_index])
2608 max_agc_index = cur_agc_index;
2610 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2613 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2614 e1000_igp_2_cable_length_table[max_agc_index]);
2615 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2617 /* Calculate cable length with the error range of +/- 10 meters. */
2618 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2619 (agc_value - IGP02E1000_AGC_RANGE) : 0);
2620 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2622 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2624 return E1000_SUCCESS;
2628 * e1000_get_phy_info_m88 - Retrieve PHY information
2629 * @hw: pointer to the HW structure
2631 * Valid for only copper links. Read the PHY status register (sticky read)
2632 * to verify that link is up. Read the PHY special control register to
2633 * determine the polarity and 10base-T extended distance. Read the PHY
2634 * special status register to determine MDI/MDIx and current speed. If
2635 * speed is 1000, then determine cable length, local and remote receiver.
2637 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2639 struct e1000_phy_info *phy = &hw->phy;
2644 DEBUGFUNC("e1000_get_phy_info_m88");
2646 if (phy->media_type != e1000_media_type_copper) {
2647 DEBUGOUT("Phy info is only valid for copper media\n");
2648 return -E1000_ERR_CONFIG;
2651 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2656 DEBUGOUT("Phy info is only valid if link is up\n");
2657 return -E1000_ERR_CONFIG;
2660 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2664 phy->polarity_correction = !!(phy_data &
2665 M88E1000_PSCR_POLARITY_REVERSAL);
2667 ret_val = e1000_check_polarity_m88(hw);
2671 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2675 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2677 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2678 ret_val = hw->phy.ops.get_cable_length(hw);
2682 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2686 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2687 ? e1000_1000t_rx_status_ok
2688 : e1000_1000t_rx_status_not_ok;
2690 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2691 ? e1000_1000t_rx_status_ok
2692 : e1000_1000t_rx_status_not_ok;
2694 /* Set values to "undefined" */
2695 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2696 phy->local_rx = e1000_1000t_rx_status_undefined;
2697 phy->remote_rx = e1000_1000t_rx_status_undefined;
2704 * e1000_get_phy_info_igp - Retrieve igp PHY information
2705 * @hw: pointer to the HW structure
2707 * Read PHY status to determine if link is up. If link is up, then
2708 * set/determine 10base-T extended distance and polarity correction. Read
2709 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2710 * determine on the cable length, local and remote receiver.
2712 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2714 struct e1000_phy_info *phy = &hw->phy;
2719 DEBUGFUNC("e1000_get_phy_info_igp");
2721 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2726 DEBUGOUT("Phy info is only valid if link is up\n");
2727 return -E1000_ERR_CONFIG;
2730 phy->polarity_correction = true;
2732 ret_val = e1000_check_polarity_igp(hw);
2736 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2740 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2742 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2743 IGP01E1000_PSSR_SPEED_1000MBPS) {
2744 ret_val = phy->ops.get_cable_length(hw);
2748 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2752 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2753 ? e1000_1000t_rx_status_ok
2754 : e1000_1000t_rx_status_not_ok;
2756 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2757 ? e1000_1000t_rx_status_ok
2758 : e1000_1000t_rx_status_not_ok;
2760 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2761 phy->local_rx = e1000_1000t_rx_status_undefined;
2762 phy->remote_rx = e1000_1000t_rx_status_undefined;
2769 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2770 * @hw: pointer to the HW structure
2772 * Populates "phy" structure with various feature states.
2774 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2776 struct e1000_phy_info *phy = &hw->phy;
2781 DEBUGFUNC("e1000_get_phy_info_ife");
2783 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2788 DEBUGOUT("Phy info is only valid if link is up\n");
2789 return -E1000_ERR_CONFIG;
2792 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2795 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2797 if (phy->polarity_correction) {
2798 ret_val = e1000_check_polarity_ife(hw);
2802 /* Polarity is forced */
2803 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2804 ? e1000_rev_polarity_reversed
2805 : e1000_rev_polarity_normal);
2808 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2812 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2814 /* The following parameters are undefined for 10/100 operation. */
2815 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2816 phy->local_rx = e1000_1000t_rx_status_undefined;
2817 phy->remote_rx = e1000_1000t_rx_status_undefined;
2819 return E1000_SUCCESS;
2823 * e1000_phy_sw_reset_generic - PHY software reset
2824 * @hw: pointer to the HW structure
2826 * Does a software reset of the PHY by reading the PHY control register and
2827 * setting/write the control register reset bit to the PHY.
2829 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2834 DEBUGFUNC("e1000_phy_sw_reset_generic");
2836 if (!hw->phy.ops.read_reg)
2837 return E1000_SUCCESS;
2839 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2843 phy_ctrl |= MII_CR_RESET;
2844 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2854 * e1000_phy_hw_reset_generic - PHY hardware reset
2855 * @hw: pointer to the HW structure
2857 * Verify the reset block is not blocking us from resetting. Acquire
2858 * semaphore (if necessary) and read/set/write the device control reset
2859 * bit in the PHY. Wait the appropriate delay time for the device to
2860 * reset and release the semaphore (if necessary).
2862 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2864 struct e1000_phy_info *phy = &hw->phy;
2868 DEBUGFUNC("e1000_phy_hw_reset_generic");
2870 if (phy->ops.check_reset_block) {
2871 ret_val = phy->ops.check_reset_block(hw);
2873 return E1000_SUCCESS;
2876 ret_val = phy->ops.acquire(hw);
2880 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2881 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2882 E1000_WRITE_FLUSH(hw);
2884 usec_delay(phy->reset_delay_us);
2886 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2887 E1000_WRITE_FLUSH(hw);
2891 phy->ops.release(hw);
2893 return phy->ops.get_cfg_done(hw);
2897 * e1000_get_cfg_done_generic - Generic configuration done
2898 * @hw: pointer to the HW structure
2900 * Generic function to wait 10 milli-seconds for configuration to complete
2901 * and return success.
2903 s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2905 DEBUGFUNC("e1000_get_cfg_done_generic");
2909 return E1000_SUCCESS;
2913 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2914 * @hw: pointer to the HW structure
2916 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2918 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2920 DEBUGOUT("Running IGP 3 PHY init script\n");
2922 /* PHY init IGP 3 */
2923 /* Enable rise/fall, 10-mode work in class-A */
2924 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2925 /* Remove all caps from Replica path filter */
2926 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2927 /* Bias trimming for ADC, AFE and Driver (Default) */
2928 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2929 /* Increase Hybrid poly bias */
2930 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2931 /* Add 4% to Tx amplitude in Gig mode */
2932 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2933 /* Disable trimming (TTT) */
2934 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2935 /* Poly DC correction to 94.6% + 2% for all channels */
2936 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2937 /* ABS DC correction to 95.9% */
2938 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2939 /* BG temp curve trim */
2940 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2941 /* Increasing ADC OPAMP stage 1 currents to max */
2942 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2943 /* Force 1000 ( required for enabling PHY regs configuration) */
2944 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2945 /* Set upd_freq to 6 */
2946 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2948 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2949 /* Disable adaptive fixed FFE (Default) */
2950 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2951 /* Enable FFE hysteresis */
2952 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2953 /* Fixed FFE for short cable lengths */
2954 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2955 /* Fixed FFE for medium cable lengths */
2956 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2957 /* Fixed FFE for long cable lengths */
2958 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2959 /* Enable Adaptive Clip Threshold */
2960 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2961 /* AHT reset limit to 1 */
2962 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2963 /* Set AHT master delay to 127 msec */
2964 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2965 /* Set scan bits for AHT */
2966 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2967 /* Set AHT Preset bits */
2968 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2969 /* Change integ_factor of channel A to 3 */
2970 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2971 /* Change prop_factor of channels BCD to 8 */
2972 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2973 /* Change cg_icount + enable integbp for channels BCD */
2974 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2975 /* Change cg_icount + enable integbp + change prop_factor_master
2976 * to 8 for channel A
2978 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2979 /* Disable AHT in Slave mode on channel A */
2980 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2981 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2984 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2985 /* Enable restart AN on an1000_dis change */
2986 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2987 /* Enable wh_fifo read clock in 10/100 modes */
2988 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2989 /* Restart AN, Speed selection is 1000 */
2990 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2992 return E1000_SUCCESS;
2996 * e1000_get_phy_type_from_id - Get PHY type from id
2997 * @phy_id: phy_id read from the phy
2999 * Returns the phy type from the id.
3001 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
3003 enum e1000_phy_type phy_type = e1000_phy_unknown;
3006 case M88E1000_I_PHY_ID:
3007 case M88E1000_E_PHY_ID:
3008 case M88E1111_I_PHY_ID:
3009 case M88E1011_I_PHY_ID:
3010 case M88E1543_E_PHY_ID:
3011 case M88E1512_E_PHY_ID:
3012 case I347AT4_E_PHY_ID:
3013 case M88E1112_E_PHY_ID:
3014 case M88E1340M_E_PHY_ID:
3015 phy_type = e1000_phy_m88;
3017 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
3018 phy_type = e1000_phy_igp_2;
3020 case GG82563_E_PHY_ID:
3021 phy_type = e1000_phy_gg82563;
3023 case IGP03E1000_E_PHY_ID:
3024 phy_type = e1000_phy_igp_3;
3027 case IFE_PLUS_E_PHY_ID:
3028 case IFE_C_E_PHY_ID:
3029 phy_type = e1000_phy_ife;
3031 case BME1000_E_PHY_ID:
3032 case BME1000_E_PHY_ID_R2:
3033 phy_type = e1000_phy_bm;
3035 case I82578_E_PHY_ID:
3036 phy_type = e1000_phy_82578;
3038 case I82577_E_PHY_ID:
3039 phy_type = e1000_phy_82577;
3041 case I82579_E_PHY_ID:
3042 phy_type = e1000_phy_82579;
3045 phy_type = e1000_phy_i217;
3047 case I82580_I_PHY_ID:
3048 phy_type = e1000_phy_82580;
3051 phy_type = e1000_phy_i210;
3054 phy_type = e1000_phy_unknown;
3061 * e1000_determine_phy_address - Determines PHY address.
3062 * @hw: pointer to the HW structure
3064 * This uses a trial and error method to loop through possible PHY
3065 * addresses. It tests each by reading the PHY ID registers and
3066 * checking for a match.
3068 s32 e1000_determine_phy_address(struct e1000_hw *hw)
3072 enum e1000_phy_type phy_type = e1000_phy_unknown;
3074 hw->phy.id = phy_type;
3076 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
3077 hw->phy.addr = phy_addr;
3081 e1000_get_phy_id(hw);
3082 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3084 /* If phy_type is valid, break - we found our
3087 if (phy_type != e1000_phy_unknown)
3088 return E1000_SUCCESS;
3095 return -E1000_ERR_PHY_TYPE;
3099 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
3100 * @page: page to access
3101 * @reg: register to access
3103 * Returns the phy address for the page requested.
3105 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
3109 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
3116 * e1000_write_phy_reg_bm - Write BM PHY register
3117 * @hw: pointer to the HW structure
3118 * @offset: register offset to write to
3119 * @data: data to write at register offset
3121 * Acquires semaphore, if necessary, then writes the data to PHY register
3122 * at the offset. Release any acquired semaphores before exiting.
3124 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
3127 u32 page = offset >> IGP_PAGE_SHIFT;
3129 DEBUGFUNC("e1000_write_phy_reg_bm");
3131 ret_val = hw->phy.ops.acquire(hw);
3135 /* Page 800 works differently than the rest so it has its own func */
3136 if (page == BM_WUC_PAGE) {
3137 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3142 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3144 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3145 u32 page_shift, page_select;
3147 /* Page select is register 31 for phy address 1 and 22 for
3148 * phy address 2 and 3. Page select is shifted only for
3151 if (hw->phy.addr == 1) {
3152 page_shift = IGP_PAGE_SHIFT;
3153 page_select = IGP01E1000_PHY_PAGE_SELECT;
3156 page_select = BM_PHY_PAGE_SELECT;
3159 /* Page is shifted left, PHY expects (page x 32) */
3160 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3161 (page << page_shift));
3166 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3170 hw->phy.ops.release(hw);
3175 * e1000_read_phy_reg_bm - Read BM PHY register
3176 * @hw: pointer to the HW structure
3177 * @offset: register offset to be read
3178 * @data: pointer to the read data
3180 * Acquires semaphore, if necessary, then reads the PHY register at offset
3181 * and storing the retrieved information in data. Release any acquired
3182 * semaphores before exiting.
3184 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
3187 u32 page = offset >> IGP_PAGE_SHIFT;
3189 DEBUGFUNC("e1000_read_phy_reg_bm");
3191 ret_val = hw->phy.ops.acquire(hw);
3195 /* Page 800 works differently than the rest so it has its own func */
3196 if (page == BM_WUC_PAGE) {
3197 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3202 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3204 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3205 u32 page_shift, page_select;
3207 /* Page select is register 31 for phy address 1 and 22 for
3208 * phy address 2 and 3. Page select is shifted only for
3211 if (hw->phy.addr == 1) {
3212 page_shift = IGP_PAGE_SHIFT;
3213 page_select = IGP01E1000_PHY_PAGE_SELECT;
3216 page_select = BM_PHY_PAGE_SELECT;
3219 /* Page is shifted left, PHY expects (page x 32) */
3220 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3221 (page << page_shift));
3226 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3229 hw->phy.ops.release(hw);
3234 * e1000_read_phy_reg_bm2 - Read BM PHY register
3235 * @hw: pointer to the HW structure
3236 * @offset: register offset to be read
3237 * @data: pointer to the read data
3239 * Acquires semaphore, if necessary, then reads the PHY register at offset
3240 * and storing the retrieved information in data. Release any acquired
3241 * semaphores before exiting.
3243 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
3246 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3248 DEBUGFUNC("e1000_read_phy_reg_bm2");
3250 ret_val = hw->phy.ops.acquire(hw);
3254 /* Page 800 works differently than the rest so it has its own func */
3255 if (page == BM_WUC_PAGE) {
3256 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3263 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3264 /* Page is shifted left, PHY expects (page x 32) */
3265 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3272 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3275 hw->phy.ops.release(hw);
3280 * e1000_write_phy_reg_bm2 - Write BM PHY register
3281 * @hw: pointer to the HW structure
3282 * @offset: register offset to write to
3283 * @data: data to write at register offset
3285 * Acquires semaphore, if necessary, then writes the data to PHY register
3286 * at the offset. Release any acquired semaphores before exiting.
3288 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
3291 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3293 DEBUGFUNC("e1000_write_phy_reg_bm2");
3295 ret_val = hw->phy.ops.acquire(hw);
3299 /* Page 800 works differently than the rest so it has its own func */
3300 if (page == BM_WUC_PAGE) {
3301 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3308 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3309 /* Page is shifted left, PHY expects (page x 32) */
3310 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3317 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3321 hw->phy.ops.release(hw);
3326 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
3327 * @hw: pointer to the HW structure
3328 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
3330 * Assumes semaphore already acquired and phy_reg points to a valid memory
3331 * address to store contents of the BM_WUC_ENABLE_REG register.
3333 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3338 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm");
3341 return -E1000_ERR_PARAM;
3343 /* All page select, port ctrl and wakeup registers use phy address 1 */
3346 /* Select Port Control Registers page */
3347 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3349 DEBUGOUT("Could not set Port Control page\n");
3353 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3355 DEBUGOUT2("Could not read PHY register %d.%d\n",
3356 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3360 /* Enable both PHY wakeup mode and Wakeup register page writes.
3361 * Prevent a power state change by disabling ME and Host PHY wakeup.
3364 temp |= BM_WUC_ENABLE_BIT;
3365 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
3367 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3369 DEBUGOUT2("Could not write PHY register %d.%d\n",
3370 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3374 /* Select Host Wakeup Registers page - caller now able to write
3375 * registers on the Wakeup registers page
3377 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3381 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
3382 * @hw: pointer to the HW structure
3383 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
3385 * Restore BM_WUC_ENABLE_REG to its original value.
3387 * Assumes semaphore already acquired and *phy_reg is the contents of the
3388 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
3391 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3395 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm");
3398 return -E1000_ERR_PARAM;
3400 /* Select Port Control Registers page */
3401 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3403 DEBUGOUT("Could not set Port Control page\n");
3407 /* Restore 769.17 to its original value */
3408 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3410 DEBUGOUT2("Could not restore PHY register %d.%d\n",
3411 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3417 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
3418 * @hw: pointer to the HW structure
3419 * @offset: register offset to be read or written
3420 * @data: pointer to the data to read or write
3421 * @read: determines if operation is read or write
3422 * @page_set: BM_WUC_PAGE already set and access enabled
3424 * Read the PHY register at offset and store the retrieved information in
3425 * data, or write data to PHY register at offset. Note the procedure to
3426 * access the PHY wakeup registers is different than reading the other PHY
3427 * registers. It works as such:
3428 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
3429 * 2) Set page to 800 for host (801 if we were manageability)
3430 * 3) Write the address using the address opcode (0x11)
3431 * 4) Read or write the data using the data opcode (0x12)
3432 * 5) Restore 769.17.2 to its original value
3434 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
3435 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
3437 * Assumes semaphore is already acquired. When page_set==true, assumes
3438 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
3439 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
3441 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
3442 u16 *data, bool read, bool page_set)
3445 u16 reg = BM_PHY_REG_NUM(offset);
3446 u16 page = BM_PHY_REG_PAGE(offset);
3449 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
3451 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
3452 if ((hw->mac.type == e1000_pchlan) &&
3453 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
3454 DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
3458 /* Enable access to PHY wakeup registers */
3459 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3461 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3466 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3468 /* Write the Wakeup register page offset value using opcode 0x11 */
3469 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3471 DEBUGOUT1("Could not write address opcode to page %d\n", page);
3476 /* Read the Wakeup register page value using opcode 0x12 */
3477 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3480 /* Write the Wakeup register page value using opcode 0x12 */
3481 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3486 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3491 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3497 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3498 * @hw: pointer to the HW structure
3500 * In the case of a PHY power down to save power, or to turn off link during a
3501 * driver unload, or wake on lan is not enabled, restore the link to previous
3504 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3508 /* The PHY will retain its settings across a power down/up cycle */
3509 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3510 mii_reg &= ~MII_CR_POWER_DOWN;
3511 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3515 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3516 * @hw: pointer to the HW structure
3518 * In the case of a PHY power down to save power, or to turn off link during a
3519 * driver unload, or wake on lan is not enabled, restore the link to previous
3522 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3526 /* The PHY will retain its settings across a power down/up cycle */
3527 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3528 mii_reg |= MII_CR_POWER_DOWN;
3529 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3534 * __e1000_read_phy_reg_hv - Read HV PHY register
3535 * @hw: pointer to the HW structure
3536 * @offset: register offset to be read
3537 * @data: pointer to the read data
3538 * @locked: semaphore has already been acquired or not
3539 * @page_set: BM_WUC_PAGE already set and access enabled
3541 * Acquires semaphore, if necessary, then reads the PHY register at offset
3542 * and stores the retrieved information in data. Release any acquired
3543 * semaphore before exiting.
3545 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3546 bool locked, bool page_set)
3549 u16 page = BM_PHY_REG_PAGE(offset);
3550 u16 reg = BM_PHY_REG_NUM(offset);
3551 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3553 DEBUGFUNC("__e1000_read_phy_reg_hv");
3556 ret_val = hw->phy.ops.acquire(hw);
3560 /* Page 800 works differently than the rest so it has its own func */
3561 if (page == BM_WUC_PAGE) {
3562 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3567 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3568 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3574 if (page == HV_INTC_FC_PAGE_START)
3577 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3578 /* Page is shifted left, PHY expects (page x 32) */
3579 ret_val = e1000_set_page_igp(hw,
3580 (page << IGP_PAGE_SHIFT));
3582 hw->phy.addr = phy_addr;
3589 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3590 page << IGP_PAGE_SHIFT, reg);
3592 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3596 hw->phy.ops.release(hw);
3602 * e1000_read_phy_reg_hv - Read HV PHY register
3603 * @hw: pointer to the HW structure
3604 * @offset: register offset to be read
3605 * @data: pointer to the read data
3607 * Acquires semaphore then reads the PHY register at offset and stores
3608 * the retrieved information in data. Release the acquired semaphore
3611 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3613 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
3617 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3618 * @hw: pointer to the HW structure
3619 * @offset: register offset to be read
3620 * @data: pointer to the read data
3622 * Reads the PHY register at offset and stores the retrieved information
3623 * in data. Assumes semaphore already acquired.
3625 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3627 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
3631 * e1000_read_phy_reg_page_hv - Read HV PHY register
3632 * @hw: pointer to the HW structure
3633 * @offset: register offset to write to
3634 * @data: data to write at register offset
3636 * Reads the PHY register at offset and stores the retrieved information
3637 * in data. Assumes semaphore already acquired and page already set.
3639 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3641 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
3645 * __e1000_write_phy_reg_hv - Write HV PHY register
3646 * @hw: pointer to the HW structure
3647 * @offset: register offset to write to
3648 * @data: data to write at register offset
3649 * @locked: semaphore has already been acquired or not
3650 * @page_set: BM_WUC_PAGE already set and access enabled
3652 * Acquires semaphore, if necessary, then writes the data to PHY register
3653 * at the offset. Release any acquired semaphores before exiting.
3655 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3656 bool locked, bool page_set)
3659 u16 page = BM_PHY_REG_PAGE(offset);
3660 u16 reg = BM_PHY_REG_NUM(offset);
3661 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3663 DEBUGFUNC("__e1000_write_phy_reg_hv");
3666 ret_val = hw->phy.ops.acquire(hw);
3670 /* Page 800 works differently than the rest so it has its own func */
3671 if (page == BM_WUC_PAGE) {
3672 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3677 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3678 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3684 if (page == HV_INTC_FC_PAGE_START)
3687 /* Workaround MDIO accesses being disabled after entering IEEE
3688 * Power Down (when bit 11 of the PHY Control register is set)
3690 if ((hw->phy.type == e1000_phy_82578) &&
3691 (hw->phy.revision >= 1) &&
3692 (hw->phy.addr == 2) &&
3693 !(MAX_PHY_REG_ADDRESS & reg) &&
3694 (data & (1 << 11))) {
3696 ret_val = e1000_access_phy_debug_regs_hv(hw,
3703 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3704 /* Page is shifted left, PHY expects (page x 32) */
3705 ret_val = e1000_set_page_igp(hw,
3706 (page << IGP_PAGE_SHIFT));
3708 hw->phy.addr = phy_addr;
3715 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3716 page << IGP_PAGE_SHIFT, reg);
3718 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3723 hw->phy.ops.release(hw);
3729 * e1000_write_phy_reg_hv - Write HV PHY register
3730 * @hw: pointer to the HW structure
3731 * @offset: register offset to write to
3732 * @data: data to write at register offset
3734 * Acquires semaphore then writes the data to PHY register at the offset.
3735 * Release the acquired semaphores before exiting.
3737 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3739 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
3743 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3744 * @hw: pointer to the HW structure
3745 * @offset: register offset to write to
3746 * @data: data to write at register offset
3748 * Writes the data to PHY register at the offset. Assumes semaphore
3751 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3753 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
3757 * e1000_write_phy_reg_page_hv - Write HV PHY register
3758 * @hw: pointer to the HW structure
3759 * @offset: register offset to write to
3760 * @data: data to write at register offset
3762 * Writes the data to PHY register at the offset. Assumes semaphore
3763 * already acquired and page already set.
3765 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3767 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
3771 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3772 * @page: page to be accessed
3774 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3778 if (page >= HV_INTC_FC_PAGE_START)
3785 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3786 * @hw: pointer to the HW structure
3787 * @offset: register offset to be read or written
3788 * @data: pointer to the data to be read or written
3789 * @read: determines if operation is read or write
3791 * Reads the PHY register at offset and stores the retreived information
3792 * in data. Assumes semaphore already acquired. Note that the procedure
3793 * to access these regs uses the address port and data port to read/write.
3794 * These accesses done with PHY address 2 and without using pages.
3796 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3797 u16 *data, bool read)
3803 DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3805 /* This takes care of the difference with desktop vs mobile phy */
3806 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3807 I82578_ADDR_REG : I82577_ADDR_REG);
3808 data_reg = addr_reg + 1;
3810 /* All operations in this function are phy address 2 */
3813 /* masking with 0x3F to remove the page from offset */
3814 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3816 DEBUGOUT("Could not write the Address Offset port register\n");
3820 /* Read or write the data value next */
3822 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3824 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3827 DEBUGOUT("Could not access the Data port register\n");
3833 * e1000_link_stall_workaround_hv - Si workaround
3834 * @hw: pointer to the HW structure
3836 * This function works around a Si bug where the link partner can get
3837 * a link up indication before the PHY does. If small packets are sent
3838 * by the link partner they can be placed in the packet buffer without
3839 * being properly accounted for by the PHY and will stall preventing
3840 * further packets from being received. The workaround is to clear the
3841 * packet buffer after the PHY detects link up.
3843 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3845 s32 ret_val = E1000_SUCCESS;
3848 DEBUGFUNC("e1000_link_stall_workaround_hv");
3850 if (hw->phy.type != e1000_phy_82578)
3851 return E1000_SUCCESS;
3853 /* Do not apply workaround if in PHY loopback bit 14 set */
3854 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3855 if (data & PHY_CONTROL_LB)
3856 return E1000_SUCCESS;
3858 /* check if link is up and at 1Gbps */
3859 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3863 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3864 BM_CS_STATUS_SPEED_MASK);
3866 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3867 BM_CS_STATUS_SPEED_1000))
3868 return E1000_SUCCESS;
3872 /* flush the packets in the fifo buffer */
3873 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3874 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3875 HV_MUX_DATA_CTRL_FORCE_SPEED));
3879 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3880 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3884 * e1000_check_polarity_82577 - Checks the polarity.
3885 * @hw: pointer to the HW structure
3887 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3889 * Polarity is determined based on the PHY specific status register.
3891 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3893 struct e1000_phy_info *phy = &hw->phy;
3897 DEBUGFUNC("e1000_check_polarity_82577");
3899 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3902 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3903 ? e1000_rev_polarity_reversed
3904 : e1000_rev_polarity_normal);
3910 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3911 * @hw: pointer to the HW structure
3913 * Calls the PHY setup function to force speed and duplex.
3915 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3917 struct e1000_phy_info *phy = &hw->phy;
3922 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3924 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3928 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3930 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3936 if (phy->autoneg_wait_to_complete) {
3937 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3939 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3945 DEBUGOUT("Link taking longer than expected.\n");
3948 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3956 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3957 * @hw: pointer to the HW structure
3959 * Read PHY status to determine if link is up. If link is up, then
3960 * set/determine 10base-T extended distance and polarity correction. Read
3961 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3962 * determine on the cable length, local and remote receiver.
3964 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3966 struct e1000_phy_info *phy = &hw->phy;
3971 DEBUGFUNC("e1000_get_phy_info_82577");
3973 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3978 DEBUGOUT("Phy info is only valid if link is up\n");
3979 return -E1000_ERR_CONFIG;
3982 phy->polarity_correction = true;
3984 ret_val = e1000_check_polarity_82577(hw);
3988 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3992 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3994 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3995 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3996 ret_val = hw->phy.ops.get_cable_length(hw);
4000 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
4004 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
4005 ? e1000_1000t_rx_status_ok
4006 : e1000_1000t_rx_status_not_ok;
4008 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
4009 ? e1000_1000t_rx_status_ok
4010 : e1000_1000t_rx_status_not_ok;
4012 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
4013 phy->local_rx = e1000_1000t_rx_status_undefined;
4014 phy->remote_rx = e1000_1000t_rx_status_undefined;
4017 return E1000_SUCCESS;
4021 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
4022 * @hw: pointer to the HW structure
4024 * Reads the diagnostic status register and verifies result is valid before
4025 * placing it in the phy_cable_length field.
4027 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
4029 struct e1000_phy_info *phy = &hw->phy;
4031 u16 phy_data, length;
4033 DEBUGFUNC("e1000_get_cable_length_82577");
4035 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4039 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
4040 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
4042 if (length == E1000_CABLE_LENGTH_UNDEFINED)
4043 return -E1000_ERR_PHY;
4045 phy->cable_length = length;
4047 return E1000_SUCCESS;
4051 * e1000_write_phy_reg_gs40g - Write GS40G PHY register
4052 * @hw: pointer to the HW structure
4053 * @offset: register offset to write to
4054 * @data: data to write at register offset
4056 * Acquires semaphore, if necessary, then writes the data to PHY register
4057 * at the offset. Release any acquired semaphores before exiting.
4059 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
4062 u16 page = offset >> GS40G_PAGE_SHIFT;
4064 DEBUGFUNC("e1000_write_phy_reg_gs40g");
4066 offset = offset & GS40G_OFFSET_MASK;
4067 ret_val = hw->phy.ops.acquire(hw);
4071 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4074 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
4077 hw->phy.ops.release(hw);
4082 * e1000_read_phy_reg_gs40g - Read GS40G PHY register
4083 * @hw: pointer to the HW structure
4084 * @offset: lower half is register offset to read to
4085 * upper half is page to use.
4086 * @data: data to read at register offset
4088 * Acquires semaphore, if necessary, then reads the data in the PHY register
4089 * at the offset. Release any acquired semaphores before exiting.
4091 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
4094 u16 page = offset >> GS40G_PAGE_SHIFT;
4096 DEBUGFUNC("e1000_read_phy_reg_gs40g");
4098 offset = offset & GS40G_OFFSET_MASK;
4099 ret_val = hw->phy.ops.acquire(hw);
4103 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4106 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
4109 hw->phy.ops.release(hw);
4114 * e1000_read_phy_reg_mphy - Read mPHY control register
4115 * @hw: pointer to the HW structure
4116 * @address: address to be read
4117 * @data: pointer to the read data
4119 * Reads the mPHY control register in the PHY at offset and stores the
4120 * information read to data.
4122 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data)
4125 bool locked = false;
4128 DEBUGFUNC("e1000_read_phy_reg_mphy");
4130 /* Check if mPHY is ready to read/write operations */
4131 ready = e1000_is_mphy_ready(hw);
4133 return -E1000_ERR_PHY;
4135 /* Check if mPHY access is disabled and enable it if so */
4136 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4137 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4139 ready = e1000_is_mphy_ready(hw);
4141 return -E1000_ERR_PHY;
4142 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4143 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4146 /* Set the address that we want to read */
4147 ready = e1000_is_mphy_ready(hw);
4149 return -E1000_ERR_PHY;
4151 /* We mask address, because we want to use only current lane */
4152 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK &
4153 ~E1000_MPHY_ADDRESS_FNC_OVERRIDE) |
4154 (address & E1000_MPHY_ADDRESS_MASK);
4155 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4157 /* Read data from the address */
4158 ready = e1000_is_mphy_ready(hw);
4160 return -E1000_ERR_PHY;
4161 *data = E1000_READ_REG(hw, E1000_MPHY_DATA);
4163 /* Disable access to mPHY if it was originally disabled */
4165 ready = e1000_is_mphy_ready(hw);
4167 return -E1000_ERR_PHY;
4168 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4169 E1000_MPHY_DIS_ACCESS);
4171 return E1000_SUCCESS;
4175 * e1000_write_phy_reg_mphy - Write mPHY control register
4176 * @hw: pointer to the HW structure
4177 * @address: address to write to
4178 * @data: data to write to register at offset
4179 * @line_override: used when we want to use different line than default one
4181 * Writes data to mPHY control register.
4183 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,
4187 bool locked = false;
4190 DEBUGFUNC("e1000_write_phy_reg_mphy");
4192 /* Check if mPHY is ready to read/write operations */
4193 ready = e1000_is_mphy_ready(hw);
4195 return -E1000_ERR_PHY;
4197 /* Check if mPHY access is disabled and enable it if so */
4198 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4199 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4201 ready = e1000_is_mphy_ready(hw);
4203 return -E1000_ERR_PHY;
4204 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4205 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4208 /* Set the address that we want to read */
4209 ready = e1000_is_mphy_ready(hw);
4211 return -E1000_ERR_PHY;
4213 /* We mask address, because we want to use only current lane */
4215 mphy_ctrl |= E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4217 mphy_ctrl &= ~E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4218 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK) |
4219 (address & E1000_MPHY_ADDRESS_MASK);
4220 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4222 /* Read data from the address */
4223 ready = e1000_is_mphy_ready(hw);
4225 return -E1000_ERR_PHY;
4226 E1000_WRITE_REG(hw, E1000_MPHY_DATA, data);
4228 /* Disable access to mPHY if it was originally disabled */
4230 ready = e1000_is_mphy_ready(hw);
4232 return -E1000_ERR_PHY;
4233 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4234 E1000_MPHY_DIS_ACCESS);
4236 return E1000_SUCCESS;
4240 * e1000_is_mphy_ready - Check if mPHY control register is not busy
4241 * @hw: pointer to the HW structure
4243 * Returns mPHY control register status.
4245 bool e1000_is_mphy_ready(struct e1000_hw *hw)
4247 u16 retry_count = 0;
4251 while (retry_count < 2) {
4252 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4253 if (mphy_ctrl & E1000_MPHY_BUSY) {
4263 DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n");
4269 * __e1000_access_xmdio_reg - Read/write XMDIO register
4270 * @hw: pointer to the HW structure
4271 * @address: XMDIO address to program
4272 * @dev_addr: device address to program
4273 * @data: pointer to value to read/write from/to the XMDIO address
4274 * @read: boolean flag to indicate read or write
4276 static s32 __e1000_access_xmdio_reg(struct e1000_hw *hw, u16 address,
4277 u8 dev_addr, u16 *data, bool read)
4281 DEBUGFUNC("__e1000_access_xmdio_reg");
4283 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);
4287 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address);
4291 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA |
4297 ret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data);
4299 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data);
4303 /* Recalibrate the device back to 0 */
4304 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0);
4312 * e1000_read_xmdio_reg - Read XMDIO register
4313 * @hw: pointer to the HW structure
4314 * @addr: XMDIO address to program
4315 * @dev_addr: device address to program
4316 * @data: value to be read from the EMI address
4318 s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data)
4320 DEBUGFUNC("e1000_read_xmdio_reg");
4322 return __e1000_access_xmdio_reg(hw, addr, dev_addr, data, true);
4326 * e1000_write_xmdio_reg - Write XMDIO register
4327 * @hw: pointer to the HW structure
4328 * @addr: XMDIO address to program
4329 * @dev_addr: device address to program
4330 * @data: value to be written to the XMDIO address
4332 s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data)
4334 DEBUGFUNC("e1000_write_xmdio_reg");
4336 return __e1000_access_xmdio_reg(hw, addr, dev_addr, &data,