1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2015, Intel Corporation
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
10 1. Redistributions of source code must retain the above copyright notice,
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14 notice, this list of conditions and the following disclaimer in the
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19 this software without specific prior written permission.
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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31 POSSIBILITY OF SUCH DAMAGE.
33 ******************************************************************************/
36 #include "e1000_api.h"
38 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
39 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
40 u16 *data, bool read, bool page_set);
41 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
42 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
43 u16 *data, bool read);
45 /* Cable length tables */
46 static const u16 e1000_m88_cable_length_table[] = {
47 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
48 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
49 (sizeof(e1000_m88_cable_length_table) / \
50 sizeof(e1000_m88_cable_length_table[0]))
52 static const u16 e1000_igp_2_cable_length_table[] = {
53 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
54 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
55 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
56 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
57 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
58 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
59 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
61 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
62 (sizeof(e1000_igp_2_cable_length_table) / \
63 sizeof(e1000_igp_2_cable_length_table[0]))
66 * e1000_init_phy_ops_generic - Initialize PHY function pointers
67 * @hw: pointer to the HW structure
69 * Setups up the function pointers to no-op functions
71 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
73 struct e1000_phy_info *phy = &hw->phy;
74 DEBUGFUNC("e1000_init_phy_ops_generic");
76 /* Initialize function pointers */
77 phy->ops.init_params = e1000_null_ops_generic;
78 phy->ops.acquire = e1000_null_ops_generic;
79 phy->ops.check_polarity = e1000_null_ops_generic;
80 phy->ops.check_reset_block = e1000_null_ops_generic;
81 phy->ops.commit = e1000_null_ops_generic;
82 phy->ops.force_speed_duplex = e1000_null_ops_generic;
83 phy->ops.get_cfg_done = e1000_null_ops_generic;
84 phy->ops.get_cable_length = e1000_null_ops_generic;
85 phy->ops.get_info = e1000_null_ops_generic;
86 phy->ops.set_page = e1000_null_set_page;
87 phy->ops.read_reg = e1000_null_read_reg;
88 phy->ops.read_reg_locked = e1000_null_read_reg;
89 phy->ops.read_reg_page = e1000_null_read_reg;
90 phy->ops.release = e1000_null_phy_generic;
91 phy->ops.reset = e1000_null_ops_generic;
92 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
93 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
94 phy->ops.write_reg = e1000_null_write_reg;
95 phy->ops.write_reg_locked = e1000_null_write_reg;
96 phy->ops.write_reg_page = e1000_null_write_reg;
97 phy->ops.power_up = e1000_null_phy_generic;
98 phy->ops.power_down = e1000_null_phy_generic;
99 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
100 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
101 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
105 * e1000_null_set_page - No-op function, return 0
106 * @hw: pointer to the HW structure
108 s32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw,
109 u16 E1000_UNUSEDARG data)
111 DEBUGFUNC("e1000_null_set_page");
112 return E1000_SUCCESS;
116 * e1000_null_read_reg - No-op function, return 0
117 * @hw: pointer to the HW structure
119 s32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw,
120 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data)
122 DEBUGFUNC("e1000_null_read_reg");
123 return E1000_SUCCESS;
127 * e1000_null_phy_generic - No-op function, return void
128 * @hw: pointer to the HW structure
130 void e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw)
132 DEBUGFUNC("e1000_null_phy_generic");
137 * e1000_null_lplu_state - No-op function, return 0
138 * @hw: pointer to the HW structure
140 s32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw,
141 bool E1000_UNUSEDARG active)
143 DEBUGFUNC("e1000_null_lplu_state");
144 return E1000_SUCCESS;
148 * e1000_null_write_reg - No-op function, return 0
149 * @hw: pointer to the HW structure
151 s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw,
152 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data)
154 DEBUGFUNC("e1000_null_write_reg");
155 return E1000_SUCCESS;
159 * e1000_read_i2c_byte_null - No-op function, return 0
160 * @hw: pointer to hardware structure
161 * @byte_offset: byte offset to write
162 * @dev_addr: device address
163 * @data: data value read
166 s32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
167 u8 E1000_UNUSEDARG byte_offset,
168 u8 E1000_UNUSEDARG dev_addr,
169 u8 E1000_UNUSEDARG *data)
171 DEBUGFUNC("e1000_read_i2c_byte_null");
172 return E1000_SUCCESS;
176 * e1000_write_i2c_byte_null - No-op function, return 0
177 * @hw: pointer to hardware structure
178 * @byte_offset: byte offset to write
179 * @dev_addr: device address
180 * @data: data value to write
183 s32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
184 u8 E1000_UNUSEDARG byte_offset,
185 u8 E1000_UNUSEDARG dev_addr,
186 u8 E1000_UNUSEDARG data)
188 DEBUGFUNC("e1000_write_i2c_byte_null");
189 return E1000_SUCCESS;
193 * e1000_check_reset_block_generic - Check if PHY reset is blocked
194 * @hw: pointer to the HW structure
196 * Read the PHY management control register and check whether a PHY reset
197 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
198 * return E1000_BLK_PHY_RESET (12).
200 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
204 DEBUGFUNC("e1000_check_reset_block");
206 manc = E1000_READ_REG(hw, E1000_MANC);
208 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
209 E1000_BLK_PHY_RESET : E1000_SUCCESS;
213 * e1000_get_phy_id - Retrieve the PHY ID and revision
214 * @hw: pointer to the HW structure
216 * Reads the PHY registers and stores the PHY ID and possibly the PHY
217 * revision in the hardware structure.
219 s32 e1000_get_phy_id(struct e1000_hw *hw)
221 struct e1000_phy_info *phy = &hw->phy;
222 s32 ret_val = E1000_SUCCESS;
226 DEBUGFUNC("e1000_get_phy_id");
228 if (!phy->ops.read_reg)
229 return E1000_SUCCESS;
231 while (retry_count < 2) {
232 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
236 phy->id = (u32)(phy_id << 16);
238 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
242 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
243 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
245 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
246 return E1000_SUCCESS;
251 return E1000_SUCCESS;
255 * e1000_phy_reset_dsp_generic - Reset PHY DSP
256 * @hw: pointer to the HW structure
258 * Reset the digital signal processor.
260 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
264 DEBUGFUNC("e1000_phy_reset_dsp_generic");
266 if (!hw->phy.ops.write_reg)
267 return E1000_SUCCESS;
269 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
273 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
277 * e1000_read_phy_reg_mdic - Read MDI control register
278 * @hw: pointer to the HW structure
279 * @offset: register offset to be read
280 * @data: pointer to the read data
282 * Reads the MDI control register in the PHY at offset and stores the
283 * information read to data.
285 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
287 struct e1000_phy_info *phy = &hw->phy;
290 DEBUGFUNC("e1000_read_phy_reg_mdic");
292 if (offset > MAX_PHY_REG_ADDRESS) {
293 DEBUGOUT1("PHY Address %d is out of range\n", offset);
294 return -E1000_ERR_PARAM;
297 /* Set up Op-code, Phy Address, and register offset in the MDI
298 * Control register. The MAC will take care of interfacing with the
299 * PHY to retrieve the desired data.
301 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
302 (phy->addr << E1000_MDIC_PHY_SHIFT) |
303 (E1000_MDIC_OP_READ));
305 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
307 /* Poll the ready bit to see if the MDI read completed
308 * Increasing the time out as testing showed failures with
311 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
313 mdic = E1000_READ_REG(hw, E1000_MDIC);
314 if (mdic & E1000_MDIC_READY)
317 if (!(mdic & E1000_MDIC_READY)) {
318 DEBUGOUT("MDI Read did not complete\n");
319 return -E1000_ERR_PHY;
321 if (mdic & E1000_MDIC_ERROR) {
322 DEBUGOUT("MDI Error\n");
323 return -E1000_ERR_PHY;
325 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
326 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n",
328 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
329 return -E1000_ERR_PHY;
333 /* Allow some time after each MDIC transaction to avoid
334 * reading duplicate data in the next MDIC transaction.
336 if (hw->mac.type == e1000_pch2lan)
339 return E1000_SUCCESS;
343 * e1000_write_phy_reg_mdic - Write MDI control register
344 * @hw: pointer to the HW structure
345 * @offset: register offset to write to
346 * @data: data to write to register at offset
348 * Writes data to MDI control register in the PHY at offset.
350 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
352 struct e1000_phy_info *phy = &hw->phy;
355 DEBUGFUNC("e1000_write_phy_reg_mdic");
357 if (offset > MAX_PHY_REG_ADDRESS) {
358 DEBUGOUT1("PHY Address %d is out of range\n", offset);
359 return -E1000_ERR_PARAM;
362 /* Set up Op-code, Phy Address, and register offset in the MDI
363 * Control register. The MAC will take care of interfacing with the
364 * PHY to retrieve the desired data.
366 mdic = (((u32)data) |
367 (offset << E1000_MDIC_REG_SHIFT) |
368 (phy->addr << E1000_MDIC_PHY_SHIFT) |
369 (E1000_MDIC_OP_WRITE));
371 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
373 /* Poll the ready bit to see if the MDI read completed
374 * Increasing the time out as testing showed failures with
377 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
379 mdic = E1000_READ_REG(hw, E1000_MDIC);
380 if (mdic & E1000_MDIC_READY)
383 if (!(mdic & E1000_MDIC_READY)) {
384 DEBUGOUT("MDI Write did not complete\n");
385 return -E1000_ERR_PHY;
387 if (mdic & E1000_MDIC_ERROR) {
388 DEBUGOUT("MDI Error\n");
389 return -E1000_ERR_PHY;
391 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
392 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n",
394 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
395 return -E1000_ERR_PHY;
398 /* Allow some time after each MDIC transaction to avoid
399 * reading duplicate data in the next MDIC transaction.
401 if (hw->mac.type == e1000_pch2lan)
404 return E1000_SUCCESS;
408 * e1000_read_phy_reg_i2c - Read PHY register using i2c
409 * @hw: pointer to the HW structure
410 * @offset: register offset to be read
411 * @data: pointer to the read data
413 * Reads the PHY register at offset using the i2c interface and stores the
414 * retrieved information in data.
416 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
418 struct e1000_phy_info *phy = &hw->phy;
421 DEBUGFUNC("e1000_read_phy_reg_i2c");
423 /* Set up Op-code, Phy Address, and register address in the I2CCMD
424 * register. The MAC will take care of interfacing with the
425 * PHY to retrieve the desired data.
427 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
428 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
429 (E1000_I2CCMD_OPCODE_READ));
431 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
433 /* Poll the ready bit to see if the I2C read completed */
434 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
436 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
437 if (i2ccmd & E1000_I2CCMD_READY)
440 if (!(i2ccmd & E1000_I2CCMD_READY)) {
441 DEBUGOUT("I2CCMD Read did not complete\n");
442 return -E1000_ERR_PHY;
444 if (i2ccmd & E1000_I2CCMD_ERROR) {
445 DEBUGOUT("I2CCMD Error bit set\n");
446 return -E1000_ERR_PHY;
449 /* Need to byte-swap the 16-bit value. */
450 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
452 return E1000_SUCCESS;
456 * e1000_write_phy_reg_i2c - Write PHY register using i2c
457 * @hw: pointer to the HW structure
458 * @offset: register offset to write to
459 * @data: data to write at register offset
461 * Writes the data to PHY register at the offset using the i2c interface.
463 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
465 struct e1000_phy_info *phy = &hw->phy;
467 u16 phy_data_swapped;
469 DEBUGFUNC("e1000_write_phy_reg_i2c");
471 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
472 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
473 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
475 return -E1000_ERR_CONFIG;
478 /* Swap the data bytes for the I2C interface */
479 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
481 /* Set up Op-code, Phy Address, and register address in the I2CCMD
482 * register. The MAC will take care of interfacing with the
483 * PHY to retrieve the desired data.
485 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
486 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
487 E1000_I2CCMD_OPCODE_WRITE |
490 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
492 /* Poll the ready bit to see if the I2C read completed */
493 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
495 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
496 if (i2ccmd & E1000_I2CCMD_READY)
499 if (!(i2ccmd & E1000_I2CCMD_READY)) {
500 DEBUGOUT("I2CCMD Write did not complete\n");
501 return -E1000_ERR_PHY;
503 if (i2ccmd & E1000_I2CCMD_ERROR) {
504 DEBUGOUT("I2CCMD Error bit set\n");
505 return -E1000_ERR_PHY;
508 return E1000_SUCCESS;
512 * e1000_read_sfp_data_byte - Reads SFP module data.
513 * @hw: pointer to the HW structure
514 * @offset: byte location offset to be read
515 * @data: read data buffer pointer
517 * Reads one byte from SFP module data stored
518 * in SFP resided EEPROM memory or SFP diagnostic area.
519 * Function should be called with
520 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
521 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
524 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
530 DEBUGFUNC("e1000_read_sfp_data_byte");
532 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
533 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
534 return -E1000_ERR_PHY;
537 /* Set up Op-code, EEPROM Address,in the I2CCMD
538 * register. The MAC will take care of interfacing with the
539 * EEPROM to retrieve the desired data.
541 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
542 E1000_I2CCMD_OPCODE_READ);
544 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
546 /* Poll the ready bit to see if the I2C read completed */
547 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
549 data_local = E1000_READ_REG(hw, E1000_I2CCMD);
550 if (data_local & E1000_I2CCMD_READY)
553 if (!(data_local & E1000_I2CCMD_READY)) {
554 DEBUGOUT("I2CCMD Read did not complete\n");
555 return -E1000_ERR_PHY;
557 if (data_local & E1000_I2CCMD_ERROR) {
558 DEBUGOUT("I2CCMD Error bit set\n");
559 return -E1000_ERR_PHY;
561 *data = (u8) data_local & 0xFF;
563 return E1000_SUCCESS;
567 * e1000_write_sfp_data_byte - Writes SFP module data.
568 * @hw: pointer to the HW structure
569 * @offset: byte location offset to write to
570 * @data: data to write
572 * Writes one byte to SFP module data stored
573 * in SFP resided EEPROM memory or SFP diagnostic area.
574 * Function should be called with
575 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
576 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
579 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
585 DEBUGFUNC("e1000_write_sfp_data_byte");
587 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
588 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
589 return -E1000_ERR_PHY;
591 /* The programming interface is 16 bits wide
592 * so we need to read the whole word first
593 * then update appropriate byte lane and write
594 * the updated word back.
596 /* Set up Op-code, EEPROM Address,in the I2CCMD
597 * register. The MAC will take care of interfacing
598 * with an EEPROM to write the data given.
600 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
601 E1000_I2CCMD_OPCODE_READ);
602 /* Set a command to read single word */
603 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
604 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
606 /* Poll the ready bit to see if lastly
607 * launched I2C operation completed
609 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
610 if (i2ccmd & E1000_I2CCMD_READY) {
611 /* Check if this is READ or WRITE phase */
612 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
613 E1000_I2CCMD_OPCODE_READ) {
614 /* Write the selected byte
615 * lane and update whole word
617 data_local = i2ccmd & 0xFF00;
620 E1000_I2CCMD_REG_ADDR_SHIFT) |
621 E1000_I2CCMD_OPCODE_WRITE | data_local);
622 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
628 if (!(i2ccmd & E1000_I2CCMD_READY)) {
629 DEBUGOUT("I2CCMD Write did not complete\n");
630 return -E1000_ERR_PHY;
632 if (i2ccmd & E1000_I2CCMD_ERROR) {
633 DEBUGOUT("I2CCMD Error bit set\n");
634 return -E1000_ERR_PHY;
636 return E1000_SUCCESS;
640 * e1000_read_phy_reg_m88 - Read m88 PHY register
641 * @hw: pointer to the HW structure
642 * @offset: register offset to be read
643 * @data: pointer to the read data
645 * Acquires semaphore, if necessary, then reads the PHY register at offset
646 * and storing the retrieved information in data. Release any acquired
647 * semaphores before exiting.
649 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
653 DEBUGFUNC("e1000_read_phy_reg_m88");
655 if (!hw->phy.ops.acquire)
656 return E1000_SUCCESS;
658 ret_val = hw->phy.ops.acquire(hw);
662 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
665 hw->phy.ops.release(hw);
671 * e1000_write_phy_reg_m88 - Write m88 PHY register
672 * @hw: pointer to the HW structure
673 * @offset: register offset to write to
674 * @data: data to write at register offset
676 * Acquires semaphore, if necessary, then writes the data to PHY register
677 * at the offset. Release any acquired semaphores before exiting.
679 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
683 DEBUGFUNC("e1000_write_phy_reg_m88");
685 if (!hw->phy.ops.acquire)
686 return E1000_SUCCESS;
688 ret_val = hw->phy.ops.acquire(hw);
692 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
695 hw->phy.ops.release(hw);
701 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
702 * @hw: pointer to the HW structure
703 * @page: page to set (shifted left when necessary)
705 * Sets PHY page required for PHY register access. Assumes semaphore is
706 * already acquired. Note, this function sets phy.addr to 1 so the caller
707 * must set it appropriately (if necessary) after this function returns.
709 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
711 DEBUGFUNC("e1000_set_page_igp");
713 DEBUGOUT1("Setting page 0x%x\n", page);
717 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
721 * __e1000_read_phy_reg_igp - Read igp PHY register
722 * @hw: pointer to the HW structure
723 * @offset: register offset to be read
724 * @data: pointer to the read data
725 * @locked: semaphore has already been acquired or not
727 * Acquires semaphore, if necessary, then reads the PHY register at offset
728 * and stores the retrieved information in data. Release any acquired
729 * semaphores before exiting.
731 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
734 s32 ret_val = E1000_SUCCESS;
736 DEBUGFUNC("__e1000_read_phy_reg_igp");
739 if (!hw->phy.ops.acquire)
740 return E1000_SUCCESS;
742 ret_val = hw->phy.ops.acquire(hw);
747 if (offset > MAX_PHY_MULTI_PAGE_REG)
748 ret_val = e1000_write_phy_reg_mdic(hw,
749 IGP01E1000_PHY_PAGE_SELECT,
752 ret_val = e1000_read_phy_reg_mdic(hw,
753 MAX_PHY_REG_ADDRESS & offset,
756 hw->phy.ops.release(hw);
762 * e1000_read_phy_reg_igp - Read igp PHY register
763 * @hw: pointer to the HW structure
764 * @offset: register offset to be read
765 * @data: pointer to the read data
767 * Acquires semaphore then reads the PHY register at offset and stores the
768 * retrieved information in data.
769 * Release the acquired semaphore before exiting.
771 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
773 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE);
777 * e1000_read_phy_reg_igp_locked - Read igp PHY register
778 * @hw: pointer to the HW structure
779 * @offset: register offset to be read
780 * @data: pointer to the read data
782 * Reads the PHY register at offset and stores the retrieved information
783 * in data. Assumes semaphore already acquired.
785 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
787 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE);
791 * e1000_write_phy_reg_igp - Write igp PHY register
792 * @hw: pointer to the HW structure
793 * @offset: register offset to write to
794 * @data: data to write at register offset
795 * @locked: semaphore has already been acquired or not
797 * Acquires semaphore, if necessary, then writes the data to PHY register
798 * at the offset. Release any acquired semaphores before exiting.
800 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
803 s32 ret_val = E1000_SUCCESS;
805 DEBUGFUNC("e1000_write_phy_reg_igp");
808 if (!hw->phy.ops.acquire)
809 return E1000_SUCCESS;
811 ret_val = hw->phy.ops.acquire(hw);
816 if (offset > MAX_PHY_MULTI_PAGE_REG)
817 ret_val = e1000_write_phy_reg_mdic(hw,
818 IGP01E1000_PHY_PAGE_SELECT,
821 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
825 hw->phy.ops.release(hw);
831 * e1000_write_phy_reg_igp - Write igp PHY register
832 * @hw: pointer to the HW structure
833 * @offset: register offset to write to
834 * @data: data to write at register offset
836 * Acquires semaphore then writes the data to PHY register
837 * at the offset. Release any acquired semaphores before exiting.
839 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
841 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE);
845 * e1000_write_phy_reg_igp_locked - Write igp PHY register
846 * @hw: pointer to the HW structure
847 * @offset: register offset to write to
848 * @data: data to write at register offset
850 * Writes the data to PHY register at the offset.
851 * Assumes semaphore already acquired.
853 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
855 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE);
859 * __e1000_read_kmrn_reg - Read kumeran register
860 * @hw: pointer to the HW structure
861 * @offset: register offset to be read
862 * @data: pointer to the read data
863 * @locked: semaphore has already been acquired or not
865 * Acquires semaphore, if necessary. Then reads the PHY register at offset
866 * using the kumeran interface. The information retrieved is stored in data.
867 * Release any acquired semaphores before exiting.
869 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
874 DEBUGFUNC("__e1000_read_kmrn_reg");
877 s32 ret_val = E1000_SUCCESS;
879 if (!hw->phy.ops.acquire)
880 return E1000_SUCCESS;
882 ret_val = hw->phy.ops.acquire(hw);
887 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
888 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
889 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
890 E1000_WRITE_FLUSH(hw);
894 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
895 *data = (u16)kmrnctrlsta;
898 hw->phy.ops.release(hw);
900 return E1000_SUCCESS;
904 * e1000_read_kmrn_reg_generic - Read kumeran register
905 * @hw: pointer to the HW structure
906 * @offset: register offset to be read
907 * @data: pointer to the read data
909 * Acquires semaphore then reads the PHY register at offset using the
910 * kumeran interface. The information retrieved is stored in data.
911 * Release the acquired semaphore before exiting.
913 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
915 return __e1000_read_kmrn_reg(hw, offset, data, FALSE);
919 * e1000_read_kmrn_reg_locked - Read kumeran register
920 * @hw: pointer to the HW structure
921 * @offset: register offset to be read
922 * @data: pointer to the read data
924 * Reads the PHY register at offset using the kumeran interface. The
925 * information retrieved is stored in data.
926 * Assumes semaphore already acquired.
928 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
930 return __e1000_read_kmrn_reg(hw, offset, data, TRUE);
934 * __e1000_write_kmrn_reg - Write kumeran register
935 * @hw: pointer to the HW structure
936 * @offset: register offset to write to
937 * @data: data to write at register offset
938 * @locked: semaphore has already been acquired or not
940 * Acquires semaphore, if necessary. Then write the data to PHY register
941 * at the offset using the kumeran interface. Release any acquired semaphores
944 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
949 DEBUGFUNC("e1000_write_kmrn_reg_generic");
952 s32 ret_val = E1000_SUCCESS;
954 if (!hw->phy.ops.acquire)
955 return E1000_SUCCESS;
957 ret_val = hw->phy.ops.acquire(hw);
962 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
963 E1000_KMRNCTRLSTA_OFFSET) | data;
964 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
965 E1000_WRITE_FLUSH(hw);
970 hw->phy.ops.release(hw);
972 return E1000_SUCCESS;
976 * e1000_write_kmrn_reg_generic - Write kumeran register
977 * @hw: pointer to the HW structure
978 * @offset: register offset to write to
979 * @data: data to write at register offset
981 * Acquires semaphore then writes the data to the PHY register at the offset
982 * using the kumeran interface. Release the acquired semaphore before exiting.
984 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
986 return __e1000_write_kmrn_reg(hw, offset, data, FALSE);
990 * e1000_write_kmrn_reg_locked - Write kumeran register
991 * @hw: pointer to the HW structure
992 * @offset: register offset to write to
993 * @data: data to write at register offset
995 * Write the data to PHY register at the offset using the kumeran interface.
996 * Assumes semaphore already acquired.
998 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
1000 return __e1000_write_kmrn_reg(hw, offset, data, TRUE);
1004 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
1005 * @hw: pointer to the HW structure
1007 * Sets up Master/slave mode
1009 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
1014 /* Resolve Master/Slave mode */
1015 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1019 /* load defaults for future use */
1020 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1021 ((phy_data & CR_1000T_MS_VALUE) ?
1022 e1000_ms_force_master :
1023 e1000_ms_force_slave) : e1000_ms_auto;
1025 switch (hw->phy.ms_type) {
1026 case e1000_ms_force_master:
1027 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1029 case e1000_ms_force_slave:
1030 phy_data |= CR_1000T_MS_ENABLE;
1031 phy_data &= ~(CR_1000T_MS_VALUE);
1034 phy_data &= ~CR_1000T_MS_ENABLE;
1040 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1044 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
1045 * @hw: pointer to the HW structure
1047 * Sets up Carrier-sense on Transmit and downshift values.
1049 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
1054 DEBUGFUNC("e1000_copper_link_setup_82577");
1056 if (hw->phy.type == e1000_phy_82580) {
1057 ret_val = hw->phy.ops.reset(hw);
1059 DEBUGOUT("Error resetting the PHY.\n");
1064 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1065 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1069 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1071 /* Enable downshift */
1072 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1074 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1078 /* Set MDI/MDIX mode */
1079 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1082 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
1084 * 0 - Auto (default)
1088 switch (hw->phy.mdix) {
1092 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
1096 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
1099 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1103 return e1000_set_master_slave_mode(hw);
1107 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1108 * @hw: pointer to the HW structure
1110 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1111 * and downshift values are set also.
1113 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1115 struct e1000_phy_info *phy = &hw->phy;
1119 DEBUGFUNC("e1000_copper_link_setup_m88");
1122 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1123 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1127 /* For BM PHY this bit is downshift enable */
1128 if (phy->type != e1000_phy_bm)
1129 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1132 * MDI/MDI-X = 0 (default)
1133 * 0 - Auto for all speeds
1136 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1138 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1140 switch (phy->mdix) {
1142 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1145 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1148 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1152 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1157 * disable_polarity_correction = 0 (default)
1158 * Automatic Correction for Reversed Cable Polarity
1162 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1163 if (phy->disable_polarity_correction)
1164 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1166 /* Enable downshift on BM (disabled by default) */
1167 if (phy->type == e1000_phy_bm) {
1168 /* For 82574/82583, first disable then enable downshift */
1169 if (phy->id == BME1000_E_PHY_ID_R2) {
1170 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
1171 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1175 /* Commit the changes. */
1176 ret_val = phy->ops.commit(hw);
1178 DEBUGOUT("Error committing the PHY changes\n");
1183 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
1186 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1190 if ((phy->type == e1000_phy_m88) &&
1191 (phy->revision < E1000_REVISION_4) &&
1192 (phy->id != BME1000_E_PHY_ID_R2)) {
1193 /* Force TX_CLK in the Extended PHY Specific Control Register
1196 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1201 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1203 if ((phy->revision == E1000_REVISION_2) &&
1204 (phy->id == M88E1111_I_PHY_ID)) {
1205 /* 82573L PHY - set the downshift counter to 5x. */
1206 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1207 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1209 /* Configure Master and Slave downshift values */
1210 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1211 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1212 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1213 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1215 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1221 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1222 /* Set PHY page 0, register 29 to 0x0003 */
1223 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1227 /* Set PHY page 0, register 30 to 0x0000 */
1228 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1233 /* Commit the changes. */
1234 ret_val = phy->ops.commit(hw);
1236 DEBUGOUT("Error committing the PHY changes\n");
1240 if (phy->type == e1000_phy_82578) {
1241 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1246 /* 82578 PHY - set the downshift count to 1x. */
1247 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
1248 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
1249 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1255 return E1000_SUCCESS;
1259 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1260 * @hw: pointer to the HW structure
1262 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1263 * Also enables and sets the downshift parameters.
1265 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1267 struct e1000_phy_info *phy = &hw->phy;
1271 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1274 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1275 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1280 * MDI/MDI-X = 0 (default)
1281 * 0 - Auto for all speeds
1284 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1286 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1288 switch (phy->mdix) {
1290 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1293 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1296 /* M88E1112 does not support this mode) */
1297 if (phy->id != M88E1112_E_PHY_ID) {
1298 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1304 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1309 * disable_polarity_correction = 0 (default)
1310 * Automatic Correction for Reversed Cable Polarity
1314 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1315 if (phy->disable_polarity_correction)
1316 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1318 /* Enable downshift and setting it to X6 */
1319 if (phy->id == M88E1543_E_PHY_ID) {
1320 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
1322 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1326 ret_val = phy->ops.commit(hw);
1328 DEBUGOUT("Error committing the PHY changes\n");
1333 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1334 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1335 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1337 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1341 /* Commit the changes. */
1342 ret_val = phy->ops.commit(hw);
1344 DEBUGOUT("Error committing the PHY changes\n");
1348 ret_val = e1000_set_master_slave_mode(hw);
1352 return E1000_SUCCESS;
1356 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1357 * @hw: pointer to the HW structure
1359 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1362 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1364 struct e1000_phy_info *phy = &hw->phy;
1368 DEBUGFUNC("e1000_copper_link_setup_igp");
1371 ret_val = hw->phy.ops.reset(hw);
1373 DEBUGOUT("Error resetting the PHY.\n");
1377 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1378 * timeout issues when LFS is enabled.
1382 /* The NVM settings will configure LPLU in D3 for
1385 if (phy->type == e1000_phy_igp) {
1386 /* disable lplu d3 during driver init */
1387 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE);
1389 DEBUGOUT("Error Disabling LPLU D3\n");
1394 /* disable lplu d0 during driver init */
1395 if (hw->phy.ops.set_d0_lplu_state) {
1396 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE);
1398 DEBUGOUT("Error Disabling LPLU D0\n");
1402 /* Configure mdi-mdix settings */
1403 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1407 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1409 switch (phy->mdix) {
1411 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1414 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1418 data |= IGP01E1000_PSCR_AUTO_MDIX;
1421 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1425 /* set auto-master slave resolution settings */
1426 if (hw->mac.autoneg) {
1427 /* when autonegotiation advertisement is only 1000Mbps then we
1428 * should disable SmartSpeed and enable Auto MasterSlave
1429 * resolution as hardware default.
1431 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1432 /* Disable SmartSpeed */
1433 ret_val = phy->ops.read_reg(hw,
1434 IGP01E1000_PHY_PORT_CONFIG,
1439 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1440 ret_val = phy->ops.write_reg(hw,
1441 IGP01E1000_PHY_PORT_CONFIG,
1446 /* Set auto Master/Slave resolution process */
1447 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1451 data &= ~CR_1000T_MS_ENABLE;
1452 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1457 ret_val = e1000_set_master_slave_mode(hw);
1464 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1465 * @hw: pointer to the HW structure
1467 * Reads the MII auto-neg advertisement register and/or the 1000T control
1468 * register and if the PHY is already setup for auto-negotiation, then
1469 * return successful. Otherwise, setup advertisement and flow control to
1470 * the appropriate values for the wanted auto-negotiation.
1472 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1474 struct e1000_phy_info *phy = &hw->phy;
1476 u16 mii_autoneg_adv_reg;
1477 u16 mii_1000t_ctrl_reg = 0;
1479 DEBUGFUNC("e1000_phy_setup_autoneg");
1481 phy->autoneg_advertised &= phy->autoneg_mask;
1483 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1484 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1488 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1489 /* Read the MII 1000Base-T Control Register (Address 9). */
1490 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1491 &mii_1000t_ctrl_reg);
1496 /* Need to parse both autoneg_advertised and fc and set up
1497 * the appropriate PHY registers. First we will parse for
1498 * autoneg_advertised software override. Since we can advertise
1499 * a plethora of combinations, we need to check each bit
1503 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1504 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1505 * the 1000Base-T Control Register (Address 9).
1507 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1508 NWAY_AR_100TX_HD_CAPS |
1509 NWAY_AR_10T_FD_CAPS |
1510 NWAY_AR_10T_HD_CAPS);
1511 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1513 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1515 /* Do we want to advertise 10 Mb Half Duplex? */
1516 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1517 DEBUGOUT("Advertise 10mb Half duplex\n");
1518 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1521 /* Do we want to advertise 10 Mb Full Duplex? */
1522 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1523 DEBUGOUT("Advertise 10mb Full duplex\n");
1524 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1527 /* Do we want to advertise 100 Mb Half Duplex? */
1528 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1529 DEBUGOUT("Advertise 100mb Half duplex\n");
1530 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1533 /* Do we want to advertise 100 Mb Full Duplex? */
1534 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1535 DEBUGOUT("Advertise 100mb Full duplex\n");
1536 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1539 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1540 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1541 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1543 /* Do we want to advertise 1000 Mb Full Duplex? */
1544 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1545 DEBUGOUT("Advertise 1000mb Full duplex\n");
1546 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1549 /* Check for a software override of the flow control settings, and
1550 * setup the PHY advertisement registers accordingly. If
1551 * auto-negotiation is enabled, then software will have to set the
1552 * "PAUSE" bits to the correct value in the Auto-Negotiation
1553 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1556 * The possible values of the "fc" parameter are:
1557 * 0: Flow control is completely disabled
1558 * 1: Rx flow control is enabled (we can receive pause frames
1559 * but not send pause frames).
1560 * 2: Tx flow control is enabled (we can send pause frames
1561 * but we do not support receiving pause frames).
1562 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1563 * other: No software override. The flow control configuration
1564 * in the EEPROM is used.
1566 switch (hw->fc.current_mode) {
1568 /* Flow control (Rx & Tx) is completely disabled by a
1569 * software over-ride.
1571 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1573 case e1000_fc_rx_pause:
1574 /* Rx Flow control is enabled, and Tx Flow control is
1575 * disabled, by a software over-ride.
1577 * Since there really isn't a way to advertise that we are
1578 * capable of Rx Pause ONLY, we will advertise that we
1579 * support both symmetric and asymmetric Rx PAUSE. Later
1580 * (in e1000_config_fc_after_link_up) we will disable the
1581 * hw's ability to send PAUSE frames.
1583 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1585 case e1000_fc_tx_pause:
1586 /* Tx Flow control is enabled, and Rx Flow control is
1587 * disabled, by a software over-ride.
1589 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1590 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1593 /* Flow control (both Rx and Tx) is enabled by a software
1596 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1599 DEBUGOUT("Flow control param set incorrectly\n");
1600 return -E1000_ERR_CONFIG;
1603 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1607 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1609 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1610 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1611 mii_1000t_ctrl_reg);
1617 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1618 * @hw: pointer to the HW structure
1620 * Performs initial bounds checking on autoneg advertisement parameter, then
1621 * configure to advertise the full capability. Setup the PHY to autoneg
1622 * and restart the negotiation process between the link partner. If
1623 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1625 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1627 struct e1000_phy_info *phy = &hw->phy;
1631 DEBUGFUNC("e1000_copper_link_autoneg");
1633 /* Perform some bounds checking on the autoneg advertisement
1636 phy->autoneg_advertised &= phy->autoneg_mask;
1638 /* If autoneg_advertised is zero, we assume it was not defaulted
1639 * by the calling code so we set to advertise full capability.
1641 if (!phy->autoneg_advertised)
1642 phy->autoneg_advertised = phy->autoneg_mask;
1644 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1645 ret_val = e1000_phy_setup_autoneg(hw);
1647 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1650 DEBUGOUT("Restarting Auto-Neg\n");
1652 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1653 * the Auto Neg Restart bit in the PHY control register.
1655 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1659 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1660 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1664 /* Does the user want to wait for Auto-Neg to complete here, or
1665 * check at a later time (for example, callback routine).
1667 if (phy->autoneg_wait_to_complete) {
1668 ret_val = e1000_wait_autoneg(hw);
1670 DEBUGOUT("Error while waiting for autoneg to complete\n");
1675 hw->mac.get_link_status = TRUE;
1681 * e1000_setup_copper_link_generic - Configure copper link settings
1682 * @hw: pointer to the HW structure
1684 * Calls the appropriate function to configure the link for auto-neg or forced
1685 * speed and duplex. Then we check for link, once link is established calls
1686 * to configure collision distance and flow control are called. If link is
1687 * not established, we return -E1000_ERR_PHY (-2).
1689 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1694 DEBUGFUNC("e1000_setup_copper_link_generic");
1696 if (hw->mac.autoneg) {
1697 /* Setup autoneg and flow control advertisement and perform
1700 ret_val = e1000_copper_link_autoneg(hw);
1704 /* PHY will be set to 10H, 10F, 100H or 100F
1705 * depending on user settings.
1707 DEBUGOUT("Forcing Speed and Duplex\n");
1708 ret_val = hw->phy.ops.force_speed_duplex(hw);
1710 DEBUGOUT("Error Forcing Speed and Duplex\n");
1715 /* Check link status. Wait up to 100 microseconds for link to become
1718 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1724 DEBUGOUT("Valid link established!!!\n");
1725 hw->mac.ops.config_collision_dist(hw);
1726 ret_val = e1000_config_fc_after_link_up_generic(hw);
1728 DEBUGOUT("Unable to establish link!!!\n");
1735 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1736 * @hw: pointer to the HW structure
1738 * Calls the PHY setup function to force speed and duplex. Clears the
1739 * auto-crossover to force MDI manually. Waits for link and returns
1740 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1742 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1744 struct e1000_phy_info *phy = &hw->phy;
1749 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1751 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1755 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1757 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1761 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1762 * forced whenever speed and duplex are forced.
1764 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1768 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1769 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1771 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1775 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1779 if (phy->autoneg_wait_to_complete) {
1780 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1782 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1788 DEBUGOUT("Link taking longer than expected.\n");
1791 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1799 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1800 * @hw: pointer to the HW structure
1802 * Calls the PHY setup function to force speed and duplex. Clears the
1803 * auto-crossover to force MDI manually. Resets the PHY to commit the
1804 * changes. If time expires while waiting for link up, we reset the DSP.
1805 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1806 * successful completion, else return corresponding error code.
1808 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1810 struct e1000_phy_info *phy = &hw->phy;
1815 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1817 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1818 if (phy->type != e1000_phy_i210) {
1819 /* Clear Auto-Crossover to force MDI manually. M88E1000
1820 * requires MDI forced whenever speed and duplex are forced.
1822 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1827 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1828 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1833 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1836 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1840 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1842 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1846 /* Reset the phy to commit changes. */
1847 ret_val = hw->phy.ops.commit(hw);
1851 if (phy->autoneg_wait_to_complete) {
1852 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1854 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1860 bool reset_dsp = TRUE;
1862 switch (hw->phy.id) {
1863 case I347AT4_E_PHY_ID:
1864 case M88E1340M_E_PHY_ID:
1865 case M88E1112_E_PHY_ID:
1866 case M88E1543_E_PHY_ID:
1867 case M88E1512_E_PHY_ID:
1872 if (hw->phy.type != e1000_phy_m88)
1878 DEBUGOUT("Link taking longer than expected.\n");
1880 /* We didn't get link.
1881 * Reset the DSP and cross our fingers.
1883 ret_val = phy->ops.write_reg(hw,
1884 M88E1000_PHY_PAGE_SELECT,
1888 ret_val = e1000_phy_reset_dsp_generic(hw);
1895 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1901 if (hw->phy.type != e1000_phy_m88)
1902 return E1000_SUCCESS;
1904 if (hw->phy.id == I347AT4_E_PHY_ID ||
1905 hw->phy.id == M88E1340M_E_PHY_ID ||
1906 hw->phy.id == M88E1112_E_PHY_ID)
1907 return E1000_SUCCESS;
1908 if (hw->phy.id == I210_I_PHY_ID)
1909 return E1000_SUCCESS;
1910 if ((hw->phy.id == M88E1543_E_PHY_ID) ||
1911 (hw->phy.id == M88E1512_E_PHY_ID))
1912 return E1000_SUCCESS;
1913 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1917 /* Resetting the phy means we need to re-force TX_CLK in the
1918 * Extended PHY Specific Control Register to 25MHz clock from
1919 * the reset value of 2.5MHz.
1921 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1922 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1926 /* In addition, we must re-enable CRS on Tx for both half and full
1929 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1933 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1934 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1940 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1941 * @hw: pointer to the HW structure
1943 * Forces the speed and duplex settings of the PHY.
1944 * This is a function pointer entry point only called by
1945 * PHY setup routines.
1947 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1949 struct e1000_phy_info *phy = &hw->phy;
1954 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1956 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1960 e1000_phy_force_speed_duplex_setup(hw, &data);
1962 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1966 /* Disable MDI-X support for 10/100 */
1967 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1971 data &= ~IFE_PMC_AUTO_MDIX;
1972 data &= ~IFE_PMC_FORCE_MDIX;
1974 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1978 DEBUGOUT1("IFE PMC: %X\n", data);
1982 if (phy->autoneg_wait_to_complete) {
1983 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1985 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1991 DEBUGOUT("Link taking longer than expected.\n");
1994 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
2000 return E1000_SUCCESS;
2004 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
2005 * @hw: pointer to the HW structure
2006 * @phy_ctrl: pointer to current value of PHY_CONTROL
2008 * Forces speed and duplex on the PHY by doing the following: disable flow
2009 * control, force speed/duplex on the MAC, disable auto speed detection,
2010 * disable auto-negotiation, configure duplex, configure speed, configure
2011 * the collision distance, write configuration to CTRL register. The
2012 * caller must write to the PHY_CONTROL register for these settings to
2015 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
2017 struct e1000_mac_info *mac = &hw->mac;
2020 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
2022 /* Turn off flow control when forcing speed/duplex */
2023 hw->fc.current_mode = e1000_fc_none;
2025 /* Force speed/duplex on the mac */
2026 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2027 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2028 ctrl &= ~E1000_CTRL_SPD_SEL;
2030 /* Disable Auto Speed Detection */
2031 ctrl &= ~E1000_CTRL_ASDE;
2033 /* Disable autoneg on the phy */
2034 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
2036 /* Forcing Full or Half Duplex? */
2037 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
2038 ctrl &= ~E1000_CTRL_FD;
2039 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
2040 DEBUGOUT("Half Duplex\n");
2042 ctrl |= E1000_CTRL_FD;
2043 *phy_ctrl |= MII_CR_FULL_DUPLEX;
2044 DEBUGOUT("Full Duplex\n");
2047 /* Forcing 10mb or 100mb? */
2048 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
2049 ctrl |= E1000_CTRL_SPD_100;
2050 *phy_ctrl |= MII_CR_SPEED_100;
2051 *phy_ctrl &= ~MII_CR_SPEED_1000;
2052 DEBUGOUT("Forcing 100mb\n");
2054 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2055 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2056 DEBUGOUT("Forcing 10mb\n");
2059 hw->mac.ops.config_collision_dist(hw);
2061 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2065 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
2066 * @hw: pointer to the HW structure
2067 * @active: boolean used to enable/disable lplu
2069 * Success returns 0, Failure returns 1
2071 * The low power link up (lplu) state is set to the power management level D3
2072 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
2073 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2074 * is used during Dx states where the power conservation is most important.
2075 * During driver activity, SmartSpeed should be enabled so performance is
2078 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
2080 struct e1000_phy_info *phy = &hw->phy;
2084 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
2086 if (!hw->phy.ops.read_reg)
2087 return E1000_SUCCESS;
2089 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2094 data &= ~IGP02E1000_PM_D3_LPLU;
2095 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2099 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2100 * during Dx states where the power conservation is most
2101 * important. During driver activity we should enable
2102 * SmartSpeed, so performance is maintained.
2104 if (phy->smart_speed == e1000_smart_speed_on) {
2105 ret_val = phy->ops.read_reg(hw,
2106 IGP01E1000_PHY_PORT_CONFIG,
2111 data |= IGP01E1000_PSCFR_SMART_SPEED;
2112 ret_val = phy->ops.write_reg(hw,
2113 IGP01E1000_PHY_PORT_CONFIG,
2117 } else if (phy->smart_speed == e1000_smart_speed_off) {
2118 ret_val = phy->ops.read_reg(hw,
2119 IGP01E1000_PHY_PORT_CONFIG,
2124 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2125 ret_val = phy->ops.write_reg(hw,
2126 IGP01E1000_PHY_PORT_CONFIG,
2131 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2132 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2133 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2134 data |= IGP02E1000_PM_D3_LPLU;
2135 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2140 /* When LPLU is enabled, we should disable SmartSpeed */
2141 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2146 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2147 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2155 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
2156 * @hw: pointer to the HW structure
2158 * Success returns 0, Failure returns 1
2160 * A downshift is detected by querying the PHY link health.
2162 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
2164 struct e1000_phy_info *phy = &hw->phy;
2166 u16 phy_data, offset, mask;
2168 DEBUGFUNC("e1000_check_downshift_generic");
2170 switch (phy->type) {
2171 case e1000_phy_i210:
2173 case e1000_phy_gg82563:
2175 case e1000_phy_82578:
2176 offset = M88E1000_PHY_SPEC_STATUS;
2177 mask = M88E1000_PSSR_DOWNSHIFT;
2180 case e1000_phy_igp_2:
2181 case e1000_phy_igp_3:
2182 offset = IGP01E1000_PHY_LINK_HEALTH;
2183 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
2186 /* speed downshift not supported */
2187 phy->speed_downgraded = FALSE;
2188 return E1000_SUCCESS;
2191 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2194 phy->speed_downgraded = !!(phy_data & mask);
2200 * e1000_check_polarity_m88 - Checks the polarity.
2201 * @hw: pointer to the HW structure
2203 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2205 * Polarity is determined based on the PHY specific status register.
2207 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2209 struct e1000_phy_info *phy = &hw->phy;
2213 DEBUGFUNC("e1000_check_polarity_m88");
2215 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2218 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
2219 ? e1000_rev_polarity_reversed
2220 : e1000_rev_polarity_normal);
2226 * e1000_check_polarity_igp - Checks the polarity.
2227 * @hw: pointer to the HW structure
2229 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2231 * Polarity is determined based on the PHY port status register, and the
2232 * current speed (since there is no polarity at 100Mbps).
2234 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2236 struct e1000_phy_info *phy = &hw->phy;
2238 u16 data, offset, mask;
2240 DEBUGFUNC("e1000_check_polarity_igp");
2242 /* Polarity is determined based on the speed of
2245 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2249 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2250 IGP01E1000_PSSR_SPEED_1000MBPS) {
2251 offset = IGP01E1000_PHY_PCS_INIT_REG;
2252 mask = IGP01E1000_PHY_POLARITY_MASK;
2254 /* This really only applies to 10Mbps since
2255 * there is no polarity for 100Mbps (always 0).
2257 offset = IGP01E1000_PHY_PORT_STATUS;
2258 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
2261 ret_val = phy->ops.read_reg(hw, offset, &data);
2264 phy->cable_polarity = ((data & mask)
2265 ? e1000_rev_polarity_reversed
2266 : e1000_rev_polarity_normal);
2272 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2273 * @hw: pointer to the HW structure
2275 * Polarity is determined on the polarity reversal feature being enabled.
2277 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2279 struct e1000_phy_info *phy = &hw->phy;
2281 u16 phy_data, offset, mask;
2283 DEBUGFUNC("e1000_check_polarity_ife");
2285 /* Polarity is determined based on the reversal feature being enabled.
2287 if (phy->polarity_correction) {
2288 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2289 mask = IFE_PESC_POLARITY_REVERSED;
2291 offset = IFE_PHY_SPECIAL_CONTROL;
2292 mask = IFE_PSC_FORCE_POLARITY;
2295 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2298 phy->cable_polarity = ((phy_data & mask)
2299 ? e1000_rev_polarity_reversed
2300 : e1000_rev_polarity_normal);
2306 * e1000_wait_autoneg - Wait for auto-neg completion
2307 * @hw: pointer to the HW structure
2309 * Waits for auto-negotiation to complete or for the auto-negotiation time
2310 * limit to expire, which ever happens first.
2312 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2314 s32 ret_val = E1000_SUCCESS;
2317 DEBUGFUNC("e1000_wait_autoneg");
2319 if (!hw->phy.ops.read_reg)
2320 return E1000_SUCCESS;
2322 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2323 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2324 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2327 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2330 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2335 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2342 * e1000_phy_has_link_generic - Polls PHY for link
2343 * @hw: pointer to the HW structure
2344 * @iterations: number of times to poll for link
2345 * @usec_interval: delay between polling attempts
2346 * @success: pointer to whether polling was successful or not
2348 * Polls the PHY status register for link, 'iterations' number of times.
2350 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2351 u32 usec_interval, bool *success)
2353 s32 ret_val = E1000_SUCCESS;
2356 DEBUGFUNC("e1000_phy_has_link_generic");
2358 if (!hw->phy.ops.read_reg)
2359 return E1000_SUCCESS;
2361 for (i = 0; i < iterations; i++) {
2362 /* Some PHYs require the PHY_STATUS register to be read
2363 * twice due to the link bit being sticky. No harm doing
2364 * it across the board.
2366 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2368 /* If the first read fails, another entity may have
2369 * ownership of the resources, wait and try again to
2370 * see if they have relinquished the resources yet.
2372 if (usec_interval >= 1000)
2373 msec_delay(usec_interval/1000);
2375 usec_delay(usec_interval);
2377 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2380 if (phy_status & MII_SR_LINK_STATUS)
2382 if (usec_interval >= 1000)
2383 msec_delay(usec_interval/1000);
2385 usec_delay(usec_interval);
2388 *success = (i < iterations);
2394 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2395 * @hw: pointer to the HW structure
2397 * Reads the PHY specific status register to retrieve the cable length
2398 * information. The cable length is determined by averaging the minimum and
2399 * maximum values to get the "average" cable length. The m88 PHY has four
2400 * possible cable length values, which are:
2401 * Register Value Cable Length
2405 * 3 110 - 140 meters
2408 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2410 struct e1000_phy_info *phy = &hw->phy;
2412 u16 phy_data, index;
2414 DEBUGFUNC("e1000_get_cable_length_m88");
2416 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2420 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2421 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2423 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2424 return -E1000_ERR_PHY;
2426 phy->min_cable_length = e1000_m88_cable_length_table[index];
2427 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2429 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2431 return E1000_SUCCESS;
2434 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2436 struct e1000_phy_info *phy = &hw->phy;
2438 u16 phy_data, phy_data2, is_cm;
2439 u16 index, default_page;
2441 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2443 switch (hw->phy.id) {
2445 /* Get cable length from PHY Cable Diagnostics Control Reg */
2446 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2447 (I347AT4_PCDL + phy->addr),
2452 /* Check if the unit of cable length is meters or cm */
2453 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2454 I347AT4_PCDC, &phy_data2);
2458 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2460 /* Populate the phy structure with cable length in meters */
2461 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2462 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2463 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2465 case M88E1543_E_PHY_ID:
2466 case M88E1512_E_PHY_ID:
2467 case M88E1340M_E_PHY_ID:
2468 case I347AT4_E_PHY_ID:
2469 /* Remember the original page select and set it to 7 */
2470 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2475 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2479 /* Get cable length from PHY Cable Diagnostics Control Reg */
2480 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2485 /* Check if the unit of cable length is meters or cm */
2486 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2490 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2492 /* Populate the phy structure with cable length in meters */
2493 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2494 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2495 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2497 /* Reset the page select to its original value */
2498 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2504 case M88E1112_E_PHY_ID:
2505 /* Remember the original page select and set it to 5 */
2506 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2511 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2515 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2520 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2521 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2523 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2524 return -E1000_ERR_PHY;
2526 phy->min_cable_length = e1000_m88_cable_length_table[index];
2527 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2529 phy->cable_length = (phy->min_cable_length +
2530 phy->max_cable_length) / 2;
2532 /* Reset the page select to its original value */
2533 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2540 return -E1000_ERR_PHY;
2547 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2548 * @hw: pointer to the HW structure
2550 * The automatic gain control (agc) normalizes the amplitude of the
2551 * received signal, adjusting for the attenuation produced by the
2552 * cable. By reading the AGC registers, which represent the
2553 * combination of coarse and fine gain value, the value can be put
2554 * into a lookup table to obtain the approximate cable length
2557 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2559 struct e1000_phy_info *phy = &hw->phy;
2561 u16 phy_data, i, agc_value = 0;
2562 u16 cur_agc_index, max_agc_index = 0;
2563 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2564 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2565 IGP02E1000_PHY_AGC_A,
2566 IGP02E1000_PHY_AGC_B,
2567 IGP02E1000_PHY_AGC_C,
2568 IGP02E1000_PHY_AGC_D
2571 DEBUGFUNC("e1000_get_cable_length_igp_2");
2573 /* Read the AGC registers for all channels */
2574 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2575 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2579 /* Getting bits 15:9, which represent the combination of
2580 * coarse and fine gain values. The result is a number
2581 * that can be put into the lookup table to obtain the
2582 * approximate cable length.
2584 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2585 IGP02E1000_AGC_LENGTH_MASK);
2587 /* Array index bound check. */
2588 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2589 (cur_agc_index == 0))
2590 return -E1000_ERR_PHY;
2592 /* Remove min & max AGC values from calculation. */
2593 if (e1000_igp_2_cable_length_table[min_agc_index] >
2594 e1000_igp_2_cable_length_table[cur_agc_index])
2595 min_agc_index = cur_agc_index;
2596 if (e1000_igp_2_cable_length_table[max_agc_index] <
2597 e1000_igp_2_cable_length_table[cur_agc_index])
2598 max_agc_index = cur_agc_index;
2600 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2603 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2604 e1000_igp_2_cable_length_table[max_agc_index]);
2605 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2607 /* Calculate cable length with the error range of +/- 10 meters. */
2608 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2609 (agc_value - IGP02E1000_AGC_RANGE) : 0);
2610 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2612 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2614 return E1000_SUCCESS;
2618 * e1000_get_phy_info_m88 - Retrieve PHY information
2619 * @hw: pointer to the HW structure
2621 * Valid for only copper links. Read the PHY status register (sticky read)
2622 * to verify that link is up. Read the PHY special control register to
2623 * determine the polarity and 10base-T extended distance. Read the PHY
2624 * special status register to determine MDI/MDIx and current speed. If
2625 * speed is 1000, then determine cable length, local and remote receiver.
2627 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2629 struct e1000_phy_info *phy = &hw->phy;
2634 DEBUGFUNC("e1000_get_phy_info_m88");
2636 if (phy->media_type != e1000_media_type_copper) {
2637 DEBUGOUT("Phy info is only valid for copper media\n");
2638 return -E1000_ERR_CONFIG;
2641 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2646 DEBUGOUT("Phy info is only valid if link is up\n");
2647 return -E1000_ERR_CONFIG;
2650 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2654 phy->polarity_correction = !!(phy_data &
2655 M88E1000_PSCR_POLARITY_REVERSAL);
2657 ret_val = e1000_check_polarity_m88(hw);
2661 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2665 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2667 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2668 ret_val = hw->phy.ops.get_cable_length(hw);
2672 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2676 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2677 ? e1000_1000t_rx_status_ok
2678 : e1000_1000t_rx_status_not_ok;
2680 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2681 ? e1000_1000t_rx_status_ok
2682 : e1000_1000t_rx_status_not_ok;
2684 /* Set values to "undefined" */
2685 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2686 phy->local_rx = e1000_1000t_rx_status_undefined;
2687 phy->remote_rx = e1000_1000t_rx_status_undefined;
2694 * e1000_get_phy_info_igp - Retrieve igp PHY information
2695 * @hw: pointer to the HW structure
2697 * Read PHY status to determine if link is up. If link is up, then
2698 * set/determine 10base-T extended distance and polarity correction. Read
2699 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2700 * determine on the cable length, local and remote receiver.
2702 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2704 struct e1000_phy_info *phy = &hw->phy;
2709 DEBUGFUNC("e1000_get_phy_info_igp");
2711 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2716 DEBUGOUT("Phy info is only valid if link is up\n");
2717 return -E1000_ERR_CONFIG;
2720 phy->polarity_correction = TRUE;
2722 ret_val = e1000_check_polarity_igp(hw);
2726 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2730 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2732 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2733 IGP01E1000_PSSR_SPEED_1000MBPS) {
2734 ret_val = phy->ops.get_cable_length(hw);
2738 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2742 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2743 ? e1000_1000t_rx_status_ok
2744 : e1000_1000t_rx_status_not_ok;
2746 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2747 ? e1000_1000t_rx_status_ok
2748 : e1000_1000t_rx_status_not_ok;
2750 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2751 phy->local_rx = e1000_1000t_rx_status_undefined;
2752 phy->remote_rx = e1000_1000t_rx_status_undefined;
2759 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2760 * @hw: pointer to the HW structure
2762 * Populates "phy" structure with various feature states.
2764 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2766 struct e1000_phy_info *phy = &hw->phy;
2771 DEBUGFUNC("e1000_get_phy_info_ife");
2773 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2778 DEBUGOUT("Phy info is only valid if link is up\n");
2779 return -E1000_ERR_CONFIG;
2782 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2785 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2787 if (phy->polarity_correction) {
2788 ret_val = e1000_check_polarity_ife(hw);
2792 /* Polarity is forced */
2793 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2794 ? e1000_rev_polarity_reversed
2795 : e1000_rev_polarity_normal);
2798 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2802 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2804 /* The following parameters are undefined for 10/100 operation. */
2805 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2806 phy->local_rx = e1000_1000t_rx_status_undefined;
2807 phy->remote_rx = e1000_1000t_rx_status_undefined;
2809 return E1000_SUCCESS;
2813 * e1000_phy_sw_reset_generic - PHY software reset
2814 * @hw: pointer to the HW structure
2816 * Does a software reset of the PHY by reading the PHY control register and
2817 * setting/write the control register reset bit to the PHY.
2819 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2824 DEBUGFUNC("e1000_phy_sw_reset_generic");
2826 if (!hw->phy.ops.read_reg)
2827 return E1000_SUCCESS;
2829 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2833 phy_ctrl |= MII_CR_RESET;
2834 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2844 * e1000_phy_hw_reset_generic - PHY hardware reset
2845 * @hw: pointer to the HW structure
2847 * Verify the reset block is not blocking us from resetting. Acquire
2848 * semaphore (if necessary) and read/set/write the device control reset
2849 * bit in the PHY. Wait the appropriate delay time for the device to
2850 * reset and release the semaphore (if necessary).
2852 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2854 struct e1000_phy_info *phy = &hw->phy;
2858 DEBUGFUNC("e1000_phy_hw_reset_generic");
2860 if (phy->ops.check_reset_block) {
2861 ret_val = phy->ops.check_reset_block(hw);
2863 return E1000_SUCCESS;
2866 ret_val = phy->ops.acquire(hw);
2870 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2871 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2872 E1000_WRITE_FLUSH(hw);
2874 usec_delay(phy->reset_delay_us);
2876 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2877 E1000_WRITE_FLUSH(hw);
2881 phy->ops.release(hw);
2883 return phy->ops.get_cfg_done(hw);
2887 * e1000_get_cfg_done_generic - Generic configuration done
2888 * @hw: pointer to the HW structure
2890 * Generic function to wait 10 milli-seconds for configuration to complete
2891 * and return success.
2893 s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2895 DEBUGFUNC("e1000_get_cfg_done_generic");
2899 return E1000_SUCCESS;
2903 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2904 * @hw: pointer to the HW structure
2906 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2908 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2910 DEBUGOUT("Running IGP 3 PHY init script\n");
2912 /* PHY init IGP 3 */
2913 /* Enable rise/fall, 10-mode work in class-A */
2914 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2915 /* Remove all caps from Replica path filter */
2916 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2917 /* Bias trimming for ADC, AFE and Driver (Default) */
2918 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2919 /* Increase Hybrid poly bias */
2920 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2921 /* Add 4% to Tx amplitude in Gig mode */
2922 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2923 /* Disable trimming (TTT) */
2924 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2925 /* Poly DC correction to 94.6% + 2% for all channels */
2926 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2927 /* ABS DC correction to 95.9% */
2928 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2929 /* BG temp curve trim */
2930 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2931 /* Increasing ADC OPAMP stage 1 currents to max */
2932 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2933 /* Force 1000 ( required for enabling PHY regs configuration) */
2934 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2935 /* Set upd_freq to 6 */
2936 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2938 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2939 /* Disable adaptive fixed FFE (Default) */
2940 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2941 /* Enable FFE hysteresis */
2942 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2943 /* Fixed FFE for short cable lengths */
2944 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2945 /* Fixed FFE for medium cable lengths */
2946 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2947 /* Fixed FFE for long cable lengths */
2948 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2949 /* Enable Adaptive Clip Threshold */
2950 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2951 /* AHT reset limit to 1 */
2952 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2953 /* Set AHT master delay to 127 msec */
2954 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2955 /* Set scan bits for AHT */
2956 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2957 /* Set AHT Preset bits */
2958 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2959 /* Change integ_factor of channel A to 3 */
2960 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2961 /* Change prop_factor of channels BCD to 8 */
2962 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2963 /* Change cg_icount + enable integbp for channels BCD */
2964 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2965 /* Change cg_icount + enable integbp + change prop_factor_master
2966 * to 8 for channel A
2968 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2969 /* Disable AHT in Slave mode on channel A */
2970 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2971 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2974 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2975 /* Enable restart AN on an1000_dis change */
2976 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2977 /* Enable wh_fifo read clock in 10/100 modes */
2978 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2979 /* Restart AN, Speed selection is 1000 */
2980 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2982 return E1000_SUCCESS;
2986 * e1000_get_phy_type_from_id - Get PHY type from id
2987 * @phy_id: phy_id read from the phy
2989 * Returns the phy type from the id.
2991 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2993 enum e1000_phy_type phy_type = e1000_phy_unknown;
2996 case M88E1000_I_PHY_ID:
2997 case M88E1000_E_PHY_ID:
2998 case M88E1111_I_PHY_ID:
2999 case M88E1011_I_PHY_ID:
3000 case M88E1543_E_PHY_ID:
3001 case M88E1512_E_PHY_ID:
3002 case I347AT4_E_PHY_ID:
3003 case M88E1112_E_PHY_ID:
3004 case M88E1340M_E_PHY_ID:
3005 phy_type = e1000_phy_m88;
3007 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
3008 phy_type = e1000_phy_igp_2;
3010 case GG82563_E_PHY_ID:
3011 phy_type = e1000_phy_gg82563;
3013 case IGP03E1000_E_PHY_ID:
3014 phy_type = e1000_phy_igp_3;
3017 case IFE_PLUS_E_PHY_ID:
3018 case IFE_C_E_PHY_ID:
3019 phy_type = e1000_phy_ife;
3021 case BME1000_E_PHY_ID:
3022 case BME1000_E_PHY_ID_R2:
3023 phy_type = e1000_phy_bm;
3025 case I82578_E_PHY_ID:
3026 phy_type = e1000_phy_82578;
3028 case I82577_E_PHY_ID:
3029 phy_type = e1000_phy_82577;
3031 case I82579_E_PHY_ID:
3032 phy_type = e1000_phy_82579;
3035 phy_type = e1000_phy_i217;
3037 case I82580_I_PHY_ID:
3038 phy_type = e1000_phy_82580;
3041 phy_type = e1000_phy_i210;
3044 phy_type = e1000_phy_unknown;
3051 * e1000_determine_phy_address - Determines PHY address.
3052 * @hw: pointer to the HW structure
3054 * This uses a trial and error method to loop through possible PHY
3055 * addresses. It tests each by reading the PHY ID registers and
3056 * checking for a match.
3058 s32 e1000_determine_phy_address(struct e1000_hw *hw)
3062 enum e1000_phy_type phy_type = e1000_phy_unknown;
3064 hw->phy.id = phy_type;
3066 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
3067 hw->phy.addr = phy_addr;
3071 e1000_get_phy_id(hw);
3072 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3074 /* If phy_type is valid, break - we found our
3077 if (phy_type != e1000_phy_unknown)
3078 return E1000_SUCCESS;
3085 return -E1000_ERR_PHY_TYPE;
3089 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
3090 * @page: page to access
3092 * Returns the phy address for the page requested.
3094 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
3098 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
3105 * e1000_write_phy_reg_bm - Write BM PHY register
3106 * @hw: pointer to the HW structure
3107 * @offset: register offset to write to
3108 * @data: data to write at register offset
3110 * Acquires semaphore, if necessary, then writes the data to PHY register
3111 * at the offset. Release any acquired semaphores before exiting.
3113 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
3116 u32 page = offset >> IGP_PAGE_SHIFT;
3118 DEBUGFUNC("e1000_write_phy_reg_bm");
3120 ret_val = hw->phy.ops.acquire(hw);
3124 /* Page 800 works differently than the rest so it has its own func */
3125 if (page == BM_WUC_PAGE) {
3126 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3131 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3133 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3134 u32 page_shift, page_select;
3136 /* Page select is register 31 for phy address 1 and 22 for
3137 * phy address 2 and 3. Page select is shifted only for
3140 if (hw->phy.addr == 1) {
3141 page_shift = IGP_PAGE_SHIFT;
3142 page_select = IGP01E1000_PHY_PAGE_SELECT;
3145 page_select = BM_PHY_PAGE_SELECT;
3148 /* Page is shifted left, PHY expects (page x 32) */
3149 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3150 (page << page_shift));
3155 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3159 hw->phy.ops.release(hw);
3164 * e1000_read_phy_reg_bm - Read BM PHY register
3165 * @hw: pointer to the HW structure
3166 * @offset: register offset to be read
3167 * @data: pointer to the read data
3169 * Acquires semaphore, if necessary, then reads the PHY register at offset
3170 * and storing the retrieved information in data. Release any acquired
3171 * semaphores before exiting.
3173 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
3176 u32 page = offset >> IGP_PAGE_SHIFT;
3178 DEBUGFUNC("e1000_read_phy_reg_bm");
3180 ret_val = hw->phy.ops.acquire(hw);
3184 /* Page 800 works differently than the rest so it has its own func */
3185 if (page == BM_WUC_PAGE) {
3186 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3191 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3193 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3194 u32 page_shift, page_select;
3196 /* Page select is register 31 for phy address 1 and 22 for
3197 * phy address 2 and 3. Page select is shifted only for
3200 if (hw->phy.addr == 1) {
3201 page_shift = IGP_PAGE_SHIFT;
3202 page_select = IGP01E1000_PHY_PAGE_SELECT;
3205 page_select = BM_PHY_PAGE_SELECT;
3208 /* Page is shifted left, PHY expects (page x 32) */
3209 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3210 (page << page_shift));
3215 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3218 hw->phy.ops.release(hw);
3223 * e1000_read_phy_reg_bm2 - Read BM PHY register
3224 * @hw: pointer to the HW structure
3225 * @offset: register offset to be read
3226 * @data: pointer to the read data
3228 * Acquires semaphore, if necessary, then reads the PHY register at offset
3229 * and storing the retrieved information in data. Release any acquired
3230 * semaphores before exiting.
3232 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
3235 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3237 DEBUGFUNC("e1000_read_phy_reg_bm2");
3239 ret_val = hw->phy.ops.acquire(hw);
3243 /* Page 800 works differently than the rest so it has its own func */
3244 if (page == BM_WUC_PAGE) {
3245 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3252 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3253 /* Page is shifted left, PHY expects (page x 32) */
3254 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3261 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3264 hw->phy.ops.release(hw);
3269 * e1000_write_phy_reg_bm2 - Write BM PHY register
3270 * @hw: pointer to the HW structure
3271 * @offset: register offset to write to
3272 * @data: data to write at register offset
3274 * Acquires semaphore, if necessary, then writes the data to PHY register
3275 * at the offset. Release any acquired semaphores before exiting.
3277 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
3280 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3282 DEBUGFUNC("e1000_write_phy_reg_bm2");
3284 ret_val = hw->phy.ops.acquire(hw);
3288 /* Page 800 works differently than the rest so it has its own func */
3289 if (page == BM_WUC_PAGE) {
3290 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3297 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3298 /* Page is shifted left, PHY expects (page x 32) */
3299 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3306 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3310 hw->phy.ops.release(hw);
3315 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
3316 * @hw: pointer to the HW structure
3317 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
3319 * Assumes semaphore already acquired and phy_reg points to a valid memory
3320 * address to store contents of the BM_WUC_ENABLE_REG register.
3322 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3327 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm");
3330 return -E1000_ERR_PARAM;
3332 /* All page select, port ctrl and wakeup registers use phy address 1 */
3335 /* Select Port Control Registers page */
3336 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3338 DEBUGOUT("Could not set Port Control page\n");
3342 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3344 DEBUGOUT2("Could not read PHY register %d.%d\n",
3345 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3349 /* Enable both PHY wakeup mode and Wakeup register page writes.
3350 * Prevent a power state change by disabling ME and Host PHY wakeup.
3353 temp |= BM_WUC_ENABLE_BIT;
3354 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
3356 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3358 DEBUGOUT2("Could not write PHY register %d.%d\n",
3359 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3363 /* Select Host Wakeup Registers page - caller now able to write
3364 * registers on the Wakeup registers page
3366 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3370 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
3371 * @hw: pointer to the HW structure
3372 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
3374 * Restore BM_WUC_ENABLE_REG to its original value.
3376 * Assumes semaphore already acquired and *phy_reg is the contents of the
3377 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
3380 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3384 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm");
3387 return -E1000_ERR_PARAM;
3389 /* Select Port Control Registers page */
3390 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3392 DEBUGOUT("Could not set Port Control page\n");
3396 /* Restore 769.17 to its original value */
3397 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3399 DEBUGOUT2("Could not restore PHY register %d.%d\n",
3400 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3406 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
3407 * @hw: pointer to the HW structure
3408 * @offset: register offset to be read or written
3409 * @data: pointer to the data to read or write
3410 * @read: determines if operation is read or write
3411 * @page_set: BM_WUC_PAGE already set and access enabled
3413 * Read the PHY register at offset and store the retrieved information in
3414 * data, or write data to PHY register at offset. Note the procedure to
3415 * access the PHY wakeup registers is different than reading the other PHY
3416 * registers. It works as such:
3417 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
3418 * 2) Set page to 800 for host (801 if we were manageability)
3419 * 3) Write the address using the address opcode (0x11)
3420 * 4) Read or write the data using the data opcode (0x12)
3421 * 5) Restore 769.17.2 to its original value
3423 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
3424 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
3426 * Assumes semaphore is already acquired. When page_set==TRUE, assumes
3427 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
3428 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
3430 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
3431 u16 *data, bool read, bool page_set)
3434 u16 reg = BM_PHY_REG_NUM(offset);
3435 u16 page = BM_PHY_REG_PAGE(offset);
3438 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
3440 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
3441 if ((hw->mac.type == e1000_pchlan) &&
3442 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
3443 DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
3447 /* Enable access to PHY wakeup registers */
3448 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3450 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3455 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3457 /* Write the Wakeup register page offset value using opcode 0x11 */
3458 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3460 DEBUGOUT1("Could not write address opcode to page %d\n", page);
3465 /* Read the Wakeup register page value using opcode 0x12 */
3466 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3469 /* Write the Wakeup register page value using opcode 0x12 */
3470 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3475 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3480 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3486 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3487 * @hw: pointer to the HW structure
3489 * In the case of a PHY power down to save power, or to turn off link during a
3490 * driver unload, or wake on lan is not enabled, restore the link to previous
3493 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3497 /* The PHY will retain its settings across a power down/up cycle */
3498 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3499 mii_reg &= ~MII_CR_POWER_DOWN;
3500 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3504 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3505 * @hw: pointer to the HW structure
3507 * In the case of a PHY power down to save power, or to turn off link during a
3508 * driver unload, or wake on lan is not enabled, restore the link to previous
3511 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3515 /* The PHY will retain its settings across a power down/up cycle */
3516 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3517 mii_reg |= MII_CR_POWER_DOWN;
3518 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3523 * __e1000_read_phy_reg_hv - Read HV PHY register
3524 * @hw: pointer to the HW structure
3525 * @offset: register offset to be read
3526 * @data: pointer to the read data
3527 * @locked: semaphore has already been acquired or not
3529 * Acquires semaphore, if necessary, then reads the PHY register at offset
3530 * and stores the retrieved information in data. Release any acquired
3531 * semaphore before exiting.
3533 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3534 bool locked, bool page_set)
3537 u16 page = BM_PHY_REG_PAGE(offset);
3538 u16 reg = BM_PHY_REG_NUM(offset);
3539 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3541 DEBUGFUNC("__e1000_read_phy_reg_hv");
3544 ret_val = hw->phy.ops.acquire(hw);
3548 /* Page 800 works differently than the rest so it has its own func */
3549 if (page == BM_WUC_PAGE) {
3550 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3555 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3556 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3562 if (page == HV_INTC_FC_PAGE_START)
3565 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3566 /* Page is shifted left, PHY expects (page x 32) */
3567 ret_val = e1000_set_page_igp(hw,
3568 (page << IGP_PAGE_SHIFT));
3570 hw->phy.addr = phy_addr;
3577 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3578 page << IGP_PAGE_SHIFT, reg);
3580 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3584 hw->phy.ops.release(hw);
3590 * e1000_read_phy_reg_hv - Read HV PHY register
3591 * @hw: pointer to the HW structure
3592 * @offset: register offset to be read
3593 * @data: pointer to the read data
3595 * Acquires semaphore then reads the PHY register at offset and stores
3596 * the retrieved information in data. Release the acquired semaphore
3599 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3601 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE, false);
3605 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3606 * @hw: pointer to the HW structure
3607 * @offset: register offset to be read
3608 * @data: pointer to the read data
3610 * Reads the PHY register at offset and stores the retrieved information
3611 * in data. Assumes semaphore already acquired.
3613 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3615 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, FALSE);
3619 * e1000_read_phy_reg_page_hv - Read HV PHY register
3620 * @hw: pointer to the HW structure
3621 * @offset: register offset to write to
3622 * @data: data to write at register offset
3624 * Reads the PHY register at offset and stores the retrieved information
3625 * in data. Assumes semaphore already acquired and page already set.
3627 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3629 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, true);
3633 * __e1000_write_phy_reg_hv - Write HV PHY register
3634 * @hw: pointer to the HW structure
3635 * @offset: register offset to write to
3636 * @data: data to write at register offset
3637 * @locked: semaphore has already been acquired or not
3639 * Acquires semaphore, if necessary, then writes the data to PHY register
3640 * at the offset. Release any acquired semaphores before exiting.
3642 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3643 bool locked, bool page_set)
3646 u16 page = BM_PHY_REG_PAGE(offset);
3647 u16 reg = BM_PHY_REG_NUM(offset);
3648 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3650 DEBUGFUNC("__e1000_write_phy_reg_hv");
3653 ret_val = hw->phy.ops.acquire(hw);
3657 /* Page 800 works differently than the rest so it has its own func */
3658 if (page == BM_WUC_PAGE) {
3659 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3664 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3665 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3671 if (page == HV_INTC_FC_PAGE_START)
3674 /* Workaround MDIO accesses being disabled after entering IEEE
3675 * Power Down (when bit 11 of the PHY Control register is set)
3677 if ((hw->phy.type == e1000_phy_82578) &&
3678 (hw->phy.revision >= 1) &&
3679 (hw->phy.addr == 2) &&
3680 !(MAX_PHY_REG_ADDRESS & reg) &&
3681 (data & (1 << 11))) {
3683 ret_val = e1000_access_phy_debug_regs_hv(hw,
3690 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3691 /* Page is shifted left, PHY expects (page x 32) */
3692 ret_val = e1000_set_page_igp(hw,
3693 (page << IGP_PAGE_SHIFT));
3695 hw->phy.addr = phy_addr;
3702 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3703 page << IGP_PAGE_SHIFT, reg);
3705 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3710 hw->phy.ops.release(hw);
3716 * e1000_write_phy_reg_hv - Write HV PHY register
3717 * @hw: pointer to the HW structure
3718 * @offset: register offset to write to
3719 * @data: data to write at register offset
3721 * Acquires semaphore then writes the data to PHY register at the offset.
3722 * Release the acquired semaphores before exiting.
3724 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3726 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE, false);
3730 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3731 * @hw: pointer to the HW structure
3732 * @offset: register offset to write to
3733 * @data: data to write at register offset
3735 * Writes the data to PHY register at the offset. Assumes semaphore
3738 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3740 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, FALSE);
3744 * e1000_write_phy_reg_page_hv - Write HV PHY register
3745 * @hw: pointer to the HW structure
3746 * @offset: register offset to write to
3747 * @data: data to write at register offset
3749 * Writes the data to PHY register at the offset. Assumes semaphore
3750 * already acquired and page already set.
3752 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3754 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, true);
3758 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3759 * @page: page to be accessed
3761 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3765 if (page >= HV_INTC_FC_PAGE_START)
3772 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3773 * @hw: pointer to the HW structure
3774 * @offset: register offset to be read or written
3775 * @data: pointer to the data to be read or written
3776 * @read: determines if operation is read or write
3778 * Reads the PHY register at offset and stores the retreived information
3779 * in data. Assumes semaphore already acquired. Note that the procedure
3780 * to access these regs uses the address port and data port to read/write.
3781 * These accesses done with PHY address 2 and without using pages.
3783 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3784 u16 *data, bool read)
3790 DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3792 /* This takes care of the difference with desktop vs mobile phy */
3793 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3794 I82578_ADDR_REG : I82577_ADDR_REG);
3795 data_reg = addr_reg + 1;
3797 /* All operations in this function are phy address 2 */
3800 /* masking with 0x3F to remove the page from offset */
3801 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3803 DEBUGOUT("Could not write the Address Offset port register\n");
3807 /* Read or write the data value next */
3809 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3811 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3814 DEBUGOUT("Could not access the Data port register\n");
3820 * e1000_link_stall_workaround_hv - Si workaround
3821 * @hw: pointer to the HW structure
3823 * This function works around a Si bug where the link partner can get
3824 * a link up indication before the PHY does. If small packets are sent
3825 * by the link partner they can be placed in the packet buffer without
3826 * being properly accounted for by the PHY and will stall preventing
3827 * further packets from being received. The workaround is to clear the
3828 * packet buffer after the PHY detects link up.
3830 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3832 s32 ret_val = E1000_SUCCESS;
3835 DEBUGFUNC("e1000_link_stall_workaround_hv");
3837 if (hw->phy.type != e1000_phy_82578)
3838 return E1000_SUCCESS;
3840 /* Do not apply workaround if in PHY loopback bit 14 set */
3841 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3842 if (data & PHY_CONTROL_LB)
3843 return E1000_SUCCESS;
3845 /* check if link is up and at 1Gbps */
3846 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3850 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3851 BM_CS_STATUS_SPEED_MASK);
3853 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3854 BM_CS_STATUS_SPEED_1000))
3855 return E1000_SUCCESS;
3859 /* flush the packets in the fifo buffer */
3860 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3861 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3862 HV_MUX_DATA_CTRL_FORCE_SPEED));
3866 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3867 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3871 * e1000_check_polarity_82577 - Checks the polarity.
3872 * @hw: pointer to the HW structure
3874 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3876 * Polarity is determined based on the PHY specific status register.
3878 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3880 struct e1000_phy_info *phy = &hw->phy;
3884 DEBUGFUNC("e1000_check_polarity_82577");
3886 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3889 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3890 ? e1000_rev_polarity_reversed
3891 : e1000_rev_polarity_normal);
3897 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3898 * @hw: pointer to the HW structure
3900 * Calls the PHY setup function to force speed and duplex.
3902 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3904 struct e1000_phy_info *phy = &hw->phy;
3909 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3911 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3915 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3917 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3923 if (phy->autoneg_wait_to_complete) {
3924 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3926 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3932 DEBUGOUT("Link taking longer than expected.\n");
3935 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3943 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3944 * @hw: pointer to the HW structure
3946 * Read PHY status to determine if link is up. If link is up, then
3947 * set/determine 10base-T extended distance and polarity correction. Read
3948 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3949 * determine on the cable length, local and remote receiver.
3951 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3953 struct e1000_phy_info *phy = &hw->phy;
3958 DEBUGFUNC("e1000_get_phy_info_82577");
3960 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3965 DEBUGOUT("Phy info is only valid if link is up\n");
3966 return -E1000_ERR_CONFIG;
3969 phy->polarity_correction = TRUE;
3971 ret_val = e1000_check_polarity_82577(hw);
3975 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3979 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3981 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3982 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3983 ret_val = hw->phy.ops.get_cable_length(hw);
3987 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3991 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3992 ? e1000_1000t_rx_status_ok
3993 : e1000_1000t_rx_status_not_ok;
3995 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3996 ? e1000_1000t_rx_status_ok
3997 : e1000_1000t_rx_status_not_ok;
3999 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
4000 phy->local_rx = e1000_1000t_rx_status_undefined;
4001 phy->remote_rx = e1000_1000t_rx_status_undefined;
4004 return E1000_SUCCESS;
4008 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
4009 * @hw: pointer to the HW structure
4011 * Reads the diagnostic status register and verifies result is valid before
4012 * placing it in the phy_cable_length field.
4014 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
4016 struct e1000_phy_info *phy = &hw->phy;
4018 u16 phy_data, length;
4020 DEBUGFUNC("e1000_get_cable_length_82577");
4022 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4026 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
4027 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
4029 if (length == E1000_CABLE_LENGTH_UNDEFINED)
4030 return -E1000_ERR_PHY;
4032 phy->cable_length = length;
4034 return E1000_SUCCESS;
4038 * e1000_write_phy_reg_gs40g - Write GS40G PHY register
4039 * @hw: pointer to the HW structure
4040 * @offset: register offset to write to
4041 * @data: data to write at register offset
4043 * Acquires semaphore, if necessary, then writes the data to PHY register
4044 * at the offset. Release any acquired semaphores before exiting.
4046 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
4049 u16 page = offset >> GS40G_PAGE_SHIFT;
4051 DEBUGFUNC("e1000_write_phy_reg_gs40g");
4053 offset = offset & GS40G_OFFSET_MASK;
4054 ret_val = hw->phy.ops.acquire(hw);
4058 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4061 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
4064 hw->phy.ops.release(hw);
4069 * e1000_read_phy_reg_gs40g - Read GS40G PHY register
4070 * @hw: pointer to the HW structure
4071 * @offset: lower half is register offset to read to
4072 * upper half is page to use.
4073 * @data: data to read at register offset
4075 * Acquires semaphore, if necessary, then reads the data in the PHY register
4076 * at the offset. Release any acquired semaphores before exiting.
4078 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
4081 u16 page = offset >> GS40G_PAGE_SHIFT;
4083 DEBUGFUNC("e1000_read_phy_reg_gs40g");
4085 offset = offset & GS40G_OFFSET_MASK;
4086 ret_val = hw->phy.ops.acquire(hw);
4090 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4093 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
4096 hw->phy.ops.release(hw);
4101 * e1000_read_phy_reg_mphy - Read mPHY control register
4102 * @hw: pointer to the HW structure
4103 * @address: address to be read
4104 * @data: pointer to the read data
4106 * Reads the mPHY control register in the PHY at offset and stores the
4107 * information read to data.
4109 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data)
4112 bool locked = FALSE;
4115 DEBUGFUNC("e1000_read_phy_reg_mphy");
4117 /* Check if mPHY is ready to read/write operations */
4118 ready = e1000_is_mphy_ready(hw);
4120 return -E1000_ERR_PHY;
4122 /* Check if mPHY access is disabled and enable it if so */
4123 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4124 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4126 ready = e1000_is_mphy_ready(hw);
4128 return -E1000_ERR_PHY;
4129 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4130 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4133 /* Set the address that we want to read */
4134 ready = e1000_is_mphy_ready(hw);
4136 return -E1000_ERR_PHY;
4138 /* We mask address, because we want to use only current lane */
4139 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK &
4140 ~E1000_MPHY_ADDRESS_FNC_OVERRIDE) |
4141 (address & E1000_MPHY_ADDRESS_MASK);
4142 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4144 /* Read data from the address */
4145 ready = e1000_is_mphy_ready(hw);
4147 return -E1000_ERR_PHY;
4148 *data = E1000_READ_REG(hw, E1000_MPHY_DATA);
4150 /* Disable access to mPHY if it was originally disabled */
4152 ready = e1000_is_mphy_ready(hw);
4154 return -E1000_ERR_PHY;
4155 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4156 E1000_MPHY_DIS_ACCESS);
4158 return E1000_SUCCESS;
4162 * e1000_write_phy_reg_mphy - Write mPHY control register
4163 * @hw: pointer to the HW structure
4164 * @address: address to write to
4165 * @data: data to write to register at offset
4166 * @line_override: used when we want to use different line than default one
4168 * Writes data to mPHY control register.
4170 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,
4174 bool locked = FALSE;
4177 DEBUGFUNC("e1000_write_phy_reg_mphy");
4179 /* Check if mPHY is ready to read/write operations */
4180 ready = e1000_is_mphy_ready(hw);
4182 return -E1000_ERR_PHY;
4184 /* Check if mPHY access is disabled and enable it if so */
4185 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4186 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4188 ready = e1000_is_mphy_ready(hw);
4190 return -E1000_ERR_PHY;
4191 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4192 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4195 /* Set the address that we want to read */
4196 ready = e1000_is_mphy_ready(hw);
4198 return -E1000_ERR_PHY;
4200 /* We mask address, because we want to use only current lane */
4202 mphy_ctrl |= E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4204 mphy_ctrl &= ~E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4205 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK) |
4206 (address & E1000_MPHY_ADDRESS_MASK);
4207 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4209 /* Read data from the address */
4210 ready = e1000_is_mphy_ready(hw);
4212 return -E1000_ERR_PHY;
4213 E1000_WRITE_REG(hw, E1000_MPHY_DATA, data);
4215 /* Disable access to mPHY if it was originally disabled */
4217 ready = e1000_is_mphy_ready(hw);
4219 return -E1000_ERR_PHY;
4220 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4221 E1000_MPHY_DIS_ACCESS);
4223 return E1000_SUCCESS;
4227 * e1000_is_mphy_ready - Check if mPHY control register is not busy
4228 * @hw: pointer to the HW structure
4230 * Returns mPHY control register status.
4232 bool e1000_is_mphy_ready(struct e1000_hw *hw)
4234 u16 retry_count = 0;
4238 while (retry_count < 2) {
4239 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4240 if (mphy_ctrl & E1000_MPHY_BUSY) {
4250 DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n");