1 /******************************************************************************
3 Copyright (c) 2001-2010, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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32 ******************************************************************************/
35 #include "e1000_api.h"
37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read);
40 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
42 u16 *data, bool read);
44 /* Cable length tables */
45 static const u16 e1000_m88_cable_length_table[] = {
46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
48 (sizeof(e1000_m88_cable_length_table) / \
49 sizeof(e1000_m88_cable_length_table[0]))
51 static const u16 e1000_igp_2_cable_length_table[] = {
52 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
53 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
54 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
55 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
56 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
57 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
58 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
60 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
61 (sizeof(e1000_igp_2_cable_length_table) / \
62 sizeof(e1000_igp_2_cable_length_table[0]))
65 * e1000_init_phy_ops_generic - Initialize PHY function pointers
66 * @hw: pointer to the HW structure
68 * Setups up the function pointers to no-op functions
70 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
72 struct e1000_phy_info *phy = &hw->phy;
73 DEBUGFUNC("e1000_init_phy_ops_generic");
75 /* Initialize function pointers */
76 phy->ops.init_params = e1000_null_ops_generic;
77 phy->ops.acquire = e1000_null_ops_generic;
78 phy->ops.check_polarity = e1000_null_ops_generic;
79 phy->ops.check_reset_block = e1000_null_ops_generic;
80 phy->ops.commit = e1000_null_ops_generic;
81 phy->ops.force_speed_duplex = e1000_null_ops_generic;
82 phy->ops.get_cfg_done = e1000_null_ops_generic;
83 phy->ops.get_cable_length = e1000_null_ops_generic;
84 phy->ops.get_info = e1000_null_ops_generic;
85 phy->ops.read_reg = e1000_null_read_reg;
86 phy->ops.read_reg_locked = e1000_null_read_reg;
87 phy->ops.release = e1000_null_phy_generic;
88 phy->ops.reset = e1000_null_ops_generic;
89 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
90 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
91 phy->ops.write_reg = e1000_null_write_reg;
92 phy->ops.write_reg_locked = e1000_null_write_reg;
93 phy->ops.power_up = e1000_null_phy_generic;
94 phy->ops.power_down = e1000_null_phy_generic;
95 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
99 * e1000_null_read_reg - No-op function, return 0
100 * @hw: pointer to the HW structure
102 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data)
104 DEBUGFUNC("e1000_null_read_reg");
105 return E1000_SUCCESS;
109 * e1000_null_phy_generic - No-op function, return void
110 * @hw: pointer to the HW structure
112 void e1000_null_phy_generic(struct e1000_hw *hw)
114 DEBUGFUNC("e1000_null_phy_generic");
119 * e1000_null_lplu_state - No-op function, return 0
120 * @hw: pointer to the HW structure
122 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active)
124 DEBUGFUNC("e1000_null_lplu_state");
125 return E1000_SUCCESS;
129 * e1000_null_write_reg - No-op function, return 0
130 * @hw: pointer to the HW structure
132 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data)
134 DEBUGFUNC("e1000_null_write_reg");
135 return E1000_SUCCESS;
139 * e1000_check_reset_block_generic - Check if PHY reset is blocked
140 * @hw: pointer to the HW structure
142 * Read the PHY management control register and check whether a PHY reset
143 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
144 * return E1000_BLK_PHY_RESET (12).
146 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
150 DEBUGFUNC("e1000_check_reset_block");
152 manc = E1000_READ_REG(hw, E1000_MANC);
154 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
155 E1000_BLK_PHY_RESET : E1000_SUCCESS;
159 * e1000_get_phy_id - Retrieve the PHY ID and revision
160 * @hw: pointer to the HW structure
162 * Reads the PHY registers and stores the PHY ID and possibly the PHY
163 * revision in the hardware structure.
165 s32 e1000_get_phy_id(struct e1000_hw *hw)
167 struct e1000_phy_info *phy = &hw->phy;
168 s32 ret_val = E1000_SUCCESS;
172 DEBUGFUNC("e1000_get_phy_id");
174 if (!(phy->ops.read_reg))
177 while (retry_count < 2) {
178 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
182 phy->id = (u32)(phy_id << 16);
184 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
188 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
189 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
191 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
201 * e1000_phy_reset_dsp_generic - Reset PHY DSP
202 * @hw: pointer to the HW structure
204 * Reset the digital signal processor.
206 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
208 s32 ret_val = E1000_SUCCESS;
210 DEBUGFUNC("e1000_phy_reset_dsp_generic");
212 if (!(hw->phy.ops.write_reg))
215 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
219 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
226 * e1000_read_phy_reg_mdic - Read MDI control register
227 * @hw: pointer to the HW structure
228 * @offset: register offset to be read
229 * @data: pointer to the read data
231 * Reads the MDI control register in the PHY at offset and stores the
232 * information read to data.
234 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
236 struct e1000_phy_info *phy = &hw->phy;
238 s32 ret_val = E1000_SUCCESS;
240 DEBUGFUNC("e1000_read_phy_reg_mdic");
242 if (offset > MAX_PHY_REG_ADDRESS) {
243 DEBUGOUT1("PHY Address %d is out of range\n", offset);
244 return -E1000_ERR_PARAM;
248 * Set up Op-code, Phy Address, and register offset in the MDI
249 * Control register. The MAC will take care of interfacing with the
250 * PHY to retrieve the desired data.
252 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
253 (phy->addr << E1000_MDIC_PHY_SHIFT) |
254 (E1000_MDIC_OP_READ));
256 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
258 /* Workaround for Si errata */
259 if ((hw->phy.type == e1000_phy_82577) && (hw->revision_id <= 2))
263 * Poll the ready bit to see if the MDI read completed
264 * Increasing the time out as testing showed failures with
267 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
269 mdic = E1000_READ_REG(hw, E1000_MDIC);
270 if (mdic & E1000_MDIC_READY)
273 if (!(mdic & E1000_MDIC_READY)) {
274 DEBUGOUT("MDI Read did not complete\n");
275 ret_val = -E1000_ERR_PHY;
278 if (mdic & E1000_MDIC_ERROR) {
279 DEBUGOUT("MDI Error\n");
280 ret_val = -E1000_ERR_PHY;
286 * Allow some time after each MDIC transaction to avoid
287 * reading duplicate data in the next MDIC transaction.
289 if (hw->mac.type == e1000_pch2lan)
297 * e1000_write_phy_reg_mdic - Write MDI control register
298 * @hw: pointer to the HW structure
299 * @offset: register offset to write to
300 * @data: data to write to register at offset
302 * Writes data to MDI control register in the PHY at offset.
304 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
306 struct e1000_phy_info *phy = &hw->phy;
308 s32 ret_val = E1000_SUCCESS;
310 DEBUGFUNC("e1000_write_phy_reg_mdic");
312 if (offset > MAX_PHY_REG_ADDRESS) {
313 DEBUGOUT1("PHY Address %d is out of range\n", offset);
314 return -E1000_ERR_PARAM;
318 * Set up Op-code, Phy Address, and register offset in the MDI
319 * Control register. The MAC will take care of interfacing with the
320 * PHY to retrieve the desired data.
322 mdic = (((u32)data) |
323 (offset << E1000_MDIC_REG_SHIFT) |
324 (phy->addr << E1000_MDIC_PHY_SHIFT) |
325 (E1000_MDIC_OP_WRITE));
327 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
329 /* Workaround for Si errata */
330 if ((hw->phy.type == e1000_phy_82577) && (hw->revision_id <= 2))
334 * Poll the ready bit to see if the MDI read completed
335 * Increasing the time out as testing showed failures with
338 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
340 mdic = E1000_READ_REG(hw, E1000_MDIC);
341 if (mdic & E1000_MDIC_READY)
344 if (!(mdic & E1000_MDIC_READY)) {
345 DEBUGOUT("MDI Write did not complete\n");
346 ret_val = -E1000_ERR_PHY;
349 if (mdic & E1000_MDIC_ERROR) {
350 DEBUGOUT("MDI Error\n");
351 ret_val = -E1000_ERR_PHY;
356 * Allow some time after each MDIC transaction to avoid
357 * reading duplicate data in the next MDIC transaction.
359 if (hw->mac.type == e1000_pch2lan)
367 * e1000_read_phy_reg_i2c - Read PHY register using i2c
368 * @hw: pointer to the HW structure
369 * @offset: register offset to be read
370 * @data: pointer to the read data
372 * Reads the PHY register at offset using the i2c interface and stores the
373 * retrieved information in data.
375 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
377 struct e1000_phy_info *phy = &hw->phy;
380 DEBUGFUNC("e1000_read_phy_reg_i2c");
383 * Set up Op-code, Phy Address, and register address in the I2CCMD
384 * register. The MAC will take care of interfacing with the
385 * PHY to retrieve the desired data.
387 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
388 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
389 (E1000_I2CCMD_OPCODE_READ));
391 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
393 /* Poll the ready bit to see if the I2C read completed */
394 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
396 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
397 if (i2ccmd & E1000_I2CCMD_READY)
400 if (!(i2ccmd & E1000_I2CCMD_READY)) {
401 DEBUGOUT("I2CCMD Read did not complete\n");
402 return -E1000_ERR_PHY;
404 if (i2ccmd & E1000_I2CCMD_ERROR) {
405 DEBUGOUT("I2CCMD Error bit set\n");
406 return -E1000_ERR_PHY;
409 /* Need to byte-swap the 16-bit value. */
410 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
412 return E1000_SUCCESS;
416 * e1000_write_phy_reg_i2c - Write PHY register using i2c
417 * @hw: pointer to the HW structure
418 * @offset: register offset to write to
419 * @data: data to write at register offset
421 * Writes the data to PHY register at the offset using the i2c interface.
423 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
425 struct e1000_phy_info *phy = &hw->phy;
427 u16 phy_data_swapped;
429 DEBUGFUNC("e1000_write_phy_reg_i2c");
431 /* Swap the data bytes for the I2C interface */
432 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
435 * Set up Op-code, Phy Address, and register address in the I2CCMD
436 * register. The MAC will take care of interfacing with the
437 * PHY to retrieve the desired data.
439 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
440 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
441 E1000_I2CCMD_OPCODE_WRITE |
444 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
446 /* Poll the ready bit to see if the I2C read completed */
447 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
449 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
450 if (i2ccmd & E1000_I2CCMD_READY)
453 if (!(i2ccmd & E1000_I2CCMD_READY)) {
454 DEBUGOUT("I2CCMD Write did not complete\n");
455 return -E1000_ERR_PHY;
457 if (i2ccmd & E1000_I2CCMD_ERROR) {
458 DEBUGOUT("I2CCMD Error bit set\n");
459 return -E1000_ERR_PHY;
462 return E1000_SUCCESS;
466 * e1000_read_phy_reg_m88 - Read m88 PHY register
467 * @hw: pointer to the HW structure
468 * @offset: register offset to be read
469 * @data: pointer to the read data
471 * Acquires semaphore, if necessary, then reads the PHY register at offset
472 * and storing the retrieved information in data. Release any acquired
473 * semaphores before exiting.
475 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
477 s32 ret_val = E1000_SUCCESS;
479 DEBUGFUNC("e1000_read_phy_reg_m88");
481 if (!(hw->phy.ops.acquire))
484 ret_val = hw->phy.ops.acquire(hw);
488 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
491 hw->phy.ops.release(hw);
498 * e1000_write_phy_reg_m88 - Write m88 PHY register
499 * @hw: pointer to the HW structure
500 * @offset: register offset to write to
501 * @data: data to write at register offset
503 * Acquires semaphore, if necessary, then writes the data to PHY register
504 * at the offset. Release any acquired semaphores before exiting.
506 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
508 s32 ret_val = E1000_SUCCESS;
510 DEBUGFUNC("e1000_write_phy_reg_m88");
512 if (!(hw->phy.ops.acquire))
515 ret_val = hw->phy.ops.acquire(hw);
519 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
522 hw->phy.ops.release(hw);
529 * __e1000_read_phy_reg_igp - Read igp PHY register
530 * @hw: pointer to the HW structure
531 * @offset: register offset to be read
532 * @data: pointer to the read data
533 * @locked: semaphore has already been acquired or not
535 * Acquires semaphore, if necessary, then reads the PHY register at offset
536 * and stores the retrieved information in data. Release any acquired
537 * semaphores before exiting.
539 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
542 s32 ret_val = E1000_SUCCESS;
544 DEBUGFUNC("__e1000_read_phy_reg_igp");
547 if (!(hw->phy.ops.acquire))
550 ret_val = hw->phy.ops.acquire(hw);
555 if (offset > MAX_PHY_MULTI_PAGE_REG) {
556 ret_val = e1000_write_phy_reg_mdic(hw,
557 IGP01E1000_PHY_PAGE_SELECT,
563 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
568 hw->phy.ops.release(hw);
574 * e1000_read_phy_reg_igp - Read igp PHY register
575 * @hw: pointer to the HW structure
576 * @offset: register offset to be read
577 * @data: pointer to the read data
579 * Acquires semaphore then reads the PHY register at offset and stores the
580 * retrieved information in data.
581 * Release the acquired semaphore before exiting.
583 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
585 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE);
589 * e1000_read_phy_reg_igp_locked - Read igp PHY register
590 * @hw: pointer to the HW structure
591 * @offset: register offset to be read
592 * @data: pointer to the read data
594 * Reads the PHY register at offset and stores the retrieved information
595 * in data. Assumes semaphore already acquired.
597 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
599 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE);
603 * e1000_write_phy_reg_igp - Write igp PHY register
604 * @hw: pointer to the HW structure
605 * @offset: register offset to write to
606 * @data: data to write at register offset
607 * @locked: semaphore has already been acquired or not
609 * Acquires semaphore, if necessary, then writes the data to PHY register
610 * at the offset. Release any acquired semaphores before exiting.
612 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
615 s32 ret_val = E1000_SUCCESS;
617 DEBUGFUNC("e1000_write_phy_reg_igp");
620 if (!(hw->phy.ops.acquire))
623 ret_val = hw->phy.ops.acquire(hw);
628 if (offset > MAX_PHY_MULTI_PAGE_REG) {
629 ret_val = e1000_write_phy_reg_mdic(hw,
630 IGP01E1000_PHY_PAGE_SELECT,
636 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
641 hw->phy.ops.release(hw);
648 * e1000_write_phy_reg_igp - Write igp PHY register
649 * @hw: pointer to the HW structure
650 * @offset: register offset to write to
651 * @data: data to write at register offset
653 * Acquires semaphore then writes the data to PHY register
654 * at the offset. Release any acquired semaphores before exiting.
656 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
658 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE);
662 * e1000_write_phy_reg_igp_locked - Write igp PHY register
663 * @hw: pointer to the HW structure
664 * @offset: register offset to write to
665 * @data: data to write at register offset
667 * Writes the data to PHY register at the offset.
668 * Assumes semaphore already acquired.
670 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
672 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE);
676 * __e1000_read_kmrn_reg - Read kumeran register
677 * @hw: pointer to the HW structure
678 * @offset: register offset to be read
679 * @data: pointer to the read data
680 * @locked: semaphore has already been acquired or not
682 * Acquires semaphore, if necessary. Then reads the PHY register at offset
683 * using the kumeran interface. The information retrieved is stored in data.
684 * Release any acquired semaphores before exiting.
686 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
690 s32 ret_val = E1000_SUCCESS;
692 DEBUGFUNC("__e1000_read_kmrn_reg");
695 if (!(hw->phy.ops.acquire))
698 ret_val = hw->phy.ops.acquire(hw);
703 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
704 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
705 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
709 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
710 *data = (u16)kmrnctrlsta;
713 hw->phy.ops.release(hw);
720 * e1000_read_kmrn_reg_generic - Read kumeran register
721 * @hw: pointer to the HW structure
722 * @offset: register offset to be read
723 * @data: pointer to the read data
725 * Acquires semaphore then reads the PHY register at offset using the
726 * kumeran interface. The information retrieved is stored in data.
727 * Release the acquired semaphore before exiting.
729 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
731 return __e1000_read_kmrn_reg(hw, offset, data, FALSE);
735 * e1000_read_kmrn_reg_locked - Read kumeran register
736 * @hw: pointer to the HW structure
737 * @offset: register offset to be read
738 * @data: pointer to the read data
740 * Reads the PHY register at offset using the kumeran interface. The
741 * information retrieved is stored in data.
742 * Assumes semaphore already acquired.
744 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
746 return __e1000_read_kmrn_reg(hw, offset, data, TRUE);
750 * __e1000_write_kmrn_reg - Write kumeran register
751 * @hw: pointer to the HW structure
752 * @offset: register offset to write to
753 * @data: data to write at register offset
754 * @locked: semaphore has already been acquired or not
756 * Acquires semaphore, if necessary. Then write the data to PHY register
757 * at the offset using the kumeran interface. Release any acquired semaphores
760 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
764 s32 ret_val = E1000_SUCCESS;
766 DEBUGFUNC("e1000_write_kmrn_reg_generic");
769 if (!(hw->phy.ops.acquire))
772 ret_val = hw->phy.ops.acquire(hw);
777 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
778 E1000_KMRNCTRLSTA_OFFSET) | data;
779 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
784 hw->phy.ops.release(hw);
791 * e1000_write_kmrn_reg_generic - Write kumeran register
792 * @hw: pointer to the HW structure
793 * @offset: register offset to write to
794 * @data: data to write at register offset
796 * Acquires semaphore then writes the data to the PHY register at the offset
797 * using the kumeran interface. Release the acquired semaphore before exiting.
799 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
801 return __e1000_write_kmrn_reg(hw, offset, data, FALSE);
805 * e1000_write_kmrn_reg_locked - Write kumeran register
806 * @hw: pointer to the HW structure
807 * @offset: register offset to write to
808 * @data: data to write at register offset
810 * Write the data to PHY register at the offset using the kumeran interface.
811 * Assumes semaphore already acquired.
813 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
815 return __e1000_write_kmrn_reg(hw, offset, data, TRUE);
819 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
820 * @hw: pointer to the HW structure
822 * Sets up Carrier-sense on Transmit and downshift values.
824 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
829 DEBUGFUNC("e1000_copper_link_setup_82577");
831 if (hw->phy.reset_disable) {
832 ret_val = E1000_SUCCESS;
836 if (hw->phy.type == e1000_phy_82580) {
837 ret_val = hw->phy.ops.reset(hw);
839 DEBUGOUT("Error resetting the PHY.\n");
844 /* Enable CRS on Tx. This must be set for half-duplex operation. */
845 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
849 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
851 /* Enable downshift */
852 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
854 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
861 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
862 * @hw: pointer to the HW structure
864 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
865 * and downshift values are set also.
867 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
869 struct e1000_phy_info *phy = &hw->phy;
873 DEBUGFUNC("e1000_copper_link_setup_m88");
875 if (phy->reset_disable) {
876 ret_val = E1000_SUCCESS;
880 /* Enable CRS on Tx. This must be set for half-duplex operation. */
881 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
885 /* For BM PHY this bit is downshift enable */
886 if (phy->type != e1000_phy_bm)
887 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
891 * MDI/MDI-X = 0 (default)
892 * 0 - Auto for all speeds
895 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
897 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
901 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
904 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
907 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
911 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
917 * disable_polarity_correction = 0 (default)
918 * Automatic Correction for Reversed Cable Polarity
922 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
923 if (phy->disable_polarity_correction == 1)
924 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
926 /* Enable downshift on BM (disabled by default) */
927 if (phy->type == e1000_phy_bm)
928 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
930 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
934 if ((phy->type == e1000_phy_m88) &&
935 (phy->revision < E1000_REVISION_4) &&
936 (phy->id != BME1000_E_PHY_ID_R2)) {
938 * Force TX_CLK in the Extended PHY Specific Control Register
941 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
946 phy_data |= M88E1000_EPSCR_TX_CLK_25;
948 if ((phy->revision == E1000_REVISION_2) &&
949 (phy->id == M88E1111_I_PHY_ID)) {
950 /* 82573L PHY - set the downshift counter to 5x. */
951 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
952 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
954 /* Configure Master and Slave downshift values */
955 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
956 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
957 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
958 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
960 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
966 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
967 /* Set PHY page 0, register 29 to 0x0003 */
968 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
972 /* Set PHY page 0, register 30 to 0x0000 */
973 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
978 /* Commit the changes. */
979 ret_val = phy->ops.commit(hw);
981 DEBUGOUT("Error committing the PHY changes\n");
985 if (phy->type == e1000_phy_82578) {
986 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
991 /* 82578 PHY - set the downshift count to 1x. */
992 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
993 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
994 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1005 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1006 * @hw: pointer to the HW structure
1008 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1009 * Also enables and sets the downshift parameters.
1011 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1013 struct e1000_phy_info *phy = &hw->phy;
1017 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1019 if (phy->reset_disable) {
1020 ret_val = E1000_SUCCESS;
1024 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1025 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1031 * MDI/MDI-X = 0 (default)
1032 * 0 - Auto for all speeds
1035 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1037 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1039 switch (phy->mdix) {
1041 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1044 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1047 /* M88E1112 does not support this mode) */
1048 if (phy->id != M88E1112_E_PHY_ID) {
1049 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1054 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1060 * disable_polarity_correction = 0 (default)
1061 * Automatic Correction for Reversed Cable Polarity
1065 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1066 if (phy->disable_polarity_correction == 1)
1067 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1069 /* Enable downshift and setting it to X6 */
1070 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1071 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1072 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1074 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1078 /* Commit the changes. */
1079 ret_val = phy->ops.commit(hw);
1081 DEBUGOUT("Error committing the PHY changes\n");
1090 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1091 * @hw: pointer to the HW structure
1093 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1096 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1098 struct e1000_phy_info *phy = &hw->phy;
1102 DEBUGFUNC("e1000_copper_link_setup_igp");
1104 if (phy->reset_disable) {
1105 ret_val = E1000_SUCCESS;
1109 ret_val = hw->phy.ops.reset(hw);
1111 DEBUGOUT("Error resetting the PHY.\n");
1116 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1117 * timeout issues when LFS is enabled.
1122 * The NVM settings will configure LPLU in D3 for
1125 if (phy->type == e1000_phy_igp) {
1126 /* disable lplu d3 during driver init */
1127 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE);
1129 DEBUGOUT("Error Disabling LPLU D3\n");
1134 /* disable lplu d0 during driver init */
1135 if (hw->phy.ops.set_d0_lplu_state) {
1136 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE);
1138 DEBUGOUT("Error Disabling LPLU D0\n");
1142 /* Configure mdi-mdix settings */
1143 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1147 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1149 switch (phy->mdix) {
1151 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1154 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1158 data |= IGP01E1000_PSCR_AUTO_MDIX;
1161 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1165 /* set auto-master slave resolution settings */
1166 if (hw->mac.autoneg) {
1168 * when autonegotiation advertisement is only 1000Mbps then we
1169 * should disable SmartSpeed and enable Auto MasterSlave
1170 * resolution as hardware default.
1172 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1173 /* Disable SmartSpeed */
1174 ret_val = phy->ops.read_reg(hw,
1175 IGP01E1000_PHY_PORT_CONFIG,
1180 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1181 ret_val = phy->ops.write_reg(hw,
1182 IGP01E1000_PHY_PORT_CONFIG,
1187 /* Set auto Master/Slave resolution process */
1188 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1192 data &= ~CR_1000T_MS_ENABLE;
1193 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1198 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1202 /* load defaults for future use */
1203 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
1204 ((data & CR_1000T_MS_VALUE) ?
1205 e1000_ms_force_master :
1206 e1000_ms_force_slave) :
1209 switch (phy->ms_type) {
1210 case e1000_ms_force_master:
1211 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1213 case e1000_ms_force_slave:
1214 data |= CR_1000T_MS_ENABLE;
1215 data &= ~(CR_1000T_MS_VALUE);
1218 data &= ~CR_1000T_MS_ENABLE;
1222 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1232 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1233 * @hw: pointer to the HW structure
1235 * Performs initial bounds checking on autoneg advertisement parameter, then
1236 * configure to advertise the full capability. Setup the PHY to autoneg
1237 * and restart the negotiation process between the link partner. If
1238 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1240 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1242 struct e1000_phy_info *phy = &hw->phy;
1246 DEBUGFUNC("e1000_copper_link_autoneg");
1249 * Perform some bounds checking on the autoneg advertisement
1252 phy->autoneg_advertised &= phy->autoneg_mask;
1255 * If autoneg_advertised is zero, we assume it was not defaulted
1256 * by the calling code so we set to advertise full capability.
1258 if (phy->autoneg_advertised == 0)
1259 phy->autoneg_advertised = phy->autoneg_mask;
1261 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1262 ret_val = e1000_phy_setup_autoneg(hw);
1264 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1267 DEBUGOUT("Restarting Auto-Neg\n");
1270 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1271 * the Auto Neg Restart bit in the PHY control register.
1273 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1277 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1278 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1283 * Does the user want to wait for Auto-Neg to complete here, or
1284 * check at a later time (for example, callback routine).
1286 if (phy->autoneg_wait_to_complete) {
1287 ret_val = hw->mac.ops.wait_autoneg(hw);
1289 DEBUGOUT("Error while waiting for "
1290 "autoneg to complete\n");
1295 hw->mac.get_link_status = TRUE;
1302 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1303 * @hw: pointer to the HW structure
1305 * Reads the MII auto-neg advertisement register and/or the 1000T control
1306 * register and if the PHY is already setup for auto-negotiation, then
1307 * return successful. Otherwise, setup advertisement and flow control to
1308 * the appropriate values for the wanted auto-negotiation.
1310 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1312 struct e1000_phy_info *phy = &hw->phy;
1314 u16 mii_autoneg_adv_reg;
1315 u16 mii_1000t_ctrl_reg = 0;
1317 DEBUGFUNC("e1000_phy_setup_autoneg");
1319 phy->autoneg_advertised &= phy->autoneg_mask;
1321 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1322 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1326 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1327 /* Read the MII 1000Base-T Control Register (Address 9). */
1328 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1329 &mii_1000t_ctrl_reg);
1335 * Need to parse both autoneg_advertised and fc and set up
1336 * the appropriate PHY registers. First we will parse for
1337 * autoneg_advertised software override. Since we can advertise
1338 * a plethora of combinations, we need to check each bit
1343 * First we clear all the 10/100 mb speed bits in the Auto-Neg
1344 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1345 * the 1000Base-T Control Register (Address 9).
1347 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1348 NWAY_AR_100TX_HD_CAPS |
1349 NWAY_AR_10T_FD_CAPS |
1350 NWAY_AR_10T_HD_CAPS);
1351 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1353 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1355 /* Do we want to advertise 10 Mb Half Duplex? */
1356 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1357 DEBUGOUT("Advertise 10mb Half duplex\n");
1358 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1361 /* Do we want to advertise 10 Mb Full Duplex? */
1362 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1363 DEBUGOUT("Advertise 10mb Full duplex\n");
1364 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1367 /* Do we want to advertise 100 Mb Half Duplex? */
1368 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1369 DEBUGOUT("Advertise 100mb Half duplex\n");
1370 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1373 /* Do we want to advertise 100 Mb Full Duplex? */
1374 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1375 DEBUGOUT("Advertise 100mb Full duplex\n");
1376 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1379 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1380 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1381 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1383 /* Do we want to advertise 1000 Mb Full Duplex? */
1384 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1385 DEBUGOUT("Advertise 1000mb Full duplex\n");
1386 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1390 * Check for a software override of the flow control settings, and
1391 * setup the PHY advertisement registers accordingly. If
1392 * auto-negotiation is enabled, then software will have to set the
1393 * "PAUSE" bits to the correct value in the Auto-Negotiation
1394 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1397 * The possible values of the "fc" parameter are:
1398 * 0: Flow control is completely disabled
1399 * 1: Rx flow control is enabled (we can receive pause frames
1400 * but not send pause frames).
1401 * 2: Tx flow control is enabled (we can send pause frames
1402 * but we do not support receiving pause frames).
1403 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1404 * other: No software override. The flow control configuration
1405 * in the EEPROM is used.
1407 switch (hw->fc.current_mode) {
1410 * Flow control (Rx & Tx) is completely disabled by a
1411 * software over-ride.
1413 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1415 case e1000_fc_rx_pause:
1417 * Rx Flow control is enabled, and Tx Flow control is
1418 * disabled, by a software over-ride.
1420 * Since there really isn't a way to advertise that we are
1421 * capable of Rx Pause ONLY, we will advertise that we
1422 * support both symmetric and asymmetric Rx PAUSE. Later
1423 * (in e1000_config_fc_after_link_up) we will disable the
1424 * hw's ability to send PAUSE frames.
1426 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1428 case e1000_fc_tx_pause:
1430 * Tx Flow control is enabled, and Rx Flow control is
1431 * disabled, by a software over-ride.
1433 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1434 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1438 * Flow control (both Rx and Tx) is enabled by a software
1441 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1444 DEBUGOUT("Flow control param set incorrectly\n");
1445 ret_val = -E1000_ERR_CONFIG;
1449 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1453 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1455 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1456 ret_val = phy->ops.write_reg(hw,
1458 mii_1000t_ctrl_reg);
1468 * e1000_setup_copper_link_generic - Configure copper link settings
1469 * @hw: pointer to the HW structure
1471 * Calls the appropriate function to configure the link for auto-neg or forced
1472 * speed and duplex. Then we check for link, once link is established calls
1473 * to configure collision distance and flow control are called. If link is
1474 * not established, we return -E1000_ERR_PHY (-2).
1476 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1481 DEBUGFUNC("e1000_setup_copper_link_generic");
1483 if (hw->mac.autoneg) {
1485 * Setup autoneg and flow control advertisement and perform
1488 ret_val = e1000_copper_link_autoneg(hw);
1493 * PHY will be set to 10H, 10F, 100H or 100F
1494 * depending on user settings.
1496 DEBUGOUT("Forcing Speed and Duplex\n");
1497 ret_val = hw->phy.ops.force_speed_duplex(hw);
1499 DEBUGOUT("Error Forcing Speed and Duplex\n");
1505 * Check link status. Wait up to 100 microseconds for link to become
1508 ret_val = e1000_phy_has_link_generic(hw,
1509 COPPER_LINK_UP_LIMIT,
1516 DEBUGOUT("Valid link established!!!\n");
1517 e1000_config_collision_dist_generic(hw);
1518 ret_val = e1000_config_fc_after_link_up_generic(hw);
1520 DEBUGOUT("Unable to establish link!!!\n");
1528 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1529 * @hw: pointer to the HW structure
1531 * Calls the PHY setup function to force speed and duplex. Clears the
1532 * auto-crossover to force MDI manually. Waits for link and returns
1533 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1535 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1537 struct e1000_phy_info *phy = &hw->phy;
1542 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1544 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1548 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1550 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1555 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1556 * forced whenever speed and duplex are forced.
1558 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1562 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1563 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1565 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1569 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1573 if (phy->autoneg_wait_to_complete) {
1574 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1576 ret_val = e1000_phy_has_link_generic(hw,
1584 DEBUGOUT("Link taking longer than expected.\n");
1587 ret_val = e1000_phy_has_link_generic(hw,
1600 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1601 * @hw: pointer to the HW structure
1603 * Calls the PHY setup function to force speed and duplex. Clears the
1604 * auto-crossover to force MDI manually. Resets the PHY to commit the
1605 * changes. If time expires while waiting for link up, we reset the DSP.
1606 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1607 * successful completion, else return corresponding error code.
1609 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1611 struct e1000_phy_info *phy = &hw->phy;
1616 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1619 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1620 * forced whenever speed and duplex are forced.
1622 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1626 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1627 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1631 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1633 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1637 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1639 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1643 /* Reset the phy to commit changes. */
1644 ret_val = hw->phy.ops.commit(hw);
1648 if (phy->autoneg_wait_to_complete) {
1649 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1651 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1657 if (hw->phy.type != e1000_phy_m88 ||
1658 hw->phy.id == I347AT4_E_PHY_ID ||
1659 hw->phy.id == M88E1112_E_PHY_ID) {
1660 DEBUGOUT("Link taking longer than expected.\n");
1663 * We didn't get link.
1664 * Reset the DSP and cross our fingers.
1666 ret_val = phy->ops.write_reg(hw,
1667 M88E1000_PHY_PAGE_SELECT,
1671 ret_val = e1000_phy_reset_dsp_generic(hw);
1678 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1684 if (hw->phy.type != e1000_phy_m88 ||
1685 hw->phy.id == I347AT4_E_PHY_ID ||
1686 hw->phy.id == M88E1112_E_PHY_ID)
1689 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1694 * Resetting the phy means we need to re-force TX_CLK in the
1695 * Extended PHY Specific Control Register to 25MHz clock from
1696 * the reset value of 2.5MHz.
1698 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1699 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1704 * In addition, we must re-enable CRS on Tx for both half and full
1707 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1711 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1712 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1719 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1720 * @hw: pointer to the HW structure
1722 * Forces the speed and duplex settings of the PHY.
1723 * This is a function pointer entry point only called by
1724 * PHY setup routines.
1726 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1728 struct e1000_phy_info *phy = &hw->phy;
1733 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1735 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1739 e1000_phy_force_speed_duplex_setup(hw, &data);
1741 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1745 /* Disable MDI-X support for 10/100 */
1746 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1750 data &= ~IFE_PMC_AUTO_MDIX;
1751 data &= ~IFE_PMC_FORCE_MDIX;
1753 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1757 DEBUGOUT1("IFE PMC: %X\n", data);
1761 if (phy->autoneg_wait_to_complete) {
1762 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1764 ret_val = e1000_phy_has_link_generic(hw,
1772 DEBUGOUT("Link taking longer than expected.\n");
1775 ret_val = e1000_phy_has_link_generic(hw,
1788 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1789 * @hw: pointer to the HW structure
1790 * @phy_ctrl: pointer to current value of PHY_CONTROL
1792 * Forces speed and duplex on the PHY by doing the following: disable flow
1793 * control, force speed/duplex on the MAC, disable auto speed detection,
1794 * disable auto-negotiation, configure duplex, configure speed, configure
1795 * the collision distance, write configuration to CTRL register. The
1796 * caller must write to the PHY_CONTROL register for these settings to
1799 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1801 struct e1000_mac_info *mac = &hw->mac;
1804 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1806 /* Turn off flow control when forcing speed/duplex */
1807 hw->fc.current_mode = e1000_fc_none;
1809 /* Force speed/duplex on the mac */
1810 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1811 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1812 ctrl &= ~E1000_CTRL_SPD_SEL;
1814 /* Disable Auto Speed Detection */
1815 ctrl &= ~E1000_CTRL_ASDE;
1817 /* Disable autoneg on the phy */
1818 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1820 /* Forcing Full or Half Duplex? */
1821 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1822 ctrl &= ~E1000_CTRL_FD;
1823 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1824 DEBUGOUT("Half Duplex\n");
1826 ctrl |= E1000_CTRL_FD;
1827 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1828 DEBUGOUT("Full Duplex\n");
1831 /* Forcing 10mb or 100mb? */
1832 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1833 ctrl |= E1000_CTRL_SPD_100;
1834 *phy_ctrl |= MII_CR_SPEED_100;
1835 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1836 DEBUGOUT("Forcing 100mb\n");
1838 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1839 *phy_ctrl |= MII_CR_SPEED_10;
1840 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1841 DEBUGOUT("Forcing 10mb\n");
1844 e1000_config_collision_dist_generic(hw);
1846 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1850 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
1851 * @hw: pointer to the HW structure
1852 * @active: boolean used to enable/disable lplu
1854 * Success returns 0, Failure returns 1
1856 * The low power link up (lplu) state is set to the power management level D3
1857 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
1858 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1859 * is used during Dx states where the power conservation is most important.
1860 * During driver activity, SmartSpeed should be enabled so performance is
1863 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
1865 struct e1000_phy_info *phy = &hw->phy;
1866 s32 ret_val = E1000_SUCCESS;
1869 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
1871 if (!(hw->phy.ops.read_reg))
1874 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1879 data &= ~IGP02E1000_PM_D3_LPLU;
1880 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1885 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1886 * during Dx states where the power conservation is most
1887 * important. During driver activity we should enable
1888 * SmartSpeed, so performance is maintained.
1890 if (phy->smart_speed == e1000_smart_speed_on) {
1891 ret_val = phy->ops.read_reg(hw,
1892 IGP01E1000_PHY_PORT_CONFIG,
1897 data |= IGP01E1000_PSCFR_SMART_SPEED;
1898 ret_val = phy->ops.write_reg(hw,
1899 IGP01E1000_PHY_PORT_CONFIG,
1903 } else if (phy->smart_speed == e1000_smart_speed_off) {
1904 ret_val = phy->ops.read_reg(hw,
1905 IGP01E1000_PHY_PORT_CONFIG,
1910 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1911 ret_val = phy->ops.write_reg(hw,
1912 IGP01E1000_PHY_PORT_CONFIG,
1917 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1918 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1919 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1920 data |= IGP02E1000_PM_D3_LPLU;
1921 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1926 /* When LPLU is enabled, we should disable SmartSpeed */
1927 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1932 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1933 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1942 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
1943 * @hw: pointer to the HW structure
1945 * Success returns 0, Failure returns 1
1947 * A downshift is detected by querying the PHY link health.
1949 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
1951 struct e1000_phy_info *phy = &hw->phy;
1953 u16 phy_data, offset, mask;
1955 DEBUGFUNC("e1000_check_downshift_generic");
1957 switch (phy->type) {
1959 case e1000_phy_gg82563:
1961 case e1000_phy_82578:
1962 offset = M88E1000_PHY_SPEC_STATUS;
1963 mask = M88E1000_PSSR_DOWNSHIFT;
1966 case e1000_phy_igp_2:
1967 case e1000_phy_igp_3:
1968 offset = IGP01E1000_PHY_LINK_HEALTH;
1969 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1972 /* speed downshift not supported */
1973 phy->speed_downgraded = FALSE;
1974 ret_val = E1000_SUCCESS;
1978 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1981 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE;
1988 * e1000_check_polarity_m88 - Checks the polarity.
1989 * @hw: pointer to the HW structure
1991 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1993 * Polarity is determined based on the PHY specific status register.
1995 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1997 struct e1000_phy_info *phy = &hw->phy;
2001 DEBUGFUNC("e1000_check_polarity_m88");
2003 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2006 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
2007 ? e1000_rev_polarity_reversed
2008 : e1000_rev_polarity_normal;
2014 * e1000_check_polarity_igp - Checks the polarity.
2015 * @hw: pointer to the HW structure
2017 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2019 * Polarity is determined based on the PHY port status register, and the
2020 * current speed (since there is no polarity at 100Mbps).
2022 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2024 struct e1000_phy_info *phy = &hw->phy;
2026 u16 data, offset, mask;
2028 DEBUGFUNC("e1000_check_polarity_igp");
2031 * Polarity is determined based on the speed of
2034 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2038 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2039 IGP01E1000_PSSR_SPEED_1000MBPS) {
2040 offset = IGP01E1000_PHY_PCS_INIT_REG;
2041 mask = IGP01E1000_PHY_POLARITY_MASK;
2044 * This really only applies to 10Mbps since
2045 * there is no polarity for 100Mbps (always 0).
2047 offset = IGP01E1000_PHY_PORT_STATUS;
2048 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
2051 ret_val = phy->ops.read_reg(hw, offset, &data);
2054 phy->cable_polarity = (data & mask)
2055 ? e1000_rev_polarity_reversed
2056 : e1000_rev_polarity_normal;
2063 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2064 * @hw: pointer to the HW structure
2066 * Polarity is determined on the polarity reversal feature being enabled.
2068 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2070 struct e1000_phy_info *phy = &hw->phy;
2072 u16 phy_data, offset, mask;
2074 DEBUGFUNC("e1000_check_polarity_ife");
2077 * Polarity is determined based on the reversal feature being enabled.
2079 if (phy->polarity_correction) {
2080 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2081 mask = IFE_PESC_POLARITY_REVERSED;
2083 offset = IFE_PHY_SPECIAL_CONTROL;
2084 mask = IFE_PSC_FORCE_POLARITY;
2087 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2090 phy->cable_polarity = (phy_data & mask)
2091 ? e1000_rev_polarity_reversed
2092 : e1000_rev_polarity_normal;
2098 * e1000_wait_autoneg_generic - Wait for auto-neg completion
2099 * @hw: pointer to the HW structure
2101 * Waits for auto-negotiation to complete or for the auto-negotiation time
2102 * limit to expire, which ever happens first.
2104 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
2106 s32 ret_val = E1000_SUCCESS;
2109 DEBUGFUNC("e1000_wait_autoneg_generic");
2111 if (!(hw->phy.ops.read_reg))
2112 return E1000_SUCCESS;
2114 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2115 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2116 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2119 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2122 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2128 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2135 * e1000_phy_has_link_generic - Polls PHY for link
2136 * @hw: pointer to the HW structure
2137 * @iterations: number of times to poll for link
2138 * @usec_interval: delay between polling attempts
2139 * @success: pointer to whether polling was successful or not
2141 * Polls the PHY status register for link, 'iterations' number of times.
2143 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2144 u32 usec_interval, bool *success)
2146 s32 ret_val = E1000_SUCCESS;
2149 DEBUGFUNC("e1000_phy_has_link_generic");
2151 if (!(hw->phy.ops.read_reg))
2152 return E1000_SUCCESS;
2154 for (i = 0; i < iterations; i++) {
2156 * Some PHYs require the PHY_STATUS register to be read
2157 * twice due to the link bit being sticky. No harm doing
2158 * it across the board.
2160 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2163 * If the first read fails, another entity may have
2164 * ownership of the resources, wait and try again to
2165 * see if they have relinquished the resources yet.
2167 usec_delay(usec_interval);
2168 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2171 if (phy_status & MII_SR_LINK_STATUS)
2173 if (usec_interval >= 1000)
2174 msec_delay_irq(usec_interval/1000);
2176 usec_delay(usec_interval);
2179 *success = (i < iterations) ? TRUE : FALSE;
2185 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2186 * @hw: pointer to the HW structure
2188 * Reads the PHY specific status register to retrieve the cable length
2189 * information. The cable length is determined by averaging the minimum and
2190 * maximum values to get the "average" cable length. The m88 PHY has four
2191 * possible cable length values, which are:
2192 * Register Value Cable Length
2196 * 3 110 - 140 meters
2199 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2201 struct e1000_phy_info *phy = &hw->phy;
2203 u16 phy_data, index;
2205 DEBUGFUNC("e1000_get_cable_length_m88");
2207 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2211 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2212 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2213 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
2214 ret_val = -E1000_ERR_PHY;
2218 phy->min_cable_length = e1000_m88_cable_length_table[index];
2219 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2221 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2227 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2229 struct e1000_phy_info *phy = &hw->phy;
2231 u16 phy_data, phy_data2, index, default_page, is_cm;
2233 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2235 switch (hw->phy.id) {
2236 case I347AT4_E_PHY_ID:
2237 /* Remember the original page select and set it to 7 */
2238 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2243 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2247 /* Get cable length from PHY Cable Diagnostics Control Reg */
2248 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2253 /* Check if the unit of cable length is meters or cm */
2254 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2258 is_cm = !(phy_data & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2260 /* Populate the phy structure with cable length in meters */
2261 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2262 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2263 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2265 /* Reset the page selec to its original value */
2266 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2271 case M88E1112_E_PHY_ID:
2272 /* Remember the original page select and set it to 5 */
2273 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2278 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2282 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2287 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2288 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2289 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
2290 ret_val = -E1000_ERR_PHY;
2294 phy->min_cable_length = e1000_m88_cable_length_table[index];
2295 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2297 phy->cable_length = (phy->min_cable_length +
2298 phy->max_cable_length) / 2;
2300 /* Reset the page select to its original value */
2301 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2308 ret_val = -E1000_ERR_PHY;
2317 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2318 * @hw: pointer to the HW structure
2320 * The automatic gain control (agc) normalizes the amplitude of the
2321 * received signal, adjusting for the attenuation produced by the
2322 * cable. By reading the AGC registers, which represent the
2323 * combination of coarse and fine gain value, the value can be put
2324 * into a lookup table to obtain the approximate cable length
2327 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2329 struct e1000_phy_info *phy = &hw->phy;
2330 s32 ret_val = E1000_SUCCESS;
2331 u16 phy_data, i, agc_value = 0;
2332 u16 cur_agc_index, max_agc_index = 0;
2333 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2334 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2335 IGP02E1000_PHY_AGC_A,
2336 IGP02E1000_PHY_AGC_B,
2337 IGP02E1000_PHY_AGC_C,
2338 IGP02E1000_PHY_AGC_D
2341 DEBUGFUNC("e1000_get_cable_length_igp_2");
2343 /* Read the AGC registers for all channels */
2344 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2345 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2350 * Getting bits 15:9, which represent the combination of
2351 * coarse and fine gain values. The result is a number
2352 * that can be put into the lookup table to obtain the
2353 * approximate cable length.
2355 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2356 IGP02E1000_AGC_LENGTH_MASK;
2358 /* Array index bound check. */
2359 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2360 (cur_agc_index == 0)) {
2361 ret_val = -E1000_ERR_PHY;
2365 /* Remove min & max AGC values from calculation. */
2366 if (e1000_igp_2_cable_length_table[min_agc_index] >
2367 e1000_igp_2_cable_length_table[cur_agc_index])
2368 min_agc_index = cur_agc_index;
2369 if (e1000_igp_2_cable_length_table[max_agc_index] <
2370 e1000_igp_2_cable_length_table[cur_agc_index])
2371 max_agc_index = cur_agc_index;
2373 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2376 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2377 e1000_igp_2_cable_length_table[max_agc_index]);
2378 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2380 /* Calculate cable length with the error range of +/- 10 meters. */
2381 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2382 (agc_value - IGP02E1000_AGC_RANGE) : 0;
2383 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2385 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2392 * e1000_get_phy_info_m88 - Retrieve PHY information
2393 * @hw: pointer to the HW structure
2395 * Valid for only copper links. Read the PHY status register (sticky read)
2396 * to verify that link is up. Read the PHY special control register to
2397 * determine the polarity and 10base-T extended distance. Read the PHY
2398 * special status register to determine MDI/MDIx and current speed. If
2399 * speed is 1000, then determine cable length, local and remote receiver.
2401 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2403 struct e1000_phy_info *phy = &hw->phy;
2408 DEBUGFUNC("e1000_get_phy_info_m88");
2410 if (phy->media_type != e1000_media_type_copper) {
2411 DEBUGOUT("Phy info is only valid for copper media\n");
2412 ret_val = -E1000_ERR_CONFIG;
2416 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2421 DEBUGOUT("Phy info is only valid if link is up\n");
2422 ret_val = -E1000_ERR_CONFIG;
2426 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2430 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
2433 ret_val = e1000_check_polarity_m88(hw);
2437 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2441 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE;
2443 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2444 ret_val = hw->phy.ops.get_cable_length(hw);
2448 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2452 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2453 ? e1000_1000t_rx_status_ok
2454 : e1000_1000t_rx_status_not_ok;
2456 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2457 ? e1000_1000t_rx_status_ok
2458 : e1000_1000t_rx_status_not_ok;
2460 /* Set values to "undefined" */
2461 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2462 phy->local_rx = e1000_1000t_rx_status_undefined;
2463 phy->remote_rx = e1000_1000t_rx_status_undefined;
2471 * e1000_get_phy_info_igp - Retrieve igp PHY information
2472 * @hw: pointer to the HW structure
2474 * Read PHY status to determine if link is up. If link is up, then
2475 * set/determine 10base-T extended distance and polarity correction. Read
2476 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2477 * determine on the cable length, local and remote receiver.
2479 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2481 struct e1000_phy_info *phy = &hw->phy;
2486 DEBUGFUNC("e1000_get_phy_info_igp");
2488 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2493 DEBUGOUT("Phy info is only valid if link is up\n");
2494 ret_val = -E1000_ERR_CONFIG;
2498 phy->polarity_correction = TRUE;
2500 ret_val = e1000_check_polarity_igp(hw);
2504 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2508 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE;
2510 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2511 IGP01E1000_PSSR_SPEED_1000MBPS) {
2512 ret_val = phy->ops.get_cable_length(hw);
2516 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2520 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2521 ? e1000_1000t_rx_status_ok
2522 : e1000_1000t_rx_status_not_ok;
2524 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2525 ? e1000_1000t_rx_status_ok
2526 : e1000_1000t_rx_status_not_ok;
2528 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2529 phy->local_rx = e1000_1000t_rx_status_undefined;
2530 phy->remote_rx = e1000_1000t_rx_status_undefined;
2538 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2539 * @hw: pointer to the HW structure
2541 * Populates "phy" structure with various feature states.
2543 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2545 struct e1000_phy_info *phy = &hw->phy;
2550 DEBUGFUNC("e1000_get_phy_info_ife");
2552 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2557 DEBUGOUT("Phy info is only valid if link is up\n");
2558 ret_val = -E1000_ERR_CONFIG;
2562 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2565 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
2568 if (phy->polarity_correction) {
2569 ret_val = e1000_check_polarity_ife(hw);
2573 /* Polarity is forced */
2574 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2575 ? e1000_rev_polarity_reversed
2576 : e1000_rev_polarity_normal;
2579 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2583 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE;
2585 /* The following parameters are undefined for 10/100 operation. */
2586 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2587 phy->local_rx = e1000_1000t_rx_status_undefined;
2588 phy->remote_rx = e1000_1000t_rx_status_undefined;
2595 * e1000_phy_sw_reset_generic - PHY software reset
2596 * @hw: pointer to the HW structure
2598 * Does a software reset of the PHY by reading the PHY control register and
2599 * setting/write the control register reset bit to the PHY.
2601 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2603 s32 ret_val = E1000_SUCCESS;
2606 DEBUGFUNC("e1000_phy_sw_reset_generic");
2608 if (!(hw->phy.ops.read_reg))
2611 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2615 phy_ctrl |= MII_CR_RESET;
2616 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2627 * e1000_phy_hw_reset_generic - PHY hardware reset
2628 * @hw: pointer to the HW structure
2630 * Verify the reset block is not blocking us from resetting. Acquire
2631 * semaphore (if necessary) and read/set/write the device control reset
2632 * bit in the PHY. Wait the appropriate delay time for the device to
2633 * reset and release the semaphore (if necessary).
2635 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2637 struct e1000_phy_info *phy = &hw->phy;
2638 s32 ret_val = E1000_SUCCESS;
2641 DEBUGFUNC("e1000_phy_hw_reset_generic");
2643 ret_val = phy->ops.check_reset_block(hw);
2645 ret_val = E1000_SUCCESS;
2649 ret_val = phy->ops.acquire(hw);
2653 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2654 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2655 E1000_WRITE_FLUSH(hw);
2657 usec_delay(phy->reset_delay_us);
2659 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2660 E1000_WRITE_FLUSH(hw);
2664 phy->ops.release(hw);
2666 ret_val = phy->ops.get_cfg_done(hw);
2673 * e1000_get_cfg_done_generic - Generic configuration done
2674 * @hw: pointer to the HW structure
2676 * Generic function to wait 10 milli-seconds for configuration to complete
2677 * and return success.
2679 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw)
2681 DEBUGFUNC("e1000_get_cfg_done_generic");
2685 return E1000_SUCCESS;
2689 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2690 * @hw: pointer to the HW structure
2692 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2694 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2696 DEBUGOUT("Running IGP 3 PHY init script\n");
2698 /* PHY init IGP 3 */
2699 /* Enable rise/fall, 10-mode work in class-A */
2700 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2701 /* Remove all caps from Replica path filter */
2702 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2703 /* Bias trimming for ADC, AFE and Driver (Default) */
2704 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2705 /* Increase Hybrid poly bias */
2706 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2707 /* Add 4% to Tx amplitude in Gig mode */
2708 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2709 /* Disable trimming (TTT) */
2710 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2711 /* Poly DC correction to 94.6% + 2% for all channels */
2712 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2713 /* ABS DC correction to 95.9% */
2714 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2715 /* BG temp curve trim */
2716 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2717 /* Increasing ADC OPAMP stage 1 currents to max */
2718 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2719 /* Force 1000 ( required for enabling PHY regs configuration) */
2720 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2721 /* Set upd_freq to 6 */
2722 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2724 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2725 /* Disable adaptive fixed FFE (Default) */
2726 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2727 /* Enable FFE hysteresis */
2728 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2729 /* Fixed FFE for short cable lengths */
2730 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2731 /* Fixed FFE for medium cable lengths */
2732 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2733 /* Fixed FFE for long cable lengths */
2734 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2735 /* Enable Adaptive Clip Threshold */
2736 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2737 /* AHT reset limit to 1 */
2738 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2739 /* Set AHT master delay to 127 msec */
2740 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2741 /* Set scan bits for AHT */
2742 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2743 /* Set AHT Preset bits */
2744 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2745 /* Change integ_factor of channel A to 3 */
2746 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2747 /* Change prop_factor of channels BCD to 8 */
2748 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2749 /* Change cg_icount + enable integbp for channels BCD */
2750 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2752 * Change cg_icount + enable integbp + change prop_factor_master
2753 * to 8 for channel A
2755 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2756 /* Disable AHT in Slave mode on channel A */
2757 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2759 * Enable LPLU and disable AN to 1000 in non-D0a states,
2762 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2763 /* Enable restart AN on an1000_dis change */
2764 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2765 /* Enable wh_fifo read clock in 10/100 modes */
2766 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2767 /* Restart AN, Speed selection is 1000 */
2768 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2770 return E1000_SUCCESS;
2774 * e1000_get_phy_type_from_id - Get PHY type from id
2775 * @phy_id: phy_id read from the phy
2777 * Returns the phy type from the id.
2779 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2781 enum e1000_phy_type phy_type = e1000_phy_unknown;
2784 case M88E1000_I_PHY_ID:
2785 case M88E1000_E_PHY_ID:
2786 case M88E1111_I_PHY_ID:
2787 case M88E1011_I_PHY_ID:
2788 case I347AT4_E_PHY_ID:
2789 case M88E1112_E_PHY_ID:
2790 phy_type = e1000_phy_m88;
2792 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2793 phy_type = e1000_phy_igp_2;
2795 case GG82563_E_PHY_ID:
2796 phy_type = e1000_phy_gg82563;
2798 case IGP03E1000_E_PHY_ID:
2799 phy_type = e1000_phy_igp_3;
2802 case IFE_PLUS_E_PHY_ID:
2803 case IFE_C_E_PHY_ID:
2804 phy_type = e1000_phy_ife;
2806 case BME1000_E_PHY_ID:
2807 case BME1000_E_PHY_ID_R2:
2808 phy_type = e1000_phy_bm;
2810 case I82578_E_PHY_ID:
2811 phy_type = e1000_phy_82578;
2813 case I82577_E_PHY_ID:
2814 phy_type = e1000_phy_82577;
2816 case I82579_E_PHY_ID:
2817 phy_type = e1000_phy_82579;
2819 case I82580_I_PHY_ID:
2820 phy_type = e1000_phy_82580;
2823 phy_type = e1000_phy_unknown;
2830 * e1000_determine_phy_address - Determines PHY address.
2831 * @hw: pointer to the HW structure
2833 * This uses a trial and error method to loop through possible PHY
2834 * addresses. It tests each by reading the PHY ID registers and
2835 * checking for a match.
2837 s32 e1000_determine_phy_address(struct e1000_hw *hw)
2839 s32 ret_val = -E1000_ERR_PHY_TYPE;
2842 enum e1000_phy_type phy_type = e1000_phy_unknown;
2844 hw->phy.id = phy_type;
2846 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2847 hw->phy.addr = phy_addr;
2851 e1000_get_phy_id(hw);
2852 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
2855 * If phy_type is valid, break - we found our
2858 if (phy_type != e1000_phy_unknown) {
2859 ret_val = E1000_SUCCESS;
2872 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2873 * @page: page to access
2875 * Returns the phy address for the page requested.
2877 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2881 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2888 * e1000_write_phy_reg_bm - Write BM PHY register
2889 * @hw: pointer to the HW structure
2890 * @offset: register offset to write to
2891 * @data: data to write at register offset
2893 * Acquires semaphore, if necessary, then writes the data to PHY register
2894 * at the offset. Release any acquired semaphores before exiting.
2896 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2899 u32 page = offset >> IGP_PAGE_SHIFT;
2901 DEBUGFUNC("e1000_write_phy_reg_bm");
2903 ret_val = hw->phy.ops.acquire(hw);
2907 /* Page 800 works differently than the rest so it has its own func */
2908 if (page == BM_WUC_PAGE) {
2909 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2914 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2916 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2917 u32 page_shift, page_select;
2920 * Page select is register 31 for phy address 1 and 22 for
2921 * phy address 2 and 3. Page select is shifted only for
2924 if (hw->phy.addr == 1) {
2925 page_shift = IGP_PAGE_SHIFT;
2926 page_select = IGP01E1000_PHY_PAGE_SELECT;
2929 page_select = BM_PHY_PAGE_SELECT;
2932 /* Page is shifted left, PHY expects (page x 32) */
2933 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
2934 (page << page_shift));
2939 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2943 hw->phy.ops.release(hw);
2948 * e1000_read_phy_reg_bm - Read BM PHY register
2949 * @hw: pointer to the HW structure
2950 * @offset: register offset to be read
2951 * @data: pointer to the read data
2953 * Acquires semaphore, if necessary, then reads the PHY register at offset
2954 * and storing the retrieved information in data. Release any acquired
2955 * semaphores before exiting.
2957 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2960 u32 page = offset >> IGP_PAGE_SHIFT;
2962 DEBUGFUNC("e1000_read_phy_reg_bm");
2964 ret_val = hw->phy.ops.acquire(hw);
2968 /* Page 800 works differently than the rest so it has its own func */
2969 if (page == BM_WUC_PAGE) {
2970 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2975 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2977 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2978 u32 page_shift, page_select;
2981 * Page select is register 31 for phy address 1 and 22 for
2982 * phy address 2 and 3. Page select is shifted only for
2985 if (hw->phy.addr == 1) {
2986 page_shift = IGP_PAGE_SHIFT;
2987 page_select = IGP01E1000_PHY_PAGE_SELECT;
2990 page_select = BM_PHY_PAGE_SELECT;
2993 /* Page is shifted left, PHY expects (page x 32) */
2994 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
2995 (page << page_shift));
3000 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3003 hw->phy.ops.release(hw);
3008 * e1000_read_phy_reg_bm2 - Read BM PHY register
3009 * @hw: pointer to the HW structure
3010 * @offset: register offset to be read
3011 * @data: pointer to the read data
3013 * Acquires semaphore, if necessary, then reads the PHY register at offset
3014 * and storing the retrieved information in data. Release any acquired
3015 * semaphores before exiting.
3017 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
3020 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3022 DEBUGFUNC("e1000_write_phy_reg_bm2");
3024 ret_val = hw->phy.ops.acquire(hw);
3028 /* Page 800 works differently than the rest so it has its own func */
3029 if (page == BM_WUC_PAGE) {
3030 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3037 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3039 /* Page is shifted left, PHY expects (page x 32) */
3040 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3047 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3050 hw->phy.ops.release(hw);
3055 * e1000_write_phy_reg_bm2 - Write BM PHY register
3056 * @hw: pointer to the HW structure
3057 * @offset: register offset to write to
3058 * @data: data to write at register offset
3060 * Acquires semaphore, if necessary, then writes the data to PHY register
3061 * at the offset. Release any acquired semaphores before exiting.
3063 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
3066 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3068 DEBUGFUNC("e1000_write_phy_reg_bm2");
3070 ret_val = hw->phy.ops.acquire(hw);
3074 /* Page 800 works differently than the rest so it has its own func */
3075 if (page == BM_WUC_PAGE) {
3076 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3083 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3084 /* Page is shifted left, PHY expects (page x 32) */
3085 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3092 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3096 hw->phy.ops.release(hw);
3101 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register
3102 * @hw: pointer to the HW structure
3103 * @offset: register offset to be read or written
3104 * @data: pointer to the data to read or write
3105 * @read: determines if operation is read or write
3107 * Acquires semaphore, if necessary, then reads the PHY register at offset
3108 * and storing the retrieved information in data. Release any acquired
3109 * semaphores before exiting. Note that procedure to read the wakeup
3110 * registers are different. It works as such:
3111 * 1) Set page 769, register 17, bit 2 = 1
3112 * 2) Set page to 800 for host (801 if we were manageability)
3113 * 3) Write the address using the address opcode (0x11)
3114 * 4) Read or write the data using the data opcode (0x12)
3115 * 5) Restore 769_17.2 to its original value
3117 * Assumes semaphore already acquired.
3119 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
3120 u16 *data, bool read)
3123 u16 reg = BM_PHY_REG_NUM(offset);
3126 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
3128 /* Gig must be disabled for MDIO accesses to page 800 */
3129 if ((hw->mac.type == e1000_pchlan) &&
3130 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
3131 DEBUGOUT("Attempting to access page 800 while gig enabled.\n");
3133 /* All operations in this function are phy address 1 */
3137 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3138 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3140 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg);
3142 DEBUGOUT("Could not read PHY page 769\n");
3146 /* First clear bit 4 to avoid a power state change */
3147 phy_reg &= ~(BM_WUC_HOST_WU_BIT);
3148 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3150 DEBUGOUT("Could not clear PHY page 769 bit 4\n");
3154 /* Write bit 2 = 1, and clear bit 4 to 769_17 */
3155 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG,
3156 phy_reg | BM_WUC_ENABLE_BIT);
3158 DEBUGOUT("Could not write PHY page 769 bit 2\n");
3162 /* Select page 800 */
3163 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3164 (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3166 /* Write the page 800 offset value using opcode 0x11 */
3167 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3169 DEBUGOUT("Could not write address opcode to page 800\n");
3174 /* Read the page 800 value using opcode 0x12 */
3175 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3178 /* Write the page 800 value using opcode 0x12 */
3179 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3184 DEBUGOUT("Could not access data value from page 800\n");
3189 * Restore 769_17.2 to its original value
3192 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3193 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3195 /* Clear 769_17.2 */
3196 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3198 DEBUGOUT("Could not clear PHY page 769 bit 2\n");
3207 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3208 * @hw: pointer to the HW structure
3210 * In the case of a PHY power down to save power, or to turn off link during a
3211 * driver unload, or wake on lan is not enabled, restore the link to previous
3214 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3218 /* The PHY will retain its settings across a power down/up cycle */
3219 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3220 mii_reg &= ~MII_CR_POWER_DOWN;
3221 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3225 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3226 * @hw: pointer to the HW structure
3228 * In the case of a PHY power down to save power, or to turn off link during a
3229 * driver unload, or wake on lan is not enabled, restore the link to previous
3232 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3236 /* The PHY will retain its settings across a power down/up cycle */
3237 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3238 mii_reg |= MII_CR_POWER_DOWN;
3239 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3244 * __e1000_read_phy_reg_hv - Read HV PHY register
3245 * @hw: pointer to the HW structure
3246 * @offset: register offset to be read
3247 * @data: pointer to the read data
3248 * @locked: semaphore has already been acquired or not
3250 * Acquires semaphore, if necessary, then reads the PHY register at offset
3251 * and stores the retrieved information in data. Release any acquired
3252 * semaphore before exiting.
3254 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3258 u16 page = BM_PHY_REG_PAGE(offset);
3259 u16 reg = BM_PHY_REG_NUM(offset);
3261 DEBUGFUNC("__e1000_read_phy_reg_hv");
3264 ret_val = hw->phy.ops.acquire(hw);
3269 /* Page 800 works differently than the rest so it has its own func */
3270 if (page == BM_WUC_PAGE) {
3271 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
3276 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3277 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3282 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3284 if (page == HV_INTC_FC_PAGE_START)
3287 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3288 u32 phy_addr = hw->phy.addr;
3292 /* Page is shifted left, PHY expects (page x 32) */
3293 ret_val = e1000_write_phy_reg_mdic(hw,
3294 IGP01E1000_PHY_PAGE_SELECT,
3295 (page << IGP_PAGE_SHIFT));
3296 hw->phy.addr = phy_addr;
3302 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3306 hw->phy.ops.release(hw);
3312 * e1000_read_phy_reg_hv - Read HV PHY register
3313 * @hw: pointer to the HW structure
3314 * @offset: register offset to be read
3315 * @data: pointer to the read data
3317 * Acquires semaphore then reads the PHY register at offset and stores
3318 * the retrieved information in data. Release the acquired semaphore
3321 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3323 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE);
3327 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3328 * @hw: pointer to the HW structure
3329 * @offset: register offset to be read
3330 * @data: pointer to the read data
3332 * Reads the PHY register at offset and stores the retrieved information
3333 * in data. Assumes semaphore already acquired.
3335 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3337 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE);
3341 * __e1000_write_phy_reg_hv - Write HV PHY register
3342 * @hw: pointer to the HW structure
3343 * @offset: register offset to write to
3344 * @data: data to write at register offset
3345 * @locked: semaphore has already been acquired or not
3347 * Acquires semaphore, if necessary, then writes the data to PHY register
3348 * at the offset. Release any acquired semaphores before exiting.
3350 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3354 u16 page = BM_PHY_REG_PAGE(offset);
3355 u16 reg = BM_PHY_REG_NUM(offset);
3357 DEBUGFUNC("__e1000_write_phy_reg_hv");
3360 ret_val = hw->phy.ops.acquire(hw);
3365 /* Page 800 works differently than the rest so it has its own func */
3366 if (page == BM_WUC_PAGE) {
3367 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
3372 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3373 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3378 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3380 if (page == HV_INTC_FC_PAGE_START)
3384 * Workaround MDIO accesses being disabled after entering IEEE Power
3385 * Down (whenever bit 11 of the PHY Control register is set)
3387 if ((hw->phy.type == e1000_phy_82578) &&
3388 (hw->phy.revision >= 1) &&
3389 (hw->phy.addr == 2) &&
3390 ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
3391 (data & (1 << 11))) {
3393 ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3,
3399 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3400 u32 phy_addr = hw->phy.addr;
3404 /* Page is shifted left, PHY expects (page x 32) */
3405 ret_val = e1000_write_phy_reg_mdic(hw,
3406 IGP01E1000_PHY_PAGE_SELECT,
3407 (page << IGP_PAGE_SHIFT));
3408 hw->phy.addr = phy_addr;
3414 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3419 hw->phy.ops.release(hw);
3425 * e1000_write_phy_reg_hv - Write HV PHY register
3426 * @hw: pointer to the HW structure
3427 * @offset: register offset to write to
3428 * @data: data to write at register offset
3430 * Acquires semaphore then writes the data to PHY register at the offset.
3431 * Release the acquired semaphores before exiting.
3433 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3435 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE);
3439 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3440 * @hw: pointer to the HW structure
3441 * @offset: register offset to write to
3442 * @data: data to write at register offset
3444 * Writes the data to PHY register at the offset. Assumes semaphore
3447 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3449 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE);
3453 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3454 * @page: page to be accessed
3456 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3460 if (page >= HV_INTC_FC_PAGE_START)
3467 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3468 * @hw: pointer to the HW structure
3469 * @offset: register offset to be read or written
3470 * @data: pointer to the data to be read or written
3471 * @read: determines if operation is read or written
3473 * Reads the PHY register at offset and stores the retreived information
3474 * in data. Assumes semaphore already acquired. Note that the procedure
3475 * to read these regs uses the address port and data port to read/write.
3477 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3478 u16 *data, bool read)
3484 DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3486 /* This takes care of the difference with desktop vs mobile phy */
3487 addr_reg = (hw->phy.type == e1000_phy_82578) ?
3488 I82578_ADDR_REG : I82577_ADDR_REG;
3489 data_reg = addr_reg + 1;
3491 /* All operations in this function are phy address 2 */
3494 /* masking with 0x3F to remove the page from offset */
3495 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3497 DEBUGOUT("Could not write PHY the HV address register\n");
3501 /* Read or write the data value next */
3503 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3505 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3508 DEBUGOUT("Could not read data value from HV data register\n");
3517 * e1000_link_stall_workaround_hv - Si workaround
3518 * @hw: pointer to the HW structure
3520 * This function works around a Si bug where the link partner can get
3521 * a link up indication before the PHY does. If small packets are sent
3522 * by the link partner they can be placed in the packet buffer without
3523 * being properly accounted for by the PHY and will stall preventing
3524 * further packets from being received. The workaround is to clear the
3525 * packet buffer after the PHY detects link up.
3527 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3529 s32 ret_val = E1000_SUCCESS;
3532 DEBUGFUNC("e1000_link_stall_workaround_hv");
3534 if (hw->phy.type != e1000_phy_82578)
3537 /* Do not apply workaround if in PHY loopback bit 14 set */
3538 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3539 if (data & PHY_CONTROL_LB)
3542 /* check if link is up and at 1Gbps */
3543 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3547 data &= BM_CS_STATUS_LINK_UP |
3548 BM_CS_STATUS_RESOLVED |
3549 BM_CS_STATUS_SPEED_MASK;
3551 if (data != (BM_CS_STATUS_LINK_UP |
3552 BM_CS_STATUS_RESOLVED |
3553 BM_CS_STATUS_SPEED_1000))
3558 /* flush the packets in the fifo buffer */
3559 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3560 HV_MUX_DATA_CTRL_GEN_TO_MAC |
3561 HV_MUX_DATA_CTRL_FORCE_SPEED);
3565 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3566 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3573 * e1000_check_polarity_82577 - Checks the polarity.
3574 * @hw: pointer to the HW structure
3576 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3578 * Polarity is determined based on the PHY specific status register.
3580 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3582 struct e1000_phy_info *phy = &hw->phy;
3586 DEBUGFUNC("e1000_check_polarity_82577");
3588 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3591 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
3592 ? e1000_rev_polarity_reversed
3593 : e1000_rev_polarity_normal;
3599 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3600 * @hw: pointer to the HW structure
3602 * Calls the PHY setup function to force speed and duplex.
3604 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3606 struct e1000_phy_info *phy = &hw->phy;
3611 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3613 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3617 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3619 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3625 if (phy->autoneg_wait_to_complete) {
3626 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3628 ret_val = e1000_phy_has_link_generic(hw,
3636 DEBUGOUT("Link taking longer than expected.\n");
3639 ret_val = e1000_phy_has_link_generic(hw,
3652 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3653 * @hw: pointer to the HW structure
3655 * Read PHY status to determine if link is up. If link is up, then
3656 * set/determine 10base-T extended distance and polarity correction. Read
3657 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3658 * determine on the cable length, local and remote receiver.
3660 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3662 struct e1000_phy_info *phy = &hw->phy;
3667 DEBUGFUNC("e1000_get_phy_info_82577");
3669 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3674 DEBUGOUT("Phy info is only valid if link is up\n");
3675 ret_val = -E1000_ERR_CONFIG;
3679 phy->polarity_correction = TRUE;
3681 ret_val = e1000_check_polarity_82577(hw);
3685 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3689 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? TRUE : FALSE;
3691 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3692 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3693 ret_val = hw->phy.ops.get_cable_length(hw);
3697 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3701 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3702 ? e1000_1000t_rx_status_ok
3703 : e1000_1000t_rx_status_not_ok;
3705 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3706 ? e1000_1000t_rx_status_ok
3707 : e1000_1000t_rx_status_not_ok;
3709 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3710 phy->local_rx = e1000_1000t_rx_status_undefined;
3711 phy->remote_rx = e1000_1000t_rx_status_undefined;
3719 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3720 * @hw: pointer to the HW structure
3722 * Reads the diagnostic status register and verifies result is valid before
3723 * placing it in the phy_cable_length field.
3725 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3727 struct e1000_phy_info *phy = &hw->phy;
3729 u16 phy_data, length;
3731 DEBUGFUNC("e1000_get_cable_length_82577");
3733 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3737 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3738 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
3740 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3741 ret_val = -E1000_ERR_PHY;
3743 phy->cable_length = length;