1 /******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ******************************************************************************/
35 #include "e1000_api.h"
37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read, bool page_set);
40 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
42 u16 *data, bool read);
44 /* Cable length tables */
45 static const u16 e1000_m88_cable_length_table[] = {
46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
48 (sizeof(e1000_m88_cable_length_table) / \
49 sizeof(e1000_m88_cable_length_table[0]))
51 static const u16 e1000_igp_2_cable_length_table[] = {
52 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
53 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
54 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
55 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
56 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
57 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
58 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
60 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
61 (sizeof(e1000_igp_2_cable_length_table) / \
62 sizeof(e1000_igp_2_cable_length_table[0]))
65 * e1000_init_phy_ops_generic - Initialize PHY function pointers
66 * @hw: pointer to the HW structure
68 * Setups up the function pointers to no-op functions
70 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
72 struct e1000_phy_info *phy = &hw->phy;
73 DEBUGFUNC("e1000_init_phy_ops_generic");
75 /* Initialize function pointers */
76 phy->ops.init_params = e1000_null_ops_generic;
77 phy->ops.acquire = e1000_null_ops_generic;
78 phy->ops.check_polarity = e1000_null_ops_generic;
79 phy->ops.check_reset_block = e1000_null_ops_generic;
80 phy->ops.commit = e1000_null_ops_generic;
81 phy->ops.force_speed_duplex = e1000_null_ops_generic;
82 phy->ops.get_cfg_done = e1000_null_ops_generic;
83 phy->ops.get_cable_length = e1000_null_ops_generic;
84 phy->ops.get_info = e1000_null_ops_generic;
85 phy->ops.set_page = e1000_null_set_page;
86 phy->ops.read_reg = e1000_null_read_reg;
87 phy->ops.read_reg_locked = e1000_null_read_reg;
88 phy->ops.read_reg_page = e1000_null_read_reg;
89 phy->ops.release = e1000_null_phy_generic;
90 phy->ops.reset = e1000_null_ops_generic;
91 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
92 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
93 phy->ops.write_reg = e1000_null_write_reg;
94 phy->ops.write_reg_locked = e1000_null_write_reg;
95 phy->ops.write_reg_page = e1000_null_write_reg;
96 phy->ops.power_up = e1000_null_phy_generic;
97 phy->ops.power_down = e1000_null_phy_generic;
98 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
99 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
100 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
104 * e1000_null_set_page - No-op function, return 0
105 * @hw: pointer to the HW structure
107 s32 e1000_null_set_page(struct e1000_hw *hw, u16 data)
109 DEBUGFUNC("e1000_null_set_page");
110 return E1000_SUCCESS;
114 * e1000_null_read_reg - No-op function, return 0
115 * @hw: pointer to the HW structure
117 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data)
119 DEBUGFUNC("e1000_null_read_reg");
120 return E1000_SUCCESS;
124 * e1000_null_phy_generic - No-op function, return void
125 * @hw: pointer to the HW structure
127 void e1000_null_phy_generic(struct e1000_hw *hw)
129 DEBUGFUNC("e1000_null_phy_generic");
134 * e1000_null_lplu_state - No-op function, return 0
135 * @hw: pointer to the HW structure
137 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active)
139 DEBUGFUNC("e1000_null_lplu_state");
140 return E1000_SUCCESS;
144 * e1000_null_write_reg - No-op function, return 0
145 * @hw: pointer to the HW structure
147 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data)
149 DEBUGFUNC("e1000_null_write_reg");
150 return E1000_SUCCESS;
154 * e1000_read_i2c_byte_null - No-op function, return 0
155 * @hw: pointer to hardware structure
156 * @byte_offset: byte offset to write
157 * @dev_addr: device address
158 * @data: data value read
161 s32 e1000_read_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,
162 u8 dev_addr, u8 *data)
164 DEBUGFUNC("e1000_read_i2c_byte_null");
165 return E1000_SUCCESS;
169 * e1000_write_i2c_byte_null - No-op function, return 0
170 * @hw: pointer to hardware structure
171 * @byte_offset: byte offset to write
172 * @dev_addr: device address
173 * @data: data value to write
176 s32 e1000_write_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,
177 u8 dev_addr, u8 data)
179 DEBUGFUNC("e1000_write_i2c_byte_null");
180 return E1000_SUCCESS;
184 * e1000_check_reset_block_generic - Check if PHY reset is blocked
185 * @hw: pointer to the HW structure
187 * Read the PHY management control register and check whether a PHY reset
188 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
189 * return E1000_BLK_PHY_RESET (12).
191 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
195 DEBUGFUNC("e1000_check_reset_block");
197 manc = E1000_READ_REG(hw, E1000_MANC);
199 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
200 E1000_BLK_PHY_RESET : E1000_SUCCESS;
204 * e1000_get_phy_id - Retrieve the PHY ID and revision
205 * @hw: pointer to the HW structure
207 * Reads the PHY registers and stores the PHY ID and possibly the PHY
208 * revision in the hardware structure.
210 s32 e1000_get_phy_id(struct e1000_hw *hw)
212 struct e1000_phy_info *phy = &hw->phy;
213 s32 ret_val = E1000_SUCCESS;
217 DEBUGFUNC("e1000_get_phy_id");
219 if (!phy->ops.read_reg)
220 return E1000_SUCCESS;
222 while (retry_count < 2) {
223 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
227 phy->id = (u32)(phy_id << 16);
229 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
233 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
234 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
236 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
237 return E1000_SUCCESS;
242 return E1000_SUCCESS;
246 * e1000_phy_reset_dsp_generic - Reset PHY DSP
247 * @hw: pointer to the HW structure
249 * Reset the digital signal processor.
251 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
255 DEBUGFUNC("e1000_phy_reset_dsp_generic");
257 if (!hw->phy.ops.write_reg)
258 return E1000_SUCCESS;
260 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
264 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
268 * e1000_read_phy_reg_mdic - Read MDI control register
269 * @hw: pointer to the HW structure
270 * @offset: register offset to be read
271 * @data: pointer to the read data
273 * Reads the MDI control register in the PHY at offset and stores the
274 * information read to data.
276 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
278 struct e1000_phy_info *phy = &hw->phy;
281 DEBUGFUNC("e1000_read_phy_reg_mdic");
283 if (offset > MAX_PHY_REG_ADDRESS) {
284 DEBUGOUT1("PHY Address %d is out of range\n", offset);
285 return -E1000_ERR_PARAM;
289 * Set up Op-code, Phy Address, and register offset in the MDI
290 * Control register. The MAC will take care of interfacing with the
291 * PHY to retrieve the desired data.
293 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
294 (phy->addr << E1000_MDIC_PHY_SHIFT) |
295 (E1000_MDIC_OP_READ));
297 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
300 * Poll the ready bit to see if the MDI read completed
301 * Increasing the time out as testing showed failures with
304 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
306 mdic = E1000_READ_REG(hw, E1000_MDIC);
307 if (mdic & E1000_MDIC_READY)
310 if (!(mdic & E1000_MDIC_READY)) {
311 DEBUGOUT("MDI Read did not complete\n");
312 return -E1000_ERR_PHY;
314 if (mdic & E1000_MDIC_ERROR) {
315 DEBUGOUT("MDI Error\n");
316 return -E1000_ERR_PHY;
321 * Allow some time after each MDIC transaction to avoid
322 * reading duplicate data in the next MDIC transaction.
324 if (hw->mac.type == e1000_pch2lan)
327 return E1000_SUCCESS;
331 * e1000_write_phy_reg_mdic - Write MDI control register
332 * @hw: pointer to the HW structure
333 * @offset: register offset to write to
334 * @data: data to write to register at offset
336 * Writes data to MDI control register in the PHY at offset.
338 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
340 struct e1000_phy_info *phy = &hw->phy;
343 DEBUGFUNC("e1000_write_phy_reg_mdic");
345 if (offset > MAX_PHY_REG_ADDRESS) {
346 DEBUGOUT1("PHY Address %d is out of range\n", offset);
347 return -E1000_ERR_PARAM;
351 * Set up Op-code, Phy Address, and register offset in the MDI
352 * Control register. The MAC will take care of interfacing with the
353 * PHY to retrieve the desired data.
355 mdic = (((u32)data) |
356 (offset << E1000_MDIC_REG_SHIFT) |
357 (phy->addr << E1000_MDIC_PHY_SHIFT) |
358 (E1000_MDIC_OP_WRITE));
360 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
363 * Poll the ready bit to see if the MDI read completed
364 * Increasing the time out as testing showed failures with
367 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
369 mdic = E1000_READ_REG(hw, E1000_MDIC);
370 if (mdic & E1000_MDIC_READY)
373 if (!(mdic & E1000_MDIC_READY)) {
374 DEBUGOUT("MDI Write did not complete\n");
375 return -E1000_ERR_PHY;
377 if (mdic & E1000_MDIC_ERROR) {
378 DEBUGOUT("MDI Error\n");
379 return -E1000_ERR_PHY;
383 * Allow some time after each MDIC transaction to avoid
384 * reading duplicate data in the next MDIC transaction.
386 if (hw->mac.type == e1000_pch2lan)
389 return E1000_SUCCESS;
393 * e1000_read_phy_reg_i2c - Read PHY register using i2c
394 * @hw: pointer to the HW structure
395 * @offset: register offset to be read
396 * @data: pointer to the read data
398 * Reads the PHY register at offset using the i2c interface and stores the
399 * retrieved information in data.
401 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
403 struct e1000_phy_info *phy = &hw->phy;
406 DEBUGFUNC("e1000_read_phy_reg_i2c");
409 * Set up Op-code, Phy Address, and register address in the I2CCMD
410 * register. The MAC will take care of interfacing with the
411 * PHY to retrieve the desired data.
413 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
414 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
415 (E1000_I2CCMD_OPCODE_READ));
417 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
419 /* Poll the ready bit to see if the I2C read completed */
420 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
422 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
423 if (i2ccmd & E1000_I2CCMD_READY)
426 if (!(i2ccmd & E1000_I2CCMD_READY)) {
427 DEBUGOUT("I2CCMD Read did not complete\n");
428 return -E1000_ERR_PHY;
430 if (i2ccmd & E1000_I2CCMD_ERROR) {
431 DEBUGOUT("I2CCMD Error bit set\n");
432 return -E1000_ERR_PHY;
435 /* Need to byte-swap the 16-bit value. */
436 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
438 return E1000_SUCCESS;
442 * e1000_write_phy_reg_i2c - Write PHY register using i2c
443 * @hw: pointer to the HW structure
444 * @offset: register offset to write to
445 * @data: data to write at register offset
447 * Writes the data to PHY register at the offset using the i2c interface.
449 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
451 struct e1000_phy_info *phy = &hw->phy;
453 u16 phy_data_swapped;
455 DEBUGFUNC("e1000_write_phy_reg_i2c");
457 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
458 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
459 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
461 return -E1000_ERR_CONFIG;
464 /* Swap the data bytes for the I2C interface */
465 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
468 * Set up Op-code, Phy Address, and register address in the I2CCMD
469 * register. The MAC will take care of interfacing with the
470 * PHY to retrieve the desired data.
472 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
473 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
474 E1000_I2CCMD_OPCODE_WRITE |
477 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
479 /* Poll the ready bit to see if the I2C read completed */
480 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
482 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
483 if (i2ccmd & E1000_I2CCMD_READY)
486 if (!(i2ccmd & E1000_I2CCMD_READY)) {
487 DEBUGOUT("I2CCMD Write did not complete\n");
488 return -E1000_ERR_PHY;
490 if (i2ccmd & E1000_I2CCMD_ERROR) {
491 DEBUGOUT("I2CCMD Error bit set\n");
492 return -E1000_ERR_PHY;
495 return E1000_SUCCESS;
499 * e1000_read_sfp_data_byte - Reads SFP module data.
500 * @hw: pointer to the HW structure
501 * @offset: byte location offset to be read
502 * @data: read data buffer pointer
504 * Reads one byte from SFP module data stored
505 * in SFP resided EEPROM memory or SFP diagnostic area.
506 * Function should be called with
507 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
508 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
511 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
517 DEBUGFUNC("e1000_read_sfp_data_byte");
519 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
520 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
521 return -E1000_ERR_PHY;
525 * Set up Op-code, EEPROM Address,in the I2CCMD
526 * register. The MAC will take care of interfacing with the
527 * EEPROM to retrieve the desired data.
529 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
530 E1000_I2CCMD_OPCODE_READ);
532 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
534 /* Poll the ready bit to see if the I2C read completed */
535 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
537 data_local = E1000_READ_REG(hw, E1000_I2CCMD);
538 if (data_local & E1000_I2CCMD_READY)
541 if (!(data_local & E1000_I2CCMD_READY)) {
542 DEBUGOUT("I2CCMD Read did not complete\n");
543 return -E1000_ERR_PHY;
545 if (data_local & E1000_I2CCMD_ERROR) {
546 DEBUGOUT("I2CCMD Error bit set\n");
547 return -E1000_ERR_PHY;
549 *data = (u8) data_local & 0xFF;
551 return E1000_SUCCESS;
555 * e1000_write_sfp_data_byte - Writes SFP module data.
556 * @hw: pointer to the HW structure
557 * @offset: byte location offset to write to
558 * @data: data to write
560 * Writes one byte to SFP module data stored
561 * in SFP resided EEPROM memory or SFP diagnostic area.
562 * Function should be called with
563 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
564 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
567 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
573 DEBUGFUNC("e1000_write_sfp_data_byte");
575 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
576 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
577 return -E1000_ERR_PHY;
580 * The programming interface is 16 bits wide
581 * so we need to read the whole word first
582 * then update appropriate byte lane and write
583 * the updated word back.
586 * Set up Op-code, EEPROM Address,in the I2CCMD
587 * register. The MAC will take care of interfacing
588 * with an EEPROM to write the data given.
590 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
591 E1000_I2CCMD_OPCODE_READ);
592 /* Set a command to read single word */
593 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
594 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
597 * Poll the ready bit to see if lastly
598 * launched I2C operation completed
600 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
601 if (i2ccmd & E1000_I2CCMD_READY) {
602 /* Check if this is READ or WRITE phase */
603 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
604 E1000_I2CCMD_OPCODE_READ) {
606 * Write the selected byte
607 * lane and update whole word
609 data_local = i2ccmd & 0xFF00;
612 E1000_I2CCMD_REG_ADDR_SHIFT) |
613 E1000_I2CCMD_OPCODE_WRITE | data_local);
614 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
620 if (!(i2ccmd & E1000_I2CCMD_READY)) {
621 DEBUGOUT("I2CCMD Write did not complete\n");
622 return -E1000_ERR_PHY;
624 if (i2ccmd & E1000_I2CCMD_ERROR) {
625 DEBUGOUT("I2CCMD Error bit set\n");
626 return -E1000_ERR_PHY;
628 return E1000_SUCCESS;
632 * e1000_read_phy_reg_m88 - Read m88 PHY register
633 * @hw: pointer to the HW structure
634 * @offset: register offset to be read
635 * @data: pointer to the read data
637 * Acquires semaphore, if necessary, then reads the PHY register at offset
638 * and storing the retrieved information in data. Release any acquired
639 * semaphores before exiting.
641 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
645 DEBUGFUNC("e1000_read_phy_reg_m88");
647 if (!hw->phy.ops.acquire)
648 return E1000_SUCCESS;
650 ret_val = hw->phy.ops.acquire(hw);
654 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
657 hw->phy.ops.release(hw);
663 * e1000_write_phy_reg_m88 - Write m88 PHY register
664 * @hw: pointer to the HW structure
665 * @offset: register offset to write to
666 * @data: data to write at register offset
668 * Acquires semaphore, if necessary, then writes the data to PHY register
669 * at the offset. Release any acquired semaphores before exiting.
671 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
675 DEBUGFUNC("e1000_write_phy_reg_m88");
677 if (!hw->phy.ops.acquire)
678 return E1000_SUCCESS;
680 ret_val = hw->phy.ops.acquire(hw);
684 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
687 hw->phy.ops.release(hw);
693 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
694 * @hw: pointer to the HW structure
695 * @page: page to set (shifted left when necessary)
697 * Sets PHY page required for PHY register access. Assumes semaphore is
698 * already acquired. Note, this function sets phy.addr to 1 so the caller
699 * must set it appropriately (if necessary) after this function returns.
701 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
703 DEBUGFUNC("e1000_set_page_igp");
705 DEBUGOUT1("Setting page 0x%x\n", page);
709 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
713 * __e1000_read_phy_reg_igp - Read igp PHY register
714 * @hw: pointer to the HW structure
715 * @offset: register offset to be read
716 * @data: pointer to the read data
717 * @locked: semaphore has already been acquired or not
719 * Acquires semaphore, if necessary, then reads the PHY register at offset
720 * and stores the retrieved information in data. Release any acquired
721 * semaphores before exiting.
723 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
726 s32 ret_val = E1000_SUCCESS;
728 DEBUGFUNC("__e1000_read_phy_reg_igp");
731 if (!hw->phy.ops.acquire)
732 return E1000_SUCCESS;
734 ret_val = hw->phy.ops.acquire(hw);
739 if (offset > MAX_PHY_MULTI_PAGE_REG)
740 ret_val = e1000_write_phy_reg_mdic(hw,
741 IGP01E1000_PHY_PAGE_SELECT,
744 ret_val = e1000_read_phy_reg_mdic(hw,
745 MAX_PHY_REG_ADDRESS & offset,
748 hw->phy.ops.release(hw);
754 * e1000_read_phy_reg_igp - Read igp PHY register
755 * @hw: pointer to the HW structure
756 * @offset: register offset to be read
757 * @data: pointer to the read data
759 * Acquires semaphore then reads the PHY register at offset and stores the
760 * retrieved information in data.
761 * Release the acquired semaphore before exiting.
763 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
765 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE);
769 * e1000_read_phy_reg_igp_locked - Read igp PHY register
770 * @hw: pointer to the HW structure
771 * @offset: register offset to be read
772 * @data: pointer to the read data
774 * Reads the PHY register at offset and stores the retrieved information
775 * in data. Assumes semaphore already acquired.
777 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
779 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE);
783 * e1000_write_phy_reg_igp - Write igp PHY register
784 * @hw: pointer to the HW structure
785 * @offset: register offset to write to
786 * @data: data to write at register offset
787 * @locked: semaphore has already been acquired or not
789 * Acquires semaphore, if necessary, then writes the data to PHY register
790 * at the offset. Release any acquired semaphores before exiting.
792 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
795 s32 ret_val = E1000_SUCCESS;
797 DEBUGFUNC("e1000_write_phy_reg_igp");
800 if (!hw->phy.ops.acquire)
801 return E1000_SUCCESS;
803 ret_val = hw->phy.ops.acquire(hw);
808 if (offset > MAX_PHY_MULTI_PAGE_REG)
809 ret_val = e1000_write_phy_reg_mdic(hw,
810 IGP01E1000_PHY_PAGE_SELECT,
813 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
817 hw->phy.ops.release(hw);
823 * e1000_write_phy_reg_igp - Write igp PHY register
824 * @hw: pointer to the HW structure
825 * @offset: register offset to write to
826 * @data: data to write at register offset
828 * Acquires semaphore then writes the data to PHY register
829 * at the offset. Release any acquired semaphores before exiting.
831 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
833 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE);
837 * e1000_write_phy_reg_igp_locked - Write igp PHY register
838 * @hw: pointer to the HW structure
839 * @offset: register offset to write to
840 * @data: data to write at register offset
842 * Writes the data to PHY register at the offset.
843 * Assumes semaphore already acquired.
845 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
847 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE);
851 * __e1000_read_kmrn_reg - Read kumeran register
852 * @hw: pointer to the HW structure
853 * @offset: register offset to be read
854 * @data: pointer to the read data
855 * @locked: semaphore has already been acquired or not
857 * Acquires semaphore, if necessary. Then reads the PHY register at offset
858 * using the kumeran interface. The information retrieved is stored in data.
859 * Release any acquired semaphores before exiting.
861 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
866 DEBUGFUNC("__e1000_read_kmrn_reg");
869 s32 ret_val = E1000_SUCCESS;
871 if (!hw->phy.ops.acquire)
872 return E1000_SUCCESS;
874 ret_val = hw->phy.ops.acquire(hw);
879 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
880 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
881 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
882 E1000_WRITE_FLUSH(hw);
886 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
887 *data = (u16)kmrnctrlsta;
890 hw->phy.ops.release(hw);
892 return E1000_SUCCESS;
896 * e1000_read_kmrn_reg_generic - Read kumeran register
897 * @hw: pointer to the HW structure
898 * @offset: register offset to be read
899 * @data: pointer to the read data
901 * Acquires semaphore then reads the PHY register at offset using the
902 * kumeran interface. The information retrieved is stored in data.
903 * Release the acquired semaphore before exiting.
905 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
907 return __e1000_read_kmrn_reg(hw, offset, data, FALSE);
911 * e1000_read_kmrn_reg_locked - Read kumeran register
912 * @hw: pointer to the HW structure
913 * @offset: register offset to be read
914 * @data: pointer to the read data
916 * Reads the PHY register at offset using the kumeran interface. The
917 * information retrieved is stored in data.
918 * Assumes semaphore already acquired.
920 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
922 return __e1000_read_kmrn_reg(hw, offset, data, TRUE);
926 * __e1000_write_kmrn_reg - Write kumeran register
927 * @hw: pointer to the HW structure
928 * @offset: register offset to write to
929 * @data: data to write at register offset
930 * @locked: semaphore has already been acquired or not
932 * Acquires semaphore, if necessary. Then write the data to PHY register
933 * at the offset using the kumeran interface. Release any acquired semaphores
936 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
941 DEBUGFUNC("e1000_write_kmrn_reg_generic");
944 s32 ret_val = E1000_SUCCESS;
946 if (!hw->phy.ops.acquire)
947 return E1000_SUCCESS;
949 ret_val = hw->phy.ops.acquire(hw);
954 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
955 E1000_KMRNCTRLSTA_OFFSET) | data;
956 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
957 E1000_WRITE_FLUSH(hw);
962 hw->phy.ops.release(hw);
964 return E1000_SUCCESS;
968 * e1000_write_kmrn_reg_generic - Write kumeran register
969 * @hw: pointer to the HW structure
970 * @offset: register offset to write to
971 * @data: data to write at register offset
973 * Acquires semaphore then writes the data to the PHY register at the offset
974 * using the kumeran interface. Release the acquired semaphore before exiting.
976 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
978 return __e1000_write_kmrn_reg(hw, offset, data, FALSE);
982 * e1000_write_kmrn_reg_locked - Write kumeran register
983 * @hw: pointer to the HW structure
984 * @offset: register offset to write to
985 * @data: data to write at register offset
987 * Write the data to PHY register at the offset using the kumeran interface.
988 * Assumes semaphore already acquired.
990 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
992 return __e1000_write_kmrn_reg(hw, offset, data, TRUE);
996 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
997 * @hw: pointer to the HW structure
999 * Sets up Master/slave mode
1001 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
1006 /* Resolve Master/Slave mode */
1007 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1011 /* load defaults for future use */
1012 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1013 ((phy_data & CR_1000T_MS_VALUE) ?
1014 e1000_ms_force_master :
1015 e1000_ms_force_slave) : e1000_ms_auto;
1017 switch (hw->phy.ms_type) {
1018 case e1000_ms_force_master:
1019 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1021 case e1000_ms_force_slave:
1022 phy_data |= CR_1000T_MS_ENABLE;
1023 phy_data &= ~(CR_1000T_MS_VALUE);
1026 phy_data &= ~CR_1000T_MS_ENABLE;
1032 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1036 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
1037 * @hw: pointer to the HW structure
1039 * Sets up Carrier-sense on Transmit and downshift values.
1041 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
1046 DEBUGFUNC("e1000_copper_link_setup_82577");
1048 if (hw->phy.type == e1000_phy_82580) {
1049 ret_val = hw->phy.ops.reset(hw);
1051 DEBUGOUT("Error resetting the PHY.\n");
1056 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1057 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1061 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1063 /* Enable downshift */
1064 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1066 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1070 /* Set MDI/MDIX mode */
1071 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1074 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
1077 * 0 - Auto (default)
1081 switch (hw->phy.mdix) {
1085 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
1089 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
1092 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1096 return e1000_set_master_slave_mode(hw);
1100 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1101 * @hw: pointer to the HW structure
1103 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1104 * and downshift values are set also.
1106 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1108 struct e1000_phy_info *phy = &hw->phy;
1112 DEBUGFUNC("e1000_copper_link_setup_m88");
1115 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1116 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1120 /* For BM PHY this bit is downshift enable */
1121 if (phy->type != e1000_phy_bm)
1122 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1126 * MDI/MDI-X = 0 (default)
1127 * 0 - Auto for all speeds
1130 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1132 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1134 switch (phy->mdix) {
1136 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1139 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1142 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1146 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1152 * disable_polarity_correction = 0 (default)
1153 * Automatic Correction for Reversed Cable Polarity
1157 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1158 if (phy->disable_polarity_correction)
1159 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1161 /* Enable downshift on BM (disabled by default) */
1162 if (phy->type == e1000_phy_bm) {
1163 /* For 82574/82583, first disable then enable downshift */
1164 if (phy->id == BME1000_E_PHY_ID_R2) {
1165 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
1166 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1170 /* Commit the changes. */
1171 ret_val = phy->ops.commit(hw);
1173 DEBUGOUT("Error committing the PHY changes\n");
1178 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
1181 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1185 if ((phy->type == e1000_phy_m88) &&
1186 (phy->revision < E1000_REVISION_4) &&
1187 (phy->id != BME1000_E_PHY_ID_R2)) {
1189 * Force TX_CLK in the Extended PHY Specific Control Register
1192 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1197 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1199 if ((phy->revision == E1000_REVISION_2) &&
1200 (phy->id == M88E1111_I_PHY_ID)) {
1201 /* 82573L PHY - set the downshift counter to 5x. */
1202 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1203 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1205 /* Configure Master and Slave downshift values */
1206 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1207 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1208 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1209 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1211 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1217 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1218 /* Set PHY page 0, register 29 to 0x0003 */
1219 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1223 /* Set PHY page 0, register 30 to 0x0000 */
1224 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1229 /* Commit the changes. */
1230 ret_val = phy->ops.commit(hw);
1232 DEBUGOUT("Error committing the PHY changes\n");
1236 if (phy->type == e1000_phy_82578) {
1237 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1242 /* 82578 PHY - set the downshift count to 1x. */
1243 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
1244 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
1245 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1251 if (phy->type == e1000_phy_i210) {
1252 ret_val = e1000_set_master_slave_mode(hw);
1257 return E1000_SUCCESS;
1261 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1262 * @hw: pointer to the HW structure
1264 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1265 * Also enables and sets the downshift parameters.
1267 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1269 struct e1000_phy_info *phy = &hw->phy;
1273 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1276 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1277 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1283 * MDI/MDI-X = 0 (default)
1284 * 0 - Auto for all speeds
1287 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1289 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1291 switch (phy->mdix) {
1293 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1296 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1299 /* M88E1112 does not support this mode) */
1300 if (phy->id != M88E1112_E_PHY_ID) {
1301 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1306 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1312 * disable_polarity_correction = 0 (default)
1313 * Automatic Correction for Reversed Cable Polarity
1317 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1318 if (phy->disable_polarity_correction)
1319 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1321 /* Enable downshift and setting it to X6 */
1322 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1323 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1324 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1326 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1330 /* Commit the changes. */
1331 ret_val = phy->ops.commit(hw);
1333 DEBUGOUT("Error committing the PHY changes\n");
1337 return E1000_SUCCESS;
1341 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1342 * @hw: pointer to the HW structure
1344 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1347 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1349 struct e1000_phy_info *phy = &hw->phy;
1353 DEBUGFUNC("e1000_copper_link_setup_igp");
1356 ret_val = hw->phy.ops.reset(hw);
1358 DEBUGOUT("Error resetting the PHY.\n");
1363 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1364 * timeout issues when LFS is enabled.
1369 * The NVM settings will configure LPLU in D3 for
1372 if (phy->type == e1000_phy_igp) {
1373 /* disable lplu d3 during driver init */
1374 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE);
1376 DEBUGOUT("Error Disabling LPLU D3\n");
1381 /* disable lplu d0 during driver init */
1382 if (hw->phy.ops.set_d0_lplu_state) {
1383 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE);
1385 DEBUGOUT("Error Disabling LPLU D0\n");
1389 /* Configure mdi-mdix settings */
1390 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1394 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1396 switch (phy->mdix) {
1398 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1401 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1405 data |= IGP01E1000_PSCR_AUTO_MDIX;
1408 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1412 /* set auto-master slave resolution settings */
1413 if (hw->mac.autoneg) {
1415 * when autonegotiation advertisement is only 1000Mbps then we
1416 * should disable SmartSpeed and enable Auto MasterSlave
1417 * resolution as hardware default.
1419 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1420 /* Disable SmartSpeed */
1421 ret_val = phy->ops.read_reg(hw,
1422 IGP01E1000_PHY_PORT_CONFIG,
1427 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1428 ret_val = phy->ops.write_reg(hw,
1429 IGP01E1000_PHY_PORT_CONFIG,
1434 /* Set auto Master/Slave resolution process */
1435 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1439 data &= ~CR_1000T_MS_ENABLE;
1440 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1445 ret_val = e1000_set_master_slave_mode(hw);
1452 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1453 * @hw: pointer to the HW structure
1455 * Reads the MII auto-neg advertisement register and/or the 1000T control
1456 * register and if the PHY is already setup for auto-negotiation, then
1457 * return successful. Otherwise, setup advertisement and flow control to
1458 * the appropriate values for the wanted auto-negotiation.
1460 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1462 struct e1000_phy_info *phy = &hw->phy;
1464 u16 mii_autoneg_adv_reg;
1465 u16 mii_1000t_ctrl_reg = 0;
1467 DEBUGFUNC("e1000_phy_setup_autoneg");
1469 phy->autoneg_advertised &= phy->autoneg_mask;
1471 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1472 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1476 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1477 /* Read the MII 1000Base-T Control Register (Address 9). */
1478 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1479 &mii_1000t_ctrl_reg);
1485 * Need to parse both autoneg_advertised and fc and set up
1486 * the appropriate PHY registers. First we will parse for
1487 * autoneg_advertised software override. Since we can advertise
1488 * a plethora of combinations, we need to check each bit
1493 * First we clear all the 10/100 mb speed bits in the Auto-Neg
1494 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1495 * the 1000Base-T Control Register (Address 9).
1497 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1498 NWAY_AR_100TX_HD_CAPS |
1499 NWAY_AR_10T_FD_CAPS |
1500 NWAY_AR_10T_HD_CAPS);
1501 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1503 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1505 /* Do we want to advertise 10 Mb Half Duplex? */
1506 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1507 DEBUGOUT("Advertise 10mb Half duplex\n");
1508 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1511 /* Do we want to advertise 10 Mb Full Duplex? */
1512 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1513 DEBUGOUT("Advertise 10mb Full duplex\n");
1514 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1517 /* Do we want to advertise 100 Mb Half Duplex? */
1518 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1519 DEBUGOUT("Advertise 100mb Half duplex\n");
1520 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1523 /* Do we want to advertise 100 Mb Full Duplex? */
1524 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1525 DEBUGOUT("Advertise 100mb Full duplex\n");
1526 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1529 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1530 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1531 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1533 /* Do we want to advertise 1000 Mb Full Duplex? */
1534 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1535 DEBUGOUT("Advertise 1000mb Full duplex\n");
1536 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1540 * Check for a software override of the flow control settings, and
1541 * setup the PHY advertisement registers accordingly. If
1542 * auto-negotiation is enabled, then software will have to set the
1543 * "PAUSE" bits to the correct value in the Auto-Negotiation
1544 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1547 * The possible values of the "fc" parameter are:
1548 * 0: Flow control is completely disabled
1549 * 1: Rx flow control is enabled (we can receive pause frames
1550 * but not send pause frames).
1551 * 2: Tx flow control is enabled (we can send pause frames
1552 * but we do not support receiving pause frames).
1553 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1554 * other: No software override. The flow control configuration
1555 * in the EEPROM is used.
1557 switch (hw->fc.current_mode) {
1560 * Flow control (Rx & Tx) is completely disabled by a
1561 * software over-ride.
1563 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1565 case e1000_fc_rx_pause:
1567 * Rx Flow control is enabled, and Tx Flow control is
1568 * disabled, by a software over-ride.
1570 * Since there really isn't a way to advertise that we are
1571 * capable of Rx Pause ONLY, we will advertise that we
1572 * support both symmetric and asymmetric Rx PAUSE. Later
1573 * (in e1000_config_fc_after_link_up) we will disable the
1574 * hw's ability to send PAUSE frames.
1576 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1578 case e1000_fc_tx_pause:
1580 * Tx Flow control is enabled, and Rx Flow control is
1581 * disabled, by a software over-ride.
1583 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1584 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1588 * Flow control (both Rx and Tx) is enabled by a software
1591 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1594 DEBUGOUT("Flow control param set incorrectly\n");
1595 return -E1000_ERR_CONFIG;
1598 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1602 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1604 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1605 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1606 mii_1000t_ctrl_reg);
1612 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1613 * @hw: pointer to the HW structure
1615 * Performs initial bounds checking on autoneg advertisement parameter, then
1616 * configure to advertise the full capability. Setup the PHY to autoneg
1617 * and restart the negotiation process between the link partner. If
1618 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1620 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1622 struct e1000_phy_info *phy = &hw->phy;
1626 DEBUGFUNC("e1000_copper_link_autoneg");
1629 * Perform some bounds checking on the autoneg advertisement
1632 phy->autoneg_advertised &= phy->autoneg_mask;
1635 * If autoneg_advertised is zero, we assume it was not defaulted
1636 * by the calling code so we set to advertise full capability.
1638 if (!phy->autoneg_advertised)
1639 phy->autoneg_advertised = phy->autoneg_mask;
1641 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1642 ret_val = e1000_phy_setup_autoneg(hw);
1644 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1647 DEBUGOUT("Restarting Auto-Neg\n");
1650 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1651 * the Auto Neg Restart bit in the PHY control register.
1653 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1657 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1658 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1663 * Does the user want to wait for Auto-Neg to complete here, or
1664 * check at a later time (for example, callback routine).
1666 if (phy->autoneg_wait_to_complete) {
1667 ret_val = hw->mac.ops.wait_autoneg(hw);
1669 DEBUGOUT("Error while waiting for autoneg to complete\n");
1674 hw->mac.get_link_status = TRUE;
1680 * e1000_setup_copper_link_generic - Configure copper link settings
1681 * @hw: pointer to the HW structure
1683 * Calls the appropriate function to configure the link for auto-neg or forced
1684 * speed and duplex. Then we check for link, once link is established calls
1685 * to configure collision distance and flow control are called. If link is
1686 * not established, we return -E1000_ERR_PHY (-2).
1688 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1693 DEBUGFUNC("e1000_setup_copper_link_generic");
1695 if (hw->mac.autoneg) {
1697 * Setup autoneg and flow control advertisement and perform
1700 ret_val = e1000_copper_link_autoneg(hw);
1705 * PHY will be set to 10H, 10F, 100H or 100F
1706 * depending on user settings.
1708 DEBUGOUT("Forcing Speed and Duplex\n");
1709 ret_val = hw->phy.ops.force_speed_duplex(hw);
1711 DEBUGOUT("Error Forcing Speed and Duplex\n");
1717 * Check link status. Wait up to 100 microseconds for link to become
1720 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1726 DEBUGOUT("Valid link established!!!\n");
1727 hw->mac.ops.config_collision_dist(hw);
1728 ret_val = e1000_config_fc_after_link_up_generic(hw);
1730 DEBUGOUT("Unable to establish link!!!\n");
1737 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1738 * @hw: pointer to the HW structure
1740 * Calls the PHY setup function to force speed and duplex. Clears the
1741 * auto-crossover to force MDI manually. Waits for link and returns
1742 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1744 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1746 struct e1000_phy_info *phy = &hw->phy;
1751 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1753 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1757 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1759 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1764 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1765 * forced whenever speed and duplex are forced.
1767 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1771 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1772 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1774 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1778 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1782 if (phy->autoneg_wait_to_complete) {
1783 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1785 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1791 DEBUGOUT("Link taking longer than expected.\n");
1794 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1802 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1803 * @hw: pointer to the HW structure
1805 * Calls the PHY setup function to force speed and duplex. Clears the
1806 * auto-crossover to force MDI manually. Resets the PHY to commit the
1807 * changes. If time expires while waiting for link up, we reset the DSP.
1808 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1809 * successful completion, else return corresponding error code.
1811 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1813 struct e1000_phy_info *phy = &hw->phy;
1818 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1821 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1822 * forced whenever speed and duplex are forced.
1824 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1828 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1829 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1833 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1835 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1839 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1841 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1845 /* Reset the phy to commit changes. */
1846 ret_val = hw->phy.ops.commit(hw);
1850 if (phy->autoneg_wait_to_complete) {
1851 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1853 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1859 bool reset_dsp = TRUE;
1861 switch (hw->phy.id) {
1862 case I347AT4_E_PHY_ID:
1863 case M88E1340M_E_PHY_ID:
1864 case M88E1112_E_PHY_ID:
1869 if (hw->phy.type != e1000_phy_m88)
1875 DEBUGOUT("Link taking longer than expected.\n");
1878 * We didn't get link.
1879 * Reset the DSP and cross our fingers.
1881 ret_val = phy->ops.write_reg(hw,
1882 M88E1000_PHY_PAGE_SELECT,
1886 ret_val = e1000_phy_reset_dsp_generic(hw);
1893 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1899 if (hw->phy.type != e1000_phy_m88)
1900 return E1000_SUCCESS;
1902 if (hw->phy.id == I347AT4_E_PHY_ID ||
1903 hw->phy.id == M88E1340M_E_PHY_ID ||
1904 hw->phy.id == M88E1112_E_PHY_ID)
1905 return E1000_SUCCESS;
1906 if (hw->phy.id == I210_I_PHY_ID)
1907 return E1000_SUCCESS;
1908 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1913 * Resetting the phy means we need to re-force TX_CLK in the
1914 * Extended PHY Specific Control Register to 25MHz clock from
1915 * the reset value of 2.5MHz.
1917 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1918 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1923 * In addition, we must re-enable CRS on Tx for both half and full
1926 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1930 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1931 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1937 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1938 * @hw: pointer to the HW structure
1940 * Forces the speed and duplex settings of the PHY.
1941 * This is a function pointer entry point only called by
1942 * PHY setup routines.
1944 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1946 struct e1000_phy_info *phy = &hw->phy;
1951 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1953 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1957 e1000_phy_force_speed_duplex_setup(hw, &data);
1959 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1963 /* Disable MDI-X support for 10/100 */
1964 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1968 data &= ~IFE_PMC_AUTO_MDIX;
1969 data &= ~IFE_PMC_FORCE_MDIX;
1971 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1975 DEBUGOUT1("IFE PMC: %X\n", data);
1979 if (phy->autoneg_wait_to_complete) {
1980 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1982 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1988 DEBUGOUT("Link taking longer than expected.\n");
1991 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1997 return E1000_SUCCESS;
2001 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
2002 * @hw: pointer to the HW structure
2003 * @phy_ctrl: pointer to current value of PHY_CONTROL
2005 * Forces speed and duplex on the PHY by doing the following: disable flow
2006 * control, force speed/duplex on the MAC, disable auto speed detection,
2007 * disable auto-negotiation, configure duplex, configure speed, configure
2008 * the collision distance, write configuration to CTRL register. The
2009 * caller must write to the PHY_CONTROL register for these settings to
2012 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
2014 struct e1000_mac_info *mac = &hw->mac;
2017 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
2019 /* Turn off flow control when forcing speed/duplex */
2020 hw->fc.current_mode = e1000_fc_none;
2022 /* Force speed/duplex on the mac */
2023 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2024 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2025 ctrl &= ~E1000_CTRL_SPD_SEL;
2027 /* Disable Auto Speed Detection */
2028 ctrl &= ~E1000_CTRL_ASDE;
2030 /* Disable autoneg on the phy */
2031 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
2033 /* Forcing Full or Half Duplex? */
2034 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
2035 ctrl &= ~E1000_CTRL_FD;
2036 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
2037 DEBUGOUT("Half Duplex\n");
2039 ctrl |= E1000_CTRL_FD;
2040 *phy_ctrl |= MII_CR_FULL_DUPLEX;
2041 DEBUGOUT("Full Duplex\n");
2044 /* Forcing 10mb or 100mb? */
2045 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
2046 ctrl |= E1000_CTRL_SPD_100;
2047 *phy_ctrl |= MII_CR_SPEED_100;
2048 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2049 DEBUGOUT("Forcing 100mb\n");
2051 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2052 *phy_ctrl |= MII_CR_SPEED_10;
2053 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2054 DEBUGOUT("Forcing 10mb\n");
2057 hw->mac.ops.config_collision_dist(hw);
2059 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2063 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
2064 * @hw: pointer to the HW structure
2065 * @active: boolean used to enable/disable lplu
2067 * Success returns 0, Failure returns 1
2069 * The low power link up (lplu) state is set to the power management level D3
2070 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
2071 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2072 * is used during Dx states where the power conservation is most important.
2073 * During driver activity, SmartSpeed should be enabled so performance is
2076 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
2078 struct e1000_phy_info *phy = &hw->phy;
2082 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
2084 if (!hw->phy.ops.read_reg)
2085 return E1000_SUCCESS;
2087 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2092 data &= ~IGP02E1000_PM_D3_LPLU;
2093 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2098 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
2099 * during Dx states where the power conservation is most
2100 * important. During driver activity we should enable
2101 * SmartSpeed, so performance is maintained.
2103 if (phy->smart_speed == e1000_smart_speed_on) {
2104 ret_val = phy->ops.read_reg(hw,
2105 IGP01E1000_PHY_PORT_CONFIG,
2110 data |= IGP01E1000_PSCFR_SMART_SPEED;
2111 ret_val = phy->ops.write_reg(hw,
2112 IGP01E1000_PHY_PORT_CONFIG,
2116 } else if (phy->smart_speed == e1000_smart_speed_off) {
2117 ret_val = phy->ops.read_reg(hw,
2118 IGP01E1000_PHY_PORT_CONFIG,
2123 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2124 ret_val = phy->ops.write_reg(hw,
2125 IGP01E1000_PHY_PORT_CONFIG,
2130 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2131 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2132 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2133 data |= IGP02E1000_PM_D3_LPLU;
2134 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2139 /* When LPLU is enabled, we should disable SmartSpeed */
2140 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2145 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2146 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2154 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
2155 * @hw: pointer to the HW structure
2157 * Success returns 0, Failure returns 1
2159 * A downshift is detected by querying the PHY link health.
2161 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
2163 struct e1000_phy_info *phy = &hw->phy;
2165 u16 phy_data, offset, mask;
2167 DEBUGFUNC("e1000_check_downshift_generic");
2169 switch (phy->type) {
2170 case e1000_phy_i210:
2172 case e1000_phy_gg82563:
2174 case e1000_phy_82578:
2175 offset = M88E1000_PHY_SPEC_STATUS;
2176 mask = M88E1000_PSSR_DOWNSHIFT;
2179 case e1000_phy_igp_2:
2180 case e1000_phy_igp_3:
2181 offset = IGP01E1000_PHY_LINK_HEALTH;
2182 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
2185 /* speed downshift not supported */
2186 phy->speed_downgraded = FALSE;
2187 return E1000_SUCCESS;
2190 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2193 phy->speed_downgraded = !!(phy_data & mask);
2199 * e1000_check_polarity_m88 - Checks the polarity.
2200 * @hw: pointer to the HW structure
2202 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2204 * Polarity is determined based on the PHY specific status register.
2206 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2208 struct e1000_phy_info *phy = &hw->phy;
2212 DEBUGFUNC("e1000_check_polarity_m88");
2214 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2217 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
2218 ? e1000_rev_polarity_reversed
2219 : e1000_rev_polarity_normal;
2225 * e1000_check_polarity_igp - Checks the polarity.
2226 * @hw: pointer to the HW structure
2228 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2230 * Polarity is determined based on the PHY port status register, and the
2231 * current speed (since there is no polarity at 100Mbps).
2233 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2235 struct e1000_phy_info *phy = &hw->phy;
2237 u16 data, offset, mask;
2239 DEBUGFUNC("e1000_check_polarity_igp");
2242 * Polarity is determined based on the speed of
2245 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2249 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2250 IGP01E1000_PSSR_SPEED_1000MBPS) {
2251 offset = IGP01E1000_PHY_PCS_INIT_REG;
2252 mask = IGP01E1000_PHY_POLARITY_MASK;
2255 * This really only applies to 10Mbps since
2256 * there is no polarity for 100Mbps (always 0).
2258 offset = IGP01E1000_PHY_PORT_STATUS;
2259 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
2262 ret_val = phy->ops.read_reg(hw, offset, &data);
2265 phy->cable_polarity = (data & mask)
2266 ? e1000_rev_polarity_reversed
2267 : e1000_rev_polarity_normal;
2273 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2274 * @hw: pointer to the HW structure
2276 * Polarity is determined on the polarity reversal feature being enabled.
2278 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2280 struct e1000_phy_info *phy = &hw->phy;
2282 u16 phy_data, offset, mask;
2284 DEBUGFUNC("e1000_check_polarity_ife");
2287 * Polarity is determined based on the reversal feature being enabled.
2289 if (phy->polarity_correction) {
2290 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2291 mask = IFE_PESC_POLARITY_REVERSED;
2293 offset = IFE_PHY_SPECIAL_CONTROL;
2294 mask = IFE_PSC_FORCE_POLARITY;
2297 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2300 phy->cable_polarity = (phy_data & mask)
2301 ? e1000_rev_polarity_reversed
2302 : e1000_rev_polarity_normal;
2308 * e1000_wait_autoneg_generic - Wait for auto-neg completion
2309 * @hw: pointer to the HW structure
2311 * Waits for auto-negotiation to complete or for the auto-negotiation time
2312 * limit to expire, which ever happens first.
2314 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
2316 s32 ret_val = E1000_SUCCESS;
2319 DEBUGFUNC("e1000_wait_autoneg_generic");
2321 if (!hw->phy.ops.read_reg)
2322 return E1000_SUCCESS;
2324 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2325 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2326 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2329 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2332 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2338 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2345 * e1000_phy_has_link_generic - Polls PHY for link
2346 * @hw: pointer to the HW structure
2347 * @iterations: number of times to poll for link
2348 * @usec_interval: delay between polling attempts
2349 * @success: pointer to whether polling was successful or not
2351 * Polls the PHY status register for link, 'iterations' number of times.
2353 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2354 u32 usec_interval, bool *success)
2356 s32 ret_val = E1000_SUCCESS;
2359 DEBUGFUNC("e1000_phy_has_link_generic");
2361 if (!hw->phy.ops.read_reg)
2362 return E1000_SUCCESS;
2364 for (i = 0; i < iterations; i++) {
2366 * Some PHYs require the PHY_STATUS register to be read
2367 * twice due to the link bit being sticky. No harm doing
2368 * it across the board.
2370 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2373 * If the first read fails, another entity may have
2374 * ownership of the resources, wait and try again to
2375 * see if they have relinquished the resources yet.
2377 usec_delay(usec_interval);
2378 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2381 if (phy_status & MII_SR_LINK_STATUS)
2383 if (usec_interval >= 1000)
2384 msec_delay_irq(usec_interval/1000);
2386 usec_delay(usec_interval);
2389 *success = (i < iterations);
2395 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2396 * @hw: pointer to the HW structure
2398 * Reads the PHY specific status register to retrieve the cable length
2399 * information. The cable length is determined by averaging the minimum and
2400 * maximum values to get the "average" cable length. The m88 PHY has four
2401 * possible cable length values, which are:
2402 * Register Value Cable Length
2406 * 3 110 - 140 meters
2409 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2411 struct e1000_phy_info *phy = &hw->phy;
2413 u16 phy_data, index;
2415 DEBUGFUNC("e1000_get_cable_length_m88");
2417 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2421 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2422 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2424 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2425 return -E1000_ERR_PHY;
2427 phy->min_cable_length = e1000_m88_cable_length_table[index];
2428 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2430 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2432 return E1000_SUCCESS;
2435 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2437 struct e1000_phy_info *phy = &hw->phy;
2439 u16 phy_data, phy_data2, index, default_page, is_cm;
2441 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2443 switch (hw->phy.id) {
2445 /* Get cable length from PHY Cable Diagnostics Control Reg */
2446 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2447 (I347AT4_PCDL + phy->addr),
2452 /* Check if the unit of cable length is meters or cm */
2453 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2454 I347AT4_PCDC, &phy_data2);
2458 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2460 /* Populate the phy structure with cable length in meters */
2461 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2462 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2463 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2465 case M88E1340M_E_PHY_ID:
2466 case I347AT4_E_PHY_ID:
2467 /* Remember the original page select and set it to 7 */
2468 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2473 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2477 /* Get cable length from PHY Cable Diagnostics Control Reg */
2478 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2483 /* Check if the unit of cable length is meters or cm */
2484 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2488 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2490 /* Populate the phy structure with cable length in meters */
2491 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2492 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2493 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2495 /* Reset the page select to its original value */
2496 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2502 case M88E1112_E_PHY_ID:
2503 /* Remember the original page select and set it to 5 */
2504 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2509 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2513 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2518 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2519 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2521 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2522 return -E1000_ERR_PHY;
2524 phy->min_cable_length = e1000_m88_cable_length_table[index];
2525 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2527 phy->cable_length = (phy->min_cable_length +
2528 phy->max_cable_length) / 2;
2530 /* Reset the page select to its original value */
2531 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2538 return -E1000_ERR_PHY;
2545 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2546 * @hw: pointer to the HW structure
2548 * The automatic gain control (agc) normalizes the amplitude of the
2549 * received signal, adjusting for the attenuation produced by the
2550 * cable. By reading the AGC registers, which represent the
2551 * combination of coarse and fine gain value, the value can be put
2552 * into a lookup table to obtain the approximate cable length
2555 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2557 struct e1000_phy_info *phy = &hw->phy;
2559 u16 phy_data, i, agc_value = 0;
2560 u16 cur_agc_index, max_agc_index = 0;
2561 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2562 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2563 IGP02E1000_PHY_AGC_A,
2564 IGP02E1000_PHY_AGC_B,
2565 IGP02E1000_PHY_AGC_C,
2566 IGP02E1000_PHY_AGC_D
2569 DEBUGFUNC("e1000_get_cable_length_igp_2");
2571 /* Read the AGC registers for all channels */
2572 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2573 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2578 * Getting bits 15:9, which represent the combination of
2579 * coarse and fine gain values. The result is a number
2580 * that can be put into the lookup table to obtain the
2581 * approximate cable length.
2583 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2584 IGP02E1000_AGC_LENGTH_MASK;
2586 /* Array index bound check. */
2587 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2588 (cur_agc_index == 0))
2589 return -E1000_ERR_PHY;
2591 /* Remove min & max AGC values from calculation. */
2592 if (e1000_igp_2_cable_length_table[min_agc_index] >
2593 e1000_igp_2_cable_length_table[cur_agc_index])
2594 min_agc_index = cur_agc_index;
2595 if (e1000_igp_2_cable_length_table[max_agc_index] <
2596 e1000_igp_2_cable_length_table[cur_agc_index])
2597 max_agc_index = cur_agc_index;
2599 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2602 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2603 e1000_igp_2_cable_length_table[max_agc_index]);
2604 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2606 /* Calculate cable length with the error range of +/- 10 meters. */
2607 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2608 (agc_value - IGP02E1000_AGC_RANGE) : 0;
2609 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2611 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2613 return E1000_SUCCESS;
2617 * e1000_get_phy_info_m88 - Retrieve PHY information
2618 * @hw: pointer to the HW structure
2620 * Valid for only copper links. Read the PHY status register (sticky read)
2621 * to verify that link is up. Read the PHY special control register to
2622 * determine the polarity and 10base-T extended distance. Read the PHY
2623 * special status register to determine MDI/MDIx and current speed. If
2624 * speed is 1000, then determine cable length, local and remote receiver.
2626 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2628 struct e1000_phy_info *phy = &hw->phy;
2633 DEBUGFUNC("e1000_get_phy_info_m88");
2635 if (phy->media_type != e1000_media_type_copper) {
2636 DEBUGOUT("Phy info is only valid for copper media\n");
2637 return -E1000_ERR_CONFIG;
2640 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2645 DEBUGOUT("Phy info is only valid if link is up\n");
2646 return -E1000_ERR_CONFIG;
2649 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2653 phy->polarity_correction = !!(phy_data &
2654 M88E1000_PSCR_POLARITY_REVERSAL);
2656 ret_val = e1000_check_polarity_m88(hw);
2660 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2664 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2666 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2667 ret_val = hw->phy.ops.get_cable_length(hw);
2671 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2675 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2676 ? e1000_1000t_rx_status_ok
2677 : e1000_1000t_rx_status_not_ok;
2679 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2680 ? e1000_1000t_rx_status_ok
2681 : e1000_1000t_rx_status_not_ok;
2683 /* Set values to "undefined" */
2684 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2685 phy->local_rx = e1000_1000t_rx_status_undefined;
2686 phy->remote_rx = e1000_1000t_rx_status_undefined;
2693 * e1000_get_phy_info_igp - Retrieve igp PHY information
2694 * @hw: pointer to the HW structure
2696 * Read PHY status to determine if link is up. If link is up, then
2697 * set/determine 10base-T extended distance and polarity correction. Read
2698 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2699 * determine on the cable length, local and remote receiver.
2701 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2703 struct e1000_phy_info *phy = &hw->phy;
2708 DEBUGFUNC("e1000_get_phy_info_igp");
2710 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2715 DEBUGOUT("Phy info is only valid if link is up\n");
2716 return -E1000_ERR_CONFIG;
2719 phy->polarity_correction = TRUE;
2721 ret_val = e1000_check_polarity_igp(hw);
2725 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2729 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2731 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2732 IGP01E1000_PSSR_SPEED_1000MBPS) {
2733 ret_val = phy->ops.get_cable_length(hw);
2737 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2741 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2742 ? e1000_1000t_rx_status_ok
2743 : e1000_1000t_rx_status_not_ok;
2745 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2746 ? e1000_1000t_rx_status_ok
2747 : e1000_1000t_rx_status_not_ok;
2749 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2750 phy->local_rx = e1000_1000t_rx_status_undefined;
2751 phy->remote_rx = e1000_1000t_rx_status_undefined;
2758 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2759 * @hw: pointer to the HW structure
2761 * Populates "phy" structure with various feature states.
2763 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2765 struct e1000_phy_info *phy = &hw->phy;
2770 DEBUGFUNC("e1000_get_phy_info_ife");
2772 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2777 DEBUGOUT("Phy info is only valid if link is up\n");
2778 return -E1000_ERR_CONFIG;
2781 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2784 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2786 if (phy->polarity_correction) {
2787 ret_val = e1000_check_polarity_ife(hw);
2791 /* Polarity is forced */
2792 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2793 ? e1000_rev_polarity_reversed
2794 : e1000_rev_polarity_normal;
2797 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2801 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2803 /* The following parameters are undefined for 10/100 operation. */
2804 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2805 phy->local_rx = e1000_1000t_rx_status_undefined;
2806 phy->remote_rx = e1000_1000t_rx_status_undefined;
2808 return E1000_SUCCESS;
2812 * e1000_phy_sw_reset_generic - PHY software reset
2813 * @hw: pointer to the HW structure
2815 * Does a software reset of the PHY by reading the PHY control register and
2816 * setting/write the control register reset bit to the PHY.
2818 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2823 DEBUGFUNC("e1000_phy_sw_reset_generic");
2825 if (!hw->phy.ops.read_reg)
2826 return E1000_SUCCESS;
2828 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2832 phy_ctrl |= MII_CR_RESET;
2833 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2843 * e1000_phy_hw_reset_generic - PHY hardware reset
2844 * @hw: pointer to the HW structure
2846 * Verify the reset block is not blocking us from resetting. Acquire
2847 * semaphore (if necessary) and read/set/write the device control reset
2848 * bit in the PHY. Wait the appropriate delay time for the device to
2849 * reset and release the semaphore (if necessary).
2851 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2853 struct e1000_phy_info *phy = &hw->phy;
2857 DEBUGFUNC("e1000_phy_hw_reset_generic");
2859 if (phy->ops.check_reset_block) {
2860 ret_val = phy->ops.check_reset_block(hw);
2862 return E1000_SUCCESS;
2865 ret_val = phy->ops.acquire(hw);
2869 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2870 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2871 E1000_WRITE_FLUSH(hw);
2873 usec_delay(phy->reset_delay_us);
2875 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2876 E1000_WRITE_FLUSH(hw);
2880 phy->ops.release(hw);
2882 return phy->ops.get_cfg_done(hw);
2886 * e1000_get_cfg_done_generic - Generic configuration done
2887 * @hw: pointer to the HW structure
2889 * Generic function to wait 10 milli-seconds for configuration to complete
2890 * and return success.
2892 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw)
2894 DEBUGFUNC("e1000_get_cfg_done_generic");
2898 return E1000_SUCCESS;
2902 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2903 * @hw: pointer to the HW structure
2905 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2907 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2909 DEBUGOUT("Running IGP 3 PHY init script\n");
2911 /* PHY init IGP 3 */
2912 /* Enable rise/fall, 10-mode work in class-A */
2913 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2914 /* Remove all caps from Replica path filter */
2915 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2916 /* Bias trimming for ADC, AFE and Driver (Default) */
2917 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2918 /* Increase Hybrid poly bias */
2919 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2920 /* Add 4% to Tx amplitude in Gig mode */
2921 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2922 /* Disable trimming (TTT) */
2923 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2924 /* Poly DC correction to 94.6% + 2% for all channels */
2925 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2926 /* ABS DC correction to 95.9% */
2927 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2928 /* BG temp curve trim */
2929 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2930 /* Increasing ADC OPAMP stage 1 currents to max */
2931 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2932 /* Force 1000 ( required for enabling PHY regs configuration) */
2933 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2934 /* Set upd_freq to 6 */
2935 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2937 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2938 /* Disable adaptive fixed FFE (Default) */
2939 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2940 /* Enable FFE hysteresis */
2941 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2942 /* Fixed FFE for short cable lengths */
2943 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2944 /* Fixed FFE for medium cable lengths */
2945 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2946 /* Fixed FFE for long cable lengths */
2947 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2948 /* Enable Adaptive Clip Threshold */
2949 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2950 /* AHT reset limit to 1 */
2951 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2952 /* Set AHT master delay to 127 msec */
2953 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2954 /* Set scan bits for AHT */
2955 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2956 /* Set AHT Preset bits */
2957 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2958 /* Change integ_factor of channel A to 3 */
2959 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2960 /* Change prop_factor of channels BCD to 8 */
2961 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2962 /* Change cg_icount + enable integbp for channels BCD */
2963 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2965 * Change cg_icount + enable integbp + change prop_factor_master
2966 * to 8 for channel A
2968 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2969 /* Disable AHT in Slave mode on channel A */
2970 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2972 * Enable LPLU and disable AN to 1000 in non-D0a states,
2975 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2976 /* Enable restart AN on an1000_dis change */
2977 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2978 /* Enable wh_fifo read clock in 10/100 modes */
2979 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2980 /* Restart AN, Speed selection is 1000 */
2981 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2983 return E1000_SUCCESS;
2987 * e1000_get_phy_type_from_id - Get PHY type from id
2988 * @phy_id: phy_id read from the phy
2990 * Returns the phy type from the id.
2992 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2994 enum e1000_phy_type phy_type = e1000_phy_unknown;
2997 case M88E1000_I_PHY_ID:
2998 case M88E1000_E_PHY_ID:
2999 case M88E1111_I_PHY_ID:
3000 case M88E1011_I_PHY_ID:
3001 case I347AT4_E_PHY_ID:
3002 case M88E1112_E_PHY_ID:
3003 case M88E1340M_E_PHY_ID:
3004 phy_type = e1000_phy_m88;
3006 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
3007 phy_type = e1000_phy_igp_2;
3009 case GG82563_E_PHY_ID:
3010 phy_type = e1000_phy_gg82563;
3012 case IGP03E1000_E_PHY_ID:
3013 phy_type = e1000_phy_igp_3;
3016 case IFE_PLUS_E_PHY_ID:
3017 case IFE_C_E_PHY_ID:
3018 phy_type = e1000_phy_ife;
3020 case BME1000_E_PHY_ID:
3021 case BME1000_E_PHY_ID_R2:
3022 phy_type = e1000_phy_bm;
3024 case I82578_E_PHY_ID:
3025 phy_type = e1000_phy_82578;
3027 case I82577_E_PHY_ID:
3028 phy_type = e1000_phy_82577;
3030 case I82579_E_PHY_ID:
3031 phy_type = e1000_phy_82579;
3033 case I82580_I_PHY_ID:
3034 phy_type = e1000_phy_82580;
3037 phy_type = e1000_phy_i210;
3040 phy_type = e1000_phy_unknown;
3047 * e1000_determine_phy_address - Determines PHY address.
3048 * @hw: pointer to the HW structure
3050 * This uses a trial and error method to loop through possible PHY
3051 * addresses. It tests each by reading the PHY ID registers and
3052 * checking for a match.
3054 s32 e1000_determine_phy_address(struct e1000_hw *hw)
3058 enum e1000_phy_type phy_type = e1000_phy_unknown;
3060 hw->phy.id = phy_type;
3062 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
3063 hw->phy.addr = phy_addr;
3067 e1000_get_phy_id(hw);
3068 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3071 * If phy_type is valid, break - we found our
3074 if (phy_type != e1000_phy_unknown)
3075 return E1000_SUCCESS;
3082 return -E1000_ERR_PHY_TYPE;
3086 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
3087 * @page: page to access
3089 * Returns the phy address for the page requested.
3091 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
3095 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
3102 * e1000_write_phy_reg_bm - Write BM PHY register
3103 * @hw: pointer to the HW structure
3104 * @offset: register offset to write to
3105 * @data: data to write at register offset
3107 * Acquires semaphore, if necessary, then writes the data to PHY register
3108 * at the offset. Release any acquired semaphores before exiting.
3110 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
3113 u32 page = offset >> IGP_PAGE_SHIFT;
3115 DEBUGFUNC("e1000_write_phy_reg_bm");
3117 ret_val = hw->phy.ops.acquire(hw);
3121 /* Page 800 works differently than the rest so it has its own func */
3122 if (page == BM_WUC_PAGE) {
3123 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3128 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3130 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3131 u32 page_shift, page_select;
3134 * Page select is register 31 for phy address 1 and 22 for
3135 * phy address 2 and 3. Page select is shifted only for
3138 if (hw->phy.addr == 1) {
3139 page_shift = IGP_PAGE_SHIFT;
3140 page_select = IGP01E1000_PHY_PAGE_SELECT;
3143 page_select = BM_PHY_PAGE_SELECT;
3146 /* Page is shifted left, PHY expects (page x 32) */
3147 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3148 (page << page_shift));
3153 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3157 hw->phy.ops.release(hw);
3162 * e1000_read_phy_reg_bm - Read BM PHY register
3163 * @hw: pointer to the HW structure
3164 * @offset: register offset to be read
3165 * @data: pointer to the read data
3167 * Acquires semaphore, if necessary, then reads the PHY register at offset
3168 * and storing the retrieved information in data. Release any acquired
3169 * semaphores before exiting.
3171 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
3174 u32 page = offset >> IGP_PAGE_SHIFT;
3176 DEBUGFUNC("e1000_read_phy_reg_bm");
3178 ret_val = hw->phy.ops.acquire(hw);
3182 /* Page 800 works differently than the rest so it has its own func */
3183 if (page == BM_WUC_PAGE) {
3184 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3189 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3191 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3192 u32 page_shift, page_select;
3195 * Page select is register 31 for phy address 1 and 22 for
3196 * phy address 2 and 3. Page select is shifted only for
3199 if (hw->phy.addr == 1) {
3200 page_shift = IGP_PAGE_SHIFT;
3201 page_select = IGP01E1000_PHY_PAGE_SELECT;
3204 page_select = BM_PHY_PAGE_SELECT;
3207 /* Page is shifted left, PHY expects (page x 32) */
3208 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3209 (page << page_shift));
3214 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3217 hw->phy.ops.release(hw);
3222 * e1000_read_phy_reg_bm2 - Read BM PHY register
3223 * @hw: pointer to the HW structure
3224 * @offset: register offset to be read
3225 * @data: pointer to the read data
3227 * Acquires semaphore, if necessary, then reads the PHY register at offset
3228 * and storing the retrieved information in data. Release any acquired
3229 * semaphores before exiting.
3231 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
3234 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3236 DEBUGFUNC("e1000_read_phy_reg_bm2");
3238 ret_val = hw->phy.ops.acquire(hw);
3242 /* Page 800 works differently than the rest so it has its own func */
3243 if (page == BM_WUC_PAGE) {
3244 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3251 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3253 /* Page is shifted left, PHY expects (page x 32) */
3254 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3261 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3264 hw->phy.ops.release(hw);
3269 * e1000_write_phy_reg_bm2 - Write BM PHY register
3270 * @hw: pointer to the HW structure
3271 * @offset: register offset to write to
3272 * @data: data to write at register offset
3274 * Acquires semaphore, if necessary, then writes the data to PHY register
3275 * at the offset. Release any acquired semaphores before exiting.
3277 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
3280 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3282 DEBUGFUNC("e1000_write_phy_reg_bm2");
3284 ret_val = hw->phy.ops.acquire(hw);
3288 /* Page 800 works differently than the rest so it has its own func */
3289 if (page == BM_WUC_PAGE) {
3290 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3297 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3298 /* Page is shifted left, PHY expects (page x 32) */
3299 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3306 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3310 hw->phy.ops.release(hw);
3315 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
3316 * @hw: pointer to the HW structure
3317 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
3319 * Assumes semaphore already acquired and phy_reg points to a valid memory
3320 * address to store contents of the BM_WUC_ENABLE_REG register.
3322 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3327 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm");
3330 return -E1000_ERR_PARAM;
3332 /* All page select, port ctrl and wakeup registers use phy address 1 */
3335 /* Select Port Control Registers page */
3336 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3338 DEBUGOUT("Could not set Port Control page\n");
3342 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3344 DEBUGOUT2("Could not read PHY register %d.%d\n",
3345 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3350 * Enable both PHY wakeup mode and Wakeup register page writes.
3351 * Prevent a power state change by disabling ME and Host PHY wakeup.
3354 temp |= BM_WUC_ENABLE_BIT;
3355 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
3357 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3359 DEBUGOUT2("Could not write PHY register %d.%d\n",
3360 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3365 * Select Host Wakeup Registers page - caller now able to write
3366 * registers on the Wakeup registers page
3368 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3372 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
3373 * @hw: pointer to the HW structure
3374 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
3376 * Restore BM_WUC_ENABLE_REG to its original value.
3378 * Assumes semaphore already acquired and *phy_reg is the contents of the
3379 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
3382 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3384 s32 ret_val = E1000_SUCCESS;
3386 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm");
3389 return -E1000_ERR_PARAM;
3391 /* Select Port Control Registers page */
3392 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3394 DEBUGOUT("Could not set Port Control page\n");
3398 /* Restore 769.17 to its original value */
3399 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3401 DEBUGOUT2("Could not restore PHY register %d.%d\n",
3402 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3408 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
3409 * @hw: pointer to the HW structure
3410 * @offset: register offset to be read or written
3411 * @data: pointer to the data to read or write
3412 * @read: determines if operation is read or write
3413 * @page_set: BM_WUC_PAGE already set and access enabled
3415 * Read the PHY register at offset and store the retrieved information in
3416 * data, or write data to PHY register at offset. Note the procedure to
3417 * access the PHY wakeup registers is different than reading the other PHY
3418 * registers. It works as such:
3419 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
3420 * 2) Set page to 800 for host (801 if we were manageability)
3421 * 3) Write the address using the address opcode (0x11)
3422 * 4) Read or write the data using the data opcode (0x12)
3423 * 5) Restore 769.17.2 to its original value
3425 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
3426 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
3428 * Assumes semaphore is already acquired. When page_set==TRUE, assumes
3429 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
3430 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
3432 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
3433 u16 *data, bool read, bool page_set)
3436 u16 reg = BM_PHY_REG_NUM(offset);
3439 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
3441 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
3442 if ((hw->mac.type == e1000_pchlan) &&
3443 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
3444 DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
3448 /* Enable access to PHY wakeup registers */
3449 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3451 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3456 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3458 /* Write the Wakeup register page offset value using opcode 0x11 */
3459 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3461 DEBUGOUT1("Could not write address opcode to page %d\n", page);
3466 /* Read the Wakeup register page value using opcode 0x12 */
3467 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3470 /* Write the Wakeup register page value using opcode 0x12 */
3471 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3476 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3481 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3487 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3488 * @hw: pointer to the HW structure
3490 * In the case of a PHY power down to save power, or to turn off link during a
3491 * driver unload, or wake on lan is not enabled, restore the link to previous
3494 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3499 /* The PHY will retain its settings across a power down/up cycle */
3500 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3501 mii_reg &= ~MII_CR_POWER_DOWN;
3502 if (hw->phy.type == e1000_phy_i210) {
3503 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
3504 power_reg &= ~GS40G_CS_POWER_DOWN;
3505 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
3507 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3511 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3512 * @hw: pointer to the HW structure
3514 * In the case of a PHY power down to save power, or to turn off link during a
3515 * driver unload, or wake on lan is not enabled, restore the link to previous
3518 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3523 /* The PHY will retain its settings across a power down/up cycle */
3524 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3525 mii_reg |= MII_CR_POWER_DOWN;
3526 /* i210 Phy requires an additional bit for power up/down */
3527 if (hw->phy.type == e1000_phy_i210) {
3528 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
3529 power_reg |= GS40G_CS_POWER_DOWN;
3530 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
3532 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3537 * __e1000_read_phy_reg_hv - Read HV PHY register
3538 * @hw: pointer to the HW structure
3539 * @offset: register offset to be read
3540 * @data: pointer to the read data
3541 * @locked: semaphore has already been acquired or not
3543 * Acquires semaphore, if necessary, then reads the PHY register at offset
3544 * and stores the retrieved information in data. Release any acquired
3545 * semaphore before exiting.
3547 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3548 bool locked, bool page_set)
3551 u16 page = BM_PHY_REG_PAGE(offset);
3552 u16 reg = BM_PHY_REG_NUM(offset);
3553 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3555 DEBUGFUNC("__e1000_read_phy_reg_hv");
3558 ret_val = hw->phy.ops.acquire(hw);
3563 /* Page 800 works differently than the rest so it has its own func */
3564 if (page == BM_WUC_PAGE) {
3565 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3570 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3571 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3577 if (page == HV_INTC_FC_PAGE_START)
3580 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3581 /* Page is shifted left, PHY expects (page x 32) */
3582 ret_val = e1000_set_page_igp(hw,
3583 (page << IGP_PAGE_SHIFT));
3585 hw->phy.addr = phy_addr;
3592 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3593 page << IGP_PAGE_SHIFT, reg);
3595 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3599 hw->phy.ops.release(hw);
3605 * e1000_read_phy_reg_hv - Read HV PHY register
3606 * @hw: pointer to the HW structure
3607 * @offset: register offset to be read
3608 * @data: pointer to the read data
3610 * Acquires semaphore then reads the PHY register at offset and stores
3611 * the retrieved information in data. Release the acquired semaphore
3614 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3616 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE, FALSE);
3620 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3621 * @hw: pointer to the HW structure
3622 * @offset: register offset to be read
3623 * @data: pointer to the read data
3625 * Reads the PHY register at offset and stores the retrieved information
3626 * in data. Assumes semaphore already acquired.
3628 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3630 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, FALSE);
3634 * e1000_read_phy_reg_page_hv - Read HV PHY register
3635 * @hw: pointer to the HW structure
3636 * @offset: register offset to write to
3637 * @data: data to write at register offset
3639 * Reads the PHY register at offset and stores the retrieved information
3640 * in data. Assumes semaphore already acquired and page already set.
3642 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3644 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, true);
3648 * __e1000_write_phy_reg_hv - Write HV PHY register
3649 * @hw: pointer to the HW structure
3650 * @offset: register offset to write to
3651 * @data: data to write at register offset
3652 * @locked: semaphore has already been acquired or not
3654 * Acquires semaphore, if necessary, then writes the data to PHY register
3655 * at the offset. Release any acquired semaphores before exiting.
3657 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3658 bool locked, bool page_set)
3661 u16 page = BM_PHY_REG_PAGE(offset);
3662 u16 reg = BM_PHY_REG_NUM(offset);
3663 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3665 DEBUGFUNC("__e1000_write_phy_reg_hv");
3668 ret_val = hw->phy.ops.acquire(hw);
3673 /* Page 800 works differently than the rest so it has its own func */
3674 if (page == BM_WUC_PAGE) {
3675 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3680 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3681 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3687 if (page == HV_INTC_FC_PAGE_START)
3691 * Workaround MDIO accesses being disabled after entering IEEE
3692 * Power Down (when bit 11 of the PHY Control register is set)
3694 if ((hw->phy.type == e1000_phy_82578) &&
3695 (hw->phy.revision >= 1) &&
3696 (hw->phy.addr == 2) &&
3697 !(MAX_PHY_REG_ADDRESS & reg) &&
3698 (data & (1 << 11))) {
3700 ret_val = e1000_access_phy_debug_regs_hv(hw,
3707 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3708 /* Page is shifted left, PHY expects (page x 32) */
3709 ret_val = e1000_set_page_igp(hw,
3710 (page << IGP_PAGE_SHIFT));
3712 hw->phy.addr = phy_addr;
3719 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3720 page << IGP_PAGE_SHIFT, reg);
3722 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3727 hw->phy.ops.release(hw);
3733 * e1000_write_phy_reg_hv - Write HV PHY register
3734 * @hw: pointer to the HW structure
3735 * @offset: register offset to write to
3736 * @data: data to write at register offset
3738 * Acquires semaphore then writes the data to PHY register at the offset.
3739 * Release the acquired semaphores before exiting.
3741 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3743 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE, FALSE);
3747 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3748 * @hw: pointer to the HW structure
3749 * @offset: register offset to write to
3750 * @data: data to write at register offset
3752 * Writes the data to PHY register at the offset. Assumes semaphore
3755 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3757 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, FALSE);
3761 * e1000_write_phy_reg_page_hv - Write HV PHY register
3762 * @hw: pointer to the HW structure
3763 * @offset: register offset to write to
3764 * @data: data to write at register offset
3766 * Writes the data to PHY register at the offset. Assumes semaphore
3767 * already acquired and page already set.
3769 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3771 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, true);
3775 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3776 * @page: page to be accessed
3778 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3782 if (page >= HV_INTC_FC_PAGE_START)
3789 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3790 * @hw: pointer to the HW structure
3791 * @offset: register offset to be read or written
3792 * @data: pointer to the data to be read or written
3793 * @read: determines if operation is read or write
3795 * Reads the PHY register at offset and stores the retreived information
3796 * in data. Assumes semaphore already acquired. Note that the procedure
3797 * to access these regs uses the address port and data port to read/write.
3798 * These accesses done with PHY address 2 and without using pages.
3800 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3801 u16 *data, bool read)
3807 DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3809 /* This takes care of the difference with desktop vs mobile phy */
3810 addr_reg = (hw->phy.type == e1000_phy_82578) ?
3811 I82578_ADDR_REG : I82577_ADDR_REG;
3812 data_reg = addr_reg + 1;
3814 /* All operations in this function are phy address 2 */
3817 /* masking with 0x3F to remove the page from offset */
3818 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3820 DEBUGOUT("Could not write the Address Offset port register\n");
3824 /* Read or write the data value next */
3826 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3828 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3831 DEBUGOUT("Could not access the Data port register\n");
3837 * e1000_link_stall_workaround_hv - Si workaround
3838 * @hw: pointer to the HW structure
3840 * This function works around a Si bug where the link partner can get
3841 * a link up indication before the PHY does. If small packets are sent
3842 * by the link partner they can be placed in the packet buffer without
3843 * being properly accounted for by the PHY and will stall preventing
3844 * further packets from being received. The workaround is to clear the
3845 * packet buffer after the PHY detects link up.
3847 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3849 s32 ret_val = E1000_SUCCESS;
3852 DEBUGFUNC("e1000_link_stall_workaround_hv");
3854 if (hw->phy.type != e1000_phy_82578)
3855 return E1000_SUCCESS;
3857 /* Do not apply workaround if in PHY loopback bit 14 set */
3858 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3859 if (data & PHY_CONTROL_LB)
3860 return E1000_SUCCESS;
3862 /* check if link is up and at 1Gbps */
3863 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3867 data &= BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3868 BM_CS_STATUS_SPEED_MASK;
3870 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3871 BM_CS_STATUS_SPEED_1000))
3872 return E1000_SUCCESS;
3876 /* flush the packets in the fifo buffer */
3877 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3878 HV_MUX_DATA_CTRL_GEN_TO_MAC |
3879 HV_MUX_DATA_CTRL_FORCE_SPEED);
3883 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3884 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3888 * e1000_check_polarity_82577 - Checks the polarity.
3889 * @hw: pointer to the HW structure
3891 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3893 * Polarity is determined based on the PHY specific status register.
3895 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3897 struct e1000_phy_info *phy = &hw->phy;
3901 DEBUGFUNC("e1000_check_polarity_82577");
3903 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3906 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
3907 ? e1000_rev_polarity_reversed
3908 : e1000_rev_polarity_normal;
3914 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3915 * @hw: pointer to the HW structure
3917 * Calls the PHY setup function to force speed and duplex.
3919 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3921 struct e1000_phy_info *phy = &hw->phy;
3926 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3928 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3932 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3934 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3940 if (phy->autoneg_wait_to_complete) {
3941 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3943 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3949 DEBUGOUT("Link taking longer than expected.\n");
3952 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3960 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3961 * @hw: pointer to the HW structure
3963 * Read PHY status to determine if link is up. If link is up, then
3964 * set/determine 10base-T extended distance and polarity correction. Read
3965 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3966 * determine on the cable length, local and remote receiver.
3968 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3970 struct e1000_phy_info *phy = &hw->phy;
3975 DEBUGFUNC("e1000_get_phy_info_82577");
3977 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3982 DEBUGOUT("Phy info is only valid if link is up\n");
3983 return -E1000_ERR_CONFIG;
3986 phy->polarity_correction = TRUE;
3988 ret_val = e1000_check_polarity_82577(hw);
3992 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3996 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3998 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3999 I82577_PHY_STATUS2_SPEED_1000MBPS) {
4000 ret_val = hw->phy.ops.get_cable_length(hw);
4004 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
4008 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
4009 ? e1000_1000t_rx_status_ok
4010 : e1000_1000t_rx_status_not_ok;
4012 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
4013 ? e1000_1000t_rx_status_ok
4014 : e1000_1000t_rx_status_not_ok;
4016 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
4017 phy->local_rx = e1000_1000t_rx_status_undefined;
4018 phy->remote_rx = e1000_1000t_rx_status_undefined;
4021 return E1000_SUCCESS;
4025 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
4026 * @hw: pointer to the HW structure
4028 * Reads the diagnostic status register and verifies result is valid before
4029 * placing it in the phy_cable_length field.
4031 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
4033 struct e1000_phy_info *phy = &hw->phy;
4035 u16 phy_data, length;
4037 DEBUGFUNC("e1000_get_cable_length_82577");
4039 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4043 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
4044 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
4046 if (length == E1000_CABLE_LENGTH_UNDEFINED)
4047 ret_val = -E1000_ERR_PHY;
4049 phy->cable_length = length;
4051 return E1000_SUCCESS;
4055 * e1000_write_phy_reg_gs40g - Write GS40G PHY register
4056 * @hw: pointer to the HW structure
4057 * @offset: register offset to write to
4058 * @data: data to write at register offset
4060 * Acquires semaphore, if necessary, then writes the data to PHY register
4061 * at the offset. Release any acquired semaphores before exiting.
4063 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
4066 u16 page = offset >> GS40G_PAGE_SHIFT;
4068 DEBUGFUNC("e1000_write_phy_reg_gs40g");
4070 offset = offset & GS40G_OFFSET_MASK;
4071 ret_val = hw->phy.ops.acquire(hw);
4075 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4078 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
4081 hw->phy.ops.release(hw);
4086 * e1000_read_phy_reg_gs40g - Read GS40G PHY register
4087 * @hw: pointer to the HW structure
4088 * @offset: lower half is register offset to read to
4089 * upper half is page to use.
4090 * @data: data to read at register offset
4092 * Acquires semaphore, if necessary, then reads the data in the PHY register
4093 * at the offset. Release any acquired semaphores before exiting.
4095 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
4098 u16 page = offset >> GS40G_PAGE_SHIFT;
4100 DEBUGFUNC("e1000_read_phy_reg_gs40g");
4102 offset = offset & GS40G_OFFSET_MASK;
4103 ret_val = hw->phy.ops.acquire(hw);
4107 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4110 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
4113 hw->phy.ops.release(hw);