1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2015, Intel Corporation
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
10 1. Redistributions of source code must retain the above copyright notice,
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14 notice, this list of conditions and the following disclaimer in the
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19 this software without specific prior written permission.
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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31 POSSIBILITY OF SUCH DAMAGE.
33 ******************************************************************************/
36 #include "e1000_api.h"
38 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
39 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
40 u16 *data, bool read, bool page_set);
41 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
42 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
43 u16 *data, bool read);
45 /* Cable length tables */
46 static const u16 e1000_m88_cable_length_table[] = {
47 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
48 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
49 (sizeof(e1000_m88_cable_length_table) / \
50 sizeof(e1000_m88_cable_length_table[0]))
52 static const u16 e1000_igp_2_cable_length_table[] = {
53 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
54 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
55 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
56 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
57 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
58 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
59 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
61 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
62 (sizeof(e1000_igp_2_cable_length_table) / \
63 sizeof(e1000_igp_2_cable_length_table[0]))
66 * e1000_init_phy_ops_generic - Initialize PHY function pointers
67 * @hw: pointer to the HW structure
69 * Setups up the function pointers to no-op functions
71 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
73 struct e1000_phy_info *phy = &hw->phy;
74 DEBUGFUNC("e1000_init_phy_ops_generic");
76 /* Initialize function pointers */
77 phy->ops.init_params = e1000_null_ops_generic;
78 phy->ops.acquire = e1000_null_ops_generic;
79 phy->ops.check_polarity = e1000_null_ops_generic;
80 phy->ops.check_reset_block = e1000_null_ops_generic;
81 phy->ops.commit = e1000_null_ops_generic;
82 phy->ops.force_speed_duplex = e1000_null_ops_generic;
83 phy->ops.get_cfg_done = e1000_null_ops_generic;
84 phy->ops.get_cable_length = e1000_null_ops_generic;
85 phy->ops.get_info = e1000_null_ops_generic;
86 phy->ops.set_page = e1000_null_set_page;
87 phy->ops.read_reg = e1000_null_read_reg;
88 phy->ops.read_reg_locked = e1000_null_read_reg;
89 phy->ops.read_reg_page = e1000_null_read_reg;
90 phy->ops.release = e1000_null_phy_generic;
91 phy->ops.reset = e1000_null_ops_generic;
92 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
93 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
94 phy->ops.write_reg = e1000_null_write_reg;
95 phy->ops.write_reg_locked = e1000_null_write_reg;
96 phy->ops.write_reg_page = e1000_null_write_reg;
97 phy->ops.power_up = e1000_null_phy_generic;
98 phy->ops.power_down = e1000_null_phy_generic;
99 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
100 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
101 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
105 * e1000_null_set_page - No-op function, return 0
106 * @hw: pointer to the HW structure
108 s32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw,
109 u16 E1000_UNUSEDARG data)
111 DEBUGFUNC("e1000_null_set_page");
112 return E1000_SUCCESS;
116 * e1000_null_read_reg - No-op function, return 0
117 * @hw: pointer to the HW structure
119 s32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw,
120 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data)
122 DEBUGFUNC("e1000_null_read_reg");
123 return E1000_SUCCESS;
127 * e1000_null_phy_generic - No-op function, return void
128 * @hw: pointer to the HW structure
130 void e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw)
132 DEBUGFUNC("e1000_null_phy_generic");
137 * e1000_null_lplu_state - No-op function, return 0
138 * @hw: pointer to the HW structure
140 s32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw,
141 bool E1000_UNUSEDARG active)
143 DEBUGFUNC("e1000_null_lplu_state");
144 return E1000_SUCCESS;
148 * e1000_null_write_reg - No-op function, return 0
149 * @hw: pointer to the HW structure
151 s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw,
152 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data)
154 DEBUGFUNC("e1000_null_write_reg");
155 return E1000_SUCCESS;
159 * e1000_read_i2c_byte_null - No-op function, return 0
160 * @hw: pointer to hardware structure
161 * @byte_offset: byte offset to write
162 * @dev_addr: device address
163 * @data: data value read
166 s32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
167 u8 E1000_UNUSEDARG byte_offset,
168 u8 E1000_UNUSEDARG dev_addr,
169 u8 E1000_UNUSEDARG *data)
171 DEBUGFUNC("e1000_read_i2c_byte_null");
172 return E1000_SUCCESS;
176 * e1000_write_i2c_byte_null - No-op function, return 0
177 * @hw: pointer to hardware structure
178 * @byte_offset: byte offset to write
179 * @dev_addr: device address
180 * @data: data value to write
183 s32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
184 u8 E1000_UNUSEDARG byte_offset,
185 u8 E1000_UNUSEDARG dev_addr,
186 u8 E1000_UNUSEDARG data)
188 DEBUGFUNC("e1000_write_i2c_byte_null");
189 return E1000_SUCCESS;
193 * e1000_check_reset_block_generic - Check if PHY reset is blocked
194 * @hw: pointer to the HW structure
196 * Read the PHY management control register and check whether a PHY reset
197 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
198 * return E1000_BLK_PHY_RESET (12).
200 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
204 DEBUGFUNC("e1000_check_reset_block");
206 manc = E1000_READ_REG(hw, E1000_MANC);
208 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
209 E1000_BLK_PHY_RESET : E1000_SUCCESS;
213 * e1000_get_phy_id - Retrieve the PHY ID and revision
214 * @hw: pointer to the HW structure
216 * Reads the PHY registers and stores the PHY ID and possibly the PHY
217 * revision in the hardware structure.
219 s32 e1000_get_phy_id(struct e1000_hw *hw)
221 struct e1000_phy_info *phy = &hw->phy;
222 s32 ret_val = E1000_SUCCESS;
226 DEBUGFUNC("e1000_get_phy_id");
228 if (!phy->ops.read_reg)
229 return E1000_SUCCESS;
231 while (retry_count < 2) {
232 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
236 phy->id = (u32)(phy_id << 16);
238 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
242 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
243 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
245 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
246 return E1000_SUCCESS;
251 return E1000_SUCCESS;
255 * e1000_phy_reset_dsp_generic - Reset PHY DSP
256 * @hw: pointer to the HW structure
258 * Reset the digital signal processor.
260 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
264 DEBUGFUNC("e1000_phy_reset_dsp_generic");
266 if (!hw->phy.ops.write_reg)
267 return E1000_SUCCESS;
269 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
273 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
277 * e1000_read_phy_reg_mdic - Read MDI control register
278 * @hw: pointer to the HW structure
279 * @offset: register offset to be read
280 * @data: pointer to the read data
282 * Reads the MDI control register in the PHY at offset and stores the
283 * information read to data.
285 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
287 struct e1000_phy_info *phy = &hw->phy;
290 DEBUGFUNC("e1000_read_phy_reg_mdic");
292 if (offset > MAX_PHY_REG_ADDRESS) {
293 DEBUGOUT1("PHY Address %d is out of range\n", offset);
294 return -E1000_ERR_PARAM;
297 /* Set up Op-code, Phy Address, and register offset in the MDI
298 * Control register. The MAC will take care of interfacing with the
299 * PHY to retrieve the desired data.
301 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
302 (phy->addr << E1000_MDIC_PHY_SHIFT) |
303 (E1000_MDIC_OP_READ));
305 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
307 /* Poll the ready bit to see if the MDI read completed
308 * Increasing the time out as testing showed failures with
311 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
313 mdic = E1000_READ_REG(hw, E1000_MDIC);
314 if (mdic & E1000_MDIC_READY)
317 if (!(mdic & E1000_MDIC_READY)) {
318 DEBUGOUT("MDI Read did not complete\n");
319 return -E1000_ERR_PHY;
321 if (mdic & E1000_MDIC_ERROR) {
322 DEBUGOUT("MDI Error\n");
323 return -E1000_ERR_PHY;
325 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
326 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n",
328 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
329 return -E1000_ERR_PHY;
333 /* Allow some time after each MDIC transaction to avoid
334 * reading duplicate data in the next MDIC transaction.
336 if (hw->mac.type == e1000_pch2lan)
339 return E1000_SUCCESS;
343 * e1000_write_phy_reg_mdic - Write MDI control register
344 * @hw: pointer to the HW structure
345 * @offset: register offset to write to
346 * @data: data to write to register at offset
348 * Writes data to MDI control register in the PHY at offset.
350 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
352 struct e1000_phy_info *phy = &hw->phy;
355 DEBUGFUNC("e1000_write_phy_reg_mdic");
357 if (offset > MAX_PHY_REG_ADDRESS) {
358 DEBUGOUT1("PHY Address %d is out of range\n", offset);
359 return -E1000_ERR_PARAM;
362 /* Set up Op-code, Phy Address, and register offset in the MDI
363 * Control register. The MAC will take care of interfacing with the
364 * PHY to retrieve the desired data.
366 mdic = (((u32)data) |
367 (offset << E1000_MDIC_REG_SHIFT) |
368 (phy->addr << E1000_MDIC_PHY_SHIFT) |
369 (E1000_MDIC_OP_WRITE));
371 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
373 /* Poll the ready bit to see if the MDI read completed
374 * Increasing the time out as testing showed failures with
377 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
379 mdic = E1000_READ_REG(hw, E1000_MDIC);
380 if (mdic & E1000_MDIC_READY)
383 if (!(mdic & E1000_MDIC_READY)) {
384 DEBUGOUT("MDI Write did not complete\n");
385 return -E1000_ERR_PHY;
387 if (mdic & E1000_MDIC_ERROR) {
388 DEBUGOUT("MDI Error\n");
389 return -E1000_ERR_PHY;
391 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
392 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n",
394 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
395 return -E1000_ERR_PHY;
398 /* Allow some time after each MDIC transaction to avoid
399 * reading duplicate data in the next MDIC transaction.
401 if (hw->mac.type == e1000_pch2lan)
404 return E1000_SUCCESS;
408 * e1000_read_phy_reg_i2c - Read PHY register using i2c
409 * @hw: pointer to the HW structure
410 * @offset: register offset to be read
411 * @data: pointer to the read data
413 * Reads the PHY register at offset using the i2c interface and stores the
414 * retrieved information in data.
416 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
418 struct e1000_phy_info *phy = &hw->phy;
421 DEBUGFUNC("e1000_read_phy_reg_i2c");
423 /* Set up Op-code, Phy Address, and register address in the I2CCMD
424 * register. The MAC will take care of interfacing with the
425 * PHY to retrieve the desired data.
427 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
428 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
429 (E1000_I2CCMD_OPCODE_READ));
431 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
433 /* Poll the ready bit to see if the I2C read completed */
434 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
436 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
437 if (i2ccmd & E1000_I2CCMD_READY)
440 if (!(i2ccmd & E1000_I2CCMD_READY)) {
441 DEBUGOUT("I2CCMD Read did not complete\n");
442 return -E1000_ERR_PHY;
444 if (i2ccmd & E1000_I2CCMD_ERROR) {
445 DEBUGOUT("I2CCMD Error bit set\n");
446 return -E1000_ERR_PHY;
449 /* Need to byte-swap the 16-bit value. */
450 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
452 return E1000_SUCCESS;
456 * e1000_write_phy_reg_i2c - Write PHY register using i2c
457 * @hw: pointer to the HW structure
458 * @offset: register offset to write to
459 * @data: data to write at register offset
461 * Writes the data to PHY register at the offset using the i2c interface.
463 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
465 struct e1000_phy_info *phy = &hw->phy;
467 u16 phy_data_swapped;
469 DEBUGFUNC("e1000_write_phy_reg_i2c");
471 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
472 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
473 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
475 return -E1000_ERR_CONFIG;
478 /* Swap the data bytes for the I2C interface */
479 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
481 /* Set up Op-code, Phy Address, and register address in the I2CCMD
482 * register. The MAC will take care of interfacing with the
483 * PHY to retrieve the desired data.
485 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
486 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
487 E1000_I2CCMD_OPCODE_WRITE |
490 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
492 /* Poll the ready bit to see if the I2C read completed */
493 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
495 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
496 if (i2ccmd & E1000_I2CCMD_READY)
499 if (!(i2ccmd & E1000_I2CCMD_READY)) {
500 DEBUGOUT("I2CCMD Write did not complete\n");
501 return -E1000_ERR_PHY;
503 if (i2ccmd & E1000_I2CCMD_ERROR) {
504 DEBUGOUT("I2CCMD Error bit set\n");
505 return -E1000_ERR_PHY;
508 return E1000_SUCCESS;
512 * e1000_read_sfp_data_byte - Reads SFP module data.
513 * @hw: pointer to the HW structure
514 * @offset: byte location offset to be read
515 * @data: read data buffer pointer
517 * Reads one byte from SFP module data stored
518 * in SFP resided EEPROM memory or SFP diagnostic area.
519 * Function should be called with
520 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
521 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
524 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
530 DEBUGFUNC("e1000_read_sfp_data_byte");
532 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
533 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
534 return -E1000_ERR_PHY;
537 /* Set up Op-code, EEPROM Address,in the I2CCMD
538 * register. The MAC will take care of interfacing with the
539 * EEPROM to retrieve the desired data.
541 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
542 E1000_I2CCMD_OPCODE_READ);
544 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
546 /* Poll the ready bit to see if the I2C read completed */
547 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
549 data_local = E1000_READ_REG(hw, E1000_I2CCMD);
550 if (data_local & E1000_I2CCMD_READY)
553 if (!(data_local & E1000_I2CCMD_READY)) {
554 DEBUGOUT("I2CCMD Read did not complete\n");
555 return -E1000_ERR_PHY;
557 if (data_local & E1000_I2CCMD_ERROR) {
558 DEBUGOUT("I2CCMD Error bit set\n");
559 return -E1000_ERR_PHY;
561 *data = (u8) data_local & 0xFF;
563 return E1000_SUCCESS;
567 * e1000_write_sfp_data_byte - Writes SFP module data.
568 * @hw: pointer to the HW structure
569 * @offset: byte location offset to write to
570 * @data: data to write
572 * Writes one byte to SFP module data stored
573 * in SFP resided EEPROM memory or SFP diagnostic area.
574 * Function should be called with
575 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
576 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
579 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
585 DEBUGFUNC("e1000_write_sfp_data_byte");
587 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
588 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
589 return -E1000_ERR_PHY;
591 /* The programming interface is 16 bits wide
592 * so we need to read the whole word first
593 * then update appropriate byte lane and write
594 * the updated word back.
596 /* Set up Op-code, EEPROM Address,in the I2CCMD
597 * register. The MAC will take care of interfacing
598 * with an EEPROM to write the data given.
600 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
601 E1000_I2CCMD_OPCODE_READ);
602 /* Set a command to read single word */
603 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
604 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
606 /* Poll the ready bit to see if lastly
607 * launched I2C operation completed
609 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
610 if (i2ccmd & E1000_I2CCMD_READY) {
611 /* Check if this is READ or WRITE phase */
612 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
613 E1000_I2CCMD_OPCODE_READ) {
614 /* Write the selected byte
615 * lane and update whole word
617 data_local = i2ccmd & 0xFF00;
620 E1000_I2CCMD_REG_ADDR_SHIFT) |
621 E1000_I2CCMD_OPCODE_WRITE | data_local);
622 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
628 if (!(i2ccmd & E1000_I2CCMD_READY)) {
629 DEBUGOUT("I2CCMD Write did not complete\n");
630 return -E1000_ERR_PHY;
632 if (i2ccmd & E1000_I2CCMD_ERROR) {
633 DEBUGOUT("I2CCMD Error bit set\n");
634 return -E1000_ERR_PHY;
636 return E1000_SUCCESS;
640 * e1000_read_phy_reg_m88 - Read m88 PHY register
641 * @hw: pointer to the HW structure
642 * @offset: register offset to be read
643 * @data: pointer to the read data
645 * Acquires semaphore, if necessary, then reads the PHY register at offset
646 * and storing the retrieved information in data. Release any acquired
647 * semaphores before exiting.
649 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
653 DEBUGFUNC("e1000_read_phy_reg_m88");
655 if (!hw->phy.ops.acquire)
656 return E1000_SUCCESS;
658 ret_val = hw->phy.ops.acquire(hw);
662 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
665 hw->phy.ops.release(hw);
671 * e1000_write_phy_reg_m88 - Write m88 PHY register
672 * @hw: pointer to the HW structure
673 * @offset: register offset to write to
674 * @data: data to write at register offset
676 * Acquires semaphore, if necessary, then writes the data to PHY register
677 * at the offset. Release any acquired semaphores before exiting.
679 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
683 DEBUGFUNC("e1000_write_phy_reg_m88");
685 if (!hw->phy.ops.acquire)
686 return E1000_SUCCESS;
688 ret_val = hw->phy.ops.acquire(hw);
692 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
695 hw->phy.ops.release(hw);
701 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
702 * @hw: pointer to the HW structure
703 * @page: page to set (shifted left when necessary)
705 * Sets PHY page required for PHY register access. Assumes semaphore is
706 * already acquired. Note, this function sets phy.addr to 1 so the caller
707 * must set it appropriately (if necessary) after this function returns.
709 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
711 DEBUGFUNC("e1000_set_page_igp");
713 DEBUGOUT1("Setting page 0x%x\n", page);
717 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
721 * __e1000_read_phy_reg_igp - Read igp PHY register
722 * @hw: pointer to the HW structure
723 * @offset: register offset to be read
724 * @data: pointer to the read data
725 * @locked: semaphore has already been acquired or not
727 * Acquires semaphore, if necessary, then reads the PHY register at offset
728 * and stores the retrieved information in data. Release any acquired
729 * semaphores before exiting.
731 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
734 s32 ret_val = E1000_SUCCESS;
736 DEBUGFUNC("__e1000_read_phy_reg_igp");
739 if (!hw->phy.ops.acquire)
740 return E1000_SUCCESS;
742 ret_val = hw->phy.ops.acquire(hw);
747 if (offset > MAX_PHY_MULTI_PAGE_REG)
748 ret_val = e1000_write_phy_reg_mdic(hw,
749 IGP01E1000_PHY_PAGE_SELECT,
752 ret_val = e1000_read_phy_reg_mdic(hw,
753 MAX_PHY_REG_ADDRESS & offset,
756 hw->phy.ops.release(hw);
762 * e1000_read_phy_reg_igp - Read igp PHY register
763 * @hw: pointer to the HW structure
764 * @offset: register offset to be read
765 * @data: pointer to the read data
767 * Acquires semaphore then reads the PHY register at offset and stores the
768 * retrieved information in data.
769 * Release the acquired semaphore before exiting.
771 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
773 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE);
777 * e1000_read_phy_reg_igp_locked - Read igp PHY register
778 * @hw: pointer to the HW structure
779 * @offset: register offset to be read
780 * @data: pointer to the read data
782 * Reads the PHY register at offset and stores the retrieved information
783 * in data. Assumes semaphore already acquired.
785 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
787 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE);
791 * e1000_write_phy_reg_igp - Write igp PHY register
792 * @hw: pointer to the HW structure
793 * @offset: register offset to write to
794 * @data: data to write at register offset
795 * @locked: semaphore has already been acquired or not
797 * Acquires semaphore, if necessary, then writes the data to PHY register
798 * at the offset. Release any acquired semaphores before exiting.
800 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
803 s32 ret_val = E1000_SUCCESS;
805 DEBUGFUNC("e1000_write_phy_reg_igp");
808 if (!hw->phy.ops.acquire)
809 return E1000_SUCCESS;
811 ret_val = hw->phy.ops.acquire(hw);
816 if (offset > MAX_PHY_MULTI_PAGE_REG)
817 ret_val = e1000_write_phy_reg_mdic(hw,
818 IGP01E1000_PHY_PAGE_SELECT,
821 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
825 hw->phy.ops.release(hw);
831 * e1000_write_phy_reg_igp - Write igp PHY register
832 * @hw: pointer to the HW structure
833 * @offset: register offset to write to
834 * @data: data to write at register offset
836 * Acquires semaphore then writes the data to PHY register
837 * at the offset. Release any acquired semaphores before exiting.
839 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
841 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE);
845 * e1000_write_phy_reg_igp_locked - Write igp PHY register
846 * @hw: pointer to the HW structure
847 * @offset: register offset to write to
848 * @data: data to write at register offset
850 * Writes the data to PHY register at the offset.
851 * Assumes semaphore already acquired.
853 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
855 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE);
859 * __e1000_read_kmrn_reg - Read kumeran register
860 * @hw: pointer to the HW structure
861 * @offset: register offset to be read
862 * @data: pointer to the read data
863 * @locked: semaphore has already been acquired or not
865 * Acquires semaphore, if necessary. Then reads the PHY register at offset
866 * using the kumeran interface. The information retrieved is stored in data.
867 * Release any acquired semaphores before exiting.
869 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
874 DEBUGFUNC("__e1000_read_kmrn_reg");
877 s32 ret_val = E1000_SUCCESS;
879 if (!hw->phy.ops.acquire)
880 return E1000_SUCCESS;
882 ret_val = hw->phy.ops.acquire(hw);
887 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
888 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
889 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
890 E1000_WRITE_FLUSH(hw);
894 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
895 *data = (u16)kmrnctrlsta;
898 hw->phy.ops.release(hw);
900 return E1000_SUCCESS;
904 * e1000_read_kmrn_reg_generic - Read kumeran register
905 * @hw: pointer to the HW structure
906 * @offset: register offset to be read
907 * @data: pointer to the read data
909 * Acquires semaphore then reads the PHY register at offset using the
910 * kumeran interface. The information retrieved is stored in data.
911 * Release the acquired semaphore before exiting.
913 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
915 return __e1000_read_kmrn_reg(hw, offset, data, FALSE);
919 * e1000_read_kmrn_reg_locked - Read kumeran register
920 * @hw: pointer to the HW structure
921 * @offset: register offset to be read
922 * @data: pointer to the read data
924 * Reads the PHY register at offset using the kumeran interface. The
925 * information retrieved is stored in data.
926 * Assumes semaphore already acquired.
928 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
930 return __e1000_read_kmrn_reg(hw, offset, data, TRUE);
934 * __e1000_write_kmrn_reg - Write kumeran register
935 * @hw: pointer to the HW structure
936 * @offset: register offset to write to
937 * @data: data to write at register offset
938 * @locked: semaphore has already been acquired or not
940 * Acquires semaphore, if necessary. Then write the data to PHY register
941 * at the offset using the kumeran interface. Release any acquired semaphores
944 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
949 DEBUGFUNC("e1000_write_kmrn_reg_generic");
952 s32 ret_val = E1000_SUCCESS;
954 if (!hw->phy.ops.acquire)
955 return E1000_SUCCESS;
957 ret_val = hw->phy.ops.acquire(hw);
962 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
963 E1000_KMRNCTRLSTA_OFFSET) | data;
964 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
965 E1000_WRITE_FLUSH(hw);
970 hw->phy.ops.release(hw);
972 return E1000_SUCCESS;
976 * e1000_write_kmrn_reg_generic - Write kumeran register
977 * @hw: pointer to the HW structure
978 * @offset: register offset to write to
979 * @data: data to write at register offset
981 * Acquires semaphore then writes the data to the PHY register at the offset
982 * using the kumeran interface. Release the acquired semaphore before exiting.
984 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
986 return __e1000_write_kmrn_reg(hw, offset, data, FALSE);
990 * e1000_write_kmrn_reg_locked - Write kumeran register
991 * @hw: pointer to the HW structure
992 * @offset: register offset to write to
993 * @data: data to write at register offset
995 * Write the data to PHY register at the offset using the kumeran interface.
996 * Assumes semaphore already acquired.
998 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
1000 return __e1000_write_kmrn_reg(hw, offset, data, TRUE);
1004 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
1005 * @hw: pointer to the HW structure
1007 * Sets up Master/slave mode
1009 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
1014 /* Resolve Master/Slave mode */
1015 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1019 /* load defaults for future use */
1020 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1021 ((phy_data & CR_1000T_MS_VALUE) ?
1022 e1000_ms_force_master :
1023 e1000_ms_force_slave) : e1000_ms_auto;
1025 switch (hw->phy.ms_type) {
1026 case e1000_ms_force_master:
1027 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1029 case e1000_ms_force_slave:
1030 phy_data |= CR_1000T_MS_ENABLE;
1031 phy_data &= ~(CR_1000T_MS_VALUE);
1034 phy_data &= ~CR_1000T_MS_ENABLE;
1040 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1044 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
1045 * @hw: pointer to the HW structure
1047 * Sets up Carrier-sense on Transmit and downshift values.
1049 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
1054 DEBUGFUNC("e1000_copper_link_setup_82577");
1056 if (hw->phy.type == e1000_phy_82580) {
1057 ret_val = hw->phy.ops.reset(hw);
1059 DEBUGOUT("Error resetting the PHY.\n");
1064 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1065 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1069 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1071 /* Enable downshift */
1072 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1074 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1078 /* Set MDI/MDIX mode */
1079 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1082 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
1084 * 0 - Auto (default)
1088 switch (hw->phy.mdix) {
1092 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
1096 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
1099 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1103 return e1000_set_master_slave_mode(hw);
1107 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1108 * @hw: pointer to the HW structure
1110 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1111 * and downshift values are set also.
1113 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1115 struct e1000_phy_info *phy = &hw->phy;
1119 DEBUGFUNC("e1000_copper_link_setup_m88");
1122 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1123 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1127 /* For BM PHY this bit is downshift enable */
1128 if (phy->type != e1000_phy_bm)
1129 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1132 * MDI/MDI-X = 0 (default)
1133 * 0 - Auto for all speeds
1136 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1138 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1140 switch (phy->mdix) {
1142 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1145 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1148 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1152 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1157 * disable_polarity_correction = 0 (default)
1158 * Automatic Correction for Reversed Cable Polarity
1162 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1163 if (phy->disable_polarity_correction)
1164 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1166 /* Enable downshift on BM (disabled by default) */
1167 if (phy->type == e1000_phy_bm) {
1168 /* For 82574/82583, first disable then enable downshift */
1169 if (phy->id == BME1000_E_PHY_ID_R2) {
1170 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
1171 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1175 /* Commit the changes. */
1176 ret_val = phy->ops.commit(hw);
1178 DEBUGOUT("Error committing the PHY changes\n");
1183 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
1186 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1190 if ((phy->type == e1000_phy_m88) &&
1191 (phy->revision < E1000_REVISION_4) &&
1192 (phy->id != BME1000_E_PHY_ID_R2)) {
1193 /* Force TX_CLK in the Extended PHY Specific Control Register
1196 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1201 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1203 if ((phy->revision == E1000_REVISION_2) &&
1204 (phy->id == M88E1111_I_PHY_ID)) {
1205 /* 82573L PHY - set the downshift counter to 5x. */
1206 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1207 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1209 /* Configure Master and Slave downshift values */
1210 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1211 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1212 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1213 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1215 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1221 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1222 /* Set PHY page 0, register 29 to 0x0003 */
1223 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1227 /* Set PHY page 0, register 30 to 0x0000 */
1228 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1233 /* Commit the changes. */
1234 ret_val = phy->ops.commit(hw);
1236 DEBUGOUT("Error committing the PHY changes\n");
1240 if (phy->type == e1000_phy_82578) {
1241 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1246 /* 82578 PHY - set the downshift count to 1x. */
1247 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
1248 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
1249 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1255 return E1000_SUCCESS;
1259 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1260 * @hw: pointer to the HW structure
1262 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1263 * Also enables and sets the downshift parameters.
1265 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1267 struct e1000_phy_info *phy = &hw->phy;
1271 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1274 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1275 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1280 * MDI/MDI-X = 0 (default)
1281 * 0 - Auto for all speeds
1284 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1286 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1288 switch (phy->mdix) {
1290 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1293 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1296 /* M88E1112 does not support this mode) */
1297 if (phy->id != M88E1112_E_PHY_ID) {
1298 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1303 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1308 * disable_polarity_correction = 0 (default)
1309 * Automatic Correction for Reversed Cable Polarity
1313 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1314 if (phy->disable_polarity_correction)
1315 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1317 /* Enable downshift and setting it to X6 */
1318 if (phy->id == M88E1543_E_PHY_ID) {
1319 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
1321 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1325 ret_val = phy->ops.commit(hw);
1327 DEBUGOUT("Error committing the PHY changes\n");
1332 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1333 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1334 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1336 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1340 /* Commit the changes. */
1341 ret_val = phy->ops.commit(hw);
1343 DEBUGOUT("Error committing the PHY changes\n");
1347 ret_val = e1000_set_master_slave_mode(hw);
1351 return E1000_SUCCESS;
1355 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1356 * @hw: pointer to the HW structure
1358 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1361 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1363 struct e1000_phy_info *phy = &hw->phy;
1367 DEBUGFUNC("e1000_copper_link_setup_igp");
1370 ret_val = hw->phy.ops.reset(hw);
1372 DEBUGOUT("Error resetting the PHY.\n");
1376 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1377 * timeout issues when LFS is enabled.
1381 /* The NVM settings will configure LPLU in D3 for
1384 if (phy->type == e1000_phy_igp) {
1385 /* disable lplu d3 during driver init */
1386 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE);
1388 DEBUGOUT("Error Disabling LPLU D3\n");
1393 /* disable lplu d0 during driver init */
1394 if (hw->phy.ops.set_d0_lplu_state) {
1395 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE);
1397 DEBUGOUT("Error Disabling LPLU D0\n");
1401 /* Configure mdi-mdix settings */
1402 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1406 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1408 switch (phy->mdix) {
1410 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1413 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1417 data |= IGP01E1000_PSCR_AUTO_MDIX;
1420 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1424 /* set auto-master slave resolution settings */
1425 if (hw->mac.autoneg) {
1426 /* when autonegotiation advertisement is only 1000Mbps then we
1427 * should disable SmartSpeed and enable Auto MasterSlave
1428 * resolution as hardware default.
1430 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1431 /* Disable SmartSpeed */
1432 ret_val = phy->ops.read_reg(hw,
1433 IGP01E1000_PHY_PORT_CONFIG,
1438 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1439 ret_val = phy->ops.write_reg(hw,
1440 IGP01E1000_PHY_PORT_CONFIG,
1445 /* Set auto Master/Slave resolution process */
1446 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1450 data &= ~CR_1000T_MS_ENABLE;
1451 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1456 ret_val = e1000_set_master_slave_mode(hw);
1463 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1464 * @hw: pointer to the HW structure
1466 * Reads the MII auto-neg advertisement register and/or the 1000T control
1467 * register and if the PHY is already setup for auto-negotiation, then
1468 * return successful. Otherwise, setup advertisement and flow control to
1469 * the appropriate values for the wanted auto-negotiation.
1471 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1473 struct e1000_phy_info *phy = &hw->phy;
1475 u16 mii_autoneg_adv_reg;
1476 u16 mii_1000t_ctrl_reg = 0;
1478 DEBUGFUNC("e1000_phy_setup_autoneg");
1480 phy->autoneg_advertised &= phy->autoneg_mask;
1482 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1483 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1487 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1488 /* Read the MII 1000Base-T Control Register (Address 9). */
1489 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1490 &mii_1000t_ctrl_reg);
1495 /* Need to parse both autoneg_advertised and fc and set up
1496 * the appropriate PHY registers. First we will parse for
1497 * autoneg_advertised software override. Since we can advertise
1498 * a plethora of combinations, we need to check each bit
1502 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1503 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1504 * the 1000Base-T Control Register (Address 9).
1506 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1507 NWAY_AR_100TX_HD_CAPS |
1508 NWAY_AR_10T_FD_CAPS |
1509 NWAY_AR_10T_HD_CAPS);
1510 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1512 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1514 /* Do we want to advertise 10 Mb Half Duplex? */
1515 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1516 DEBUGOUT("Advertise 10mb Half duplex\n");
1517 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1520 /* Do we want to advertise 10 Mb Full Duplex? */
1521 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1522 DEBUGOUT("Advertise 10mb Full duplex\n");
1523 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1526 /* Do we want to advertise 100 Mb Half Duplex? */
1527 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1528 DEBUGOUT("Advertise 100mb Half duplex\n");
1529 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1532 /* Do we want to advertise 100 Mb Full Duplex? */
1533 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1534 DEBUGOUT("Advertise 100mb Full duplex\n");
1535 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1538 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1539 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1540 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1542 /* Do we want to advertise 1000 Mb Full Duplex? */
1543 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1544 DEBUGOUT("Advertise 1000mb Full duplex\n");
1545 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1548 /* Check for a software override of the flow control settings, and
1549 * setup the PHY advertisement registers accordingly. If
1550 * auto-negotiation is enabled, then software will have to set the
1551 * "PAUSE" bits to the correct value in the Auto-Negotiation
1552 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1555 * The possible values of the "fc" parameter are:
1556 * 0: Flow control is completely disabled
1557 * 1: Rx flow control is enabled (we can receive pause frames
1558 * but not send pause frames).
1559 * 2: Tx flow control is enabled (we can send pause frames
1560 * but we do not support receiving pause frames).
1561 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1562 * other: No software override. The flow control configuration
1563 * in the EEPROM is used.
1565 switch (hw->fc.current_mode) {
1567 /* Flow control (Rx & Tx) is completely disabled by a
1568 * software over-ride.
1570 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1572 case e1000_fc_rx_pause:
1573 /* Rx Flow control is enabled, and Tx Flow control is
1574 * disabled, by a software over-ride.
1576 * Since there really isn't a way to advertise that we are
1577 * capable of Rx Pause ONLY, we will advertise that we
1578 * support both symmetric and asymmetric Rx PAUSE. Later
1579 * (in e1000_config_fc_after_link_up) we will disable the
1580 * hw's ability to send PAUSE frames.
1582 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1584 case e1000_fc_tx_pause:
1585 /* Tx Flow control is enabled, and Rx Flow control is
1586 * disabled, by a software over-ride.
1588 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1589 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1592 /* Flow control (both Rx and Tx) is enabled by a software
1595 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1598 DEBUGOUT("Flow control param set incorrectly\n");
1599 return -E1000_ERR_CONFIG;
1602 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1606 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1608 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1609 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1610 mii_1000t_ctrl_reg);
1616 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1617 * @hw: pointer to the HW structure
1619 * Performs initial bounds checking on autoneg advertisement parameter, then
1620 * configure to advertise the full capability. Setup the PHY to autoneg
1621 * and restart the negotiation process between the link partner. If
1622 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1624 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1626 struct e1000_phy_info *phy = &hw->phy;
1630 DEBUGFUNC("e1000_copper_link_autoneg");
1632 /* Perform some bounds checking on the autoneg advertisement
1635 phy->autoneg_advertised &= phy->autoneg_mask;
1637 /* If autoneg_advertised is zero, we assume it was not defaulted
1638 * by the calling code so we set to advertise full capability.
1640 if (!phy->autoneg_advertised)
1641 phy->autoneg_advertised = phy->autoneg_mask;
1643 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1644 ret_val = e1000_phy_setup_autoneg(hw);
1646 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1649 DEBUGOUT("Restarting Auto-Neg\n");
1651 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1652 * the Auto Neg Restart bit in the PHY control register.
1654 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1658 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1659 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1663 /* Does the user want to wait for Auto-Neg to complete here, or
1664 * check at a later time (for example, callback routine).
1666 if (phy->autoneg_wait_to_complete) {
1667 ret_val = e1000_wait_autoneg(hw);
1669 DEBUGOUT("Error while waiting for autoneg to complete\n");
1674 hw->mac.get_link_status = TRUE;
1680 * e1000_setup_copper_link_generic - Configure copper link settings
1681 * @hw: pointer to the HW structure
1683 * Calls the appropriate function to configure the link for auto-neg or forced
1684 * speed and duplex. Then we check for link, once link is established calls
1685 * to configure collision distance and flow control are called. If link is
1686 * not established, we return -E1000_ERR_PHY (-2).
1688 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1693 DEBUGFUNC("e1000_setup_copper_link_generic");
1695 if (hw->mac.autoneg) {
1696 /* Setup autoneg and flow control advertisement and perform
1699 ret_val = e1000_copper_link_autoneg(hw);
1703 /* PHY will be set to 10H, 10F, 100H or 100F
1704 * depending on user settings.
1706 DEBUGOUT("Forcing Speed and Duplex\n");
1707 ret_val = hw->phy.ops.force_speed_duplex(hw);
1709 DEBUGOUT("Error Forcing Speed and Duplex\n");
1714 /* Check link status. Wait up to 100 microseconds for link to become
1717 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1723 DEBUGOUT("Valid link established!!!\n");
1724 hw->mac.ops.config_collision_dist(hw);
1725 ret_val = e1000_config_fc_after_link_up_generic(hw);
1727 DEBUGOUT("Unable to establish link!!!\n");
1734 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1735 * @hw: pointer to the HW structure
1737 * Calls the PHY setup function to force speed and duplex. Clears the
1738 * auto-crossover to force MDI manually. Waits for link and returns
1739 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1741 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1743 struct e1000_phy_info *phy = &hw->phy;
1748 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1750 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1754 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1756 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1760 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1761 * forced whenever speed and duplex are forced.
1763 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1767 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1768 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1770 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1774 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1778 if (phy->autoneg_wait_to_complete) {
1779 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1781 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1787 DEBUGOUT("Link taking longer than expected.\n");
1790 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1798 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1799 * @hw: pointer to the HW structure
1801 * Calls the PHY setup function to force speed and duplex. Clears the
1802 * auto-crossover to force MDI manually. Resets the PHY to commit the
1803 * changes. If time expires while waiting for link up, we reset the DSP.
1804 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1805 * successful completion, else return corresponding error code.
1807 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1809 struct e1000_phy_info *phy = &hw->phy;
1814 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1816 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1817 if (phy->type != e1000_phy_i210) {
1818 /* Clear Auto-Crossover to force MDI manually. M88E1000
1819 * requires MDI forced whenever speed and duplex are forced.
1821 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1826 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1827 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1832 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1835 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1839 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1841 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1845 /* Reset the phy to commit changes. */
1846 ret_val = hw->phy.ops.commit(hw);
1850 if (phy->autoneg_wait_to_complete) {
1851 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1853 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1859 bool reset_dsp = TRUE;
1861 switch (hw->phy.id) {
1862 case I347AT4_E_PHY_ID:
1863 case M88E1340M_E_PHY_ID:
1864 case M88E1112_E_PHY_ID:
1865 case M88E1543_E_PHY_ID:
1866 case M88E1512_E_PHY_ID:
1871 if (hw->phy.type != e1000_phy_m88)
1877 DEBUGOUT("Link taking longer than expected.\n");
1879 /* We didn't get link.
1880 * Reset the DSP and cross our fingers.
1882 ret_val = phy->ops.write_reg(hw,
1883 M88E1000_PHY_PAGE_SELECT,
1887 ret_val = e1000_phy_reset_dsp_generic(hw);
1894 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1900 if (hw->phy.type != e1000_phy_m88)
1901 return E1000_SUCCESS;
1903 if (hw->phy.id == I347AT4_E_PHY_ID ||
1904 hw->phy.id == M88E1340M_E_PHY_ID ||
1905 hw->phy.id == M88E1112_E_PHY_ID)
1906 return E1000_SUCCESS;
1907 if (hw->phy.id == I210_I_PHY_ID)
1908 return E1000_SUCCESS;
1909 if ((hw->phy.id == M88E1543_E_PHY_ID) ||
1910 (hw->phy.id == M88E1512_E_PHY_ID))
1911 return E1000_SUCCESS;
1912 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1916 /* Resetting the phy means we need to re-force TX_CLK in the
1917 * Extended PHY Specific Control Register to 25MHz clock from
1918 * the reset value of 2.5MHz.
1920 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1921 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1925 /* In addition, we must re-enable CRS on Tx for both half and full
1928 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1932 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1933 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1939 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1940 * @hw: pointer to the HW structure
1942 * Forces the speed and duplex settings of the PHY.
1943 * This is a function pointer entry point only called by
1944 * PHY setup routines.
1946 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1948 struct e1000_phy_info *phy = &hw->phy;
1953 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1955 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1959 e1000_phy_force_speed_duplex_setup(hw, &data);
1961 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1965 /* Disable MDI-X support for 10/100 */
1966 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1970 data &= ~IFE_PMC_AUTO_MDIX;
1971 data &= ~IFE_PMC_FORCE_MDIX;
1973 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1977 DEBUGOUT1("IFE PMC: %X\n", data);
1981 if (phy->autoneg_wait_to_complete) {
1982 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1984 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1990 DEBUGOUT("Link taking longer than expected.\n");
1993 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1999 return E1000_SUCCESS;
2003 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
2004 * @hw: pointer to the HW structure
2005 * @phy_ctrl: pointer to current value of PHY_CONTROL
2007 * Forces speed and duplex on the PHY by doing the following: disable flow
2008 * control, force speed/duplex on the MAC, disable auto speed detection,
2009 * disable auto-negotiation, configure duplex, configure speed, configure
2010 * the collision distance, write configuration to CTRL register. The
2011 * caller must write to the PHY_CONTROL register for these settings to
2014 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
2016 struct e1000_mac_info *mac = &hw->mac;
2019 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
2021 /* Turn off flow control when forcing speed/duplex */
2022 hw->fc.current_mode = e1000_fc_none;
2024 /* Force speed/duplex on the mac */
2025 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2026 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2027 ctrl &= ~E1000_CTRL_SPD_SEL;
2029 /* Disable Auto Speed Detection */
2030 ctrl &= ~E1000_CTRL_ASDE;
2032 /* Disable autoneg on the phy */
2033 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
2035 /* Forcing Full or Half Duplex? */
2036 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
2037 ctrl &= ~E1000_CTRL_FD;
2038 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
2039 DEBUGOUT("Half Duplex\n");
2041 ctrl |= E1000_CTRL_FD;
2042 *phy_ctrl |= MII_CR_FULL_DUPLEX;
2043 DEBUGOUT("Full Duplex\n");
2046 /* Forcing 10mb or 100mb? */
2047 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
2048 ctrl |= E1000_CTRL_SPD_100;
2049 *phy_ctrl |= MII_CR_SPEED_100;
2050 *phy_ctrl &= ~MII_CR_SPEED_1000;
2051 DEBUGOUT("Forcing 100mb\n");
2053 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2054 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2055 DEBUGOUT("Forcing 10mb\n");
2058 hw->mac.ops.config_collision_dist(hw);
2060 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2064 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
2065 * @hw: pointer to the HW structure
2066 * @active: boolean used to enable/disable lplu
2068 * Success returns 0, Failure returns 1
2070 * The low power link up (lplu) state is set to the power management level D3
2071 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
2072 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2073 * is used during Dx states where the power conservation is most important.
2074 * During driver activity, SmartSpeed should be enabled so performance is
2077 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
2079 struct e1000_phy_info *phy = &hw->phy;
2083 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
2085 if (!hw->phy.ops.read_reg)
2086 return E1000_SUCCESS;
2088 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2093 data &= ~IGP02E1000_PM_D3_LPLU;
2094 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2098 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2099 * during Dx states where the power conservation is most
2100 * important. During driver activity we should enable
2101 * SmartSpeed, so performance is maintained.
2103 if (phy->smart_speed == e1000_smart_speed_on) {
2104 ret_val = phy->ops.read_reg(hw,
2105 IGP01E1000_PHY_PORT_CONFIG,
2110 data |= IGP01E1000_PSCFR_SMART_SPEED;
2111 ret_val = phy->ops.write_reg(hw,
2112 IGP01E1000_PHY_PORT_CONFIG,
2116 } else if (phy->smart_speed == e1000_smart_speed_off) {
2117 ret_val = phy->ops.read_reg(hw,
2118 IGP01E1000_PHY_PORT_CONFIG,
2123 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2124 ret_val = phy->ops.write_reg(hw,
2125 IGP01E1000_PHY_PORT_CONFIG,
2130 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2131 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2132 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2133 data |= IGP02E1000_PM_D3_LPLU;
2134 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2139 /* When LPLU is enabled, we should disable SmartSpeed */
2140 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2145 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2146 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2154 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
2155 * @hw: pointer to the HW structure
2157 * Success returns 0, Failure returns 1
2159 * A downshift is detected by querying the PHY link health.
2161 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
2163 struct e1000_phy_info *phy = &hw->phy;
2165 u16 phy_data, offset, mask;
2167 DEBUGFUNC("e1000_check_downshift_generic");
2169 switch (phy->type) {
2170 case e1000_phy_i210:
2172 case e1000_phy_gg82563:
2174 case e1000_phy_82578:
2175 offset = M88E1000_PHY_SPEC_STATUS;
2176 mask = M88E1000_PSSR_DOWNSHIFT;
2179 case e1000_phy_igp_2:
2180 case e1000_phy_igp_3:
2181 offset = IGP01E1000_PHY_LINK_HEALTH;
2182 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
2185 /* speed downshift not supported */
2186 phy->speed_downgraded = FALSE;
2187 return E1000_SUCCESS;
2190 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2193 phy->speed_downgraded = !!(phy_data & mask);
2199 * e1000_check_polarity_m88 - Checks the polarity.
2200 * @hw: pointer to the HW structure
2202 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2204 * Polarity is determined based on the PHY specific status register.
2206 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2208 struct e1000_phy_info *phy = &hw->phy;
2212 DEBUGFUNC("e1000_check_polarity_m88");
2214 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2217 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
2218 ? e1000_rev_polarity_reversed
2219 : e1000_rev_polarity_normal);
2225 * e1000_check_polarity_igp - Checks the polarity.
2226 * @hw: pointer to the HW structure
2228 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2230 * Polarity is determined based on the PHY port status register, and the
2231 * current speed (since there is no polarity at 100Mbps).
2233 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2235 struct e1000_phy_info *phy = &hw->phy;
2237 u16 data, offset, mask;
2239 DEBUGFUNC("e1000_check_polarity_igp");
2241 /* Polarity is determined based on the speed of
2244 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2248 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2249 IGP01E1000_PSSR_SPEED_1000MBPS) {
2250 offset = IGP01E1000_PHY_PCS_INIT_REG;
2251 mask = IGP01E1000_PHY_POLARITY_MASK;
2253 /* This really only applies to 10Mbps since
2254 * there is no polarity for 100Mbps (always 0).
2256 offset = IGP01E1000_PHY_PORT_STATUS;
2257 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
2260 ret_val = phy->ops.read_reg(hw, offset, &data);
2263 phy->cable_polarity = ((data & mask)
2264 ? e1000_rev_polarity_reversed
2265 : e1000_rev_polarity_normal);
2271 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2272 * @hw: pointer to the HW structure
2274 * Polarity is determined on the polarity reversal feature being enabled.
2276 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2278 struct e1000_phy_info *phy = &hw->phy;
2280 u16 phy_data, offset, mask;
2282 DEBUGFUNC("e1000_check_polarity_ife");
2284 /* Polarity is determined based on the reversal feature being enabled.
2286 if (phy->polarity_correction) {
2287 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2288 mask = IFE_PESC_POLARITY_REVERSED;
2290 offset = IFE_PHY_SPECIAL_CONTROL;
2291 mask = IFE_PSC_FORCE_POLARITY;
2294 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2297 phy->cable_polarity = ((phy_data & mask)
2298 ? e1000_rev_polarity_reversed
2299 : e1000_rev_polarity_normal);
2305 * e1000_wait_autoneg - Wait for auto-neg completion
2306 * @hw: pointer to the HW structure
2308 * Waits for auto-negotiation to complete or for the auto-negotiation time
2309 * limit to expire, which ever happens first.
2311 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2313 s32 ret_val = E1000_SUCCESS;
2316 DEBUGFUNC("e1000_wait_autoneg");
2318 if (!hw->phy.ops.read_reg)
2319 return E1000_SUCCESS;
2321 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2322 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2323 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2326 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2329 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2334 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2341 * e1000_phy_has_link_generic - Polls PHY for link
2342 * @hw: pointer to the HW structure
2343 * @iterations: number of times to poll for link
2344 * @usec_interval: delay between polling attempts
2345 * @success: pointer to whether polling was successful or not
2347 * Polls the PHY status register for link, 'iterations' number of times.
2349 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2350 u32 usec_interval, bool *success)
2352 s32 ret_val = E1000_SUCCESS;
2355 DEBUGFUNC("e1000_phy_has_link_generic");
2357 if (!hw->phy.ops.read_reg)
2358 return E1000_SUCCESS;
2360 for (i = 0; i < iterations; i++) {
2361 /* Some PHYs require the PHY_STATUS register to be read
2362 * twice due to the link bit being sticky. No harm doing
2363 * it across the board.
2365 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2367 /* If the first read fails, another entity may have
2368 * ownership of the resources, wait and try again to
2369 * see if they have relinquished the resources yet.
2371 if (usec_interval >= 1000)
2372 msec_delay(usec_interval/1000);
2374 usec_delay(usec_interval);
2376 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2379 if (phy_status & MII_SR_LINK_STATUS)
2381 if (usec_interval >= 1000)
2382 msec_delay(usec_interval/1000);
2384 usec_delay(usec_interval);
2387 *success = (i < iterations);
2393 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2394 * @hw: pointer to the HW structure
2396 * Reads the PHY specific status register to retrieve the cable length
2397 * information. The cable length is determined by averaging the minimum and
2398 * maximum values to get the "average" cable length. The m88 PHY has four
2399 * possible cable length values, which are:
2400 * Register Value Cable Length
2404 * 3 110 - 140 meters
2407 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2409 struct e1000_phy_info *phy = &hw->phy;
2411 u16 phy_data, index;
2413 DEBUGFUNC("e1000_get_cable_length_m88");
2415 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2419 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2420 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2422 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2423 return -E1000_ERR_PHY;
2425 phy->min_cable_length = e1000_m88_cable_length_table[index];
2426 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2428 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2430 return E1000_SUCCESS;
2433 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2435 struct e1000_phy_info *phy = &hw->phy;
2437 u16 phy_data, phy_data2, is_cm;
2438 u16 index, default_page;
2440 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2442 switch (hw->phy.id) {
2444 /* Get cable length from PHY Cable Diagnostics Control Reg */
2445 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2446 (I347AT4_PCDL + phy->addr),
2451 /* Check if the unit of cable length is meters or cm */
2452 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2453 I347AT4_PCDC, &phy_data2);
2457 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2459 /* Populate the phy structure with cable length in meters */
2460 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2461 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2462 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2464 case M88E1543_E_PHY_ID:
2465 case M88E1512_E_PHY_ID:
2466 case M88E1340M_E_PHY_ID:
2467 case I347AT4_E_PHY_ID:
2468 /* Remember the original page select and set it to 7 */
2469 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2474 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2478 /* Get cable length from PHY Cable Diagnostics Control Reg */
2479 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2484 /* Check if the unit of cable length is meters or cm */
2485 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2489 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2491 /* Populate the phy structure with cable length in meters */
2492 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2493 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2494 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2496 /* Reset the page select to its original value */
2497 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2503 case M88E1112_E_PHY_ID:
2504 /* Remember the original page select and set it to 5 */
2505 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2510 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2514 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2519 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2520 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2522 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2523 return -E1000_ERR_PHY;
2525 phy->min_cable_length = e1000_m88_cable_length_table[index];
2526 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2528 phy->cable_length = (phy->min_cable_length +
2529 phy->max_cable_length) / 2;
2531 /* Reset the page select to its original value */
2532 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2539 return -E1000_ERR_PHY;
2546 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2547 * @hw: pointer to the HW structure
2549 * The automatic gain control (agc) normalizes the amplitude of the
2550 * received signal, adjusting for the attenuation produced by the
2551 * cable. By reading the AGC registers, which represent the
2552 * combination of coarse and fine gain value, the value can be put
2553 * into a lookup table to obtain the approximate cable length
2556 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2558 struct e1000_phy_info *phy = &hw->phy;
2560 u16 phy_data, i, agc_value = 0;
2561 u16 cur_agc_index, max_agc_index = 0;
2562 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2563 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2564 IGP02E1000_PHY_AGC_A,
2565 IGP02E1000_PHY_AGC_B,
2566 IGP02E1000_PHY_AGC_C,
2567 IGP02E1000_PHY_AGC_D
2570 DEBUGFUNC("e1000_get_cable_length_igp_2");
2572 /* Read the AGC registers for all channels */
2573 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2574 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2578 /* Getting bits 15:9, which represent the combination of
2579 * coarse and fine gain values. The result is a number
2580 * that can be put into the lookup table to obtain the
2581 * approximate cable length.
2583 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2584 IGP02E1000_AGC_LENGTH_MASK);
2586 /* Array index bound check. */
2587 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2588 (cur_agc_index == 0))
2589 return -E1000_ERR_PHY;
2591 /* Remove min & max AGC values from calculation. */
2592 if (e1000_igp_2_cable_length_table[min_agc_index] >
2593 e1000_igp_2_cable_length_table[cur_agc_index])
2594 min_agc_index = cur_agc_index;
2595 if (e1000_igp_2_cable_length_table[max_agc_index] <
2596 e1000_igp_2_cable_length_table[cur_agc_index])
2597 max_agc_index = cur_agc_index;
2599 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2602 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2603 e1000_igp_2_cable_length_table[max_agc_index]);
2604 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2606 /* Calculate cable length with the error range of +/- 10 meters. */
2607 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2608 (agc_value - IGP02E1000_AGC_RANGE) : 0);
2609 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2611 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2613 return E1000_SUCCESS;
2617 * e1000_get_phy_info_m88 - Retrieve PHY information
2618 * @hw: pointer to the HW structure
2620 * Valid for only copper links. Read the PHY status register (sticky read)
2621 * to verify that link is up. Read the PHY special control register to
2622 * determine the polarity and 10base-T extended distance. Read the PHY
2623 * special status register to determine MDI/MDIx and current speed. If
2624 * speed is 1000, then determine cable length, local and remote receiver.
2626 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2628 struct e1000_phy_info *phy = &hw->phy;
2633 DEBUGFUNC("e1000_get_phy_info_m88");
2635 if (phy->media_type != e1000_media_type_copper) {
2636 DEBUGOUT("Phy info is only valid for copper media\n");
2637 return -E1000_ERR_CONFIG;
2640 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2645 DEBUGOUT("Phy info is only valid if link is up\n");
2646 return -E1000_ERR_CONFIG;
2649 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2653 phy->polarity_correction = !!(phy_data &
2654 M88E1000_PSCR_POLARITY_REVERSAL);
2656 ret_val = e1000_check_polarity_m88(hw);
2660 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2664 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2666 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2667 ret_val = hw->phy.ops.get_cable_length(hw);
2671 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2675 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2676 ? e1000_1000t_rx_status_ok
2677 : e1000_1000t_rx_status_not_ok;
2679 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2680 ? e1000_1000t_rx_status_ok
2681 : e1000_1000t_rx_status_not_ok;
2683 /* Set values to "undefined" */
2684 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2685 phy->local_rx = e1000_1000t_rx_status_undefined;
2686 phy->remote_rx = e1000_1000t_rx_status_undefined;
2693 * e1000_get_phy_info_igp - Retrieve igp PHY information
2694 * @hw: pointer to the HW structure
2696 * Read PHY status to determine if link is up. If link is up, then
2697 * set/determine 10base-T extended distance and polarity correction. Read
2698 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2699 * determine on the cable length, local and remote receiver.
2701 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2703 struct e1000_phy_info *phy = &hw->phy;
2708 DEBUGFUNC("e1000_get_phy_info_igp");
2710 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2715 DEBUGOUT("Phy info is only valid if link is up\n");
2716 return -E1000_ERR_CONFIG;
2719 phy->polarity_correction = TRUE;
2721 ret_val = e1000_check_polarity_igp(hw);
2725 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2729 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2731 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2732 IGP01E1000_PSSR_SPEED_1000MBPS) {
2733 ret_val = phy->ops.get_cable_length(hw);
2737 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2741 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2742 ? e1000_1000t_rx_status_ok
2743 : e1000_1000t_rx_status_not_ok;
2745 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2746 ? e1000_1000t_rx_status_ok
2747 : e1000_1000t_rx_status_not_ok;
2749 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2750 phy->local_rx = e1000_1000t_rx_status_undefined;
2751 phy->remote_rx = e1000_1000t_rx_status_undefined;
2758 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2759 * @hw: pointer to the HW structure
2761 * Populates "phy" structure with various feature states.
2763 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2765 struct e1000_phy_info *phy = &hw->phy;
2770 DEBUGFUNC("e1000_get_phy_info_ife");
2772 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2777 DEBUGOUT("Phy info is only valid if link is up\n");
2778 return -E1000_ERR_CONFIG;
2781 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2784 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2786 if (phy->polarity_correction) {
2787 ret_val = e1000_check_polarity_ife(hw);
2791 /* Polarity is forced */
2792 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2793 ? e1000_rev_polarity_reversed
2794 : e1000_rev_polarity_normal);
2797 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2801 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2803 /* The following parameters are undefined for 10/100 operation. */
2804 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2805 phy->local_rx = e1000_1000t_rx_status_undefined;
2806 phy->remote_rx = e1000_1000t_rx_status_undefined;
2808 return E1000_SUCCESS;
2812 * e1000_phy_sw_reset_generic - PHY software reset
2813 * @hw: pointer to the HW structure
2815 * Does a software reset of the PHY by reading the PHY control register and
2816 * setting/write the control register reset bit to the PHY.
2818 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2823 DEBUGFUNC("e1000_phy_sw_reset_generic");
2825 if (!hw->phy.ops.read_reg)
2826 return E1000_SUCCESS;
2828 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2832 phy_ctrl |= MII_CR_RESET;
2833 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2843 * e1000_phy_hw_reset_generic - PHY hardware reset
2844 * @hw: pointer to the HW structure
2846 * Verify the reset block is not blocking us from resetting. Acquire
2847 * semaphore (if necessary) and read/set/write the device control reset
2848 * bit in the PHY. Wait the appropriate delay time for the device to
2849 * reset and release the semaphore (if necessary).
2851 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2853 struct e1000_phy_info *phy = &hw->phy;
2857 DEBUGFUNC("e1000_phy_hw_reset_generic");
2859 if (phy->ops.check_reset_block) {
2860 ret_val = phy->ops.check_reset_block(hw);
2862 return E1000_SUCCESS;
2865 ret_val = phy->ops.acquire(hw);
2869 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2870 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2871 E1000_WRITE_FLUSH(hw);
2873 usec_delay(phy->reset_delay_us);
2875 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2876 E1000_WRITE_FLUSH(hw);
2880 phy->ops.release(hw);
2882 return phy->ops.get_cfg_done(hw);
2886 * e1000_get_cfg_done_generic - Generic configuration done
2887 * @hw: pointer to the HW structure
2889 * Generic function to wait 10 milli-seconds for configuration to complete
2890 * and return success.
2892 s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2894 DEBUGFUNC("e1000_get_cfg_done_generic");
2898 return E1000_SUCCESS;
2902 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2903 * @hw: pointer to the HW structure
2905 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2907 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2909 DEBUGOUT("Running IGP 3 PHY init script\n");
2911 /* PHY init IGP 3 */
2912 /* Enable rise/fall, 10-mode work in class-A */
2913 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2914 /* Remove all caps from Replica path filter */
2915 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2916 /* Bias trimming for ADC, AFE and Driver (Default) */
2917 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2918 /* Increase Hybrid poly bias */
2919 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2920 /* Add 4% to Tx amplitude in Gig mode */
2921 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2922 /* Disable trimming (TTT) */
2923 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2924 /* Poly DC correction to 94.6% + 2% for all channels */
2925 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2926 /* ABS DC correction to 95.9% */
2927 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2928 /* BG temp curve trim */
2929 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2930 /* Increasing ADC OPAMP stage 1 currents to max */
2931 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2932 /* Force 1000 ( required for enabling PHY regs configuration) */
2933 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2934 /* Set upd_freq to 6 */
2935 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2937 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2938 /* Disable adaptive fixed FFE (Default) */
2939 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2940 /* Enable FFE hysteresis */
2941 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2942 /* Fixed FFE for short cable lengths */
2943 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2944 /* Fixed FFE for medium cable lengths */
2945 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2946 /* Fixed FFE for long cable lengths */
2947 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2948 /* Enable Adaptive Clip Threshold */
2949 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2950 /* AHT reset limit to 1 */
2951 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2952 /* Set AHT master delay to 127 msec */
2953 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2954 /* Set scan bits for AHT */
2955 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2956 /* Set AHT Preset bits */
2957 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2958 /* Change integ_factor of channel A to 3 */
2959 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2960 /* Change prop_factor of channels BCD to 8 */
2961 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2962 /* Change cg_icount + enable integbp for channels BCD */
2963 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2964 /* Change cg_icount + enable integbp + change prop_factor_master
2965 * to 8 for channel A
2967 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2968 /* Disable AHT in Slave mode on channel A */
2969 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2970 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2973 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2974 /* Enable restart AN on an1000_dis change */
2975 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2976 /* Enable wh_fifo read clock in 10/100 modes */
2977 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2978 /* Restart AN, Speed selection is 1000 */
2979 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2981 return E1000_SUCCESS;
2985 * e1000_get_phy_type_from_id - Get PHY type from id
2986 * @phy_id: phy_id read from the phy
2988 * Returns the phy type from the id.
2990 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2992 enum e1000_phy_type phy_type = e1000_phy_unknown;
2995 case M88E1000_I_PHY_ID:
2996 case M88E1000_E_PHY_ID:
2997 case M88E1111_I_PHY_ID:
2998 case M88E1011_I_PHY_ID:
2999 case M88E1543_E_PHY_ID:
3000 case M88E1512_E_PHY_ID:
3001 case I347AT4_E_PHY_ID:
3002 case M88E1112_E_PHY_ID:
3003 case M88E1340M_E_PHY_ID:
3004 phy_type = e1000_phy_m88;
3006 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
3007 phy_type = e1000_phy_igp_2;
3009 case GG82563_E_PHY_ID:
3010 phy_type = e1000_phy_gg82563;
3012 case IGP03E1000_E_PHY_ID:
3013 phy_type = e1000_phy_igp_3;
3016 case IFE_PLUS_E_PHY_ID:
3017 case IFE_C_E_PHY_ID:
3018 phy_type = e1000_phy_ife;
3020 case BME1000_E_PHY_ID:
3021 case BME1000_E_PHY_ID_R2:
3022 phy_type = e1000_phy_bm;
3024 case I82578_E_PHY_ID:
3025 phy_type = e1000_phy_82578;
3027 case I82577_E_PHY_ID:
3028 phy_type = e1000_phy_82577;
3030 case I82579_E_PHY_ID:
3031 phy_type = e1000_phy_82579;
3034 phy_type = e1000_phy_i217;
3036 case I82580_I_PHY_ID:
3037 phy_type = e1000_phy_82580;
3040 phy_type = e1000_phy_i210;
3043 phy_type = e1000_phy_unknown;
3050 * e1000_determine_phy_address - Determines PHY address.
3051 * @hw: pointer to the HW structure
3053 * This uses a trial and error method to loop through possible PHY
3054 * addresses. It tests each by reading the PHY ID registers and
3055 * checking for a match.
3057 s32 e1000_determine_phy_address(struct e1000_hw *hw)
3061 enum e1000_phy_type phy_type = e1000_phy_unknown;
3063 hw->phy.id = phy_type;
3065 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
3066 hw->phy.addr = phy_addr;
3070 e1000_get_phy_id(hw);
3071 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3073 /* If phy_type is valid, break - we found our
3076 if (phy_type != e1000_phy_unknown)
3077 return E1000_SUCCESS;
3084 return -E1000_ERR_PHY_TYPE;
3088 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
3089 * @page: page to access
3091 * Returns the phy address for the page requested.
3093 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
3097 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
3104 * e1000_write_phy_reg_bm - Write BM PHY register
3105 * @hw: pointer to the HW structure
3106 * @offset: register offset to write to
3107 * @data: data to write at register offset
3109 * Acquires semaphore, if necessary, then writes the data to PHY register
3110 * at the offset. Release any acquired semaphores before exiting.
3112 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
3115 u32 page = offset >> IGP_PAGE_SHIFT;
3117 DEBUGFUNC("e1000_write_phy_reg_bm");
3119 ret_val = hw->phy.ops.acquire(hw);
3123 /* Page 800 works differently than the rest so it has its own func */
3124 if (page == BM_WUC_PAGE) {
3125 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3130 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3132 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3133 u32 page_shift, page_select;
3135 /* Page select is register 31 for phy address 1 and 22 for
3136 * phy address 2 and 3. Page select is shifted only for
3139 if (hw->phy.addr == 1) {
3140 page_shift = IGP_PAGE_SHIFT;
3141 page_select = IGP01E1000_PHY_PAGE_SELECT;
3144 page_select = BM_PHY_PAGE_SELECT;
3147 /* Page is shifted left, PHY expects (page x 32) */
3148 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3149 (page << page_shift));
3154 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3158 hw->phy.ops.release(hw);
3163 * e1000_read_phy_reg_bm - Read BM PHY register
3164 * @hw: pointer to the HW structure
3165 * @offset: register offset to be read
3166 * @data: pointer to the read data
3168 * Acquires semaphore, if necessary, then reads the PHY register at offset
3169 * and storing the retrieved information in data. Release any acquired
3170 * semaphores before exiting.
3172 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
3175 u32 page = offset >> IGP_PAGE_SHIFT;
3177 DEBUGFUNC("e1000_read_phy_reg_bm");
3179 ret_val = hw->phy.ops.acquire(hw);
3183 /* Page 800 works differently than the rest so it has its own func */
3184 if (page == BM_WUC_PAGE) {
3185 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3190 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3192 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3193 u32 page_shift, page_select;
3195 /* Page select is register 31 for phy address 1 and 22 for
3196 * phy address 2 and 3. Page select is shifted only for
3199 if (hw->phy.addr == 1) {
3200 page_shift = IGP_PAGE_SHIFT;
3201 page_select = IGP01E1000_PHY_PAGE_SELECT;
3204 page_select = BM_PHY_PAGE_SELECT;
3207 /* Page is shifted left, PHY expects (page x 32) */
3208 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3209 (page << page_shift));
3214 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3217 hw->phy.ops.release(hw);
3222 * e1000_read_phy_reg_bm2 - Read BM PHY register
3223 * @hw: pointer to the HW structure
3224 * @offset: register offset to be read
3225 * @data: pointer to the read data
3227 * Acquires semaphore, if necessary, then reads the PHY register at offset
3228 * and storing the retrieved information in data. Release any acquired
3229 * semaphores before exiting.
3231 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
3234 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3236 DEBUGFUNC("e1000_read_phy_reg_bm2");
3238 ret_val = hw->phy.ops.acquire(hw);
3242 /* Page 800 works differently than the rest so it has its own func */
3243 if (page == BM_WUC_PAGE) {
3244 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3251 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3252 /* Page is shifted left, PHY expects (page x 32) */
3253 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3260 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3263 hw->phy.ops.release(hw);
3268 * e1000_write_phy_reg_bm2 - Write BM PHY register
3269 * @hw: pointer to the HW structure
3270 * @offset: register offset to write to
3271 * @data: data to write at register offset
3273 * Acquires semaphore, if necessary, then writes the data to PHY register
3274 * at the offset. Release any acquired semaphores before exiting.
3276 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
3279 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3281 DEBUGFUNC("e1000_write_phy_reg_bm2");
3283 ret_val = hw->phy.ops.acquire(hw);
3287 /* Page 800 works differently than the rest so it has its own func */
3288 if (page == BM_WUC_PAGE) {
3289 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3296 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3297 /* Page is shifted left, PHY expects (page x 32) */
3298 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3305 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3309 hw->phy.ops.release(hw);
3314 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
3315 * @hw: pointer to the HW structure
3316 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
3318 * Assumes semaphore already acquired and phy_reg points to a valid memory
3319 * address to store contents of the BM_WUC_ENABLE_REG register.
3321 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3326 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm");
3329 return -E1000_ERR_PARAM;
3331 /* All page select, port ctrl and wakeup registers use phy address 1 */
3334 /* Select Port Control Registers page */
3335 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3337 DEBUGOUT("Could not set Port Control page\n");
3341 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3343 DEBUGOUT2("Could not read PHY register %d.%d\n",
3344 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3348 /* Enable both PHY wakeup mode and Wakeup register page writes.
3349 * Prevent a power state change by disabling ME and Host PHY wakeup.
3352 temp |= BM_WUC_ENABLE_BIT;
3353 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
3355 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3357 DEBUGOUT2("Could not write PHY register %d.%d\n",
3358 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3362 /* Select Host Wakeup Registers page - caller now able to write
3363 * registers on the Wakeup registers page
3365 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3369 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
3370 * @hw: pointer to the HW structure
3371 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
3373 * Restore BM_WUC_ENABLE_REG to its original value.
3375 * Assumes semaphore already acquired and *phy_reg is the contents of the
3376 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
3379 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3383 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm");
3386 return -E1000_ERR_PARAM;
3388 /* Select Port Control Registers page */
3389 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3391 DEBUGOUT("Could not set Port Control page\n");
3395 /* Restore 769.17 to its original value */
3396 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3398 DEBUGOUT2("Could not restore PHY register %d.%d\n",
3399 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3405 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
3406 * @hw: pointer to the HW structure
3407 * @offset: register offset to be read or written
3408 * @data: pointer to the data to read or write
3409 * @read: determines if operation is read or write
3410 * @page_set: BM_WUC_PAGE already set and access enabled
3412 * Read the PHY register at offset and store the retrieved information in
3413 * data, or write data to PHY register at offset. Note the procedure to
3414 * access the PHY wakeup registers is different than reading the other PHY
3415 * registers. It works as such:
3416 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
3417 * 2) Set page to 800 for host (801 if we were manageability)
3418 * 3) Write the address using the address opcode (0x11)
3419 * 4) Read or write the data using the data opcode (0x12)
3420 * 5) Restore 769.17.2 to its original value
3422 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
3423 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
3425 * Assumes semaphore is already acquired. When page_set==TRUE, assumes
3426 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
3427 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
3429 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
3430 u16 *data, bool read, bool page_set)
3433 u16 reg = BM_PHY_REG_NUM(offset);
3434 u16 page = BM_PHY_REG_PAGE(offset);
3437 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
3439 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
3440 if ((hw->mac.type == e1000_pchlan) &&
3441 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
3442 DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
3446 /* Enable access to PHY wakeup registers */
3447 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3449 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3454 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3456 /* Write the Wakeup register page offset value using opcode 0x11 */
3457 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3459 DEBUGOUT1("Could not write address opcode to page %d\n", page);
3464 /* Read the Wakeup register page value using opcode 0x12 */
3465 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3468 /* Write the Wakeup register page value using opcode 0x12 */
3469 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3474 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3479 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3485 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3486 * @hw: pointer to the HW structure
3488 * In the case of a PHY power down to save power, or to turn off link during a
3489 * driver unload, or wake on lan is not enabled, restore the link to previous
3492 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3496 /* The PHY will retain its settings across a power down/up cycle */
3497 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3498 mii_reg &= ~MII_CR_POWER_DOWN;
3499 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3503 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3504 * @hw: pointer to the HW structure
3506 * In the case of a PHY power down to save power, or to turn off link during a
3507 * driver unload, or wake on lan is not enabled, restore the link to previous
3510 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3514 /* The PHY will retain its settings across a power down/up cycle */
3515 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3516 mii_reg |= MII_CR_POWER_DOWN;
3517 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3522 * __e1000_read_phy_reg_hv - Read HV PHY register
3523 * @hw: pointer to the HW structure
3524 * @offset: register offset to be read
3525 * @data: pointer to the read data
3526 * @locked: semaphore has already been acquired or not
3528 * Acquires semaphore, if necessary, then reads the PHY register at offset
3529 * and stores the retrieved information in data. Release any acquired
3530 * semaphore before exiting.
3532 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3533 bool locked, bool page_set)
3536 u16 page = BM_PHY_REG_PAGE(offset);
3537 u16 reg = BM_PHY_REG_NUM(offset);
3538 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3540 DEBUGFUNC("__e1000_read_phy_reg_hv");
3543 ret_val = hw->phy.ops.acquire(hw);
3547 /* Page 800 works differently than the rest so it has its own func */
3548 if (page == BM_WUC_PAGE) {
3549 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3554 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3555 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3561 if (page == HV_INTC_FC_PAGE_START)
3564 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3565 /* Page is shifted left, PHY expects (page x 32) */
3566 ret_val = e1000_set_page_igp(hw,
3567 (page << IGP_PAGE_SHIFT));
3569 hw->phy.addr = phy_addr;
3576 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3577 page << IGP_PAGE_SHIFT, reg);
3579 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3583 hw->phy.ops.release(hw);
3589 * e1000_read_phy_reg_hv - Read HV PHY register
3590 * @hw: pointer to the HW structure
3591 * @offset: register offset to be read
3592 * @data: pointer to the read data
3594 * Acquires semaphore then reads the PHY register at offset and stores
3595 * the retrieved information in data. Release the acquired semaphore
3598 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3600 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE, false);
3604 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3605 * @hw: pointer to the HW structure
3606 * @offset: register offset to be read
3607 * @data: pointer to the read data
3609 * Reads the PHY register at offset and stores the retrieved information
3610 * in data. Assumes semaphore already acquired.
3612 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3614 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, FALSE);
3618 * e1000_read_phy_reg_page_hv - Read HV PHY register
3619 * @hw: pointer to the HW structure
3620 * @offset: register offset to write to
3621 * @data: data to write at register offset
3623 * Reads the PHY register at offset and stores the retrieved information
3624 * in data. Assumes semaphore already acquired and page already set.
3626 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3628 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, true);
3632 * __e1000_write_phy_reg_hv - Write HV PHY register
3633 * @hw: pointer to the HW structure
3634 * @offset: register offset to write to
3635 * @data: data to write at register offset
3636 * @locked: semaphore has already been acquired or not
3638 * Acquires semaphore, if necessary, then writes the data to PHY register
3639 * at the offset. Release any acquired semaphores before exiting.
3641 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3642 bool locked, bool page_set)
3645 u16 page = BM_PHY_REG_PAGE(offset);
3646 u16 reg = BM_PHY_REG_NUM(offset);
3647 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3649 DEBUGFUNC("__e1000_write_phy_reg_hv");
3652 ret_val = hw->phy.ops.acquire(hw);
3656 /* Page 800 works differently than the rest so it has its own func */
3657 if (page == BM_WUC_PAGE) {
3658 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3663 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3664 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3670 if (page == HV_INTC_FC_PAGE_START)
3673 /* Workaround MDIO accesses being disabled after entering IEEE
3674 * Power Down (when bit 11 of the PHY Control register is set)
3676 if ((hw->phy.type == e1000_phy_82578) &&
3677 (hw->phy.revision >= 1) &&
3678 (hw->phy.addr == 2) &&
3679 !(MAX_PHY_REG_ADDRESS & reg) &&
3680 (data & (1 << 11))) {
3682 ret_val = e1000_access_phy_debug_regs_hv(hw,
3689 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3690 /* Page is shifted left, PHY expects (page x 32) */
3691 ret_val = e1000_set_page_igp(hw,
3692 (page << IGP_PAGE_SHIFT));
3694 hw->phy.addr = phy_addr;
3701 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3702 page << IGP_PAGE_SHIFT, reg);
3704 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3709 hw->phy.ops.release(hw);
3715 * e1000_write_phy_reg_hv - Write HV PHY register
3716 * @hw: pointer to the HW structure
3717 * @offset: register offset to write to
3718 * @data: data to write at register offset
3720 * Acquires semaphore then writes the data to PHY register at the offset.
3721 * Release the acquired semaphores before exiting.
3723 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3725 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE, false);
3729 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3730 * @hw: pointer to the HW structure
3731 * @offset: register offset to write to
3732 * @data: data to write at register offset
3734 * Writes the data to PHY register at the offset. Assumes semaphore
3737 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3739 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, FALSE);
3743 * e1000_write_phy_reg_page_hv - Write HV PHY register
3744 * @hw: pointer to the HW structure
3745 * @offset: register offset to write to
3746 * @data: data to write at register offset
3748 * Writes the data to PHY register at the offset. Assumes semaphore
3749 * already acquired and page already set.
3751 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3753 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, true);
3757 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3758 * @page: page to be accessed
3760 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3764 if (page >= HV_INTC_FC_PAGE_START)
3771 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3772 * @hw: pointer to the HW structure
3773 * @offset: register offset to be read or written
3774 * @data: pointer to the data to be read or written
3775 * @read: determines if operation is read or write
3777 * Reads the PHY register at offset and stores the retreived information
3778 * in data. Assumes semaphore already acquired. Note that the procedure
3779 * to access these regs uses the address port and data port to read/write.
3780 * These accesses done with PHY address 2 and without using pages.
3782 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3783 u16 *data, bool read)
3789 DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3791 /* This takes care of the difference with desktop vs mobile phy */
3792 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3793 I82578_ADDR_REG : I82577_ADDR_REG);
3794 data_reg = addr_reg + 1;
3796 /* All operations in this function are phy address 2 */
3799 /* masking with 0x3F to remove the page from offset */
3800 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3802 DEBUGOUT("Could not write the Address Offset port register\n");
3806 /* Read or write the data value next */
3808 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3810 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3813 DEBUGOUT("Could not access the Data port register\n");
3819 * e1000_link_stall_workaround_hv - Si workaround
3820 * @hw: pointer to the HW structure
3822 * This function works around a Si bug where the link partner can get
3823 * a link up indication before the PHY does. If small packets are sent
3824 * by the link partner they can be placed in the packet buffer without
3825 * being properly accounted for by the PHY and will stall preventing
3826 * further packets from being received. The workaround is to clear the
3827 * packet buffer after the PHY detects link up.
3829 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3831 s32 ret_val = E1000_SUCCESS;
3834 DEBUGFUNC("e1000_link_stall_workaround_hv");
3836 if (hw->phy.type != e1000_phy_82578)
3837 return E1000_SUCCESS;
3839 /* Do not apply workaround if in PHY loopback bit 14 set */
3840 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3841 if (data & PHY_CONTROL_LB)
3842 return E1000_SUCCESS;
3844 /* check if link is up and at 1Gbps */
3845 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3849 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3850 BM_CS_STATUS_SPEED_MASK);
3852 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3853 BM_CS_STATUS_SPEED_1000))
3854 return E1000_SUCCESS;
3858 /* flush the packets in the fifo buffer */
3859 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3860 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3861 HV_MUX_DATA_CTRL_FORCE_SPEED));
3865 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3866 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3870 * e1000_check_polarity_82577 - Checks the polarity.
3871 * @hw: pointer to the HW structure
3873 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3875 * Polarity is determined based on the PHY specific status register.
3877 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3879 struct e1000_phy_info *phy = &hw->phy;
3883 DEBUGFUNC("e1000_check_polarity_82577");
3885 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3888 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3889 ? e1000_rev_polarity_reversed
3890 : e1000_rev_polarity_normal);
3896 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3897 * @hw: pointer to the HW structure
3899 * Calls the PHY setup function to force speed and duplex.
3901 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3903 struct e1000_phy_info *phy = &hw->phy;
3908 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3910 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3914 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3916 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3922 if (phy->autoneg_wait_to_complete) {
3923 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3925 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3931 DEBUGOUT("Link taking longer than expected.\n");
3934 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3942 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3943 * @hw: pointer to the HW structure
3945 * Read PHY status to determine if link is up. If link is up, then
3946 * set/determine 10base-T extended distance and polarity correction. Read
3947 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3948 * determine on the cable length, local and remote receiver.
3950 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3952 struct e1000_phy_info *phy = &hw->phy;
3957 DEBUGFUNC("e1000_get_phy_info_82577");
3959 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3964 DEBUGOUT("Phy info is only valid if link is up\n");
3965 return -E1000_ERR_CONFIG;
3968 phy->polarity_correction = TRUE;
3970 ret_val = e1000_check_polarity_82577(hw);
3974 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3978 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3980 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3981 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3982 ret_val = hw->phy.ops.get_cable_length(hw);
3986 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3990 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3991 ? e1000_1000t_rx_status_ok
3992 : e1000_1000t_rx_status_not_ok;
3994 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3995 ? e1000_1000t_rx_status_ok
3996 : e1000_1000t_rx_status_not_ok;
3998 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3999 phy->local_rx = e1000_1000t_rx_status_undefined;
4000 phy->remote_rx = e1000_1000t_rx_status_undefined;
4003 return E1000_SUCCESS;
4007 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
4008 * @hw: pointer to the HW structure
4010 * Reads the diagnostic status register and verifies result is valid before
4011 * placing it in the phy_cable_length field.
4013 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
4015 struct e1000_phy_info *phy = &hw->phy;
4017 u16 phy_data, length;
4019 DEBUGFUNC("e1000_get_cable_length_82577");
4021 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4025 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
4026 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
4028 if (length == E1000_CABLE_LENGTH_UNDEFINED)
4029 return -E1000_ERR_PHY;
4031 phy->cable_length = length;
4033 return E1000_SUCCESS;
4037 * e1000_write_phy_reg_gs40g - Write GS40G PHY register
4038 * @hw: pointer to the HW structure
4039 * @offset: register offset to write to
4040 * @data: data to write at register offset
4042 * Acquires semaphore, if necessary, then writes the data to PHY register
4043 * at the offset. Release any acquired semaphores before exiting.
4045 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
4048 u16 page = offset >> GS40G_PAGE_SHIFT;
4050 DEBUGFUNC("e1000_write_phy_reg_gs40g");
4052 offset = offset & GS40G_OFFSET_MASK;
4053 ret_val = hw->phy.ops.acquire(hw);
4057 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4060 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
4063 hw->phy.ops.release(hw);
4068 * e1000_read_phy_reg_gs40g - Read GS40G PHY register
4069 * @hw: pointer to the HW structure
4070 * @offset: lower half is register offset to read to
4071 * upper half is page to use.
4072 * @data: data to read at register offset
4074 * Acquires semaphore, if necessary, then reads the data in the PHY register
4075 * at the offset. Release any acquired semaphores before exiting.
4077 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
4080 u16 page = offset >> GS40G_PAGE_SHIFT;
4082 DEBUGFUNC("e1000_read_phy_reg_gs40g");
4084 offset = offset & GS40G_OFFSET_MASK;
4085 ret_val = hw->phy.ops.acquire(hw);
4089 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4092 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
4095 hw->phy.ops.release(hw);
4100 * e1000_read_phy_reg_mphy - Read mPHY control register
4101 * @hw: pointer to the HW structure
4102 * @address: address to be read
4103 * @data: pointer to the read data
4105 * Reads the mPHY control register in the PHY at offset and stores the
4106 * information read to data.
4108 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data)
4111 bool locked = FALSE;
4114 DEBUGFUNC("e1000_read_phy_reg_mphy");
4116 /* Check if mPHY is ready to read/write operations */
4117 ready = e1000_is_mphy_ready(hw);
4119 return -E1000_ERR_PHY;
4121 /* Check if mPHY access is disabled and enable it if so */
4122 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4123 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4125 ready = e1000_is_mphy_ready(hw);
4127 return -E1000_ERR_PHY;
4128 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4129 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4132 /* Set the address that we want to read */
4133 ready = e1000_is_mphy_ready(hw);
4135 return -E1000_ERR_PHY;
4137 /* We mask address, because we want to use only current lane */
4138 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK &
4139 ~E1000_MPHY_ADDRESS_FNC_OVERRIDE) |
4140 (address & E1000_MPHY_ADDRESS_MASK);
4141 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4143 /* Read data from the address */
4144 ready = e1000_is_mphy_ready(hw);
4146 return -E1000_ERR_PHY;
4147 *data = E1000_READ_REG(hw, E1000_MPHY_DATA);
4149 /* Disable access to mPHY if it was originally disabled */
4151 ready = e1000_is_mphy_ready(hw);
4153 return -E1000_ERR_PHY;
4154 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4155 E1000_MPHY_DIS_ACCESS);
4157 return E1000_SUCCESS;
4161 * e1000_write_phy_reg_mphy - Write mPHY control register
4162 * @hw: pointer to the HW structure
4163 * @address: address to write to
4164 * @data: data to write to register at offset
4165 * @line_override: used when we want to use different line than default one
4167 * Writes data to mPHY control register.
4169 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,
4173 bool locked = FALSE;
4176 DEBUGFUNC("e1000_write_phy_reg_mphy");
4178 /* Check if mPHY is ready to read/write operations */
4179 ready = e1000_is_mphy_ready(hw);
4181 return -E1000_ERR_PHY;
4183 /* Check if mPHY access is disabled and enable it if so */
4184 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4185 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4187 ready = e1000_is_mphy_ready(hw);
4189 return -E1000_ERR_PHY;
4190 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4191 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4194 /* Set the address that we want to read */
4195 ready = e1000_is_mphy_ready(hw);
4197 return -E1000_ERR_PHY;
4199 /* We mask address, because we want to use only current lane */
4201 mphy_ctrl |= E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4203 mphy_ctrl &= ~E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4204 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK) |
4205 (address & E1000_MPHY_ADDRESS_MASK);
4206 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4208 /* Read data from the address */
4209 ready = e1000_is_mphy_ready(hw);
4211 return -E1000_ERR_PHY;
4212 E1000_WRITE_REG(hw, E1000_MPHY_DATA, data);
4214 /* Disable access to mPHY if it was originally disabled */
4216 ready = e1000_is_mphy_ready(hw);
4218 return -E1000_ERR_PHY;
4219 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4220 E1000_MPHY_DIS_ACCESS);
4222 return E1000_SUCCESS;
4226 * e1000_is_mphy_ready - Check if mPHY control register is not busy
4227 * @hw: pointer to the HW structure
4229 * Returns mPHY control register status.
4231 bool e1000_is_mphy_ready(struct e1000_hw *hw)
4233 u16 retry_count = 0;
4237 while (retry_count < 2) {
4238 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4239 if (mphy_ctrl & E1000_MPHY_BUSY) {
4249 DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n");