sys/dev/e1000/if_em.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /* $FreeBSD$ */
  30 #include "if_em.h"
  31 #include <sys/sbuf.h>
  32 #include <machine/_inttypes.h>
  33
  34 #define em_mac_min e1000_82547
  35 #define igb_mac_min e1000_82575
  36
  37 /*********************************************************************
  38  *  Driver version:
  39  *********************************************************************/
  40 char em_driver_version[] = "7.6.1-k";
  41
  42 /*********************************************************************
  43  *  PCI Device ID Table
  44  *
  45  *  Used by probe to select devices to load on
  46  *  Last field stores an index into e1000_strings
  47  *  Last entry must be all 0s
  48  *
  49  *  { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
  50  *********************************************************************/
  51
  52 static pci_vendor_info_t em_vendor_info_array[] =
  53 {
  54         /* Intel(R) PRO/1000 Network Connection - Legacy em*/
  55         PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"),
  56         PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"),
  57         PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"),
  58         PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"),
  59         PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"),
  60
  61         PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"),
  62         PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"),
  63         PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"),
  64         PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  65         PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"),
  66         PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"),
  67         PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  68
  69         PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"),
  70
  71         PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"),
  72         PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
  73
  74         PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
  75         PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
  76         PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
  77         PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"),
  78
  79         PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"),
  80         PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"),
  81         PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"),
  82         PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"),
  83         PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"),
  84
  85         PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  86         PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
  87         PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
  88         PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  89         PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"),
  90         PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"),
  91         PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"),
  92         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
  93         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"),
  94
  95         PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"),
  96         PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  97         PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"),
  98
  99         /* Intel(R) PRO/1000 Network Connection - em */
 100         PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
 101         PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
 102         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"),
 103         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"),
 104         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"),
 105         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 106         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"),
 107         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"),
 108         PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 109         PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"),
 110         PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
 111         PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
 112         PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"),
 113         PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"),
 114         PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"),
 115         PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"),
 116         PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"),
 117         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"),
 118         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"),
 119         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"),
 120         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"),
 121         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
 122         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 123         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"),
 124         PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"),
 125         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
 126         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"),
 127         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"),
 128         PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"),
 129         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
 130         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 131         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"),
 132         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"),
 133         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"),
 134         PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"),
 135         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
 136         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"),
 137         PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"),
 138         PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"),
 139         PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"),
 140         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"),
 141         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"),
 142         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"),
 143         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"),
 144         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"),
 145         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"),
 146         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"),
 147         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"),
 148         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"),
 149         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"),
 150         PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"),
 151         PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"),
 152         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"),
 153         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"),
 154         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"),
 155         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"),
 156         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"),
 157         PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"),
 158         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"),
 159         PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"),
 160         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"),
 161         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"),
 162         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"),
 163         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"),
 164         PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"),
 165         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"),
 166         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"),
 167         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"),
 168         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"),
 169         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) PRO/1000 Network Connection"),
 170         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) PRO/1000 Network Connection"),
 171         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) PRO/1000 Network Connection"),
 172         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) PRO/1000 Network Connection"),
 173         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) PRO/1000 Network Connection"),
 174         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) PRO/1000 Network Connection"),
 175         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) PRO/1000 Network Connection"),
 176         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) PRO/1000 Network Connection"),
 177         /* required last entry */
 178         PVID_END
 179 };
 180
 181 static pci_vendor_info_t igb_vendor_info_array[] =
 182 {
 183         /* Intel(R) PRO/1000 Network Connection - igb */
 184         PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 185         PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 186         PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 187         PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 188         PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 189         PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 190         PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 191         PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 192         PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 193         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 194         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 195         PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 196         PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 197         PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 198         PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 199         PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 200         PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 201         PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 202         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 203         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 204         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 205         PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 206         PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 207         PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 208         PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 209         PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 210         PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 211         PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 212         PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 213         PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 214         PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 215         PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 216         PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 217         PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 218         PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 219         PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 220         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 221         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 222         PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 223         /* required last entry */
 224         PVID_END
 225 };
 226
 227 /*********************************************************************
 228  *  Function prototypes
 229  *********************************************************************/
 230 static void     *em_register(device_t dev);
 231 static void     *igb_register(device_t dev);
 232 static int      em_if_attach_pre(if_ctx_t ctx);
 233 static int      em_if_attach_post(if_ctx_t ctx);
 234 static int      em_if_detach(if_ctx_t ctx);
 235 static int      em_if_shutdown(if_ctx_t ctx);
 236 static int      em_if_suspend(if_ctx_t ctx);
 237 static int      em_if_resume(if_ctx_t ctx);
 238
 239 static int      em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets);
 240 static int      em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets);
 241 static void     em_if_queues_free(if_ctx_t ctx);
 242
 243 static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
 244 static void     em_if_init(if_ctx_t ctx);
 245 static void     em_if_stop(if_ctx_t ctx);
 246 static void     em_if_media_status(if_ctx_t, struct ifmediareq *);
 247 static int      em_if_media_change(if_ctx_t ctx);
 248 static int      em_if_mtu_set(if_ctx_t ctx, uint32_t mtu);
 249 static void     em_if_timer(if_ctx_t ctx, uint16_t qid);
 250 static void     em_if_vlan_register(if_ctx_t ctx, u16 vtag);
 251 static void     em_if_vlan_unregister(if_ctx_t ctx, u16 vtag);
 252
 253 static void     em_identify_hardware(if_ctx_t ctx);
 254 static int      em_allocate_pci_resources(if_ctx_t ctx);
 255 static void     em_free_pci_resources(if_ctx_t ctx);
 256 static void     em_reset(if_ctx_t ctx);
 257 static int      em_setup_interface(if_ctx_t ctx);
 258 static int      em_setup_msix(if_ctx_t ctx);
 259
 260 static void     em_initialize_transmit_unit(if_ctx_t ctx);
 261 static void     em_initialize_receive_unit(if_ctx_t ctx);
 262
 263 static void     em_if_enable_intr(if_ctx_t ctx);
 264 static void     em_if_disable_intr(if_ctx_t ctx);
 265 static int      em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 266 static int      em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
 267 static void     em_if_multi_set(if_ctx_t ctx);
 268 static void     em_if_update_admin_status(if_ctx_t ctx);
 269 static void     em_if_debug(if_ctx_t ctx);
 270 static void     em_update_stats_counters(struct adapter *);
 271 static void     em_add_hw_stats(struct adapter *adapter);
 272 static int      em_if_set_promisc(if_ctx_t ctx, int flags);
 273 static void     em_setup_vlan_hw_support(struct adapter *);
 274 static int      em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
 275 static void     em_print_nvm_info(struct adapter *);
 276 static int      em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 277 static int      em_get_rs(SYSCTL_HANDLER_ARGS);
 278 static void     em_print_debug_info(struct adapter *);
 279 static int      em_is_valid_ether_addr(u8 *);
 280 static int      em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
 281 static void     em_add_int_delay_sysctl(struct adapter *, const char *,
 282                     const char *, struct em_int_delay_info *, int, int);
 283 /* Management and WOL Support */
 284 static void     em_init_manageability(struct adapter *);
 285 static void     em_release_manageability(struct adapter *);
 286 static void     em_get_hw_control(struct adapter *);
 287 static void     em_release_hw_control(struct adapter *);
 288 static void     em_get_wakeup(if_ctx_t ctx);
 289 static void     em_enable_wakeup(if_ctx_t ctx);
 290 static int      em_enable_phy_wakeup(struct adapter *);
 291 static void     em_disable_aspm(struct adapter *);
 292
 293 int             em_intr(void *arg);
 294 static void     em_disable_promisc(if_ctx_t ctx);
 295
 296 /* MSI-X handlers */
 297 static int      em_if_msix_intr_assign(if_ctx_t, int);
 298 static int      em_msix_link(void *);
 299 static void     em_handle_link(void *context);
 300
 301 static void     em_enable_vectors_82574(if_ctx_t);
 302
 303 static int      em_set_flowcntl(SYSCTL_HANDLER_ARGS);
 304 static int      em_sysctl_eee(SYSCTL_HANDLER_ARGS);
 305 static void     em_if_led_func(if_ctx_t ctx, int onoff);
 306
 307 static int      em_get_regs(SYSCTL_HANDLER_ARGS);
 308
 309 static void     lem_smartspeed(struct adapter *adapter);
 310 static void     igb_configure_queues(struct adapter *adapter);
 311
 312
 313 /*********************************************************************
 314  *  FreeBSD Device Interface Entry Points
 315  *********************************************************************/
 316 static device_method_t em_methods[] = {
 317         /* Device interface */
 318         DEVMETHOD(device_register, em_register),
 319         DEVMETHOD(device_probe, iflib_device_probe),
 320         DEVMETHOD(device_attach, iflib_device_attach),
 321         DEVMETHOD(device_detach, iflib_device_detach),
 322         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 323         DEVMETHOD(device_suspend, iflib_device_suspend),
 324         DEVMETHOD(device_resume, iflib_device_resume),
 325         DEVMETHOD_END
 326 };
 327
 328 static device_method_t igb_methods[] = {
 329         /* Device interface */
 330         DEVMETHOD(device_register, igb_register),
 331         DEVMETHOD(device_probe, iflib_device_probe),
 332         DEVMETHOD(device_attach, iflib_device_attach),
 333         DEVMETHOD(device_detach, iflib_device_detach),
 334         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 335         DEVMETHOD(device_suspend, iflib_device_suspend),
 336         DEVMETHOD(device_resume, iflib_device_resume),
 337         DEVMETHOD_END
 338 };
 339
 340
 341 static driver_t em_driver = {
 342         "em", em_methods, sizeof(struct adapter),
 343 };
 344
 345 static devclass_t em_devclass;
 346 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
 347
 348 MODULE_DEPEND(em, pci, 1, 1, 1);
 349 MODULE_DEPEND(em, ether, 1, 1, 1);
 350 MODULE_DEPEND(em, iflib, 1, 1, 1);
 351
 352 IFLIB_PNP_INFO(pci, em, em_vendor_info_array);
 353
 354 static driver_t igb_driver = {
 355         "igb", igb_methods, sizeof(struct adapter),
 356 };
 357
 358 static devclass_t igb_devclass;
 359 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
 360
 361 MODULE_DEPEND(igb, pci, 1, 1, 1);
 362 MODULE_DEPEND(igb, ether, 1, 1, 1);
 363 MODULE_DEPEND(igb, iflib, 1, 1, 1);
 364
 365 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array);
 366
 367 static device_method_t em_if_methods[] = {
 368         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 369         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 370         DEVMETHOD(ifdi_detach, em_if_detach),
 371         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 372         DEVMETHOD(ifdi_suspend, em_if_suspend),
 373         DEVMETHOD(ifdi_resume, em_if_resume),
 374         DEVMETHOD(ifdi_init, em_if_init),
 375         DEVMETHOD(ifdi_stop, em_if_stop),
 376         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 377         DEVMETHOD(ifdi_intr_enable, em_if_enable_intr),
 378         DEVMETHOD(ifdi_intr_disable, em_if_disable_intr),
 379         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 380         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 381         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 382         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 383         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 384         DEVMETHOD(ifdi_media_status, em_if_media_status),
 385         DEVMETHOD(ifdi_media_change, em_if_media_change),
 386         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 387         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 388         DEVMETHOD(ifdi_timer, em_if_timer),
 389         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 390         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 391         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 392         DEVMETHOD(ifdi_led_func, em_if_led_func),
 393         DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable),
 394         DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable),
 395         DEVMETHOD(ifdi_debug, em_if_debug),
 396         DEVMETHOD_END
 397 };
 398
 399 /*
 400  * note that if (adapter->msix_mem) is replaced by:
 401  * if (adapter->intr_type == IFLIB_INTR_MSIX)
 402  */
 403 static driver_t em_if_driver = {
 404         "em_if", em_if_methods, sizeof(struct adapter)
 405 };
 406
 407 /*********************************************************************
 408  *  Tunable default values.
 409  *********************************************************************/
 410
 411 #define EM_TICKS_TO_USECS(ticks)        ((1024 * (ticks) + 500) / 1000)
 412 #define EM_USECS_TO_TICKS(usecs)        ((1000 * (usecs) + 512) / 1024)
 413
 414 #define MAX_INTS_PER_SEC        8000
 415 #define DEFAULT_ITR             (1000000000/(MAX_INTS_PER_SEC * 256))
 416
 417 /* Allow common code without TSO */
 418 #ifndef CSUM_TSO
 419 #define CSUM_TSO        0
 420 #endif
 421
 422 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters");
 423
 424 static int em_disable_crc_stripping = 0;
 425 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
 426     &em_disable_crc_stripping, 0, "Disable CRC Stripping");
 427
 428 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
 429 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
 430 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
 431     0, "Default transmit interrupt delay in usecs");
 432 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
 433     0, "Default receive interrupt delay in usecs");
 434
 435 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
 436 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
 437 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
 438     &em_tx_abs_int_delay_dflt, 0,
 439     "Default transmit interrupt delay limit in usecs");
 440 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
 441     &em_rx_abs_int_delay_dflt, 0,
 442     "Default receive interrupt delay limit in usecs");
 443
 444 static int em_smart_pwr_down = FALSE;
 445 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
 446     0, "Set to true to leave smart power down enabled on newer adapters");
 447
 448 /* Controls whether promiscuous also shows bad packets */
 449 static int em_debug_sbp = TRUE;
 450 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
 451     "Show bad packets in promiscuous mode");
 452
 453 /* How many packets rxeof tries to clean at a time */
 454 static int em_rx_process_limit = 100;
 455 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
 456     &em_rx_process_limit, 0,
 457     "Maximum number of received packets to process "
 458     "at a time, -1 means unlimited");
 459
 460 /* Energy efficient ethernet - default to OFF */
 461 static int eee_setting = 1;
 462 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
 463     "Enable Energy Efficient Ethernet");
 464
 465 /*
 466 ** Tuneable Interrupt rate
 467 */
 468 static int em_max_interrupt_rate = 8000;
 469 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
 470     &em_max_interrupt_rate, 0, "Maximum interrupts per second");
 471
 472
 473
 474 /* Global used in WOL setup with multiport cards */
 475 static int global_quad_port_a = 0;
 476
 477 extern struct if_txrx igb_txrx;
 478 extern struct if_txrx em_txrx;
 479 extern struct if_txrx lem_txrx;
 480
 481 static struct if_shared_ctx em_sctx_init = {
 482         .isc_magic = IFLIB_MAGIC,
 483         .isc_q_align = PAGE_SIZE,
 484         .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 485         .isc_tx_maxsegsize = PAGE_SIZE,
 486         .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 487         .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
 488         .isc_rx_maxsize = MJUM9BYTES,
 489         .isc_rx_nsegments = 1,
 490         .isc_rx_maxsegsize = MJUM9BYTES,
 491         .isc_nfl = 1,
 492         .isc_nrxqs = 1,
 493         .isc_ntxqs = 1,
 494         .isc_admin_intrcnt = 1,
 495         .isc_vendor_info = em_vendor_info_array,
 496         .isc_driver_version = em_driver_version,
 497         .isc_driver = &em_if_driver,
 498         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 499
 500         .isc_nrxd_min = {EM_MIN_RXD},
 501         .isc_ntxd_min = {EM_MIN_TXD},
 502         .isc_nrxd_max = {EM_MAX_RXD},
 503         .isc_ntxd_max = {EM_MAX_TXD},
 504         .isc_nrxd_default = {EM_DEFAULT_RXD},
 505         .isc_ntxd_default = {EM_DEFAULT_TXD},
 506 };
 507
 508 if_shared_ctx_t em_sctx = &em_sctx_init;
 509
 510 static struct if_shared_ctx igb_sctx_init = {
 511         .isc_magic = IFLIB_MAGIC,
 512         .isc_q_align = PAGE_SIZE,
 513         .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 514         .isc_tx_maxsegsize = PAGE_SIZE,
 515         .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 516         .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
 517         .isc_rx_maxsize = MJUM9BYTES,
 518         .isc_rx_nsegments = 1,
 519         .isc_rx_maxsegsize = MJUM9BYTES,
 520         .isc_nfl = 1,
 521         .isc_nrxqs = 1,
 522         .isc_ntxqs = 1,
 523         .isc_admin_intrcnt = 1,
 524         .isc_vendor_info = igb_vendor_info_array,
 525         .isc_driver_version = em_driver_version,
 526         .isc_driver = &em_if_driver,
 527         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 528
 529         .isc_nrxd_min = {EM_MIN_RXD},
 530         .isc_ntxd_min = {EM_MIN_TXD},
 531         .isc_nrxd_max = {IGB_MAX_RXD},
 532         .isc_ntxd_max = {IGB_MAX_TXD},
 533         .isc_nrxd_default = {EM_DEFAULT_RXD},
 534         .isc_ntxd_default = {EM_DEFAULT_TXD},
 535 };
 536
 537 if_shared_ctx_t igb_sctx = &igb_sctx_init;
 538
 539 /*****************************************************************
 540  *
 541  * Dump Registers
 542  *
 543  ****************************************************************/
 544 #define IGB_REGS_LEN 739
 545
 546 static int em_get_regs(SYSCTL_HANDLER_ARGS)
 547 {
 548         struct adapter *adapter = (struct adapter *)arg1;
 549         struct e1000_hw *hw = &adapter->hw;
 550         struct sbuf *sb;
 551         u32 *regs_buff;
 552         int rc;
 553
 554         regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK);
 555         memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
 556
 557         rc = sysctl_wire_old_buffer(req, 0);
 558         MPASS(rc == 0);
 559         if (rc != 0) {
 560                 free(regs_buff, M_DEVBUF);
 561                 return (rc);
 562         }
 563
 564         sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
 565         MPASS(sb != NULL);
 566         if (sb == NULL) {
 567                 free(regs_buff, M_DEVBUF);
 568                 return (ENOMEM);
 569         }
 570
 571         /* General Registers */
 572         regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
 573         regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
 574         regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
 575         regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
 576         regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
 577         regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
 578         regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
 579         regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
 580         regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
 581         regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
 582         regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
 583         regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
 584         regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
 585         regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
 586         regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
 587         regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
 588         regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
 589         regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
 590         regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
 591         regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
 592         regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
 593         regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
 594
 595         sbuf_printf(sb, "General Registers\n");
 596         sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
 597         sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
 598         sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]);
 599
 600         sbuf_printf(sb, "Interrupt Registers\n");
 601         sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
 602
 603         sbuf_printf(sb, "RX Registers\n");
 604         sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
 605         sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
 606         sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
 607         sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
 608         sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
 609         sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
 610         sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
 611
 612         sbuf_printf(sb, "TX Registers\n");
 613         sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
 614         sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
 615         sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
 616         sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
 617         sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
 618         sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
 619         sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
 620         sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
 621         sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
 622         sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
 623         sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
 624
 625         free(regs_buff, M_DEVBUF);
 626
 627 #ifdef DUMP_DESCS
 628         {
 629                 if_softc_ctx_t scctx = adapter->shared;
 630                 struct rx_ring *rxr = &rx_que->rxr;
 631                 struct tx_ring *txr = &tx_que->txr;
 632                 int ntxd = scctx->isc_ntxd[0];
 633                 int nrxd = scctx->isc_nrxd[0];
 634                 int j;
 635
 636         for (j = 0; j < nrxd; j++) {
 637                 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
 638                 u32 length =  le32toh(rxr->rx_base[j].wb.upper.length);
 639                 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 "  Error:%d  Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
 640         }
 641
 642         for (j = 0; j < min(ntxd, 256); j++) {
 643                 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
 644
 645                 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x  eop: %d DD=%d\n",
 646                             j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
 647                             buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
 648
 649         }
 650         }
 651 #endif
 652
 653         rc = sbuf_finish(sb);
 654         sbuf_delete(sb);
 655         return(rc);
 656 }
 657
 658 static void *
 659 em_register(device_t dev)
 660 {
 661         return (em_sctx);
 662 }
 663
 664 static void *
 665 igb_register(device_t dev)
 666 {
 667         return (igb_sctx);
 668 }
 669
 670 static int
 671 em_set_num_queues(if_ctx_t ctx)
 672 {
 673         struct adapter *adapter = iflib_get_softc(ctx);
 674         int maxqueues;
 675
 676         /* Sanity check based on HW */
 677         switch (adapter->hw.mac.type) {
 678         case e1000_82576:
 679         case e1000_82580:
 680         case e1000_i350:
 681         case e1000_i354:
 682                 maxqueues = 8;
 683                 break;
 684         case e1000_i210:
 685         case e1000_82575:
 686                 maxqueues = 4;
 687                 break;
 688         case e1000_i211:
 689         case e1000_82574:
 690                 maxqueues = 2;
 691                 break;
 692         default:
 693                 maxqueues = 1;
 694                 break;
 695         }
 696
 697         return (maxqueues);
 698 }
 699
 700 #define LEM_CAPS                                                        \
 701     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 702     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER
 703
 704 #define EM_CAPS                                                         \
 705     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 706     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 |  \
 707     IFCAP_LRO | IFCAP_VLAN_HWTSO
 708
 709 #define IGB_CAPS                                                        \
 710     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 711     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 |  \
 712     IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\
 713     IFCAP_TSO6
 714
 715 /*********************************************************************
 716  *  Device initialization routine
 717  *
 718  *  The attach entry point is called when the driver is being loaded.
 719  *  This routine identifies the type of hardware, allocates all resources
 720  *  and initializes the hardware.
 721  *
 722  *  return 0 on success, positive on failure
 723  *********************************************************************/
 724
 725 static int
 726 em_if_attach_pre(if_ctx_t ctx)
 727 {
 728         struct adapter *adapter;
 729         if_softc_ctx_t scctx;
 730         device_t dev;
 731         struct e1000_hw *hw;
 732         int error = 0;
 733
 734         INIT_DEBUGOUT("em_if_attach_pre begin");
 735         dev = iflib_get_dev(ctx);
 736         adapter = iflib_get_softc(ctx);
 737
 738         if (resource_disabled("em", device_get_unit(dev))) {
 739                 device_printf(dev, "Disabled by device hint\n");
 740                 return (ENXIO);
 741         }
 742
 743         adapter->ctx = adapter->osdep.ctx = ctx;
 744         adapter->dev = adapter->osdep.dev = dev;
 745         scctx = adapter->shared = iflib_get_softc_ctx(ctx);
 746         adapter->media = iflib_get_media(ctx);
 747         hw = &adapter->hw;
 748
 749         adapter->tx_process_limit = scctx->isc_ntxd[0];
 750
 751         /* SYSCTL stuff */
 752         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 753             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 754             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 755             em_sysctl_nvm_info, "I", "NVM Information");
 756
 757         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 758             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 759             OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 760             em_sysctl_debug_info, "I", "Debug Information");
 761
 762         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 763             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 764             OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 765             em_set_flowcntl, "I", "Flow Control");
 766
 767         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 768             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 769             OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0,
 770             em_get_regs, "A", "Dump Registers");
 771
 772         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 773             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 774             OID_AUTO, "rs_dump", CTLTYPE_INT | CTLFLAG_RW, adapter, 0,
 775             em_get_rs, "I", "Dump RS indexes");
 776
 777         /* Determine hardware and mac info */
 778         em_identify_hardware(ctx);
 779
 780         scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR);
 781         scctx->isc_tx_nsegments = EM_MAX_SCATTER;
 782         scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
 783         if (bootverbose)
 784                 device_printf(dev, "attach_pre capping queues at %d\n",
 785                     scctx->isc_ntxqsets_max);
 786
 787         if (adapter->hw.mac.type >= igb_mac_min) {
 788                 int try_second_bar;
 789
 790                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
 791                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
 792                 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
 793                 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
 794                 scctx->isc_txrx = &igb_txrx;
 795                 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
 796                 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 797                 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 798                 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS;
 799                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO |
 800                      CSUM_IP6_TCP | CSUM_IP6_UDP;
 801                 if (adapter->hw.mac.type != e1000_82575)
 802                         scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
 803
 804                 /*
 805                 ** Some new devices, as with ixgbe, now may
 806                 ** use a different BAR, so we need to keep
 807                 ** track of which is used.
 808                 */
 809                 try_second_bar = pci_read_config(dev, scctx->isc_msix_bar, 4);
 810                 if (try_second_bar == 0)
 811                         scctx->isc_msix_bar += 4;
 812         } else if (adapter->hw.mac.type >= em_mac_min) {
 813                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 814                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
 815                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 816                 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
 817                 scctx->isc_txrx = &em_txrx;
 818                 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
 819                 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 820                 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 821                 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS;
 822                 /*
 823                  * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO}
 824                  * by default as we don't have workarounds for all associated
 825                  * silicon errata.  E. g., with several MACs such as 82573E,
 826                  * TSO only works at Gigabit speed and otherwise can cause the
 827                  * hardware to hang (which also would be next to impossible to
 828                  * work around given that already queued TSO-using descriptors
 829                  * would need to be flushed and vlan(4) reconfigured at runtime
 830                  * in case of a link speed change).  Moreover, MACs like 82579
 831                  * still can hang at Gigabit even with all publicly documented
 832                  * TSO workarounds implemented.  Generally, the penality of
 833                  * these workarounds is rather high and may involve copying
 834                  * mbuf data around so advantages of TSO lapse.  Still, TSO may
 835                  * work for a few MACs of this class - at least when sticking
 836                  * with Gigabit - in which case users may enable TSO manually.
 837                  */
 838                 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
 839                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 840         } else {
 841                 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 842                 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
 843                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 844                 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
 845                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP;
 846                 scctx->isc_txrx = &lem_txrx;
 847                 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS;
 848                 if (adapter->hw.mac.type < e1000_82543)
 849                         scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
 850                 scctx->isc_msix_bar = 0;
 851         }
 852
 853         /* Setup PCI resources */
 854         if (em_allocate_pci_resources(ctx)) {
 855                 device_printf(dev, "Allocation of PCI resources failed\n");
 856                 error = ENXIO;
 857                 goto err_pci;
 858         }
 859
 860         /*
 861         ** For ICH8 and family we need to
 862         ** map the flash memory, and this
 863         ** must happen after the MAC is
 864         ** identified
 865         */
 866         if ((hw->mac.type == e1000_ich8lan) ||
 867             (hw->mac.type == e1000_ich9lan) ||
 868             (hw->mac.type == e1000_ich10lan) ||
 869             (hw->mac.type == e1000_pchlan) ||
 870             (hw->mac.type == e1000_pch2lan) ||
 871             (hw->mac.type == e1000_pch_lpt)) {
 872                 int rid = EM_BAR_TYPE_FLASH;
 873                 adapter->flash = bus_alloc_resource_any(dev,
 874                     SYS_RES_MEMORY, &rid, RF_ACTIVE);
 875                 if (adapter->flash == NULL) {
 876                         device_printf(dev, "Mapping of Flash failed\n");
 877                         error = ENXIO;
 878                         goto err_pci;
 879                 }
 880                 /* This is used in the shared code */
 881                 hw->flash_address = (u8 *)adapter->flash;
 882                 adapter->osdep.flash_bus_space_tag =
 883                     rman_get_bustag(adapter->flash);
 884                 adapter->osdep.flash_bus_space_handle =
 885                     rman_get_bushandle(adapter->flash);
 886         }
 887         /*
 888         ** In the new SPT device flash is not  a
 889         ** separate BAR, rather it is also in BAR0,
 890         ** so use the same tag and an offset handle for the
 891         ** FLASH read/write macros in the shared code.
 892         */
 893         else if (hw->mac.type >= e1000_pch_spt) {
 894                 adapter->osdep.flash_bus_space_tag =
 895                     adapter->osdep.mem_bus_space_tag;
 896                 adapter->osdep.flash_bus_space_handle =
 897                     adapter->osdep.mem_bus_space_handle
 898                     + E1000_FLASH_BASE_ADDR;
 899         }
 900
 901         /* Do Shared Code initialization */
 902         error = e1000_setup_init_funcs(hw, TRUE);
 903         if (error) {
 904                 device_printf(dev, "Setup of Shared code failed, error %d\n",
 905                     error);
 906                 error = ENXIO;
 907                 goto err_pci;
 908         }
 909
 910         em_setup_msix(ctx);
 911         e1000_get_bus_info(hw);
 912
 913         /* Set up some sysctls for the tunable interrupt delays */
 914         em_add_int_delay_sysctl(adapter, "rx_int_delay",
 915             "receive interrupt delay in usecs", &adapter->rx_int_delay,
 916             E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
 917         em_add_int_delay_sysctl(adapter, "tx_int_delay",
 918             "transmit interrupt delay in usecs", &adapter->tx_int_delay,
 919             E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
 920         em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
 921             "receive interrupt delay limit in usecs",
 922             &adapter->rx_abs_int_delay,
 923             E1000_REGISTER(hw, E1000_RADV),
 924             em_rx_abs_int_delay_dflt);
 925         em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
 926             "transmit interrupt delay limit in usecs",
 927             &adapter->tx_abs_int_delay,
 928             E1000_REGISTER(hw, E1000_TADV),
 929             em_tx_abs_int_delay_dflt);
 930         em_add_int_delay_sysctl(adapter, "itr",
 931             "interrupt delay limit in usecs/4",
 932             &adapter->tx_itr,
 933             E1000_REGISTER(hw, E1000_ITR),
 934             DEFAULT_ITR);
 935
 936         hw->mac.autoneg = DO_AUTO_NEG;
 937         hw->phy.autoneg_wait_to_complete = FALSE;
 938         hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 939
 940         if (adapter->hw.mac.type < em_mac_min) {
 941                 e1000_init_script_state_82541(&adapter->hw, TRUE);
 942                 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
 943         }
 944         /* Copper options */
 945         if (hw->phy.media_type == e1000_media_type_copper) {
 946                 hw->phy.mdix = AUTO_ALL_MODES;
 947                 hw->phy.disable_polarity_correction = FALSE;
 948                 hw->phy.ms_type = EM_MASTER_SLAVE;
 949         }
 950
 951         /*
 952          * Set the frame limits assuming
 953          * standard ethernet sized frames.
 954          */
 955         scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
 956             ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
 957
 958         /*
 959          * This controls when hardware reports transmit completion
 960          * status.
 961          */
 962         hw->mac.report_tx_early = 1;
 963
 964         /* Allocate multicast array memory. */
 965         adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN *
 966             MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
 967         if (adapter->mta == NULL) {
 968                 device_printf(dev, "Can not allocate multicast setup array\n");
 969                 error = ENOMEM;
 970                 goto err_late;
 971         }
 972
 973         /* Check SOL/IDER usage */
 974         if (e1000_check_reset_block(hw))
 975                 device_printf(dev, "PHY reset is blocked"
 976                               " due to SOL/IDER session.\n");
 977
 978         /* Sysctl for setting Energy Efficient Ethernet */
 979         hw->dev_spec.ich8lan.eee_disable = eee_setting;
 980         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 981             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 982             OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW,
 983             adapter, 0, em_sysctl_eee, "I",
 984             "Disable Energy Efficient Ethernet");
 985
 986         /*
 987         ** Start from a known state, this is
 988         ** important in reading the nvm and
 989         ** mac from that.
 990         */
 991         e1000_reset_hw(hw);
 992
 993         /* Make sure we have a good EEPROM before we read from it */
 994         if (e1000_validate_nvm_checksum(hw) < 0) {
 995                 /*
 996                 ** Some PCI-E parts fail the first check due to
 997                 ** the link being in sleep state, call it again,
 998                 ** if it fails a second time its a real issue.
 999                 */
1000                 if (e1000_validate_nvm_checksum(hw) < 0) {
1001                         device_printf(dev,
1002                             "The EEPROM Checksum Is Not Valid\n");
1003                         error = EIO;
1004                         goto err_late;
1005                 }
1006         }
1007
1008         /* Copy the permanent MAC address out of the EEPROM */
1009         if (e1000_read_mac_addr(hw) < 0) {
1010                 device_printf(dev, "EEPROM read error while reading MAC"
1011                               " address\n");
1012                 error = EIO;
1013                 goto err_late;
1014         }
1015
1016         if (!em_is_valid_ether_addr(hw->mac.addr)) {
1017                 device_printf(dev, "Invalid MAC address\n");
1018                 error = EIO;
1019                 goto err_late;
1020         }
1021
1022         /* Disable ULP support */
1023         e1000_disable_ulp_lpt_lp(hw, TRUE);
1024
1025         /*
1026          * Get Wake-on-Lan and Management info for later use
1027          */
1028         em_get_wakeup(ctx);
1029
1030         /* Enable only WOL MAGIC by default */
1031         scctx->isc_capenable &= ~IFCAP_WOL;
1032         if (adapter->wol != 0)
1033                 scctx->isc_capenable |= IFCAP_WOL_MAGIC;
1034
1035         iflib_set_mac(ctx, hw->mac.addr);
1036
1037         return (0);
1038
1039 err_late:
1040         em_release_hw_control(adapter);
1041 err_pci:
1042         em_free_pci_resources(ctx);
1043         free(adapter->mta, M_DEVBUF);
1044
1045         return (error);
1046 }
1047
1048 static int
1049 em_if_attach_post(if_ctx_t ctx)
1050 {
1051         struct adapter *adapter = iflib_get_softc(ctx);
1052         struct e1000_hw *hw = &adapter->hw;
1053         int error = 0;
1054
1055         /* Setup OS specific network interface */
1056         error = em_setup_interface(ctx);
1057         if (error != 0) {
1058                 goto err_late;
1059         }
1060
1061         em_reset(ctx);
1062
1063         /* Initialize statistics */
1064         em_update_stats_counters(adapter);
1065         hw->mac.get_link_status = 1;
1066         em_if_update_admin_status(ctx);
1067         em_add_hw_stats(adapter);
1068
1069         /* Non-AMT based hardware can now take control from firmware */
1070         if (adapter->has_manage && !adapter->has_amt)
1071                 em_get_hw_control(adapter);
1072
1073         INIT_DEBUGOUT("em_if_attach_post: end");
1074
1075         return (error);
1076
1077 err_late:
1078         em_release_hw_control(adapter);
1079         em_free_pci_resources(ctx);
1080         em_if_queues_free(ctx);
1081         free(adapter->mta, M_DEVBUF);
1082
1083         return (error);
1084 }
1085
1086 /*********************************************************************
1087  *  Device removal routine
1088  *
1089  *  The detach entry point is called when the driver is being removed.
1090  *  This routine stops the adapter and deallocates all the resources
1091  *  that were allocated for driver operation.
1092  *
1093  *  return 0 on success, positive on failure
1094  *********************************************************************/
1095
1096 static int
1097 em_if_detach(if_ctx_t ctx)
1098 {
1099         struct adapter  *adapter = iflib_get_softc(ctx);
1100
1101         INIT_DEBUGOUT("em_detach: begin");
1102
1103         e1000_phy_hw_reset(&adapter->hw);
1104
1105         em_release_manageability(adapter);
1106         em_release_hw_control(adapter);
1107         em_free_pci_resources(ctx);
1108
1109         return (0);
1110 }
1111
1112 /*********************************************************************
1113  *
1114  *  Shutdown entry point
1115  *
1116  **********************************************************************/
1117
1118 static int
1119 em_if_shutdown(if_ctx_t ctx)
1120 {
1121         return em_if_suspend(ctx);
1122 }
1123
1124 /*
1125  * Suspend/resume device methods.
1126  */
1127 static int
1128 em_if_suspend(if_ctx_t ctx)
1129 {
1130         struct adapter *adapter = iflib_get_softc(ctx);
1131
1132         em_release_manageability(adapter);
1133         em_release_hw_control(adapter);
1134         em_enable_wakeup(ctx);
1135         return (0);
1136 }
1137
1138 static int
1139 em_if_resume(if_ctx_t ctx)
1140 {
1141         struct adapter *adapter = iflib_get_softc(ctx);
1142
1143         if (adapter->hw.mac.type == e1000_pch2lan)
1144                 e1000_resume_workarounds_pchlan(&adapter->hw);
1145         em_if_init(ctx);
1146         em_init_manageability(adapter);
1147
1148         return(0);
1149 }
1150
1151 static int
1152 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1153 {
1154         int max_frame_size;
1155         struct adapter *adapter = iflib_get_softc(ctx);
1156         if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1157
1158          IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1159
1160         switch (adapter->hw.mac.type) {
1161         case e1000_82571:
1162         case e1000_82572:
1163         case e1000_ich9lan:
1164         case e1000_ich10lan:
1165         case e1000_pch2lan:
1166         case e1000_pch_lpt:
1167         case e1000_pch_spt:
1168         case e1000_pch_cnp:
1169         case e1000_82574:
1170         case e1000_82583:
1171         case e1000_80003es2lan:
1172                 /* 9K Jumbo Frame size */
1173                 max_frame_size = 9234;
1174                 break;
1175         case e1000_pchlan:
1176                 max_frame_size = 4096;
1177                 break;
1178         case e1000_82542:
1179         case e1000_ich8lan:
1180                 /* Adapters that do not support jumbo frames */
1181                 max_frame_size = ETHER_MAX_LEN;
1182                 break;
1183         default:
1184                 if (adapter->hw.mac.type >= igb_mac_min)
1185                         max_frame_size = 9234;
1186                 else /* lem */
1187                         max_frame_size = MAX_JUMBO_FRAME_SIZE;
1188         }
1189         if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1190                 return (EINVAL);
1191         }
1192
1193         scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
1194             mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1195         return (0);
1196 }
1197
1198 /*********************************************************************
1199  *  Init entry point
1200  *
1201  *  This routine is used in two ways. It is used by the stack as
1202  *  init entry point in network interface structure. It is also used
1203  *  by the driver as a hw/sw initialization routine to get to a
1204  *  consistent state.
1205  *
1206  *  return 0 on success, positive on failure
1207  **********************************************************************/
1208
1209 static void
1210 em_if_init(if_ctx_t ctx)
1211 {
1212         struct adapter *adapter = iflib_get_softc(ctx);
1213         if_softc_ctx_t scctx = adapter->shared;
1214         struct ifnet *ifp = iflib_get_ifp(ctx);
1215         struct em_tx_queue *tx_que;
1216         int i;
1217         INIT_DEBUGOUT("em_if_init: begin");
1218
1219         /* Get the latest mac address, User can use a LAA */
1220         bcopy(if_getlladdr(ifp), adapter->hw.mac.addr,
1221             ETHER_ADDR_LEN);
1222
1223         /* Put the address into the Receive Address Array */
1224         e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1225
1226         /*
1227          * With the 82571 adapter, RAR[0] may be overwritten
1228          * when the other port is reset, we make a duplicate
1229          * in RAR[14] for that eventuality, this assures
1230          * the interface continues to function.
1231          */
1232         if (adapter->hw.mac.type == e1000_82571) {
1233                 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1234                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1235                     E1000_RAR_ENTRIES - 1);
1236         }
1237
1238
1239         /* Initialize the hardware */
1240         em_reset(ctx);
1241         em_if_update_admin_status(ctx);
1242
1243         for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) {
1244                 struct tx_ring *txr = &tx_que->txr;
1245
1246                 txr->tx_rs_cidx = txr->tx_rs_pidx;
1247
1248                 /* Initialize the last processed descriptor to be the end of
1249                  * the ring, rather than the start, so that we avoid an
1250                  * off-by-one error when calculating how many descriptors are
1251                  * done in the credits_update function.
1252                  */
1253                 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
1254         }
1255
1256         /* Setup VLAN support, basic and offload if available */
1257         E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1258
1259         /* Clear bad data from Rx FIFOs */
1260         if (adapter->hw.mac.type >= igb_mac_min)
1261                 e1000_rx_fifo_flush_82575(&adapter->hw);
1262
1263         /* Configure for OS presence */
1264         em_init_manageability(adapter);
1265
1266         /* Prepare transmit descriptors and buffers */
1267         em_initialize_transmit_unit(ctx);
1268
1269         /* Setup Multicast table */
1270         em_if_multi_set(ctx);
1271
1272         /*
1273          * Figure out the desired mbuf
1274          * pool for doing jumbos
1275          */
1276         if (adapter->hw.mac.max_frame_size <= 2048)
1277                 adapter->rx_mbuf_sz = MCLBYTES;
1278 #ifndef CONTIGMALLOC_WORKS
1279         else
1280                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
1281 #else
1282         else if (adapter->hw.mac.max_frame_size <= 4096)
1283                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
1284         else
1285                 adapter->rx_mbuf_sz = MJUM9BYTES;
1286 #endif
1287         em_initialize_receive_unit(ctx);
1288
1289         /* Use real VLAN Filter support? */
1290         if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1291                 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
1292                         /* Use real VLAN Filter support */
1293                         em_setup_vlan_hw_support(adapter);
1294                 else {
1295                         u32 ctrl;
1296                         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1297                         ctrl |= E1000_CTRL_VME;
1298                         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1299                 }
1300         }
1301
1302         /* Don't lose promiscuous settings */
1303         em_if_set_promisc(ctx, IFF_PROMISC);
1304         e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1305
1306         /* MSI-X configuration for 82574 */
1307         if (adapter->hw.mac.type == e1000_82574) {
1308                 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1309
1310                 tmp |= E1000_CTRL_EXT_PBA_CLR;
1311                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1312                 /* Set the IVAR - interrupt vector routing. */
1313                 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars);
1314         } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1315                 igb_configure_queues(adapter);
1316
1317         /* this clears any pending interrupts */
1318         E1000_READ_REG(&adapter->hw, E1000_ICR);
1319         E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC);
1320
1321         /* AMT based hardware can now take control from firmware */
1322         if (adapter->has_manage && adapter->has_amt)
1323                 em_get_hw_control(adapter);
1324
1325         /* Set Energy Efficient Ethernet */
1326         if (adapter->hw.mac.type >= igb_mac_min &&
1327             adapter->hw.phy.media_type == e1000_media_type_copper) {
1328                 if (adapter->hw.mac.type == e1000_i354)
1329                         e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
1330                 else
1331                         e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
1332         }
1333 }
1334
1335 /*********************************************************************
1336  *
1337  *  Fast Legacy/MSI Combined Interrupt Service routine
1338  *
1339  *********************************************************************/
1340 int
1341 em_intr(void *arg)
1342 {
1343         struct adapter *adapter = arg;
1344         if_ctx_t ctx = adapter->ctx;
1345         u32 reg_icr;
1346
1347         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1348
1349         if (adapter->intr_type != IFLIB_INTR_LEGACY)
1350                 goto skip_stray;
1351         /* Hot eject? */
1352         if (reg_icr == 0xffffffff)
1353                 return FILTER_STRAY;
1354
1355         /* Definitely not our interrupt. */
1356         if (reg_icr == 0x0)
1357                 return FILTER_STRAY;
1358
1359         /*
1360          * Starting with the 82571 chip, bit 31 should be used to
1361          * determine whether the interrupt belongs to us.
1362          */
1363         if (adapter->hw.mac.type >= e1000_82571 &&
1364             (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1365                 return FILTER_STRAY;
1366
1367 skip_stray:
1368         /* Link status change */
1369         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1370                 adapter->hw.mac.get_link_status = 1;
1371                 iflib_admin_intr_deferred(ctx);
1372         }
1373
1374         if (reg_icr & E1000_ICR_RXO)
1375                 adapter->rx_overruns++;
1376
1377         return (FILTER_SCHEDULE_THREAD);
1378 }
1379
1380 static void
1381 igb_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq)
1382 {
1383         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims);
1384 }
1385
1386 static void
1387 em_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq)
1388 {
1389         E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims);
1390 }
1391
1392 static void
1393 igb_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq)
1394 {
1395         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims);
1396 }
1397
1398 static void
1399 em_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq)
1400 {
1401         E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims);
1402 }
1403
1404 static int
1405 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1406 {
1407         struct adapter *adapter = iflib_get_softc(ctx);
1408         struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1409
1410         if (adapter->hw.mac.type >= igb_mac_min)
1411                 igb_rx_enable_queue(adapter, rxq);
1412         else
1413                 em_rx_enable_queue(adapter, rxq);
1414         return (0);
1415 }
1416
1417 static int
1418 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1419 {
1420         struct adapter *adapter = iflib_get_softc(ctx);
1421         struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1422
1423         if (adapter->hw.mac.type >= igb_mac_min)
1424                 igb_tx_enable_queue(adapter, txq);
1425         else
1426                 em_tx_enable_queue(adapter, txq);
1427         return (0);
1428 }
1429
1430 /*********************************************************************
1431  *
1432  *  MSI-X RX Interrupt Service routine
1433  *
1434  **********************************************************************/
1435 static int
1436 em_msix_que(void *arg)
1437 {
1438         struct em_rx_queue *que = arg;
1439
1440         ++que->irqs;
1441
1442         return (FILTER_SCHEDULE_THREAD);
1443 }
1444
1445 /*********************************************************************
1446  *
1447  *  MSI-X Link Fast Interrupt Service routine
1448  *
1449  **********************************************************************/
1450 static int
1451 em_msix_link(void *arg)
1452 {
1453         struct adapter *adapter = arg;
1454         u32 reg_icr;
1455
1456         ++adapter->link_irq;
1457         MPASS(adapter->hw.back != NULL);
1458         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1459
1460         if (reg_icr & E1000_ICR_RXO)
1461                 adapter->rx_overruns++;
1462
1463         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1464                 em_handle_link(adapter->ctx);
1465         } else {
1466                 E1000_WRITE_REG(&adapter->hw, E1000_IMS,
1467                                 EM_MSIX_LINK | E1000_IMS_LSC);
1468                 if (adapter->hw.mac.type >= igb_mac_min)
1469                         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1470         }
1471
1472         /*
1473          * Because we must read the ICR for this interrupt
1474          * it may clear other causes using autoclear, for
1475          * this reason we simply create a soft interrupt
1476          * for all these vectors.
1477          */
1478         if (reg_icr && adapter->hw.mac.type < igb_mac_min) {
1479                 E1000_WRITE_REG(&adapter->hw,
1480                         E1000_ICS, adapter->ims);
1481         }
1482
1483         return (FILTER_HANDLED);
1484 }
1485
1486 static void
1487 em_handle_link(void *context)
1488 {
1489         if_ctx_t ctx = context;
1490         struct adapter *adapter = iflib_get_softc(ctx);
1491
1492         adapter->hw.mac.get_link_status = 1;
1493         iflib_admin_intr_deferred(ctx);
1494 }
1495
1496
1497 /*********************************************************************
1498  *
1499  *  Media Ioctl callback
1500  *
1501  *  This routine is called whenever the user queries the status of
1502  *  the interface using ifconfig.
1503  *
1504  **********************************************************************/
1505 static void
1506 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1507 {
1508         struct adapter *adapter = iflib_get_softc(ctx);
1509         u_char fiber_type = IFM_1000_SX;
1510
1511         INIT_DEBUGOUT("em_if_media_status: begin");
1512
1513         iflib_admin_intr_deferred(ctx);
1514
1515         ifmr->ifm_status = IFM_AVALID;
1516         ifmr->ifm_active = IFM_ETHER;
1517
1518         if (!adapter->link_active) {
1519                 return;
1520         }
1521
1522         ifmr->ifm_status |= IFM_ACTIVE;
1523
1524         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
1525             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1526                 if (adapter->hw.mac.type == e1000_82545)
1527                         fiber_type = IFM_1000_LX;
1528                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1529         } else {
1530                 switch (adapter->link_speed) {
1531                 case 10:
1532                         ifmr->ifm_active |= IFM_10_T;
1533                         break;
1534                 case 100:
1535                         ifmr->ifm_active |= IFM_100_TX;
1536                         break;
1537                 case 1000:
1538                         ifmr->ifm_active |= IFM_1000_T;
1539                         break;
1540                 }
1541                 if (adapter->link_duplex == FULL_DUPLEX)
1542                         ifmr->ifm_active |= IFM_FDX;
1543                 else
1544                         ifmr->ifm_active |= IFM_HDX;
1545         }
1546 }
1547
1548 /*********************************************************************
1549  *
1550  *  Media Ioctl callback
1551  *
1552  *  This routine is called when the user changes speed/duplex using
1553  *  media/mediopt option with ifconfig.
1554  *
1555  **********************************************************************/
1556 static int
1557 em_if_media_change(if_ctx_t ctx)
1558 {
1559         struct adapter *adapter = iflib_get_softc(ctx);
1560         struct ifmedia *ifm = iflib_get_media(ctx);
1561
1562         INIT_DEBUGOUT("em_if_media_change: begin");
1563
1564         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1565                 return (EINVAL);
1566
1567         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1568         case IFM_AUTO:
1569                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1570                 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1571                 break;
1572         case IFM_1000_LX:
1573         case IFM_1000_SX:
1574         case IFM_1000_T:
1575                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1576                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1577                 break;
1578         case IFM_100_TX:
1579                 adapter->hw.mac.autoneg = FALSE;
1580                 adapter->hw.phy.autoneg_advertised = 0;
1581                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1582                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1583                 else
1584                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1585                 break;
1586         case IFM_10_T:
1587                 adapter->hw.mac.autoneg = FALSE;
1588                 adapter->hw.phy.autoneg_advertised = 0;
1589                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1590                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1591                 else
1592                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1593                 break;
1594         default:
1595                 device_printf(adapter->dev, "Unsupported media type\n");
1596         }
1597
1598         em_if_init(ctx);
1599
1600         return (0);
1601 }
1602
1603 static int
1604 em_if_set_promisc(if_ctx_t ctx, int flags)
1605 {
1606         struct adapter *adapter = iflib_get_softc(ctx);
1607         u32 reg_rctl;
1608
1609         em_disable_promisc(ctx);
1610
1611         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1612
1613         if (flags & IFF_PROMISC) {
1614                 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1615                 /* Turn this on if you want to see bad packets */
1616                 if (em_debug_sbp)
1617                         reg_rctl |= E1000_RCTL_SBP;
1618                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1619         } else if (flags & IFF_ALLMULTI) {
1620                 reg_rctl |= E1000_RCTL_MPE;
1621                 reg_rctl &= ~E1000_RCTL_UPE;
1622                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1623         }
1624         return (0);
1625 }
1626
1627 static void
1628 em_disable_promisc(if_ctx_t ctx)
1629 {
1630         struct adapter *adapter = iflib_get_softc(ctx);
1631         struct ifnet *ifp = iflib_get_ifp(ctx);
1632         u32 reg_rctl;
1633         int mcnt = 0;
1634
1635         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1636         reg_rctl &= (~E1000_RCTL_UPE);
1637         if (if_getflags(ifp) & IFF_ALLMULTI)
1638                 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1639         else
1640                 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES);
1641         /* Don't disable if in MAX groups */
1642         if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1643                 reg_rctl &=  (~E1000_RCTL_MPE);
1644         reg_rctl &=  (~E1000_RCTL_SBP);
1645         E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1646 }
1647
1648
1649 /*********************************************************************
1650  *  Multicast Update
1651  *
1652  *  This routine is called whenever multicast address list is updated.
1653  *
1654  **********************************************************************/
1655
1656 static void
1657 em_if_multi_set(if_ctx_t ctx)
1658 {
1659         struct adapter *adapter = iflib_get_softc(ctx);
1660         struct ifnet *ifp = iflib_get_ifp(ctx);
1661         u32 reg_rctl = 0;
1662         u8  *mta; /* Multicast array memory */
1663         int mcnt = 0;
1664
1665         IOCTL_DEBUGOUT("em_set_multi: begin");
1666
1667         mta = adapter->mta;
1668         bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1669
1670         if (adapter->hw.mac.type == e1000_82542 &&
1671             adapter->hw.revision_id == E1000_REVISION_2) {
1672                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1673                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1674                         e1000_pci_clear_mwi(&adapter->hw);
1675                 reg_rctl |= E1000_RCTL_RST;
1676                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1677                 msec_delay(5);
1678         }
1679
1680         if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES);
1681
1682         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1683                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1684                 reg_rctl |= E1000_RCTL_MPE;
1685                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1686         } else
1687                 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
1688
1689         if (adapter->hw.mac.type == e1000_82542 &&
1690             adapter->hw.revision_id == E1000_REVISION_2) {
1691                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1692                 reg_rctl &= ~E1000_RCTL_RST;
1693                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1694                 msec_delay(5);
1695                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1696                         e1000_pci_set_mwi(&adapter->hw);
1697         }
1698 }
1699
1700
1701 /*********************************************************************
1702  *  Timer routine
1703  *
1704  *  This routine checks for link status and updates statistics.
1705  *
1706  **********************************************************************/
1707
1708 static void
1709 em_if_timer(if_ctx_t ctx, uint16_t qid)
1710 {
1711         struct adapter *adapter = iflib_get_softc(ctx);
1712         struct em_rx_queue *que;
1713         int i;
1714         int trigger = 0;
1715
1716         if (qid != 0)
1717                 return;
1718
1719         iflib_admin_intr_deferred(ctx);
1720
1721         /* Mask to use in the irq trigger */
1722         if (adapter->intr_type == IFLIB_INTR_MSIX) {
1723                 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++)
1724                         trigger |= que->eims;
1725         } else {
1726                 trigger = E1000_ICS_RXDMT0;
1727         }
1728 }
1729
1730
1731 static void
1732 em_if_update_admin_status(if_ctx_t ctx)
1733 {
1734         struct adapter *adapter = iflib_get_softc(ctx);
1735         struct e1000_hw *hw = &adapter->hw;
1736         device_t dev = iflib_get_dev(ctx);
1737         u32 link_check, thstat, ctrl;
1738
1739         link_check = thstat = ctrl = 0;
1740         /* Get the cached link value or read phy for real */
1741         switch (hw->phy.media_type) {
1742         case e1000_media_type_copper:
1743                 if (hw->mac.get_link_status) {
1744                         if (hw->mac.type == e1000_pch_spt)
1745                                 msec_delay(50);
1746                         /* Do the work to read phy */
1747                         e1000_check_for_link(hw);
1748                         link_check = !hw->mac.get_link_status;
1749                         if (link_check) /* ESB2 fix */
1750                                 e1000_cfg_on_link_up(hw);
1751                 } else {
1752                         link_check = TRUE;
1753                 }
1754                 break;
1755         case e1000_media_type_fiber:
1756                 e1000_check_for_link(hw);
1757                 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1758                             E1000_STATUS_LU);
1759                 break;
1760         case e1000_media_type_internal_serdes:
1761                 e1000_check_for_link(hw);
1762                 link_check = adapter->hw.mac.serdes_has_link;
1763                 break;
1764         /* VF device is type_unknown */
1765         case e1000_media_type_unknown:
1766                 e1000_check_for_link(hw);
1767                 link_check = !hw->mac.get_link_status;
1768                 /* FALLTHROUGH */
1769         default:
1770                 break;
1771         }
1772
1773         /* Check for thermal downshift or shutdown */
1774         if (hw->mac.type == e1000_i350) {
1775                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1776                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1777         }
1778
1779         /* Now check for a transition */
1780         if (link_check && (adapter->link_active == 0)) {
1781                 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
1782                     &adapter->link_duplex);
1783                 /* Check if we must disable SPEED_MODE bit on PCI-E */
1784                 if ((adapter->link_speed != SPEED_1000) &&
1785                     ((hw->mac.type == e1000_82571) ||
1786                     (hw->mac.type == e1000_82572))) {
1787                         int tarc0;
1788                         tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1789                         tarc0 &= ~TARC_SPEED_MODE_BIT;
1790                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1791                 }
1792                 if (bootverbose)
1793                         device_printf(dev, "Link is up %d Mbps %s\n",
1794                             adapter->link_speed,
1795                             ((adapter->link_duplex == FULL_DUPLEX) ?
1796                             "Full Duplex" : "Half Duplex"));
1797                 adapter->link_active = 1;
1798                 adapter->smartspeed = 0;
1799                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) ==
1800                     E1000_CTRL_EXT_LINK_MODE_GMII &&
1801                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1802                         device_printf(dev, "Link: thermal downshift\n");
1803                 /* Delay Link Up for Phy update */
1804                 if (((hw->mac.type == e1000_i210) ||
1805                     (hw->mac.type == e1000_i211)) &&
1806                     (hw->phy.id == I210_I_PHY_ID))
1807                         msec_delay(I210_LINK_DELAY);
1808                 /* Reset if the media type changed. */
1809                 if ((hw->dev_spec._82575.media_changed) &&
1810                         (adapter->hw.mac.type >= igb_mac_min)) {
1811                         hw->dev_spec._82575.media_changed = false;
1812                         adapter->flags |= IGB_MEDIA_RESET;
1813                         em_reset(ctx);
1814                 }
1815                 iflib_link_state_change(ctx, LINK_STATE_UP,
1816                     IF_Mbps(adapter->link_speed));
1817         } else if (!link_check && (adapter->link_active == 1)) {
1818                 adapter->link_speed = 0;
1819                 adapter->link_duplex = 0;
1820                 adapter->link_active = 0;
1821                 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
1822         }
1823         em_update_stats_counters(adapter);
1824
1825         /* Reset LAA into RAR[0] on 82571 */
1826         if ((adapter->hw.mac.type == e1000_82571) &&
1827             e1000_get_laa_state_82571(&adapter->hw))
1828                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1829
1830         if (adapter->hw.mac.type < em_mac_min)
1831                 lem_smartspeed(adapter);
1832
1833         E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC);
1834 }
1835
1836 /*********************************************************************
1837  *
1838  *  This routine disables all traffic on the adapter by issuing a
1839  *  global reset on the MAC and deallocates TX/RX buffers.
1840  *
1841  *  This routine should always be called with BOTH the CORE
1842  *  and TX locks.
1843  **********************************************************************/
1844
1845 static void
1846 em_if_stop(if_ctx_t ctx)
1847 {
1848         struct adapter *adapter = iflib_get_softc(ctx);
1849
1850         INIT_DEBUGOUT("em_stop: begin");
1851
1852         e1000_reset_hw(&adapter->hw);
1853         if (adapter->hw.mac.type >= e1000_82544)
1854                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0);
1855
1856         e1000_led_off(&adapter->hw);
1857         e1000_cleanup_led(&adapter->hw);
1858 }
1859
1860
1861 /*********************************************************************
1862  *
1863  *  Determine hardware revision.
1864  *
1865  **********************************************************************/
1866 static void
1867 em_identify_hardware(if_ctx_t ctx)
1868 {
1869         device_t dev = iflib_get_dev(ctx);
1870         struct adapter *adapter = iflib_get_softc(ctx);
1871
1872         /* Make sure our PCI config space has the necessary stuff set */
1873         adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1874
1875         /* Save off the information about this board */
1876         adapter->hw.vendor_id = pci_get_vendor(dev);
1877         adapter->hw.device_id = pci_get_device(dev);
1878         adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1879         adapter->hw.subsystem_vendor_id =
1880             pci_read_config(dev, PCIR_SUBVEND_0, 2);
1881         adapter->hw.subsystem_device_id =
1882             pci_read_config(dev, PCIR_SUBDEV_0, 2);
1883
1884         /* Do Shared Code Init and Setup */
1885         if (e1000_set_mac_type(&adapter->hw)) {
1886                 device_printf(dev, "Setup init failure\n");
1887                 return;
1888         }
1889 }
1890
1891 static int
1892 em_allocate_pci_resources(if_ctx_t ctx)
1893 {
1894         struct adapter *adapter = iflib_get_softc(ctx);
1895         device_t dev = iflib_get_dev(ctx);
1896         int rid, val;
1897
1898         rid = PCIR_BAR(0);
1899         adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1900             &rid, RF_ACTIVE);
1901         if (adapter->memory == NULL) {
1902                 device_printf(dev, "Unable to allocate bus resource: memory\n");
1903                 return (ENXIO);
1904         }
1905         adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory);
1906         adapter->osdep.mem_bus_space_handle =
1907             rman_get_bushandle(adapter->memory);
1908         adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle;
1909
1910         /* Only older adapters use IO mapping */
1911         if (adapter->hw.mac.type < em_mac_min &&
1912             adapter->hw.mac.type > e1000_82543) {
1913                 /* Figure our where our IO BAR is ? */
1914                 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1915                         val = pci_read_config(dev, rid, 4);
1916                         if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1917                                 break;
1918                         }
1919                         rid += 4;
1920                         /* check for 64bit BAR */
1921                         if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1922                                 rid += 4;
1923                 }
1924                 if (rid >= PCIR_CIS) {
1925                         device_printf(dev, "Unable to locate IO BAR\n");
1926                         return (ENXIO);
1927                 }
1928                 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
1929                     &rid, RF_ACTIVE);
1930                 if (adapter->ioport == NULL) {
1931                         device_printf(dev, "Unable to allocate bus resource: "
1932                             "ioport\n");
1933                         return (ENXIO);
1934                 }
1935                 adapter->hw.io_base = 0;
1936                 adapter->osdep.io_bus_space_tag =
1937                     rman_get_bustag(adapter->ioport);
1938                 adapter->osdep.io_bus_space_handle =
1939                     rman_get_bushandle(adapter->ioport);
1940         }
1941
1942         adapter->hw.back = &adapter->osdep;
1943
1944         return (0);
1945 }
1946
1947 /*********************************************************************
1948  *
1949  *  Set up the MSI-X Interrupt handlers
1950  *
1951  **********************************************************************/
1952 static int
1953 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
1954 {
1955         struct adapter *adapter = iflib_get_softc(ctx);
1956         struct em_rx_queue *rx_que = adapter->rx_queues;
1957         struct em_tx_queue *tx_que = adapter->tx_queues;
1958         int error, rid, i, vector = 0, rx_vectors;
1959         char buf[16];
1960
1961         /* First set up ring resources */
1962         for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) {
1963                 rid = vector + 1;
1964                 snprintf(buf, sizeof(buf), "rxq%d", i);
1965                 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
1966                 if (error) {
1967                         device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
1968                         adapter->rx_num_queues = i + 1;
1969                         goto fail;
1970                 }
1971
1972                 rx_que->msix =  vector;
1973
1974                 /*
1975                  * Set the bit to enable interrupt
1976                  * in E1000_IMS -- bits 20 and 21
1977                  * are for RX0 and RX1, note this has
1978                  * NOTHING to do with the MSI-X vector
1979                  */
1980                 if (adapter->hw.mac.type == e1000_82574) {
1981                         rx_que->eims = 1 << (20 + i);
1982                         adapter->ims |= rx_que->eims;
1983                         adapter->ivars |= (8 | rx_que->msix) << (i * 4);
1984                 } else if (adapter->hw.mac.type == e1000_82575)
1985                         rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
1986                 else
1987                         rx_que->eims = 1 << vector;
1988         }
1989         rx_vectors = vector;
1990
1991         vector = 0;
1992         for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) {
1993                 snprintf(buf, sizeof(buf), "txq%d", i);
1994                 tx_que = &adapter->tx_queues[i];
1995                 iflib_softirq_alloc_generic(ctx,
1996                     &adapter->rx_queues[i % adapter->rx_num_queues].que_irq,
1997                     IFLIB_INTR_TX, tx_que, tx_que->me, buf);
1998
1999                 tx_que->msix = (vector % adapter->tx_num_queues);
2000
2001                 /*
2002                  * Set the bit to enable interrupt
2003                  * in E1000_IMS -- bits 22 and 23
2004                  * are for TX0 and TX1, note this has
2005                  * NOTHING to do with the MSI-X vector
2006                  */
2007                 if (adapter->hw.mac.type == e1000_82574) {
2008                         tx_que->eims = 1 << (22 + i);
2009                         adapter->ims |= tx_que->eims;
2010                         adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
2011                 } else if (adapter->hw.mac.type == e1000_82575) {
2012                         tx_que->eims = E1000_EICR_TX_QUEUE0 << (i %  adapter->tx_num_queues);
2013                 } else {
2014                         tx_que->eims = 1 << (i %  adapter->tx_num_queues);
2015                 }
2016         }
2017
2018         /* Link interrupt */
2019         rid = rx_vectors + 1;
2020         error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq");
2021
2022         if (error) {
2023                 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
2024                 goto fail;
2025         }
2026         adapter->linkvec = rx_vectors;
2027         if (adapter->hw.mac.type < igb_mac_min) {
2028                 adapter->ivars |=  (8 | rx_vectors) << 16;
2029                 adapter->ivars |= 0x80000000;
2030         }
2031         return (0);
2032 fail:
2033         iflib_irq_free(ctx, &adapter->irq);
2034         rx_que = adapter->rx_queues;
2035         for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++)
2036                 iflib_irq_free(ctx, &rx_que->que_irq);
2037         return (error);
2038 }
2039
2040 static void
2041 igb_configure_queues(struct adapter *adapter)
2042 {
2043         struct e1000_hw *hw = &adapter->hw;
2044         struct em_rx_queue *rx_que;
2045         struct em_tx_queue *tx_que;
2046         u32 tmp, ivar = 0, newitr = 0;
2047
2048         /* First turn on RSS capability */
2049         if (adapter->hw.mac.type != e1000_82575)
2050                 E1000_WRITE_REG(hw, E1000_GPIE,
2051                     E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
2052                     E1000_GPIE_PBA | E1000_GPIE_NSICR);
2053
2054         /* Turn on MSI-X */
2055         switch (adapter->hw.mac.type) {
2056         case e1000_82580:
2057         case e1000_i350:
2058         case e1000_i354:
2059         case e1000_i210:
2060         case e1000_i211:
2061         case e1000_vfadapt:
2062         case e1000_vfadapt_i350:
2063                 /* RX entries */
2064                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2065                         u32 index = i >> 1;
2066                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2067                         rx_que = &adapter->rx_queues[i];
2068                         if (i & 1) {
2069                                 ivar &= 0xFF00FFFF;
2070                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2071                         } else {
2072                                 ivar &= 0xFFFFFF00;
2073                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2074                         }
2075                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2076                 }
2077                 /* TX entries */
2078                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2079                         u32 index = i >> 1;
2080                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2081                         tx_que = &adapter->tx_queues[i];
2082                         if (i & 1) {
2083                                 ivar &= 0x00FFFFFF;
2084                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2085                         } else {
2086                                 ivar &= 0xFFFF00FF;
2087                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2088                         }
2089                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2090                         adapter->que_mask |= tx_que->eims;
2091                 }
2092
2093                 /* And for the link interrupt */
2094                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2095                 adapter->link_mask = 1 << adapter->linkvec;
2096                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2097                 break;
2098         case e1000_82576:
2099                 /* RX entries */
2100                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2101                         u32 index = i & 0x7; /* Each IVAR has two entries */
2102                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2103                         rx_que = &adapter->rx_queues[i];
2104                         if (i < 8) {
2105                                 ivar &= 0xFFFFFF00;
2106                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2107                         } else {
2108                                 ivar &= 0xFF00FFFF;
2109                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2110                         }
2111                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2112                         adapter->que_mask |= rx_que->eims;
2113                 }
2114                 /* TX entries */
2115                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2116                         u32 index = i & 0x7; /* Each IVAR has two entries */
2117                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2118                         tx_que = &adapter->tx_queues[i];
2119                         if (i < 8) {
2120                                 ivar &= 0xFFFF00FF;
2121                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2122                         } else {
2123                                 ivar &= 0x00FFFFFF;
2124                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2125                         }
2126                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2127                         adapter->que_mask |= tx_que->eims;
2128                 }
2129
2130                 /* And for the link interrupt */
2131                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2132                 adapter->link_mask = 1 << adapter->linkvec;
2133                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2134                 break;
2135
2136         case e1000_82575:
2137                 /* enable MSI-X support*/
2138                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2139                 tmp |= E1000_CTRL_EXT_PBA_CLR;
2140                 /* Auto-Mask interrupts upon ICR read. */
2141                 tmp |= E1000_CTRL_EXT_EIAME;
2142                 tmp |= E1000_CTRL_EXT_IRCA;
2143                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2144
2145                 /* Queues */
2146                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2147                         rx_que = &adapter->rx_queues[i];
2148                         tmp = E1000_EICR_RX_QUEUE0 << i;
2149                         tmp |= E1000_EICR_TX_QUEUE0 << i;
2150                         rx_que->eims = tmp;
2151                         E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2152                             i, rx_que->eims);
2153                         adapter->que_mask |= rx_que->eims;
2154                 }
2155
2156                 /* Link */
2157                 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec),
2158                     E1000_EIMS_OTHER);
2159                 adapter->link_mask |= E1000_EIMS_OTHER;
2160         default:
2161                 break;
2162         }
2163
2164         /* Set the starting interrupt rate */
2165         if (em_max_interrupt_rate > 0)
2166                 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2167
2168         if (hw->mac.type == e1000_82575)
2169                 newitr |= newitr << 16;
2170         else
2171                 newitr |= E1000_EITR_CNT_IGNR;
2172
2173         for (int i = 0; i < adapter->rx_num_queues; i++) {
2174                 rx_que = &adapter->rx_queues[i];
2175                 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2176         }
2177
2178         return;
2179 }
2180
2181 static void
2182 em_free_pci_resources(if_ctx_t ctx)
2183 {
2184         struct adapter *adapter = iflib_get_softc(ctx);
2185         struct em_rx_queue *que = adapter->rx_queues;
2186         device_t dev = iflib_get_dev(ctx);
2187
2188         /* Release all MSI-X queue resources */
2189         if (adapter->intr_type == IFLIB_INTR_MSIX)
2190                 iflib_irq_free(ctx, &adapter->irq);
2191
2192         for (int i = 0; i < adapter->rx_num_queues; i++, que++) {
2193                 iflib_irq_free(ctx, &que->que_irq);
2194         }
2195
2196         if (adapter->memory != NULL) {
2197                 bus_release_resource(dev, SYS_RES_MEMORY,
2198                     rman_get_rid(adapter->memory), adapter->memory);
2199                 adapter->memory = NULL;
2200         }
2201
2202         if (adapter->flash != NULL) {
2203                 bus_release_resource(dev, SYS_RES_MEMORY,
2204                     rman_get_rid(adapter->flash), adapter->flash);
2205                 adapter->flash = NULL;
2206         }
2207
2208         if (adapter->ioport != NULL) {
2209                 bus_release_resource(dev, SYS_RES_IOPORT,
2210                     rman_get_rid(adapter->ioport), adapter->ioport);
2211                 adapter->ioport = NULL;
2212         }
2213 }
2214
2215 /* Set up MSI or MSI-X */
2216 static int
2217 em_setup_msix(if_ctx_t ctx)
2218 {
2219         struct adapter *adapter = iflib_get_softc(ctx);
2220
2221         if (adapter->hw.mac.type == e1000_82574) {
2222                 em_enable_vectors_82574(ctx);
2223         }
2224         return (0);
2225 }
2226
2227 /*********************************************************************
2228  *
2229  *  Initialize the hardware to a configuration
2230  *  as specified by the adapter structure.
2231  *
2232  **********************************************************************/
2233
2234 static void
2235 lem_smartspeed(struct adapter *adapter)
2236 {
2237         u16 phy_tmp;
2238
2239         if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) ||
2240             adapter->hw.mac.autoneg == 0 ||
2241             (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2242                 return;
2243
2244         if (adapter->smartspeed == 0) {
2245                 /* If Master/Slave config fault is asserted twice,
2246                  * we assume back-to-back */
2247                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2248                 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2249                         return;
2250                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2251                 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2252                         e1000_read_phy_reg(&adapter->hw,
2253                             PHY_1000T_CTRL, &phy_tmp);
2254                         if(phy_tmp & CR_1000T_MS_ENABLE) {
2255                                 phy_tmp &= ~CR_1000T_MS_ENABLE;
2256                                 e1000_write_phy_reg(&adapter->hw,
2257                                     PHY_1000T_CTRL, phy_tmp);
2258                                 adapter->smartspeed++;
2259                                 if(adapter->hw.mac.autoneg &&
2260                                    !e1000_copper_link_autoneg(&adapter->hw) &&
2261                                    !e1000_read_phy_reg(&adapter->hw,
2262                                     PHY_CONTROL, &phy_tmp)) {
2263                                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2264                                                     MII_CR_RESTART_AUTO_NEG);
2265                                         e1000_write_phy_reg(&adapter->hw,
2266                                             PHY_CONTROL, phy_tmp);
2267                                 }
2268                         }
2269                 }
2270                 return;
2271         } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2272                 /* If still no link, perhaps using 2/3 pair cable */
2273                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2274                 phy_tmp |= CR_1000T_MS_ENABLE;
2275                 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2276                 if(adapter->hw.mac.autoneg &&
2277                    !e1000_copper_link_autoneg(&adapter->hw) &&
2278                    !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2279                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2280                                     MII_CR_RESTART_AUTO_NEG);
2281                         e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2282                 }
2283         }
2284         /* Restart process after EM_SMARTSPEED_MAX iterations */
2285         if(adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2286                 adapter->smartspeed = 0;
2287 }
2288
2289 /*********************************************************************
2290  *
2291  *  Initialize the DMA Coalescing feature
2292  *
2293  **********************************************************************/
2294 static void
2295 igb_init_dmac(struct adapter *adapter, u32 pba)
2296 {
2297         device_t        dev = adapter->dev;
2298         struct e1000_hw *hw = &adapter->hw;
2299         u32             dmac, reg = ~E1000_DMACR_DMAC_EN;
2300         u16             hwm;
2301         u16             max_frame_size;
2302
2303         if (hw->mac.type == e1000_i211)
2304                 return;
2305
2306         max_frame_size = adapter->shared->isc_max_frame_size;
2307         if (hw->mac.type > e1000_82580) {
2308
2309                 if (adapter->dmac == 0) { /* Disabling it */
2310                         E1000_WRITE_REG(hw, E1000_DMACR, reg);
2311                         return;
2312                 } else
2313                         device_printf(dev, "DMA Coalescing enabled\n");
2314
2315                 /* Set starting threshold */
2316                 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
2317
2318                 hwm = 64 * pba - max_frame_size / 16;
2319                 if (hwm < 64 * (pba - 6))
2320                         hwm = 64 * (pba - 6);
2321                 reg = E1000_READ_REG(hw, E1000_FCRTC);
2322                 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
2323                 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
2324                     & E1000_FCRTC_RTH_COAL_MASK);
2325                 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
2326
2327
2328                 dmac = pba - max_frame_size / 512;
2329                 if (dmac < pba - 10)
2330                         dmac = pba - 10;
2331                 reg = E1000_READ_REG(hw, E1000_DMACR);
2332                 reg &= ~E1000_DMACR_DMACTHR_MASK;
2333                 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT)
2334                     & E1000_DMACR_DMACTHR_MASK);
2335
2336                 /* transition to L0x or L1 if available..*/
2337                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
2338
2339                 /* Check if status is 2.5Gb backplane connection
2340                 * before configuration of watchdog timer, which is
2341                 * in msec values in 12.8usec intervals
2342                 * watchdog timer= msec values in 32usec intervals
2343                 * for non 2.5Gb connection
2344                 */
2345                 if (hw->mac.type == e1000_i354) {
2346                         int status = E1000_READ_REG(hw, E1000_STATUS);
2347                         if ((status & E1000_STATUS_2P5_SKU) &&
2348                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2349                                 reg |= ((adapter->dmac * 5) >> 6);
2350                         else
2351                                 reg |= (adapter->dmac >> 5);
2352                 } else {
2353                         reg |= (adapter->dmac >> 5);
2354                 }
2355
2356                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2357
2358                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
2359
2360                 /* Set the interval before transition */
2361                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
2362                 if (hw->mac.type == e1000_i350)
2363                         reg |= IGB_DMCTLX_DCFLUSH_DIS;
2364                 /*
2365                 ** in 2.5Gb connection, TTLX unit is 0.4 usec
2366                 ** which is 0x4*2 = 0xA. But delay is still 4 usec
2367                 */
2368                 if (hw->mac.type == e1000_i354) {
2369                         int status = E1000_READ_REG(hw, E1000_STATUS);
2370                         if ((status & E1000_STATUS_2P5_SKU) &&
2371                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2372                                 reg |= 0xA;
2373                         else
2374                                 reg |= 0x4;
2375                 } else {
2376                         reg |= 0x4;
2377                 }
2378
2379                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
2380
2381                 /* free space in tx packet buffer to wake from DMA coal */
2382                 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE -
2383                     (2 * max_frame_size)) >> 6);
2384
2385                 /* make low power state decision controlled by DMA coal */
2386                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2387                 reg &= ~E1000_PCIEMISC_LX_DECISION;
2388                 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
2389
2390         } else if (hw->mac.type == e1000_82580) {
2391                 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2392                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
2393                     reg & ~E1000_PCIEMISC_LX_DECISION);
2394                 E1000_WRITE_REG(hw, E1000_DMACR, 0);
2395         }
2396 }
2397
2398 static void
2399 em_reset(if_ctx_t ctx)
2400 {
2401         device_t dev = iflib_get_dev(ctx);
2402         struct adapter *adapter = iflib_get_softc(ctx);
2403         struct ifnet *ifp = iflib_get_ifp(ctx);
2404         struct e1000_hw *hw = &adapter->hw;
2405         u16 rx_buffer_size;
2406         u32 pba;
2407
2408         INIT_DEBUGOUT("em_reset: begin");
2409         /* Let the firmware know the OS is in control */
2410         em_get_hw_control(adapter);
2411
2412         /* Set up smart power down as default off on newer adapters. */
2413         if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2414             hw->mac.type == e1000_82572)) {
2415                 u16 phy_tmp = 0;
2416
2417                 /* Speed up time to link by disabling smart power down. */
2418                 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2419                 phy_tmp &= ~IGP02E1000_PM_SPD;
2420                 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2421         }
2422
2423         /*
2424          * Packet Buffer Allocation (PBA)
2425          * Writing PBA sets the receive portion of the buffer
2426          * the remainder is used for the transmit buffer.
2427          */
2428         switch (hw->mac.type) {
2429         /* Total Packet Buffer on these is 48K */
2430         case e1000_82571:
2431         case e1000_82572:
2432         case e1000_80003es2lan:
2433                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2434                 break;
2435         case e1000_82573: /* 82573: Total Packet Buffer is 32K */
2436                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2437                 break;
2438         case e1000_82574:
2439         case e1000_82583:
2440                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2441                 break;
2442         case e1000_ich8lan:
2443                 pba = E1000_PBA_8K;
2444                 break;
2445         case e1000_ich9lan:
2446         case e1000_ich10lan:
2447                 /* Boost Receive side for jumbo frames */
2448                 if (adapter->hw.mac.max_frame_size > 4096)
2449                         pba = E1000_PBA_14K;
2450                 else
2451                         pba = E1000_PBA_10K;
2452                 break;
2453         case e1000_pchlan:
2454         case e1000_pch2lan:
2455         case e1000_pch_lpt:
2456         case e1000_pch_spt:
2457         case e1000_pch_cnp:
2458                 pba = E1000_PBA_26K;
2459                 break;
2460         case e1000_82575:
2461                 pba = E1000_PBA_32K;
2462                 break;
2463         case e1000_82576:
2464         case e1000_vfadapt:
2465                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2466                 pba &= E1000_RXPBS_SIZE_MASK_82576;
2467                 break;
2468         case e1000_82580:
2469         case e1000_i350:
2470         case e1000_i354:
2471         case e1000_vfadapt_i350:
2472                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2473                 pba = e1000_rxpbs_adjust_82580(pba);
2474                 break;
2475         case e1000_i210:
2476         case e1000_i211:
2477                 pba = E1000_PBA_34K;
2478                 break;
2479         default:
2480                 if (adapter->hw.mac.max_frame_size > 8192)
2481                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2482                 else
2483                         pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2484         }
2485
2486         /* Special needs in case of Jumbo frames */
2487         if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) {
2488                 u32 tx_space, min_tx, min_rx;
2489                 pba = E1000_READ_REG(hw, E1000_PBA);
2490                 tx_space = pba >> 16;
2491                 pba &= 0xffff;
2492                 min_tx = (adapter->hw.mac.max_frame_size +
2493                     sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
2494                 min_tx = roundup2(min_tx, 1024);
2495                 min_tx >>= 10;
2496                 min_rx = adapter->hw.mac.max_frame_size;
2497                 min_rx = roundup2(min_rx, 1024);
2498                 min_rx >>= 10;
2499                 if (tx_space < min_tx &&
2500                     ((min_tx - tx_space) < pba)) {
2501                         pba = pba - (min_tx - tx_space);
2502                         /*
2503                          * if short on rx space, rx wins
2504                          * and must trump tx adjustment
2505                          */
2506                         if (pba < min_rx)
2507                                 pba = min_rx;
2508                 }
2509                 E1000_WRITE_REG(hw, E1000_PBA, pba);
2510         }
2511
2512         if (hw->mac.type < igb_mac_min)
2513                 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
2514
2515         INIT_DEBUGOUT1("em_reset: pba=%dK",pba);
2516
2517         /*
2518          * These parameters control the automatic generation (Tx) and
2519          * response (Rx) to Ethernet PAUSE frames.
2520          * - High water mark should allow for at least two frames to be
2521          *   received after sending an XOFF.
2522          * - Low water mark works best when it is very near the high water mark.
2523          *   This allows the receiver to restart by sending XON when it has
2524          *   drained a bit. Here we use an arbitrary value of 1500 which will
2525          *   restart after one full frame is pulled from the buffer. There
2526          *   could be several smaller frames in the buffer and if so they will
2527          *   not trigger the XON until their total number reduces the buffer
2528          *   by 1500.
2529          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2530          */
2531         rx_buffer_size = (pba & 0xffff) << 10;
2532         hw->fc.high_water = rx_buffer_size -
2533             roundup2(adapter->hw.mac.max_frame_size, 1024);
2534         hw->fc.low_water = hw->fc.high_water - 1500;
2535
2536         if (adapter->fc) /* locally set flow control value? */
2537                 hw->fc.requested_mode = adapter->fc;
2538         else
2539                 hw->fc.requested_mode = e1000_fc_full;
2540
2541         if (hw->mac.type == e1000_80003es2lan)
2542                 hw->fc.pause_time = 0xFFFF;
2543         else
2544                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
2545
2546         hw->fc.send_xon = TRUE;
2547
2548         /* Device specific overrides/settings */
2549         switch (hw->mac.type) {
2550         case e1000_pchlan:
2551                 /* Workaround: no TX flow ctrl for PCH */
2552                 hw->fc.requested_mode = e1000_fc_rx_pause;
2553                 hw->fc.pause_time = 0xFFFF; /* override */
2554                 if (if_getmtu(ifp) > ETHERMTU) {
2555                         hw->fc.high_water = 0x3500;
2556                         hw->fc.low_water = 0x1500;
2557                 } else {
2558                         hw->fc.high_water = 0x5000;
2559                         hw->fc.low_water = 0x3000;
2560                 }
2561                 hw->fc.refresh_time = 0x1000;
2562                 break;
2563         case e1000_pch2lan:
2564         case e1000_pch_lpt:
2565         case e1000_pch_spt:
2566         case e1000_pch_cnp:
2567                 hw->fc.high_water = 0x5C20;
2568                 hw->fc.low_water = 0x5048;
2569                 hw->fc.pause_time = 0x0650;
2570                 hw->fc.refresh_time = 0x0400;
2571                 /* Jumbos need adjusted PBA */
2572                 if (if_getmtu(ifp) > ETHERMTU)
2573                         E1000_WRITE_REG(hw, E1000_PBA, 12);
2574                 else
2575                         E1000_WRITE_REG(hw, E1000_PBA, 26);
2576                 break;
2577         case e1000_82575:
2578         case e1000_82576:
2579                 /* 8-byte granularity */
2580                 hw->fc.low_water = hw->fc.high_water - 8;
2581                 break;
2582         case e1000_82580:
2583         case e1000_i350:
2584         case e1000_i354:
2585         case e1000_i210:
2586         case e1000_i211:
2587         case e1000_vfadapt:
2588         case e1000_vfadapt_i350:
2589                 /* 16-byte granularity */
2590                 hw->fc.low_water = hw->fc.high_water - 16;
2591                 break;
2592         case e1000_ich9lan:
2593         case e1000_ich10lan:
2594                 if (if_getmtu(ifp) > ETHERMTU) {
2595                         hw->fc.high_water = 0x2800;
2596                         hw->fc.low_water = hw->fc.high_water - 8;
2597                         break;
2598                 }
2599                 /* FALLTHROUGH */
2600         default:
2601                 if (hw->mac.type == e1000_80003es2lan)
2602                         hw->fc.pause_time = 0xFFFF;
2603                 break;
2604         }
2605
2606         /* Issue a global reset */
2607         e1000_reset_hw(hw);
2608         if (adapter->hw.mac.type >= igb_mac_min) {
2609                 E1000_WRITE_REG(hw, E1000_WUC, 0);
2610         } else {
2611                 E1000_WRITE_REG(hw, E1000_WUFC, 0);
2612                 em_disable_aspm(adapter);
2613         }
2614         if (adapter->flags & IGB_MEDIA_RESET) {
2615                 e1000_setup_init_funcs(hw, TRUE);
2616                 e1000_get_bus_info(hw);
2617                 adapter->flags &= ~IGB_MEDIA_RESET;
2618         }
2619         /* and a re-init */
2620         if (e1000_init_hw(hw) < 0) {
2621                 device_printf(dev, "Hardware Initialization Failed\n");
2622                 return;
2623         }
2624         if (adapter->hw.mac.type >= igb_mac_min)
2625                 igb_init_dmac(adapter, pba);
2626
2627         E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2628         e1000_get_phy_info(hw);
2629         e1000_check_for_link(hw);
2630 }
2631
2632 #define RSSKEYLEN 10
2633 static void
2634 em_initialize_rss_mapping(struct adapter *adapter)
2635 {
2636         uint8_t  rss_key[4 * RSSKEYLEN];
2637         uint32_t reta = 0;
2638         struct e1000_hw *hw = &adapter->hw;
2639         int i;
2640
2641         /*
2642          * Configure RSS key
2643          */
2644         arc4rand(rss_key, sizeof(rss_key), 0);
2645         for (i = 0; i < RSSKEYLEN; ++i) {
2646                 uint32_t rssrk = 0;
2647
2648                 rssrk = EM_RSSRK_VAL(rss_key, i);
2649                 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2650         }
2651
2652         /*
2653          * Configure RSS redirect table in following fashion:
2654          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2655          */
2656         for (i = 0; i < sizeof(reta); ++i) {
2657                 uint32_t q;
2658
2659                 q = (i % adapter->rx_num_queues) << 7;
2660                 reta |= q << (8 * i);
2661         }
2662
2663         for (i = 0; i < 32; ++i)
2664                 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2665
2666         E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2667                         E1000_MRQC_RSS_FIELD_IPV4_TCP |
2668                         E1000_MRQC_RSS_FIELD_IPV4 |
2669                         E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2670                         E1000_MRQC_RSS_FIELD_IPV6_EX |
2671                         E1000_MRQC_RSS_FIELD_IPV6);
2672
2673 }
2674
2675 static void
2676 igb_initialize_rss_mapping(struct adapter *adapter)
2677 {
2678         struct e1000_hw *hw = &adapter->hw;
2679         int i;
2680         int queue_id;
2681         u32 reta;
2682         u32 rss_key[10], mrqc, shift = 0;
2683
2684         /* XXX? */
2685         if (adapter->hw.mac.type == e1000_82575)
2686                 shift = 6;
2687
2688         /*
2689          * The redirection table controls which destination
2690          * queue each bucket redirects traffic to.
2691          * Each DWORD represents four queues, with the LSB
2692          * being the first queue in the DWORD.
2693          *
2694          * This just allocates buckets to queues using round-robin
2695          * allocation.
2696          *
2697          * NOTE: It Just Happens to line up with the default
2698          * RSS allocation method.
2699          */
2700
2701         /* Warning FM follows */
2702         reta = 0;
2703         for (i = 0; i < 128; i++) {
2704 #ifdef RSS
2705                 queue_id = rss_get_indirection_to_bucket(i);
2706                 /*
2707                  * If we have more queues than buckets, we'll
2708                  * end up mapping buckets to a subset of the
2709                  * queues.
2710                  *
2711                  * If we have more buckets than queues, we'll
2712                  * end up instead assigning multiple buckets
2713                  * to queues.
2714                  *
2715                  * Both are suboptimal, but we need to handle
2716                  * the case so we don't go out of bounds
2717                  * indexing arrays and such.
2718                  */
2719                 queue_id = queue_id % adapter->rx_num_queues;
2720 #else
2721                 queue_id = (i % adapter->rx_num_queues);
2722 #endif
2723                 /* Adjust if required */
2724                 queue_id = queue_id << shift;
2725
2726                 /*
2727                  * The low 8 bits are for hash value (n+0);
2728                  * The next 8 bits are for hash value (n+1), etc.
2729                  */
2730                 reta = reta >> 8;
2731                 reta = reta | ( ((uint32_t) queue_id) << 24);
2732                 if ((i & 3) == 3) {
2733                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2734                         reta = 0;
2735                 }
2736         }
2737
2738         /* Now fill in hash table */
2739
2740         /*
2741          * MRQC: Multiple Receive Queues Command
2742          * Set queuing to RSS control, number depends on the device.
2743          */
2744         mrqc = E1000_MRQC_ENABLE_RSS_8Q;
2745
2746 #ifdef RSS
2747         /* XXX ew typecasting */
2748         rss_getkey((uint8_t *) &rss_key);
2749 #else
2750         arc4rand(&rss_key, sizeof(rss_key), 0);
2751 #endif
2752         for (i = 0; i < 10; i++)
2753                 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]);
2754
2755         /*
2756          * Configure the RSS fields to hash upon.
2757          */
2758         mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2759             E1000_MRQC_RSS_FIELD_IPV4_TCP);
2760         mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2761             E1000_MRQC_RSS_FIELD_IPV6_TCP);
2762         mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2763             E1000_MRQC_RSS_FIELD_IPV6_UDP);
2764         mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2765             E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2766
2767         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2768 }
2769
2770 /*********************************************************************
2771  *
2772  *  Setup networking device structure and register an interface.
2773  *
2774  **********************************************************************/
2775 static int
2776 em_setup_interface(if_ctx_t ctx)
2777 {
2778         struct ifnet *ifp = iflib_get_ifp(ctx);
2779         struct adapter *adapter = iflib_get_softc(ctx);
2780         if_softc_ctx_t scctx = adapter->shared;
2781
2782         INIT_DEBUGOUT("em_setup_interface: begin");
2783
2784         /* Single Queue */
2785         if (adapter->tx_num_queues == 1) {
2786                 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
2787                 if_setsendqready(ifp);
2788         }
2789
2790         /*
2791          * Specify the media types supported by this adapter and register
2792          * callbacks to update media and link information
2793          */
2794         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
2795             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
2796                 u_char fiber_type = IFM_1000_SX;        /* default type */
2797
2798                 if (adapter->hw.mac.type == e1000_82545)
2799                         fiber_type = IFM_1000_LX;
2800                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
2801                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2802         } else {
2803                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2804                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2805                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2806                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2807                 if (adapter->hw.phy.type != e1000_phy_ife) {
2808                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2809                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2810                 }
2811         }
2812         ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2813         ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO);
2814         return (0);
2815 }
2816
2817 static int
2818 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
2819 {
2820         struct adapter *adapter = iflib_get_softc(ctx);
2821         if_softc_ctx_t scctx = adapter->shared;
2822         int error = E1000_SUCCESS;
2823         struct em_tx_queue *que;
2824         int i, j;
2825
2826         MPASS(adapter->tx_num_queues > 0);
2827         MPASS(adapter->tx_num_queues == ntxqsets);
2828
2829         /* First allocate the top level queue structs */
2830         if (!(adapter->tx_queues =
2831             (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
2832             adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2833                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2834                 return(ENOMEM);
2835         }
2836
2837         for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) {
2838                 /* Set up some basics */
2839
2840                 struct tx_ring *txr = &que->txr;
2841                 txr->adapter = que->adapter = adapter;
2842                 que->me = txr->me =  i;
2843
2844                 /* Allocate report status array */
2845                 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2846                         device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n");
2847                         error = ENOMEM;
2848                         goto fail;
2849                 }
2850                 for (j = 0; j < scctx->isc_ntxd[0]; j++)
2851                         txr->tx_rsq[j] = QIDX_INVALID;
2852                 /* get the virtual and physical address of the hardware queues */
2853                 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
2854                 txr->tx_paddr = paddrs[i*ntxqs];
2855         }
2856
2857         if (bootverbose)
2858                 device_printf(iflib_get_dev(ctx),
2859                     "allocated for %d tx_queues\n", adapter->tx_num_queues);
2860         return (0);
2861 fail:
2862         em_if_queues_free(ctx);
2863         return (error);
2864 }
2865
2866 static int
2867 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
2868 {
2869         struct adapter *adapter = iflib_get_softc(ctx);
2870         int error = E1000_SUCCESS;
2871         struct em_rx_queue *que;
2872         int i;
2873
2874         MPASS(adapter->rx_num_queues > 0);
2875         MPASS(adapter->rx_num_queues == nrxqsets);
2876
2877         /* First allocate the top level queue structs */
2878         if (!(adapter->rx_queues =
2879             (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
2880             adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2881                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2882                 error = ENOMEM;
2883                 goto fail;
2884         }
2885
2886         for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) {
2887                 /* Set up some basics */
2888                 struct rx_ring *rxr = &que->rxr;
2889                 rxr->adapter = que->adapter = adapter;
2890                 rxr->que = que;
2891                 que->me = rxr->me =  i;
2892
2893                 /* get the virtual and physical address of the hardware queues */
2894                 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
2895                 rxr->rx_paddr = paddrs[i*nrxqs];
2896         }
2897
2898         if (bootverbose)
2899                 device_printf(iflib_get_dev(ctx),
2900                     "allocated for %d rx_queues\n", adapter->rx_num_queues);
2901
2902         return (0);
2903 fail:
2904         em_if_queues_free(ctx);
2905         return (error);
2906 }
2907
2908 static void
2909 em_if_queues_free(if_ctx_t ctx)
2910 {
2911         struct adapter *adapter = iflib_get_softc(ctx);
2912         struct em_tx_queue *tx_que = adapter->tx_queues;
2913         struct em_rx_queue *rx_que = adapter->rx_queues;
2914
2915         if (tx_que != NULL) {
2916                 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
2917                         struct tx_ring *txr = &tx_que->txr;
2918                         if (txr->tx_rsq == NULL)
2919                                 break;
2920
2921                         free(txr->tx_rsq, M_DEVBUF);
2922                         txr->tx_rsq = NULL;
2923                 }
2924                 free(adapter->tx_queues, M_DEVBUF);
2925                 adapter->tx_queues = NULL;
2926         }
2927
2928         if (rx_que != NULL) {
2929                 free(adapter->rx_queues, M_DEVBUF);
2930                 adapter->rx_queues = NULL;
2931         }
2932
2933         em_release_hw_control(adapter);
2934
2935         if (adapter->mta != NULL) {
2936                 free(adapter->mta, M_DEVBUF);
2937         }
2938 }
2939
2940 /*********************************************************************
2941  *
2942  *  Enable transmit unit.
2943  *
2944  **********************************************************************/
2945 static void
2946 em_initialize_transmit_unit(if_ctx_t ctx)
2947 {
2948         struct adapter *adapter = iflib_get_softc(ctx);
2949         if_softc_ctx_t scctx = adapter->shared;
2950         struct em_tx_queue *que;
2951         struct tx_ring  *txr;
2952         struct e1000_hw *hw = &adapter->hw;
2953         u32 tctl, txdctl = 0, tarc, tipg = 0;
2954
2955         INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
2956
2957         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
2958                 u64 bus_addr;
2959                 caddr_t offp, endp;
2960
2961                 que = &adapter->tx_queues[i];
2962                 txr = &que->txr;
2963                 bus_addr = txr->tx_paddr;
2964
2965                 /* Clear checksum offload context. */
2966                 offp = (caddr_t)&txr->csum_flags;
2967                 endp = (caddr_t)(txr + 1);
2968                 bzero(offp, endp - offp);
2969
2970                 /* Base and Len of TX Ring */
2971                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
2972                     scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
2973                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
2974                     (u32)(bus_addr >> 32));
2975                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
2976                     (u32)bus_addr);
2977                 /* Init the HEAD/TAIL indices */
2978                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
2979                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
2980
2981                 HW_DEBUGOUT2("Base = %x, Length = %x\n",
2982                     E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)),
2983                     E1000_READ_REG(&adapter->hw, E1000_TDLEN(i)));
2984
2985                 txdctl = 0; /* clear txdctl */
2986                 txdctl |= 0x1f; /* PTHRESH */
2987                 txdctl |= 1 << 8; /* HTHRESH */
2988                 txdctl |= 1 << 16;/* WTHRESH */
2989                 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
2990                 txdctl |= E1000_TXDCTL_GRAN;
2991                 txdctl |= 1 << 25; /* LWTHRESH */
2992
2993                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
2994         }
2995
2996         /* Set the default values for the Tx Inter Packet Gap timer */
2997         switch (adapter->hw.mac.type) {
2998         case e1000_80003es2lan:
2999                 tipg = DEFAULT_82543_TIPG_IPGR1;
3000                 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
3001                     E1000_TIPG_IPGR2_SHIFT;
3002                 break;
3003         case e1000_82542:
3004                 tipg = DEFAULT_82542_TIPG_IPGT;
3005                 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3006                 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3007                 break;
3008         default:
3009                 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
3010                     (adapter->hw.phy.media_type ==
3011                     e1000_media_type_internal_serdes))
3012                         tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
3013                 else
3014                         tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
3015                 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3016                 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3017         }
3018
3019         E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
3020         E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value);
3021
3022         if(adapter->hw.mac.type >= e1000_82540)
3023                 E1000_WRITE_REG(&adapter->hw, E1000_TADV,
3024                     adapter->tx_abs_int_delay.value);
3025
3026         if ((adapter->hw.mac.type == e1000_82571) ||
3027             (adapter->hw.mac.type == e1000_82572)) {
3028                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3029                 tarc |= TARC_SPEED_MODE_BIT;
3030                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3031         } else if (adapter->hw.mac.type == e1000_80003es2lan) {
3032                 /* errata: program both queues to unweighted RR */
3033                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3034                 tarc |= 1;
3035                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3036                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
3037                 tarc |= 1;
3038                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
3039         } else if (adapter->hw.mac.type == e1000_82574) {
3040                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3041                 tarc |= TARC_ERRATA_BIT;
3042                 if ( adapter->tx_num_queues > 1) {
3043                         tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
3044                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3045                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
3046                 } else
3047                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3048         }
3049
3050         if (adapter->tx_int_delay.value > 0)
3051                 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3052
3053         /* Program the Transmit Control Register */
3054         tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
3055         tctl &= ~E1000_TCTL_CT;
3056         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
3057                    (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
3058
3059         if (adapter->hw.mac.type >= e1000_82571)
3060                 tctl |= E1000_TCTL_MULR;
3061
3062         /* This write will effectively turn on the transmit unit. */
3063         E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
3064
3065         /* SPT and KBL errata workarounds */
3066         if (hw->mac.type == e1000_pch_spt) {
3067                 u32 reg;
3068                 reg = E1000_READ_REG(hw, E1000_IOSFPC);
3069                 reg |= E1000_RCTL_RDMTS_HEX;
3070                 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
3071                 /* i218-i219 Specification Update 1.5.4.5 */
3072                 reg = E1000_READ_REG(hw, E1000_TARC(0));
3073                 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3074                 reg |= E1000_TARC0_CB_MULTIQ_2_REQ;
3075                 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3076         }
3077 }
3078
3079 /*********************************************************************
3080  *
3081  *  Enable receive unit.
3082  *
3083  **********************************************************************/
3084
3085 static void
3086 em_initialize_receive_unit(if_ctx_t ctx)
3087 {
3088         struct adapter *adapter = iflib_get_softc(ctx);
3089         if_softc_ctx_t scctx = adapter->shared;
3090         struct ifnet *ifp = iflib_get_ifp(ctx);
3091         struct e1000_hw *hw = &adapter->hw;
3092         struct em_rx_queue *que;
3093         int i;
3094         u32 rctl, rxcsum, rfctl;
3095
3096         INIT_DEBUGOUT("em_initialize_receive_units: begin");
3097
3098         /*
3099          * Make sure receives are disabled while setting
3100          * up the descriptor ring
3101          */
3102         rctl = E1000_READ_REG(hw, E1000_RCTL);
3103         /* Do not disable if ever enabled on this hardware */
3104         if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
3105                 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3106
3107         /* Setup the Receive Control Register */
3108         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3109         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3110             E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3111             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3112
3113         /* Do not store bad packets */
3114         rctl &= ~E1000_RCTL_SBP;
3115
3116         /* Enable Long Packet receive */
3117         if (if_getmtu(ifp) > ETHERMTU)
3118                 rctl |= E1000_RCTL_LPE;
3119         else
3120                 rctl &= ~E1000_RCTL_LPE;
3121
3122         /* Strip the CRC */
3123         if (!em_disable_crc_stripping)
3124                 rctl |= E1000_RCTL_SECRC;
3125
3126         if (adapter->hw.mac.type >= e1000_82540) {
3127                 E1000_WRITE_REG(&adapter->hw, E1000_RADV,
3128                             adapter->rx_abs_int_delay.value);
3129
3130                 /*
3131                  * Set the interrupt throttling rate. Value is calculated
3132                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
3133                  */
3134                 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
3135         }
3136         E1000_WRITE_REG(&adapter->hw, E1000_RDTR,
3137             adapter->rx_int_delay.value);
3138
3139         /* Use extended rx descriptor formats */
3140         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3141         rfctl |= E1000_RFCTL_EXTEN;
3142         /*
3143          * When using MSI-X interrupts we need to throttle
3144          * using the EITR register (82574 only)
3145          */
3146         if (hw->mac.type == e1000_82574) {
3147                 for (int i = 0; i < 4; i++)
3148                         E1000_WRITE_REG(hw, E1000_EITR_82574(i),
3149                             DEFAULT_ITR);
3150                 /* Disable accelerated acknowledge */
3151                 rfctl |= E1000_RFCTL_ACK_DIS;
3152         }
3153         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3154
3155         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
3156         if (if_getcapenable(ifp) & IFCAP_RXCSUM &&
3157             adapter->hw.mac.type >= e1000_82543) {
3158                 if (adapter->tx_num_queues > 1) {
3159                         if (adapter->hw.mac.type >= igb_mac_min) {
3160                                 rxcsum |= E1000_RXCSUM_PCSD;
3161                                 if (hw->mac.type != e1000_82575)
3162                                         rxcsum |= E1000_RXCSUM_CRCOFL;
3163                         } else
3164                                 rxcsum |= E1000_RXCSUM_TUOFL |
3165                                         E1000_RXCSUM_IPOFL |
3166                                         E1000_RXCSUM_PCSD;
3167                 } else {
3168                         if (adapter->hw.mac.type >= igb_mac_min)
3169                                 rxcsum |= E1000_RXCSUM_IPPCSE;
3170                         else
3171                                 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
3172                         if (adapter->hw.mac.type > e1000_82575)
3173                                 rxcsum |= E1000_RXCSUM_CRCOFL;
3174                 }
3175         } else
3176                 rxcsum &= ~E1000_RXCSUM_TUOFL;
3177
3178         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
3179
3180         if (adapter->rx_num_queues > 1) {
3181                 if (adapter->hw.mac.type >= igb_mac_min)
3182                         igb_initialize_rss_mapping(adapter);
3183                 else
3184                         em_initialize_rss_mapping(adapter);
3185         }
3186
3187         /*
3188          * XXX TEMPORARY WORKAROUND: on some systems with 82573
3189          * long latencies are observed, like Lenovo X60. This
3190          * change eliminates the problem, but since having positive
3191          * values in RDTR is a known source of problems on other
3192          * platforms another solution is being sought.
3193          */
3194         if (hw->mac.type == e1000_82573)
3195                 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
3196
3197         for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3198                 struct rx_ring *rxr = &que->rxr;
3199                 /* Setup the Base and Length of the Rx Descriptor Ring */
3200                 u64 bus_addr = rxr->rx_paddr;
3201 #if 0
3202                 u32 rdt = adapter->rx_num_queues -1;  /* default */
3203 #endif
3204
3205                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3206                     scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
3207                 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
3208                 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
3209                 /* Setup the Head and Tail Descriptor Pointers */
3210                 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
3211                 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
3212         }
3213
3214         /*
3215          * Set PTHRESH for improved jumbo performance
3216          * According to 10.2.5.11 of Intel 82574 Datasheet,
3217          * RXDCTL(1) is written whenever RXDCTL(0) is written.
3218          * Only write to RXDCTL(1) if there is a need for different
3219          * settings.
3220          */
3221
3222         if (((adapter->hw.mac.type == e1000_ich9lan) ||
3223             (adapter->hw.mac.type == e1000_pch2lan) ||
3224             (adapter->hw.mac.type == e1000_ich10lan)) &&
3225             (if_getmtu(ifp) > ETHERMTU)) {
3226                 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
3227                 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
3228         } else if (adapter->hw.mac.type == e1000_82574) {
3229                 for (int i = 0; i < adapter->rx_num_queues; i++) {
3230                         u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3231                         rxdctl |= 0x20; /* PTHRESH */
3232                         rxdctl |= 4 << 8; /* HTHRESH */
3233                         rxdctl |= 4 << 16;/* WTHRESH */
3234                         rxdctl |= 1 << 24; /* Switch to granularity */
3235                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3236                 }
3237         } else if (adapter->hw.mac.type >= igb_mac_min) {
3238                 u32 psize, srrctl = 0;
3239
3240                 if (if_getmtu(ifp) > ETHERMTU) {
3241                         /* Set maximum packet len */
3242                         if (adapter->rx_mbuf_sz <= 4096) {
3243                                 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3244                                 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3245                         } else if (adapter->rx_mbuf_sz > 4096) {
3246                                 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3247                                 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3248                         }
3249                         psize = scctx->isc_max_frame_size;
3250                         /* are we on a vlan? */
3251                         if (ifp->if_vlantrunk != NULL)
3252                                 psize += VLAN_TAG_SIZE;
3253                         E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
3254                 } else {
3255                         srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3256                         rctl |= E1000_RCTL_SZ_2048;
3257                 }
3258
3259                 /*
3260                  * If TX flow control is disabled and there's >1 queue defined,
3261                  * enable DROP.
3262                  *
3263                  * This drops frames rather than hanging the RX MAC for all queues.
3264                  */
3265                 if ((adapter->rx_num_queues > 1) &&
3266                     (adapter->fc == e1000_fc_none ||
3267                      adapter->fc == e1000_fc_rx_pause)) {
3268                         srrctl |= E1000_SRRCTL_DROP_EN;
3269                 }
3270                         /* Setup the Base and Length of the Rx Descriptor Rings */
3271                 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3272                         struct rx_ring *rxr = &que->rxr;
3273                         u64 bus_addr = rxr->rx_paddr;
3274                         u32 rxdctl;
3275
3276 #ifdef notyet
3277                         /* Configure for header split? -- ignore for now */
3278                         rxr->hdr_split = igb_header_split;
3279 #else
3280                         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3281 #endif
3282
3283                         E1000_WRITE_REG(hw, E1000_RDLEN(i),
3284                                         scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3285                         E1000_WRITE_REG(hw, E1000_RDBAH(i),
3286                                         (uint32_t)(bus_addr >> 32));
3287                         E1000_WRITE_REG(hw, E1000_RDBAL(i),
3288                                         (uint32_t)bus_addr);
3289                         E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3290                         /* Enable this Queue */
3291                         rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3292                         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3293                         rxdctl &= 0xFFF00000;
3294                         rxdctl |= IGB_RX_PTHRESH;
3295                         rxdctl |= IGB_RX_HTHRESH << 8;
3296                         rxdctl |= IGB_RX_WTHRESH << 16;
3297                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3298                 }
3299         } else if (adapter->hw.mac.type >= e1000_pch2lan) {
3300                 if (if_getmtu(ifp) > ETHERMTU)
3301                         e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
3302                 else
3303                         e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
3304         }
3305
3306         /* Make sure VLAN Filters are off */
3307         rctl &= ~E1000_RCTL_VFE;
3308
3309         if (adapter->hw.mac.type < igb_mac_min) {
3310                 if (adapter->rx_mbuf_sz == MCLBYTES)
3311                         rctl |= E1000_RCTL_SZ_2048;
3312                 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE)
3313                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3314                 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE)
3315                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3316
3317                 /* ensure we clear use DTYPE of 00 here */
3318                 rctl &= ~0x00000C00;
3319         }
3320
3321         /* Write out the settings */
3322         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3323
3324         return;
3325 }
3326
3327 static void
3328 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3329 {
3330         struct adapter *adapter = iflib_get_softc(ctx);
3331         u32 index, bit;
3332
3333         index = (vtag >> 5) & 0x7F;
3334         bit = vtag & 0x1F;
3335         adapter->shadow_vfta[index] |= (1 << bit);
3336         ++adapter->num_vlans;
3337 }
3338
3339 static void
3340 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3341 {
3342         struct adapter *adapter = iflib_get_softc(ctx);
3343         u32 index, bit;
3344
3345         index = (vtag >> 5) & 0x7F;
3346         bit = vtag & 0x1F;
3347         adapter->shadow_vfta[index] &= ~(1 << bit);
3348         --adapter->num_vlans;
3349 }
3350
3351 static void
3352 em_setup_vlan_hw_support(struct adapter *adapter)
3353 {
3354         struct e1000_hw *hw = &adapter->hw;
3355         u32 reg;
3356
3357         /*
3358          * We get here thru init_locked, meaning
3359          * a soft reset, this has already cleared
3360          * the VFTA and other state, so if there
3361          * have been no vlan's registered do nothing.
3362          */
3363         if (adapter->num_vlans == 0)
3364                 return;
3365
3366         /*
3367          * A soft reset zero's out the VFTA, so
3368          * we need to repopulate it now.
3369          */
3370         for (int i = 0; i < EM_VFTA_SIZE; i++)
3371                 if (adapter->shadow_vfta[i] != 0)
3372                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
3373                             i, adapter->shadow_vfta[i]);
3374
3375         reg = E1000_READ_REG(hw, E1000_CTRL);
3376         reg |= E1000_CTRL_VME;
3377         E1000_WRITE_REG(hw, E1000_CTRL, reg);
3378
3379         /* Enable the Filter Table */
3380         reg = E1000_READ_REG(hw, E1000_RCTL);
3381         reg &= ~E1000_RCTL_CFIEN;
3382         reg |= E1000_RCTL_VFE;
3383         E1000_WRITE_REG(hw, E1000_RCTL, reg);
3384 }
3385
3386 static void
3387 em_if_enable_intr(if_ctx_t ctx)
3388 {
3389         struct adapter *adapter = iflib_get_softc(ctx);
3390         struct e1000_hw *hw = &adapter->hw;
3391         u32 ims_mask = IMS_ENABLE_MASK;
3392
3393         if (hw->mac.type == e1000_82574) {
3394                 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK);
3395                 ims_mask |= adapter->ims;
3396         } else if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min)  {
3397                 u32 mask = (adapter->que_mask | adapter->link_mask);
3398
3399                 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask);
3400                 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask);
3401                 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask);
3402                 ims_mask = E1000_IMS_LSC;
3403         }
3404
3405         E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3406 }
3407
3408 static void
3409 em_if_disable_intr(if_ctx_t ctx)
3410 {
3411         struct adapter *adapter = iflib_get_softc(ctx);
3412         struct e1000_hw *hw = &adapter->hw;
3413
3414         if (adapter->intr_type == IFLIB_INTR_MSIX) {
3415                 if (hw->mac.type >= igb_mac_min)
3416                         E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0);
3417                 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0);
3418         }
3419         E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
3420 }
3421
3422 /*
3423  * Bit of a misnomer, what this really means is
3424  * to enable OS management of the system... aka
3425  * to disable special hardware management features
3426  */
3427 static void
3428 em_init_manageability(struct adapter *adapter)
3429 {
3430         /* A shared code workaround */
3431 #define E1000_82542_MANC2H E1000_MANC2H
3432         if (adapter->has_manage) {
3433                 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3434                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3435
3436                 /* disable hardware interception of ARP */
3437                 manc &= ~(E1000_MANC_ARP_EN);
3438
3439                 /* enable receiving management packets to the host */
3440                 manc |= E1000_MANC_EN_MNG2HOST;
3441 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3442 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3443                 manc2h |= E1000_MNG2HOST_PORT_623;
3444                 manc2h |= E1000_MNG2HOST_PORT_664;
3445                 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3446                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3447         }
3448 }
3449
3450 /*
3451  * Give control back to hardware management
3452  * controller if there is one.
3453  */
3454 static void
3455 em_release_manageability(struct adapter *adapter)
3456 {
3457         if (adapter->has_manage) {
3458                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3459
3460                 /* re-enable hardware interception of ARP */
3461                 manc |= E1000_MANC_ARP_EN;
3462                 manc &= ~E1000_MANC_EN_MNG2HOST;
3463
3464                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3465         }
3466 }
3467
3468 /*
3469  * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3470  * For ASF and Pass Through versions of f/w this means
3471  * that the driver is loaded. For AMT version type f/w
3472  * this means that the network i/f is open.
3473  */
3474 static void
3475 em_get_hw_control(struct adapter *adapter)
3476 {
3477         u32 ctrl_ext, swsm;
3478
3479         if (adapter->vf_ifp)
3480                 return;
3481
3482         if (adapter->hw.mac.type == e1000_82573) {
3483                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3484                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3485                     swsm | E1000_SWSM_DRV_LOAD);
3486                 return;
3487         }
3488         /* else */
3489         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3490         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3491             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3492 }
3493
3494 /*
3495  * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3496  * For ASF and Pass Through versions of f/w this means that
3497  * the driver is no longer loaded. For AMT versions of the
3498  * f/w this means that the network i/f is closed.
3499  */
3500 static void
3501 em_release_hw_control(struct adapter *adapter)
3502 {
3503         u32 ctrl_ext, swsm;
3504
3505         if (!adapter->has_manage)
3506                 return;
3507
3508         if (adapter->hw.mac.type == e1000_82573) {
3509                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3510                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3511                     swsm & ~E1000_SWSM_DRV_LOAD);
3512                 return;
3513         }
3514         /* else */
3515         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3516         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3517             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3518         return;
3519 }
3520
3521 static int
3522 em_is_valid_ether_addr(u8 *addr)
3523 {
3524         char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3525
3526         if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3527                 return (FALSE);
3528         }
3529
3530         return (TRUE);
3531 }
3532
3533 /*
3534 ** Parse the interface capabilities with regard
3535 ** to both system management and wake-on-lan for
3536 ** later use.
3537 */
3538 static void
3539 em_get_wakeup(if_ctx_t ctx)
3540 {
3541         struct adapter *adapter = iflib_get_softc(ctx);
3542         device_t dev = iflib_get_dev(ctx);
3543         u16 eeprom_data = 0, device_id, apme_mask;
3544
3545         adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
3546         apme_mask = EM_EEPROM_APME;
3547
3548         switch (adapter->hw.mac.type) {
3549         case e1000_82542:
3550         case e1000_82543:
3551                 break;
3552         case e1000_82544:
3553                 e1000_read_nvm(&adapter->hw,
3554                     NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3555                 apme_mask = EM_82544_APME;
3556                 break;
3557         case e1000_82546:
3558         case e1000_82546_rev_3:
3559                 if (adapter->hw.bus.func == 1) {
3560                         e1000_read_nvm(&adapter->hw,
3561                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3562                         break;
3563                 } else
3564                         e1000_read_nvm(&adapter->hw,
3565                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3566                 break;
3567         case e1000_82573:
3568         case e1000_82583:
3569                 adapter->has_amt = TRUE;
3570                 /* FALLTHROUGH */
3571         case e1000_82571:
3572         case e1000_82572:
3573         case e1000_80003es2lan:
3574                 if (adapter->hw.bus.func == 1) {
3575                         e1000_read_nvm(&adapter->hw,
3576                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3577                         break;
3578                 } else
3579                         e1000_read_nvm(&adapter->hw,
3580                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3581                 break;
3582         case e1000_ich8lan:
3583         case e1000_ich9lan:
3584         case e1000_ich10lan:
3585         case e1000_pchlan:
3586         case e1000_pch2lan:
3587         case e1000_pch_lpt:
3588         case e1000_pch_spt:
3589         case e1000_82575:       /* listing all igb devices */
3590         case e1000_82576:
3591         case e1000_82580:
3592         case e1000_i350:
3593         case e1000_i354:
3594         case e1000_i210:
3595         case e1000_i211:
3596         case e1000_vfadapt:
3597         case e1000_vfadapt_i350:
3598                 apme_mask = E1000_WUC_APME;
3599                 adapter->has_amt = TRUE;
3600                 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
3601                 break;
3602         default:
3603                 e1000_read_nvm(&adapter->hw,
3604                     NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3605                 break;
3606         }
3607         if (eeprom_data & apme_mask)
3608                 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
3609         /*
3610          * We have the eeprom settings, now apply the special cases
3611          * where the eeprom may be wrong or the board won't support
3612          * wake on lan on a particular port
3613          */
3614         device_id = pci_get_device(dev);
3615         switch (device_id) {
3616         case E1000_DEV_ID_82546GB_PCIE:
3617                 adapter->wol = 0;
3618                 break;
3619         case E1000_DEV_ID_82546EB_FIBER:
3620         case E1000_DEV_ID_82546GB_FIBER:
3621                 /* Wake events only supported on port A for dual fiber
3622                  * regardless of eeprom setting */
3623                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3624                     E1000_STATUS_FUNC_1)
3625                         adapter->wol = 0;
3626                 break;
3627         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
3628                 /* if quad port adapter, disable WoL on all but port A */
3629                 if (global_quad_port_a != 0)
3630                         adapter->wol = 0;
3631                 /* Reset for multiple quad port adapters */
3632                 if (++global_quad_port_a == 4)
3633                         global_quad_port_a = 0;
3634                 break;
3635         case E1000_DEV_ID_82571EB_FIBER:
3636                 /* Wake events only supported on port A for dual fiber
3637                  * regardless of eeprom setting */
3638                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3639                     E1000_STATUS_FUNC_1)
3640                         adapter->wol = 0;
3641                 break;
3642         case E1000_DEV_ID_82571EB_QUAD_COPPER:
3643         case E1000_DEV_ID_82571EB_QUAD_FIBER:
3644         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
3645                 /* if quad port adapter, disable WoL on all but port A */
3646                 if (global_quad_port_a != 0)
3647                         adapter->wol = 0;
3648                 /* Reset for multiple quad port adapters */
3649                 if (++global_quad_port_a == 4)
3650                         global_quad_port_a = 0;
3651                 break;
3652         }
3653         return;
3654 }
3655
3656
3657 /*
3658  * Enable PCI Wake On Lan capability
3659  */
3660 static void
3661 em_enable_wakeup(if_ctx_t ctx)
3662 {
3663         struct adapter *adapter = iflib_get_softc(ctx);
3664         device_t dev = iflib_get_dev(ctx);
3665         if_t ifp = iflib_get_ifp(ctx);
3666         int error = 0;
3667         u32 pmc, ctrl, ctrl_ext, rctl;
3668         u16 status;
3669
3670         if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
3671                 return;
3672
3673         /*
3674          * Determine type of Wakeup: note that wol
3675          * is set with all bits on by default.
3676          */
3677         if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
3678                 adapter->wol &= ~E1000_WUFC_MAG;
3679
3680         if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
3681                 adapter->wol &= ~E1000_WUFC_EX;
3682
3683         if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
3684                 adapter->wol &= ~E1000_WUFC_MC;
3685         else {
3686                 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3687                 rctl |= E1000_RCTL_MPE;
3688                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3689         }
3690
3691         if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC)))
3692                 goto pme;
3693
3694         /* Advertise the wakeup capability */
3695         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
3696         ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
3697         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
3698
3699         /* Keep the laser running on Fiber adapters */
3700         if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3701             adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
3702                 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3703                 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
3704                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext);
3705         }
3706
3707         if ((adapter->hw.mac.type == e1000_ich8lan) ||
3708             (adapter->hw.mac.type == e1000_pchlan) ||
3709             (adapter->hw.mac.type == e1000_ich9lan) ||
3710             (adapter->hw.mac.type == e1000_ich10lan))
3711                 e1000_suspend_workarounds_ich8lan(&adapter->hw);
3712
3713         if ( adapter->hw.mac.type >= e1000_pchlan) {
3714                 error = em_enable_phy_wakeup(adapter);
3715                 if (error)
3716                         goto pme;
3717         } else {
3718                 /* Enable wakeup by the MAC */
3719                 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
3720                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
3721         }
3722
3723         if (adapter->hw.phy.type == e1000_phy_igp_3)
3724                 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
3725
3726 pme:
3727         status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
3728         status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3729         if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
3730                 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3731         pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
3732
3733         return;
3734 }
3735
3736 /*
3737  * WOL in the newer chipset interfaces (pchlan)
3738  * require thing to be copied into the phy
3739  */
3740 static int
3741 em_enable_phy_wakeup(struct adapter *adapter)
3742 {
3743         struct e1000_hw *hw = &adapter->hw;
3744         u32 mreg, ret = 0;
3745         u16 preg;
3746
3747         /* copy MAC RARs to PHY RARs */
3748         e1000_copy_rx_addrs_to_phy_ich8lan(hw);
3749
3750         /* copy MAC MTA to PHY MTA */
3751         for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
3752                 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
3753                 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
3754                 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
3755                     (u16)((mreg >> 16) & 0xFFFF));
3756         }
3757
3758         /* configure PHY Rx Control register */
3759         e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg);
3760         mreg = E1000_READ_REG(hw, E1000_RCTL);
3761         if (mreg & E1000_RCTL_UPE)
3762                 preg |= BM_RCTL_UPE;
3763         if (mreg & E1000_RCTL_MPE)
3764                 preg |= BM_RCTL_MPE;
3765         preg &= ~(BM_RCTL_MO_MASK);
3766         if (mreg & E1000_RCTL_MO_3)
3767                 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
3768                                 << BM_RCTL_MO_SHIFT);
3769         if (mreg & E1000_RCTL_BAM)
3770                 preg |= BM_RCTL_BAM;
3771         if (mreg & E1000_RCTL_PMCF)
3772                 preg |= BM_RCTL_PMCF;
3773         mreg = E1000_READ_REG(hw, E1000_CTRL);
3774         if (mreg & E1000_CTRL_RFCE)
3775                 preg |= BM_RCTL_RFCE;
3776         e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg);
3777
3778         /* enable PHY wakeup in MAC register */
3779         E1000_WRITE_REG(hw, E1000_WUC,
3780             E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
3781         E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol);
3782
3783         /* configure and enable PHY wakeup in PHY registers */
3784         e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol);
3785         e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
3786
3787         /* activate PHY wakeup */
3788         ret = hw->phy.ops.acquire(hw);
3789         if (ret) {
3790                 printf("Could not acquire PHY\n");
3791                 return ret;
3792         }
3793         e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3794                                  (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3795         ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
3796         if (ret) {
3797                 printf("Could not read PHY page 769\n");
3798                 goto out;
3799         }
3800         preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
3801         ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
3802         if (ret)
3803                 printf("Could not set PHY Host Wakeup bit\n");
3804 out:
3805         hw->phy.ops.release(hw);
3806
3807         return ret;
3808 }
3809
3810 static void
3811 em_if_led_func(if_ctx_t ctx, int onoff)
3812 {
3813         struct adapter *adapter = iflib_get_softc(ctx);
3814
3815         if (onoff) {
3816                 e1000_setup_led(&adapter->hw);
3817                 e1000_led_on(&adapter->hw);
3818         } else {
3819                 e1000_led_off(&adapter->hw);
3820                 e1000_cleanup_led(&adapter->hw);
3821         }
3822 }
3823
3824 /*
3825  * Disable the L0S and L1 LINK states
3826  */
3827 static void
3828 em_disable_aspm(struct adapter *adapter)
3829 {
3830         int base, reg;
3831         u16 link_cap,link_ctrl;
3832         device_t dev = adapter->dev;
3833
3834         switch (adapter->hw.mac.type) {
3835         case e1000_82573:
3836         case e1000_82574:
3837         case e1000_82583:
3838                 break;
3839         default:
3840                 return;
3841         }
3842         if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
3843                 return;
3844         reg = base + PCIER_LINK_CAP;
3845         link_cap = pci_read_config(dev, reg, 2);
3846         if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
3847                 return;
3848         reg = base + PCIER_LINK_CTL;
3849         link_ctrl = pci_read_config(dev, reg, 2);
3850         link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
3851         pci_write_config(dev, reg, link_ctrl, 2);
3852         return;
3853 }
3854
3855 /**********************************************************************
3856  *
3857  *  Update the board statistics counters.
3858  *
3859  **********************************************************************/
3860 static void
3861 em_update_stats_counters(struct adapter *adapter)
3862 {
3863
3864         if(adapter->hw.phy.media_type == e1000_media_type_copper ||
3865            (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3866                 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
3867                 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
3868         }
3869         adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
3870         adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
3871         adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
3872         adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
3873
3874         adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
3875         adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
3876         adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
3877         adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
3878         adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
3879         adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
3880         adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
3881         adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
3882         /*
3883          ** For watchdog management we need to know if we have been
3884          ** paused during the last interval, so capture that here.
3885         */
3886         adapter->shared->isc_pause_frames = adapter->stats.xoffrxc;
3887         adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
3888         adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
3889         adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
3890         adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
3891         adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
3892         adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
3893         adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
3894         adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
3895         adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
3896         adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
3897         adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
3898         adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
3899
3900         /* For the 64-bit byte counters the low dword must be read first. */
3901         /* Both registers clear on the read of the high dword */
3902
3903         adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) +
3904             ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32);
3905         adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) +
3906             ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32);
3907
3908         adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
3909         adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
3910         adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
3911         adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
3912         adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
3913
3914         adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
3915         adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
3916
3917         adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
3918         adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
3919         adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
3920         adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
3921         adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
3922         adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
3923         adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
3924         adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
3925         adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
3926         adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
3927
3928         /* Interrupt Counts */
3929
3930         adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC);
3931         adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC);
3932         adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC);
3933         adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC);
3934         adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC);
3935         adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC);
3936         adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC);
3937         adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC);
3938         adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC);
3939
3940         if (adapter->hw.mac.type >= e1000_82543) {
3941                 adapter->stats.algnerrc +=
3942                 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
3943                 adapter->stats.rxerrc +=
3944                 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
3945                 adapter->stats.tncrs +=
3946                 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
3947                 adapter->stats.cexterr +=
3948                 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
3949                 adapter->stats.tsctc +=
3950                 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
3951                 adapter->stats.tsctfc +=
3952                 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
3953         }
3954 }
3955
3956 static uint64_t
3957 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
3958 {
3959         struct adapter *adapter = iflib_get_softc(ctx);
3960         struct ifnet *ifp = iflib_get_ifp(ctx);
3961
3962         switch (cnt) {
3963         case IFCOUNTER_COLLISIONS:
3964                 return (adapter->stats.colc);
3965         case IFCOUNTER_IERRORS:
3966                 return (adapter->dropped_pkts + adapter->stats.rxerrc +
3967                     adapter->stats.crcerrs + adapter->stats.algnerrc +
3968                     adapter->stats.ruc + adapter->stats.roc +
3969                     adapter->stats.mpc + adapter->stats.cexterr);
3970         case IFCOUNTER_OERRORS:
3971                 return (adapter->stats.ecol + adapter->stats.latecol +
3972                     adapter->watchdog_events);
3973         default:
3974                 return (if_get_counter_default(ifp, cnt));
3975         }
3976 }
3977
3978 /* Export a single 32-bit register via a read-only sysctl. */
3979 static int
3980 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
3981 {
3982         struct adapter *adapter;
3983         u_int val;
3984
3985         adapter = oidp->oid_arg1;
3986         val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2);
3987         return (sysctl_handle_int(oidp, &val, 0, req));
3988 }
3989
3990 /*
3991  * Add sysctl variables, one per statistic, to the system.
3992  */
3993 static void
3994 em_add_hw_stats(struct adapter *adapter)
3995 {
3996         device_t dev = iflib_get_dev(adapter->ctx);
3997         struct em_tx_queue *tx_que = adapter->tx_queues;
3998         struct em_rx_queue *rx_que = adapter->rx_queues;
3999
4000         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
4001         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
4002         struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
4003         struct e1000_hw_stats *stats = &adapter->stats;
4004
4005         struct sysctl_oid *stat_node, *queue_node, *int_node;
4006         struct sysctl_oid_list *stat_list, *queue_list, *int_list;
4007
4008 #define QUEUE_NAME_LEN 32
4009         char namebuf[QUEUE_NAME_LEN];
4010
4011         /* Driver Statistics */
4012         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
4013                         CTLFLAG_RD, &adapter->dropped_pkts,
4014                         "Driver dropped packets");
4015         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
4016                         CTLFLAG_RD, &adapter->link_irq,
4017                         "Link MSI-X IRQ Handled");
4018         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "mbuf_defrag_fail",
4019                          CTLFLAG_RD, &adapter->mbuf_defrag_failed,
4020                          "Defragmenting mbuf chain failed");
4021         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "tx_dma_fail",
4022                         CTLFLAG_RD, &adapter->no_tx_dma_setup,
4023                         "Driver tx dma failure in xmit");
4024         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
4025                         CTLFLAG_RD, &adapter->rx_overruns,
4026                         "RX overruns");
4027         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
4028                         CTLFLAG_RD, &adapter->watchdog_events,
4029                         "Watchdog timeouts");
4030         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
4031                         CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL,
4032                         em_sysctl_reg_handler, "IU",
4033                         "Device Control Register");
4034         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
4035                         CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL,
4036                         em_sysctl_reg_handler, "IU",
4037                         "Receiver Control Register");
4038         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
4039                         CTLFLAG_RD, &adapter->hw.fc.high_water, 0,
4040                         "Flow Control High Watermark");
4041         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
4042                         CTLFLAG_RD, &adapter->hw.fc.low_water, 0,
4043                         "Flow Control Low Watermark");
4044
4045         for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
4046                 struct tx_ring *txr = &tx_que->txr;
4047                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
4048                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4049                                             CTLFLAG_RD, NULL, "TX Queue Name");
4050                 queue_list = SYSCTL_CHILDREN(queue_node);
4051
4052                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
4053                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4054                                 E1000_TDH(txr->me),
4055                                 em_sysctl_reg_handler, "IU",
4056                                 "Transmit Descriptor Head");
4057                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
4058                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4059                                 E1000_TDT(txr->me),
4060                                 em_sysctl_reg_handler, "IU",
4061                                 "Transmit Descriptor Tail");
4062                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
4063                                 CTLFLAG_RD, &txr->tx_irq,
4064                                 "Queue MSI-X Transmit Interrupts");
4065         }
4066
4067         for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) {
4068                 struct rx_ring *rxr = &rx_que->rxr;
4069                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
4070                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4071                                             CTLFLAG_RD, NULL, "RX Queue Name");
4072                 queue_list = SYSCTL_CHILDREN(queue_node);
4073
4074                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
4075                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4076                                 E1000_RDH(rxr->me),
4077                                 em_sysctl_reg_handler, "IU",
4078                                 "Receive Descriptor Head");
4079                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
4080                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4081                                 E1000_RDT(rxr->me),
4082                                 em_sysctl_reg_handler, "IU",
4083                                 "Receive Descriptor Tail");
4084                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
4085                                 CTLFLAG_RD, &rxr->rx_irq,
4086                                 "Queue MSI-X Receive Interrupts");
4087         }
4088
4089         /* MAC stats get their own sub node */
4090
4091         stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
4092                                     CTLFLAG_RD, NULL, "Statistics");
4093         stat_list = SYSCTL_CHILDREN(stat_node);
4094
4095         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
4096                         CTLFLAG_RD, &stats->ecol,
4097                         "Excessive collisions");
4098         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
4099                         CTLFLAG_RD, &stats->scc,
4100                         "Single collisions");
4101         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
4102                         CTLFLAG_RD, &stats->mcc,
4103                         "Multiple collisions");
4104         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
4105                         CTLFLAG_RD, &stats->latecol,
4106                         "Late collisions");
4107         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
4108                         CTLFLAG_RD, &stats->colc,
4109                         "Collision Count");
4110         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
4111                         CTLFLAG_RD, &adapter->stats.symerrs,
4112                         "Symbol Errors");
4113         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
4114                         CTLFLAG_RD, &adapter->stats.sec,
4115                         "Sequence Errors");
4116         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
4117                         CTLFLAG_RD, &adapter->stats.dc,
4118                         "Defer Count");
4119         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
4120                         CTLFLAG_RD, &adapter->stats.mpc,
4121                         "Missed Packets");
4122         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
4123                         CTLFLAG_RD, &adapter->stats.rnbc,
4124                         "Receive No Buffers");
4125         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
4126                         CTLFLAG_RD, &adapter->stats.ruc,
4127                         "Receive Undersize");
4128         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
4129                         CTLFLAG_RD, &adapter->stats.rfc,
4130                         "Fragmented Packets Received ");
4131         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
4132                         CTLFLAG_RD, &adapter->stats.roc,
4133                         "Oversized Packets Received");
4134         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
4135                         CTLFLAG_RD, &adapter->stats.rjc,
4136                         "Recevied Jabber");
4137         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
4138                         CTLFLAG_RD, &adapter->stats.rxerrc,
4139                         "Receive Errors");
4140         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
4141                         CTLFLAG_RD, &adapter->stats.crcerrs,
4142                         "CRC errors");
4143         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
4144                         CTLFLAG_RD, &adapter->stats.algnerrc,
4145                         "Alignment Errors");
4146         /* On 82575 these are collision counts */
4147         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
4148                         CTLFLAG_RD, &adapter->stats.cexterr,
4149                         "Collision/Carrier extension errors");
4150         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
4151                         CTLFLAG_RD, &adapter->stats.xonrxc,
4152                         "XON Received");
4153         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
4154                         CTLFLAG_RD, &adapter->stats.xontxc,
4155                         "XON Transmitted");
4156         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
4157                         CTLFLAG_RD, &adapter->stats.xoffrxc,
4158                         "XOFF Received");
4159         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
4160                         CTLFLAG_RD, &adapter->stats.xofftxc,
4161                         "XOFF Transmitted");
4162
4163         /* Packet Reception Stats */
4164         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
4165                         CTLFLAG_RD, &adapter->stats.tpr,
4166                         "Total Packets Received ");
4167         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
4168                         CTLFLAG_RD, &adapter->stats.gprc,
4169                         "Good Packets Received");
4170         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
4171                         CTLFLAG_RD, &adapter->stats.bprc,
4172                         "Broadcast Packets Received");
4173         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
4174                         CTLFLAG_RD, &adapter->stats.mprc,
4175                         "Multicast Packets Received");
4176         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
4177                         CTLFLAG_RD, &adapter->stats.prc64,
4178                         "64 byte frames received ");
4179         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
4180                         CTLFLAG_RD, &adapter->stats.prc127,
4181                         "65-127 byte frames received");
4182         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
4183                         CTLFLAG_RD, &adapter->stats.prc255,
4184                         "128-255 byte frames received");
4185         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
4186                         CTLFLAG_RD, &adapter->stats.prc511,
4187                         "256-511 byte frames received");
4188         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
4189                         CTLFLAG_RD, &adapter->stats.prc1023,
4190                         "512-1023 byte frames received");
4191         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
4192                         CTLFLAG_RD, &adapter->stats.prc1522,
4193                         "1023-1522 byte frames received");
4194         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
4195                         CTLFLAG_RD, &adapter->stats.gorc,
4196                         "Good Octets Received");
4197
4198         /* Packet Transmission Stats */
4199         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
4200                         CTLFLAG_RD, &adapter->stats.gotc,
4201                         "Good Octets Transmitted");
4202         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
4203                         CTLFLAG_RD, &adapter->stats.tpt,
4204                         "Total Packets Transmitted");
4205         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
4206                         CTLFLAG_RD, &adapter->stats.gptc,
4207                         "Good Packets Transmitted");
4208         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
4209                         CTLFLAG_RD, &adapter->stats.bptc,
4210                         "Broadcast Packets Transmitted");
4211         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
4212                         CTLFLAG_RD, &adapter->stats.mptc,
4213                         "Multicast Packets Transmitted");
4214         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
4215                         CTLFLAG_RD, &adapter->stats.ptc64,
4216                         "64 byte frames transmitted ");
4217         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
4218                         CTLFLAG_RD, &adapter->stats.ptc127,
4219                         "65-127 byte frames transmitted");
4220         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
4221                         CTLFLAG_RD, &adapter->stats.ptc255,
4222                         "128-255 byte frames transmitted");
4223         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
4224                         CTLFLAG_RD, &adapter->stats.ptc511,
4225                         "256-511 byte frames transmitted");
4226         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
4227                         CTLFLAG_RD, &adapter->stats.ptc1023,
4228                         "512-1023 byte frames transmitted");
4229         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
4230                         CTLFLAG_RD, &adapter->stats.ptc1522,
4231                         "1024-1522 byte frames transmitted");
4232         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
4233                         CTLFLAG_RD, &adapter->stats.tsctc,
4234                         "TSO Contexts Transmitted");
4235         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
4236                         CTLFLAG_RD, &adapter->stats.tsctfc,
4237                         "TSO Contexts Failed");
4238
4239
4240         /* Interrupt Stats */
4241
4242         int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
4243                                     CTLFLAG_RD, NULL, "Interrupt Statistics");
4244         int_list = SYSCTL_CHILDREN(int_node);
4245
4246         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
4247                         CTLFLAG_RD, &adapter->stats.iac,
4248                         "Interrupt Assertion Count");
4249
4250         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
4251                         CTLFLAG_RD, &adapter->stats.icrxptc,
4252                         "Interrupt Cause Rx Pkt Timer Expire Count");
4253
4254         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
4255                         CTLFLAG_RD, &adapter->stats.icrxatc,
4256                         "Interrupt Cause Rx Abs Timer Expire Count");
4257
4258         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
4259                         CTLFLAG_RD, &adapter->stats.ictxptc,
4260                         "Interrupt Cause Tx Pkt Timer Expire Count");
4261
4262         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
4263                         CTLFLAG_RD, &adapter->stats.ictxatc,
4264                         "Interrupt Cause Tx Abs Timer Expire Count");
4265
4266         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
4267                         CTLFLAG_RD, &adapter->stats.ictxqec,
4268                         "Interrupt Cause Tx Queue Empty Count");
4269
4270         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
4271                         CTLFLAG_RD, &adapter->stats.ictxqmtc,
4272                         "Interrupt Cause Tx Queue Min Thresh Count");
4273
4274         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
4275                         CTLFLAG_RD, &adapter->stats.icrxdmtc,
4276                         "Interrupt Cause Rx Desc Min Thresh Count");
4277
4278         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
4279                         CTLFLAG_RD, &adapter->stats.icrxoc,
4280                         "Interrupt Cause Receiver Overrun Count");
4281 }
4282
4283 /**********************************************************************
4284  *
4285  *  This routine provides a way to dump out the adapter eeprom,
4286  *  often a useful debug/service tool. This only dumps the first
4287  *  32 words, stuff that matters is in that extent.
4288  *
4289  **********************************************************************/
4290 static int
4291 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4292 {
4293         struct adapter *adapter = (struct adapter *)arg1;
4294         int error;
4295         int result;
4296
4297         result = -1;
4298         error = sysctl_handle_int(oidp, &result, 0, req);
4299
4300         if (error || !req->newptr)
4301                 return (error);
4302
4303         /*
4304          * This value will cause a hex dump of the
4305          * first 32 16-bit words of the EEPROM to
4306          * the screen.
4307          */
4308         if (result == 1)
4309                 em_print_nvm_info(adapter);
4310
4311         return (error);
4312 }
4313
4314 static void
4315 em_print_nvm_info(struct adapter *adapter)
4316 {
4317         u16 eeprom_data;
4318         int i, j, row = 0;
4319
4320         /* Its a bit crude, but it gets the job done */
4321         printf("\nInterface EEPROM Dump:\n");
4322         printf("Offset\n0x0000  ");
4323         for (i = 0, j = 0; i < 32; i++, j++) {
4324                 if (j == 8) { /* Make the offset block */
4325                         j = 0; ++row;
4326                         printf("\n0x00%x0  ",row);
4327                 }
4328                 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
4329                 printf("%04x ", eeprom_data);
4330         }
4331         printf("\n");
4332 }
4333
4334 static int
4335 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4336 {
4337         struct em_int_delay_info *info;
4338         struct adapter *adapter;
4339         u32 regval;
4340         int error, usecs, ticks;
4341
4342         info = (struct em_int_delay_info *) arg1;
4343         usecs = info->value;
4344         error = sysctl_handle_int(oidp, &usecs, 0, req);
4345         if (error != 0 || req->newptr == NULL)
4346                 return (error);
4347         if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4348                 return (EINVAL);
4349         info->value = usecs;
4350         ticks = EM_USECS_TO_TICKS(usecs);
4351         if (info->offset == E1000_ITR)  /* units are 256ns here */
4352                 ticks *= 4;
4353
4354         adapter = info->adapter;
4355
4356         regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
4357         regval = (regval & ~0xffff) | (ticks & 0xffff);
4358         /* Handle a few special cases. */
4359         switch (info->offset) {
4360         case E1000_RDTR:
4361                 break;
4362         case E1000_TIDV:
4363                 if (ticks == 0) {
4364                         adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
4365                         /* Don't write 0 into the TIDV register. */
4366                         regval++;
4367                 } else
4368                         adapter->txd_cmd |= E1000_TXD_CMD_IDE;
4369                 break;
4370         }
4371         E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
4372         return (0);
4373 }
4374
4375 static void
4376 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
4377         const char *description, struct em_int_delay_info *info,
4378         int offset, int value)
4379 {
4380         info->adapter = adapter;
4381         info->offset = offset;
4382         info->value = value;
4383         SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev),
4384             SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4385             OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
4386             info, 0, em_sysctl_int_delay, "I", description);
4387 }
4388
4389 /*
4390  * Set flow control using sysctl:
4391  * Flow control values:
4392  *      0 - off
4393  *      1 - rx pause
4394  *      2 - tx pause
4395  *      3 - full
4396  */
4397 static int
4398 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4399 {
4400         int error;
4401         static int input = 3; /* default is full */
4402         struct adapter  *adapter = (struct adapter *) arg1;
4403
4404         error = sysctl_handle_int(oidp, &input, 0, req);
4405
4406         if ((error) || (req->newptr == NULL))
4407                 return (error);
4408
4409         if (input == adapter->fc) /* no change? */
4410                 return (error);
4411
4412         switch (input) {
4413         case e1000_fc_rx_pause:
4414         case e1000_fc_tx_pause:
4415         case e1000_fc_full:
4416         case e1000_fc_none:
4417                 adapter->hw.fc.requested_mode = input;
4418                 adapter->fc = input;
4419                 break;
4420         default:
4421                 /* Do nothing */
4422                 return (error);
4423         }
4424
4425         adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
4426         e1000_force_mac_fc(&adapter->hw);
4427         return (error);
4428 }
4429
4430 /*
4431  * Manage Energy Efficient Ethernet:
4432  * Control values:
4433  *     0/1 - enabled/disabled
4434  */
4435 static int
4436 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4437 {
4438         struct adapter *adapter = (struct adapter *) arg1;
4439         int error, value;
4440
4441         value = adapter->hw.dev_spec.ich8lan.eee_disable;
4442         error = sysctl_handle_int(oidp, &value, 0, req);
4443         if (error || req->newptr == NULL)
4444                 return (error);
4445         adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4446         em_if_init(adapter->ctx);
4447
4448         return (0);
4449 }
4450
4451 static int
4452 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4453 {
4454         struct adapter *adapter;
4455         int error;
4456         int result;
4457
4458         result = -1;
4459         error = sysctl_handle_int(oidp, &result, 0, req);
4460
4461         if (error || !req->newptr)
4462                 return (error);
4463
4464         if (result == 1) {
4465                 adapter = (struct adapter *) arg1;
4466                 em_print_debug_info(adapter);
4467         }
4468
4469         return (error);
4470 }
4471
4472 static int
4473 em_get_rs(SYSCTL_HANDLER_ARGS)
4474 {
4475         struct adapter *adapter = (struct adapter *) arg1;
4476         int error;
4477         int result;
4478
4479         result = 0;
4480         error = sysctl_handle_int(oidp, &result, 0, req);
4481
4482         if (error || !req->newptr || result != 1)
4483                 return (error);
4484         em_dump_rs(adapter);
4485
4486         return (error);
4487 }
4488
4489 static void
4490 em_if_debug(if_ctx_t ctx)
4491 {
4492         em_dump_rs(iflib_get_softc(ctx));
4493 }
4494
4495 /*
4496  * This routine is meant to be fluid, add whatever is
4497  * needed for debugging a problem.  -jfv
4498  */
4499 static void
4500 em_print_debug_info(struct adapter *adapter)
4501 {
4502         device_t dev = iflib_get_dev(adapter->ctx);
4503         struct ifnet *ifp = iflib_get_ifp(adapter->ctx);
4504         struct tx_ring *txr = &adapter->tx_queues->txr;
4505         struct rx_ring *rxr = &adapter->rx_queues->rxr;
4506
4507         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
4508                 printf("Interface is RUNNING ");
4509         else
4510                 printf("Interface is NOT RUNNING\n");
4511
4512         if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
4513                 printf("and INACTIVE\n");
4514         else
4515                 printf("and ACTIVE\n");
4516
4517         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
4518                 device_printf(dev, "TX Queue %d ------\n", i);
4519                 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
4520                         E1000_READ_REG(&adapter->hw, E1000_TDH(i)),
4521                         E1000_READ_REG(&adapter->hw, E1000_TDT(i)));
4522
4523         }
4524         for (int j=0; j < adapter->rx_num_queues; j++, rxr++) {
4525                 device_printf(dev, "RX Queue %d ------\n", j);
4526                 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
4527                         E1000_READ_REG(&adapter->hw, E1000_RDH(j)),
4528                         E1000_READ_REG(&adapter->hw, E1000_RDT(j)));
4529         }
4530 }
4531
4532 /*
4533  * 82574 only:
4534  * Write a new value to the EEPROM increasing the number of MSI-X
4535  * vectors from 3 to 5, for proper multiqueue support.
4536  */
4537 static void
4538 em_enable_vectors_82574(if_ctx_t ctx)
4539 {
4540         struct adapter *adapter = iflib_get_softc(ctx);
4541         struct e1000_hw *hw = &adapter->hw;
4542         device_t dev = iflib_get_dev(ctx);
4543         u16 edata;
4544
4545         e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4546         printf("Current cap: %#06x\n", edata);
4547         if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
4548                 device_printf(dev, "Writing to eeprom: increasing "
4549                     "reported MSI-X vectors from 3 to 5...\n");
4550                 edata &= ~(EM_NVM_MSIX_N_MASK);
4551                 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
4552                 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4553                 e1000_update_nvm_checksum(hw);
4554                 device_printf(dev, "Writing to eeprom: done\n");
4555         }
4556 }