sys/dev/e1000/if_em.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /* $FreeBSD$ */
  30 #include "if_em.h"
  31 #include <sys/sbuf.h>
  32 #include <machine/_inttypes.h>
  33
  34 #define em_mac_min e1000_82547
  35 #define igb_mac_min e1000_82575
  36
  37 /*********************************************************************
  38  *  Driver version:
  39  *********************************************************************/
  40 char em_driver_version[] = "7.6.1-k";
  41
  42 /*********************************************************************
  43  *  PCI Device ID Table
  44  *
  45  *  Used by probe to select devices to load on
  46  *  Last field stores an index into e1000_strings
  47  *  Last entry must be all 0s
  48  *
  49  *  { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
  50  *********************************************************************/
  51
  52 static pci_vendor_info_t em_vendor_info_array[] =
  53 {
  54         /* Intel(R) PRO/1000 Network Connection - Legacy em*/
  55         PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"),
  56         PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"),
  57         PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"),
  58         PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"),
  59         PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"),
  60
  61         PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"),
  62         PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"),
  63         PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"),
  64         PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  65         PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"),
  66         PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"),
  67         PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  68
  69         PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"),
  70
  71         PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"),
  72         PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
  73
  74         PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
  75         PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
  76         PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
  77         PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"),
  78
  79         PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"),
  80         PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"),
  81         PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"),
  82         PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"),
  83         PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"),
  84
  85         PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  86         PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
  87         PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
  88         PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  89         PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"),
  90         PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"),
  91         PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"),
  92         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
  93         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"),
  94
  95         PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"),
  96         PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  97         PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"),
  98
  99         /* Intel(R) PRO/1000 Network Connection - em */
 100         PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
 101         PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
 102         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"),
 103         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"),
 104         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"),
 105         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 106         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"),
 107         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"),
 108         PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 109         PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"),
 110         PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
 111         PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
 112         PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"),
 113         PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"),
 114         PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"),
 115         PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"),
 116         PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"),
 117         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"),
 118         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"),
 119         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"),
 120         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"),
 121         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
 122         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 123         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"),
 124         PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"),
 125         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
 126         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"),
 127         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"),
 128         PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"),
 129         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
 130         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 131         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"),
 132         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"),
 133         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"),
 134         PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"),
 135         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
 136         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"),
 137         PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"),
 138         PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"),
 139         PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"),
 140         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"),
 141         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"),
 142         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"),
 143         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"),
 144         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"),
 145         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"),
 146         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"),
 147         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"),
 148         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"),
 149         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"),
 150         PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"),
 151         PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"),
 152         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"),
 153         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"),
 154         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"),
 155         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"),
 156         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"),
 157         PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"),
 158         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"),
 159         PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"),
 160         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"),
 161         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"),
 162         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"),
 163         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"),
 164         PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"),
 165         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"),
 166         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"),
 167         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"),
 168         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"),
 169         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) PRO/1000 Network Connection"),
 170         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) PRO/1000 Network Connection"),
 171         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) PRO/1000 Network Connection"),
 172         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) PRO/1000 Network Connection"),
 173         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) PRO/1000 Network Connection"),
 174         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) PRO/1000 Network Connection"),
 175         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) PRO/1000 Network Connection"),
 176         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) PRO/1000 Network Connection"),
 177         /* required last entry */
 178         PVID_END
 179 };
 180
 181 static pci_vendor_info_t igb_vendor_info_array[] =
 182 {
 183         /* Intel(R) PRO/1000 Network Connection - igb */
 184         PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 185         PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 186         PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 187         PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 188         PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 189         PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 190         PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 191         PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 192         PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 193         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 194         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 195         PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 196         PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 197         PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 198         PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 199         PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 200         PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 201         PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 202         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 203         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 204         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 205         PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 206         PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 207         PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 208         PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 209         PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 210         PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 211         PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 212         PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 213         PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 214         PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 215         PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 216         PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 217         PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 218         PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 219         PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 220         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 221         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 222         PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 223         /* required last entry */
 224         PVID_END
 225 };
 226
 227 /*********************************************************************
 228  *  Function prototypes
 229  *********************************************************************/
 230 static void     *em_register(device_t dev);
 231 static void     *igb_register(device_t dev);
 232 static int      em_if_attach_pre(if_ctx_t ctx);
 233 static int      em_if_attach_post(if_ctx_t ctx);
 234 static int      em_if_detach(if_ctx_t ctx);
 235 static int      em_if_shutdown(if_ctx_t ctx);
 236 static int      em_if_suspend(if_ctx_t ctx);
 237 static int      em_if_resume(if_ctx_t ctx);
 238
 239 static int      em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets);
 240 static int      em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets);
 241 static void     em_if_queues_free(if_ctx_t ctx);
 242
 243 static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
 244 static void     em_if_init(if_ctx_t ctx);
 245 static void     em_if_stop(if_ctx_t ctx);
 246 static void     em_if_media_status(if_ctx_t, struct ifmediareq *);
 247 static int      em_if_media_change(if_ctx_t ctx);
 248 static int      em_if_mtu_set(if_ctx_t ctx, uint32_t mtu);
 249 static void     em_if_timer(if_ctx_t ctx, uint16_t qid);
 250 static void     em_if_vlan_register(if_ctx_t ctx, u16 vtag);
 251 static void     em_if_vlan_unregister(if_ctx_t ctx, u16 vtag);
 252 static void     em_if_watchdog_reset(if_ctx_t ctx);
 253
 254 static void     em_identify_hardware(if_ctx_t ctx);
 255 static int      em_allocate_pci_resources(if_ctx_t ctx);
 256 static void     em_free_pci_resources(if_ctx_t ctx);
 257 static void     em_reset(if_ctx_t ctx);
 258 static int      em_setup_interface(if_ctx_t ctx);
 259 static int      em_setup_msix(if_ctx_t ctx);
 260
 261 static void     em_initialize_transmit_unit(if_ctx_t ctx);
 262 static void     em_initialize_receive_unit(if_ctx_t ctx);
 263
 264 static void     em_if_enable_intr(if_ctx_t ctx);
 265 static void     em_if_disable_intr(if_ctx_t ctx);
 266 static int      em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 267 static int      em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
 268 static void     em_if_multi_set(if_ctx_t ctx);
 269 static void     em_if_update_admin_status(if_ctx_t ctx);
 270 static void     em_if_debug(if_ctx_t ctx);
 271 static void     em_update_stats_counters(struct adapter *);
 272 static void     em_add_hw_stats(struct adapter *adapter);
 273 static int      em_if_set_promisc(if_ctx_t ctx, int flags);
 274 static void     em_setup_vlan_hw_support(struct adapter *);
 275 static int      em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
 276 static void     em_print_nvm_info(struct adapter *);
 277 static int      em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 278 static int      em_get_rs(SYSCTL_HANDLER_ARGS);
 279 static void     em_print_debug_info(struct adapter *);
 280 static int      em_is_valid_ether_addr(u8 *);
 281 static int      em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
 282 static void     em_add_int_delay_sysctl(struct adapter *, const char *,
 283                     const char *, struct em_int_delay_info *, int, int);
 284 /* Management and WOL Support */
 285 static void     em_init_manageability(struct adapter *);
 286 static void     em_release_manageability(struct adapter *);
 287 static void     em_get_hw_control(struct adapter *);
 288 static void     em_release_hw_control(struct adapter *);
 289 static void     em_get_wakeup(if_ctx_t ctx);
 290 static void     em_enable_wakeup(if_ctx_t ctx);
 291 static int      em_enable_phy_wakeup(struct adapter *);
 292 static void     em_disable_aspm(struct adapter *);
 293
 294 int             em_intr(void *arg);
 295 static void     em_disable_promisc(if_ctx_t ctx);
 296
 297 /* MSI-X handlers */
 298 static int      em_if_msix_intr_assign(if_ctx_t, int);
 299 static int      em_msix_link(void *);
 300 static void     em_handle_link(void *context);
 301
 302 static void     em_enable_vectors_82574(if_ctx_t);
 303
 304 static int      em_set_flowcntl(SYSCTL_HANDLER_ARGS);
 305 static int      em_sysctl_eee(SYSCTL_HANDLER_ARGS);
 306 static void     em_if_led_func(if_ctx_t ctx, int onoff);
 307
 308 static int      em_get_regs(SYSCTL_HANDLER_ARGS);
 309
 310 static void     lem_smartspeed(struct adapter *adapter);
 311 static void     igb_configure_queues(struct adapter *adapter);
 312
 313
 314 /*********************************************************************
 315  *  FreeBSD Device Interface Entry Points
 316  *********************************************************************/
 317 static device_method_t em_methods[] = {
 318         /* Device interface */
 319         DEVMETHOD(device_register, em_register),
 320         DEVMETHOD(device_probe, iflib_device_probe),
 321         DEVMETHOD(device_attach, iflib_device_attach),
 322         DEVMETHOD(device_detach, iflib_device_detach),
 323         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 324         DEVMETHOD(device_suspend, iflib_device_suspend),
 325         DEVMETHOD(device_resume, iflib_device_resume),
 326         DEVMETHOD_END
 327 };
 328
 329 static device_method_t igb_methods[] = {
 330         /* Device interface */
 331         DEVMETHOD(device_register, igb_register),
 332         DEVMETHOD(device_probe, iflib_device_probe),
 333         DEVMETHOD(device_attach, iflib_device_attach),
 334         DEVMETHOD(device_detach, iflib_device_detach),
 335         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 336         DEVMETHOD(device_suspend, iflib_device_suspend),
 337         DEVMETHOD(device_resume, iflib_device_resume),
 338         DEVMETHOD_END
 339 };
 340
 341
 342 static driver_t em_driver = {
 343         "em", em_methods, sizeof(struct adapter),
 344 };
 345
 346 static devclass_t em_devclass;
 347 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
 348
 349 MODULE_DEPEND(em, pci, 1, 1, 1);
 350 MODULE_DEPEND(em, ether, 1, 1, 1);
 351 MODULE_DEPEND(em, iflib, 1, 1, 1);
 352
 353 IFLIB_PNP_INFO(pci, em, em_vendor_info_array);
 354
 355 static driver_t igb_driver = {
 356         "igb", igb_methods, sizeof(struct adapter),
 357 };
 358
 359 static devclass_t igb_devclass;
 360 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
 361
 362 MODULE_DEPEND(igb, pci, 1, 1, 1);
 363 MODULE_DEPEND(igb, ether, 1, 1, 1);
 364 MODULE_DEPEND(igb, iflib, 1, 1, 1);
 365
 366 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array);
 367
 368 static device_method_t em_if_methods[] = {
 369         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 370         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 371         DEVMETHOD(ifdi_detach, em_if_detach),
 372         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 373         DEVMETHOD(ifdi_suspend, em_if_suspend),
 374         DEVMETHOD(ifdi_resume, em_if_resume),
 375         DEVMETHOD(ifdi_init, em_if_init),
 376         DEVMETHOD(ifdi_stop, em_if_stop),
 377         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 378         DEVMETHOD(ifdi_intr_enable, em_if_enable_intr),
 379         DEVMETHOD(ifdi_intr_disable, em_if_disable_intr),
 380         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 381         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 382         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 383         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 384         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 385         DEVMETHOD(ifdi_media_status, em_if_media_status),
 386         DEVMETHOD(ifdi_media_change, em_if_media_change),
 387         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 388         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 389         DEVMETHOD(ifdi_timer, em_if_timer),
 390         DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
 391         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 392         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 393         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 394         DEVMETHOD(ifdi_led_func, em_if_led_func),
 395         DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable),
 396         DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable),
 397         DEVMETHOD(ifdi_debug, em_if_debug),
 398         DEVMETHOD_END
 399 };
 400
 401 /*
 402  * note that if (adapter->msix_mem) is replaced by:
 403  * if (adapter->intr_type == IFLIB_INTR_MSIX)
 404  */
 405 static driver_t em_if_driver = {
 406         "em_if", em_if_methods, sizeof(struct adapter)
 407 };
 408
 409 /*********************************************************************
 410  *  Tunable default values.
 411  *********************************************************************/
 412
 413 #define EM_TICKS_TO_USECS(ticks)        ((1024 * (ticks) + 500) / 1000)
 414 #define EM_USECS_TO_TICKS(usecs)        ((1000 * (usecs) + 512) / 1024)
 415
 416 #define MAX_INTS_PER_SEC        8000
 417 #define DEFAULT_ITR             (1000000000/(MAX_INTS_PER_SEC * 256))
 418
 419 /* Allow common code without TSO */
 420 #ifndef CSUM_TSO
 421 #define CSUM_TSO        0
 422 #endif
 423
 424 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters");
 425
 426 static int em_disable_crc_stripping = 0;
 427 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
 428     &em_disable_crc_stripping, 0, "Disable CRC Stripping");
 429
 430 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
 431 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
 432 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
 433     0, "Default transmit interrupt delay in usecs");
 434 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
 435     0, "Default receive interrupt delay in usecs");
 436
 437 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
 438 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
 439 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
 440     &em_tx_abs_int_delay_dflt, 0,
 441     "Default transmit interrupt delay limit in usecs");
 442 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
 443     &em_rx_abs_int_delay_dflt, 0,
 444     "Default receive interrupt delay limit in usecs");
 445
 446 static int em_smart_pwr_down = FALSE;
 447 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
 448     0, "Set to true to leave smart power down enabled on newer adapters");
 449
 450 /* Controls whether promiscuous also shows bad packets */
 451 static int em_debug_sbp = TRUE;
 452 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
 453     "Show bad packets in promiscuous mode");
 454
 455 /* How many packets rxeof tries to clean at a time */
 456 static int em_rx_process_limit = 100;
 457 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
 458     &em_rx_process_limit, 0,
 459     "Maximum number of received packets to process "
 460     "at a time, -1 means unlimited");
 461
 462 /* Energy efficient ethernet - default to OFF */
 463 static int eee_setting = 1;
 464 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
 465     "Enable Energy Efficient Ethernet");
 466
 467 /*
 468 ** Tuneable Interrupt rate
 469 */
 470 static int em_max_interrupt_rate = 8000;
 471 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
 472     &em_max_interrupt_rate, 0, "Maximum interrupts per second");
 473
 474
 475
 476 /* Global used in WOL setup with multiport cards */
 477 static int global_quad_port_a = 0;
 478
 479 extern struct if_txrx igb_txrx;
 480 extern struct if_txrx em_txrx;
 481 extern struct if_txrx lem_txrx;
 482
 483 static struct if_shared_ctx em_sctx_init = {
 484         .isc_magic = IFLIB_MAGIC,
 485         .isc_q_align = PAGE_SIZE,
 486         .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 487         .isc_tx_maxsegsize = PAGE_SIZE,
 488         .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 489         .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
 490         .isc_rx_maxsize = MJUM9BYTES,
 491         .isc_rx_nsegments = 1,
 492         .isc_rx_maxsegsize = MJUM9BYTES,
 493         .isc_nfl = 1,
 494         .isc_nrxqs = 1,
 495         .isc_ntxqs = 1,
 496         .isc_admin_intrcnt = 1,
 497         .isc_vendor_info = em_vendor_info_array,
 498         .isc_driver_version = em_driver_version,
 499         .isc_driver = &em_if_driver,
 500         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 501
 502         .isc_nrxd_min = {EM_MIN_RXD},
 503         .isc_ntxd_min = {EM_MIN_TXD},
 504         .isc_nrxd_max = {EM_MAX_RXD},
 505         .isc_ntxd_max = {EM_MAX_TXD},
 506         .isc_nrxd_default = {EM_DEFAULT_RXD},
 507         .isc_ntxd_default = {EM_DEFAULT_TXD},
 508 };
 509
 510 if_shared_ctx_t em_sctx = &em_sctx_init;
 511
 512 static struct if_shared_ctx igb_sctx_init = {
 513         .isc_magic = IFLIB_MAGIC,
 514         .isc_q_align = PAGE_SIZE,
 515         .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 516         .isc_tx_maxsegsize = PAGE_SIZE,
 517         .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 518         .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
 519         .isc_rx_maxsize = MJUM9BYTES,
 520         .isc_rx_nsegments = 1,
 521         .isc_rx_maxsegsize = MJUM9BYTES,
 522         .isc_nfl = 1,
 523         .isc_nrxqs = 1,
 524         .isc_ntxqs = 1,
 525         .isc_admin_intrcnt = 1,
 526         .isc_vendor_info = igb_vendor_info_array,
 527         .isc_driver_version = em_driver_version,
 528         .isc_driver = &em_if_driver,
 529         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 530
 531         .isc_nrxd_min = {EM_MIN_RXD},
 532         .isc_ntxd_min = {EM_MIN_TXD},
 533         .isc_nrxd_max = {IGB_MAX_RXD},
 534         .isc_ntxd_max = {IGB_MAX_TXD},
 535         .isc_nrxd_default = {EM_DEFAULT_RXD},
 536         .isc_ntxd_default = {EM_DEFAULT_TXD},
 537 };
 538
 539 if_shared_ctx_t igb_sctx = &igb_sctx_init;
 540
 541 /*****************************************************************
 542  *
 543  * Dump Registers
 544  *
 545  ****************************************************************/
 546 #define IGB_REGS_LEN 739
 547
 548 static int em_get_regs(SYSCTL_HANDLER_ARGS)
 549 {
 550         struct adapter *adapter = (struct adapter *)arg1;
 551         struct e1000_hw *hw = &adapter->hw;
 552         struct sbuf *sb;
 553         u32 *regs_buff;
 554         int rc;
 555
 556         regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK);
 557         memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
 558
 559         rc = sysctl_wire_old_buffer(req, 0);
 560         MPASS(rc == 0);
 561         if (rc != 0) {
 562                 free(regs_buff, M_DEVBUF);
 563                 return (rc);
 564         }
 565
 566         sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
 567         MPASS(sb != NULL);
 568         if (sb == NULL) {
 569                 free(regs_buff, M_DEVBUF);
 570                 return (ENOMEM);
 571         }
 572
 573         /* General Registers */
 574         regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
 575         regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
 576         regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
 577         regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
 578         regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
 579         regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
 580         regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
 581         regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
 582         regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
 583         regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
 584         regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
 585         regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
 586         regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
 587         regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
 588         regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
 589         regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
 590         regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
 591         regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
 592         regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
 593         regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
 594         regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
 595         regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
 596
 597         sbuf_printf(sb, "General Registers\n");
 598         sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
 599         sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
 600         sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]);
 601
 602         sbuf_printf(sb, "Interrupt Registers\n");
 603         sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
 604
 605         sbuf_printf(sb, "RX Registers\n");
 606         sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
 607         sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
 608         sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
 609         sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
 610         sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
 611         sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
 612         sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
 613
 614         sbuf_printf(sb, "TX Registers\n");
 615         sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
 616         sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
 617         sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
 618         sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
 619         sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
 620         sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
 621         sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
 622         sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
 623         sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
 624         sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
 625         sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
 626
 627         free(regs_buff, M_DEVBUF);
 628
 629 #ifdef DUMP_DESCS
 630         {
 631                 if_softc_ctx_t scctx = adapter->shared;
 632                 struct rx_ring *rxr = &rx_que->rxr;
 633                 struct tx_ring *txr = &tx_que->txr;
 634                 int ntxd = scctx->isc_ntxd[0];
 635                 int nrxd = scctx->isc_nrxd[0];
 636                 int j;
 637
 638         for (j = 0; j < nrxd; j++) {
 639                 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
 640                 u32 length =  le32toh(rxr->rx_base[j].wb.upper.length);
 641                 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 "  Error:%d  Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
 642         }
 643
 644         for (j = 0; j < min(ntxd, 256); j++) {
 645                 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
 646
 647                 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x  eop: %d DD=%d\n",
 648                             j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
 649                             buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
 650
 651         }
 652         }
 653 #endif
 654
 655         rc = sbuf_finish(sb);
 656         sbuf_delete(sb);
 657         return(rc);
 658 }
 659
 660 static void *
 661 em_register(device_t dev)
 662 {
 663         return (em_sctx);
 664 }
 665
 666 static void *
 667 igb_register(device_t dev)
 668 {
 669         return (igb_sctx);
 670 }
 671
 672 static int
 673 em_set_num_queues(if_ctx_t ctx)
 674 {
 675         struct adapter *adapter = iflib_get_softc(ctx);
 676         int maxqueues;
 677
 678         /* Sanity check based on HW */
 679         switch (adapter->hw.mac.type) {
 680         case e1000_82576:
 681         case e1000_82580:
 682         case e1000_i350:
 683         case e1000_i354:
 684                 maxqueues = 8;
 685                 break;
 686         case e1000_i210:
 687         case e1000_82575:
 688                 maxqueues = 4;
 689                 break;
 690         case e1000_i211:
 691         case e1000_82574:
 692                 maxqueues = 2;
 693                 break;
 694         default:
 695                 maxqueues = 1;
 696                 break;
 697         }
 698
 699         return (maxqueues);
 700 }
 701
 702 #define LEM_CAPS                                                        \
 703     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 704     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER
 705
 706 #define EM_CAPS                                                         \
 707     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 708     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 |  \
 709     IFCAP_LRO | IFCAP_VLAN_HWTSO
 710
 711 #define IGB_CAPS                                                        \
 712     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 713     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 |  \
 714     IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\
 715     IFCAP_TSO6
 716
 717 /*********************************************************************
 718  *  Device initialization routine
 719  *
 720  *  The attach entry point is called when the driver is being loaded.
 721  *  This routine identifies the type of hardware, allocates all resources
 722  *  and initializes the hardware.
 723  *
 724  *  return 0 on success, positive on failure
 725  *********************************************************************/
 726 static int
 727 em_if_attach_pre(if_ctx_t ctx)
 728 {
 729         struct adapter *adapter;
 730         if_softc_ctx_t scctx;
 731         device_t dev;
 732         struct e1000_hw *hw;
 733         int error = 0;
 734
 735         INIT_DEBUGOUT("em_if_attach_pre: begin");
 736         dev = iflib_get_dev(ctx);
 737         adapter = iflib_get_softc(ctx);
 738
 739         adapter->ctx = adapter->osdep.ctx = ctx;
 740         adapter->dev = adapter->osdep.dev = dev;
 741         scctx = adapter->shared = iflib_get_softc_ctx(ctx);
 742         adapter->media = iflib_get_media(ctx);
 743         hw = &adapter->hw;
 744
 745         adapter->tx_process_limit = scctx->isc_ntxd[0];
 746
 747         /* SYSCTL stuff */
 748         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 749             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 750             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 751             em_sysctl_nvm_info, "I", "NVM Information");
 752
 753         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 754             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 755             OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 756             em_sysctl_debug_info, "I", "Debug Information");
 757
 758         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 759             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 760             OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 761             em_set_flowcntl, "I", "Flow Control");
 762
 763         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 764             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 765             OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0,
 766             em_get_regs, "A", "Dump Registers");
 767
 768         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 769             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 770             OID_AUTO, "rs_dump", CTLTYPE_INT | CTLFLAG_RW, adapter, 0,
 771             em_get_rs, "I", "Dump RS indexes");
 772
 773         /* Determine hardware and mac info */
 774         em_identify_hardware(ctx);
 775
 776         scctx->isc_tx_nsegments = EM_MAX_SCATTER;
 777         scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
 778         if (bootverbose)
 779                 device_printf(dev, "attach_pre capping queues at %d\n",
 780                     scctx->isc_ntxqsets_max);
 781
 782         if (adapter->hw.mac.type >= igb_mac_min) {
 783                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
 784                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
 785                 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
 786                 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
 787                 scctx->isc_txrx = &igb_txrx;
 788                 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
 789                 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 790                 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 791                 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS;
 792                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO |
 793                      CSUM_IP6_TCP | CSUM_IP6_UDP;
 794                 if (adapter->hw.mac.type != e1000_82575)
 795                         scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
 796                 /*
 797                 ** Some new devices, as with ixgbe, now may
 798                 ** use a different BAR, so we need to keep
 799                 ** track of which is used.
 800                 */
 801                 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR);
 802                 if (pci_read_config(dev, scctx->isc_msix_bar, 4) == 0)
 803                         scctx->isc_msix_bar += 4;
 804         } else if (adapter->hw.mac.type >= em_mac_min) {
 805                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 806                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
 807                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 808                 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
 809                 scctx->isc_txrx = &em_txrx;
 810                 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
 811                 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 812                 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 813                 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS;
 814                 /*
 815                  * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO}
 816                  * by default as we don't have workarounds for all associated
 817                  * silicon errata.  E. g., with several MACs such as 82573E,
 818                  * TSO only works at Gigabit speed and otherwise can cause the
 819                  * hardware to hang (which also would be next to impossible to
 820                  * work around given that already queued TSO-using descriptors
 821                  * would need to be flushed and vlan(4) reconfigured at runtime
 822                  * in case of a link speed change).  Moreover, MACs like 82579
 823                  * still can hang at Gigabit even with all publicly documented
 824                  * TSO workarounds implemented.  Generally, the penality of
 825                  * these workarounds is rather high and may involve copying
 826                  * mbuf data around so advantages of TSO lapse.  Still, TSO may
 827                  * work for a few MACs of this class - at least when sticking
 828                  * with Gigabit - in which case users may enable TSO manually.
 829                  */
 830                 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
 831                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 832                 /*
 833                  * We support MSI-X with 82574 only, but indicate to iflib(4)
 834                  * that it shall give MSI at least a try with other devices.
 835                  */
 836                 if (adapter->hw.mac.type == e1000_82574) {
 837                         scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR);
 838                 } else {
 839                         scctx->isc_msix_bar = -1;
 840                         scctx->isc_disable_msix = 1;
 841                 }
 842         } else {
 843                 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 844                 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
 845                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 846                 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
 847                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP;
 848                 scctx->isc_txrx = &lem_txrx;
 849                 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS;
 850                 if (adapter->hw.mac.type < e1000_82543)
 851                         scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
 852                 /* INTx only */
 853                 scctx->isc_msix_bar = 0;
 854         }
 855
 856         /* Setup PCI resources */
 857         if (em_allocate_pci_resources(ctx)) {
 858                 device_printf(dev, "Allocation of PCI resources failed\n");
 859                 error = ENXIO;
 860                 goto err_pci;
 861         }
 862
 863         /*
 864         ** For ICH8 and family we need to
 865         ** map the flash memory, and this
 866         ** must happen after the MAC is
 867         ** identified
 868         */
 869         if ((hw->mac.type == e1000_ich8lan) ||
 870             (hw->mac.type == e1000_ich9lan) ||
 871             (hw->mac.type == e1000_ich10lan) ||
 872             (hw->mac.type == e1000_pchlan) ||
 873             (hw->mac.type == e1000_pch2lan) ||
 874             (hw->mac.type == e1000_pch_lpt)) {
 875                 int rid = EM_BAR_TYPE_FLASH;
 876                 adapter->flash = bus_alloc_resource_any(dev,
 877                     SYS_RES_MEMORY, &rid, RF_ACTIVE);
 878                 if (adapter->flash == NULL) {
 879                         device_printf(dev, "Mapping of Flash failed\n");
 880                         error = ENXIO;
 881                         goto err_pci;
 882                 }
 883                 /* This is used in the shared code */
 884                 hw->flash_address = (u8 *)adapter->flash;
 885                 adapter->osdep.flash_bus_space_tag =
 886                     rman_get_bustag(adapter->flash);
 887                 adapter->osdep.flash_bus_space_handle =
 888                     rman_get_bushandle(adapter->flash);
 889         }
 890         /*
 891         ** In the new SPT device flash is not  a
 892         ** separate BAR, rather it is also in BAR0,
 893         ** so use the same tag and an offset handle for the
 894         ** FLASH read/write macros in the shared code.
 895         */
 896         else if (hw->mac.type >= e1000_pch_spt) {
 897                 adapter->osdep.flash_bus_space_tag =
 898                     adapter->osdep.mem_bus_space_tag;
 899                 adapter->osdep.flash_bus_space_handle =
 900                     adapter->osdep.mem_bus_space_handle
 901                     + E1000_FLASH_BASE_ADDR;
 902         }
 903
 904         /* Do Shared Code initialization */
 905         error = e1000_setup_init_funcs(hw, TRUE);
 906         if (error) {
 907                 device_printf(dev, "Setup of Shared code failed, error %d\n",
 908                     error);
 909                 error = ENXIO;
 910                 goto err_pci;
 911         }
 912
 913         em_setup_msix(ctx);
 914         e1000_get_bus_info(hw);
 915
 916         /* Set up some sysctls for the tunable interrupt delays */
 917         em_add_int_delay_sysctl(adapter, "rx_int_delay",
 918             "receive interrupt delay in usecs", &adapter->rx_int_delay,
 919             E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
 920         em_add_int_delay_sysctl(adapter, "tx_int_delay",
 921             "transmit interrupt delay in usecs", &adapter->tx_int_delay,
 922             E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
 923         em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
 924             "receive interrupt delay limit in usecs",
 925             &adapter->rx_abs_int_delay,
 926             E1000_REGISTER(hw, E1000_RADV),
 927             em_rx_abs_int_delay_dflt);
 928         em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
 929             "transmit interrupt delay limit in usecs",
 930             &adapter->tx_abs_int_delay,
 931             E1000_REGISTER(hw, E1000_TADV),
 932             em_tx_abs_int_delay_dflt);
 933         em_add_int_delay_sysctl(adapter, "itr",
 934             "interrupt delay limit in usecs/4",
 935             &adapter->tx_itr,
 936             E1000_REGISTER(hw, E1000_ITR),
 937             DEFAULT_ITR);
 938
 939         hw->mac.autoneg = DO_AUTO_NEG;
 940         hw->phy.autoneg_wait_to_complete = FALSE;
 941         hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 942
 943         if (adapter->hw.mac.type < em_mac_min) {
 944                 e1000_init_script_state_82541(&adapter->hw, TRUE);
 945                 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
 946         }
 947         /* Copper options */
 948         if (hw->phy.media_type == e1000_media_type_copper) {
 949                 hw->phy.mdix = AUTO_ALL_MODES;
 950                 hw->phy.disable_polarity_correction = FALSE;
 951                 hw->phy.ms_type = EM_MASTER_SLAVE;
 952         }
 953
 954         /*
 955          * Set the frame limits assuming
 956          * standard ethernet sized frames.
 957          */
 958         scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
 959             ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
 960
 961         /*
 962          * This controls when hardware reports transmit completion
 963          * status.
 964          */
 965         hw->mac.report_tx_early = 1;
 966
 967         /* Allocate multicast array memory. */
 968         adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN *
 969             MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
 970         if (adapter->mta == NULL) {
 971                 device_printf(dev, "Can not allocate multicast setup array\n");
 972                 error = ENOMEM;
 973                 goto err_late;
 974         }
 975
 976         /* Check SOL/IDER usage */
 977         if (e1000_check_reset_block(hw))
 978                 device_printf(dev, "PHY reset is blocked"
 979                               " due to SOL/IDER session.\n");
 980
 981         /* Sysctl for setting Energy Efficient Ethernet */
 982         hw->dev_spec.ich8lan.eee_disable = eee_setting;
 983         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 984             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 985             OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW,
 986             adapter, 0, em_sysctl_eee, "I",
 987             "Disable Energy Efficient Ethernet");
 988
 989         /*
 990         ** Start from a known state, this is
 991         ** important in reading the nvm and
 992         ** mac from that.
 993         */
 994         e1000_reset_hw(hw);
 995
 996         /* Make sure we have a good EEPROM before we read from it */
 997         if (e1000_validate_nvm_checksum(hw) < 0) {
 998                 /*
 999                 ** Some PCI-E parts fail the first check due to
1000                 ** the link being in sleep state, call it again,
1001                 ** if it fails a second time its a real issue.
1002                 */
1003                 if (e1000_validate_nvm_checksum(hw) < 0) {
1004                         device_printf(dev,
1005                             "The EEPROM Checksum Is Not Valid\n");
1006                         error = EIO;
1007                         goto err_late;
1008                 }
1009         }
1010
1011         /* Copy the permanent MAC address out of the EEPROM */
1012         if (e1000_read_mac_addr(hw) < 0) {
1013                 device_printf(dev, "EEPROM read error while reading MAC"
1014                               " address\n");
1015                 error = EIO;
1016                 goto err_late;
1017         }
1018
1019         if (!em_is_valid_ether_addr(hw->mac.addr)) {
1020                 device_printf(dev, "Invalid MAC address\n");
1021                 error = EIO;
1022                 goto err_late;
1023         }
1024
1025         /* Disable ULP support */
1026         e1000_disable_ulp_lpt_lp(hw, TRUE);
1027
1028         /*
1029          * Get Wake-on-Lan and Management info for later use
1030          */
1031         em_get_wakeup(ctx);
1032
1033         /* Enable only WOL MAGIC by default */
1034         scctx->isc_capenable &= ~IFCAP_WOL;
1035         if (adapter->wol != 0)
1036                 scctx->isc_capenable |= IFCAP_WOL_MAGIC;
1037
1038         iflib_set_mac(ctx, hw->mac.addr);
1039
1040         return (0);
1041
1042 err_late:
1043         em_release_hw_control(adapter);
1044 err_pci:
1045         em_free_pci_resources(ctx);
1046         free(adapter->mta, M_DEVBUF);
1047
1048         return (error);
1049 }
1050
1051 static int
1052 em_if_attach_post(if_ctx_t ctx)
1053 {
1054         struct adapter *adapter = iflib_get_softc(ctx);
1055         struct e1000_hw *hw = &adapter->hw;
1056         int error = 0;
1057
1058         /* Setup OS specific network interface */
1059         error = em_setup_interface(ctx);
1060         if (error != 0) {
1061                 goto err_late;
1062         }
1063
1064         em_reset(ctx);
1065
1066         /* Initialize statistics */
1067         em_update_stats_counters(adapter);
1068         hw->mac.get_link_status = 1;
1069         em_if_update_admin_status(ctx);
1070         em_add_hw_stats(adapter);
1071
1072         /* Non-AMT based hardware can now take control from firmware */
1073         if (adapter->has_manage && !adapter->has_amt)
1074                 em_get_hw_control(adapter);
1075
1076         INIT_DEBUGOUT("em_if_attach_post: end");
1077
1078         return (error);
1079
1080 err_late:
1081         em_release_hw_control(adapter);
1082         em_free_pci_resources(ctx);
1083         em_if_queues_free(ctx);
1084         free(adapter->mta, M_DEVBUF);
1085
1086         return (error);
1087 }
1088
1089 /*********************************************************************
1090  *  Device removal routine
1091  *
1092  *  The detach entry point is called when the driver is being removed.
1093  *  This routine stops the adapter and deallocates all the resources
1094  *  that were allocated for driver operation.
1095  *
1096  *  return 0 on success, positive on failure
1097  *********************************************************************/
1098 static int
1099 em_if_detach(if_ctx_t ctx)
1100 {
1101         struct adapter  *adapter = iflib_get_softc(ctx);
1102
1103         INIT_DEBUGOUT("em_if_detach: begin");
1104
1105         e1000_phy_hw_reset(&adapter->hw);
1106
1107         em_release_manageability(adapter);
1108         em_release_hw_control(adapter);
1109         em_free_pci_resources(ctx);
1110
1111         return (0);
1112 }
1113
1114 /*********************************************************************
1115  *
1116  *  Shutdown entry point
1117  *
1118  **********************************************************************/
1119
1120 static int
1121 em_if_shutdown(if_ctx_t ctx)
1122 {
1123         return em_if_suspend(ctx);
1124 }
1125
1126 /*
1127  * Suspend/resume device methods.
1128  */
1129 static int
1130 em_if_suspend(if_ctx_t ctx)
1131 {
1132         struct adapter *adapter = iflib_get_softc(ctx);
1133
1134         em_release_manageability(adapter);
1135         em_release_hw_control(adapter);
1136         em_enable_wakeup(ctx);
1137         return (0);
1138 }
1139
1140 static int
1141 em_if_resume(if_ctx_t ctx)
1142 {
1143         struct adapter *adapter = iflib_get_softc(ctx);
1144
1145         if (adapter->hw.mac.type == e1000_pch2lan)
1146                 e1000_resume_workarounds_pchlan(&adapter->hw);
1147         em_if_init(ctx);
1148         em_init_manageability(adapter);
1149
1150         return(0);
1151 }
1152
1153 static int
1154 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1155 {
1156         int max_frame_size;
1157         struct adapter *adapter = iflib_get_softc(ctx);
1158         if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1159
1160          IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1161
1162         switch (adapter->hw.mac.type) {
1163         case e1000_82571:
1164         case e1000_82572:
1165         case e1000_ich9lan:
1166         case e1000_ich10lan:
1167         case e1000_pch2lan:
1168         case e1000_pch_lpt:
1169         case e1000_pch_spt:
1170         case e1000_pch_cnp:
1171         case e1000_82574:
1172         case e1000_82583:
1173         case e1000_80003es2lan:
1174                 /* 9K Jumbo Frame size */
1175                 max_frame_size = 9234;
1176                 break;
1177         case e1000_pchlan:
1178                 max_frame_size = 4096;
1179                 break;
1180         case e1000_82542:
1181         case e1000_ich8lan:
1182                 /* Adapters that do not support jumbo frames */
1183                 max_frame_size = ETHER_MAX_LEN;
1184                 break;
1185         default:
1186                 if (adapter->hw.mac.type >= igb_mac_min)
1187                         max_frame_size = 9234;
1188                 else /* lem */
1189                         max_frame_size = MAX_JUMBO_FRAME_SIZE;
1190         }
1191         if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1192                 return (EINVAL);
1193         }
1194
1195         scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
1196             mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1197         return (0);
1198 }
1199
1200 /*********************************************************************
1201  *  Init entry point
1202  *
1203  *  This routine is used in two ways. It is used by the stack as
1204  *  init entry point in network interface structure. It is also used
1205  *  by the driver as a hw/sw initialization routine to get to a
1206  *  consistent state.
1207  *
1208  **********************************************************************/
1209 static void
1210 em_if_init(if_ctx_t ctx)
1211 {
1212         struct adapter *adapter = iflib_get_softc(ctx);
1213         if_softc_ctx_t scctx = adapter->shared;
1214         struct ifnet *ifp = iflib_get_ifp(ctx);
1215         struct em_tx_queue *tx_que;
1216         int i;
1217
1218         INIT_DEBUGOUT("em_if_init: begin");
1219
1220         /* Get the latest mac address, User can use a LAA */
1221         bcopy(if_getlladdr(ifp), adapter->hw.mac.addr,
1222             ETHER_ADDR_LEN);
1223
1224         /* Put the address into the Receive Address Array */
1225         e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1226
1227         /*
1228          * With the 82571 adapter, RAR[0] may be overwritten
1229          * when the other port is reset, we make a duplicate
1230          * in RAR[14] for that eventuality, this assures
1231          * the interface continues to function.
1232          */
1233         if (adapter->hw.mac.type == e1000_82571) {
1234                 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1235                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1236                     E1000_RAR_ENTRIES - 1);
1237         }
1238
1239
1240         /* Initialize the hardware */
1241         em_reset(ctx);
1242         em_if_update_admin_status(ctx);
1243
1244         for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) {
1245                 struct tx_ring *txr = &tx_que->txr;
1246
1247                 txr->tx_rs_cidx = txr->tx_rs_pidx;
1248
1249                 /* Initialize the last processed descriptor to be the end of
1250                  * the ring, rather than the start, so that we avoid an
1251                  * off-by-one error when calculating how many descriptors are
1252                  * done in the credits_update function.
1253                  */
1254                 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
1255         }
1256
1257         /* Setup VLAN support, basic and offload if available */
1258         E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1259
1260         /* Clear bad data from Rx FIFOs */
1261         if (adapter->hw.mac.type >= igb_mac_min)
1262                 e1000_rx_fifo_flush_82575(&adapter->hw);
1263
1264         /* Configure for OS presence */
1265         em_init_manageability(adapter);
1266
1267         /* Prepare transmit descriptors and buffers */
1268         em_initialize_transmit_unit(ctx);
1269
1270         /* Setup Multicast table */
1271         em_if_multi_set(ctx);
1272
1273         /*
1274          * Figure out the desired mbuf
1275          * pool for doing jumbos
1276          */
1277         if (adapter->hw.mac.max_frame_size <= 2048)
1278                 adapter->rx_mbuf_sz = MCLBYTES;
1279 #ifndef CONTIGMALLOC_WORKS
1280         else
1281                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
1282 #else
1283         else if (adapter->hw.mac.max_frame_size <= 4096)
1284                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
1285         else
1286                 adapter->rx_mbuf_sz = MJUM9BYTES;
1287 #endif
1288         em_initialize_receive_unit(ctx);
1289
1290         /* Use real VLAN Filter support? */
1291         if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1292                 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
1293                         /* Use real VLAN Filter support */
1294                         em_setup_vlan_hw_support(adapter);
1295                 else {
1296                         u32 ctrl;
1297                         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1298                         ctrl |= E1000_CTRL_VME;
1299                         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1300                 }
1301         }
1302
1303         /* Don't lose promiscuous settings */
1304         em_if_set_promisc(ctx, IFF_PROMISC);
1305         e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1306
1307         /* MSI-X configuration for 82574 */
1308         if (adapter->hw.mac.type == e1000_82574) {
1309                 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1310
1311                 tmp |= E1000_CTRL_EXT_PBA_CLR;
1312                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1313                 /* Set the IVAR - interrupt vector routing. */
1314                 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars);
1315         } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1316                 igb_configure_queues(adapter);
1317
1318         /* this clears any pending interrupts */
1319         E1000_READ_REG(&adapter->hw, E1000_ICR);
1320         E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC);
1321
1322         /* AMT based hardware can now take control from firmware */
1323         if (adapter->has_manage && adapter->has_amt)
1324                 em_get_hw_control(adapter);
1325
1326         /* Set Energy Efficient Ethernet */
1327         if (adapter->hw.mac.type >= igb_mac_min &&
1328             adapter->hw.phy.media_type == e1000_media_type_copper) {
1329                 if (adapter->hw.mac.type == e1000_i354)
1330                         e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
1331                 else
1332                         e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
1333         }
1334 }
1335
1336 /*********************************************************************
1337  *
1338  *  Fast Legacy/MSI Combined Interrupt Service routine
1339  *
1340  *********************************************************************/
1341 int
1342 em_intr(void *arg)
1343 {
1344         struct adapter *adapter = arg;
1345         if_ctx_t ctx = adapter->ctx;
1346         u32 reg_icr;
1347
1348         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1349
1350         if (adapter->intr_type != IFLIB_INTR_LEGACY)
1351                 goto skip_stray;
1352         /* Hot eject? */
1353         if (reg_icr == 0xffffffff)
1354                 return FILTER_STRAY;
1355
1356         /* Definitely not our interrupt. */
1357         if (reg_icr == 0x0)
1358                 return FILTER_STRAY;
1359
1360         /*
1361          * Starting with the 82571 chip, bit 31 should be used to
1362          * determine whether the interrupt belongs to us.
1363          */
1364         if (adapter->hw.mac.type >= e1000_82571 &&
1365             (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1366                 return FILTER_STRAY;
1367
1368 skip_stray:
1369         /* Link status change */
1370         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1371                 adapter->hw.mac.get_link_status = 1;
1372                 iflib_admin_intr_deferred(ctx);
1373         }
1374
1375         if (reg_icr & E1000_ICR_RXO)
1376                 adapter->rx_overruns++;
1377
1378         return (FILTER_SCHEDULE_THREAD);
1379 }
1380
1381 static void
1382 igb_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq)
1383 {
1384         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims);
1385 }
1386
1387 static void
1388 em_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq)
1389 {
1390         E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims);
1391 }
1392
1393 static void
1394 igb_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq)
1395 {
1396         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims);
1397 }
1398
1399 static void
1400 em_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq)
1401 {
1402         E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims);
1403 }
1404
1405 static int
1406 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1407 {
1408         struct adapter *adapter = iflib_get_softc(ctx);
1409         struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1410
1411         if (adapter->hw.mac.type >= igb_mac_min)
1412                 igb_rx_enable_queue(adapter, rxq);
1413         else
1414                 em_rx_enable_queue(adapter, rxq);
1415         return (0);
1416 }
1417
1418 static int
1419 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1420 {
1421         struct adapter *adapter = iflib_get_softc(ctx);
1422         struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1423
1424         if (adapter->hw.mac.type >= igb_mac_min)
1425                 igb_tx_enable_queue(adapter, txq);
1426         else
1427                 em_tx_enable_queue(adapter, txq);
1428         return (0);
1429 }
1430
1431 /*********************************************************************
1432  *
1433  *  MSI-X RX Interrupt Service routine
1434  *
1435  **********************************************************************/
1436 static int
1437 em_msix_que(void *arg)
1438 {
1439         struct em_rx_queue *que = arg;
1440
1441         ++que->irqs;
1442
1443         return (FILTER_SCHEDULE_THREAD);
1444 }
1445
1446 /*********************************************************************
1447  *
1448  *  MSI-X Link Fast Interrupt Service routine
1449  *
1450  **********************************************************************/
1451 static int
1452 em_msix_link(void *arg)
1453 {
1454         struct adapter *adapter = arg;
1455         u32 reg_icr;
1456
1457         ++adapter->link_irq;
1458         MPASS(adapter->hw.back != NULL);
1459         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1460
1461         if (reg_icr & E1000_ICR_RXO)
1462                 adapter->rx_overruns++;
1463
1464         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1465                 em_handle_link(adapter->ctx);
1466         } else {
1467                 E1000_WRITE_REG(&adapter->hw, E1000_IMS,
1468                                 EM_MSIX_LINK | E1000_IMS_LSC);
1469                 if (adapter->hw.mac.type >= igb_mac_min)
1470                         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1471         }
1472
1473         /*
1474          * Because we must read the ICR for this interrupt
1475          * it may clear other causes using autoclear, for
1476          * this reason we simply create a soft interrupt
1477          * for all these vectors.
1478          */
1479         if (reg_icr && adapter->hw.mac.type < igb_mac_min) {
1480                 E1000_WRITE_REG(&adapter->hw,
1481                         E1000_ICS, adapter->ims);
1482         }
1483
1484         return (FILTER_HANDLED);
1485 }
1486
1487 static void
1488 em_handle_link(void *context)
1489 {
1490         if_ctx_t ctx = context;
1491         struct adapter *adapter = iflib_get_softc(ctx);
1492
1493         adapter->hw.mac.get_link_status = 1;
1494         iflib_admin_intr_deferred(ctx);
1495 }
1496
1497
1498 /*********************************************************************
1499  *
1500  *  Media Ioctl callback
1501  *
1502  *  This routine is called whenever the user queries the status of
1503  *  the interface using ifconfig.
1504  *
1505  **********************************************************************/
1506 static void
1507 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1508 {
1509         struct adapter *adapter = iflib_get_softc(ctx);
1510         u_char fiber_type = IFM_1000_SX;
1511
1512         INIT_DEBUGOUT("em_if_media_status: begin");
1513
1514         iflib_admin_intr_deferred(ctx);
1515
1516         ifmr->ifm_status = IFM_AVALID;
1517         ifmr->ifm_active = IFM_ETHER;
1518
1519         if (!adapter->link_active) {
1520                 return;
1521         }
1522
1523         ifmr->ifm_status |= IFM_ACTIVE;
1524
1525         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
1526             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1527                 if (adapter->hw.mac.type == e1000_82545)
1528                         fiber_type = IFM_1000_LX;
1529                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1530         } else {
1531                 switch (adapter->link_speed) {
1532                 case 10:
1533                         ifmr->ifm_active |= IFM_10_T;
1534                         break;
1535                 case 100:
1536                         ifmr->ifm_active |= IFM_100_TX;
1537                         break;
1538                 case 1000:
1539                         ifmr->ifm_active |= IFM_1000_T;
1540                         break;
1541                 }
1542                 if (adapter->link_duplex == FULL_DUPLEX)
1543                         ifmr->ifm_active |= IFM_FDX;
1544                 else
1545                         ifmr->ifm_active |= IFM_HDX;
1546         }
1547 }
1548
1549 /*********************************************************************
1550  *
1551  *  Media Ioctl callback
1552  *
1553  *  This routine is called when the user changes speed/duplex using
1554  *  media/mediopt option with ifconfig.
1555  *
1556  **********************************************************************/
1557 static int
1558 em_if_media_change(if_ctx_t ctx)
1559 {
1560         struct adapter *adapter = iflib_get_softc(ctx);
1561         struct ifmedia *ifm = iflib_get_media(ctx);
1562
1563         INIT_DEBUGOUT("em_if_media_change: begin");
1564
1565         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1566                 return (EINVAL);
1567
1568         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1569         case IFM_AUTO:
1570                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1571                 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1572                 break;
1573         case IFM_1000_LX:
1574         case IFM_1000_SX:
1575         case IFM_1000_T:
1576                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1577                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1578                 break;
1579         case IFM_100_TX:
1580                 adapter->hw.mac.autoneg = FALSE;
1581                 adapter->hw.phy.autoneg_advertised = 0;
1582                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1583                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1584                 else
1585                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1586                 break;
1587         case IFM_10_T:
1588                 adapter->hw.mac.autoneg = FALSE;
1589                 adapter->hw.phy.autoneg_advertised = 0;
1590                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1591                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1592                 else
1593                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1594                 break;
1595         default:
1596                 device_printf(adapter->dev, "Unsupported media type\n");
1597         }
1598
1599         em_if_init(ctx);
1600
1601         return (0);
1602 }
1603
1604 static int
1605 em_if_set_promisc(if_ctx_t ctx, int flags)
1606 {
1607         struct adapter *adapter = iflib_get_softc(ctx);
1608         u32 reg_rctl;
1609
1610         em_disable_promisc(ctx);
1611
1612         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1613
1614         if (flags & IFF_PROMISC) {
1615                 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1616                 /* Turn this on if you want to see bad packets */
1617                 if (em_debug_sbp)
1618                         reg_rctl |= E1000_RCTL_SBP;
1619                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1620         } else if (flags & IFF_ALLMULTI) {
1621                 reg_rctl |= E1000_RCTL_MPE;
1622                 reg_rctl &= ~E1000_RCTL_UPE;
1623                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1624         }
1625         return (0);
1626 }
1627
1628 static void
1629 em_disable_promisc(if_ctx_t ctx)
1630 {
1631         struct adapter *adapter = iflib_get_softc(ctx);
1632         struct ifnet *ifp = iflib_get_ifp(ctx);
1633         u32 reg_rctl;
1634         int mcnt = 0;
1635
1636         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1637         reg_rctl &= (~E1000_RCTL_UPE);
1638         if (if_getflags(ifp) & IFF_ALLMULTI)
1639                 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1640         else
1641                 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES);
1642         /* Don't disable if in MAX groups */
1643         if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1644                 reg_rctl &=  (~E1000_RCTL_MPE);
1645         reg_rctl &=  (~E1000_RCTL_SBP);
1646         E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1647 }
1648
1649
1650 /*********************************************************************
1651  *  Multicast Update
1652  *
1653  *  This routine is called whenever multicast address list is updated.
1654  *
1655  **********************************************************************/
1656
1657 static void
1658 em_if_multi_set(if_ctx_t ctx)
1659 {
1660         struct adapter *adapter = iflib_get_softc(ctx);
1661         struct ifnet *ifp = iflib_get_ifp(ctx);
1662         u32 reg_rctl = 0;
1663         u8  *mta; /* Multicast array memory */
1664         int mcnt = 0;
1665
1666         IOCTL_DEBUGOUT("em_set_multi: begin");
1667
1668         mta = adapter->mta;
1669         bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1670
1671         if (adapter->hw.mac.type == e1000_82542 &&
1672             adapter->hw.revision_id == E1000_REVISION_2) {
1673                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1674                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1675                         e1000_pci_clear_mwi(&adapter->hw);
1676                 reg_rctl |= E1000_RCTL_RST;
1677                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1678                 msec_delay(5);
1679         }
1680
1681         if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES);
1682
1683         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1684                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1685                 reg_rctl |= E1000_RCTL_MPE;
1686                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1687         } else
1688                 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
1689
1690         if (adapter->hw.mac.type == e1000_82542 &&
1691             adapter->hw.revision_id == E1000_REVISION_2) {
1692                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1693                 reg_rctl &= ~E1000_RCTL_RST;
1694                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1695                 msec_delay(5);
1696                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1697                         e1000_pci_set_mwi(&adapter->hw);
1698         }
1699 }
1700
1701 /*********************************************************************
1702  *  Timer routine
1703  *
1704  *  This routine schedules em_if_update_admin_status() to check for
1705  *  link status and to gather statistics as well as to perform some
1706  *  controller-specific hardware patting.
1707  *
1708  **********************************************************************/
1709 static void
1710 em_if_timer(if_ctx_t ctx, uint16_t qid)
1711 {
1712
1713         if (qid != 0)
1714                 return;
1715
1716         iflib_admin_intr_deferred(ctx);
1717 }
1718
1719 static void
1720 em_if_update_admin_status(if_ctx_t ctx)
1721 {
1722         struct adapter *adapter = iflib_get_softc(ctx);
1723         struct e1000_hw *hw = &adapter->hw;
1724         device_t dev = iflib_get_dev(ctx);
1725         u32 link_check, thstat, ctrl;
1726
1727         link_check = thstat = ctrl = 0;
1728         /* Get the cached link value or read phy for real */
1729         switch (hw->phy.media_type) {
1730         case e1000_media_type_copper:
1731                 if (hw->mac.get_link_status) {
1732                         if (hw->mac.type == e1000_pch_spt)
1733                                 msec_delay(50);
1734                         /* Do the work to read phy */
1735                         e1000_check_for_link(hw);
1736                         link_check = !hw->mac.get_link_status;
1737                         if (link_check) /* ESB2 fix */
1738                                 e1000_cfg_on_link_up(hw);
1739                 } else {
1740                         link_check = TRUE;
1741                 }
1742                 break;
1743         case e1000_media_type_fiber:
1744                 e1000_check_for_link(hw);
1745                 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1746                             E1000_STATUS_LU);
1747                 break;
1748         case e1000_media_type_internal_serdes:
1749                 e1000_check_for_link(hw);
1750                 link_check = adapter->hw.mac.serdes_has_link;
1751                 break;
1752         /* VF device is type_unknown */
1753         case e1000_media_type_unknown:
1754                 e1000_check_for_link(hw);
1755                 link_check = !hw->mac.get_link_status;
1756                 /* FALLTHROUGH */
1757         default:
1758                 break;
1759         }
1760
1761         /* Check for thermal downshift or shutdown */
1762         if (hw->mac.type == e1000_i350) {
1763                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1764                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1765         }
1766
1767         /* Now check for a transition */
1768         if (link_check && (adapter->link_active == 0)) {
1769                 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
1770                     &adapter->link_duplex);
1771                 /* Check if we must disable SPEED_MODE bit on PCI-E */
1772                 if ((adapter->link_speed != SPEED_1000) &&
1773                     ((hw->mac.type == e1000_82571) ||
1774                     (hw->mac.type == e1000_82572))) {
1775                         int tarc0;
1776                         tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1777                         tarc0 &= ~TARC_SPEED_MODE_BIT;
1778                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1779                 }
1780                 if (bootverbose)
1781                         device_printf(dev, "Link is up %d Mbps %s\n",
1782                             adapter->link_speed,
1783                             ((adapter->link_duplex == FULL_DUPLEX) ?
1784                             "Full Duplex" : "Half Duplex"));
1785                 adapter->link_active = 1;
1786                 adapter->smartspeed = 0;
1787                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) ==
1788                     E1000_CTRL_EXT_LINK_MODE_GMII &&
1789                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1790                         device_printf(dev, "Link: thermal downshift\n");
1791                 /* Delay Link Up for Phy update */
1792                 if (((hw->mac.type == e1000_i210) ||
1793                     (hw->mac.type == e1000_i211)) &&
1794                     (hw->phy.id == I210_I_PHY_ID))
1795                         msec_delay(I210_LINK_DELAY);
1796                 /* Reset if the media type changed. */
1797                 if ((hw->dev_spec._82575.media_changed) &&
1798                         (adapter->hw.mac.type >= igb_mac_min)) {
1799                         hw->dev_spec._82575.media_changed = false;
1800                         adapter->flags |= IGB_MEDIA_RESET;
1801                         em_reset(ctx);
1802                 }
1803                 iflib_link_state_change(ctx, LINK_STATE_UP,
1804                     IF_Mbps(adapter->link_speed));
1805         } else if (!link_check && (adapter->link_active == 1)) {
1806                 adapter->link_speed = 0;
1807                 adapter->link_duplex = 0;
1808                 adapter->link_active = 0;
1809                 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
1810         }
1811         em_update_stats_counters(adapter);
1812
1813         /* Reset LAA into RAR[0] on 82571 */
1814         if ((adapter->hw.mac.type == e1000_82571) &&
1815             e1000_get_laa_state_82571(&adapter->hw))
1816                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1817
1818         if (adapter->hw.mac.type < em_mac_min)
1819                 lem_smartspeed(adapter);
1820
1821         E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC);
1822 }
1823
1824 static void
1825 em_if_watchdog_reset(if_ctx_t ctx)
1826 {
1827         struct adapter *adapter = iflib_get_softc(ctx);
1828
1829         /*
1830          * Just count the event; iflib(4) will already trigger a
1831          * sufficient reset of the controller.
1832          */
1833         adapter->watchdog_events++;
1834 }
1835
1836 /*********************************************************************
1837  *
1838  *  This routine disables all traffic on the adapter by issuing a
1839  *  global reset on the MAC.
1840  *
1841  **********************************************************************/
1842 static void
1843 em_if_stop(if_ctx_t ctx)
1844 {
1845         struct adapter *adapter = iflib_get_softc(ctx);
1846
1847         INIT_DEBUGOUT("em_if_stop: begin");
1848
1849         e1000_reset_hw(&adapter->hw);
1850         if (adapter->hw.mac.type >= e1000_82544)
1851                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0);
1852
1853         e1000_led_off(&adapter->hw);
1854         e1000_cleanup_led(&adapter->hw);
1855 }
1856
1857 /*********************************************************************
1858  *
1859  *  Determine hardware revision.
1860  *
1861  **********************************************************************/
1862 static void
1863 em_identify_hardware(if_ctx_t ctx)
1864 {
1865         device_t dev = iflib_get_dev(ctx);
1866         struct adapter *adapter = iflib_get_softc(ctx);
1867
1868         /* Make sure our PCI config space has the necessary stuff set */
1869         adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1870
1871         /* Save off the information about this board */
1872         adapter->hw.vendor_id = pci_get_vendor(dev);
1873         adapter->hw.device_id = pci_get_device(dev);
1874         adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1875         adapter->hw.subsystem_vendor_id =
1876             pci_read_config(dev, PCIR_SUBVEND_0, 2);
1877         adapter->hw.subsystem_device_id =
1878             pci_read_config(dev, PCIR_SUBDEV_0, 2);
1879
1880         /* Do Shared Code Init and Setup */
1881         if (e1000_set_mac_type(&adapter->hw)) {
1882                 device_printf(dev, "Setup init failure\n");
1883                 return;
1884         }
1885 }
1886
1887 static int
1888 em_allocate_pci_resources(if_ctx_t ctx)
1889 {
1890         struct adapter *adapter = iflib_get_softc(ctx);
1891         device_t dev = iflib_get_dev(ctx);
1892         int rid, val;
1893
1894         rid = PCIR_BAR(0);
1895         adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1896             &rid, RF_ACTIVE);
1897         if (adapter->memory == NULL) {
1898                 device_printf(dev, "Unable to allocate bus resource: memory\n");
1899                 return (ENXIO);
1900         }
1901         adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory);
1902         adapter->osdep.mem_bus_space_handle =
1903             rman_get_bushandle(adapter->memory);
1904         adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle;
1905
1906         /* Only older adapters use IO mapping */
1907         if (adapter->hw.mac.type < em_mac_min &&
1908             adapter->hw.mac.type > e1000_82543) {
1909                 /* Figure our where our IO BAR is ? */
1910                 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1911                         val = pci_read_config(dev, rid, 4);
1912                         if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1913                                 break;
1914                         }
1915                         rid += 4;
1916                         /* check for 64bit BAR */
1917                         if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1918                                 rid += 4;
1919                 }
1920                 if (rid >= PCIR_CIS) {
1921                         device_printf(dev, "Unable to locate IO BAR\n");
1922                         return (ENXIO);
1923                 }
1924                 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
1925                     &rid, RF_ACTIVE);
1926                 if (adapter->ioport == NULL) {
1927                         device_printf(dev, "Unable to allocate bus resource: "
1928                             "ioport\n");
1929                         return (ENXIO);
1930                 }
1931                 adapter->hw.io_base = 0;
1932                 adapter->osdep.io_bus_space_tag =
1933                     rman_get_bustag(adapter->ioport);
1934                 adapter->osdep.io_bus_space_handle =
1935                     rman_get_bushandle(adapter->ioport);
1936         }
1937
1938         adapter->hw.back = &adapter->osdep;
1939
1940         return (0);
1941 }
1942
1943 /*********************************************************************
1944  *
1945  *  Set up the MSI-X Interrupt handlers
1946  *
1947  **********************************************************************/
1948 static int
1949 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
1950 {
1951         struct adapter *adapter = iflib_get_softc(ctx);
1952         struct em_rx_queue *rx_que = adapter->rx_queues;
1953         struct em_tx_queue *tx_que = adapter->tx_queues;
1954         int error, rid, i, vector = 0, rx_vectors;
1955         char buf[16];
1956
1957         /* First set up ring resources */
1958         for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) {
1959                 rid = vector + 1;
1960                 snprintf(buf, sizeof(buf), "rxq%d", i);
1961                 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
1962                 if (error) {
1963                         device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
1964                         adapter->rx_num_queues = i + 1;
1965                         goto fail;
1966                 }
1967
1968                 rx_que->msix =  vector;
1969
1970                 /*
1971                  * Set the bit to enable interrupt
1972                  * in E1000_IMS -- bits 20 and 21
1973                  * are for RX0 and RX1, note this has
1974                  * NOTHING to do with the MSI-X vector
1975                  */
1976                 if (adapter->hw.mac.type == e1000_82574) {
1977                         rx_que->eims = 1 << (20 + i);
1978                         adapter->ims |= rx_que->eims;
1979                         adapter->ivars |= (8 | rx_que->msix) << (i * 4);
1980                 } else if (adapter->hw.mac.type == e1000_82575)
1981                         rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
1982                 else
1983                         rx_que->eims = 1 << vector;
1984         }
1985         rx_vectors = vector;
1986
1987         vector = 0;
1988         for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) {
1989                 snprintf(buf, sizeof(buf), "txq%d", i);
1990                 tx_que = &adapter->tx_queues[i];
1991                 iflib_softirq_alloc_generic(ctx,
1992                     &adapter->rx_queues[i % adapter->rx_num_queues].que_irq,
1993                     IFLIB_INTR_TX, tx_que, tx_que->me, buf);
1994
1995                 tx_que->msix = (vector % adapter->rx_num_queues);
1996
1997                 /*
1998                  * Set the bit to enable interrupt
1999                  * in E1000_IMS -- bits 22 and 23
2000                  * are for TX0 and TX1, note this has
2001                  * NOTHING to do with the MSI-X vector
2002                  */
2003                 if (adapter->hw.mac.type == e1000_82574) {
2004                         tx_que->eims = 1 << (22 + i);
2005                         adapter->ims |= tx_que->eims;
2006                         adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
2007                 } else if (adapter->hw.mac.type == e1000_82575) {
2008                         tx_que->eims = E1000_EICR_TX_QUEUE0 << i;
2009                 } else {
2010                         tx_que->eims = 1 << i;
2011                 }
2012         }
2013
2014         /* Link interrupt */
2015         rid = rx_vectors + 1;
2016         error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq");
2017
2018         if (error) {
2019                 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
2020                 goto fail;
2021         }
2022         adapter->linkvec = rx_vectors;
2023         if (adapter->hw.mac.type < igb_mac_min) {
2024                 adapter->ivars |=  (8 | rx_vectors) << 16;
2025                 adapter->ivars |= 0x80000000;
2026         }
2027         return (0);
2028 fail:
2029         iflib_irq_free(ctx, &adapter->irq);
2030         rx_que = adapter->rx_queues;
2031         for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++)
2032                 iflib_irq_free(ctx, &rx_que->que_irq);
2033         return (error);
2034 }
2035
2036 static void
2037 igb_configure_queues(struct adapter *adapter)
2038 {
2039         struct e1000_hw *hw = &adapter->hw;
2040         struct em_rx_queue *rx_que;
2041         struct em_tx_queue *tx_que;
2042         u32 tmp, ivar = 0, newitr = 0;
2043
2044         /* First turn on RSS capability */
2045         if (adapter->hw.mac.type != e1000_82575)
2046                 E1000_WRITE_REG(hw, E1000_GPIE,
2047                     E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
2048                     E1000_GPIE_PBA | E1000_GPIE_NSICR);
2049
2050         /* Turn on MSI-X */
2051         switch (adapter->hw.mac.type) {
2052         case e1000_82580:
2053         case e1000_i350:
2054         case e1000_i354:
2055         case e1000_i210:
2056         case e1000_i211:
2057         case e1000_vfadapt:
2058         case e1000_vfadapt_i350:
2059                 /* RX entries */
2060                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2061                         u32 index = i >> 1;
2062                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2063                         rx_que = &adapter->rx_queues[i];
2064                         if (i & 1) {
2065                                 ivar &= 0xFF00FFFF;
2066                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2067                         } else {
2068                                 ivar &= 0xFFFFFF00;
2069                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2070                         }
2071                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2072                 }
2073                 /* TX entries */
2074                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2075                         u32 index = i >> 1;
2076                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2077                         tx_que = &adapter->tx_queues[i];
2078                         if (i & 1) {
2079                                 ivar &= 0x00FFFFFF;
2080                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2081                         } else {
2082                                 ivar &= 0xFFFF00FF;
2083                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2084                         }
2085                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2086                         adapter->que_mask |= tx_que->eims;
2087                 }
2088
2089                 /* And for the link interrupt */
2090                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2091                 adapter->link_mask = 1 << adapter->linkvec;
2092                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2093                 break;
2094         case e1000_82576:
2095                 /* RX entries */
2096                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2097                         u32 index = i & 0x7; /* Each IVAR has two entries */
2098                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2099                         rx_que = &adapter->rx_queues[i];
2100                         if (i < 8) {
2101                                 ivar &= 0xFFFFFF00;
2102                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2103                         } else {
2104                                 ivar &= 0xFF00FFFF;
2105                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2106                         }
2107                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2108                         adapter->que_mask |= rx_que->eims;
2109                 }
2110                 /* TX entries */
2111                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2112                         u32 index = i & 0x7; /* Each IVAR has two entries */
2113                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2114                         tx_que = &adapter->tx_queues[i];
2115                         if (i < 8) {
2116                                 ivar &= 0xFFFF00FF;
2117                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2118                         } else {
2119                                 ivar &= 0x00FFFFFF;
2120                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2121                         }
2122                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2123                         adapter->que_mask |= tx_que->eims;
2124                 }
2125
2126                 /* And for the link interrupt */
2127                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2128                 adapter->link_mask = 1 << adapter->linkvec;
2129                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2130                 break;
2131
2132         case e1000_82575:
2133                 /* enable MSI-X support*/
2134                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2135                 tmp |= E1000_CTRL_EXT_PBA_CLR;
2136                 /* Auto-Mask interrupts upon ICR read. */
2137                 tmp |= E1000_CTRL_EXT_EIAME;
2138                 tmp |= E1000_CTRL_EXT_IRCA;
2139                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2140
2141                 /* Queues */
2142                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2143                         rx_que = &adapter->rx_queues[i];
2144                         tmp = E1000_EICR_RX_QUEUE0 << i;
2145                         tmp |= E1000_EICR_TX_QUEUE0 << i;
2146                         rx_que->eims = tmp;
2147                         E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2148                             i, rx_que->eims);
2149                         adapter->que_mask |= rx_que->eims;
2150                 }
2151
2152                 /* Link */
2153                 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec),
2154                     E1000_EIMS_OTHER);
2155                 adapter->link_mask |= E1000_EIMS_OTHER;
2156         default:
2157                 break;
2158         }
2159
2160         /* Set the starting interrupt rate */
2161         if (em_max_interrupt_rate > 0)
2162                 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2163
2164         if (hw->mac.type == e1000_82575)
2165                 newitr |= newitr << 16;
2166         else
2167                 newitr |= E1000_EITR_CNT_IGNR;
2168
2169         for (int i = 0; i < adapter->rx_num_queues; i++) {
2170                 rx_que = &adapter->rx_queues[i];
2171                 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2172         }
2173
2174         return;
2175 }
2176
2177 static void
2178 em_free_pci_resources(if_ctx_t ctx)
2179 {
2180         struct adapter *adapter = iflib_get_softc(ctx);
2181         struct em_rx_queue *que = adapter->rx_queues;
2182         device_t dev = iflib_get_dev(ctx);
2183
2184         /* Release all MSI-X queue resources */
2185         if (adapter->intr_type == IFLIB_INTR_MSIX)
2186                 iflib_irq_free(ctx, &adapter->irq);
2187
2188         for (int i = 0; i < adapter->rx_num_queues; i++, que++) {
2189                 iflib_irq_free(ctx, &que->que_irq);
2190         }
2191
2192         if (adapter->memory != NULL) {
2193                 bus_release_resource(dev, SYS_RES_MEMORY,
2194                     rman_get_rid(adapter->memory), adapter->memory);
2195                 adapter->memory = NULL;
2196         }
2197
2198         if (adapter->flash != NULL) {
2199                 bus_release_resource(dev, SYS_RES_MEMORY,
2200                     rman_get_rid(adapter->flash), adapter->flash);
2201                 adapter->flash = NULL;
2202         }
2203
2204         if (adapter->ioport != NULL) {
2205                 bus_release_resource(dev, SYS_RES_IOPORT,
2206                     rman_get_rid(adapter->ioport), adapter->ioport);
2207                 adapter->ioport = NULL;
2208         }
2209 }
2210
2211 /* Set up MSI or MSI-X */
2212 static int
2213 em_setup_msix(if_ctx_t ctx)
2214 {
2215         struct adapter *adapter = iflib_get_softc(ctx);
2216
2217         if (adapter->hw.mac.type == e1000_82574) {
2218                 em_enable_vectors_82574(ctx);
2219         }
2220         return (0);
2221 }
2222
2223 /*********************************************************************
2224  *
2225  *  Workaround for SmartSpeed on 82541 and 82547 controllers
2226  *
2227  **********************************************************************/
2228 static void
2229 lem_smartspeed(struct adapter *adapter)
2230 {
2231         u16 phy_tmp;
2232
2233         if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) ||
2234             adapter->hw.mac.autoneg == 0 ||
2235             (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2236                 return;
2237
2238         if (adapter->smartspeed == 0) {
2239                 /* If Master/Slave config fault is asserted twice,
2240                  * we assume back-to-back */
2241                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2242                 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2243                         return;
2244                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2245                 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2246                         e1000_read_phy_reg(&adapter->hw,
2247                             PHY_1000T_CTRL, &phy_tmp);
2248                         if(phy_tmp & CR_1000T_MS_ENABLE) {
2249                                 phy_tmp &= ~CR_1000T_MS_ENABLE;
2250                                 e1000_write_phy_reg(&adapter->hw,
2251                                     PHY_1000T_CTRL, phy_tmp);
2252                                 adapter->smartspeed++;
2253                                 if(adapter->hw.mac.autoneg &&
2254                                    !e1000_copper_link_autoneg(&adapter->hw) &&
2255                                    !e1000_read_phy_reg(&adapter->hw,
2256                                     PHY_CONTROL, &phy_tmp)) {
2257                                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2258                                                     MII_CR_RESTART_AUTO_NEG);
2259                                         e1000_write_phy_reg(&adapter->hw,
2260                                             PHY_CONTROL, phy_tmp);
2261                                 }
2262                         }
2263                 }
2264                 return;
2265         } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2266                 /* If still no link, perhaps using 2/3 pair cable */
2267                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2268                 phy_tmp |= CR_1000T_MS_ENABLE;
2269                 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2270                 if(adapter->hw.mac.autoneg &&
2271                    !e1000_copper_link_autoneg(&adapter->hw) &&
2272                    !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2273                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2274                                     MII_CR_RESTART_AUTO_NEG);
2275                         e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2276                 }
2277         }
2278         /* Restart process after EM_SMARTSPEED_MAX iterations */
2279         if(adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2280                 adapter->smartspeed = 0;
2281 }
2282
2283 /*********************************************************************
2284  *
2285  *  Initialize the DMA Coalescing feature
2286  *
2287  **********************************************************************/
2288 static void
2289 igb_init_dmac(struct adapter *adapter, u32 pba)
2290 {
2291         device_t        dev = adapter->dev;
2292         struct e1000_hw *hw = &adapter->hw;
2293         u32             dmac, reg = ~E1000_DMACR_DMAC_EN;
2294         u16             hwm;
2295         u16             max_frame_size;
2296
2297         if (hw->mac.type == e1000_i211)
2298                 return;
2299
2300         max_frame_size = adapter->shared->isc_max_frame_size;
2301         if (hw->mac.type > e1000_82580) {
2302
2303                 if (adapter->dmac == 0) { /* Disabling it */
2304                         E1000_WRITE_REG(hw, E1000_DMACR, reg);
2305                         return;
2306                 } else
2307                         device_printf(dev, "DMA Coalescing enabled\n");
2308
2309                 /* Set starting threshold */
2310                 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
2311
2312                 hwm = 64 * pba - max_frame_size / 16;
2313                 if (hwm < 64 * (pba - 6))
2314                         hwm = 64 * (pba - 6);
2315                 reg = E1000_READ_REG(hw, E1000_FCRTC);
2316                 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
2317                 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
2318                     & E1000_FCRTC_RTH_COAL_MASK);
2319                 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
2320
2321
2322                 dmac = pba - max_frame_size / 512;
2323                 if (dmac < pba - 10)
2324                         dmac = pba - 10;
2325                 reg = E1000_READ_REG(hw, E1000_DMACR);
2326                 reg &= ~E1000_DMACR_DMACTHR_MASK;
2327                 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT)
2328                     & E1000_DMACR_DMACTHR_MASK);
2329
2330                 /* transition to L0x or L1 if available..*/
2331                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
2332
2333                 /* Check if status is 2.5Gb backplane connection
2334                 * before configuration of watchdog timer, which is
2335                 * in msec values in 12.8usec intervals
2336                 * watchdog timer= msec values in 32usec intervals
2337                 * for non 2.5Gb connection
2338                 */
2339                 if (hw->mac.type == e1000_i354) {
2340                         int status = E1000_READ_REG(hw, E1000_STATUS);
2341                         if ((status & E1000_STATUS_2P5_SKU) &&
2342                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2343                                 reg |= ((adapter->dmac * 5) >> 6);
2344                         else
2345                                 reg |= (adapter->dmac >> 5);
2346                 } else {
2347                         reg |= (adapter->dmac >> 5);
2348                 }
2349
2350                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2351
2352                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
2353
2354                 /* Set the interval before transition */
2355                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
2356                 if (hw->mac.type == e1000_i350)
2357                         reg |= IGB_DMCTLX_DCFLUSH_DIS;
2358                 /*
2359                 ** in 2.5Gb connection, TTLX unit is 0.4 usec
2360                 ** which is 0x4*2 = 0xA. But delay is still 4 usec
2361                 */
2362                 if (hw->mac.type == e1000_i354) {
2363                         int status = E1000_READ_REG(hw, E1000_STATUS);
2364                         if ((status & E1000_STATUS_2P5_SKU) &&
2365                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2366                                 reg |= 0xA;
2367                         else
2368                                 reg |= 0x4;
2369                 } else {
2370                         reg |= 0x4;
2371                 }
2372
2373                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
2374
2375                 /* free space in tx packet buffer to wake from DMA coal */
2376                 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE -
2377                     (2 * max_frame_size)) >> 6);
2378
2379                 /* make low power state decision controlled by DMA coal */
2380                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2381                 reg &= ~E1000_PCIEMISC_LX_DECISION;
2382                 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
2383
2384         } else if (hw->mac.type == e1000_82580) {
2385                 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2386                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
2387                     reg & ~E1000_PCIEMISC_LX_DECISION);
2388                 E1000_WRITE_REG(hw, E1000_DMACR, 0);
2389         }
2390 }
2391
2392 /*********************************************************************
2393  *
2394  *  Initialize the hardware to a configuration as specified by the
2395  *  adapter structure.
2396  *
2397  **********************************************************************/
2398 static void
2399 em_reset(if_ctx_t ctx)
2400 {
2401         device_t dev = iflib_get_dev(ctx);
2402         struct adapter *adapter = iflib_get_softc(ctx);
2403         struct ifnet *ifp = iflib_get_ifp(ctx);
2404         struct e1000_hw *hw = &adapter->hw;
2405         u16 rx_buffer_size;
2406         u32 pba;
2407
2408         INIT_DEBUGOUT("em_reset: begin");
2409         /* Let the firmware know the OS is in control */
2410         em_get_hw_control(adapter);
2411
2412         /* Set up smart power down as default off on newer adapters. */
2413         if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2414             hw->mac.type == e1000_82572)) {
2415                 u16 phy_tmp = 0;
2416
2417                 /* Speed up time to link by disabling smart power down. */
2418                 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2419                 phy_tmp &= ~IGP02E1000_PM_SPD;
2420                 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2421         }
2422
2423         /*
2424          * Packet Buffer Allocation (PBA)
2425          * Writing PBA sets the receive portion of the buffer
2426          * the remainder is used for the transmit buffer.
2427          */
2428         switch (hw->mac.type) {
2429         /* Total Packet Buffer on these is 48K */
2430         case e1000_82571:
2431         case e1000_82572:
2432         case e1000_80003es2lan:
2433                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2434                 break;
2435         case e1000_82573: /* 82573: Total Packet Buffer is 32K */
2436                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2437                 break;
2438         case e1000_82574:
2439         case e1000_82583:
2440                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2441                 break;
2442         case e1000_ich8lan:
2443                 pba = E1000_PBA_8K;
2444                 break;
2445         case e1000_ich9lan:
2446         case e1000_ich10lan:
2447                 /* Boost Receive side for jumbo frames */
2448                 if (adapter->hw.mac.max_frame_size > 4096)
2449                         pba = E1000_PBA_14K;
2450                 else
2451                         pba = E1000_PBA_10K;
2452                 break;
2453         case e1000_pchlan:
2454         case e1000_pch2lan:
2455         case e1000_pch_lpt:
2456         case e1000_pch_spt:
2457         case e1000_pch_cnp:
2458                 pba = E1000_PBA_26K;
2459                 break;
2460         case e1000_82575:
2461                 pba = E1000_PBA_32K;
2462                 break;
2463         case e1000_82576:
2464         case e1000_vfadapt:
2465                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2466                 pba &= E1000_RXPBS_SIZE_MASK_82576;
2467                 break;
2468         case e1000_82580:
2469         case e1000_i350:
2470         case e1000_i354:
2471         case e1000_vfadapt_i350:
2472                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2473                 pba = e1000_rxpbs_adjust_82580(pba);
2474                 break;
2475         case e1000_i210:
2476         case e1000_i211:
2477                 pba = E1000_PBA_34K;
2478                 break;
2479         default:
2480                 if (adapter->hw.mac.max_frame_size > 8192)
2481                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2482                 else
2483                         pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2484         }
2485
2486         /* Special needs in case of Jumbo frames */
2487         if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) {
2488                 u32 tx_space, min_tx, min_rx;
2489                 pba = E1000_READ_REG(hw, E1000_PBA);
2490                 tx_space = pba >> 16;
2491                 pba &= 0xffff;
2492                 min_tx = (adapter->hw.mac.max_frame_size +
2493                     sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
2494                 min_tx = roundup2(min_tx, 1024);
2495                 min_tx >>= 10;
2496                 min_rx = adapter->hw.mac.max_frame_size;
2497                 min_rx = roundup2(min_rx, 1024);
2498                 min_rx >>= 10;
2499                 if (tx_space < min_tx &&
2500                     ((min_tx - tx_space) < pba)) {
2501                         pba = pba - (min_tx - tx_space);
2502                         /*
2503                          * if short on rx space, rx wins
2504                          * and must trump tx adjustment
2505                          */
2506                         if (pba < min_rx)
2507                                 pba = min_rx;
2508                 }
2509                 E1000_WRITE_REG(hw, E1000_PBA, pba);
2510         }
2511
2512         if (hw->mac.type < igb_mac_min)
2513                 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
2514
2515         INIT_DEBUGOUT1("em_reset: pba=%dK",pba);
2516
2517         /*
2518          * These parameters control the automatic generation (Tx) and
2519          * response (Rx) to Ethernet PAUSE frames.
2520          * - High water mark should allow for at least two frames to be
2521          *   received after sending an XOFF.
2522          * - Low water mark works best when it is very near the high water mark.
2523          *   This allows the receiver to restart by sending XON when it has
2524          *   drained a bit. Here we use an arbitrary value of 1500 which will
2525          *   restart after one full frame is pulled from the buffer. There
2526          *   could be several smaller frames in the buffer and if so they will
2527          *   not trigger the XON until their total number reduces the buffer
2528          *   by 1500.
2529          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2530          */
2531         rx_buffer_size = (pba & 0xffff) << 10;
2532         hw->fc.high_water = rx_buffer_size -
2533             roundup2(adapter->hw.mac.max_frame_size, 1024);
2534         hw->fc.low_water = hw->fc.high_water - 1500;
2535
2536         if (adapter->fc) /* locally set flow control value? */
2537                 hw->fc.requested_mode = adapter->fc;
2538         else
2539                 hw->fc.requested_mode = e1000_fc_full;
2540
2541         if (hw->mac.type == e1000_80003es2lan)
2542                 hw->fc.pause_time = 0xFFFF;
2543         else
2544                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
2545
2546         hw->fc.send_xon = TRUE;
2547
2548         /* Device specific overrides/settings */
2549         switch (hw->mac.type) {
2550         case e1000_pchlan:
2551                 /* Workaround: no TX flow ctrl for PCH */
2552                 hw->fc.requested_mode = e1000_fc_rx_pause;
2553                 hw->fc.pause_time = 0xFFFF; /* override */
2554                 if (if_getmtu(ifp) > ETHERMTU) {
2555                         hw->fc.high_water = 0x3500;
2556                         hw->fc.low_water = 0x1500;
2557                 } else {
2558                         hw->fc.high_water = 0x5000;
2559                         hw->fc.low_water = 0x3000;
2560                 }
2561                 hw->fc.refresh_time = 0x1000;
2562                 break;
2563         case e1000_pch2lan:
2564         case e1000_pch_lpt:
2565         case e1000_pch_spt:
2566         case e1000_pch_cnp:
2567                 hw->fc.high_water = 0x5C20;
2568                 hw->fc.low_water = 0x5048;
2569                 hw->fc.pause_time = 0x0650;
2570                 hw->fc.refresh_time = 0x0400;
2571                 /* Jumbos need adjusted PBA */
2572                 if (if_getmtu(ifp) > ETHERMTU)
2573                         E1000_WRITE_REG(hw, E1000_PBA, 12);
2574                 else
2575                         E1000_WRITE_REG(hw, E1000_PBA, 26);
2576                 break;
2577         case e1000_82575:
2578         case e1000_82576:
2579                 /* 8-byte granularity */
2580                 hw->fc.low_water = hw->fc.high_water - 8;
2581                 break;
2582         case e1000_82580:
2583         case e1000_i350:
2584         case e1000_i354:
2585         case e1000_i210:
2586         case e1000_i211:
2587         case e1000_vfadapt:
2588         case e1000_vfadapt_i350:
2589                 /* 16-byte granularity */
2590                 hw->fc.low_water = hw->fc.high_water - 16;
2591                 break;
2592         case e1000_ich9lan:
2593         case e1000_ich10lan:
2594                 if (if_getmtu(ifp) > ETHERMTU) {
2595                         hw->fc.high_water = 0x2800;
2596                         hw->fc.low_water = hw->fc.high_water - 8;
2597                         break;
2598                 }
2599                 /* FALLTHROUGH */
2600         default:
2601                 if (hw->mac.type == e1000_80003es2lan)
2602                         hw->fc.pause_time = 0xFFFF;
2603                 break;
2604         }
2605
2606         /* Issue a global reset */
2607         e1000_reset_hw(hw);
2608         if (adapter->hw.mac.type >= igb_mac_min) {
2609                 E1000_WRITE_REG(hw, E1000_WUC, 0);
2610         } else {
2611                 E1000_WRITE_REG(hw, E1000_WUFC, 0);
2612                 em_disable_aspm(adapter);
2613         }
2614         if (adapter->flags & IGB_MEDIA_RESET) {
2615                 e1000_setup_init_funcs(hw, TRUE);
2616                 e1000_get_bus_info(hw);
2617                 adapter->flags &= ~IGB_MEDIA_RESET;
2618         }
2619         /* and a re-init */
2620         if (e1000_init_hw(hw) < 0) {
2621                 device_printf(dev, "Hardware Initialization Failed\n");
2622                 return;
2623         }
2624         if (adapter->hw.mac.type >= igb_mac_min)
2625                 igb_init_dmac(adapter, pba);
2626
2627         E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2628         e1000_get_phy_info(hw);
2629         e1000_check_for_link(hw);
2630 }
2631
2632 /*
2633  * Initialise the RSS mapping for NICs that support multiple transmit/
2634  * receive rings.
2635  */
2636
2637 #define RSSKEYLEN 10
2638 static void
2639 em_initialize_rss_mapping(struct adapter *adapter)
2640 {
2641         uint8_t  rss_key[4 * RSSKEYLEN];
2642         uint32_t reta = 0;
2643         struct e1000_hw *hw = &adapter->hw;
2644         int i;
2645
2646         /*
2647          * Configure RSS key
2648          */
2649         arc4rand(rss_key, sizeof(rss_key), 0);
2650         for (i = 0; i < RSSKEYLEN; ++i) {
2651                 uint32_t rssrk = 0;
2652
2653                 rssrk = EM_RSSRK_VAL(rss_key, i);
2654                 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2655         }
2656
2657         /*
2658          * Configure RSS redirect table in following fashion:
2659          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2660          */
2661         for (i = 0; i < sizeof(reta); ++i) {
2662                 uint32_t q;
2663
2664                 q = (i % adapter->rx_num_queues) << 7;
2665                 reta |= q << (8 * i);
2666         }
2667
2668         for (i = 0; i < 32; ++i)
2669                 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2670
2671         E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2672                         E1000_MRQC_RSS_FIELD_IPV4_TCP |
2673                         E1000_MRQC_RSS_FIELD_IPV4 |
2674                         E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2675                         E1000_MRQC_RSS_FIELD_IPV6_EX |
2676                         E1000_MRQC_RSS_FIELD_IPV6);
2677 }
2678
2679 static void
2680 igb_initialize_rss_mapping(struct adapter *adapter)
2681 {
2682         struct e1000_hw *hw = &adapter->hw;
2683         int i;
2684         int queue_id;
2685         u32 reta;
2686         u32 rss_key[10], mrqc, shift = 0;
2687
2688         /* XXX? */
2689         if (adapter->hw.mac.type == e1000_82575)
2690                 shift = 6;
2691
2692         /*
2693          * The redirection table controls which destination
2694          * queue each bucket redirects traffic to.
2695          * Each DWORD represents four queues, with the LSB
2696          * being the first queue in the DWORD.
2697          *
2698          * This just allocates buckets to queues using round-robin
2699          * allocation.
2700          *
2701          * NOTE: It Just Happens to line up with the default
2702          * RSS allocation method.
2703          */
2704
2705         /* Warning FM follows */
2706         reta = 0;
2707         for (i = 0; i < 128; i++) {
2708 #ifdef RSS
2709                 queue_id = rss_get_indirection_to_bucket(i);
2710                 /*
2711                  * If we have more queues than buckets, we'll
2712                  * end up mapping buckets to a subset of the
2713                  * queues.
2714                  *
2715                  * If we have more buckets than queues, we'll
2716                  * end up instead assigning multiple buckets
2717                  * to queues.
2718                  *
2719                  * Both are suboptimal, but we need to handle
2720                  * the case so we don't go out of bounds
2721                  * indexing arrays and such.
2722                  */
2723                 queue_id = queue_id % adapter->rx_num_queues;
2724 #else
2725                 queue_id = (i % adapter->rx_num_queues);
2726 #endif
2727                 /* Adjust if required */
2728                 queue_id = queue_id << shift;
2729
2730                 /*
2731                  * The low 8 bits are for hash value (n+0);
2732                  * The next 8 bits are for hash value (n+1), etc.
2733                  */
2734                 reta = reta >> 8;
2735                 reta = reta | ( ((uint32_t) queue_id) << 24);
2736                 if ((i & 3) == 3) {
2737                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2738                         reta = 0;
2739                 }
2740         }
2741
2742         /* Now fill in hash table */
2743
2744         /*
2745          * MRQC: Multiple Receive Queues Command
2746          * Set queuing to RSS control, number depends on the device.
2747          */
2748         mrqc = E1000_MRQC_ENABLE_RSS_8Q;
2749
2750 #ifdef RSS
2751         /* XXX ew typecasting */
2752         rss_getkey((uint8_t *) &rss_key);
2753 #else
2754         arc4rand(&rss_key, sizeof(rss_key), 0);
2755 #endif
2756         for (i = 0; i < 10; i++)
2757                 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]);
2758
2759         /*
2760          * Configure the RSS fields to hash upon.
2761          */
2762         mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2763             E1000_MRQC_RSS_FIELD_IPV4_TCP);
2764         mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2765             E1000_MRQC_RSS_FIELD_IPV6_TCP);
2766         mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2767             E1000_MRQC_RSS_FIELD_IPV6_UDP);
2768         mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2769             E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2770
2771         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2772 }
2773
2774 /*********************************************************************
2775  *
2776  *  Setup networking device structure and register interface media.
2777  *
2778  **********************************************************************/
2779 static int
2780 em_setup_interface(if_ctx_t ctx)
2781 {
2782         struct ifnet *ifp = iflib_get_ifp(ctx);
2783         struct adapter *adapter = iflib_get_softc(ctx);
2784         if_softc_ctx_t scctx = adapter->shared;
2785
2786         INIT_DEBUGOUT("em_setup_interface: begin");
2787
2788         /* Single Queue */
2789         if (adapter->tx_num_queues == 1) {
2790                 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
2791                 if_setsendqready(ifp);
2792         }
2793
2794         /*
2795          * Specify the media types supported by this adapter and register
2796          * callbacks to update media and link information
2797          */
2798         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
2799             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
2800                 u_char fiber_type = IFM_1000_SX;        /* default type */
2801
2802                 if (adapter->hw.mac.type == e1000_82545)
2803                         fiber_type = IFM_1000_LX;
2804                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
2805                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2806         } else {
2807                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2808                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2809                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2810                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2811                 if (adapter->hw.phy.type != e1000_phy_ife) {
2812                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2813                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2814                 }
2815         }
2816         ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2817         ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO);
2818         return (0);
2819 }
2820
2821 static int
2822 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
2823 {
2824         struct adapter *adapter = iflib_get_softc(ctx);
2825         if_softc_ctx_t scctx = adapter->shared;
2826         int error = E1000_SUCCESS;
2827         struct em_tx_queue *que;
2828         int i, j;
2829
2830         MPASS(adapter->tx_num_queues > 0);
2831         MPASS(adapter->tx_num_queues == ntxqsets);
2832
2833         /* First allocate the top level queue structs */
2834         if (!(adapter->tx_queues =
2835             (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
2836             adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2837                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2838                 return(ENOMEM);
2839         }
2840
2841         for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) {
2842                 /* Set up some basics */
2843
2844                 struct tx_ring *txr = &que->txr;
2845                 txr->adapter = que->adapter = adapter;
2846                 que->me = txr->me =  i;
2847
2848                 /* Allocate report status array */
2849                 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2850                         device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n");
2851                         error = ENOMEM;
2852                         goto fail;
2853                 }
2854                 for (j = 0; j < scctx->isc_ntxd[0]; j++)
2855                         txr->tx_rsq[j] = QIDX_INVALID;
2856                 /* get the virtual and physical address of the hardware queues */
2857                 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
2858                 txr->tx_paddr = paddrs[i*ntxqs];
2859         }
2860
2861         if (bootverbose)
2862                 device_printf(iflib_get_dev(ctx),
2863                     "allocated for %d tx_queues\n", adapter->tx_num_queues);
2864         return (0);
2865 fail:
2866         em_if_queues_free(ctx);
2867         return (error);
2868 }
2869
2870 static int
2871 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
2872 {
2873         struct adapter *adapter = iflib_get_softc(ctx);
2874         int error = E1000_SUCCESS;
2875         struct em_rx_queue *que;
2876         int i;
2877
2878         MPASS(adapter->rx_num_queues > 0);
2879         MPASS(adapter->rx_num_queues == nrxqsets);
2880
2881         /* First allocate the top level queue structs */
2882         if (!(adapter->rx_queues =
2883             (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
2884             adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2885                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2886                 error = ENOMEM;
2887                 goto fail;
2888         }
2889
2890         for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) {
2891                 /* Set up some basics */
2892                 struct rx_ring *rxr = &que->rxr;
2893                 rxr->adapter = que->adapter = adapter;
2894                 rxr->que = que;
2895                 que->me = rxr->me =  i;
2896
2897                 /* get the virtual and physical address of the hardware queues */
2898                 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
2899                 rxr->rx_paddr = paddrs[i*nrxqs];
2900         }
2901
2902         if (bootverbose)
2903                 device_printf(iflib_get_dev(ctx),
2904                     "allocated for %d rx_queues\n", adapter->rx_num_queues);
2905
2906         return (0);
2907 fail:
2908         em_if_queues_free(ctx);
2909         return (error);
2910 }
2911
2912 static void
2913 em_if_queues_free(if_ctx_t ctx)
2914 {
2915         struct adapter *adapter = iflib_get_softc(ctx);
2916         struct em_tx_queue *tx_que = adapter->tx_queues;
2917         struct em_rx_queue *rx_que = adapter->rx_queues;
2918
2919         if (tx_que != NULL) {
2920                 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
2921                         struct tx_ring *txr = &tx_que->txr;
2922                         if (txr->tx_rsq == NULL)
2923                                 break;
2924
2925                         free(txr->tx_rsq, M_DEVBUF);
2926                         txr->tx_rsq = NULL;
2927                 }
2928                 free(adapter->tx_queues, M_DEVBUF);
2929                 adapter->tx_queues = NULL;
2930         }
2931
2932         if (rx_que != NULL) {
2933                 free(adapter->rx_queues, M_DEVBUF);
2934                 adapter->rx_queues = NULL;
2935         }
2936
2937         em_release_hw_control(adapter);
2938
2939         if (adapter->mta != NULL) {
2940                 free(adapter->mta, M_DEVBUF);
2941         }
2942 }
2943
2944 /*********************************************************************
2945  *
2946  *  Enable transmit unit.
2947  *
2948  **********************************************************************/
2949 static void
2950 em_initialize_transmit_unit(if_ctx_t ctx)
2951 {
2952         struct adapter *adapter = iflib_get_softc(ctx);
2953         if_softc_ctx_t scctx = adapter->shared;
2954         struct em_tx_queue *que;
2955         struct tx_ring  *txr;
2956         struct e1000_hw *hw = &adapter->hw;
2957         u32 tctl, txdctl = 0, tarc, tipg = 0;
2958
2959         INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
2960
2961         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
2962                 u64 bus_addr;
2963                 caddr_t offp, endp;
2964
2965                 que = &adapter->tx_queues[i];
2966                 txr = &que->txr;
2967                 bus_addr = txr->tx_paddr;
2968
2969                 /* Clear checksum offload context. */
2970                 offp = (caddr_t)&txr->csum_flags;
2971                 endp = (caddr_t)(txr + 1);
2972                 bzero(offp, endp - offp);
2973
2974                 /* Base and Len of TX Ring */
2975                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
2976                     scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
2977                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
2978                     (u32)(bus_addr >> 32));
2979                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
2980                     (u32)bus_addr);
2981                 /* Init the HEAD/TAIL indices */
2982                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
2983                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
2984
2985                 HW_DEBUGOUT2("Base = %x, Length = %x\n",
2986                     E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)),
2987                     E1000_READ_REG(&adapter->hw, E1000_TDLEN(i)));
2988
2989                 txdctl = 0; /* clear txdctl */
2990                 txdctl |= 0x1f; /* PTHRESH */
2991                 txdctl |= 1 << 8; /* HTHRESH */
2992                 txdctl |= 1 << 16;/* WTHRESH */
2993                 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
2994                 txdctl |= E1000_TXDCTL_GRAN;
2995                 txdctl |= 1 << 25; /* LWTHRESH */
2996
2997                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
2998         }
2999
3000         /* Set the default values for the Tx Inter Packet Gap timer */
3001         switch (adapter->hw.mac.type) {
3002         case e1000_80003es2lan:
3003                 tipg = DEFAULT_82543_TIPG_IPGR1;
3004                 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
3005                     E1000_TIPG_IPGR2_SHIFT;
3006                 break;
3007         case e1000_82542:
3008                 tipg = DEFAULT_82542_TIPG_IPGT;
3009                 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3010                 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3011                 break;
3012         default:
3013                 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
3014                     (adapter->hw.phy.media_type ==
3015                     e1000_media_type_internal_serdes))
3016                         tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
3017                 else
3018                         tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
3019                 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3020                 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3021         }
3022
3023         E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
3024         E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value);
3025
3026         if(adapter->hw.mac.type >= e1000_82540)
3027                 E1000_WRITE_REG(&adapter->hw, E1000_TADV,
3028                     adapter->tx_abs_int_delay.value);
3029
3030         if ((adapter->hw.mac.type == e1000_82571) ||
3031             (adapter->hw.mac.type == e1000_82572)) {
3032                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3033                 tarc |= TARC_SPEED_MODE_BIT;
3034                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3035         } else if (adapter->hw.mac.type == e1000_80003es2lan) {
3036                 /* errata: program both queues to unweighted RR */
3037                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3038                 tarc |= 1;
3039                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3040                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
3041                 tarc |= 1;
3042                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
3043         } else if (adapter->hw.mac.type == e1000_82574) {
3044                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3045                 tarc |= TARC_ERRATA_BIT;
3046                 if ( adapter->tx_num_queues > 1) {
3047                         tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
3048                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3049                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
3050                 } else
3051                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3052         }
3053
3054         if (adapter->tx_int_delay.value > 0)
3055                 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3056
3057         /* Program the Transmit Control Register */
3058         tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
3059         tctl &= ~E1000_TCTL_CT;
3060         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
3061                    (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
3062
3063         if (adapter->hw.mac.type >= e1000_82571)
3064                 tctl |= E1000_TCTL_MULR;
3065
3066         /* This write will effectively turn on the transmit unit. */
3067         E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
3068
3069         /* SPT and KBL errata workarounds */
3070         if (hw->mac.type == e1000_pch_spt) {
3071                 u32 reg;
3072                 reg = E1000_READ_REG(hw, E1000_IOSFPC);
3073                 reg |= E1000_RCTL_RDMTS_HEX;
3074                 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
3075                 /* i218-i219 Specification Update 1.5.4.5 */
3076                 reg = E1000_READ_REG(hw, E1000_TARC(0));
3077                 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3078                 reg |= E1000_TARC0_CB_MULTIQ_2_REQ;
3079                 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3080         }
3081 }
3082
3083 /*********************************************************************
3084  *
3085  *  Enable receive unit.
3086  *
3087  **********************************************************************/
3088
3089 static void
3090 em_initialize_receive_unit(if_ctx_t ctx)
3091 {
3092         struct adapter *adapter = iflib_get_softc(ctx);
3093         if_softc_ctx_t scctx = adapter->shared;
3094         struct ifnet *ifp = iflib_get_ifp(ctx);
3095         struct e1000_hw *hw = &adapter->hw;
3096         struct em_rx_queue *que;
3097         int i;
3098         u32 rctl, rxcsum, rfctl;
3099
3100         INIT_DEBUGOUT("em_initialize_receive_units: begin");
3101
3102         /*
3103          * Make sure receives are disabled while setting
3104          * up the descriptor ring
3105          */
3106         rctl = E1000_READ_REG(hw, E1000_RCTL);
3107         /* Do not disable if ever enabled on this hardware */
3108         if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
3109                 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3110
3111         /* Setup the Receive Control Register */
3112         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3113         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3114             E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3115             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3116
3117         /* Do not store bad packets */
3118         rctl &= ~E1000_RCTL_SBP;
3119
3120         /* Enable Long Packet receive */
3121         if (if_getmtu(ifp) > ETHERMTU)
3122                 rctl |= E1000_RCTL_LPE;
3123         else
3124                 rctl &= ~E1000_RCTL_LPE;
3125
3126         /* Strip the CRC */
3127         if (!em_disable_crc_stripping)
3128                 rctl |= E1000_RCTL_SECRC;
3129
3130         if (adapter->hw.mac.type >= e1000_82540) {
3131                 E1000_WRITE_REG(&adapter->hw, E1000_RADV,
3132                             adapter->rx_abs_int_delay.value);
3133
3134                 /*
3135                  * Set the interrupt throttling rate. Value is calculated
3136                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
3137                  */
3138                 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
3139         }
3140         E1000_WRITE_REG(&adapter->hw, E1000_RDTR,
3141             adapter->rx_int_delay.value);
3142
3143         /* Use extended rx descriptor formats */
3144         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3145         rfctl |= E1000_RFCTL_EXTEN;
3146         /*
3147          * When using MSI-X interrupts we need to throttle
3148          * using the EITR register (82574 only)
3149          */
3150         if (hw->mac.type == e1000_82574) {
3151                 for (int i = 0; i < 4; i++)
3152                         E1000_WRITE_REG(hw, E1000_EITR_82574(i),
3153                             DEFAULT_ITR);
3154                 /* Disable accelerated acknowledge */
3155                 rfctl |= E1000_RFCTL_ACK_DIS;
3156         }
3157         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3158
3159         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
3160         if (if_getcapenable(ifp) & IFCAP_RXCSUM &&
3161             adapter->hw.mac.type >= e1000_82543) {
3162                 if (adapter->tx_num_queues > 1) {
3163                         if (adapter->hw.mac.type >= igb_mac_min) {
3164                                 rxcsum |= E1000_RXCSUM_PCSD;
3165                                 if (hw->mac.type != e1000_82575)
3166                                         rxcsum |= E1000_RXCSUM_CRCOFL;
3167                         } else
3168                                 rxcsum |= E1000_RXCSUM_TUOFL |
3169                                         E1000_RXCSUM_IPOFL |
3170                                         E1000_RXCSUM_PCSD;
3171                 } else {
3172                         if (adapter->hw.mac.type >= igb_mac_min)
3173                                 rxcsum |= E1000_RXCSUM_IPPCSE;
3174                         else
3175                                 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
3176                         if (adapter->hw.mac.type > e1000_82575)
3177                                 rxcsum |= E1000_RXCSUM_CRCOFL;
3178                 }
3179         } else
3180                 rxcsum &= ~E1000_RXCSUM_TUOFL;
3181
3182         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
3183
3184         if (adapter->rx_num_queues > 1) {
3185                 if (adapter->hw.mac.type >= igb_mac_min)
3186                         igb_initialize_rss_mapping(adapter);
3187                 else
3188                         em_initialize_rss_mapping(adapter);
3189         }
3190
3191         /*
3192          * XXX TEMPORARY WORKAROUND: on some systems with 82573
3193          * long latencies are observed, like Lenovo X60. This
3194          * change eliminates the problem, but since having positive
3195          * values in RDTR is a known source of problems on other
3196          * platforms another solution is being sought.
3197          */
3198         if (hw->mac.type == e1000_82573)
3199                 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
3200
3201         for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3202                 struct rx_ring *rxr = &que->rxr;
3203                 /* Setup the Base and Length of the Rx Descriptor Ring */
3204                 u64 bus_addr = rxr->rx_paddr;
3205 #if 0
3206                 u32 rdt = adapter->rx_num_queues -1;  /* default */
3207 #endif
3208
3209                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3210                     scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
3211                 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
3212                 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
3213                 /* Setup the Head and Tail Descriptor Pointers */
3214                 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
3215                 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
3216         }
3217
3218         /*
3219          * Set PTHRESH for improved jumbo performance
3220          * According to 10.2.5.11 of Intel 82574 Datasheet,
3221          * RXDCTL(1) is written whenever RXDCTL(0) is written.
3222          * Only write to RXDCTL(1) if there is a need for different
3223          * settings.
3224          */
3225
3226         if (((adapter->hw.mac.type == e1000_ich9lan) ||
3227             (adapter->hw.mac.type == e1000_pch2lan) ||
3228             (adapter->hw.mac.type == e1000_ich10lan)) &&
3229             (if_getmtu(ifp) > ETHERMTU)) {
3230                 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
3231                 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
3232         } else if (adapter->hw.mac.type == e1000_82574) {
3233                 for (int i = 0; i < adapter->rx_num_queues; i++) {
3234                         u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3235                         rxdctl |= 0x20; /* PTHRESH */
3236                         rxdctl |= 4 << 8; /* HTHRESH */
3237                         rxdctl |= 4 << 16;/* WTHRESH */
3238                         rxdctl |= 1 << 24; /* Switch to granularity */
3239                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3240                 }
3241         } else if (adapter->hw.mac.type >= igb_mac_min) {
3242                 u32 psize, srrctl = 0;
3243
3244                 if (if_getmtu(ifp) > ETHERMTU) {
3245                         /* Set maximum packet len */
3246                         if (adapter->rx_mbuf_sz <= 4096) {
3247                                 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3248                                 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3249                         } else if (adapter->rx_mbuf_sz > 4096) {
3250                                 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3251                                 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3252                         }
3253                         psize = scctx->isc_max_frame_size;
3254                         /* are we on a vlan? */
3255                         if (ifp->if_vlantrunk != NULL)
3256                                 psize += VLAN_TAG_SIZE;
3257                         E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
3258                 } else {
3259                         srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3260                         rctl |= E1000_RCTL_SZ_2048;
3261                 }
3262
3263                 /*
3264                  * If TX flow control is disabled and there's >1 queue defined,
3265                  * enable DROP.
3266                  *
3267                  * This drops frames rather than hanging the RX MAC for all queues.
3268                  */
3269                 if ((adapter->rx_num_queues > 1) &&
3270                     (adapter->fc == e1000_fc_none ||
3271                      adapter->fc == e1000_fc_rx_pause)) {
3272                         srrctl |= E1000_SRRCTL_DROP_EN;
3273                 }
3274                         /* Setup the Base and Length of the Rx Descriptor Rings */
3275                 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3276                         struct rx_ring *rxr = &que->rxr;
3277                         u64 bus_addr = rxr->rx_paddr;
3278                         u32 rxdctl;
3279
3280 #ifdef notyet
3281                         /* Configure for header split? -- ignore for now */
3282                         rxr->hdr_split = igb_header_split;
3283 #else
3284                         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3285 #endif
3286
3287                         E1000_WRITE_REG(hw, E1000_RDLEN(i),
3288                                         scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3289                         E1000_WRITE_REG(hw, E1000_RDBAH(i),
3290                                         (uint32_t)(bus_addr >> 32));
3291                         E1000_WRITE_REG(hw, E1000_RDBAL(i),
3292                                         (uint32_t)bus_addr);
3293                         E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3294                         /* Enable this Queue */
3295                         rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3296                         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3297                         rxdctl &= 0xFFF00000;
3298                         rxdctl |= IGB_RX_PTHRESH;
3299                         rxdctl |= IGB_RX_HTHRESH << 8;
3300                         rxdctl |= IGB_RX_WTHRESH << 16;
3301                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3302                 }
3303         } else if (adapter->hw.mac.type >= e1000_pch2lan) {
3304                 if (if_getmtu(ifp) > ETHERMTU)
3305                         e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
3306                 else
3307                         e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
3308         }
3309
3310         /* Make sure VLAN Filters are off */
3311         rctl &= ~E1000_RCTL_VFE;
3312
3313         if (adapter->hw.mac.type < igb_mac_min) {
3314                 if (adapter->rx_mbuf_sz == MCLBYTES)
3315                         rctl |= E1000_RCTL_SZ_2048;
3316                 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE)
3317                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3318                 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE)
3319                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3320
3321                 /* ensure we clear use DTYPE of 00 here */
3322                 rctl &= ~0x00000C00;
3323         }
3324
3325         /* Write out the settings */
3326         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3327
3328         return;
3329 }
3330
3331 static void
3332 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3333 {
3334         struct adapter *adapter = iflib_get_softc(ctx);
3335         u32 index, bit;
3336
3337         index = (vtag >> 5) & 0x7F;
3338         bit = vtag & 0x1F;
3339         adapter->shadow_vfta[index] |= (1 << bit);
3340         ++adapter->num_vlans;
3341 }
3342
3343 static void
3344 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3345 {
3346         struct adapter *adapter = iflib_get_softc(ctx);
3347         u32 index, bit;
3348
3349         index = (vtag >> 5) & 0x7F;
3350         bit = vtag & 0x1F;
3351         adapter->shadow_vfta[index] &= ~(1 << bit);
3352         --adapter->num_vlans;
3353 }
3354
3355 static void
3356 em_setup_vlan_hw_support(struct adapter *adapter)
3357 {
3358         struct e1000_hw *hw = &adapter->hw;
3359         u32 reg;
3360
3361         /*
3362          * We get here thru init_locked, meaning
3363          * a soft reset, this has already cleared
3364          * the VFTA and other state, so if there
3365          * have been no vlan's registered do nothing.
3366          */
3367         if (adapter->num_vlans == 0)
3368                 return;
3369
3370         /*
3371          * A soft reset zero's out the VFTA, so
3372          * we need to repopulate it now.
3373          */
3374         for (int i = 0; i < EM_VFTA_SIZE; i++)
3375                 if (adapter->shadow_vfta[i] != 0)
3376                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
3377                             i, adapter->shadow_vfta[i]);
3378
3379         reg = E1000_READ_REG(hw, E1000_CTRL);
3380         reg |= E1000_CTRL_VME;
3381         E1000_WRITE_REG(hw, E1000_CTRL, reg);
3382
3383         /* Enable the Filter Table */
3384         reg = E1000_READ_REG(hw, E1000_RCTL);
3385         reg &= ~E1000_RCTL_CFIEN;
3386         reg |= E1000_RCTL_VFE;
3387         E1000_WRITE_REG(hw, E1000_RCTL, reg);
3388 }
3389
3390 static void
3391 em_if_enable_intr(if_ctx_t ctx)
3392 {
3393         struct adapter *adapter = iflib_get_softc(ctx);
3394         struct e1000_hw *hw = &adapter->hw;
3395         u32 ims_mask = IMS_ENABLE_MASK;
3396
3397         if (hw->mac.type == e1000_82574) {
3398                 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK);
3399                 ims_mask |= adapter->ims;
3400         } else if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min)  {
3401                 u32 mask = (adapter->que_mask | adapter->link_mask);
3402
3403                 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask);
3404                 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask);
3405                 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask);
3406                 ims_mask = E1000_IMS_LSC;
3407         }
3408
3409         E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3410 }
3411
3412 static void
3413 em_if_disable_intr(if_ctx_t ctx)
3414 {
3415         struct adapter *adapter = iflib_get_softc(ctx);
3416         struct e1000_hw *hw = &adapter->hw;
3417
3418         if (adapter->intr_type == IFLIB_INTR_MSIX) {
3419                 if (hw->mac.type >= igb_mac_min)
3420                         E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0);
3421                 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0);
3422         }
3423         E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
3424 }
3425
3426 /*
3427  * Bit of a misnomer, what this really means is
3428  * to enable OS management of the system... aka
3429  * to disable special hardware management features
3430  */
3431 static void
3432 em_init_manageability(struct adapter *adapter)
3433 {
3434         /* A shared code workaround */
3435 #define E1000_82542_MANC2H E1000_MANC2H
3436         if (adapter->has_manage) {
3437                 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3438                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3439
3440                 /* disable hardware interception of ARP */
3441                 manc &= ~(E1000_MANC_ARP_EN);
3442
3443                 /* enable receiving management packets to the host */
3444                 manc |= E1000_MANC_EN_MNG2HOST;
3445 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3446 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3447                 manc2h |= E1000_MNG2HOST_PORT_623;
3448                 manc2h |= E1000_MNG2HOST_PORT_664;
3449                 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3450                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3451         }
3452 }
3453
3454 /*
3455  * Give control back to hardware management
3456  * controller if there is one.
3457  */
3458 static void
3459 em_release_manageability(struct adapter *adapter)
3460 {
3461         if (adapter->has_manage) {
3462                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3463
3464                 /* re-enable hardware interception of ARP */
3465                 manc |= E1000_MANC_ARP_EN;
3466                 manc &= ~E1000_MANC_EN_MNG2HOST;
3467
3468                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3469         }
3470 }
3471
3472 /*
3473  * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3474  * For ASF and Pass Through versions of f/w this means
3475  * that the driver is loaded. For AMT version type f/w
3476  * this means that the network i/f is open.
3477  */
3478 static void
3479 em_get_hw_control(struct adapter *adapter)
3480 {
3481         u32 ctrl_ext, swsm;
3482
3483         if (adapter->vf_ifp)
3484                 return;
3485
3486         if (adapter->hw.mac.type == e1000_82573) {
3487                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3488                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3489                     swsm | E1000_SWSM_DRV_LOAD);
3490                 return;
3491         }
3492         /* else */
3493         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3494         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3495             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3496 }
3497
3498 /*
3499  * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3500  * For ASF and Pass Through versions of f/w this means that
3501  * the driver is no longer loaded. For AMT versions of the
3502  * f/w this means that the network i/f is closed.
3503  */
3504 static void
3505 em_release_hw_control(struct adapter *adapter)
3506 {
3507         u32 ctrl_ext, swsm;
3508
3509         if (!adapter->has_manage)
3510                 return;
3511
3512         if (adapter->hw.mac.type == e1000_82573) {
3513                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3514                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3515                     swsm & ~E1000_SWSM_DRV_LOAD);
3516                 return;
3517         }
3518         /* else */
3519         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3520         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3521             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3522         return;
3523 }
3524
3525 static int
3526 em_is_valid_ether_addr(u8 *addr)
3527 {
3528         char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3529
3530         if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3531                 return (FALSE);
3532         }
3533
3534         return (TRUE);
3535 }
3536
3537 /*
3538 ** Parse the interface capabilities with regard
3539 ** to both system management and wake-on-lan for
3540 ** later use.
3541 */
3542 static void
3543 em_get_wakeup(if_ctx_t ctx)
3544 {
3545         struct adapter *adapter = iflib_get_softc(ctx);
3546         device_t dev = iflib_get_dev(ctx);
3547         u16 eeprom_data = 0, device_id, apme_mask;
3548
3549         adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
3550         apme_mask = EM_EEPROM_APME;
3551
3552         switch (adapter->hw.mac.type) {
3553         case e1000_82542:
3554         case e1000_82543:
3555                 break;
3556         case e1000_82544:
3557                 e1000_read_nvm(&adapter->hw,
3558                     NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3559                 apme_mask = EM_82544_APME;
3560                 break;
3561         case e1000_82546:
3562         case e1000_82546_rev_3:
3563                 if (adapter->hw.bus.func == 1) {
3564                         e1000_read_nvm(&adapter->hw,
3565                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3566                         break;
3567                 } else
3568                         e1000_read_nvm(&adapter->hw,
3569                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3570                 break;
3571         case e1000_82573:
3572         case e1000_82583:
3573                 adapter->has_amt = TRUE;
3574                 /* FALLTHROUGH */
3575         case e1000_82571:
3576         case e1000_82572:
3577         case e1000_80003es2lan:
3578                 if (adapter->hw.bus.func == 1) {
3579                         e1000_read_nvm(&adapter->hw,
3580                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3581                         break;
3582                 } else
3583                         e1000_read_nvm(&adapter->hw,
3584                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3585                 break;
3586         case e1000_ich8lan:
3587         case e1000_ich9lan:
3588         case e1000_ich10lan:
3589         case e1000_pchlan:
3590         case e1000_pch2lan:
3591         case e1000_pch_lpt:
3592         case e1000_pch_spt:
3593         case e1000_82575:       /* listing all igb devices */
3594         case e1000_82576:
3595         case e1000_82580:
3596         case e1000_i350:
3597         case e1000_i354:
3598         case e1000_i210:
3599         case e1000_i211:
3600         case e1000_vfadapt:
3601         case e1000_vfadapt_i350:
3602                 apme_mask = E1000_WUC_APME;
3603                 adapter->has_amt = TRUE;
3604                 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
3605                 break;
3606         default:
3607                 e1000_read_nvm(&adapter->hw,
3608                     NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3609                 break;
3610         }
3611         if (eeprom_data & apme_mask)
3612                 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
3613         /*
3614          * We have the eeprom settings, now apply the special cases
3615          * where the eeprom may be wrong or the board won't support
3616          * wake on lan on a particular port
3617          */
3618         device_id = pci_get_device(dev);
3619         switch (device_id) {
3620         case E1000_DEV_ID_82546GB_PCIE:
3621                 adapter->wol = 0;
3622                 break;
3623         case E1000_DEV_ID_82546EB_FIBER:
3624         case E1000_DEV_ID_82546GB_FIBER:
3625                 /* Wake events only supported on port A for dual fiber
3626                  * regardless of eeprom setting */
3627                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3628                     E1000_STATUS_FUNC_1)
3629                         adapter->wol = 0;
3630                 break;
3631         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
3632                 /* if quad port adapter, disable WoL on all but port A */
3633                 if (global_quad_port_a != 0)
3634                         adapter->wol = 0;
3635                 /* Reset for multiple quad port adapters */
3636                 if (++global_quad_port_a == 4)
3637                         global_quad_port_a = 0;
3638                 break;
3639         case E1000_DEV_ID_82571EB_FIBER:
3640                 /* Wake events only supported on port A for dual fiber
3641                  * regardless of eeprom setting */
3642                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3643                     E1000_STATUS_FUNC_1)
3644                         adapter->wol = 0;
3645                 break;
3646         case E1000_DEV_ID_82571EB_QUAD_COPPER:
3647         case E1000_DEV_ID_82571EB_QUAD_FIBER:
3648         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
3649                 /* if quad port adapter, disable WoL on all but port A */
3650                 if (global_quad_port_a != 0)
3651                         adapter->wol = 0;
3652                 /* Reset for multiple quad port adapters */
3653                 if (++global_quad_port_a == 4)
3654                         global_quad_port_a = 0;
3655                 break;
3656         }
3657         return;
3658 }
3659
3660
3661 /*
3662  * Enable PCI Wake On Lan capability
3663  */
3664 static void
3665 em_enable_wakeup(if_ctx_t ctx)
3666 {
3667         struct adapter *adapter = iflib_get_softc(ctx);
3668         device_t dev = iflib_get_dev(ctx);
3669         if_t ifp = iflib_get_ifp(ctx);
3670         int error = 0;
3671         u32 pmc, ctrl, ctrl_ext, rctl;
3672         u16 status;
3673
3674         if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
3675                 return;
3676
3677         /*
3678          * Determine type of Wakeup: note that wol
3679          * is set with all bits on by default.
3680          */
3681         if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
3682                 adapter->wol &= ~E1000_WUFC_MAG;
3683
3684         if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
3685                 adapter->wol &= ~E1000_WUFC_EX;
3686
3687         if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
3688                 adapter->wol &= ~E1000_WUFC_MC;
3689         else {
3690                 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3691                 rctl |= E1000_RCTL_MPE;
3692                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3693         }
3694
3695         if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC)))
3696                 goto pme;
3697
3698         /* Advertise the wakeup capability */
3699         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
3700         ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
3701         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
3702
3703         /* Keep the laser running on Fiber adapters */
3704         if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3705             adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
3706                 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3707                 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
3708                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext);
3709         }
3710
3711         if ((adapter->hw.mac.type == e1000_ich8lan) ||
3712             (adapter->hw.mac.type == e1000_pchlan) ||
3713             (adapter->hw.mac.type == e1000_ich9lan) ||
3714             (adapter->hw.mac.type == e1000_ich10lan))
3715                 e1000_suspend_workarounds_ich8lan(&adapter->hw);
3716
3717         if ( adapter->hw.mac.type >= e1000_pchlan) {
3718                 error = em_enable_phy_wakeup(adapter);
3719                 if (error)
3720                         goto pme;
3721         } else {
3722                 /* Enable wakeup by the MAC */
3723                 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
3724                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
3725         }
3726
3727         if (adapter->hw.phy.type == e1000_phy_igp_3)
3728                 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
3729
3730 pme:
3731         status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
3732         status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3733         if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
3734                 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3735         pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
3736
3737         return;
3738 }
3739
3740 /*
3741  * WOL in the newer chipset interfaces (pchlan)
3742  * require thing to be copied into the phy
3743  */
3744 static int
3745 em_enable_phy_wakeup(struct adapter *adapter)
3746 {
3747         struct e1000_hw *hw = &adapter->hw;
3748         u32 mreg, ret = 0;
3749         u16 preg;
3750
3751         /* copy MAC RARs to PHY RARs */
3752         e1000_copy_rx_addrs_to_phy_ich8lan(hw);
3753
3754         /* copy MAC MTA to PHY MTA */
3755         for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
3756                 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
3757                 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
3758                 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
3759                     (u16)((mreg >> 16) & 0xFFFF));
3760         }
3761
3762         /* configure PHY Rx Control register */
3763         e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg);
3764         mreg = E1000_READ_REG(hw, E1000_RCTL);
3765         if (mreg & E1000_RCTL_UPE)
3766                 preg |= BM_RCTL_UPE;
3767         if (mreg & E1000_RCTL_MPE)
3768                 preg |= BM_RCTL_MPE;
3769         preg &= ~(BM_RCTL_MO_MASK);
3770         if (mreg & E1000_RCTL_MO_3)
3771                 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
3772                                 << BM_RCTL_MO_SHIFT);
3773         if (mreg & E1000_RCTL_BAM)
3774                 preg |= BM_RCTL_BAM;
3775         if (mreg & E1000_RCTL_PMCF)
3776                 preg |= BM_RCTL_PMCF;
3777         mreg = E1000_READ_REG(hw, E1000_CTRL);
3778         if (mreg & E1000_CTRL_RFCE)
3779                 preg |= BM_RCTL_RFCE;
3780         e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg);
3781
3782         /* enable PHY wakeup in MAC register */
3783         E1000_WRITE_REG(hw, E1000_WUC,
3784             E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
3785         E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol);
3786
3787         /* configure and enable PHY wakeup in PHY registers */
3788         e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol);
3789         e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
3790
3791         /* activate PHY wakeup */
3792         ret = hw->phy.ops.acquire(hw);
3793         if (ret) {
3794                 printf("Could not acquire PHY\n");
3795                 return ret;
3796         }
3797         e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3798                                  (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3799         ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
3800         if (ret) {
3801                 printf("Could not read PHY page 769\n");
3802                 goto out;
3803         }
3804         preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
3805         ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
3806         if (ret)
3807                 printf("Could not set PHY Host Wakeup bit\n");
3808 out:
3809         hw->phy.ops.release(hw);
3810
3811         return ret;
3812 }
3813
3814 static void
3815 em_if_led_func(if_ctx_t ctx, int onoff)
3816 {
3817         struct adapter *adapter = iflib_get_softc(ctx);
3818
3819         if (onoff) {
3820                 e1000_setup_led(&adapter->hw);
3821                 e1000_led_on(&adapter->hw);
3822         } else {
3823                 e1000_led_off(&adapter->hw);
3824                 e1000_cleanup_led(&adapter->hw);
3825         }
3826 }
3827
3828 /*
3829  * Disable the L0S and L1 LINK states
3830  */
3831 static void
3832 em_disable_aspm(struct adapter *adapter)
3833 {
3834         int base, reg;
3835         u16 link_cap,link_ctrl;
3836         device_t dev = adapter->dev;
3837
3838         switch (adapter->hw.mac.type) {
3839         case e1000_82573:
3840         case e1000_82574:
3841         case e1000_82583:
3842                 break;
3843         default:
3844                 return;
3845         }
3846         if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
3847                 return;
3848         reg = base + PCIER_LINK_CAP;
3849         link_cap = pci_read_config(dev, reg, 2);
3850         if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
3851                 return;
3852         reg = base + PCIER_LINK_CTL;
3853         link_ctrl = pci_read_config(dev, reg, 2);
3854         link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
3855         pci_write_config(dev, reg, link_ctrl, 2);
3856         return;
3857 }
3858
3859 /**********************************************************************
3860  *
3861  *  Update the board statistics counters.
3862  *
3863  **********************************************************************/
3864 static void
3865 em_update_stats_counters(struct adapter *adapter)
3866 {
3867
3868         if(adapter->hw.phy.media_type == e1000_media_type_copper ||
3869            (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3870                 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
3871                 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
3872         }
3873         adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
3874         adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
3875         adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
3876         adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
3877
3878         adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
3879         adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
3880         adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
3881         adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
3882         adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
3883         adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
3884         adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
3885         adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
3886         /*
3887          ** For watchdog management we need to know if we have been
3888          ** paused during the last interval, so capture that here.
3889         */
3890         adapter->shared->isc_pause_frames = adapter->stats.xoffrxc;
3891         adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
3892         adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
3893         adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
3894         adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
3895         adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
3896         adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
3897         adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
3898         adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
3899         adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
3900         adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
3901         adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
3902         adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
3903
3904         /* For the 64-bit byte counters the low dword must be read first. */
3905         /* Both registers clear on the read of the high dword */
3906
3907         adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) +
3908             ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32);
3909         adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) +
3910             ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32);
3911
3912         adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
3913         adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
3914         adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
3915         adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
3916         adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
3917
3918         adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
3919         adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
3920
3921         adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
3922         adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
3923         adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
3924         adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
3925         adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
3926         adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
3927         adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
3928         adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
3929         adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
3930         adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
3931
3932         /* Interrupt Counts */
3933
3934         adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC);
3935         adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC);
3936         adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC);
3937         adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC);
3938         adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC);
3939         adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC);
3940         adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC);
3941         adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC);
3942         adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC);
3943
3944         if (adapter->hw.mac.type >= e1000_82543) {
3945                 adapter->stats.algnerrc +=
3946                 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
3947                 adapter->stats.rxerrc +=
3948                 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
3949                 adapter->stats.tncrs +=
3950                 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
3951                 adapter->stats.cexterr +=
3952                 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
3953                 adapter->stats.tsctc +=
3954                 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
3955                 adapter->stats.tsctfc +=
3956                 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
3957         }
3958 }
3959
3960 static uint64_t
3961 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
3962 {
3963         struct adapter *adapter = iflib_get_softc(ctx);
3964         struct ifnet *ifp = iflib_get_ifp(ctx);
3965
3966         switch (cnt) {
3967         case IFCOUNTER_COLLISIONS:
3968                 return (adapter->stats.colc);
3969         case IFCOUNTER_IERRORS:
3970                 return (adapter->dropped_pkts + adapter->stats.rxerrc +
3971                     adapter->stats.crcerrs + adapter->stats.algnerrc +
3972                     adapter->stats.ruc + adapter->stats.roc +
3973                     adapter->stats.mpc + adapter->stats.cexterr);
3974         case IFCOUNTER_OERRORS:
3975                 return (adapter->stats.ecol + adapter->stats.latecol +
3976                     adapter->watchdog_events);
3977         default:
3978                 return (if_get_counter_default(ifp, cnt));
3979         }
3980 }
3981
3982 /* Export a single 32-bit register via a read-only sysctl. */
3983 static int
3984 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
3985 {
3986         struct adapter *adapter;
3987         u_int val;
3988
3989         adapter = oidp->oid_arg1;
3990         val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2);
3991         return (sysctl_handle_int(oidp, &val, 0, req));
3992 }
3993
3994 /*
3995  * Add sysctl variables, one per statistic, to the system.
3996  */
3997 static void
3998 em_add_hw_stats(struct adapter *adapter)
3999 {
4000         device_t dev = iflib_get_dev(adapter->ctx);
4001         struct em_tx_queue *tx_que = adapter->tx_queues;
4002         struct em_rx_queue *rx_que = adapter->rx_queues;
4003
4004         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
4005         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
4006         struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
4007         struct e1000_hw_stats *stats = &adapter->stats;
4008
4009         struct sysctl_oid *stat_node, *queue_node, *int_node;
4010         struct sysctl_oid_list *stat_list, *queue_list, *int_list;
4011
4012 #define QUEUE_NAME_LEN 32
4013         char namebuf[QUEUE_NAME_LEN];
4014
4015         /* Driver Statistics */
4016         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
4017                         CTLFLAG_RD, &adapter->dropped_pkts,
4018                         "Driver dropped packets");
4019         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
4020                         CTLFLAG_RD, &adapter->link_irq,
4021                         "Link MSI-X IRQ Handled");
4022         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
4023                         CTLFLAG_RD, &adapter->rx_overruns,
4024                         "RX overruns");
4025         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
4026                         CTLFLAG_RD, &adapter->watchdog_events,
4027                         "Watchdog timeouts");
4028         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
4029                         CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL,
4030                         em_sysctl_reg_handler, "IU",
4031                         "Device Control Register");
4032         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
4033                         CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL,
4034                         em_sysctl_reg_handler, "IU",
4035                         "Receiver Control Register");
4036         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
4037                         CTLFLAG_RD, &adapter->hw.fc.high_water, 0,
4038                         "Flow Control High Watermark");
4039         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
4040                         CTLFLAG_RD, &adapter->hw.fc.low_water, 0,
4041                         "Flow Control Low Watermark");
4042
4043         for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
4044                 struct tx_ring *txr = &tx_que->txr;
4045                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
4046                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4047                                             CTLFLAG_RD, NULL, "TX Queue Name");
4048                 queue_list = SYSCTL_CHILDREN(queue_node);
4049
4050                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
4051                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4052                                 E1000_TDH(txr->me),
4053                                 em_sysctl_reg_handler, "IU",
4054                                 "Transmit Descriptor Head");
4055                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
4056                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4057                                 E1000_TDT(txr->me),
4058                                 em_sysctl_reg_handler, "IU",
4059                                 "Transmit Descriptor Tail");
4060                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
4061                                 CTLFLAG_RD, &txr->tx_irq,
4062                                 "Queue MSI-X Transmit Interrupts");
4063         }
4064
4065         for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) {
4066                 struct rx_ring *rxr = &rx_que->rxr;
4067                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
4068                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4069                                             CTLFLAG_RD, NULL, "RX Queue Name");
4070                 queue_list = SYSCTL_CHILDREN(queue_node);
4071
4072                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
4073                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4074                                 E1000_RDH(rxr->me),
4075                                 em_sysctl_reg_handler, "IU",
4076                                 "Receive Descriptor Head");
4077                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
4078                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4079                                 E1000_RDT(rxr->me),
4080                                 em_sysctl_reg_handler, "IU",
4081                                 "Receive Descriptor Tail");
4082                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
4083                                 CTLFLAG_RD, &rxr->rx_irq,
4084                                 "Queue MSI-X Receive Interrupts");
4085         }
4086
4087         /* MAC stats get their own sub node */
4088
4089         stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
4090                                     CTLFLAG_RD, NULL, "Statistics");
4091         stat_list = SYSCTL_CHILDREN(stat_node);
4092
4093         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
4094                         CTLFLAG_RD, &stats->ecol,
4095                         "Excessive collisions");
4096         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
4097                         CTLFLAG_RD, &stats->scc,
4098                         "Single collisions");
4099         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
4100                         CTLFLAG_RD, &stats->mcc,
4101                         "Multiple collisions");
4102         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
4103                         CTLFLAG_RD, &stats->latecol,
4104                         "Late collisions");
4105         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
4106                         CTLFLAG_RD, &stats->colc,
4107                         "Collision Count");
4108         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
4109                         CTLFLAG_RD, &adapter->stats.symerrs,
4110                         "Symbol Errors");
4111         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
4112                         CTLFLAG_RD, &adapter->stats.sec,
4113                         "Sequence Errors");
4114         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
4115                         CTLFLAG_RD, &adapter->stats.dc,
4116                         "Defer Count");
4117         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
4118                         CTLFLAG_RD, &adapter->stats.mpc,
4119                         "Missed Packets");
4120         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
4121                         CTLFLAG_RD, &adapter->stats.rnbc,
4122                         "Receive No Buffers");
4123         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
4124                         CTLFLAG_RD, &adapter->stats.ruc,
4125                         "Receive Undersize");
4126         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
4127                         CTLFLAG_RD, &adapter->stats.rfc,
4128                         "Fragmented Packets Received ");
4129         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
4130                         CTLFLAG_RD, &adapter->stats.roc,
4131                         "Oversized Packets Received");
4132         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
4133                         CTLFLAG_RD, &adapter->stats.rjc,
4134                         "Recevied Jabber");
4135         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
4136                         CTLFLAG_RD, &adapter->stats.rxerrc,
4137                         "Receive Errors");
4138         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
4139                         CTLFLAG_RD, &adapter->stats.crcerrs,
4140                         "CRC errors");
4141         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
4142                         CTLFLAG_RD, &adapter->stats.algnerrc,
4143                         "Alignment Errors");
4144         /* On 82575 these are collision counts */
4145         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
4146                         CTLFLAG_RD, &adapter->stats.cexterr,
4147                         "Collision/Carrier extension errors");
4148         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
4149                         CTLFLAG_RD, &adapter->stats.xonrxc,
4150                         "XON Received");
4151         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
4152                         CTLFLAG_RD, &adapter->stats.xontxc,
4153                         "XON Transmitted");
4154         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
4155                         CTLFLAG_RD, &adapter->stats.xoffrxc,
4156                         "XOFF Received");
4157         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
4158                         CTLFLAG_RD, &adapter->stats.xofftxc,
4159                         "XOFF Transmitted");
4160
4161         /* Packet Reception Stats */
4162         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
4163                         CTLFLAG_RD, &adapter->stats.tpr,
4164                         "Total Packets Received ");
4165         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
4166                         CTLFLAG_RD, &adapter->stats.gprc,
4167                         "Good Packets Received");
4168         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
4169                         CTLFLAG_RD, &adapter->stats.bprc,
4170                         "Broadcast Packets Received");
4171         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
4172                         CTLFLAG_RD, &adapter->stats.mprc,
4173                         "Multicast Packets Received");
4174         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
4175                         CTLFLAG_RD, &adapter->stats.prc64,
4176                         "64 byte frames received ");
4177         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
4178                         CTLFLAG_RD, &adapter->stats.prc127,
4179                         "65-127 byte frames received");
4180         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
4181                         CTLFLAG_RD, &adapter->stats.prc255,
4182                         "128-255 byte frames received");
4183         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
4184                         CTLFLAG_RD, &adapter->stats.prc511,
4185                         "256-511 byte frames received");
4186         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
4187                         CTLFLAG_RD, &adapter->stats.prc1023,
4188                         "512-1023 byte frames received");
4189         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
4190                         CTLFLAG_RD, &adapter->stats.prc1522,
4191                         "1023-1522 byte frames received");
4192         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
4193                         CTLFLAG_RD, &adapter->stats.gorc,
4194                         "Good Octets Received");
4195
4196         /* Packet Transmission Stats */
4197         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
4198                         CTLFLAG_RD, &adapter->stats.gotc,
4199                         "Good Octets Transmitted");
4200         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
4201                         CTLFLAG_RD, &adapter->stats.tpt,
4202                         "Total Packets Transmitted");
4203         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
4204                         CTLFLAG_RD, &adapter->stats.gptc,
4205                         "Good Packets Transmitted");
4206         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
4207                         CTLFLAG_RD, &adapter->stats.bptc,
4208                         "Broadcast Packets Transmitted");
4209         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
4210                         CTLFLAG_RD, &adapter->stats.mptc,
4211                         "Multicast Packets Transmitted");
4212         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
4213                         CTLFLAG_RD, &adapter->stats.ptc64,
4214                         "64 byte frames transmitted ");
4215         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
4216                         CTLFLAG_RD, &adapter->stats.ptc127,
4217                         "65-127 byte frames transmitted");
4218         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
4219                         CTLFLAG_RD, &adapter->stats.ptc255,
4220                         "128-255 byte frames transmitted");
4221         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
4222                         CTLFLAG_RD, &adapter->stats.ptc511,
4223                         "256-511 byte frames transmitted");
4224         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
4225                         CTLFLAG_RD, &adapter->stats.ptc1023,
4226                         "512-1023 byte frames transmitted");
4227         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
4228                         CTLFLAG_RD, &adapter->stats.ptc1522,
4229                         "1024-1522 byte frames transmitted");
4230         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
4231                         CTLFLAG_RD, &adapter->stats.tsctc,
4232                         "TSO Contexts Transmitted");
4233         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
4234                         CTLFLAG_RD, &adapter->stats.tsctfc,
4235                         "TSO Contexts Failed");
4236
4237
4238         /* Interrupt Stats */
4239
4240         int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
4241                                     CTLFLAG_RD, NULL, "Interrupt Statistics");
4242         int_list = SYSCTL_CHILDREN(int_node);
4243
4244         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
4245                         CTLFLAG_RD, &adapter->stats.iac,
4246                         "Interrupt Assertion Count");
4247
4248         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
4249                         CTLFLAG_RD, &adapter->stats.icrxptc,
4250                         "Interrupt Cause Rx Pkt Timer Expire Count");
4251
4252         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
4253                         CTLFLAG_RD, &adapter->stats.icrxatc,
4254                         "Interrupt Cause Rx Abs Timer Expire Count");
4255
4256         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
4257                         CTLFLAG_RD, &adapter->stats.ictxptc,
4258                         "Interrupt Cause Tx Pkt Timer Expire Count");
4259
4260         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
4261                         CTLFLAG_RD, &adapter->stats.ictxatc,
4262                         "Interrupt Cause Tx Abs Timer Expire Count");
4263
4264         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
4265                         CTLFLAG_RD, &adapter->stats.ictxqec,
4266                         "Interrupt Cause Tx Queue Empty Count");
4267
4268         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
4269                         CTLFLAG_RD, &adapter->stats.ictxqmtc,
4270                         "Interrupt Cause Tx Queue Min Thresh Count");
4271
4272         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
4273                         CTLFLAG_RD, &adapter->stats.icrxdmtc,
4274                         "Interrupt Cause Rx Desc Min Thresh Count");
4275
4276         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
4277                         CTLFLAG_RD, &adapter->stats.icrxoc,
4278                         "Interrupt Cause Receiver Overrun Count");
4279 }
4280
4281 /**********************************************************************
4282  *
4283  *  This routine provides a way to dump out the adapter eeprom,
4284  *  often a useful debug/service tool. This only dumps the first
4285  *  32 words, stuff that matters is in that extent.
4286  *
4287  **********************************************************************/
4288 static int
4289 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4290 {
4291         struct adapter *adapter = (struct adapter *)arg1;
4292         int error;
4293         int result;
4294
4295         result = -1;
4296         error = sysctl_handle_int(oidp, &result, 0, req);
4297
4298         if (error || !req->newptr)
4299                 return (error);
4300
4301         /*
4302          * This value will cause a hex dump of the
4303          * first 32 16-bit words of the EEPROM to
4304          * the screen.
4305          */
4306         if (result == 1)
4307                 em_print_nvm_info(adapter);
4308
4309         return (error);
4310 }
4311
4312 static void
4313 em_print_nvm_info(struct adapter *adapter)
4314 {
4315         u16 eeprom_data;
4316         int i, j, row = 0;
4317
4318         /* Its a bit crude, but it gets the job done */
4319         printf("\nInterface EEPROM Dump:\n");
4320         printf("Offset\n0x0000  ");
4321         for (i = 0, j = 0; i < 32; i++, j++) {
4322                 if (j == 8) { /* Make the offset block */
4323                         j = 0; ++row;
4324                         printf("\n0x00%x0  ",row);
4325                 }
4326                 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
4327                 printf("%04x ", eeprom_data);
4328         }
4329         printf("\n");
4330 }
4331
4332 static int
4333 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4334 {
4335         struct em_int_delay_info *info;
4336         struct adapter *adapter;
4337         u32 regval;
4338         int error, usecs, ticks;
4339
4340         info = (struct em_int_delay_info *) arg1;
4341         usecs = info->value;
4342         error = sysctl_handle_int(oidp, &usecs, 0, req);
4343         if (error != 0 || req->newptr == NULL)
4344                 return (error);
4345         if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4346                 return (EINVAL);
4347         info->value = usecs;
4348         ticks = EM_USECS_TO_TICKS(usecs);
4349         if (info->offset == E1000_ITR)  /* units are 256ns here */
4350                 ticks *= 4;
4351
4352         adapter = info->adapter;
4353
4354         regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
4355         regval = (regval & ~0xffff) | (ticks & 0xffff);
4356         /* Handle a few special cases. */
4357         switch (info->offset) {
4358         case E1000_RDTR:
4359                 break;
4360         case E1000_TIDV:
4361                 if (ticks == 0) {
4362                         adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
4363                         /* Don't write 0 into the TIDV register. */
4364                         regval++;
4365                 } else
4366                         adapter->txd_cmd |= E1000_TXD_CMD_IDE;
4367                 break;
4368         }
4369         E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
4370         return (0);
4371 }
4372
4373 static void
4374 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
4375         const char *description, struct em_int_delay_info *info,
4376         int offset, int value)
4377 {
4378         info->adapter = adapter;
4379         info->offset = offset;
4380         info->value = value;
4381         SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev),
4382             SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4383             OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
4384             info, 0, em_sysctl_int_delay, "I", description);
4385 }
4386
4387 /*
4388  * Set flow control using sysctl:
4389  * Flow control values:
4390  *      0 - off
4391  *      1 - rx pause
4392  *      2 - tx pause
4393  *      3 - full
4394  */
4395 static int
4396 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4397 {
4398         int error;
4399         static int input = 3; /* default is full */
4400         struct adapter  *adapter = (struct adapter *) arg1;
4401
4402         error = sysctl_handle_int(oidp, &input, 0, req);
4403
4404         if ((error) || (req->newptr == NULL))
4405                 return (error);
4406
4407         if (input == adapter->fc) /* no change? */
4408                 return (error);
4409
4410         switch (input) {
4411         case e1000_fc_rx_pause:
4412         case e1000_fc_tx_pause:
4413         case e1000_fc_full:
4414         case e1000_fc_none:
4415                 adapter->hw.fc.requested_mode = input;
4416                 adapter->fc = input;
4417                 break;
4418         default:
4419                 /* Do nothing */
4420                 return (error);
4421         }
4422
4423         adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
4424         e1000_force_mac_fc(&adapter->hw);
4425         return (error);
4426 }
4427
4428 /*
4429  * Manage Energy Efficient Ethernet:
4430  * Control values:
4431  *     0/1 - enabled/disabled
4432  */
4433 static int
4434 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4435 {
4436         struct adapter *adapter = (struct adapter *) arg1;
4437         int error, value;
4438
4439         value = adapter->hw.dev_spec.ich8lan.eee_disable;
4440         error = sysctl_handle_int(oidp, &value, 0, req);
4441         if (error || req->newptr == NULL)
4442                 return (error);
4443         adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4444         em_if_init(adapter->ctx);
4445
4446         return (0);
4447 }
4448
4449 static int
4450 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4451 {
4452         struct adapter *adapter;
4453         int error;
4454         int result;
4455
4456         result = -1;
4457         error = sysctl_handle_int(oidp, &result, 0, req);
4458
4459         if (error || !req->newptr)
4460                 return (error);
4461
4462         if (result == 1) {
4463                 adapter = (struct adapter *) arg1;
4464                 em_print_debug_info(adapter);
4465         }
4466
4467         return (error);
4468 }
4469
4470 static int
4471 em_get_rs(SYSCTL_HANDLER_ARGS)
4472 {
4473         struct adapter *adapter = (struct adapter *) arg1;
4474         int error;
4475         int result;
4476
4477         result = 0;
4478         error = sysctl_handle_int(oidp, &result, 0, req);
4479
4480         if (error || !req->newptr || result != 1)
4481                 return (error);
4482         em_dump_rs(adapter);
4483
4484         return (error);
4485 }
4486
4487 static void
4488 em_if_debug(if_ctx_t ctx)
4489 {
4490         em_dump_rs(iflib_get_softc(ctx));
4491 }
4492
4493 /*
4494  * This routine is meant to be fluid, add whatever is
4495  * needed for debugging a problem.  -jfv
4496  */
4497 static void
4498 em_print_debug_info(struct adapter *adapter)
4499 {
4500         device_t dev = iflib_get_dev(adapter->ctx);
4501         struct ifnet *ifp = iflib_get_ifp(adapter->ctx);
4502         struct tx_ring *txr = &adapter->tx_queues->txr;
4503         struct rx_ring *rxr = &adapter->rx_queues->rxr;
4504
4505         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
4506                 printf("Interface is RUNNING ");
4507         else
4508                 printf("Interface is NOT RUNNING\n");
4509
4510         if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
4511                 printf("and INACTIVE\n");
4512         else
4513                 printf("and ACTIVE\n");
4514
4515         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
4516                 device_printf(dev, "TX Queue %d ------\n", i);
4517                 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
4518                         E1000_READ_REG(&adapter->hw, E1000_TDH(i)),
4519                         E1000_READ_REG(&adapter->hw, E1000_TDT(i)));
4520
4521         }
4522         for (int j=0; j < adapter->rx_num_queues; j++, rxr++) {
4523                 device_printf(dev, "RX Queue %d ------\n", j);
4524                 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
4525                         E1000_READ_REG(&adapter->hw, E1000_RDH(j)),
4526                         E1000_READ_REG(&adapter->hw, E1000_RDT(j)));
4527         }
4528 }
4529
4530 /*
4531  * 82574 only:
4532  * Write a new value to the EEPROM increasing the number of MSI-X
4533  * vectors from 3 to 5, for proper multiqueue support.
4534  */
4535 static void
4536 em_enable_vectors_82574(if_ctx_t ctx)
4537 {
4538         struct adapter *adapter = iflib_get_softc(ctx);
4539         struct e1000_hw *hw = &adapter->hw;
4540         device_t dev = iflib_get_dev(ctx);
4541         u16 edata;
4542
4543         e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4544         if (bootverbose)
4545                 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata);
4546         if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
4547                 device_printf(dev, "Writing to eeprom: increasing "
4548                     "reported MSI-X vectors from 3 to 5...\n");
4549                 edata &= ~(EM_NVM_MSIX_N_MASK);
4550                 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
4551                 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4552                 e1000_update_nvm_checksum(hw);
4553                 device_printf(dev, "Writing to eeprom: done\n");
4554         }
4555 }