sys/dev/e1000/if_em.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /* $FreeBSD$ */
  30 #include "if_em.h"
  31 #include <sys/sbuf.h>
  32 #include <machine/_inttypes.h>
  33
  34 #define em_mac_min e1000_82547
  35 #define igb_mac_min e1000_82575
  36
  37 /*********************************************************************
  38  *  Driver version:
  39  *********************************************************************/
  40 char em_driver_version[] = "7.6.1-k";
  41
  42 /*********************************************************************
  43  *  PCI Device ID Table
  44  *
  45  *  Used by probe to select devices to load on
  46  *  Last field stores an index into e1000_strings
  47  *  Last entry must be all 0s
  48  *
  49  *  { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
  50  *********************************************************************/
  51
  52 static pci_vendor_info_t em_vendor_info_array[] =
  53 {
  54         /* Intel(R) PRO/1000 Network Connection - Legacy em*/
  55         PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"),
  56         PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"),
  57         PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"),
  58         PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"),
  59         PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"),
  60
  61         PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"),
  62         PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"),
  63         PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"),
  64         PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  65         PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"),
  66         PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"),
  67         PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  68
  69         PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"),
  70
  71         PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"),
  72         PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
  73
  74         PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
  75         PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
  76         PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
  77         PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"),
  78
  79         PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"),
  80         PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"),
  81         PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"),
  82         PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"),
  83         PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"),
  84
  85         PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  86         PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
  87         PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
  88         PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  89         PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"),
  90         PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"),
  91         PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"),
  92         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
  93         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"),
  94
  95         PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"),
  96         PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  97         PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"),
  98
  99         /* Intel(R) PRO/1000 Network Connection - em */
 100         PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
 101         PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
 102         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"),
 103         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"),
 104         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"),
 105         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 106         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"),
 107         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"),
 108         PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 109         PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"),
 110         PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
 111         PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
 112         PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"),
 113         PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"),
 114         PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"),
 115         PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"),
 116         PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"),
 117         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"),
 118         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"),
 119         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"),
 120         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"),
 121         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
 122         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 123         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"),
 124         PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"),
 125         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
 126         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"),
 127         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"),
 128         PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"),
 129         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
 130         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 131         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"),
 132         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"),
 133         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"),
 134         PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"),
 135         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
 136         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"),
 137         PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"),
 138         PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"),
 139         PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"),
 140         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"),
 141         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"),
 142         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"),
 143         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"),
 144         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"),
 145         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"),
 146         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"),
 147         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"),
 148         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"),
 149         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"),
 150         PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"),
 151         PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"),
 152         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"),
 153         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"),
 154         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"),
 155         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"),
 156         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"),
 157         PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"),
 158         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"),
 159         PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"),
 160         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"),
 161         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"),
 162         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"),
 163         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"),
 164         PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"),
 165         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"),
 166         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"),
 167         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"),
 168         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"),
 169         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) PRO/1000 Network Connection"),
 170         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) PRO/1000 Network Connection"),
 171         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) PRO/1000 Network Connection"),
 172         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) PRO/1000 Network Connection"),
 173         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) PRO/1000 Network Connection"),
 174         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) PRO/1000 Network Connection"),
 175         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) PRO/1000 Network Connection"),
 176         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) PRO/1000 Network Connection"),
 177         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V10, "Intel(R) PRO/1000 Network Connection"),
 178         /* required last entry */
 179         PVID_END
 180 };
 181
 182 static pci_vendor_info_t igb_vendor_info_array[] =
 183 {
 184         /* Intel(R) PRO/1000 Network Connection - igb */
 185         PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 186         PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 187         PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 188         PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 189         PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 190         PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 191         PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 192         PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 193         PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 194         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 195         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 196         PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 197         PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 198         PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 199         PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 200         PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 201         PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 202         PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 203         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 204         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 205         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 206         PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 207         PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 208         PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 209         PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 210         PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 211         PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 212         PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 213         PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 214         PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 215         PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 216         PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 217         PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 218         PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 219         PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 220         PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 221         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 222         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 223         PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 224         /* required last entry */
 225         PVID_END
 226 };
 227
 228 /*********************************************************************
 229  *  Function prototypes
 230  *********************************************************************/
 231 static void     *em_register(device_t dev);
 232 static void     *igb_register(device_t dev);
 233 static int      em_if_attach_pre(if_ctx_t ctx);
 234 static int      em_if_attach_post(if_ctx_t ctx);
 235 static int      em_if_detach(if_ctx_t ctx);
 236 static int      em_if_shutdown(if_ctx_t ctx);
 237 static int      em_if_suspend(if_ctx_t ctx);
 238 static int      em_if_resume(if_ctx_t ctx);
 239
 240 static int      em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets);
 241 static int      em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets);
 242 static void     em_if_queues_free(if_ctx_t ctx);
 243
 244 static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
 245 static void     em_if_init(if_ctx_t ctx);
 246 static void     em_if_stop(if_ctx_t ctx);
 247 static void     em_if_media_status(if_ctx_t, struct ifmediareq *);
 248 static int      em_if_media_change(if_ctx_t ctx);
 249 static int      em_if_mtu_set(if_ctx_t ctx, uint32_t mtu);
 250 static void     em_if_timer(if_ctx_t ctx, uint16_t qid);
 251 static void     em_if_vlan_register(if_ctx_t ctx, u16 vtag);
 252 static void     em_if_vlan_unregister(if_ctx_t ctx, u16 vtag);
 253 static void     em_if_watchdog_reset(if_ctx_t ctx);
 254
 255 static void     em_identify_hardware(if_ctx_t ctx);
 256 static int      em_allocate_pci_resources(if_ctx_t ctx);
 257 static void     em_free_pci_resources(if_ctx_t ctx);
 258 static void     em_reset(if_ctx_t ctx);
 259 static int      em_setup_interface(if_ctx_t ctx);
 260 static int      em_setup_msix(if_ctx_t ctx);
 261
 262 static void     em_initialize_transmit_unit(if_ctx_t ctx);
 263 static void     em_initialize_receive_unit(if_ctx_t ctx);
 264
 265 static void     em_if_intr_enable(if_ctx_t ctx);
 266 static void     em_if_intr_disable(if_ctx_t ctx);
 267 static void     igb_if_intr_enable(if_ctx_t ctx);
 268 static void     igb_if_intr_disable(if_ctx_t ctx);
 269 static int      em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 270 static int      em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
 271 static int      igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 272 static int      igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
 273 static void     em_if_multi_set(if_ctx_t ctx);
 274 static void     em_if_update_admin_status(if_ctx_t ctx);
 275 static void     em_if_debug(if_ctx_t ctx);
 276 static void     em_update_stats_counters(struct adapter *);
 277 static void     em_add_hw_stats(struct adapter *adapter);
 278 static int      em_if_set_promisc(if_ctx_t ctx, int flags);
 279 static void     em_setup_vlan_hw_support(struct adapter *);
 280 static int      em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
 281 static void     em_print_nvm_info(struct adapter *);
 282 static int      em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 283 static int      em_get_rs(SYSCTL_HANDLER_ARGS);
 284 static void     em_print_debug_info(struct adapter *);
 285 static int      em_is_valid_ether_addr(u8 *);
 286 static int      em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
 287 static void     em_add_int_delay_sysctl(struct adapter *, const char *,
 288                     const char *, struct em_int_delay_info *, int, int);
 289 /* Management and WOL Support */
 290 static void     em_init_manageability(struct adapter *);
 291 static void     em_release_manageability(struct adapter *);
 292 static void     em_get_hw_control(struct adapter *);
 293 static void     em_release_hw_control(struct adapter *);
 294 static void     em_get_wakeup(if_ctx_t ctx);
 295 static void     em_enable_wakeup(if_ctx_t ctx);
 296 static int      em_enable_phy_wakeup(struct adapter *);
 297 static void     em_disable_aspm(struct adapter *);
 298
 299 int             em_intr(void *arg);
 300 static void     em_disable_promisc(if_ctx_t ctx);
 301
 302 /* MSI-X handlers */
 303 static int      em_if_msix_intr_assign(if_ctx_t, int);
 304 static int      em_msix_link(void *);
 305 static void     em_handle_link(void *context);
 306
 307 static void     em_enable_vectors_82574(if_ctx_t);
 308
 309 static int      em_set_flowcntl(SYSCTL_HANDLER_ARGS);
 310 static int      em_sysctl_eee(SYSCTL_HANDLER_ARGS);
 311 static void     em_if_led_func(if_ctx_t ctx, int onoff);
 312
 313 static int      em_get_regs(SYSCTL_HANDLER_ARGS);
 314
 315 static void     lem_smartspeed(struct adapter *adapter);
 316 static void     igb_configure_queues(struct adapter *adapter);
 317
 318
 319 /*********************************************************************
 320  *  FreeBSD Device Interface Entry Points
 321  *********************************************************************/
 322 static device_method_t em_methods[] = {
 323         /* Device interface */
 324         DEVMETHOD(device_register, em_register),
 325         DEVMETHOD(device_probe, iflib_device_probe),
 326         DEVMETHOD(device_attach, iflib_device_attach),
 327         DEVMETHOD(device_detach, iflib_device_detach),
 328         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 329         DEVMETHOD(device_suspend, iflib_device_suspend),
 330         DEVMETHOD(device_resume, iflib_device_resume),
 331         DEVMETHOD_END
 332 };
 333
 334 static device_method_t igb_methods[] = {
 335         /* Device interface */
 336         DEVMETHOD(device_register, igb_register),
 337         DEVMETHOD(device_probe, iflib_device_probe),
 338         DEVMETHOD(device_attach, iflib_device_attach),
 339         DEVMETHOD(device_detach, iflib_device_detach),
 340         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 341         DEVMETHOD(device_suspend, iflib_device_suspend),
 342         DEVMETHOD(device_resume, iflib_device_resume),
 343         DEVMETHOD_END
 344 };
 345
 346
 347 static driver_t em_driver = {
 348         "em", em_methods, sizeof(struct adapter),
 349 };
 350
 351 static devclass_t em_devclass;
 352 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
 353
 354 MODULE_DEPEND(em, pci, 1, 1, 1);
 355 MODULE_DEPEND(em, ether, 1, 1, 1);
 356 MODULE_DEPEND(em, iflib, 1, 1, 1);
 357
 358 IFLIB_PNP_INFO(pci, em, em_vendor_info_array);
 359
 360 static driver_t igb_driver = {
 361         "igb", igb_methods, sizeof(struct adapter),
 362 };
 363
 364 static devclass_t igb_devclass;
 365 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
 366
 367 MODULE_DEPEND(igb, pci, 1, 1, 1);
 368 MODULE_DEPEND(igb, ether, 1, 1, 1);
 369 MODULE_DEPEND(igb, iflib, 1, 1, 1);
 370
 371 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array);
 372
 373 static device_method_t em_if_methods[] = {
 374         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 375         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 376         DEVMETHOD(ifdi_detach, em_if_detach),
 377         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 378         DEVMETHOD(ifdi_suspend, em_if_suspend),
 379         DEVMETHOD(ifdi_resume, em_if_resume),
 380         DEVMETHOD(ifdi_init, em_if_init),
 381         DEVMETHOD(ifdi_stop, em_if_stop),
 382         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 383         DEVMETHOD(ifdi_intr_enable, em_if_intr_enable),
 384         DEVMETHOD(ifdi_intr_disable, em_if_intr_disable),
 385         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 386         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 387         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 388         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 389         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 390         DEVMETHOD(ifdi_media_status, em_if_media_status),
 391         DEVMETHOD(ifdi_media_change, em_if_media_change),
 392         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 393         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 394         DEVMETHOD(ifdi_timer, em_if_timer),
 395         DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
 396         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 397         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 398         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 399         DEVMETHOD(ifdi_led_func, em_if_led_func),
 400         DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable),
 401         DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable),
 402         DEVMETHOD(ifdi_debug, em_if_debug),
 403         DEVMETHOD_END
 404 };
 405
 406 static driver_t em_if_driver = {
 407         "em_if", em_if_methods, sizeof(struct adapter)
 408 };
 409
 410 static device_method_t igb_if_methods[] = {
 411         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 412         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 413         DEVMETHOD(ifdi_detach, em_if_detach),
 414         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 415         DEVMETHOD(ifdi_suspend, em_if_suspend),
 416         DEVMETHOD(ifdi_resume, em_if_resume),
 417         DEVMETHOD(ifdi_init, em_if_init),
 418         DEVMETHOD(ifdi_stop, em_if_stop),
 419         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 420         DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable),
 421         DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable),
 422         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 423         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 424         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 425         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 426         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 427         DEVMETHOD(ifdi_media_status, em_if_media_status),
 428         DEVMETHOD(ifdi_media_change, em_if_media_change),
 429         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 430         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 431         DEVMETHOD(ifdi_timer, em_if_timer),
 432         DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
 433         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 434         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 435         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 436         DEVMETHOD(ifdi_led_func, em_if_led_func),
 437         DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable),
 438         DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable),
 439         DEVMETHOD(ifdi_debug, em_if_debug),
 440         DEVMETHOD_END
 441 };
 442
 443 static driver_t igb_if_driver = {
 444         "igb_if", igb_if_methods, sizeof(struct adapter)
 445 };
 446
 447 /*********************************************************************
 448  *  Tunable default values.
 449  *********************************************************************/
 450
 451 #define EM_TICKS_TO_USECS(ticks)        ((1024 * (ticks) + 500) / 1000)
 452 #define EM_USECS_TO_TICKS(usecs)        ((1000 * (usecs) + 512) / 1024)
 453
 454 #define MAX_INTS_PER_SEC        8000
 455 #define DEFAULT_ITR             (1000000000/(MAX_INTS_PER_SEC * 256))
 456
 457 /* Allow common code without TSO */
 458 #ifndef CSUM_TSO
 459 #define CSUM_TSO        0
 460 #endif
 461
 462 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
 463     "EM driver parameters");
 464
 465 static int em_disable_crc_stripping = 0;
 466 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
 467     &em_disable_crc_stripping, 0, "Disable CRC Stripping");
 468
 469 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
 470 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
 471 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
 472     0, "Default transmit interrupt delay in usecs");
 473 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
 474     0, "Default receive interrupt delay in usecs");
 475
 476 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
 477 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
 478 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
 479     &em_tx_abs_int_delay_dflt, 0,
 480     "Default transmit interrupt delay limit in usecs");
 481 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
 482     &em_rx_abs_int_delay_dflt, 0,
 483     "Default receive interrupt delay limit in usecs");
 484
 485 static int em_smart_pwr_down = FALSE;
 486 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
 487     0, "Set to true to leave smart power down enabled on newer adapters");
 488
 489 /* Controls whether promiscuous also shows bad packets */
 490 static int em_debug_sbp = TRUE;
 491 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
 492     "Show bad packets in promiscuous mode");
 493
 494 /* How many packets rxeof tries to clean at a time */
 495 static int em_rx_process_limit = 100;
 496 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
 497     &em_rx_process_limit, 0,
 498     "Maximum number of received packets to process "
 499     "at a time, -1 means unlimited");
 500
 501 /* Energy efficient ethernet - default to OFF */
 502 static int eee_setting = 1;
 503 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
 504     "Enable Energy Efficient Ethernet");
 505
 506 /*
 507 ** Tuneable Interrupt rate
 508 */
 509 static int em_max_interrupt_rate = 8000;
 510 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
 511     &em_max_interrupt_rate, 0, "Maximum interrupts per second");
 512
 513
 514
 515 /* Global used in WOL setup with multiport cards */
 516 static int global_quad_port_a = 0;
 517
 518 extern struct if_txrx igb_txrx;
 519 extern struct if_txrx em_txrx;
 520 extern struct if_txrx lem_txrx;
 521
 522 static struct if_shared_ctx em_sctx_init = {
 523         .isc_magic = IFLIB_MAGIC,
 524         .isc_q_align = PAGE_SIZE,
 525         .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 526         .isc_tx_maxsegsize = PAGE_SIZE,
 527         .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 528         .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
 529         .isc_rx_maxsize = MJUM9BYTES,
 530         .isc_rx_nsegments = 1,
 531         .isc_rx_maxsegsize = MJUM9BYTES,
 532         .isc_nfl = 1,
 533         .isc_nrxqs = 1,
 534         .isc_ntxqs = 1,
 535         .isc_admin_intrcnt = 1,
 536         .isc_vendor_info = em_vendor_info_array,
 537         .isc_driver_version = em_driver_version,
 538         .isc_driver = &em_if_driver,
 539         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 540
 541         .isc_nrxd_min = {EM_MIN_RXD},
 542         .isc_ntxd_min = {EM_MIN_TXD},
 543         .isc_nrxd_max = {EM_MAX_RXD},
 544         .isc_ntxd_max = {EM_MAX_TXD},
 545         .isc_nrxd_default = {EM_DEFAULT_RXD},
 546         .isc_ntxd_default = {EM_DEFAULT_TXD},
 547 };
 548
 549 if_shared_ctx_t em_sctx = &em_sctx_init;
 550
 551 static struct if_shared_ctx igb_sctx_init = {
 552         .isc_magic = IFLIB_MAGIC,
 553         .isc_q_align = PAGE_SIZE,
 554         .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 555         .isc_tx_maxsegsize = PAGE_SIZE,
 556         .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 557         .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
 558         .isc_rx_maxsize = MJUM9BYTES,
 559         .isc_rx_nsegments = 1,
 560         .isc_rx_maxsegsize = MJUM9BYTES,
 561         .isc_nfl = 1,
 562         .isc_nrxqs = 1,
 563         .isc_ntxqs = 1,
 564         .isc_admin_intrcnt = 1,
 565         .isc_vendor_info = igb_vendor_info_array,
 566         .isc_driver_version = em_driver_version,
 567         .isc_driver = &igb_if_driver,
 568         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 569
 570         .isc_nrxd_min = {EM_MIN_RXD},
 571         .isc_ntxd_min = {EM_MIN_TXD},
 572         .isc_nrxd_max = {IGB_MAX_RXD},
 573         .isc_ntxd_max = {IGB_MAX_TXD},
 574         .isc_nrxd_default = {EM_DEFAULT_RXD},
 575         .isc_ntxd_default = {EM_DEFAULT_TXD},
 576 };
 577
 578 if_shared_ctx_t igb_sctx = &igb_sctx_init;
 579
 580 /*****************************************************************
 581  *
 582  * Dump Registers
 583  *
 584  ****************************************************************/
 585 #define IGB_REGS_LEN 739
 586
 587 static int em_get_regs(SYSCTL_HANDLER_ARGS)
 588 {
 589         struct adapter *adapter = (struct adapter *)arg1;
 590         struct e1000_hw *hw = &adapter->hw;
 591         struct sbuf *sb;
 592         u32 *regs_buff;
 593         int rc;
 594
 595         regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK);
 596         memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
 597
 598         rc = sysctl_wire_old_buffer(req, 0);
 599         MPASS(rc == 0);
 600         if (rc != 0) {
 601                 free(regs_buff, M_DEVBUF);
 602                 return (rc);
 603         }
 604
 605         sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
 606         MPASS(sb != NULL);
 607         if (sb == NULL) {
 608                 free(regs_buff, M_DEVBUF);
 609                 return (ENOMEM);
 610         }
 611
 612         /* General Registers */
 613         regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
 614         regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
 615         regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
 616         regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
 617         regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
 618         regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
 619         regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
 620         regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
 621         regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
 622         regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
 623         regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
 624         regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
 625         regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
 626         regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
 627         regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
 628         regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
 629         regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
 630         regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
 631         regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
 632         regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
 633         regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
 634         regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
 635
 636         sbuf_printf(sb, "General Registers\n");
 637         sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
 638         sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
 639         sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]);
 640
 641         sbuf_printf(sb, "Interrupt Registers\n");
 642         sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
 643
 644         sbuf_printf(sb, "RX Registers\n");
 645         sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
 646         sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
 647         sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
 648         sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
 649         sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
 650         sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
 651         sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
 652
 653         sbuf_printf(sb, "TX Registers\n");
 654         sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
 655         sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
 656         sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
 657         sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
 658         sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
 659         sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
 660         sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
 661         sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
 662         sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
 663         sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
 664         sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
 665
 666         free(regs_buff, M_DEVBUF);
 667
 668 #ifdef DUMP_DESCS
 669         {
 670                 if_softc_ctx_t scctx = adapter->shared;
 671                 struct rx_ring *rxr = &rx_que->rxr;
 672                 struct tx_ring *txr = &tx_que->txr;
 673                 int ntxd = scctx->isc_ntxd[0];
 674                 int nrxd = scctx->isc_nrxd[0];
 675                 int j;
 676
 677         for (j = 0; j < nrxd; j++) {
 678                 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
 679                 u32 length =  le32toh(rxr->rx_base[j].wb.upper.length);
 680                 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 "  Error:%d  Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
 681         }
 682
 683         for (j = 0; j < min(ntxd, 256); j++) {
 684                 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
 685
 686                 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x  eop: %d DD=%d\n",
 687                             j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
 688                             buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
 689
 690         }
 691         }
 692 #endif
 693
 694         rc = sbuf_finish(sb);
 695         sbuf_delete(sb);
 696         return(rc);
 697 }
 698
 699 static void *
 700 em_register(device_t dev)
 701 {
 702         return (em_sctx);
 703 }
 704
 705 static void *
 706 igb_register(device_t dev)
 707 {
 708         return (igb_sctx);
 709 }
 710
 711 static int
 712 em_set_num_queues(if_ctx_t ctx)
 713 {
 714         struct adapter *adapter = iflib_get_softc(ctx);
 715         int maxqueues;
 716
 717         /* Sanity check based on HW */
 718         switch (adapter->hw.mac.type) {
 719         case e1000_82576:
 720         case e1000_82580:
 721         case e1000_i350:
 722         case e1000_i354:
 723                 maxqueues = 8;
 724                 break;
 725         case e1000_i210:
 726         case e1000_82575:
 727                 maxqueues = 4;
 728                 break;
 729         case e1000_i211:
 730         case e1000_82574:
 731                 maxqueues = 2;
 732                 break;
 733         default:
 734                 maxqueues = 1;
 735                 break;
 736         }
 737
 738         return (maxqueues);
 739 }
 740
 741 #define LEM_CAPS                                                        \
 742     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 743     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER
 744
 745 #define EM_CAPS                                                         \
 746     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 747     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 |  \
 748     IFCAP_LRO | IFCAP_VLAN_HWTSO
 749
 750 #define IGB_CAPS                                                        \
 751     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 752     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 |  \
 753     IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\
 754     IFCAP_TSO6
 755
 756 /*********************************************************************
 757  *  Device initialization routine
 758  *
 759  *  The attach entry point is called when the driver is being loaded.
 760  *  This routine identifies the type of hardware, allocates all resources
 761  *  and initializes the hardware.
 762  *
 763  *  return 0 on success, positive on failure
 764  *********************************************************************/
 765 static int
 766 em_if_attach_pre(if_ctx_t ctx)
 767 {
 768         struct adapter *adapter;
 769         if_softc_ctx_t scctx;
 770         device_t dev;
 771         struct e1000_hw *hw;
 772         int error = 0;
 773
 774         INIT_DEBUGOUT("em_if_attach_pre: begin");
 775         dev = iflib_get_dev(ctx);
 776         adapter = iflib_get_softc(ctx);
 777
 778         adapter->ctx = adapter->osdep.ctx = ctx;
 779         adapter->dev = adapter->osdep.dev = dev;
 780         scctx = adapter->shared = iflib_get_softc_ctx(ctx);
 781         adapter->media = iflib_get_media(ctx);
 782         hw = &adapter->hw;
 783
 784         adapter->tx_process_limit = scctx->isc_ntxd[0];
 785
 786         /* SYSCTL stuff */
 787         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 788             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 789             OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
 790             adapter, 0, em_sysctl_nvm_info, "I", "NVM Information");
 791
 792         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 793             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 794             OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
 795             adapter, 0, em_sysctl_debug_info, "I", "Debug Information");
 796
 797         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 798             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 799             OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
 800             adapter, 0, em_set_flowcntl, "I", "Flow Control");
 801
 802         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 803             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 804             OID_AUTO, "reg_dump",
 805             CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 0,
 806             em_get_regs, "A", "Dump Registers");
 807
 808         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 809             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 810             OID_AUTO, "rs_dump",
 811             CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, adapter, 0,
 812             em_get_rs, "I", "Dump RS indexes");
 813
 814         /* Determine hardware and mac info */
 815         em_identify_hardware(ctx);
 816
 817         scctx->isc_tx_nsegments = EM_MAX_SCATTER;
 818         scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
 819         if (bootverbose)
 820                 device_printf(dev, "attach_pre capping queues at %d\n",
 821                     scctx->isc_ntxqsets_max);
 822
 823         if (adapter->hw.mac.type >= igb_mac_min) {
 824                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
 825                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
 826                 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
 827                 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
 828                 scctx->isc_txrx = &igb_txrx;
 829                 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
 830                 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 831                 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 832                 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS;
 833                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO |
 834                      CSUM_IP6_TCP | CSUM_IP6_UDP;
 835                 if (adapter->hw.mac.type != e1000_82575)
 836                         scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
 837                 /*
 838                 ** Some new devices, as with ixgbe, now may
 839                 ** use a different BAR, so we need to keep
 840                 ** track of which is used.
 841                 */
 842                 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR);
 843                 if (pci_read_config(dev, scctx->isc_msix_bar, 4) == 0)
 844                         scctx->isc_msix_bar += 4;
 845         } else if (adapter->hw.mac.type >= em_mac_min) {
 846                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 847                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
 848                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 849                 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
 850                 scctx->isc_txrx = &em_txrx;
 851                 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
 852                 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 853                 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 854                 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS;
 855                 /*
 856                  * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO}
 857                  * by default as we don't have workarounds for all associated
 858                  * silicon errata.  E. g., with several MACs such as 82573E,
 859                  * TSO only works at Gigabit speed and otherwise can cause the
 860                  * hardware to hang (which also would be next to impossible to
 861                  * work around given that already queued TSO-using descriptors
 862                  * would need to be flushed and vlan(4) reconfigured at runtime
 863                  * in case of a link speed change).  Moreover, MACs like 82579
 864                  * still can hang at Gigabit even with all publicly documented
 865                  * TSO workarounds implemented.  Generally, the penality of
 866                  * these workarounds is rather high and may involve copying
 867                  * mbuf data around so advantages of TSO lapse.  Still, TSO may
 868                  * work for a few MACs of this class - at least when sticking
 869                  * with Gigabit - in which case users may enable TSO manually.
 870                  */
 871                 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
 872                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 873                 /*
 874                  * We support MSI-X with 82574 only, but indicate to iflib(4)
 875                  * that it shall give MSI at least a try with other devices.
 876                  */
 877                 if (adapter->hw.mac.type == e1000_82574) {
 878                         scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR);
 879                 } else {
 880                         scctx->isc_msix_bar = -1;
 881                         scctx->isc_disable_msix = 1;
 882                 }
 883         } else {
 884                 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 885                 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
 886                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 887                 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
 888                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP;
 889                 scctx->isc_txrx = &lem_txrx;
 890                 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS;
 891                 if (adapter->hw.mac.type < e1000_82543)
 892                         scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
 893                 /* INTx only */
 894                 scctx->isc_msix_bar = 0;
 895         }
 896
 897         /* Setup PCI resources */
 898         if (em_allocate_pci_resources(ctx)) {
 899                 device_printf(dev, "Allocation of PCI resources failed\n");
 900                 error = ENXIO;
 901                 goto err_pci;
 902         }
 903
 904         /*
 905         ** For ICH8 and family we need to
 906         ** map the flash memory, and this
 907         ** must happen after the MAC is
 908         ** identified
 909         */
 910         if ((hw->mac.type == e1000_ich8lan) ||
 911             (hw->mac.type == e1000_ich9lan) ||
 912             (hw->mac.type == e1000_ich10lan) ||
 913             (hw->mac.type == e1000_pchlan) ||
 914             (hw->mac.type == e1000_pch2lan) ||
 915             (hw->mac.type == e1000_pch_lpt)) {
 916                 int rid = EM_BAR_TYPE_FLASH;
 917                 adapter->flash = bus_alloc_resource_any(dev,
 918                     SYS_RES_MEMORY, &rid, RF_ACTIVE);
 919                 if (adapter->flash == NULL) {
 920                         device_printf(dev, "Mapping of Flash failed\n");
 921                         error = ENXIO;
 922                         goto err_pci;
 923                 }
 924                 /* This is used in the shared code */
 925                 hw->flash_address = (u8 *)adapter->flash;
 926                 adapter->osdep.flash_bus_space_tag =
 927                     rman_get_bustag(adapter->flash);
 928                 adapter->osdep.flash_bus_space_handle =
 929                     rman_get_bushandle(adapter->flash);
 930         }
 931         /*
 932         ** In the new SPT device flash is not  a
 933         ** separate BAR, rather it is also in BAR0,
 934         ** so use the same tag and an offset handle for the
 935         ** FLASH read/write macros in the shared code.
 936         */
 937         else if (hw->mac.type >= e1000_pch_spt) {
 938                 adapter->osdep.flash_bus_space_tag =
 939                     adapter->osdep.mem_bus_space_tag;
 940                 adapter->osdep.flash_bus_space_handle =
 941                     adapter->osdep.mem_bus_space_handle
 942                     + E1000_FLASH_BASE_ADDR;
 943         }
 944
 945         /* Do Shared Code initialization */
 946         error = e1000_setup_init_funcs(hw, TRUE);
 947         if (error) {
 948                 device_printf(dev, "Setup of Shared code failed, error %d\n",
 949                     error);
 950                 error = ENXIO;
 951                 goto err_pci;
 952         }
 953
 954         em_setup_msix(ctx);
 955         e1000_get_bus_info(hw);
 956
 957         /* Set up some sysctls for the tunable interrupt delays */
 958         em_add_int_delay_sysctl(adapter, "rx_int_delay",
 959             "receive interrupt delay in usecs", &adapter->rx_int_delay,
 960             E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
 961         em_add_int_delay_sysctl(adapter, "tx_int_delay",
 962             "transmit interrupt delay in usecs", &adapter->tx_int_delay,
 963             E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
 964         em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
 965             "receive interrupt delay limit in usecs",
 966             &adapter->rx_abs_int_delay,
 967             E1000_REGISTER(hw, E1000_RADV),
 968             em_rx_abs_int_delay_dflt);
 969         em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
 970             "transmit interrupt delay limit in usecs",
 971             &adapter->tx_abs_int_delay,
 972             E1000_REGISTER(hw, E1000_TADV),
 973             em_tx_abs_int_delay_dflt);
 974         em_add_int_delay_sysctl(adapter, "itr",
 975             "interrupt delay limit in usecs/4",
 976             &adapter->tx_itr,
 977             E1000_REGISTER(hw, E1000_ITR),
 978             DEFAULT_ITR);
 979
 980         hw->mac.autoneg = DO_AUTO_NEG;
 981         hw->phy.autoneg_wait_to_complete = FALSE;
 982         hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 983
 984         if (adapter->hw.mac.type < em_mac_min) {
 985                 e1000_init_script_state_82541(&adapter->hw, TRUE);
 986                 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
 987         }
 988         /* Copper options */
 989         if (hw->phy.media_type == e1000_media_type_copper) {
 990                 hw->phy.mdix = AUTO_ALL_MODES;
 991                 hw->phy.disable_polarity_correction = FALSE;
 992                 hw->phy.ms_type = EM_MASTER_SLAVE;
 993         }
 994
 995         /*
 996          * Set the frame limits assuming
 997          * standard ethernet sized frames.
 998          */
 999         scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
1000             ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
1001
1002         /*
1003          * This controls when hardware reports transmit completion
1004          * status.
1005          */
1006         hw->mac.report_tx_early = 1;
1007
1008         /* Allocate multicast array memory. */
1009         adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN *
1010             MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
1011         if (adapter->mta == NULL) {
1012                 device_printf(dev, "Can not allocate multicast setup array\n");
1013                 error = ENOMEM;
1014                 goto err_late;
1015         }
1016
1017         /* Check SOL/IDER usage */
1018         if (e1000_check_reset_block(hw))
1019                 device_printf(dev, "PHY reset is blocked"
1020                               " due to SOL/IDER session.\n");
1021
1022         /* Sysctl for setting Energy Efficient Ethernet */
1023         hw->dev_spec.ich8lan.eee_disable = eee_setting;
1024         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1025             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1026             OID_AUTO, "eee_control",
1027             CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
1028             adapter, 0, em_sysctl_eee, "I",
1029             "Disable Energy Efficient Ethernet");
1030
1031         /*
1032         ** Start from a known state, this is
1033         ** important in reading the nvm and
1034         ** mac from that.
1035         */
1036         e1000_reset_hw(hw);
1037
1038         /* Make sure we have a good EEPROM before we read from it */
1039         if (e1000_validate_nvm_checksum(hw) < 0) {
1040                 /*
1041                 ** Some PCI-E parts fail the first check due to
1042                 ** the link being in sleep state, call it again,
1043                 ** if it fails a second time its a real issue.
1044                 */
1045                 if (e1000_validate_nvm_checksum(hw) < 0) {
1046                         device_printf(dev,
1047                             "The EEPROM Checksum Is Not Valid\n");
1048                         error = EIO;
1049                         goto err_late;
1050                 }
1051         }
1052
1053         /* Copy the permanent MAC address out of the EEPROM */
1054         if (e1000_read_mac_addr(hw) < 0) {
1055                 device_printf(dev, "EEPROM read error while reading MAC"
1056                               " address\n");
1057                 error = EIO;
1058                 goto err_late;
1059         }
1060
1061         if (!em_is_valid_ether_addr(hw->mac.addr)) {
1062                 device_printf(dev, "Invalid MAC address\n");
1063                 error = EIO;
1064                 goto err_late;
1065         }
1066
1067         /* Disable ULP support */
1068         e1000_disable_ulp_lpt_lp(hw, TRUE);
1069
1070         /*
1071          * Get Wake-on-Lan and Management info for later use
1072          */
1073         em_get_wakeup(ctx);
1074
1075         /* Enable only WOL MAGIC by default */
1076         scctx->isc_capenable &= ~IFCAP_WOL;
1077         if (adapter->wol != 0)
1078                 scctx->isc_capenable |= IFCAP_WOL_MAGIC;
1079
1080         iflib_set_mac(ctx, hw->mac.addr);
1081
1082         return (0);
1083
1084 err_late:
1085         em_release_hw_control(adapter);
1086 err_pci:
1087         em_free_pci_resources(ctx);
1088         free(adapter->mta, M_DEVBUF);
1089
1090         return (error);
1091 }
1092
1093 static int
1094 em_if_attach_post(if_ctx_t ctx)
1095 {
1096         struct adapter *adapter = iflib_get_softc(ctx);
1097         struct e1000_hw *hw = &adapter->hw;
1098         int error = 0;
1099
1100         /* Setup OS specific network interface */
1101         error = em_setup_interface(ctx);
1102         if (error != 0) {
1103                 goto err_late;
1104         }
1105
1106         em_reset(ctx);
1107
1108         /* Initialize statistics */
1109         em_update_stats_counters(adapter);
1110         hw->mac.get_link_status = 1;
1111         em_if_update_admin_status(ctx);
1112         em_add_hw_stats(adapter);
1113
1114         /* Non-AMT based hardware can now take control from firmware */
1115         if (adapter->has_manage && !adapter->has_amt)
1116                 em_get_hw_control(adapter);
1117
1118         INIT_DEBUGOUT("em_if_attach_post: end");
1119
1120         return (error);
1121
1122 err_late:
1123         em_release_hw_control(adapter);
1124         em_free_pci_resources(ctx);
1125         em_if_queues_free(ctx);
1126         free(adapter->mta, M_DEVBUF);
1127
1128         return (error);
1129 }
1130
1131 /*********************************************************************
1132  *  Device removal routine
1133  *
1134  *  The detach entry point is called when the driver is being removed.
1135  *  This routine stops the adapter and deallocates all the resources
1136  *  that were allocated for driver operation.
1137  *
1138  *  return 0 on success, positive on failure
1139  *********************************************************************/
1140 static int
1141 em_if_detach(if_ctx_t ctx)
1142 {
1143         struct adapter  *adapter = iflib_get_softc(ctx);
1144
1145         INIT_DEBUGOUT("em_if_detach: begin");
1146
1147         e1000_phy_hw_reset(&adapter->hw);
1148
1149         em_release_manageability(adapter);
1150         em_release_hw_control(adapter);
1151         em_free_pci_resources(ctx);
1152
1153         return (0);
1154 }
1155
1156 /*********************************************************************
1157  *
1158  *  Shutdown entry point
1159  *
1160  **********************************************************************/
1161
1162 static int
1163 em_if_shutdown(if_ctx_t ctx)
1164 {
1165         return em_if_suspend(ctx);
1166 }
1167
1168 /*
1169  * Suspend/resume device methods.
1170  */
1171 static int
1172 em_if_suspend(if_ctx_t ctx)
1173 {
1174         struct adapter *adapter = iflib_get_softc(ctx);
1175
1176         em_release_manageability(adapter);
1177         em_release_hw_control(adapter);
1178         em_enable_wakeup(ctx);
1179         return (0);
1180 }
1181
1182 static int
1183 em_if_resume(if_ctx_t ctx)
1184 {
1185         struct adapter *adapter = iflib_get_softc(ctx);
1186
1187         if (adapter->hw.mac.type == e1000_pch2lan)
1188                 e1000_resume_workarounds_pchlan(&adapter->hw);
1189         em_if_init(ctx);
1190         em_init_manageability(adapter);
1191
1192         return(0);
1193 }
1194
1195 static int
1196 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1197 {
1198         int max_frame_size;
1199         struct adapter *adapter = iflib_get_softc(ctx);
1200         if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1201
1202          IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1203
1204         switch (adapter->hw.mac.type) {
1205         case e1000_82571:
1206         case e1000_82572:
1207         case e1000_ich9lan:
1208         case e1000_ich10lan:
1209         case e1000_pch2lan:
1210         case e1000_pch_lpt:
1211         case e1000_pch_spt:
1212         case e1000_pch_cnp:
1213         case e1000_82574:
1214         case e1000_82583:
1215         case e1000_80003es2lan:
1216                 /* 9K Jumbo Frame size */
1217                 max_frame_size = 9234;
1218                 break;
1219         case e1000_pchlan:
1220                 max_frame_size = 4096;
1221                 break;
1222         case e1000_82542:
1223         case e1000_ich8lan:
1224                 /* Adapters that do not support jumbo frames */
1225                 max_frame_size = ETHER_MAX_LEN;
1226                 break;
1227         default:
1228                 if (adapter->hw.mac.type >= igb_mac_min)
1229                         max_frame_size = 9234;
1230                 else /* lem */
1231                         max_frame_size = MAX_JUMBO_FRAME_SIZE;
1232         }
1233         if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1234                 return (EINVAL);
1235         }
1236
1237         scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
1238             mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1239         return (0);
1240 }
1241
1242 /*********************************************************************
1243  *  Init entry point
1244  *
1245  *  This routine is used in two ways. It is used by the stack as
1246  *  init entry point in network interface structure. It is also used
1247  *  by the driver as a hw/sw initialization routine to get to a
1248  *  consistent state.
1249  *
1250  **********************************************************************/
1251 static void
1252 em_if_init(if_ctx_t ctx)
1253 {
1254         struct adapter *adapter = iflib_get_softc(ctx);
1255         if_softc_ctx_t scctx = adapter->shared;
1256         struct ifnet *ifp = iflib_get_ifp(ctx);
1257         struct em_tx_queue *tx_que;
1258         int i;
1259
1260         INIT_DEBUGOUT("em_if_init: begin");
1261
1262         /* Get the latest mac address, User can use a LAA */
1263         bcopy(if_getlladdr(ifp), adapter->hw.mac.addr,
1264             ETHER_ADDR_LEN);
1265
1266         /* Put the address into the Receive Address Array */
1267         e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1268
1269         /*
1270          * With the 82571 adapter, RAR[0] may be overwritten
1271          * when the other port is reset, we make a duplicate
1272          * in RAR[14] for that eventuality, this assures
1273          * the interface continues to function.
1274          */
1275         if (adapter->hw.mac.type == e1000_82571) {
1276                 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1277                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1278                     E1000_RAR_ENTRIES - 1);
1279         }
1280
1281
1282         /* Initialize the hardware */
1283         em_reset(ctx);
1284         em_if_update_admin_status(ctx);
1285
1286         for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) {
1287                 struct tx_ring *txr = &tx_que->txr;
1288
1289                 txr->tx_rs_cidx = txr->tx_rs_pidx;
1290
1291                 /* Initialize the last processed descriptor to be the end of
1292                  * the ring, rather than the start, so that we avoid an
1293                  * off-by-one error when calculating how many descriptors are
1294                  * done in the credits_update function.
1295                  */
1296                 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
1297         }
1298
1299         /* Setup VLAN support, basic and offload if available */
1300         E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1301
1302         /* Clear bad data from Rx FIFOs */
1303         if (adapter->hw.mac.type >= igb_mac_min)
1304                 e1000_rx_fifo_flush_82575(&adapter->hw);
1305
1306         /* Configure for OS presence */
1307         em_init_manageability(adapter);
1308
1309         /* Prepare transmit descriptors and buffers */
1310         em_initialize_transmit_unit(ctx);
1311
1312         /* Setup Multicast table */
1313         em_if_multi_set(ctx);
1314
1315         adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx);
1316         em_initialize_receive_unit(ctx);
1317
1318         /* Use real VLAN Filter support? */
1319         if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1320                 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
1321                         /* Use real VLAN Filter support */
1322                         em_setup_vlan_hw_support(adapter);
1323                 else {
1324                         u32 ctrl;
1325                         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1326                         ctrl |= E1000_CTRL_VME;
1327                         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1328                 }
1329         }
1330
1331         /* Don't lose promiscuous settings */
1332         em_if_set_promisc(ctx, IFF_PROMISC);
1333         e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1334
1335         /* MSI-X configuration for 82574 */
1336         if (adapter->hw.mac.type == e1000_82574) {
1337                 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1338
1339                 tmp |= E1000_CTRL_EXT_PBA_CLR;
1340                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1341                 /* Set the IVAR - interrupt vector routing. */
1342                 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars);
1343         } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1344                 igb_configure_queues(adapter);
1345
1346         /* this clears any pending interrupts */
1347         E1000_READ_REG(&adapter->hw, E1000_ICR);
1348         E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC);
1349
1350         /* AMT based hardware can now take control from firmware */
1351         if (adapter->has_manage && adapter->has_amt)
1352                 em_get_hw_control(adapter);
1353
1354         /* Set Energy Efficient Ethernet */
1355         if (adapter->hw.mac.type >= igb_mac_min &&
1356             adapter->hw.phy.media_type == e1000_media_type_copper) {
1357                 if (adapter->hw.mac.type == e1000_i354)
1358                         e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
1359                 else
1360                         e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
1361         }
1362 }
1363
1364 /*********************************************************************
1365  *
1366  *  Fast Legacy/MSI Combined Interrupt Service routine
1367  *
1368  *********************************************************************/
1369 int
1370 em_intr(void *arg)
1371 {
1372         struct adapter *adapter = arg;
1373         if_ctx_t ctx = adapter->ctx;
1374         u32 reg_icr;
1375
1376         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1377
1378         /* Hot eject? */
1379         if (reg_icr == 0xffffffff)
1380                 return FILTER_STRAY;
1381
1382         /* Definitely not our interrupt. */
1383         if (reg_icr == 0x0)
1384                 return FILTER_STRAY;
1385
1386         /*
1387          * Starting with the 82571 chip, bit 31 should be used to
1388          * determine whether the interrupt belongs to us.
1389          */
1390         if (adapter->hw.mac.type >= e1000_82571 &&
1391             (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1392                 return FILTER_STRAY;
1393
1394         /*
1395          * Only MSI-X interrupts have one-shot behavior by taking advantage
1396          * of the EIAC register.  Thus, explicitly disable interrupts.  This
1397          * also works around the MSI message reordering errata on certain
1398          * systems.
1399          */
1400         IFDI_INTR_DISABLE(ctx);
1401
1402         /* Link status change */
1403         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))
1404                 em_handle_link(ctx);
1405
1406         if (reg_icr & E1000_ICR_RXO)
1407                 adapter->rx_overruns++;
1408
1409         return (FILTER_SCHEDULE_THREAD);
1410 }
1411
1412 static int
1413 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1414 {
1415         struct adapter *adapter = iflib_get_softc(ctx);
1416         struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1417
1418         E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims);
1419         return (0);
1420 }
1421
1422 static int
1423 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1424 {
1425         struct adapter *adapter = iflib_get_softc(ctx);
1426         struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1427
1428         E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims);
1429         return (0);
1430 }
1431
1432 static int
1433 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1434 {
1435         struct adapter *adapter = iflib_get_softc(ctx);
1436         struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1437
1438         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims);
1439         return (0);
1440 }
1441
1442 static int
1443 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1444 {
1445         struct adapter *adapter = iflib_get_softc(ctx);
1446         struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1447
1448         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims);
1449         return (0);
1450 }
1451
1452 /*********************************************************************
1453  *
1454  *  MSI-X RX Interrupt Service routine
1455  *
1456  **********************************************************************/
1457 static int
1458 em_msix_que(void *arg)
1459 {
1460         struct em_rx_queue *que = arg;
1461
1462         ++que->irqs;
1463
1464         return (FILTER_SCHEDULE_THREAD);
1465 }
1466
1467 /*********************************************************************
1468  *
1469  *  MSI-X Link Fast Interrupt Service routine
1470  *
1471  **********************************************************************/
1472 static int
1473 em_msix_link(void *arg)
1474 {
1475         struct adapter *adapter = arg;
1476         u32 reg_icr;
1477
1478         ++adapter->link_irq;
1479         MPASS(adapter->hw.back != NULL);
1480         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1481
1482         if (reg_icr & E1000_ICR_RXO)
1483                 adapter->rx_overruns++;
1484
1485         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1486                 em_handle_link(adapter->ctx);
1487         } else if (adapter->hw.mac.type == e1000_82574) {
1488                 /* Only re-arm 82574 if em_if_update_admin_status() won't. */
1489                 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK |
1490                     E1000_IMS_LSC);
1491         }
1492
1493         if (adapter->hw.mac.type == e1000_82574) {
1494                 /*
1495                  * Because we must read the ICR for this interrupt it may
1496                  * clear other causes using autoclear, for this reason we
1497                  * simply create a soft interrupt for all these vectors.
1498                  */
1499                 if (reg_icr)
1500                         E1000_WRITE_REG(&adapter->hw, E1000_ICS, adapter->ims);
1501         } else {
1502                 /* Re-arm unconditionally */
1503                 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC);
1504                 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1505         }
1506
1507         return (FILTER_HANDLED);
1508 }
1509
1510 static void
1511 em_handle_link(void *context)
1512 {
1513         if_ctx_t ctx = context;
1514         struct adapter *adapter = iflib_get_softc(ctx);
1515
1516         adapter->hw.mac.get_link_status = 1;
1517         iflib_admin_intr_deferred(ctx);
1518 }
1519
1520 /*********************************************************************
1521  *
1522  *  Media Ioctl callback
1523  *
1524  *  This routine is called whenever the user queries the status of
1525  *  the interface using ifconfig.
1526  *
1527  **********************************************************************/
1528 static void
1529 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1530 {
1531         struct adapter *adapter = iflib_get_softc(ctx);
1532         u_char fiber_type = IFM_1000_SX;
1533
1534         INIT_DEBUGOUT("em_if_media_status: begin");
1535
1536         iflib_admin_intr_deferred(ctx);
1537
1538         ifmr->ifm_status = IFM_AVALID;
1539         ifmr->ifm_active = IFM_ETHER;
1540
1541         if (!adapter->link_active) {
1542                 return;
1543         }
1544
1545         ifmr->ifm_status |= IFM_ACTIVE;
1546
1547         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
1548             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1549                 if (adapter->hw.mac.type == e1000_82545)
1550                         fiber_type = IFM_1000_LX;
1551                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1552         } else {
1553                 switch (adapter->link_speed) {
1554                 case 10:
1555                         ifmr->ifm_active |= IFM_10_T;
1556                         break;
1557                 case 100:
1558                         ifmr->ifm_active |= IFM_100_TX;
1559                         break;
1560                 case 1000:
1561                         ifmr->ifm_active |= IFM_1000_T;
1562                         break;
1563                 }
1564                 if (adapter->link_duplex == FULL_DUPLEX)
1565                         ifmr->ifm_active |= IFM_FDX;
1566                 else
1567                         ifmr->ifm_active |= IFM_HDX;
1568         }
1569 }
1570
1571 /*********************************************************************
1572  *
1573  *  Media Ioctl callback
1574  *
1575  *  This routine is called when the user changes speed/duplex using
1576  *  media/mediopt option with ifconfig.
1577  *
1578  **********************************************************************/
1579 static int
1580 em_if_media_change(if_ctx_t ctx)
1581 {
1582         struct adapter *adapter = iflib_get_softc(ctx);
1583         struct ifmedia *ifm = iflib_get_media(ctx);
1584
1585         INIT_DEBUGOUT("em_if_media_change: begin");
1586
1587         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1588                 return (EINVAL);
1589
1590         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1591         case IFM_AUTO:
1592                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1593                 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1594                 break;
1595         case IFM_1000_LX:
1596         case IFM_1000_SX:
1597         case IFM_1000_T:
1598                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1599                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1600                 break;
1601         case IFM_100_TX:
1602                 adapter->hw.mac.autoneg = FALSE;
1603                 adapter->hw.phy.autoneg_advertised = 0;
1604                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1605                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1606                 else
1607                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1608                 break;
1609         case IFM_10_T:
1610                 adapter->hw.mac.autoneg = FALSE;
1611                 adapter->hw.phy.autoneg_advertised = 0;
1612                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1613                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1614                 else
1615                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1616                 break;
1617         default:
1618                 device_printf(adapter->dev, "Unsupported media type\n");
1619         }
1620
1621         em_if_init(ctx);
1622
1623         return (0);
1624 }
1625
1626 static int
1627 em_if_set_promisc(if_ctx_t ctx, int flags)
1628 {
1629         struct adapter *adapter = iflib_get_softc(ctx);
1630         u32 reg_rctl;
1631
1632         em_disable_promisc(ctx);
1633
1634         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1635
1636         if (flags & IFF_PROMISC) {
1637                 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1638                 /* Turn this on if you want to see bad packets */
1639                 if (em_debug_sbp)
1640                         reg_rctl |= E1000_RCTL_SBP;
1641                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1642         } else if (flags & IFF_ALLMULTI) {
1643                 reg_rctl |= E1000_RCTL_MPE;
1644                 reg_rctl &= ~E1000_RCTL_UPE;
1645                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1646         }
1647         return (0);
1648 }
1649
1650 static void
1651 em_disable_promisc(if_ctx_t ctx)
1652 {
1653         struct adapter *adapter = iflib_get_softc(ctx);
1654         struct ifnet *ifp = iflib_get_ifp(ctx);
1655         u32 reg_rctl;
1656         int mcnt = 0;
1657
1658         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1659         reg_rctl &= (~E1000_RCTL_UPE);
1660         if (if_getflags(ifp) & IFF_ALLMULTI)
1661                 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1662         else
1663                 mcnt = if_llmaddr_count(ifp);
1664         /* Don't disable if in MAX groups */
1665         if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1666                 reg_rctl &=  (~E1000_RCTL_MPE);
1667         reg_rctl &=  (~E1000_RCTL_SBP);
1668         E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1669 }
1670
1671
1672 static u_int
1673 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1674 {
1675         u8 *mta = arg;
1676
1677         if (cnt == MAX_NUM_MULTICAST_ADDRESSES)
1678                 return (1);
1679
1680         bcopy(LLADDR(sdl), &mta[cnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1681
1682         return (1);
1683 }
1684
1685 /*********************************************************************
1686  *  Multicast Update
1687  *
1688  *  This routine is called whenever multicast address list is updated.
1689  *
1690  **********************************************************************/
1691
1692 static void
1693 em_if_multi_set(if_ctx_t ctx)
1694 {
1695         struct adapter *adapter = iflib_get_softc(ctx);
1696         struct ifnet *ifp = iflib_get_ifp(ctx);
1697         u32 reg_rctl = 0;
1698         u8  *mta; /* Multicast array memory */
1699         int mcnt = 0;
1700
1701         IOCTL_DEBUGOUT("em_set_multi: begin");
1702
1703         mta = adapter->mta;
1704         bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1705
1706         if (adapter->hw.mac.type == e1000_82542 &&
1707             adapter->hw.revision_id == E1000_REVISION_2) {
1708                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1709                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1710                         e1000_pci_clear_mwi(&adapter->hw);
1711                 reg_rctl |= E1000_RCTL_RST;
1712                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1713                 msec_delay(5);
1714         }
1715
1716         mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta);
1717
1718         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1719                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1720                 reg_rctl |= E1000_RCTL_MPE;
1721                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1722         } else
1723                 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
1724
1725         if (adapter->hw.mac.type == e1000_82542 &&
1726             adapter->hw.revision_id == E1000_REVISION_2) {
1727                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1728                 reg_rctl &= ~E1000_RCTL_RST;
1729                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1730                 msec_delay(5);
1731                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1732                         e1000_pci_set_mwi(&adapter->hw);
1733         }
1734 }
1735
1736 /*********************************************************************
1737  *  Timer routine
1738  *
1739  *  This routine schedules em_if_update_admin_status() to check for
1740  *  link status and to gather statistics as well as to perform some
1741  *  controller-specific hardware patting.
1742  *
1743  **********************************************************************/
1744 static void
1745 em_if_timer(if_ctx_t ctx, uint16_t qid)
1746 {
1747
1748         if (qid != 0)
1749                 return;
1750
1751         iflib_admin_intr_deferred(ctx);
1752 }
1753
1754 static void
1755 em_if_update_admin_status(if_ctx_t ctx)
1756 {
1757         struct adapter *adapter = iflib_get_softc(ctx);
1758         struct e1000_hw *hw = &adapter->hw;
1759         device_t dev = iflib_get_dev(ctx);
1760         u32 link_check, thstat, ctrl;
1761
1762         link_check = thstat = ctrl = 0;
1763         /* Get the cached link value or read phy for real */
1764         switch (hw->phy.media_type) {
1765         case e1000_media_type_copper:
1766                 if (hw->mac.get_link_status) {
1767                         if (hw->mac.type == e1000_pch_spt)
1768                                 msec_delay(50);
1769                         /* Do the work to read phy */
1770                         e1000_check_for_link(hw);
1771                         link_check = !hw->mac.get_link_status;
1772                         if (link_check) /* ESB2 fix */
1773                                 e1000_cfg_on_link_up(hw);
1774                 } else {
1775                         link_check = TRUE;
1776                 }
1777                 break;
1778         case e1000_media_type_fiber:
1779                 e1000_check_for_link(hw);
1780                 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1781                             E1000_STATUS_LU);
1782                 break;
1783         case e1000_media_type_internal_serdes:
1784                 e1000_check_for_link(hw);
1785                 link_check = adapter->hw.mac.serdes_has_link;
1786                 break;
1787         /* VF device is type_unknown */
1788         case e1000_media_type_unknown:
1789                 e1000_check_for_link(hw);
1790                 link_check = !hw->mac.get_link_status;
1791                 /* FALLTHROUGH */
1792         default:
1793                 break;
1794         }
1795
1796         /* Check for thermal downshift or shutdown */
1797         if (hw->mac.type == e1000_i350) {
1798                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1799                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1800         }
1801
1802         /* Now check for a transition */
1803         if (link_check && (adapter->link_active == 0)) {
1804                 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
1805                     &adapter->link_duplex);
1806                 /* Check if we must disable SPEED_MODE bit on PCI-E */
1807                 if ((adapter->link_speed != SPEED_1000) &&
1808                     ((hw->mac.type == e1000_82571) ||
1809                     (hw->mac.type == e1000_82572))) {
1810                         int tarc0;
1811                         tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1812                         tarc0 &= ~TARC_SPEED_MODE_BIT;
1813                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1814                 }
1815                 if (bootverbose)
1816                         device_printf(dev, "Link is up %d Mbps %s\n",
1817                             adapter->link_speed,
1818                             ((adapter->link_duplex == FULL_DUPLEX) ?
1819                             "Full Duplex" : "Half Duplex"));
1820                 adapter->link_active = 1;
1821                 adapter->smartspeed = 0;
1822                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) ==
1823                     E1000_CTRL_EXT_LINK_MODE_GMII &&
1824                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1825                         device_printf(dev, "Link: thermal downshift\n");
1826                 /* Delay Link Up for Phy update */
1827                 if (((hw->mac.type == e1000_i210) ||
1828                     (hw->mac.type == e1000_i211)) &&
1829                     (hw->phy.id == I210_I_PHY_ID))
1830                         msec_delay(I210_LINK_DELAY);
1831                 /* Reset if the media type changed. */
1832                 if ((hw->dev_spec._82575.media_changed) &&
1833                         (adapter->hw.mac.type >= igb_mac_min)) {
1834                         hw->dev_spec._82575.media_changed = false;
1835                         adapter->flags |= IGB_MEDIA_RESET;
1836                         em_reset(ctx);
1837                 }
1838                 iflib_link_state_change(ctx, LINK_STATE_UP,
1839                     IF_Mbps(adapter->link_speed));
1840         } else if (!link_check && (adapter->link_active == 1)) {
1841                 adapter->link_speed = 0;
1842                 adapter->link_duplex = 0;
1843                 adapter->link_active = 0;
1844                 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
1845         }
1846         em_update_stats_counters(adapter);
1847
1848         /* Reset LAA into RAR[0] on 82571 */
1849         if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw))
1850                 e1000_rar_set(hw, hw->mac.addr, 0);
1851
1852         if (hw->mac.type < em_mac_min)
1853                 lem_smartspeed(adapter);
1854         else if (hw->mac.type == e1000_82574 &&
1855             adapter->intr_type == IFLIB_INTR_MSIX)
1856                 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK |
1857                     E1000_IMS_LSC);
1858 }
1859
1860 static void
1861 em_if_watchdog_reset(if_ctx_t ctx)
1862 {
1863         struct adapter *adapter = iflib_get_softc(ctx);
1864
1865         /*
1866          * Just count the event; iflib(4) will already trigger a
1867          * sufficient reset of the controller.
1868          */
1869         adapter->watchdog_events++;
1870 }
1871
1872 /*********************************************************************
1873  *
1874  *  This routine disables all traffic on the adapter by issuing a
1875  *  global reset on the MAC.
1876  *
1877  **********************************************************************/
1878 static void
1879 em_if_stop(if_ctx_t ctx)
1880 {
1881         struct adapter *adapter = iflib_get_softc(ctx);
1882
1883         INIT_DEBUGOUT("em_if_stop: begin");
1884
1885         e1000_reset_hw(&adapter->hw);
1886         if (adapter->hw.mac.type >= e1000_82544)
1887                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0);
1888
1889         e1000_led_off(&adapter->hw);
1890         e1000_cleanup_led(&adapter->hw);
1891 }
1892
1893 /*********************************************************************
1894  *
1895  *  Determine hardware revision.
1896  *
1897  **********************************************************************/
1898 static void
1899 em_identify_hardware(if_ctx_t ctx)
1900 {
1901         device_t dev = iflib_get_dev(ctx);
1902         struct adapter *adapter = iflib_get_softc(ctx);
1903
1904         /* Make sure our PCI config space has the necessary stuff set */
1905         adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1906
1907         /* Save off the information about this board */
1908         adapter->hw.vendor_id = pci_get_vendor(dev);
1909         adapter->hw.device_id = pci_get_device(dev);
1910         adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1911         adapter->hw.subsystem_vendor_id =
1912             pci_read_config(dev, PCIR_SUBVEND_0, 2);
1913         adapter->hw.subsystem_device_id =
1914             pci_read_config(dev, PCIR_SUBDEV_0, 2);
1915
1916         /* Do Shared Code Init and Setup */
1917         if (e1000_set_mac_type(&adapter->hw)) {
1918                 device_printf(dev, "Setup init failure\n");
1919                 return;
1920         }
1921 }
1922
1923 static int
1924 em_allocate_pci_resources(if_ctx_t ctx)
1925 {
1926         struct adapter *adapter = iflib_get_softc(ctx);
1927         device_t dev = iflib_get_dev(ctx);
1928         int rid, val;
1929
1930         rid = PCIR_BAR(0);
1931         adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1932             &rid, RF_ACTIVE);
1933         if (adapter->memory == NULL) {
1934                 device_printf(dev, "Unable to allocate bus resource: memory\n");
1935                 return (ENXIO);
1936         }
1937         adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory);
1938         adapter->osdep.mem_bus_space_handle =
1939             rman_get_bushandle(adapter->memory);
1940         adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle;
1941
1942         /* Only older adapters use IO mapping */
1943         if (adapter->hw.mac.type < em_mac_min &&
1944             adapter->hw.mac.type > e1000_82543) {
1945                 /* Figure our where our IO BAR is ? */
1946                 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1947                         val = pci_read_config(dev, rid, 4);
1948                         if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1949                                 break;
1950                         }
1951                         rid += 4;
1952                         /* check for 64bit BAR */
1953                         if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1954                                 rid += 4;
1955                 }
1956                 if (rid >= PCIR_CIS) {
1957                         device_printf(dev, "Unable to locate IO BAR\n");
1958                         return (ENXIO);
1959                 }
1960                 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
1961                     &rid, RF_ACTIVE);
1962                 if (adapter->ioport == NULL) {
1963                         device_printf(dev, "Unable to allocate bus resource: "
1964                             "ioport\n");
1965                         return (ENXIO);
1966                 }
1967                 adapter->hw.io_base = 0;
1968                 adapter->osdep.io_bus_space_tag =
1969                     rman_get_bustag(adapter->ioport);
1970                 adapter->osdep.io_bus_space_handle =
1971                     rman_get_bushandle(adapter->ioport);
1972         }
1973
1974         adapter->hw.back = &adapter->osdep;
1975
1976         return (0);
1977 }
1978
1979 /*********************************************************************
1980  *
1981  *  Set up the MSI-X Interrupt handlers
1982  *
1983  **********************************************************************/
1984 static int
1985 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
1986 {
1987         struct adapter *adapter = iflib_get_softc(ctx);
1988         struct em_rx_queue *rx_que = adapter->rx_queues;
1989         struct em_tx_queue *tx_que = adapter->tx_queues;
1990         int error, rid, i, vector = 0, rx_vectors;
1991         char buf[16];
1992
1993         /* First set up ring resources */
1994         for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) {
1995                 rid = vector + 1;
1996                 snprintf(buf, sizeof(buf), "rxq%d", i);
1997                 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
1998                 if (error) {
1999                         device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
2000                         adapter->rx_num_queues = i + 1;
2001                         goto fail;
2002                 }
2003
2004                 rx_que->msix =  vector;
2005
2006                 /*
2007                  * Set the bit to enable interrupt
2008                  * in E1000_IMS -- bits 20 and 21
2009                  * are for RX0 and RX1, note this has
2010                  * NOTHING to do with the MSI-X vector
2011                  */
2012                 if (adapter->hw.mac.type == e1000_82574) {
2013                         rx_que->eims = 1 << (20 + i);
2014                         adapter->ims |= rx_que->eims;
2015                         adapter->ivars |= (8 | rx_que->msix) << (i * 4);
2016                 } else if (adapter->hw.mac.type == e1000_82575)
2017                         rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
2018                 else
2019                         rx_que->eims = 1 << vector;
2020         }
2021         rx_vectors = vector;
2022
2023         vector = 0;
2024         for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) {
2025                 snprintf(buf, sizeof(buf), "txq%d", i);
2026                 tx_que = &adapter->tx_queues[i];
2027                 iflib_softirq_alloc_generic(ctx,
2028                     &adapter->rx_queues[i % adapter->rx_num_queues].que_irq,
2029                     IFLIB_INTR_TX, tx_que, tx_que->me, buf);
2030
2031                 tx_que->msix = (vector % adapter->rx_num_queues);
2032
2033                 /*
2034                  * Set the bit to enable interrupt
2035                  * in E1000_IMS -- bits 22 and 23
2036                  * are for TX0 and TX1, note this has
2037                  * NOTHING to do with the MSI-X vector
2038                  */
2039                 if (adapter->hw.mac.type == e1000_82574) {
2040                         tx_que->eims = 1 << (22 + i);
2041                         adapter->ims |= tx_que->eims;
2042                         adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
2043                 } else if (adapter->hw.mac.type == e1000_82575) {
2044                         tx_que->eims = E1000_EICR_TX_QUEUE0 << i;
2045                 } else {
2046                         tx_que->eims = 1 << i;
2047                 }
2048         }
2049
2050         /* Link interrupt */
2051         rid = rx_vectors + 1;
2052         error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq");
2053
2054         if (error) {
2055                 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
2056                 goto fail;
2057         }
2058         adapter->linkvec = rx_vectors;
2059         if (adapter->hw.mac.type < igb_mac_min) {
2060                 adapter->ivars |=  (8 | rx_vectors) << 16;
2061                 adapter->ivars |= 0x80000000;
2062         }
2063         return (0);
2064 fail:
2065         iflib_irq_free(ctx, &adapter->irq);
2066         rx_que = adapter->rx_queues;
2067         for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++)
2068                 iflib_irq_free(ctx, &rx_que->que_irq);
2069         return (error);
2070 }
2071
2072 static void
2073 igb_configure_queues(struct adapter *adapter)
2074 {
2075         struct e1000_hw *hw = &adapter->hw;
2076         struct em_rx_queue *rx_que;
2077         struct em_tx_queue *tx_que;
2078         u32 tmp, ivar = 0, newitr = 0;
2079
2080         /* First turn on RSS capability */
2081         if (adapter->hw.mac.type != e1000_82575)
2082                 E1000_WRITE_REG(hw, E1000_GPIE,
2083                     E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
2084                     E1000_GPIE_PBA | E1000_GPIE_NSICR);
2085
2086         /* Turn on MSI-X */
2087         switch (adapter->hw.mac.type) {
2088         case e1000_82580:
2089         case e1000_i350:
2090         case e1000_i354:
2091         case e1000_i210:
2092         case e1000_i211:
2093         case e1000_vfadapt:
2094         case e1000_vfadapt_i350:
2095                 /* RX entries */
2096                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2097                         u32 index = i >> 1;
2098                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2099                         rx_que = &adapter->rx_queues[i];
2100                         if (i & 1) {
2101                                 ivar &= 0xFF00FFFF;
2102                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2103                         } else {
2104                                 ivar &= 0xFFFFFF00;
2105                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2106                         }
2107                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2108                 }
2109                 /* TX entries */
2110                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2111                         u32 index = i >> 1;
2112                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2113                         tx_que = &adapter->tx_queues[i];
2114                         if (i & 1) {
2115                                 ivar &= 0x00FFFFFF;
2116                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2117                         } else {
2118                                 ivar &= 0xFFFF00FF;
2119                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2120                         }
2121                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2122                         adapter->que_mask |= tx_que->eims;
2123                 }
2124
2125                 /* And for the link interrupt */
2126                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2127                 adapter->link_mask = 1 << adapter->linkvec;
2128                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2129                 break;
2130         case e1000_82576:
2131                 /* RX entries */
2132                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2133                         u32 index = i & 0x7; /* Each IVAR has two entries */
2134                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2135                         rx_que = &adapter->rx_queues[i];
2136                         if (i < 8) {
2137                                 ivar &= 0xFFFFFF00;
2138                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2139                         } else {
2140                                 ivar &= 0xFF00FFFF;
2141                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2142                         }
2143                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2144                         adapter->que_mask |= rx_que->eims;
2145                 }
2146                 /* TX entries */
2147                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2148                         u32 index = i & 0x7; /* Each IVAR has two entries */
2149                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2150                         tx_que = &adapter->tx_queues[i];
2151                         if (i < 8) {
2152                                 ivar &= 0xFFFF00FF;
2153                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2154                         } else {
2155                                 ivar &= 0x00FFFFFF;
2156                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2157                         }
2158                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2159                         adapter->que_mask |= tx_que->eims;
2160                 }
2161
2162                 /* And for the link interrupt */
2163                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2164                 adapter->link_mask = 1 << adapter->linkvec;
2165                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2166                 break;
2167
2168         case e1000_82575:
2169                 /* enable MSI-X support*/
2170                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2171                 tmp |= E1000_CTRL_EXT_PBA_CLR;
2172                 /* Auto-Mask interrupts upon ICR read. */
2173                 tmp |= E1000_CTRL_EXT_EIAME;
2174                 tmp |= E1000_CTRL_EXT_IRCA;
2175                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2176
2177                 /* Queues */
2178                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2179                         rx_que = &adapter->rx_queues[i];
2180                         tmp = E1000_EICR_RX_QUEUE0 << i;
2181                         tmp |= E1000_EICR_TX_QUEUE0 << i;
2182                         rx_que->eims = tmp;
2183                         E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2184                             i, rx_que->eims);
2185                         adapter->que_mask |= rx_que->eims;
2186                 }
2187
2188                 /* Link */
2189                 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec),
2190                     E1000_EIMS_OTHER);
2191                 adapter->link_mask |= E1000_EIMS_OTHER;
2192         default:
2193                 break;
2194         }
2195
2196         /* Set the starting interrupt rate */
2197         if (em_max_interrupt_rate > 0)
2198                 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2199
2200         if (hw->mac.type == e1000_82575)
2201                 newitr |= newitr << 16;
2202         else
2203                 newitr |= E1000_EITR_CNT_IGNR;
2204
2205         for (int i = 0; i < adapter->rx_num_queues; i++) {
2206                 rx_que = &adapter->rx_queues[i];
2207                 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2208         }
2209
2210         return;
2211 }
2212
2213 static void
2214 em_free_pci_resources(if_ctx_t ctx)
2215 {
2216         struct adapter *adapter = iflib_get_softc(ctx);
2217         struct em_rx_queue *que = adapter->rx_queues;
2218         device_t dev = iflib_get_dev(ctx);
2219
2220         /* Release all MSI-X queue resources */
2221         if (adapter->intr_type == IFLIB_INTR_MSIX)
2222                 iflib_irq_free(ctx, &adapter->irq);
2223
2224         for (int i = 0; i < adapter->rx_num_queues; i++, que++) {
2225                 iflib_irq_free(ctx, &que->que_irq);
2226         }
2227
2228         if (adapter->memory != NULL) {
2229                 bus_release_resource(dev, SYS_RES_MEMORY,
2230                     rman_get_rid(adapter->memory), adapter->memory);
2231                 adapter->memory = NULL;
2232         }
2233
2234         if (adapter->flash != NULL) {
2235                 bus_release_resource(dev, SYS_RES_MEMORY,
2236                     rman_get_rid(adapter->flash), adapter->flash);
2237                 adapter->flash = NULL;
2238         }
2239
2240         if (adapter->ioport != NULL) {
2241                 bus_release_resource(dev, SYS_RES_IOPORT,
2242                     rman_get_rid(adapter->ioport), adapter->ioport);
2243                 adapter->ioport = NULL;
2244         }
2245 }
2246
2247 /* Set up MSI or MSI-X */
2248 static int
2249 em_setup_msix(if_ctx_t ctx)
2250 {
2251         struct adapter *adapter = iflib_get_softc(ctx);
2252
2253         if (adapter->hw.mac.type == e1000_82574) {
2254                 em_enable_vectors_82574(ctx);
2255         }
2256         return (0);
2257 }
2258
2259 /*********************************************************************
2260  *
2261  *  Workaround for SmartSpeed on 82541 and 82547 controllers
2262  *
2263  **********************************************************************/
2264 static void
2265 lem_smartspeed(struct adapter *adapter)
2266 {
2267         u16 phy_tmp;
2268
2269         if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) ||
2270             adapter->hw.mac.autoneg == 0 ||
2271             (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2272                 return;
2273
2274         if (adapter->smartspeed == 0) {
2275                 /* If Master/Slave config fault is asserted twice,
2276                  * we assume back-to-back */
2277                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2278                 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2279                         return;
2280                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2281                 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2282                         e1000_read_phy_reg(&adapter->hw,
2283                             PHY_1000T_CTRL, &phy_tmp);
2284                         if(phy_tmp & CR_1000T_MS_ENABLE) {
2285                                 phy_tmp &= ~CR_1000T_MS_ENABLE;
2286                                 e1000_write_phy_reg(&adapter->hw,
2287                                     PHY_1000T_CTRL, phy_tmp);
2288                                 adapter->smartspeed++;
2289                                 if(adapter->hw.mac.autoneg &&
2290                                    !e1000_copper_link_autoneg(&adapter->hw) &&
2291                                    !e1000_read_phy_reg(&adapter->hw,
2292                                     PHY_CONTROL, &phy_tmp)) {
2293                                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2294                                                     MII_CR_RESTART_AUTO_NEG);
2295                                         e1000_write_phy_reg(&adapter->hw,
2296                                             PHY_CONTROL, phy_tmp);
2297                                 }
2298                         }
2299                 }
2300                 return;
2301         } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2302                 /* If still no link, perhaps using 2/3 pair cable */
2303                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2304                 phy_tmp |= CR_1000T_MS_ENABLE;
2305                 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2306                 if(adapter->hw.mac.autoneg &&
2307                    !e1000_copper_link_autoneg(&adapter->hw) &&
2308                    !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2309                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2310                                     MII_CR_RESTART_AUTO_NEG);
2311                         e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2312                 }
2313         }
2314         /* Restart process after EM_SMARTSPEED_MAX iterations */
2315         if(adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2316                 adapter->smartspeed = 0;
2317 }
2318
2319 /*********************************************************************
2320  *
2321  *  Initialize the DMA Coalescing feature
2322  *
2323  **********************************************************************/
2324 static void
2325 igb_init_dmac(struct adapter *adapter, u32 pba)
2326 {
2327         device_t        dev = adapter->dev;
2328         struct e1000_hw *hw = &adapter->hw;
2329         u32             dmac, reg = ~E1000_DMACR_DMAC_EN;
2330         u16             hwm;
2331         u16             max_frame_size;
2332
2333         if (hw->mac.type == e1000_i211)
2334                 return;
2335
2336         max_frame_size = adapter->shared->isc_max_frame_size;
2337         if (hw->mac.type > e1000_82580) {
2338
2339                 if (adapter->dmac == 0) { /* Disabling it */
2340                         E1000_WRITE_REG(hw, E1000_DMACR, reg);
2341                         return;
2342                 } else
2343                         device_printf(dev, "DMA Coalescing enabled\n");
2344
2345                 /* Set starting threshold */
2346                 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
2347
2348                 hwm = 64 * pba - max_frame_size / 16;
2349                 if (hwm < 64 * (pba - 6))
2350                         hwm = 64 * (pba - 6);
2351                 reg = E1000_READ_REG(hw, E1000_FCRTC);
2352                 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
2353                 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
2354                     & E1000_FCRTC_RTH_COAL_MASK);
2355                 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
2356
2357
2358                 dmac = pba - max_frame_size / 512;
2359                 if (dmac < pba - 10)
2360                         dmac = pba - 10;
2361                 reg = E1000_READ_REG(hw, E1000_DMACR);
2362                 reg &= ~E1000_DMACR_DMACTHR_MASK;
2363                 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT)
2364                     & E1000_DMACR_DMACTHR_MASK);
2365
2366                 /* transition to L0x or L1 if available..*/
2367                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
2368
2369                 /* Check if status is 2.5Gb backplane connection
2370                 * before configuration of watchdog timer, which is
2371                 * in msec values in 12.8usec intervals
2372                 * watchdog timer= msec values in 32usec intervals
2373                 * for non 2.5Gb connection
2374                 */
2375                 if (hw->mac.type == e1000_i354) {
2376                         int status = E1000_READ_REG(hw, E1000_STATUS);
2377                         if ((status & E1000_STATUS_2P5_SKU) &&
2378                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2379                                 reg |= ((adapter->dmac * 5) >> 6);
2380                         else
2381                                 reg |= (adapter->dmac >> 5);
2382                 } else {
2383                         reg |= (adapter->dmac >> 5);
2384                 }
2385
2386                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2387
2388                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
2389
2390                 /* Set the interval before transition */
2391                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
2392                 if (hw->mac.type == e1000_i350)
2393                         reg |= IGB_DMCTLX_DCFLUSH_DIS;
2394                 /*
2395                 ** in 2.5Gb connection, TTLX unit is 0.4 usec
2396                 ** which is 0x4*2 = 0xA. But delay is still 4 usec
2397                 */
2398                 if (hw->mac.type == e1000_i354) {
2399                         int status = E1000_READ_REG(hw, E1000_STATUS);
2400                         if ((status & E1000_STATUS_2P5_SKU) &&
2401                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2402                                 reg |= 0xA;
2403                         else
2404                                 reg |= 0x4;
2405                 } else {
2406                         reg |= 0x4;
2407                 }
2408
2409                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
2410
2411                 /* free space in tx packet buffer to wake from DMA coal */
2412                 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE -
2413                     (2 * max_frame_size)) >> 6);
2414
2415                 /* make low power state decision controlled by DMA coal */
2416                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2417                 reg &= ~E1000_PCIEMISC_LX_DECISION;
2418                 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
2419
2420         } else if (hw->mac.type == e1000_82580) {
2421                 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2422                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
2423                     reg & ~E1000_PCIEMISC_LX_DECISION);
2424                 E1000_WRITE_REG(hw, E1000_DMACR, 0);
2425         }
2426 }
2427
2428 /*********************************************************************
2429  *
2430  *  Initialize the hardware to a configuration as specified by the
2431  *  adapter structure.
2432  *
2433  **********************************************************************/
2434 static void
2435 em_reset(if_ctx_t ctx)
2436 {
2437         device_t dev = iflib_get_dev(ctx);
2438         struct adapter *adapter = iflib_get_softc(ctx);
2439         struct ifnet *ifp = iflib_get_ifp(ctx);
2440         struct e1000_hw *hw = &adapter->hw;
2441         u16 rx_buffer_size;
2442         u32 pba;
2443
2444         INIT_DEBUGOUT("em_reset: begin");
2445         /* Let the firmware know the OS is in control */
2446         em_get_hw_control(adapter);
2447
2448         /* Set up smart power down as default off on newer adapters. */
2449         if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2450             hw->mac.type == e1000_82572)) {
2451                 u16 phy_tmp = 0;
2452
2453                 /* Speed up time to link by disabling smart power down. */
2454                 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2455                 phy_tmp &= ~IGP02E1000_PM_SPD;
2456                 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2457         }
2458
2459         /*
2460          * Packet Buffer Allocation (PBA)
2461          * Writing PBA sets the receive portion of the buffer
2462          * the remainder is used for the transmit buffer.
2463          */
2464         switch (hw->mac.type) {
2465         /* Total Packet Buffer on these is 48K */
2466         case e1000_82571:
2467         case e1000_82572:
2468         case e1000_80003es2lan:
2469                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2470                 break;
2471         case e1000_82573: /* 82573: Total Packet Buffer is 32K */
2472                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2473                 break;
2474         case e1000_82574:
2475         case e1000_82583:
2476                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2477                 break;
2478         case e1000_ich8lan:
2479                 pba = E1000_PBA_8K;
2480                 break;
2481         case e1000_ich9lan:
2482         case e1000_ich10lan:
2483                 /* Boost Receive side for jumbo frames */
2484                 if (adapter->hw.mac.max_frame_size > 4096)
2485                         pba = E1000_PBA_14K;
2486                 else
2487                         pba = E1000_PBA_10K;
2488                 break;
2489         case e1000_pchlan:
2490         case e1000_pch2lan:
2491         case e1000_pch_lpt:
2492         case e1000_pch_spt:
2493         case e1000_pch_cnp:
2494                 pba = E1000_PBA_26K;
2495                 break;
2496         case e1000_82575:
2497                 pba = E1000_PBA_32K;
2498                 break;
2499         case e1000_82576:
2500         case e1000_vfadapt:
2501                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2502                 pba &= E1000_RXPBS_SIZE_MASK_82576;
2503                 break;
2504         case e1000_82580:
2505         case e1000_i350:
2506         case e1000_i354:
2507         case e1000_vfadapt_i350:
2508                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2509                 pba = e1000_rxpbs_adjust_82580(pba);
2510                 break;
2511         case e1000_i210:
2512         case e1000_i211:
2513                 pba = E1000_PBA_34K;
2514                 break;
2515         default:
2516                 if (adapter->hw.mac.max_frame_size > 8192)
2517                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2518                 else
2519                         pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2520         }
2521
2522         /* Special needs in case of Jumbo frames */
2523         if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) {
2524                 u32 tx_space, min_tx, min_rx;
2525                 pba = E1000_READ_REG(hw, E1000_PBA);
2526                 tx_space = pba >> 16;
2527                 pba &= 0xffff;
2528                 min_tx = (adapter->hw.mac.max_frame_size +
2529                     sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
2530                 min_tx = roundup2(min_tx, 1024);
2531                 min_tx >>= 10;
2532                 min_rx = adapter->hw.mac.max_frame_size;
2533                 min_rx = roundup2(min_rx, 1024);
2534                 min_rx >>= 10;
2535                 if (tx_space < min_tx &&
2536                     ((min_tx - tx_space) < pba)) {
2537                         pba = pba - (min_tx - tx_space);
2538                         /*
2539                          * if short on rx space, rx wins
2540                          * and must trump tx adjustment
2541                          */
2542                         if (pba < min_rx)
2543                                 pba = min_rx;
2544                 }
2545                 E1000_WRITE_REG(hw, E1000_PBA, pba);
2546         }
2547
2548         if (hw->mac.type < igb_mac_min)
2549                 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
2550
2551         INIT_DEBUGOUT1("em_reset: pba=%dK",pba);
2552
2553         /*
2554          * These parameters control the automatic generation (Tx) and
2555          * response (Rx) to Ethernet PAUSE frames.
2556          * - High water mark should allow for at least two frames to be
2557          *   received after sending an XOFF.
2558          * - Low water mark works best when it is very near the high water mark.
2559          *   This allows the receiver to restart by sending XON when it has
2560          *   drained a bit. Here we use an arbitrary value of 1500 which will
2561          *   restart after one full frame is pulled from the buffer. There
2562          *   could be several smaller frames in the buffer and if so they will
2563          *   not trigger the XON until their total number reduces the buffer
2564          *   by 1500.
2565          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2566          */
2567         rx_buffer_size = (pba & 0xffff) << 10;
2568         hw->fc.high_water = rx_buffer_size -
2569             roundup2(adapter->hw.mac.max_frame_size, 1024);
2570         hw->fc.low_water = hw->fc.high_water - 1500;
2571
2572         if (adapter->fc) /* locally set flow control value? */
2573                 hw->fc.requested_mode = adapter->fc;
2574         else
2575                 hw->fc.requested_mode = e1000_fc_full;
2576
2577         if (hw->mac.type == e1000_80003es2lan)
2578                 hw->fc.pause_time = 0xFFFF;
2579         else
2580                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
2581
2582         hw->fc.send_xon = TRUE;
2583
2584         /* Device specific overrides/settings */
2585         switch (hw->mac.type) {
2586         case e1000_pchlan:
2587                 /* Workaround: no TX flow ctrl for PCH */
2588                 hw->fc.requested_mode = e1000_fc_rx_pause;
2589                 hw->fc.pause_time = 0xFFFF; /* override */
2590                 if (if_getmtu(ifp) > ETHERMTU) {
2591                         hw->fc.high_water = 0x3500;
2592                         hw->fc.low_water = 0x1500;
2593                 } else {
2594                         hw->fc.high_water = 0x5000;
2595                         hw->fc.low_water = 0x3000;
2596                 }
2597                 hw->fc.refresh_time = 0x1000;
2598                 break;
2599         case e1000_pch2lan:
2600         case e1000_pch_lpt:
2601         case e1000_pch_spt:
2602         case e1000_pch_cnp:
2603                 hw->fc.high_water = 0x5C20;
2604                 hw->fc.low_water = 0x5048;
2605                 hw->fc.pause_time = 0x0650;
2606                 hw->fc.refresh_time = 0x0400;
2607                 /* Jumbos need adjusted PBA */
2608                 if (if_getmtu(ifp) > ETHERMTU)
2609                         E1000_WRITE_REG(hw, E1000_PBA, 12);
2610                 else
2611                         E1000_WRITE_REG(hw, E1000_PBA, 26);
2612                 break;
2613         case e1000_82575:
2614         case e1000_82576:
2615                 /* 8-byte granularity */
2616                 hw->fc.low_water = hw->fc.high_water - 8;
2617                 break;
2618         case e1000_82580:
2619         case e1000_i350:
2620         case e1000_i354:
2621         case e1000_i210:
2622         case e1000_i211:
2623         case e1000_vfadapt:
2624         case e1000_vfadapt_i350:
2625                 /* 16-byte granularity */
2626                 hw->fc.low_water = hw->fc.high_water - 16;
2627                 break;
2628         case e1000_ich9lan:
2629         case e1000_ich10lan:
2630                 if (if_getmtu(ifp) > ETHERMTU) {
2631                         hw->fc.high_water = 0x2800;
2632                         hw->fc.low_water = hw->fc.high_water - 8;
2633                         break;
2634                 }
2635                 /* FALLTHROUGH */
2636         default:
2637                 if (hw->mac.type == e1000_80003es2lan)
2638                         hw->fc.pause_time = 0xFFFF;
2639                 break;
2640         }
2641
2642         /* Issue a global reset */
2643         e1000_reset_hw(hw);
2644         if (adapter->hw.mac.type >= igb_mac_min) {
2645                 E1000_WRITE_REG(hw, E1000_WUC, 0);
2646         } else {
2647                 E1000_WRITE_REG(hw, E1000_WUFC, 0);
2648                 em_disable_aspm(adapter);
2649         }
2650         if (adapter->flags & IGB_MEDIA_RESET) {
2651                 e1000_setup_init_funcs(hw, TRUE);
2652                 e1000_get_bus_info(hw);
2653                 adapter->flags &= ~IGB_MEDIA_RESET;
2654         }
2655         /* and a re-init */
2656         if (e1000_init_hw(hw) < 0) {
2657                 device_printf(dev, "Hardware Initialization Failed\n");
2658                 return;
2659         }
2660         if (adapter->hw.mac.type >= igb_mac_min)
2661                 igb_init_dmac(adapter, pba);
2662
2663         E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2664         e1000_get_phy_info(hw);
2665         e1000_check_for_link(hw);
2666 }
2667
2668 /*
2669  * Initialise the RSS mapping for NICs that support multiple transmit/
2670  * receive rings.
2671  */
2672
2673 #define RSSKEYLEN 10
2674 static void
2675 em_initialize_rss_mapping(struct adapter *adapter)
2676 {
2677         uint8_t  rss_key[4 * RSSKEYLEN];
2678         uint32_t reta = 0;
2679         struct e1000_hw *hw = &adapter->hw;
2680         int i;
2681
2682         /*
2683          * Configure RSS key
2684          */
2685         arc4rand(rss_key, sizeof(rss_key), 0);
2686         for (i = 0; i < RSSKEYLEN; ++i) {
2687                 uint32_t rssrk = 0;
2688
2689                 rssrk = EM_RSSRK_VAL(rss_key, i);
2690                 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2691         }
2692
2693         /*
2694          * Configure RSS redirect table in following fashion:
2695          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2696          */
2697         for (i = 0; i < sizeof(reta); ++i) {
2698                 uint32_t q;
2699
2700                 q = (i % adapter->rx_num_queues) << 7;
2701                 reta |= q << (8 * i);
2702         }
2703
2704         for (i = 0; i < 32; ++i)
2705                 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2706
2707         E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2708                         E1000_MRQC_RSS_FIELD_IPV4_TCP |
2709                         E1000_MRQC_RSS_FIELD_IPV4 |
2710                         E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2711                         E1000_MRQC_RSS_FIELD_IPV6_EX |
2712                         E1000_MRQC_RSS_FIELD_IPV6);
2713 }
2714
2715 static void
2716 igb_initialize_rss_mapping(struct adapter *adapter)
2717 {
2718         struct e1000_hw *hw = &adapter->hw;
2719         int i;
2720         int queue_id;
2721         u32 reta;
2722         u32 rss_key[10], mrqc, shift = 0;
2723
2724         /* XXX? */
2725         if (adapter->hw.mac.type == e1000_82575)
2726                 shift = 6;
2727
2728         /*
2729          * The redirection table controls which destination
2730          * queue each bucket redirects traffic to.
2731          * Each DWORD represents four queues, with the LSB
2732          * being the first queue in the DWORD.
2733          *
2734          * This just allocates buckets to queues using round-robin
2735          * allocation.
2736          *
2737          * NOTE: It Just Happens to line up with the default
2738          * RSS allocation method.
2739          */
2740
2741         /* Warning FM follows */
2742         reta = 0;
2743         for (i = 0; i < 128; i++) {
2744 #ifdef RSS
2745                 queue_id = rss_get_indirection_to_bucket(i);
2746                 /*
2747                  * If we have more queues than buckets, we'll
2748                  * end up mapping buckets to a subset of the
2749                  * queues.
2750                  *
2751                  * If we have more buckets than queues, we'll
2752                  * end up instead assigning multiple buckets
2753                  * to queues.
2754                  *
2755                  * Both are suboptimal, but we need to handle
2756                  * the case so we don't go out of bounds
2757                  * indexing arrays and such.
2758                  */
2759                 queue_id = queue_id % adapter->rx_num_queues;
2760 #else
2761                 queue_id = (i % adapter->rx_num_queues);
2762 #endif
2763                 /* Adjust if required */
2764                 queue_id = queue_id << shift;
2765
2766                 /*
2767                  * The low 8 bits are for hash value (n+0);
2768                  * The next 8 bits are for hash value (n+1), etc.
2769                  */
2770                 reta = reta >> 8;
2771                 reta = reta | ( ((uint32_t) queue_id) << 24);
2772                 if ((i & 3) == 3) {
2773                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2774                         reta = 0;
2775                 }
2776         }
2777
2778         /* Now fill in hash table */
2779
2780         /*
2781          * MRQC: Multiple Receive Queues Command
2782          * Set queuing to RSS control, number depends on the device.
2783          */
2784         mrqc = E1000_MRQC_ENABLE_RSS_8Q;
2785
2786 #ifdef RSS
2787         /* XXX ew typecasting */
2788         rss_getkey((uint8_t *) &rss_key);
2789 #else
2790         arc4rand(&rss_key, sizeof(rss_key), 0);
2791 #endif
2792         for (i = 0; i < 10; i++)
2793                 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]);
2794
2795         /*
2796          * Configure the RSS fields to hash upon.
2797          */
2798         mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2799             E1000_MRQC_RSS_FIELD_IPV4_TCP);
2800         mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2801             E1000_MRQC_RSS_FIELD_IPV6_TCP);
2802         mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2803             E1000_MRQC_RSS_FIELD_IPV6_UDP);
2804         mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2805             E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2806
2807         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2808 }
2809
2810 /*********************************************************************
2811  *
2812  *  Setup networking device structure and register interface media.
2813  *
2814  **********************************************************************/
2815 static int
2816 em_setup_interface(if_ctx_t ctx)
2817 {
2818         struct ifnet *ifp = iflib_get_ifp(ctx);
2819         struct adapter *adapter = iflib_get_softc(ctx);
2820         if_softc_ctx_t scctx = adapter->shared;
2821
2822         INIT_DEBUGOUT("em_setup_interface: begin");
2823
2824         /* Single Queue */
2825         if (adapter->tx_num_queues == 1) {
2826                 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
2827                 if_setsendqready(ifp);
2828         }
2829
2830         /*
2831          * Specify the media types supported by this adapter and register
2832          * callbacks to update media and link information
2833          */
2834         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
2835             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
2836                 u_char fiber_type = IFM_1000_SX;        /* default type */
2837
2838                 if (adapter->hw.mac.type == e1000_82545)
2839                         fiber_type = IFM_1000_LX;
2840                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
2841                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2842         } else {
2843                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2844                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2845                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2846                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2847                 if (adapter->hw.phy.type != e1000_phy_ife) {
2848                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2849                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2850                 }
2851         }
2852         ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2853         ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO);
2854         return (0);
2855 }
2856
2857 static int
2858 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
2859 {
2860         struct adapter *adapter = iflib_get_softc(ctx);
2861         if_softc_ctx_t scctx = adapter->shared;
2862         int error = E1000_SUCCESS;
2863         struct em_tx_queue *que;
2864         int i, j;
2865
2866         MPASS(adapter->tx_num_queues > 0);
2867         MPASS(adapter->tx_num_queues == ntxqsets);
2868
2869         /* First allocate the top level queue structs */
2870         if (!(adapter->tx_queues =
2871             (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
2872             adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2873                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2874                 return(ENOMEM);
2875         }
2876
2877         for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) {
2878                 /* Set up some basics */
2879
2880                 struct tx_ring *txr = &que->txr;
2881                 txr->adapter = que->adapter = adapter;
2882                 que->me = txr->me =  i;
2883
2884                 /* Allocate report status array */
2885                 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2886                         device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n");
2887                         error = ENOMEM;
2888                         goto fail;
2889                 }
2890                 for (j = 0; j < scctx->isc_ntxd[0]; j++)
2891                         txr->tx_rsq[j] = QIDX_INVALID;
2892                 /* get the virtual and physical address of the hardware queues */
2893                 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
2894                 txr->tx_paddr = paddrs[i*ntxqs];
2895         }
2896
2897         if (bootverbose)
2898                 device_printf(iflib_get_dev(ctx),
2899                     "allocated for %d tx_queues\n", adapter->tx_num_queues);
2900         return (0);
2901 fail:
2902         em_if_queues_free(ctx);
2903         return (error);
2904 }
2905
2906 static int
2907 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
2908 {
2909         struct adapter *adapter = iflib_get_softc(ctx);
2910         int error = E1000_SUCCESS;
2911         struct em_rx_queue *que;
2912         int i;
2913
2914         MPASS(adapter->rx_num_queues > 0);
2915         MPASS(adapter->rx_num_queues == nrxqsets);
2916
2917         /* First allocate the top level queue structs */
2918         if (!(adapter->rx_queues =
2919             (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
2920             adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2921                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2922                 error = ENOMEM;
2923                 goto fail;
2924         }
2925
2926         for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) {
2927                 /* Set up some basics */
2928                 struct rx_ring *rxr = &que->rxr;
2929                 rxr->adapter = que->adapter = adapter;
2930                 rxr->que = que;
2931                 que->me = rxr->me =  i;
2932
2933                 /* get the virtual and physical address of the hardware queues */
2934                 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
2935                 rxr->rx_paddr = paddrs[i*nrxqs];
2936         }
2937
2938         if (bootverbose)
2939                 device_printf(iflib_get_dev(ctx),
2940                     "allocated for %d rx_queues\n", adapter->rx_num_queues);
2941
2942         return (0);
2943 fail:
2944         em_if_queues_free(ctx);
2945         return (error);
2946 }
2947
2948 static void
2949 em_if_queues_free(if_ctx_t ctx)
2950 {
2951         struct adapter *adapter = iflib_get_softc(ctx);
2952         struct em_tx_queue *tx_que = adapter->tx_queues;
2953         struct em_rx_queue *rx_que = adapter->rx_queues;
2954
2955         if (tx_que != NULL) {
2956                 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
2957                         struct tx_ring *txr = &tx_que->txr;
2958                         if (txr->tx_rsq == NULL)
2959                                 break;
2960
2961                         free(txr->tx_rsq, M_DEVBUF);
2962                         txr->tx_rsq = NULL;
2963                 }
2964                 free(adapter->tx_queues, M_DEVBUF);
2965                 adapter->tx_queues = NULL;
2966         }
2967
2968         if (rx_que != NULL) {
2969                 free(adapter->rx_queues, M_DEVBUF);
2970                 adapter->rx_queues = NULL;
2971         }
2972
2973         em_release_hw_control(adapter);
2974
2975         if (adapter->mta != NULL) {
2976                 free(adapter->mta, M_DEVBUF);
2977         }
2978 }
2979
2980 /*********************************************************************
2981  *
2982  *  Enable transmit unit.
2983  *
2984  **********************************************************************/
2985 static void
2986 em_initialize_transmit_unit(if_ctx_t ctx)
2987 {
2988         struct adapter *adapter = iflib_get_softc(ctx);
2989         if_softc_ctx_t scctx = adapter->shared;
2990         struct em_tx_queue *que;
2991         struct tx_ring  *txr;
2992         struct e1000_hw *hw = &adapter->hw;
2993         u32 tctl, txdctl = 0, tarc, tipg = 0;
2994
2995         INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
2996
2997         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
2998                 u64 bus_addr;
2999                 caddr_t offp, endp;
3000
3001                 que = &adapter->tx_queues[i];
3002                 txr = &que->txr;
3003                 bus_addr = txr->tx_paddr;
3004
3005                 /* Clear checksum offload context. */
3006                 offp = (caddr_t)&txr->csum_flags;
3007                 endp = (caddr_t)(txr + 1);
3008                 bzero(offp, endp - offp);
3009
3010                 /* Base and Len of TX Ring */
3011                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
3012                     scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
3013                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
3014                     (u32)(bus_addr >> 32));
3015                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
3016                     (u32)bus_addr);
3017                 /* Init the HEAD/TAIL indices */
3018                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
3019                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
3020
3021                 HW_DEBUGOUT2("Base = %x, Length = %x\n",
3022                     E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)),
3023                     E1000_READ_REG(&adapter->hw, E1000_TDLEN(i)));
3024
3025                 txdctl = 0; /* clear txdctl */
3026                 txdctl |= 0x1f; /* PTHRESH */
3027                 txdctl |= 1 << 8; /* HTHRESH */
3028                 txdctl |= 1 << 16;/* WTHRESH */
3029                 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
3030                 txdctl |= E1000_TXDCTL_GRAN;
3031                 txdctl |= 1 << 25; /* LWTHRESH */
3032
3033                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
3034         }
3035
3036         /* Set the default values for the Tx Inter Packet Gap timer */
3037         switch (adapter->hw.mac.type) {
3038         case e1000_80003es2lan:
3039                 tipg = DEFAULT_82543_TIPG_IPGR1;
3040                 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
3041                     E1000_TIPG_IPGR2_SHIFT;
3042                 break;
3043         case e1000_82542:
3044                 tipg = DEFAULT_82542_TIPG_IPGT;
3045                 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3046                 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3047                 break;
3048         default:
3049                 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
3050                     (adapter->hw.phy.media_type ==
3051                     e1000_media_type_internal_serdes))
3052                         tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
3053                 else
3054                         tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
3055                 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3056                 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3057         }
3058
3059         E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
3060         E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value);
3061
3062         if(adapter->hw.mac.type >= e1000_82540)
3063                 E1000_WRITE_REG(&adapter->hw, E1000_TADV,
3064                     adapter->tx_abs_int_delay.value);
3065
3066         if ((adapter->hw.mac.type == e1000_82571) ||
3067             (adapter->hw.mac.type == e1000_82572)) {
3068                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3069                 tarc |= TARC_SPEED_MODE_BIT;
3070                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3071         } else if (adapter->hw.mac.type == e1000_80003es2lan) {
3072                 /* errata: program both queues to unweighted RR */
3073                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3074                 tarc |= 1;
3075                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3076                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
3077                 tarc |= 1;
3078                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
3079         } else if (adapter->hw.mac.type == e1000_82574) {
3080                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3081                 tarc |= TARC_ERRATA_BIT;
3082                 if ( adapter->tx_num_queues > 1) {
3083                         tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
3084                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3085                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
3086                 } else
3087                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3088         }
3089
3090         if (adapter->tx_int_delay.value > 0)
3091                 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3092
3093         /* Program the Transmit Control Register */
3094         tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
3095         tctl &= ~E1000_TCTL_CT;
3096         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
3097                    (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
3098
3099         if (adapter->hw.mac.type >= e1000_82571)
3100                 tctl |= E1000_TCTL_MULR;
3101
3102         /* This write will effectively turn on the transmit unit. */
3103         E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
3104
3105         /* SPT and KBL errata workarounds */
3106         if (hw->mac.type == e1000_pch_spt) {
3107                 u32 reg;
3108                 reg = E1000_READ_REG(hw, E1000_IOSFPC);
3109                 reg |= E1000_RCTL_RDMTS_HEX;
3110                 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
3111                 /* i218-i219 Specification Update 1.5.4.5 */
3112                 reg = E1000_READ_REG(hw, E1000_TARC(0));
3113                 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3114                 reg |= E1000_TARC0_CB_MULTIQ_2_REQ;
3115                 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3116         }
3117 }
3118
3119 /*********************************************************************
3120  *
3121  *  Enable receive unit.
3122  *
3123  **********************************************************************/
3124
3125 static void
3126 em_initialize_receive_unit(if_ctx_t ctx)
3127 {
3128         struct adapter *adapter = iflib_get_softc(ctx);
3129         if_softc_ctx_t scctx = adapter->shared;
3130         struct ifnet *ifp = iflib_get_ifp(ctx);
3131         struct e1000_hw *hw = &adapter->hw;
3132         struct em_rx_queue *que;
3133         int i;
3134         u32 rctl, rxcsum, rfctl;
3135
3136         INIT_DEBUGOUT("em_initialize_receive_units: begin");
3137
3138         /*
3139          * Make sure receives are disabled while setting
3140          * up the descriptor ring
3141          */
3142         rctl = E1000_READ_REG(hw, E1000_RCTL);
3143         /* Do not disable if ever enabled on this hardware */
3144         if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
3145                 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3146
3147         /* Setup the Receive Control Register */
3148         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3149         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3150             E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3151             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3152
3153         /* Do not store bad packets */
3154         rctl &= ~E1000_RCTL_SBP;
3155
3156         /* Enable Long Packet receive */
3157         if (if_getmtu(ifp) > ETHERMTU)
3158                 rctl |= E1000_RCTL_LPE;
3159         else
3160                 rctl &= ~E1000_RCTL_LPE;
3161
3162         /* Strip the CRC */
3163         if (!em_disable_crc_stripping)
3164                 rctl |= E1000_RCTL_SECRC;
3165
3166         if (adapter->hw.mac.type >= e1000_82540) {
3167                 E1000_WRITE_REG(&adapter->hw, E1000_RADV,
3168                             adapter->rx_abs_int_delay.value);
3169
3170                 /*
3171                  * Set the interrupt throttling rate. Value is calculated
3172                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
3173                  */
3174                 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
3175         }
3176         E1000_WRITE_REG(&adapter->hw, E1000_RDTR,
3177             adapter->rx_int_delay.value);
3178
3179         /* Use extended rx descriptor formats */
3180         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3181         rfctl |= E1000_RFCTL_EXTEN;
3182         /*
3183          * When using MSI-X interrupts we need to throttle
3184          * using the EITR register (82574 only)
3185          */
3186         if (hw->mac.type == e1000_82574) {
3187                 for (int i = 0; i < 4; i++)
3188                         E1000_WRITE_REG(hw, E1000_EITR_82574(i),
3189                             DEFAULT_ITR);
3190                 /* Disable accelerated acknowledge */
3191                 rfctl |= E1000_RFCTL_ACK_DIS;
3192         }
3193         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3194
3195         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
3196         if (if_getcapenable(ifp) & IFCAP_RXCSUM &&
3197             adapter->hw.mac.type >= e1000_82543) {
3198                 if (adapter->tx_num_queues > 1) {
3199                         if (adapter->hw.mac.type >= igb_mac_min) {
3200                                 rxcsum |= E1000_RXCSUM_PCSD;
3201                                 if (hw->mac.type != e1000_82575)
3202                                         rxcsum |= E1000_RXCSUM_CRCOFL;
3203                         } else
3204                                 rxcsum |= E1000_RXCSUM_TUOFL |
3205                                         E1000_RXCSUM_IPOFL |
3206                                         E1000_RXCSUM_PCSD;
3207                 } else {
3208                         if (adapter->hw.mac.type >= igb_mac_min)
3209                                 rxcsum |= E1000_RXCSUM_IPPCSE;
3210                         else
3211                                 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
3212                         if (adapter->hw.mac.type > e1000_82575)
3213                                 rxcsum |= E1000_RXCSUM_CRCOFL;
3214                 }
3215         } else
3216                 rxcsum &= ~E1000_RXCSUM_TUOFL;
3217
3218         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
3219
3220         if (adapter->rx_num_queues > 1) {
3221                 if (adapter->hw.mac.type >= igb_mac_min)
3222                         igb_initialize_rss_mapping(adapter);
3223                 else
3224                         em_initialize_rss_mapping(adapter);
3225         }
3226
3227         /*
3228          * XXX TEMPORARY WORKAROUND: on some systems with 82573
3229          * long latencies are observed, like Lenovo X60. This
3230          * change eliminates the problem, but since having positive
3231          * values in RDTR is a known source of problems on other
3232          * platforms another solution is being sought.
3233          */
3234         if (hw->mac.type == e1000_82573)
3235                 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
3236
3237         for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3238                 struct rx_ring *rxr = &que->rxr;
3239                 /* Setup the Base and Length of the Rx Descriptor Ring */
3240                 u64 bus_addr = rxr->rx_paddr;
3241 #if 0
3242                 u32 rdt = adapter->rx_num_queues -1;  /* default */
3243 #endif
3244
3245                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3246                     scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
3247                 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
3248                 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
3249                 /* Setup the Head and Tail Descriptor Pointers */
3250                 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
3251                 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
3252         }
3253
3254         /*
3255          * Set PTHRESH for improved jumbo performance
3256          * According to 10.2.5.11 of Intel 82574 Datasheet,
3257          * RXDCTL(1) is written whenever RXDCTL(0) is written.
3258          * Only write to RXDCTL(1) if there is a need for different
3259          * settings.
3260          */
3261
3262         if (((adapter->hw.mac.type == e1000_ich9lan) ||
3263             (adapter->hw.mac.type == e1000_pch2lan) ||
3264             (adapter->hw.mac.type == e1000_ich10lan)) &&
3265             (if_getmtu(ifp) > ETHERMTU)) {
3266                 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
3267                 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
3268         } else if (adapter->hw.mac.type == e1000_82574) {
3269                 for (int i = 0; i < adapter->rx_num_queues; i++) {
3270                         u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3271                         rxdctl |= 0x20; /* PTHRESH */
3272                         rxdctl |= 4 << 8; /* HTHRESH */
3273                         rxdctl |= 4 << 16;/* WTHRESH */
3274                         rxdctl |= 1 << 24; /* Switch to granularity */
3275                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3276                 }
3277         } else if (adapter->hw.mac.type >= igb_mac_min) {
3278                 u32 psize, srrctl = 0;
3279
3280                 if (if_getmtu(ifp) > ETHERMTU) {
3281                         /* Set maximum packet len */
3282                         if (adapter->rx_mbuf_sz <= 4096) {
3283                                 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3284                                 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3285                         } else if (adapter->rx_mbuf_sz > 4096) {
3286                                 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3287                                 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3288                         }
3289                         psize = scctx->isc_max_frame_size;
3290                         /* are we on a vlan? */
3291                         if (ifp->if_vlantrunk != NULL)
3292                                 psize += VLAN_TAG_SIZE;
3293                         E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
3294                 } else {
3295                         srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3296                         rctl |= E1000_RCTL_SZ_2048;
3297                 }
3298
3299                 /*
3300                  * If TX flow control is disabled and there's >1 queue defined,
3301                  * enable DROP.
3302                  *
3303                  * This drops frames rather than hanging the RX MAC for all queues.
3304                  */
3305                 if ((adapter->rx_num_queues > 1) &&
3306                     (adapter->fc == e1000_fc_none ||
3307                      adapter->fc == e1000_fc_rx_pause)) {
3308                         srrctl |= E1000_SRRCTL_DROP_EN;
3309                 }
3310                         /* Setup the Base and Length of the Rx Descriptor Rings */
3311                 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3312                         struct rx_ring *rxr = &que->rxr;
3313                         u64 bus_addr = rxr->rx_paddr;
3314                         u32 rxdctl;
3315
3316 #ifdef notyet
3317                         /* Configure for header split? -- ignore for now */
3318                         rxr->hdr_split = igb_header_split;
3319 #else
3320                         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3321 #endif
3322
3323                         E1000_WRITE_REG(hw, E1000_RDLEN(i),
3324                                         scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3325                         E1000_WRITE_REG(hw, E1000_RDBAH(i),
3326                                         (uint32_t)(bus_addr >> 32));
3327                         E1000_WRITE_REG(hw, E1000_RDBAL(i),
3328                                         (uint32_t)bus_addr);
3329                         E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3330                         /* Enable this Queue */
3331                         rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3332                         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3333                         rxdctl &= 0xFFF00000;
3334                         rxdctl |= IGB_RX_PTHRESH;
3335                         rxdctl |= IGB_RX_HTHRESH << 8;
3336                         rxdctl |= IGB_RX_WTHRESH << 16;
3337                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3338                 }
3339         } else if (adapter->hw.mac.type >= e1000_pch2lan) {
3340                 if (if_getmtu(ifp) > ETHERMTU)
3341                         e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
3342                 else
3343                         e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
3344         }
3345
3346         /* Make sure VLAN Filters are off */
3347         rctl &= ~E1000_RCTL_VFE;
3348
3349         if (adapter->hw.mac.type < igb_mac_min) {
3350                 if (adapter->rx_mbuf_sz == MCLBYTES)
3351                         rctl |= E1000_RCTL_SZ_2048;
3352                 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE)
3353                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3354                 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE)
3355                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3356
3357                 /* ensure we clear use DTYPE of 00 here */
3358                 rctl &= ~0x00000C00;
3359         }
3360
3361         /* Write out the settings */
3362         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3363
3364         return;
3365 }
3366
3367 static void
3368 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3369 {
3370         struct adapter *adapter = iflib_get_softc(ctx);
3371         u32 index, bit;
3372
3373         index = (vtag >> 5) & 0x7F;
3374         bit = vtag & 0x1F;
3375         adapter->shadow_vfta[index] |= (1 << bit);
3376         ++adapter->num_vlans;
3377 }
3378
3379 static void
3380 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3381 {
3382         struct adapter *adapter = iflib_get_softc(ctx);
3383         u32 index, bit;
3384
3385         index = (vtag >> 5) & 0x7F;
3386         bit = vtag & 0x1F;
3387         adapter->shadow_vfta[index] &= ~(1 << bit);
3388         --adapter->num_vlans;
3389 }
3390
3391 static void
3392 em_setup_vlan_hw_support(struct adapter *adapter)
3393 {
3394         struct e1000_hw *hw = &adapter->hw;
3395         u32 reg;
3396
3397         /*
3398          * We get here thru init_locked, meaning
3399          * a soft reset, this has already cleared
3400          * the VFTA and other state, so if there
3401          * have been no vlan's registered do nothing.
3402          */
3403         if (adapter->num_vlans == 0)
3404                 return;
3405
3406         /*
3407          * A soft reset zero's out the VFTA, so
3408          * we need to repopulate it now.
3409          */
3410         for (int i = 0; i < EM_VFTA_SIZE; i++)
3411                 if (adapter->shadow_vfta[i] != 0)
3412                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
3413                             i, adapter->shadow_vfta[i]);
3414
3415         reg = E1000_READ_REG(hw, E1000_CTRL);
3416         reg |= E1000_CTRL_VME;
3417         E1000_WRITE_REG(hw, E1000_CTRL, reg);
3418
3419         /* Enable the Filter Table */
3420         reg = E1000_READ_REG(hw, E1000_RCTL);
3421         reg &= ~E1000_RCTL_CFIEN;
3422         reg |= E1000_RCTL_VFE;
3423         E1000_WRITE_REG(hw, E1000_RCTL, reg);
3424 }
3425
3426 static void
3427 em_if_intr_enable(if_ctx_t ctx)
3428 {
3429         struct adapter *adapter = iflib_get_softc(ctx);
3430         struct e1000_hw *hw = &adapter->hw;
3431         u32 ims_mask = IMS_ENABLE_MASK;
3432
3433         if (hw->mac.type == e1000_82574) {
3434                 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK);
3435                 ims_mask |= adapter->ims;
3436         }
3437         E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3438 }
3439
3440 static void
3441 em_if_intr_disable(if_ctx_t ctx)
3442 {
3443         struct adapter *adapter = iflib_get_softc(ctx);
3444         struct e1000_hw *hw = &adapter->hw;
3445
3446         if (hw->mac.type == e1000_82574)
3447                 E1000_WRITE_REG(hw, EM_EIAC, 0);
3448         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3449 }
3450
3451 static void
3452 igb_if_intr_enable(if_ctx_t ctx)
3453 {
3454         struct adapter *adapter = iflib_get_softc(ctx);
3455         struct e1000_hw *hw = &adapter->hw;
3456         u32 mask;
3457
3458         if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) {
3459                 mask = (adapter->que_mask | adapter->link_mask);
3460                 E1000_WRITE_REG(hw, E1000_EIAC, mask);
3461                 E1000_WRITE_REG(hw, E1000_EIAM, mask);
3462                 E1000_WRITE_REG(hw, E1000_EIMS, mask);
3463                 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
3464         } else
3465                 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
3466         E1000_WRITE_FLUSH(hw);
3467 }
3468
3469 static void
3470 igb_if_intr_disable(if_ctx_t ctx)
3471 {
3472         struct adapter *adapter = iflib_get_softc(ctx);
3473         struct e1000_hw *hw = &adapter->hw;
3474
3475         if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) {
3476                 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff);
3477                 E1000_WRITE_REG(hw, E1000_EIAC, 0);
3478         }
3479         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3480         E1000_WRITE_FLUSH(hw);
3481 }
3482
3483 /*
3484  * Bit of a misnomer, what this really means is
3485  * to enable OS management of the system... aka
3486  * to disable special hardware management features
3487  */
3488 static void
3489 em_init_manageability(struct adapter *adapter)
3490 {
3491         /* A shared code workaround */
3492 #define E1000_82542_MANC2H E1000_MANC2H
3493         if (adapter->has_manage) {
3494                 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3495                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3496
3497                 /* disable hardware interception of ARP */
3498                 manc &= ~(E1000_MANC_ARP_EN);
3499
3500                 /* enable receiving management packets to the host */
3501                 manc |= E1000_MANC_EN_MNG2HOST;
3502 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3503 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3504                 manc2h |= E1000_MNG2HOST_PORT_623;
3505                 manc2h |= E1000_MNG2HOST_PORT_664;
3506                 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3507                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3508         }
3509 }
3510
3511 /*
3512  * Give control back to hardware management
3513  * controller if there is one.
3514  */
3515 static void
3516 em_release_manageability(struct adapter *adapter)
3517 {
3518         if (adapter->has_manage) {
3519                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3520
3521                 /* re-enable hardware interception of ARP */
3522                 manc |= E1000_MANC_ARP_EN;
3523                 manc &= ~E1000_MANC_EN_MNG2HOST;
3524
3525                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3526         }
3527 }
3528
3529 /*
3530  * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3531  * For ASF and Pass Through versions of f/w this means
3532  * that the driver is loaded. For AMT version type f/w
3533  * this means that the network i/f is open.
3534  */
3535 static void
3536 em_get_hw_control(struct adapter *adapter)
3537 {
3538         u32 ctrl_ext, swsm;
3539
3540         if (adapter->vf_ifp)
3541                 return;
3542
3543         if (adapter->hw.mac.type == e1000_82573) {
3544                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3545                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3546                     swsm | E1000_SWSM_DRV_LOAD);
3547                 return;
3548         }
3549         /* else */
3550         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3551         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3552             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3553 }
3554
3555 /*
3556  * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3557  * For ASF and Pass Through versions of f/w this means that
3558  * the driver is no longer loaded. For AMT versions of the
3559  * f/w this means that the network i/f is closed.
3560  */
3561 static void
3562 em_release_hw_control(struct adapter *adapter)
3563 {
3564         u32 ctrl_ext, swsm;
3565
3566         if (!adapter->has_manage)
3567                 return;
3568
3569         if (adapter->hw.mac.type == e1000_82573) {
3570                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3571                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3572                     swsm & ~E1000_SWSM_DRV_LOAD);
3573                 return;
3574         }
3575         /* else */
3576         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3577         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3578             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3579         return;
3580 }
3581
3582 static int
3583 em_is_valid_ether_addr(u8 *addr)
3584 {
3585         char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3586
3587         if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3588                 return (FALSE);
3589         }
3590
3591         return (TRUE);
3592 }
3593
3594 /*
3595 ** Parse the interface capabilities with regard
3596 ** to both system management and wake-on-lan for
3597 ** later use.
3598 */
3599 static void
3600 em_get_wakeup(if_ctx_t ctx)
3601 {
3602         struct adapter *adapter = iflib_get_softc(ctx);
3603         device_t dev = iflib_get_dev(ctx);
3604         u16 eeprom_data = 0, device_id, apme_mask;
3605
3606         adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
3607         apme_mask = EM_EEPROM_APME;
3608
3609         switch (adapter->hw.mac.type) {
3610         case e1000_82542:
3611         case e1000_82543:
3612                 break;
3613         case e1000_82544:
3614                 e1000_read_nvm(&adapter->hw,
3615                     NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3616                 apme_mask = EM_82544_APME;
3617                 break;
3618         case e1000_82546:
3619         case e1000_82546_rev_3:
3620                 if (adapter->hw.bus.func == 1) {
3621                         e1000_read_nvm(&adapter->hw,
3622                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3623                         break;
3624                 } else
3625                         e1000_read_nvm(&adapter->hw,
3626                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3627                 break;
3628         case e1000_82573:
3629         case e1000_82583:
3630                 adapter->has_amt = TRUE;
3631                 /* FALLTHROUGH */
3632         case e1000_82571:
3633         case e1000_82572:
3634         case e1000_80003es2lan:
3635                 if (adapter->hw.bus.func == 1) {
3636                         e1000_read_nvm(&adapter->hw,
3637                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3638                         break;
3639                 } else
3640                         e1000_read_nvm(&adapter->hw,
3641                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3642                 break;
3643         case e1000_ich8lan:
3644         case e1000_ich9lan:
3645         case e1000_ich10lan:
3646         case e1000_pchlan:
3647         case e1000_pch2lan:
3648         case e1000_pch_lpt:
3649         case e1000_pch_spt:
3650         case e1000_82575:       /* listing all igb devices */
3651         case e1000_82576:
3652         case e1000_82580:
3653         case e1000_i350:
3654         case e1000_i354:
3655         case e1000_i210:
3656         case e1000_i211:
3657         case e1000_vfadapt:
3658         case e1000_vfadapt_i350:
3659                 apme_mask = E1000_WUC_APME;
3660                 adapter->has_amt = TRUE;
3661                 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
3662                 break;
3663         default:
3664                 e1000_read_nvm(&adapter->hw,
3665                     NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3666                 break;
3667         }
3668         if (eeprom_data & apme_mask)
3669                 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
3670         /*
3671          * We have the eeprom settings, now apply the special cases
3672          * where the eeprom may be wrong or the board won't support
3673          * wake on lan on a particular port
3674          */
3675         device_id = pci_get_device(dev);
3676         switch (device_id) {
3677         case E1000_DEV_ID_82546GB_PCIE:
3678                 adapter->wol = 0;
3679                 break;
3680         case E1000_DEV_ID_82546EB_FIBER:
3681         case E1000_DEV_ID_82546GB_FIBER:
3682                 /* Wake events only supported on port A for dual fiber
3683                  * regardless of eeprom setting */
3684                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3685                     E1000_STATUS_FUNC_1)
3686                         adapter->wol = 0;
3687                 break;
3688         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
3689                 /* if quad port adapter, disable WoL on all but port A */
3690                 if (global_quad_port_a != 0)
3691                         adapter->wol = 0;
3692                 /* Reset for multiple quad port adapters */
3693                 if (++global_quad_port_a == 4)
3694                         global_quad_port_a = 0;
3695                 break;
3696         case E1000_DEV_ID_82571EB_FIBER:
3697                 /* Wake events only supported on port A for dual fiber
3698                  * regardless of eeprom setting */
3699                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3700                     E1000_STATUS_FUNC_1)
3701                         adapter->wol = 0;
3702                 break;
3703         case E1000_DEV_ID_82571EB_QUAD_COPPER:
3704         case E1000_DEV_ID_82571EB_QUAD_FIBER:
3705         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
3706                 /* if quad port adapter, disable WoL on all but port A */
3707                 if (global_quad_port_a != 0)
3708                         adapter->wol = 0;
3709                 /* Reset for multiple quad port adapters */
3710                 if (++global_quad_port_a == 4)
3711                         global_quad_port_a = 0;
3712                 break;
3713         }
3714         return;
3715 }
3716
3717
3718 /*
3719  * Enable PCI Wake On Lan capability
3720  */
3721 static void
3722 em_enable_wakeup(if_ctx_t ctx)
3723 {
3724         struct adapter *adapter = iflib_get_softc(ctx);
3725         device_t dev = iflib_get_dev(ctx);
3726         if_t ifp = iflib_get_ifp(ctx);
3727         int error = 0;
3728         u32 pmc, ctrl, ctrl_ext, rctl;
3729         u16 status;
3730
3731         if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
3732                 return;
3733
3734         /*
3735          * Determine type of Wakeup: note that wol
3736          * is set with all bits on by default.
3737          */
3738         if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
3739                 adapter->wol &= ~E1000_WUFC_MAG;
3740
3741         if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
3742                 adapter->wol &= ~E1000_WUFC_EX;
3743
3744         if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
3745                 adapter->wol &= ~E1000_WUFC_MC;
3746         else {
3747                 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3748                 rctl |= E1000_RCTL_MPE;
3749                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3750         }
3751
3752         if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC)))
3753                 goto pme;
3754
3755         /* Advertise the wakeup capability */
3756         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
3757         ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
3758         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
3759
3760         /* Keep the laser running on Fiber adapters */
3761         if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3762             adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
3763                 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3764                 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
3765                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext);
3766         }
3767
3768         if ((adapter->hw.mac.type == e1000_ich8lan) ||
3769             (adapter->hw.mac.type == e1000_pchlan) ||
3770             (adapter->hw.mac.type == e1000_ich9lan) ||
3771             (adapter->hw.mac.type == e1000_ich10lan))
3772                 e1000_suspend_workarounds_ich8lan(&adapter->hw);
3773
3774         if ( adapter->hw.mac.type >= e1000_pchlan) {
3775                 error = em_enable_phy_wakeup(adapter);
3776                 if (error)
3777                         goto pme;
3778         } else {
3779                 /* Enable wakeup by the MAC */
3780                 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
3781                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
3782         }
3783
3784         if (adapter->hw.phy.type == e1000_phy_igp_3)
3785                 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
3786
3787 pme:
3788         status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
3789         status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3790         if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
3791                 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3792         pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
3793
3794         return;
3795 }
3796
3797 /*
3798  * WOL in the newer chipset interfaces (pchlan)
3799  * require thing to be copied into the phy
3800  */
3801 static int
3802 em_enable_phy_wakeup(struct adapter *adapter)
3803 {
3804         struct e1000_hw *hw = &adapter->hw;
3805         u32 mreg, ret = 0;
3806         u16 preg;
3807
3808         /* copy MAC RARs to PHY RARs */
3809         e1000_copy_rx_addrs_to_phy_ich8lan(hw);
3810
3811         /* copy MAC MTA to PHY MTA */
3812         for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
3813                 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
3814                 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
3815                 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
3816                     (u16)((mreg >> 16) & 0xFFFF));
3817         }
3818
3819         /* configure PHY Rx Control register */
3820         e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg);
3821         mreg = E1000_READ_REG(hw, E1000_RCTL);
3822         if (mreg & E1000_RCTL_UPE)
3823                 preg |= BM_RCTL_UPE;
3824         if (mreg & E1000_RCTL_MPE)
3825                 preg |= BM_RCTL_MPE;
3826         preg &= ~(BM_RCTL_MO_MASK);
3827         if (mreg & E1000_RCTL_MO_3)
3828                 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
3829                                 << BM_RCTL_MO_SHIFT);
3830         if (mreg & E1000_RCTL_BAM)
3831                 preg |= BM_RCTL_BAM;
3832         if (mreg & E1000_RCTL_PMCF)
3833                 preg |= BM_RCTL_PMCF;
3834         mreg = E1000_READ_REG(hw, E1000_CTRL);
3835         if (mreg & E1000_CTRL_RFCE)
3836                 preg |= BM_RCTL_RFCE;
3837         e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg);
3838
3839         /* enable PHY wakeup in MAC register */
3840         E1000_WRITE_REG(hw, E1000_WUC,
3841             E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
3842         E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol);
3843
3844         /* configure and enable PHY wakeup in PHY registers */
3845         e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol);
3846         e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
3847
3848         /* activate PHY wakeup */
3849         ret = hw->phy.ops.acquire(hw);
3850         if (ret) {
3851                 printf("Could not acquire PHY\n");
3852                 return ret;
3853         }
3854         e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3855                                  (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3856         ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
3857         if (ret) {
3858                 printf("Could not read PHY page 769\n");
3859                 goto out;
3860         }
3861         preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
3862         ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
3863         if (ret)
3864                 printf("Could not set PHY Host Wakeup bit\n");
3865 out:
3866         hw->phy.ops.release(hw);
3867
3868         return ret;
3869 }
3870
3871 static void
3872 em_if_led_func(if_ctx_t ctx, int onoff)
3873 {
3874         struct adapter *adapter = iflib_get_softc(ctx);
3875
3876         if (onoff) {
3877                 e1000_setup_led(&adapter->hw);
3878                 e1000_led_on(&adapter->hw);
3879         } else {
3880                 e1000_led_off(&adapter->hw);
3881                 e1000_cleanup_led(&adapter->hw);
3882         }
3883 }
3884
3885 /*
3886  * Disable the L0S and L1 LINK states
3887  */
3888 static void
3889 em_disable_aspm(struct adapter *adapter)
3890 {
3891         int base, reg;
3892         u16 link_cap,link_ctrl;
3893         device_t dev = adapter->dev;
3894
3895         switch (adapter->hw.mac.type) {
3896         case e1000_82573:
3897         case e1000_82574:
3898         case e1000_82583:
3899                 break;
3900         default:
3901                 return;
3902         }
3903         if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
3904                 return;
3905         reg = base + PCIER_LINK_CAP;
3906         link_cap = pci_read_config(dev, reg, 2);
3907         if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
3908                 return;
3909         reg = base + PCIER_LINK_CTL;
3910         link_ctrl = pci_read_config(dev, reg, 2);
3911         link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
3912         pci_write_config(dev, reg, link_ctrl, 2);
3913         return;
3914 }
3915
3916 /**********************************************************************
3917  *
3918  *  Update the board statistics counters.
3919  *
3920  **********************************************************************/
3921 static void
3922 em_update_stats_counters(struct adapter *adapter)
3923 {
3924         u64 prev_xoffrxc = adapter->stats.xoffrxc;
3925
3926         if(adapter->hw.phy.media_type == e1000_media_type_copper ||
3927            (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3928                 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
3929                 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
3930         }
3931         adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
3932         adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
3933         adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
3934         adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
3935
3936         adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
3937         adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
3938         adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
3939         adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
3940         adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
3941         adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
3942         adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
3943         adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
3944         /*
3945          ** For watchdog management we need to know if we have been
3946          ** paused during the last interval, so capture that here.
3947         */
3948         if (adapter->stats.xoffrxc != prev_xoffrxc)
3949                 adapter->shared->isc_pause_frames = 1;
3950         adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
3951         adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
3952         adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
3953         adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
3954         adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
3955         adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
3956         adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
3957         adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
3958         adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
3959         adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
3960         adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
3961         adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
3962
3963         /* For the 64-bit byte counters the low dword must be read first. */
3964         /* Both registers clear on the read of the high dword */
3965
3966         adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) +
3967             ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32);
3968         adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) +
3969             ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32);
3970
3971         adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
3972         adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
3973         adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
3974         adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
3975         adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
3976
3977         adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
3978         adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
3979
3980         adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
3981         adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
3982         adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
3983         adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
3984         adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
3985         adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
3986         adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
3987         adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
3988         adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
3989         adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
3990
3991         /* Interrupt Counts */
3992
3993         adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC);
3994         adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC);
3995         adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC);
3996         adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC);
3997         adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC);
3998         adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC);
3999         adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC);
4000         adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC);
4001         adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC);
4002
4003         if (adapter->hw.mac.type >= e1000_82543) {
4004                 adapter->stats.algnerrc +=
4005                 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
4006                 adapter->stats.rxerrc +=
4007                 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
4008                 adapter->stats.tncrs +=
4009                 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
4010                 adapter->stats.cexterr +=
4011                 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
4012                 adapter->stats.tsctc +=
4013                 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
4014                 adapter->stats.tsctfc +=
4015                 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
4016         }
4017 }
4018
4019 static uint64_t
4020 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
4021 {
4022         struct adapter *adapter = iflib_get_softc(ctx);
4023         struct ifnet *ifp = iflib_get_ifp(ctx);
4024
4025         switch (cnt) {
4026         case IFCOUNTER_COLLISIONS:
4027                 return (adapter->stats.colc);
4028         case IFCOUNTER_IERRORS:
4029                 return (adapter->dropped_pkts + adapter->stats.rxerrc +
4030                     adapter->stats.crcerrs + adapter->stats.algnerrc +
4031                     adapter->stats.ruc + adapter->stats.roc +
4032                     adapter->stats.mpc + adapter->stats.cexterr);
4033         case IFCOUNTER_OERRORS:
4034                 return (adapter->stats.ecol + adapter->stats.latecol +
4035                     adapter->watchdog_events);
4036         default:
4037                 return (if_get_counter_default(ifp, cnt));
4038         }
4039 }
4040
4041 /* Export a single 32-bit register via a read-only sysctl. */
4042 static int
4043 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
4044 {
4045         struct adapter *adapter;
4046         u_int val;
4047
4048         adapter = oidp->oid_arg1;
4049         val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2);
4050         return (sysctl_handle_int(oidp, &val, 0, req));
4051 }
4052
4053 /*
4054  * Add sysctl variables, one per statistic, to the system.
4055  */
4056 static void
4057 em_add_hw_stats(struct adapter *adapter)
4058 {
4059         device_t dev = iflib_get_dev(adapter->ctx);
4060         struct em_tx_queue *tx_que = adapter->tx_queues;
4061         struct em_rx_queue *rx_que = adapter->rx_queues;
4062
4063         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
4064         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
4065         struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
4066         struct e1000_hw_stats *stats = &adapter->stats;
4067
4068         struct sysctl_oid *stat_node, *queue_node, *int_node;
4069         struct sysctl_oid_list *stat_list, *queue_list, *int_list;
4070
4071 #define QUEUE_NAME_LEN 32
4072         char namebuf[QUEUE_NAME_LEN];
4073
4074         /* Driver Statistics */
4075         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
4076                         CTLFLAG_RD, &adapter->dropped_pkts,
4077                         "Driver dropped packets");
4078         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
4079                         CTLFLAG_RD, &adapter->link_irq,
4080                         "Link MSI-X IRQ Handled");
4081         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
4082                         CTLFLAG_RD, &adapter->rx_overruns,
4083                         "RX overruns");
4084         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
4085                         CTLFLAG_RD, &adapter->watchdog_events,
4086                         "Watchdog timeouts");
4087         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
4088             CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
4089             adapter, E1000_CTRL, em_sysctl_reg_handler, "IU",
4090             "Device Control Register");
4091         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
4092             CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
4093             adapter, E1000_RCTL, em_sysctl_reg_handler, "IU",
4094             "Receiver Control Register");
4095         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
4096                         CTLFLAG_RD, &adapter->hw.fc.high_water, 0,
4097                         "Flow Control High Watermark");
4098         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
4099                         CTLFLAG_RD, &adapter->hw.fc.low_water, 0,
4100                         "Flow Control Low Watermark");
4101
4102         for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
4103                 struct tx_ring *txr = &tx_que->txr;
4104                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
4105                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4106                     CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name");
4107                 queue_list = SYSCTL_CHILDREN(queue_node);
4108
4109                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
4110                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4111                     E1000_TDH(txr->me), em_sysctl_reg_handler, "IU",
4112                     "Transmit Descriptor Head");
4113                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
4114                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4115                     E1000_TDT(txr->me), em_sysctl_reg_handler, "IU",
4116                     "Transmit Descriptor Tail");
4117                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
4118                                 CTLFLAG_RD, &txr->tx_irq,
4119                                 "Queue MSI-X Transmit Interrupts");
4120         }
4121
4122         for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) {
4123                 struct rx_ring *rxr = &rx_que->rxr;
4124                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
4125                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4126                     CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name");
4127                 queue_list = SYSCTL_CHILDREN(queue_node);
4128
4129                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
4130                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4131                     E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU",
4132                     "Receive Descriptor Head");
4133                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
4134                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4135                     E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU",
4136                     "Receive Descriptor Tail");
4137                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
4138                                 CTLFLAG_RD, &rxr->rx_irq,
4139                                 "Queue MSI-X Receive Interrupts");
4140         }
4141
4142         /* MAC stats get their own sub node */
4143
4144         stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
4145             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics");
4146         stat_list = SYSCTL_CHILDREN(stat_node);
4147
4148         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
4149                         CTLFLAG_RD, &stats->ecol,
4150                         "Excessive collisions");
4151         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
4152                         CTLFLAG_RD, &stats->scc,
4153                         "Single collisions");
4154         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
4155                         CTLFLAG_RD, &stats->mcc,
4156                         "Multiple collisions");
4157         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
4158                         CTLFLAG_RD, &stats->latecol,
4159                         "Late collisions");
4160         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
4161                         CTLFLAG_RD, &stats->colc,
4162                         "Collision Count");
4163         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
4164                         CTLFLAG_RD, &adapter->stats.symerrs,
4165                         "Symbol Errors");
4166         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
4167                         CTLFLAG_RD, &adapter->stats.sec,
4168                         "Sequence Errors");
4169         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
4170                         CTLFLAG_RD, &adapter->stats.dc,
4171                         "Defer Count");
4172         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
4173                         CTLFLAG_RD, &adapter->stats.mpc,
4174                         "Missed Packets");
4175         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
4176                         CTLFLAG_RD, &adapter->stats.rnbc,
4177                         "Receive No Buffers");
4178         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
4179                         CTLFLAG_RD, &adapter->stats.ruc,
4180                         "Receive Undersize");
4181         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
4182                         CTLFLAG_RD, &adapter->stats.rfc,
4183                         "Fragmented Packets Received ");
4184         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
4185                         CTLFLAG_RD, &adapter->stats.roc,
4186                         "Oversized Packets Received");
4187         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
4188                         CTLFLAG_RD, &adapter->stats.rjc,
4189                         "Recevied Jabber");
4190         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
4191                         CTLFLAG_RD, &adapter->stats.rxerrc,
4192                         "Receive Errors");
4193         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
4194                         CTLFLAG_RD, &adapter->stats.crcerrs,
4195                         "CRC errors");
4196         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
4197                         CTLFLAG_RD, &adapter->stats.algnerrc,
4198                         "Alignment Errors");
4199         /* On 82575 these are collision counts */
4200         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
4201                         CTLFLAG_RD, &adapter->stats.cexterr,
4202                         "Collision/Carrier extension errors");
4203         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
4204                         CTLFLAG_RD, &adapter->stats.xonrxc,
4205                         "XON Received");
4206         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
4207                         CTLFLAG_RD, &adapter->stats.xontxc,
4208                         "XON Transmitted");
4209         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
4210                         CTLFLAG_RD, &adapter->stats.xoffrxc,
4211                         "XOFF Received");
4212         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
4213                         CTLFLAG_RD, &adapter->stats.xofftxc,
4214                         "XOFF Transmitted");
4215
4216         /* Packet Reception Stats */
4217         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
4218                         CTLFLAG_RD, &adapter->stats.tpr,
4219                         "Total Packets Received ");
4220         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
4221                         CTLFLAG_RD, &adapter->stats.gprc,
4222                         "Good Packets Received");
4223         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
4224                         CTLFLAG_RD, &adapter->stats.bprc,
4225                         "Broadcast Packets Received");
4226         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
4227                         CTLFLAG_RD, &adapter->stats.mprc,
4228                         "Multicast Packets Received");
4229         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
4230                         CTLFLAG_RD, &adapter->stats.prc64,
4231                         "64 byte frames received ");
4232         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
4233                         CTLFLAG_RD, &adapter->stats.prc127,
4234                         "65-127 byte frames received");
4235         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
4236                         CTLFLAG_RD, &adapter->stats.prc255,
4237                         "128-255 byte frames received");
4238         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
4239                         CTLFLAG_RD, &adapter->stats.prc511,
4240                         "256-511 byte frames received");
4241         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
4242                         CTLFLAG_RD, &adapter->stats.prc1023,
4243                         "512-1023 byte frames received");
4244         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
4245                         CTLFLAG_RD, &adapter->stats.prc1522,
4246                         "1023-1522 byte frames received");
4247         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
4248                         CTLFLAG_RD, &adapter->stats.gorc,
4249                         "Good Octets Received");
4250
4251         /* Packet Transmission Stats */
4252         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
4253                         CTLFLAG_RD, &adapter->stats.gotc,
4254                         "Good Octets Transmitted");
4255         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
4256                         CTLFLAG_RD, &adapter->stats.tpt,
4257                         "Total Packets Transmitted");
4258         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
4259                         CTLFLAG_RD, &adapter->stats.gptc,
4260                         "Good Packets Transmitted");
4261         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
4262                         CTLFLAG_RD, &adapter->stats.bptc,
4263                         "Broadcast Packets Transmitted");
4264         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
4265                         CTLFLAG_RD, &adapter->stats.mptc,
4266                         "Multicast Packets Transmitted");
4267         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
4268                         CTLFLAG_RD, &adapter->stats.ptc64,
4269                         "64 byte frames transmitted ");
4270         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
4271                         CTLFLAG_RD, &adapter->stats.ptc127,
4272                         "65-127 byte frames transmitted");
4273         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
4274                         CTLFLAG_RD, &adapter->stats.ptc255,
4275                         "128-255 byte frames transmitted");
4276         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
4277                         CTLFLAG_RD, &adapter->stats.ptc511,
4278                         "256-511 byte frames transmitted");
4279         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
4280                         CTLFLAG_RD, &adapter->stats.ptc1023,
4281                         "512-1023 byte frames transmitted");
4282         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
4283                         CTLFLAG_RD, &adapter->stats.ptc1522,
4284                         "1024-1522 byte frames transmitted");
4285         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
4286                         CTLFLAG_RD, &adapter->stats.tsctc,
4287                         "TSO Contexts Transmitted");
4288         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
4289                         CTLFLAG_RD, &adapter->stats.tsctfc,
4290                         "TSO Contexts Failed");
4291
4292
4293         /* Interrupt Stats */
4294
4295         int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
4296             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics");
4297         int_list = SYSCTL_CHILDREN(int_node);
4298
4299         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
4300                         CTLFLAG_RD, &adapter->stats.iac,
4301                         "Interrupt Assertion Count");
4302
4303         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
4304                         CTLFLAG_RD, &adapter->stats.icrxptc,
4305                         "Interrupt Cause Rx Pkt Timer Expire Count");
4306
4307         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
4308                         CTLFLAG_RD, &adapter->stats.icrxatc,
4309                         "Interrupt Cause Rx Abs Timer Expire Count");
4310
4311         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
4312                         CTLFLAG_RD, &adapter->stats.ictxptc,
4313                         "Interrupt Cause Tx Pkt Timer Expire Count");
4314
4315         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
4316                         CTLFLAG_RD, &adapter->stats.ictxatc,
4317                         "Interrupt Cause Tx Abs Timer Expire Count");
4318
4319         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
4320                         CTLFLAG_RD, &adapter->stats.ictxqec,
4321                         "Interrupt Cause Tx Queue Empty Count");
4322
4323         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
4324                         CTLFLAG_RD, &adapter->stats.ictxqmtc,
4325                         "Interrupt Cause Tx Queue Min Thresh Count");
4326
4327         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
4328                         CTLFLAG_RD, &adapter->stats.icrxdmtc,
4329                         "Interrupt Cause Rx Desc Min Thresh Count");
4330
4331         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
4332                         CTLFLAG_RD, &adapter->stats.icrxoc,
4333                         "Interrupt Cause Receiver Overrun Count");
4334 }
4335
4336 /**********************************************************************
4337  *
4338  *  This routine provides a way to dump out the adapter eeprom,
4339  *  often a useful debug/service tool. This only dumps the first
4340  *  32 words, stuff that matters is in that extent.
4341  *
4342  **********************************************************************/
4343 static int
4344 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4345 {
4346         struct adapter *adapter = (struct adapter *)arg1;
4347         int error;
4348         int result;
4349
4350         result = -1;
4351         error = sysctl_handle_int(oidp, &result, 0, req);
4352
4353         if (error || !req->newptr)
4354                 return (error);
4355
4356         /*
4357          * This value will cause a hex dump of the
4358          * first 32 16-bit words of the EEPROM to
4359          * the screen.
4360          */
4361         if (result == 1)
4362                 em_print_nvm_info(adapter);
4363
4364         return (error);
4365 }
4366
4367 static void
4368 em_print_nvm_info(struct adapter *adapter)
4369 {
4370         u16 eeprom_data;
4371         int i, j, row = 0;
4372
4373         /* Its a bit crude, but it gets the job done */
4374         printf("\nInterface EEPROM Dump:\n");
4375         printf("Offset\n0x0000  ");
4376         for (i = 0, j = 0; i < 32; i++, j++) {
4377                 if (j == 8) { /* Make the offset block */
4378                         j = 0; ++row;
4379                         printf("\n0x00%x0  ",row);
4380                 }
4381                 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
4382                 printf("%04x ", eeprom_data);
4383         }
4384         printf("\n");
4385 }
4386
4387 static int
4388 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4389 {
4390         struct em_int_delay_info *info;
4391         struct adapter *adapter;
4392         u32 regval;
4393         int error, usecs, ticks;
4394
4395         info = (struct em_int_delay_info *) arg1;
4396         usecs = info->value;
4397         error = sysctl_handle_int(oidp, &usecs, 0, req);
4398         if (error != 0 || req->newptr == NULL)
4399                 return (error);
4400         if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4401                 return (EINVAL);
4402         info->value = usecs;
4403         ticks = EM_USECS_TO_TICKS(usecs);
4404         if (info->offset == E1000_ITR)  /* units are 256ns here */
4405                 ticks *= 4;
4406
4407         adapter = info->adapter;
4408
4409         regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
4410         regval = (regval & ~0xffff) | (ticks & 0xffff);
4411         /* Handle a few special cases. */
4412         switch (info->offset) {
4413         case E1000_RDTR:
4414                 break;
4415         case E1000_TIDV:
4416                 if (ticks == 0) {
4417                         adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
4418                         /* Don't write 0 into the TIDV register. */
4419                         regval++;
4420                 } else
4421                         adapter->txd_cmd |= E1000_TXD_CMD_IDE;
4422                 break;
4423         }
4424         E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
4425         return (0);
4426 }
4427
4428 static void
4429 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
4430         const char *description, struct em_int_delay_info *info,
4431         int offset, int value)
4432 {
4433         info->adapter = adapter;
4434         info->offset = offset;
4435         info->value = value;
4436         SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev),
4437             SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4438             OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
4439             info, 0, em_sysctl_int_delay, "I", description);
4440 }
4441
4442 /*
4443  * Set flow control using sysctl:
4444  * Flow control values:
4445  *      0 - off
4446  *      1 - rx pause
4447  *      2 - tx pause
4448  *      3 - full
4449  */
4450 static int
4451 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4452 {
4453         int error;
4454         static int input = 3; /* default is full */
4455         struct adapter  *adapter = (struct adapter *) arg1;
4456
4457         error = sysctl_handle_int(oidp, &input, 0, req);
4458
4459         if ((error) || (req->newptr == NULL))
4460                 return (error);
4461
4462         if (input == adapter->fc) /* no change? */
4463                 return (error);
4464
4465         switch (input) {
4466         case e1000_fc_rx_pause:
4467         case e1000_fc_tx_pause:
4468         case e1000_fc_full:
4469         case e1000_fc_none:
4470                 adapter->hw.fc.requested_mode = input;
4471                 adapter->fc = input;
4472                 break;
4473         default:
4474                 /* Do nothing */
4475                 return (error);
4476         }
4477
4478         adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
4479         e1000_force_mac_fc(&adapter->hw);
4480         return (error);
4481 }
4482
4483 /*
4484  * Manage Energy Efficient Ethernet:
4485  * Control values:
4486  *     0/1 - enabled/disabled
4487  */
4488 static int
4489 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4490 {
4491         struct adapter *adapter = (struct adapter *) arg1;
4492         int error, value;
4493
4494         value = adapter->hw.dev_spec.ich8lan.eee_disable;
4495         error = sysctl_handle_int(oidp, &value, 0, req);
4496         if (error || req->newptr == NULL)
4497                 return (error);
4498         adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4499         em_if_init(adapter->ctx);
4500
4501         return (0);
4502 }
4503
4504 static int
4505 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4506 {
4507         struct adapter *adapter;
4508         int error;
4509         int result;
4510
4511         result = -1;
4512         error = sysctl_handle_int(oidp, &result, 0, req);
4513
4514         if (error || !req->newptr)
4515                 return (error);
4516
4517         if (result == 1) {
4518                 adapter = (struct adapter *) arg1;
4519                 em_print_debug_info(adapter);
4520         }
4521
4522         return (error);
4523 }
4524
4525 static int
4526 em_get_rs(SYSCTL_HANDLER_ARGS)
4527 {
4528         struct adapter *adapter = (struct adapter *) arg1;
4529         int error;
4530         int result;
4531
4532         result = 0;
4533         error = sysctl_handle_int(oidp, &result, 0, req);
4534
4535         if (error || !req->newptr || result != 1)
4536                 return (error);
4537         em_dump_rs(adapter);
4538
4539         return (error);
4540 }
4541
4542 static void
4543 em_if_debug(if_ctx_t ctx)
4544 {
4545         em_dump_rs(iflib_get_softc(ctx));
4546 }
4547
4548 /*
4549  * This routine is meant to be fluid, add whatever is
4550  * needed for debugging a problem.  -jfv
4551  */
4552 static void
4553 em_print_debug_info(struct adapter *adapter)
4554 {
4555         device_t dev = iflib_get_dev(adapter->ctx);
4556         struct ifnet *ifp = iflib_get_ifp(adapter->ctx);
4557         struct tx_ring *txr = &adapter->tx_queues->txr;
4558         struct rx_ring *rxr = &adapter->rx_queues->rxr;
4559
4560         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
4561                 printf("Interface is RUNNING ");
4562         else
4563                 printf("Interface is NOT RUNNING\n");
4564
4565         if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
4566                 printf("and INACTIVE\n");
4567         else
4568                 printf("and ACTIVE\n");
4569
4570         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
4571                 device_printf(dev, "TX Queue %d ------\n", i);
4572                 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
4573                         E1000_READ_REG(&adapter->hw, E1000_TDH(i)),
4574                         E1000_READ_REG(&adapter->hw, E1000_TDT(i)));
4575
4576         }
4577         for (int j=0; j < adapter->rx_num_queues; j++, rxr++) {
4578                 device_printf(dev, "RX Queue %d ------\n", j);
4579                 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
4580                         E1000_READ_REG(&adapter->hw, E1000_RDH(j)),
4581                         E1000_READ_REG(&adapter->hw, E1000_RDT(j)));
4582         }
4583 }
4584
4585 /*
4586  * 82574 only:
4587  * Write a new value to the EEPROM increasing the number of MSI-X
4588  * vectors from 3 to 5, for proper multiqueue support.
4589  */
4590 static void
4591 em_enable_vectors_82574(if_ctx_t ctx)
4592 {
4593         struct adapter *adapter = iflib_get_softc(ctx);
4594         struct e1000_hw *hw = &adapter->hw;
4595         device_t dev = iflib_get_dev(ctx);
4596         u16 edata;
4597
4598         e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4599         if (bootverbose)
4600                 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata);
4601         if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
4602                 device_printf(dev, "Writing to eeprom: increasing "
4603                     "reported MSI-X vectors from 3 to 5...\n");
4604                 edata &= ~(EM_NVM_MSIX_N_MASK);
4605                 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
4606                 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4607                 e1000_update_nvm_checksum(hw);
4608                 device_printf(dev, "Writing to eeprom: done\n");
4609         }
4610 }