sys/dev/e1000/if_em.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /* $FreeBSD$ */
  30 #include "if_em.h"
  31 #include <sys/sbuf.h>
  32 #include <machine/_inttypes.h>
  33
  34 #define em_mac_min e1000_82547
  35 #define igb_mac_min e1000_82575
  36
  37 /*********************************************************************
  38  *  Driver version:
  39  *********************************************************************/
  40 char em_driver_version[] = "7.6.1-k";
  41
  42 /*********************************************************************
  43  *  PCI Device ID Table
  44  *
  45  *  Used by probe to select devices to load on
  46  *  Last field stores an index into e1000_strings
  47  *  Last entry must be all 0s
  48  *
  49  *  { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
  50  *********************************************************************/
  51
  52 static pci_vendor_info_t em_vendor_info_array[] =
  53 {
  54         /* Intel(R) PRO/1000 Network Connection - Legacy em*/
  55         PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"),
  56         PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"),
  57         PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"),
  58         PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"),
  59         PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"),
  60
  61         PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"),
  62         PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"),
  63         PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"),
  64         PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  65         PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"),
  66         PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"),
  67         PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  68
  69         PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"),
  70
  71         PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"),
  72         PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
  73
  74         PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
  75         PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
  76         PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
  77         PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"),
  78
  79         PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"),
  80         PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"),
  81         PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"),
  82         PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"),
  83         PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"),
  84
  85         PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  86         PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
  87         PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
  88         PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  89         PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"),
  90         PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"),
  91         PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"),
  92         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
  93         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"),
  94
  95         PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"),
  96         PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  97         PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"),
  98
  99         /* Intel(R) PRO/1000 Network Connection - em */
 100         PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
 101         PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
 102         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"),
 103         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"),
 104         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"),
 105         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 106         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"),
 107         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"),
 108         PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 109         PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"),
 110         PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
 111         PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
 112         PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"),
 113         PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"),
 114         PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"),
 115         PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"),
 116         PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"),
 117         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"),
 118         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"),
 119         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"),
 120         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"),
 121         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
 122         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 123         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"),
 124         PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"),
 125         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
 126         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"),
 127         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"),
 128         PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"),
 129         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
 130         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 131         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"),
 132         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"),
 133         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"),
 134         PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"),
 135         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
 136         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"),
 137         PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"),
 138         PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"),
 139         PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"),
 140         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"),
 141         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"),
 142         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"),
 143         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"),
 144         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"),
 145         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"),
 146         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"),
 147         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"),
 148         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"),
 149         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"),
 150         PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"),
 151         PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"),
 152         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"),
 153         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"),
 154         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"),
 155         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"),
 156         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"),
 157         PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"),
 158         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"),
 159         PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"),
 160         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"),
 161         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"),
 162         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"),
 163         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"),
 164         PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"),
 165         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"),
 166         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"),
 167         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"),
 168         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"),
 169         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) PRO/1000 Network Connection"),
 170         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) PRO/1000 Network Connection"),
 171         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) PRO/1000 Network Connection"),
 172         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) PRO/1000 Network Connection"),
 173         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) PRO/1000 Network Connection"),
 174         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) PRO/1000 Network Connection"),
 175         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) PRO/1000 Network Connection"),
 176         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) PRO/1000 Network Connection"),
 177         /* required last entry */
 178         PVID_END
 179 };
 180
 181 static pci_vendor_info_t igb_vendor_info_array[] =
 182 {
 183         /* Intel(R) PRO/1000 Network Connection - igb */
 184         PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 185         PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 186         PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 187         PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 188         PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 189         PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 190         PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 191         PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 192         PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 193         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 194         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 195         PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 196         PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 197         PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 198         PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 199         PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 200         PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 201         PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 202         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 203         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 204         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 205         PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 206         PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 207         PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 208         PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 209         PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 210         PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 211         PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 212         PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 213         PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 214         PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 215         PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 216         PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 217         PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 218         PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 219         PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 220         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 221         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 222         PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 223         /* required last entry */
 224         PVID_END
 225 };
 226
 227 /*********************************************************************
 228  *  Function prototypes
 229  *********************************************************************/
 230 static void     *em_register(device_t dev);
 231 static void     *igb_register(device_t dev);
 232 static int      em_if_attach_pre(if_ctx_t ctx);
 233 static int      em_if_attach_post(if_ctx_t ctx);
 234 static int      em_if_detach(if_ctx_t ctx);
 235 static int      em_if_shutdown(if_ctx_t ctx);
 236 static int      em_if_suspend(if_ctx_t ctx);
 237 static int      em_if_resume(if_ctx_t ctx);
 238
 239 static int      em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets);
 240 static int      em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets);
 241 static void     em_if_queues_free(if_ctx_t ctx);
 242
 243 static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
 244 static void     em_if_init(if_ctx_t ctx);
 245 static void     em_if_stop(if_ctx_t ctx);
 246 static void     em_if_media_status(if_ctx_t, struct ifmediareq *);
 247 static int      em_if_media_change(if_ctx_t ctx);
 248 static int      em_if_mtu_set(if_ctx_t ctx, uint32_t mtu);
 249 static void     em_if_timer(if_ctx_t ctx, uint16_t qid);
 250 static void     em_if_vlan_register(if_ctx_t ctx, u16 vtag);
 251 static void     em_if_vlan_unregister(if_ctx_t ctx, u16 vtag);
 252 static void     em_if_watchdog_reset(if_ctx_t ctx);
 253
 254 static void     em_identify_hardware(if_ctx_t ctx);
 255 static int      em_allocate_pci_resources(if_ctx_t ctx);
 256 static void     em_free_pci_resources(if_ctx_t ctx);
 257 static void     em_reset(if_ctx_t ctx);
 258 static int      em_setup_interface(if_ctx_t ctx);
 259 static int      em_setup_msix(if_ctx_t ctx);
 260
 261 static void     em_initialize_transmit_unit(if_ctx_t ctx);
 262 static void     em_initialize_receive_unit(if_ctx_t ctx);
 263
 264 static void     em_if_enable_intr(if_ctx_t ctx);
 265 static void     em_if_disable_intr(if_ctx_t ctx);
 266 static int      em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 267 static int      em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
 268 static void     em_if_multi_set(if_ctx_t ctx);
 269 static void     em_if_update_admin_status(if_ctx_t ctx);
 270 static void     em_if_debug(if_ctx_t ctx);
 271 static void     em_update_stats_counters(struct adapter *);
 272 static void     em_add_hw_stats(struct adapter *adapter);
 273 static int      em_if_set_promisc(if_ctx_t ctx, int flags);
 274 static void     em_setup_vlan_hw_support(struct adapter *);
 275 static int      em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
 276 static void     em_print_nvm_info(struct adapter *);
 277 static int      em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 278 static int      em_get_rs(SYSCTL_HANDLER_ARGS);
 279 static void     em_print_debug_info(struct adapter *);
 280 static int      em_is_valid_ether_addr(u8 *);
 281 static int      em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
 282 static void     em_add_int_delay_sysctl(struct adapter *, const char *,
 283                     const char *, struct em_int_delay_info *, int, int);
 284 /* Management and WOL Support */
 285 static void     em_init_manageability(struct adapter *);
 286 static void     em_release_manageability(struct adapter *);
 287 static void     em_get_hw_control(struct adapter *);
 288 static void     em_release_hw_control(struct adapter *);
 289 static void     em_get_wakeup(if_ctx_t ctx);
 290 static void     em_enable_wakeup(if_ctx_t ctx);
 291 static int      em_enable_phy_wakeup(struct adapter *);
 292 static void     em_disable_aspm(struct adapter *);
 293
 294 int             em_intr(void *arg);
 295 static void     em_disable_promisc(if_ctx_t ctx);
 296
 297 /* MSI-X handlers */
 298 static int      em_if_msix_intr_assign(if_ctx_t, int);
 299 static int      em_msix_link(void *);
 300 static void     em_handle_link(void *context);
 301
 302 static void     em_enable_vectors_82574(if_ctx_t);
 303
 304 static int      em_set_flowcntl(SYSCTL_HANDLER_ARGS);
 305 static int      em_sysctl_eee(SYSCTL_HANDLER_ARGS);
 306 static void     em_if_led_func(if_ctx_t ctx, int onoff);
 307
 308 static int      em_get_regs(SYSCTL_HANDLER_ARGS);
 309
 310 static void     lem_smartspeed(struct adapter *adapter);
 311 static void     igb_configure_queues(struct adapter *adapter);
 312
 313
 314 /*********************************************************************
 315  *  FreeBSD Device Interface Entry Points
 316  *********************************************************************/
 317 static device_method_t em_methods[] = {
 318         /* Device interface */
 319         DEVMETHOD(device_register, em_register),
 320         DEVMETHOD(device_probe, iflib_device_probe),
 321         DEVMETHOD(device_attach, iflib_device_attach),
 322         DEVMETHOD(device_detach, iflib_device_detach),
 323         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 324         DEVMETHOD(device_suspend, iflib_device_suspend),
 325         DEVMETHOD(device_resume, iflib_device_resume),
 326         DEVMETHOD_END
 327 };
 328
 329 static device_method_t igb_methods[] = {
 330         /* Device interface */
 331         DEVMETHOD(device_register, igb_register),
 332         DEVMETHOD(device_probe, iflib_device_probe),
 333         DEVMETHOD(device_attach, iflib_device_attach),
 334         DEVMETHOD(device_detach, iflib_device_detach),
 335         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 336         DEVMETHOD(device_suspend, iflib_device_suspend),
 337         DEVMETHOD(device_resume, iflib_device_resume),
 338         DEVMETHOD_END
 339 };
 340
 341
 342 static driver_t em_driver = {
 343         "em", em_methods, sizeof(struct adapter),
 344 };
 345
 346 static devclass_t em_devclass;
 347 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
 348
 349 MODULE_DEPEND(em, pci, 1, 1, 1);
 350 MODULE_DEPEND(em, ether, 1, 1, 1);
 351 MODULE_DEPEND(em, iflib, 1, 1, 1);
 352
 353 IFLIB_PNP_INFO(pci, em, em_vendor_info_array);
 354
 355 static driver_t igb_driver = {
 356         "igb", igb_methods, sizeof(struct adapter),
 357 };
 358
 359 static devclass_t igb_devclass;
 360 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
 361
 362 MODULE_DEPEND(igb, pci, 1, 1, 1);
 363 MODULE_DEPEND(igb, ether, 1, 1, 1);
 364 MODULE_DEPEND(igb, iflib, 1, 1, 1);
 365
 366 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array);
 367
 368 static device_method_t em_if_methods[] = {
 369         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 370         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 371         DEVMETHOD(ifdi_detach, em_if_detach),
 372         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 373         DEVMETHOD(ifdi_suspend, em_if_suspend),
 374         DEVMETHOD(ifdi_resume, em_if_resume),
 375         DEVMETHOD(ifdi_init, em_if_init),
 376         DEVMETHOD(ifdi_stop, em_if_stop),
 377         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 378         DEVMETHOD(ifdi_intr_enable, em_if_enable_intr),
 379         DEVMETHOD(ifdi_intr_disable, em_if_disable_intr),
 380         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 381         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 382         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 383         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 384         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 385         DEVMETHOD(ifdi_media_status, em_if_media_status),
 386         DEVMETHOD(ifdi_media_change, em_if_media_change),
 387         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 388         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 389         DEVMETHOD(ifdi_timer, em_if_timer),
 390         DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
 391         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 392         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 393         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 394         DEVMETHOD(ifdi_led_func, em_if_led_func),
 395         DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable),
 396         DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable),
 397         DEVMETHOD(ifdi_debug, em_if_debug),
 398         DEVMETHOD_END
 399 };
 400
 401 /*
 402  * note that if (adapter->msix_mem) is replaced by:
 403  * if (adapter->intr_type == IFLIB_INTR_MSIX)
 404  */
 405 static driver_t em_if_driver = {
 406         "em_if", em_if_methods, sizeof(struct adapter)
 407 };
 408
 409 /*********************************************************************
 410  *  Tunable default values.
 411  *********************************************************************/
 412
 413 #define EM_TICKS_TO_USECS(ticks)        ((1024 * (ticks) + 500) / 1000)
 414 #define EM_USECS_TO_TICKS(usecs)        ((1000 * (usecs) + 512) / 1024)
 415
 416 #define MAX_INTS_PER_SEC        8000
 417 #define DEFAULT_ITR             (1000000000/(MAX_INTS_PER_SEC * 256))
 418
 419 /* Allow common code without TSO */
 420 #ifndef CSUM_TSO
 421 #define CSUM_TSO        0
 422 #endif
 423
 424 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters");
 425
 426 static int em_disable_crc_stripping = 0;
 427 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
 428     &em_disable_crc_stripping, 0, "Disable CRC Stripping");
 429
 430 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
 431 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
 432 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
 433     0, "Default transmit interrupt delay in usecs");
 434 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
 435     0, "Default receive interrupt delay in usecs");
 436
 437 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
 438 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
 439 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
 440     &em_tx_abs_int_delay_dflt, 0,
 441     "Default transmit interrupt delay limit in usecs");
 442 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
 443     &em_rx_abs_int_delay_dflt, 0,
 444     "Default receive interrupt delay limit in usecs");
 445
 446 static int em_smart_pwr_down = FALSE;
 447 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
 448     0, "Set to true to leave smart power down enabled on newer adapters");
 449
 450 /* Controls whether promiscuous also shows bad packets */
 451 static int em_debug_sbp = TRUE;
 452 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
 453     "Show bad packets in promiscuous mode");
 454
 455 /* How many packets rxeof tries to clean at a time */
 456 static int em_rx_process_limit = 100;
 457 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
 458     &em_rx_process_limit, 0,
 459     "Maximum number of received packets to process "
 460     "at a time, -1 means unlimited");
 461
 462 /* Energy efficient ethernet - default to OFF */
 463 static int eee_setting = 1;
 464 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
 465     "Enable Energy Efficient Ethernet");
 466
 467 /*
 468 ** Tuneable Interrupt rate
 469 */
 470 static int em_max_interrupt_rate = 8000;
 471 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
 472     &em_max_interrupt_rate, 0, "Maximum interrupts per second");
 473
 474
 475
 476 /* Global used in WOL setup with multiport cards */
 477 static int global_quad_port_a = 0;
 478
 479 extern struct if_txrx igb_txrx;
 480 extern struct if_txrx em_txrx;
 481 extern struct if_txrx lem_txrx;
 482
 483 static struct if_shared_ctx em_sctx_init = {
 484         .isc_magic = IFLIB_MAGIC,
 485         .isc_q_align = PAGE_SIZE,
 486         .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 487         .isc_tx_maxsegsize = PAGE_SIZE,
 488         .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 489         .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
 490         .isc_rx_maxsize = MJUM9BYTES,
 491         .isc_rx_nsegments = 1,
 492         .isc_rx_maxsegsize = MJUM9BYTES,
 493         .isc_nfl = 1,
 494         .isc_nrxqs = 1,
 495         .isc_ntxqs = 1,
 496         .isc_admin_intrcnt = 1,
 497         .isc_vendor_info = em_vendor_info_array,
 498         .isc_driver_version = em_driver_version,
 499         .isc_driver = &em_if_driver,
 500         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 501
 502         .isc_nrxd_min = {EM_MIN_RXD},
 503         .isc_ntxd_min = {EM_MIN_TXD},
 504         .isc_nrxd_max = {EM_MAX_RXD},
 505         .isc_ntxd_max = {EM_MAX_TXD},
 506         .isc_nrxd_default = {EM_DEFAULT_RXD},
 507         .isc_ntxd_default = {EM_DEFAULT_TXD},
 508 };
 509
 510 if_shared_ctx_t em_sctx = &em_sctx_init;
 511
 512 static struct if_shared_ctx igb_sctx_init = {
 513         .isc_magic = IFLIB_MAGIC,
 514         .isc_q_align = PAGE_SIZE,
 515         .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 516         .isc_tx_maxsegsize = PAGE_SIZE,
 517         .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 518         .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
 519         .isc_rx_maxsize = MJUM9BYTES,
 520         .isc_rx_nsegments = 1,
 521         .isc_rx_maxsegsize = MJUM9BYTES,
 522         .isc_nfl = 1,
 523         .isc_nrxqs = 1,
 524         .isc_ntxqs = 1,
 525         .isc_admin_intrcnt = 1,
 526         .isc_vendor_info = igb_vendor_info_array,
 527         .isc_driver_version = em_driver_version,
 528         .isc_driver = &em_if_driver,
 529         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 530
 531         .isc_nrxd_min = {EM_MIN_RXD},
 532         .isc_ntxd_min = {EM_MIN_TXD},
 533         .isc_nrxd_max = {IGB_MAX_RXD},
 534         .isc_ntxd_max = {IGB_MAX_TXD},
 535         .isc_nrxd_default = {EM_DEFAULT_RXD},
 536         .isc_ntxd_default = {EM_DEFAULT_TXD},
 537 };
 538
 539 if_shared_ctx_t igb_sctx = &igb_sctx_init;
 540
 541 /*****************************************************************
 542  *
 543  * Dump Registers
 544  *
 545  ****************************************************************/
 546 #define IGB_REGS_LEN 739
 547
 548 static int em_get_regs(SYSCTL_HANDLER_ARGS)
 549 {
 550         struct adapter *adapter = (struct adapter *)arg1;
 551         struct e1000_hw *hw = &adapter->hw;
 552         struct sbuf *sb;
 553         u32 *regs_buff;
 554         int rc;
 555
 556         regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK);
 557         memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
 558
 559         rc = sysctl_wire_old_buffer(req, 0);
 560         MPASS(rc == 0);
 561         if (rc != 0) {
 562                 free(regs_buff, M_DEVBUF);
 563                 return (rc);
 564         }
 565
 566         sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
 567         MPASS(sb != NULL);
 568         if (sb == NULL) {
 569                 free(regs_buff, M_DEVBUF);
 570                 return (ENOMEM);
 571         }
 572
 573         /* General Registers */
 574         regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
 575         regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
 576         regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
 577         regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
 578         regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
 579         regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
 580         regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
 581         regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
 582         regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
 583         regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
 584         regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
 585         regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
 586         regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
 587         regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
 588         regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
 589         regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
 590         regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
 591         regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
 592         regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
 593         regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
 594         regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
 595         regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
 596
 597         sbuf_printf(sb, "General Registers\n");
 598         sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
 599         sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
 600         sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]);
 601
 602         sbuf_printf(sb, "Interrupt Registers\n");
 603         sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
 604
 605         sbuf_printf(sb, "RX Registers\n");
 606         sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
 607         sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
 608         sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
 609         sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
 610         sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
 611         sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
 612         sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
 613
 614         sbuf_printf(sb, "TX Registers\n");
 615         sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
 616         sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
 617         sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
 618         sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
 619         sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
 620         sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
 621         sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
 622         sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
 623         sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
 624         sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
 625         sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
 626
 627         free(regs_buff, M_DEVBUF);
 628
 629 #ifdef DUMP_DESCS
 630         {
 631                 if_softc_ctx_t scctx = adapter->shared;
 632                 struct rx_ring *rxr = &rx_que->rxr;
 633                 struct tx_ring *txr = &tx_que->txr;
 634                 int ntxd = scctx->isc_ntxd[0];
 635                 int nrxd = scctx->isc_nrxd[0];
 636                 int j;
 637
 638         for (j = 0; j < nrxd; j++) {
 639                 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
 640                 u32 length =  le32toh(rxr->rx_base[j].wb.upper.length);
 641                 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 "  Error:%d  Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
 642         }
 643
 644         for (j = 0; j < min(ntxd, 256); j++) {
 645                 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
 646
 647                 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x  eop: %d DD=%d\n",
 648                             j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
 649                             buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
 650
 651         }
 652         }
 653 #endif
 654
 655         rc = sbuf_finish(sb);
 656         sbuf_delete(sb);
 657         return(rc);
 658 }
 659
 660 static void *
 661 em_register(device_t dev)
 662 {
 663         return (em_sctx);
 664 }
 665
 666 static void *
 667 igb_register(device_t dev)
 668 {
 669         return (igb_sctx);
 670 }
 671
 672 static int
 673 em_set_num_queues(if_ctx_t ctx)
 674 {
 675         struct adapter *adapter = iflib_get_softc(ctx);
 676         int maxqueues;
 677
 678         /* Sanity check based on HW */
 679         switch (adapter->hw.mac.type) {
 680         case e1000_82576:
 681         case e1000_82580:
 682         case e1000_i350:
 683         case e1000_i354:
 684                 maxqueues = 8;
 685                 break;
 686         case e1000_i210:
 687         case e1000_82575:
 688                 maxqueues = 4;
 689                 break;
 690         case e1000_i211:
 691         case e1000_82574:
 692                 maxqueues = 2;
 693                 break;
 694         default:
 695                 maxqueues = 1;
 696                 break;
 697         }
 698
 699         return (maxqueues);
 700 }
 701
 702 #define LEM_CAPS                                                        \
 703     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 704     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER
 705
 706 #define EM_CAPS                                                         \
 707     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 708     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 |  \
 709     IFCAP_LRO | IFCAP_VLAN_HWTSO
 710
 711 #define IGB_CAPS                                                        \
 712     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 713     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 |  \
 714     IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\
 715     IFCAP_TSO6
 716
 717 /*********************************************************************
 718  *  Device initialization routine
 719  *
 720  *  The attach entry point is called when the driver is being loaded.
 721  *  This routine identifies the type of hardware, allocates all resources
 722  *  and initializes the hardware.
 723  *
 724  *  return 0 on success, positive on failure
 725  *********************************************************************/
 726 static int
 727 em_if_attach_pre(if_ctx_t ctx)
 728 {
 729         struct adapter *adapter;
 730         if_softc_ctx_t scctx;
 731         device_t dev;
 732         struct e1000_hw *hw;
 733         int error = 0;
 734
 735         INIT_DEBUGOUT("em_if_attach_pre: begin");
 736         dev = iflib_get_dev(ctx);
 737         adapter = iflib_get_softc(ctx);
 738
 739         adapter->ctx = adapter->osdep.ctx = ctx;
 740         adapter->dev = adapter->osdep.dev = dev;
 741         scctx = adapter->shared = iflib_get_softc_ctx(ctx);
 742         adapter->media = iflib_get_media(ctx);
 743         hw = &adapter->hw;
 744
 745         adapter->tx_process_limit = scctx->isc_ntxd[0];
 746
 747         /* SYSCTL stuff */
 748         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 749             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 750             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 751             em_sysctl_nvm_info, "I", "NVM Information");
 752
 753         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 754             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 755             OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 756             em_sysctl_debug_info, "I", "Debug Information");
 757
 758         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 759             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 760             OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 761             em_set_flowcntl, "I", "Flow Control");
 762
 763         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 764             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 765             OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0,
 766             em_get_regs, "A", "Dump Registers");
 767
 768         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 769             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 770             OID_AUTO, "rs_dump", CTLTYPE_INT | CTLFLAG_RW, adapter, 0,
 771             em_get_rs, "I", "Dump RS indexes");
 772
 773         /* Determine hardware and mac info */
 774         em_identify_hardware(ctx);
 775
 776         scctx->isc_tx_nsegments = EM_MAX_SCATTER;
 777         scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
 778         if (bootverbose)
 779                 device_printf(dev, "attach_pre capping queues at %d\n",
 780                     scctx->isc_ntxqsets_max);
 781
 782         if (adapter->hw.mac.type >= igb_mac_min) {
 783                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
 784                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
 785                 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
 786                 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
 787                 scctx->isc_txrx = &igb_txrx;
 788                 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
 789                 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 790                 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 791                 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS;
 792                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO |
 793                      CSUM_IP6_TCP | CSUM_IP6_UDP;
 794                 if (adapter->hw.mac.type != e1000_82575)
 795                         scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
 796                 /*
 797                 ** Some new devices, as with ixgbe, now may
 798                 ** use a different BAR, so we need to keep
 799                 ** track of which is used.
 800                 */
 801                 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR);
 802                 if (pci_read_config(dev, scctx->isc_msix_bar, 4) == 0)
 803                         scctx->isc_msix_bar += 4;
 804         } else if (adapter->hw.mac.type >= em_mac_min) {
 805                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 806                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
 807                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 808                 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
 809                 scctx->isc_txrx = &em_txrx;
 810                 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
 811                 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 812                 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 813                 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS;
 814                 /*
 815                  * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO}
 816                  * by default as we don't have workarounds for all associated
 817                  * silicon errata.  E. g., with several MACs such as 82573E,
 818                  * TSO only works at Gigabit speed and otherwise can cause the
 819                  * hardware to hang (which also would be next to impossible to
 820                  * work around given that already queued TSO-using descriptors
 821                  * would need to be flushed and vlan(4) reconfigured at runtime
 822                  * in case of a link speed change).  Moreover, MACs like 82579
 823                  * still can hang at Gigabit even with all publicly documented
 824                  * TSO workarounds implemented.  Generally, the penality of
 825                  * these workarounds is rather high and may involve copying
 826                  * mbuf data around so advantages of TSO lapse.  Still, TSO may
 827                  * work for a few MACs of this class - at least when sticking
 828                  * with Gigabit - in which case users may enable TSO manually.
 829                  */
 830                 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
 831                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 832                 /*
 833                  * We support MSI-X with 82574 only, but indicate to iflib(4)
 834                  * that it shall give MSI at least a try with other devices.
 835                  */
 836                 if (adapter->hw.mac.type == e1000_82574) {
 837                         scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR);
 838                 } else {
 839                         scctx->isc_msix_bar = -1;
 840                         scctx->isc_disable_msix = 1;
 841                 }
 842         } else {
 843                 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 844                 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
 845                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 846                 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
 847                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP;
 848                 scctx->isc_txrx = &lem_txrx;
 849                 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS;
 850                 if (adapter->hw.mac.type < e1000_82543)
 851                         scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
 852                 /* INTx only */
 853                 scctx->isc_msix_bar = 0;
 854         }
 855
 856         /* Setup PCI resources */
 857         if (em_allocate_pci_resources(ctx)) {
 858                 device_printf(dev, "Allocation of PCI resources failed\n");
 859                 error = ENXIO;
 860                 goto err_pci;
 861         }
 862
 863         /*
 864         ** For ICH8 and family we need to
 865         ** map the flash memory, and this
 866         ** must happen after the MAC is
 867         ** identified
 868         */
 869         if ((hw->mac.type == e1000_ich8lan) ||
 870             (hw->mac.type == e1000_ich9lan) ||
 871             (hw->mac.type == e1000_ich10lan) ||
 872             (hw->mac.type == e1000_pchlan) ||
 873             (hw->mac.type == e1000_pch2lan) ||
 874             (hw->mac.type == e1000_pch_lpt)) {
 875                 int rid = EM_BAR_TYPE_FLASH;
 876                 adapter->flash = bus_alloc_resource_any(dev,
 877                     SYS_RES_MEMORY, &rid, RF_ACTIVE);
 878                 if (adapter->flash == NULL) {
 879                         device_printf(dev, "Mapping of Flash failed\n");
 880                         error = ENXIO;
 881                         goto err_pci;
 882                 }
 883                 /* This is used in the shared code */
 884                 hw->flash_address = (u8 *)adapter->flash;
 885                 adapter->osdep.flash_bus_space_tag =
 886                     rman_get_bustag(adapter->flash);
 887                 adapter->osdep.flash_bus_space_handle =
 888                     rman_get_bushandle(adapter->flash);
 889         }
 890         /*
 891         ** In the new SPT device flash is not  a
 892         ** separate BAR, rather it is also in BAR0,
 893         ** so use the same tag and an offset handle for the
 894         ** FLASH read/write macros in the shared code.
 895         */
 896         else if (hw->mac.type >= e1000_pch_spt) {
 897                 adapter->osdep.flash_bus_space_tag =
 898                     adapter->osdep.mem_bus_space_tag;
 899                 adapter->osdep.flash_bus_space_handle =
 900                     adapter->osdep.mem_bus_space_handle
 901                     + E1000_FLASH_BASE_ADDR;
 902         }
 903
 904         /* Do Shared Code initialization */
 905         error = e1000_setup_init_funcs(hw, TRUE);
 906         if (error) {
 907                 device_printf(dev, "Setup of Shared code failed, error %d\n",
 908                     error);
 909                 error = ENXIO;
 910                 goto err_pci;
 911         }
 912
 913         em_setup_msix(ctx);
 914         e1000_get_bus_info(hw);
 915
 916         /* Set up some sysctls for the tunable interrupt delays */
 917         em_add_int_delay_sysctl(adapter, "rx_int_delay",
 918             "receive interrupt delay in usecs", &adapter->rx_int_delay,
 919             E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
 920         em_add_int_delay_sysctl(adapter, "tx_int_delay",
 921             "transmit interrupt delay in usecs", &adapter->tx_int_delay,
 922             E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
 923         em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
 924             "receive interrupt delay limit in usecs",
 925             &adapter->rx_abs_int_delay,
 926             E1000_REGISTER(hw, E1000_RADV),
 927             em_rx_abs_int_delay_dflt);
 928         em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
 929             "transmit interrupt delay limit in usecs",
 930             &adapter->tx_abs_int_delay,
 931             E1000_REGISTER(hw, E1000_TADV),
 932             em_tx_abs_int_delay_dflt);
 933         em_add_int_delay_sysctl(adapter, "itr",
 934             "interrupt delay limit in usecs/4",
 935             &adapter->tx_itr,
 936             E1000_REGISTER(hw, E1000_ITR),
 937             DEFAULT_ITR);
 938
 939         hw->mac.autoneg = DO_AUTO_NEG;
 940         hw->phy.autoneg_wait_to_complete = FALSE;
 941         hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 942
 943         if (adapter->hw.mac.type < em_mac_min) {
 944                 e1000_init_script_state_82541(&adapter->hw, TRUE);
 945                 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
 946         }
 947         /* Copper options */
 948         if (hw->phy.media_type == e1000_media_type_copper) {
 949                 hw->phy.mdix = AUTO_ALL_MODES;
 950                 hw->phy.disable_polarity_correction = FALSE;
 951                 hw->phy.ms_type = EM_MASTER_SLAVE;
 952         }
 953
 954         /*
 955          * Set the frame limits assuming
 956          * standard ethernet sized frames.
 957          */
 958         scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
 959             ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
 960
 961         /*
 962          * This controls when hardware reports transmit completion
 963          * status.
 964          */
 965         hw->mac.report_tx_early = 1;
 966
 967         /* Allocate multicast array memory. */
 968         adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN *
 969             MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
 970         if (adapter->mta == NULL) {
 971                 device_printf(dev, "Can not allocate multicast setup array\n");
 972                 error = ENOMEM;
 973                 goto err_late;
 974         }
 975
 976         /* Check SOL/IDER usage */
 977         if (e1000_check_reset_block(hw))
 978                 device_printf(dev, "PHY reset is blocked"
 979                               " due to SOL/IDER session.\n");
 980
 981         /* Sysctl for setting Energy Efficient Ethernet */
 982         hw->dev_spec.ich8lan.eee_disable = eee_setting;
 983         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 984             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 985             OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW,
 986             adapter, 0, em_sysctl_eee, "I",
 987             "Disable Energy Efficient Ethernet");
 988
 989         /*
 990         ** Start from a known state, this is
 991         ** important in reading the nvm and
 992         ** mac from that.
 993         */
 994         e1000_reset_hw(hw);
 995
 996         /* Make sure we have a good EEPROM before we read from it */
 997         if (e1000_validate_nvm_checksum(hw) < 0) {
 998                 /*
 999                 ** Some PCI-E parts fail the first check due to
1000                 ** the link being in sleep state, call it again,
1001                 ** if it fails a second time its a real issue.
1002                 */
1003                 if (e1000_validate_nvm_checksum(hw) < 0) {
1004                         device_printf(dev,
1005                             "The EEPROM Checksum Is Not Valid\n");
1006                         error = EIO;
1007                         goto err_late;
1008                 }
1009         }
1010
1011         /* Copy the permanent MAC address out of the EEPROM */
1012         if (e1000_read_mac_addr(hw) < 0) {
1013                 device_printf(dev, "EEPROM read error while reading MAC"
1014                               " address\n");
1015                 error = EIO;
1016                 goto err_late;
1017         }
1018
1019         if (!em_is_valid_ether_addr(hw->mac.addr)) {
1020                 device_printf(dev, "Invalid MAC address\n");
1021                 error = EIO;
1022                 goto err_late;
1023         }
1024
1025         /* Disable ULP support */
1026         e1000_disable_ulp_lpt_lp(hw, TRUE);
1027
1028         /*
1029          * Get Wake-on-Lan and Management info for later use
1030          */
1031         em_get_wakeup(ctx);
1032
1033         /* Enable only WOL MAGIC by default */
1034         scctx->isc_capenable &= ~IFCAP_WOL;
1035         if (adapter->wol != 0)
1036                 scctx->isc_capenable |= IFCAP_WOL_MAGIC;
1037
1038         iflib_set_mac(ctx, hw->mac.addr);
1039
1040         return (0);
1041
1042 err_late:
1043         em_release_hw_control(adapter);
1044 err_pci:
1045         em_free_pci_resources(ctx);
1046         free(adapter->mta, M_DEVBUF);
1047
1048         return (error);
1049 }
1050
1051 static int
1052 em_if_attach_post(if_ctx_t ctx)
1053 {
1054         struct adapter *adapter = iflib_get_softc(ctx);
1055         struct e1000_hw *hw = &adapter->hw;
1056         int error = 0;
1057
1058         /* Setup OS specific network interface */
1059         error = em_setup_interface(ctx);
1060         if (error != 0) {
1061                 goto err_late;
1062         }
1063
1064         em_reset(ctx);
1065
1066         /* Initialize statistics */
1067         em_update_stats_counters(adapter);
1068         hw->mac.get_link_status = 1;
1069         em_if_update_admin_status(ctx);
1070         em_add_hw_stats(adapter);
1071
1072         /* Non-AMT based hardware can now take control from firmware */
1073         if (adapter->has_manage && !adapter->has_amt)
1074                 em_get_hw_control(adapter);
1075
1076         INIT_DEBUGOUT("em_if_attach_post: end");
1077
1078         return (error);
1079
1080 err_late:
1081         em_release_hw_control(adapter);
1082         em_free_pci_resources(ctx);
1083         em_if_queues_free(ctx);
1084         free(adapter->mta, M_DEVBUF);
1085
1086         return (error);
1087 }
1088
1089 /*********************************************************************
1090  *  Device removal routine
1091  *
1092  *  The detach entry point is called when the driver is being removed.
1093  *  This routine stops the adapter and deallocates all the resources
1094  *  that were allocated for driver operation.
1095  *
1096  *  return 0 on success, positive on failure
1097  *********************************************************************/
1098 static int
1099 em_if_detach(if_ctx_t ctx)
1100 {
1101         struct adapter  *adapter = iflib_get_softc(ctx);
1102
1103         INIT_DEBUGOUT("em_if_detach: begin");
1104
1105         e1000_phy_hw_reset(&adapter->hw);
1106
1107         em_release_manageability(adapter);
1108         em_release_hw_control(adapter);
1109         em_free_pci_resources(ctx);
1110
1111         return (0);
1112 }
1113
1114 /*********************************************************************
1115  *
1116  *  Shutdown entry point
1117  *
1118  **********************************************************************/
1119
1120 static int
1121 em_if_shutdown(if_ctx_t ctx)
1122 {
1123         return em_if_suspend(ctx);
1124 }
1125
1126 /*
1127  * Suspend/resume device methods.
1128  */
1129 static int
1130 em_if_suspend(if_ctx_t ctx)
1131 {
1132         struct adapter *adapter = iflib_get_softc(ctx);
1133
1134         em_release_manageability(adapter);
1135         em_release_hw_control(adapter);
1136         em_enable_wakeup(ctx);
1137         return (0);
1138 }
1139
1140 static int
1141 em_if_resume(if_ctx_t ctx)
1142 {
1143         struct adapter *adapter = iflib_get_softc(ctx);
1144
1145         if (adapter->hw.mac.type == e1000_pch2lan)
1146                 e1000_resume_workarounds_pchlan(&adapter->hw);
1147         em_if_init(ctx);
1148         em_init_manageability(adapter);
1149
1150         return(0);
1151 }
1152
1153 static int
1154 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1155 {
1156         int max_frame_size;
1157         struct adapter *adapter = iflib_get_softc(ctx);
1158         if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1159
1160          IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1161
1162         switch (adapter->hw.mac.type) {
1163         case e1000_82571:
1164         case e1000_82572:
1165         case e1000_ich9lan:
1166         case e1000_ich10lan:
1167         case e1000_pch2lan:
1168         case e1000_pch_lpt:
1169         case e1000_pch_spt:
1170         case e1000_pch_cnp:
1171         case e1000_82574:
1172         case e1000_82583:
1173         case e1000_80003es2lan:
1174                 /* 9K Jumbo Frame size */
1175                 max_frame_size = 9234;
1176                 break;
1177         case e1000_pchlan:
1178                 max_frame_size = 4096;
1179                 break;
1180         case e1000_82542:
1181         case e1000_ich8lan:
1182                 /* Adapters that do not support jumbo frames */
1183                 max_frame_size = ETHER_MAX_LEN;
1184                 break;
1185         default:
1186                 if (adapter->hw.mac.type >= igb_mac_min)
1187                         max_frame_size = 9234;
1188                 else /* lem */
1189                         max_frame_size = MAX_JUMBO_FRAME_SIZE;
1190         }
1191         if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1192                 return (EINVAL);
1193         }
1194
1195         scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
1196             mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1197         return (0);
1198 }
1199
1200 /*********************************************************************
1201  *  Init entry point
1202  *
1203  *  This routine is used in two ways. It is used by the stack as
1204  *  init entry point in network interface structure. It is also used
1205  *  by the driver as a hw/sw initialization routine to get to a
1206  *  consistent state.
1207  *
1208  **********************************************************************/
1209 static void
1210 em_if_init(if_ctx_t ctx)
1211 {
1212         struct adapter *adapter = iflib_get_softc(ctx);
1213         if_softc_ctx_t scctx = adapter->shared;
1214         struct ifnet *ifp = iflib_get_ifp(ctx);
1215         struct em_tx_queue *tx_que;
1216         int i;
1217
1218         INIT_DEBUGOUT("em_if_init: begin");
1219
1220         /* Get the latest mac address, User can use a LAA */
1221         bcopy(if_getlladdr(ifp), adapter->hw.mac.addr,
1222             ETHER_ADDR_LEN);
1223
1224         /* Put the address into the Receive Address Array */
1225         e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1226
1227         /*
1228          * With the 82571 adapter, RAR[0] may be overwritten
1229          * when the other port is reset, we make a duplicate
1230          * in RAR[14] for that eventuality, this assures
1231          * the interface continues to function.
1232          */
1233         if (adapter->hw.mac.type == e1000_82571) {
1234                 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1235                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1236                     E1000_RAR_ENTRIES - 1);
1237         }
1238
1239
1240         /* Initialize the hardware */
1241         em_reset(ctx);
1242         em_if_update_admin_status(ctx);
1243
1244         for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) {
1245                 struct tx_ring *txr = &tx_que->txr;
1246
1247                 txr->tx_rs_cidx = txr->tx_rs_pidx;
1248
1249                 /* Initialize the last processed descriptor to be the end of
1250                  * the ring, rather than the start, so that we avoid an
1251                  * off-by-one error when calculating how many descriptors are
1252                  * done in the credits_update function.
1253                  */
1254                 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
1255         }
1256
1257         /* Setup VLAN support, basic and offload if available */
1258         E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1259
1260         /* Clear bad data from Rx FIFOs */
1261         if (adapter->hw.mac.type >= igb_mac_min)
1262                 e1000_rx_fifo_flush_82575(&adapter->hw);
1263
1264         /* Configure for OS presence */
1265         em_init_manageability(adapter);
1266
1267         /* Prepare transmit descriptors and buffers */
1268         em_initialize_transmit_unit(ctx);
1269
1270         /* Setup Multicast table */
1271         em_if_multi_set(ctx);
1272
1273         /*
1274          * Figure out the desired mbuf
1275          * pool for doing jumbos
1276          */
1277         if (adapter->hw.mac.max_frame_size <= 2048)
1278                 adapter->rx_mbuf_sz = MCLBYTES;
1279         else
1280                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
1281         em_initialize_receive_unit(ctx);
1282
1283         /* Use real VLAN Filter support? */
1284         if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1285                 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
1286                         /* Use real VLAN Filter support */
1287                         em_setup_vlan_hw_support(adapter);
1288                 else {
1289                         u32 ctrl;
1290                         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1291                         ctrl |= E1000_CTRL_VME;
1292                         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1293                 }
1294         }
1295
1296         /* Don't lose promiscuous settings */
1297         em_if_set_promisc(ctx, IFF_PROMISC);
1298         e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1299
1300         /* MSI-X configuration for 82574 */
1301         if (adapter->hw.mac.type == e1000_82574) {
1302                 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1303
1304                 tmp |= E1000_CTRL_EXT_PBA_CLR;
1305                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1306                 /* Set the IVAR - interrupt vector routing. */
1307                 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars);
1308         } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1309                 igb_configure_queues(adapter);
1310
1311         /* this clears any pending interrupts */
1312         E1000_READ_REG(&adapter->hw, E1000_ICR);
1313         E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC);
1314
1315         /* AMT based hardware can now take control from firmware */
1316         if (adapter->has_manage && adapter->has_amt)
1317                 em_get_hw_control(adapter);
1318
1319         /* Set Energy Efficient Ethernet */
1320         if (adapter->hw.mac.type >= igb_mac_min &&
1321             adapter->hw.phy.media_type == e1000_media_type_copper) {
1322                 if (adapter->hw.mac.type == e1000_i354)
1323                         e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
1324                 else
1325                         e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
1326         }
1327 }
1328
1329 /*********************************************************************
1330  *
1331  *  Fast Legacy/MSI Combined Interrupt Service routine
1332  *
1333  *********************************************************************/
1334 int
1335 em_intr(void *arg)
1336 {
1337         struct adapter *adapter = arg;
1338         if_ctx_t ctx = adapter->ctx;
1339         u32 reg_icr;
1340
1341         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1342
1343         if (adapter->intr_type != IFLIB_INTR_LEGACY)
1344                 goto skip_stray;
1345         /* Hot eject? */
1346         if (reg_icr == 0xffffffff)
1347                 return FILTER_STRAY;
1348
1349         /* Definitely not our interrupt. */
1350         if (reg_icr == 0x0)
1351                 return FILTER_STRAY;
1352
1353         /*
1354          * Starting with the 82571 chip, bit 31 should be used to
1355          * determine whether the interrupt belongs to us.
1356          */
1357         if (adapter->hw.mac.type >= e1000_82571 &&
1358             (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1359                 return FILTER_STRAY;
1360
1361 skip_stray:
1362         /* Link status change */
1363         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1364                 adapter->hw.mac.get_link_status = 1;
1365                 iflib_admin_intr_deferred(ctx);
1366         }
1367
1368         if (reg_icr & E1000_ICR_RXO)
1369                 adapter->rx_overruns++;
1370
1371         return (FILTER_SCHEDULE_THREAD);
1372 }
1373
1374 static void
1375 igb_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq)
1376 {
1377         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims);
1378 }
1379
1380 static void
1381 em_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq)
1382 {
1383         E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims);
1384 }
1385
1386 static void
1387 igb_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq)
1388 {
1389         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims);
1390 }
1391
1392 static void
1393 em_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq)
1394 {
1395         E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims);
1396 }
1397
1398 static int
1399 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1400 {
1401         struct adapter *adapter = iflib_get_softc(ctx);
1402         struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1403
1404         if (adapter->hw.mac.type >= igb_mac_min)
1405                 igb_rx_enable_queue(adapter, rxq);
1406         else
1407                 em_rx_enable_queue(adapter, rxq);
1408         return (0);
1409 }
1410
1411 static int
1412 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1413 {
1414         struct adapter *adapter = iflib_get_softc(ctx);
1415         struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1416
1417         if (adapter->hw.mac.type >= igb_mac_min)
1418                 igb_tx_enable_queue(adapter, txq);
1419         else
1420                 em_tx_enable_queue(adapter, txq);
1421         return (0);
1422 }
1423
1424 /*********************************************************************
1425  *
1426  *  MSI-X RX Interrupt Service routine
1427  *
1428  **********************************************************************/
1429 static int
1430 em_msix_que(void *arg)
1431 {
1432         struct em_rx_queue *que = arg;
1433
1434         ++que->irqs;
1435
1436         return (FILTER_SCHEDULE_THREAD);
1437 }
1438
1439 /*********************************************************************
1440  *
1441  *  MSI-X Link Fast Interrupt Service routine
1442  *
1443  **********************************************************************/
1444 static int
1445 em_msix_link(void *arg)
1446 {
1447         struct adapter *adapter = arg;
1448         u32 reg_icr;
1449
1450         ++adapter->link_irq;
1451         MPASS(adapter->hw.back != NULL);
1452         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1453
1454         if (reg_icr & E1000_ICR_RXO)
1455                 adapter->rx_overruns++;
1456
1457         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1458                 em_handle_link(adapter->ctx);
1459         } else {
1460                 E1000_WRITE_REG(&adapter->hw, E1000_IMS,
1461                                 EM_MSIX_LINK | E1000_IMS_LSC);
1462                 if (adapter->hw.mac.type >= igb_mac_min)
1463                         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1464         }
1465
1466         /*
1467          * Because we must read the ICR for this interrupt
1468          * it may clear other causes using autoclear, for
1469          * this reason we simply create a soft interrupt
1470          * for all these vectors.
1471          */
1472         if (reg_icr && adapter->hw.mac.type < igb_mac_min) {
1473                 E1000_WRITE_REG(&adapter->hw,
1474                         E1000_ICS, adapter->ims);
1475         }
1476
1477         return (FILTER_HANDLED);
1478 }
1479
1480 static void
1481 em_handle_link(void *context)
1482 {
1483         if_ctx_t ctx = context;
1484         struct adapter *adapter = iflib_get_softc(ctx);
1485
1486         adapter->hw.mac.get_link_status = 1;
1487         iflib_admin_intr_deferred(ctx);
1488 }
1489
1490
1491 /*********************************************************************
1492  *
1493  *  Media Ioctl callback
1494  *
1495  *  This routine is called whenever the user queries the status of
1496  *  the interface using ifconfig.
1497  *
1498  **********************************************************************/
1499 static void
1500 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1501 {
1502         struct adapter *adapter = iflib_get_softc(ctx);
1503         u_char fiber_type = IFM_1000_SX;
1504
1505         INIT_DEBUGOUT("em_if_media_status: begin");
1506
1507         iflib_admin_intr_deferred(ctx);
1508
1509         ifmr->ifm_status = IFM_AVALID;
1510         ifmr->ifm_active = IFM_ETHER;
1511
1512         if (!adapter->link_active) {
1513                 return;
1514         }
1515
1516         ifmr->ifm_status |= IFM_ACTIVE;
1517
1518         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
1519             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1520                 if (adapter->hw.mac.type == e1000_82545)
1521                         fiber_type = IFM_1000_LX;
1522                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1523         } else {
1524                 switch (adapter->link_speed) {
1525                 case 10:
1526                         ifmr->ifm_active |= IFM_10_T;
1527                         break;
1528                 case 100:
1529                         ifmr->ifm_active |= IFM_100_TX;
1530                         break;
1531                 case 1000:
1532                         ifmr->ifm_active |= IFM_1000_T;
1533                         break;
1534                 }
1535                 if (adapter->link_duplex == FULL_DUPLEX)
1536                         ifmr->ifm_active |= IFM_FDX;
1537                 else
1538                         ifmr->ifm_active |= IFM_HDX;
1539         }
1540 }
1541
1542 /*********************************************************************
1543  *
1544  *  Media Ioctl callback
1545  *
1546  *  This routine is called when the user changes speed/duplex using
1547  *  media/mediopt option with ifconfig.
1548  *
1549  **********************************************************************/
1550 static int
1551 em_if_media_change(if_ctx_t ctx)
1552 {
1553         struct adapter *adapter = iflib_get_softc(ctx);
1554         struct ifmedia *ifm = iflib_get_media(ctx);
1555
1556         INIT_DEBUGOUT("em_if_media_change: begin");
1557
1558         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1559                 return (EINVAL);
1560
1561         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1562         case IFM_AUTO:
1563                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1564                 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1565                 break;
1566         case IFM_1000_LX:
1567         case IFM_1000_SX:
1568         case IFM_1000_T:
1569                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1570                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1571                 break;
1572         case IFM_100_TX:
1573                 adapter->hw.mac.autoneg = FALSE;
1574                 adapter->hw.phy.autoneg_advertised = 0;
1575                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1576                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1577                 else
1578                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1579                 break;
1580         case IFM_10_T:
1581                 adapter->hw.mac.autoneg = FALSE;
1582                 adapter->hw.phy.autoneg_advertised = 0;
1583                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1584                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1585                 else
1586                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1587                 break;
1588         default:
1589                 device_printf(adapter->dev, "Unsupported media type\n");
1590         }
1591
1592         em_if_init(ctx);
1593
1594         return (0);
1595 }
1596
1597 static int
1598 em_if_set_promisc(if_ctx_t ctx, int flags)
1599 {
1600         struct adapter *adapter = iflib_get_softc(ctx);
1601         u32 reg_rctl;
1602
1603         em_disable_promisc(ctx);
1604
1605         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1606
1607         if (flags & IFF_PROMISC) {
1608                 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1609                 /* Turn this on if you want to see bad packets */
1610                 if (em_debug_sbp)
1611                         reg_rctl |= E1000_RCTL_SBP;
1612                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1613         } else if (flags & IFF_ALLMULTI) {
1614                 reg_rctl |= E1000_RCTL_MPE;
1615                 reg_rctl &= ~E1000_RCTL_UPE;
1616                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1617         }
1618         return (0);
1619 }
1620
1621 static void
1622 em_disable_promisc(if_ctx_t ctx)
1623 {
1624         struct adapter *adapter = iflib_get_softc(ctx);
1625         struct ifnet *ifp = iflib_get_ifp(ctx);
1626         u32 reg_rctl;
1627         int mcnt = 0;
1628
1629         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1630         reg_rctl &= (~E1000_RCTL_UPE);
1631         if (if_getflags(ifp) & IFF_ALLMULTI)
1632                 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1633         else
1634                 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES);
1635         /* Don't disable if in MAX groups */
1636         if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1637                 reg_rctl &=  (~E1000_RCTL_MPE);
1638         reg_rctl &=  (~E1000_RCTL_SBP);
1639         E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1640 }
1641
1642
1643 /*********************************************************************
1644  *  Multicast Update
1645  *
1646  *  This routine is called whenever multicast address list is updated.
1647  *
1648  **********************************************************************/
1649
1650 static void
1651 em_if_multi_set(if_ctx_t ctx)
1652 {
1653         struct adapter *adapter = iflib_get_softc(ctx);
1654         struct ifnet *ifp = iflib_get_ifp(ctx);
1655         u32 reg_rctl = 0;
1656         u8  *mta; /* Multicast array memory */
1657         int mcnt = 0;
1658
1659         IOCTL_DEBUGOUT("em_set_multi: begin");
1660
1661         mta = adapter->mta;
1662         bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1663
1664         if (adapter->hw.mac.type == e1000_82542 &&
1665             adapter->hw.revision_id == E1000_REVISION_2) {
1666                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1667                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1668                         e1000_pci_clear_mwi(&adapter->hw);
1669                 reg_rctl |= E1000_RCTL_RST;
1670                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1671                 msec_delay(5);
1672         }
1673
1674         if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES);
1675
1676         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1677                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1678                 reg_rctl |= E1000_RCTL_MPE;
1679                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1680         } else
1681                 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
1682
1683         if (adapter->hw.mac.type == e1000_82542 &&
1684             adapter->hw.revision_id == E1000_REVISION_2) {
1685                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1686                 reg_rctl &= ~E1000_RCTL_RST;
1687                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1688                 msec_delay(5);
1689                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1690                         e1000_pci_set_mwi(&adapter->hw);
1691         }
1692 }
1693
1694 /*********************************************************************
1695  *  Timer routine
1696  *
1697  *  This routine schedules em_if_update_admin_status() to check for
1698  *  link status and to gather statistics as well as to perform some
1699  *  controller-specific hardware patting.
1700  *
1701  **********************************************************************/
1702 static void
1703 em_if_timer(if_ctx_t ctx, uint16_t qid)
1704 {
1705
1706         if (qid != 0)
1707                 return;
1708
1709         iflib_admin_intr_deferred(ctx);
1710 }
1711
1712 static void
1713 em_if_update_admin_status(if_ctx_t ctx)
1714 {
1715         struct adapter *adapter = iflib_get_softc(ctx);
1716         struct e1000_hw *hw = &adapter->hw;
1717         device_t dev = iflib_get_dev(ctx);
1718         u32 link_check, thstat, ctrl;
1719
1720         link_check = thstat = ctrl = 0;
1721         /* Get the cached link value or read phy for real */
1722         switch (hw->phy.media_type) {
1723         case e1000_media_type_copper:
1724                 if (hw->mac.get_link_status) {
1725                         if (hw->mac.type == e1000_pch_spt)
1726                                 msec_delay(50);
1727                         /* Do the work to read phy */
1728                         e1000_check_for_link(hw);
1729                         link_check = !hw->mac.get_link_status;
1730                         if (link_check) /* ESB2 fix */
1731                                 e1000_cfg_on_link_up(hw);
1732                 } else {
1733                         link_check = TRUE;
1734                 }
1735                 break;
1736         case e1000_media_type_fiber:
1737                 e1000_check_for_link(hw);
1738                 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1739                             E1000_STATUS_LU);
1740                 break;
1741         case e1000_media_type_internal_serdes:
1742                 e1000_check_for_link(hw);
1743                 link_check = adapter->hw.mac.serdes_has_link;
1744                 break;
1745         /* VF device is type_unknown */
1746         case e1000_media_type_unknown:
1747                 e1000_check_for_link(hw);
1748                 link_check = !hw->mac.get_link_status;
1749                 /* FALLTHROUGH */
1750         default:
1751                 break;
1752         }
1753
1754         /* Check for thermal downshift or shutdown */
1755         if (hw->mac.type == e1000_i350) {
1756                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1757                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1758         }
1759
1760         /* Now check for a transition */
1761         if (link_check && (adapter->link_active == 0)) {
1762                 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
1763                     &adapter->link_duplex);
1764                 /* Check if we must disable SPEED_MODE bit on PCI-E */
1765                 if ((adapter->link_speed != SPEED_1000) &&
1766                     ((hw->mac.type == e1000_82571) ||
1767                     (hw->mac.type == e1000_82572))) {
1768                         int tarc0;
1769                         tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1770                         tarc0 &= ~TARC_SPEED_MODE_BIT;
1771                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1772                 }
1773                 if (bootverbose)
1774                         device_printf(dev, "Link is up %d Mbps %s\n",
1775                             adapter->link_speed,
1776                             ((adapter->link_duplex == FULL_DUPLEX) ?
1777                             "Full Duplex" : "Half Duplex"));
1778                 adapter->link_active = 1;
1779                 adapter->smartspeed = 0;
1780                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) ==
1781                     E1000_CTRL_EXT_LINK_MODE_GMII &&
1782                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1783                         device_printf(dev, "Link: thermal downshift\n");
1784                 /* Delay Link Up for Phy update */
1785                 if (((hw->mac.type == e1000_i210) ||
1786                     (hw->mac.type == e1000_i211)) &&
1787                     (hw->phy.id == I210_I_PHY_ID))
1788                         msec_delay(I210_LINK_DELAY);
1789                 /* Reset if the media type changed. */
1790                 if ((hw->dev_spec._82575.media_changed) &&
1791                         (adapter->hw.mac.type >= igb_mac_min)) {
1792                         hw->dev_spec._82575.media_changed = false;
1793                         adapter->flags |= IGB_MEDIA_RESET;
1794                         em_reset(ctx);
1795                 }
1796                 iflib_link_state_change(ctx, LINK_STATE_UP,
1797                     IF_Mbps(adapter->link_speed));
1798         } else if (!link_check && (adapter->link_active == 1)) {
1799                 adapter->link_speed = 0;
1800                 adapter->link_duplex = 0;
1801                 adapter->link_active = 0;
1802                 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
1803         }
1804         em_update_stats_counters(adapter);
1805
1806         /* Reset LAA into RAR[0] on 82571 */
1807         if ((adapter->hw.mac.type == e1000_82571) &&
1808             e1000_get_laa_state_82571(&adapter->hw))
1809                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1810
1811         if (adapter->hw.mac.type < em_mac_min)
1812                 lem_smartspeed(adapter);
1813
1814         E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC);
1815 }
1816
1817 static void
1818 em_if_watchdog_reset(if_ctx_t ctx)
1819 {
1820         struct adapter *adapter = iflib_get_softc(ctx);
1821
1822         /*
1823          * Just count the event; iflib(4) will already trigger a
1824          * sufficient reset of the controller.
1825          */
1826         adapter->watchdog_events++;
1827 }
1828
1829 /*********************************************************************
1830  *
1831  *  This routine disables all traffic on the adapter by issuing a
1832  *  global reset on the MAC.
1833  *
1834  **********************************************************************/
1835 static void
1836 em_if_stop(if_ctx_t ctx)
1837 {
1838         struct adapter *adapter = iflib_get_softc(ctx);
1839
1840         INIT_DEBUGOUT("em_if_stop: begin");
1841
1842         e1000_reset_hw(&adapter->hw);
1843         if (adapter->hw.mac.type >= e1000_82544)
1844                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0);
1845
1846         e1000_led_off(&adapter->hw);
1847         e1000_cleanup_led(&adapter->hw);
1848 }
1849
1850 /*********************************************************************
1851  *
1852  *  Determine hardware revision.
1853  *
1854  **********************************************************************/
1855 static void
1856 em_identify_hardware(if_ctx_t ctx)
1857 {
1858         device_t dev = iflib_get_dev(ctx);
1859         struct adapter *adapter = iflib_get_softc(ctx);
1860
1861         /* Make sure our PCI config space has the necessary stuff set */
1862         adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1863
1864         /* Save off the information about this board */
1865         adapter->hw.vendor_id = pci_get_vendor(dev);
1866         adapter->hw.device_id = pci_get_device(dev);
1867         adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1868         adapter->hw.subsystem_vendor_id =
1869             pci_read_config(dev, PCIR_SUBVEND_0, 2);
1870         adapter->hw.subsystem_device_id =
1871             pci_read_config(dev, PCIR_SUBDEV_0, 2);
1872
1873         /* Do Shared Code Init and Setup */
1874         if (e1000_set_mac_type(&adapter->hw)) {
1875                 device_printf(dev, "Setup init failure\n");
1876                 return;
1877         }
1878 }
1879
1880 static int
1881 em_allocate_pci_resources(if_ctx_t ctx)
1882 {
1883         struct adapter *adapter = iflib_get_softc(ctx);
1884         device_t dev = iflib_get_dev(ctx);
1885         int rid, val;
1886
1887         rid = PCIR_BAR(0);
1888         adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1889             &rid, RF_ACTIVE);
1890         if (adapter->memory == NULL) {
1891                 device_printf(dev, "Unable to allocate bus resource: memory\n");
1892                 return (ENXIO);
1893         }
1894         adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory);
1895         adapter->osdep.mem_bus_space_handle =
1896             rman_get_bushandle(adapter->memory);
1897         adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle;
1898
1899         /* Only older adapters use IO mapping */
1900         if (adapter->hw.mac.type < em_mac_min &&
1901             adapter->hw.mac.type > e1000_82543) {
1902                 /* Figure our where our IO BAR is ? */
1903                 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1904                         val = pci_read_config(dev, rid, 4);
1905                         if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1906                                 break;
1907                         }
1908                         rid += 4;
1909                         /* check for 64bit BAR */
1910                         if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1911                                 rid += 4;
1912                 }
1913                 if (rid >= PCIR_CIS) {
1914                         device_printf(dev, "Unable to locate IO BAR\n");
1915                         return (ENXIO);
1916                 }
1917                 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
1918                     &rid, RF_ACTIVE);
1919                 if (adapter->ioport == NULL) {
1920                         device_printf(dev, "Unable to allocate bus resource: "
1921                             "ioport\n");
1922                         return (ENXIO);
1923                 }
1924                 adapter->hw.io_base = 0;
1925                 adapter->osdep.io_bus_space_tag =
1926                     rman_get_bustag(adapter->ioport);
1927                 adapter->osdep.io_bus_space_handle =
1928                     rman_get_bushandle(adapter->ioport);
1929         }
1930
1931         adapter->hw.back = &adapter->osdep;
1932
1933         return (0);
1934 }
1935
1936 /*********************************************************************
1937  *
1938  *  Set up the MSI-X Interrupt handlers
1939  *
1940  **********************************************************************/
1941 static int
1942 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
1943 {
1944         struct adapter *adapter = iflib_get_softc(ctx);
1945         struct em_rx_queue *rx_que = adapter->rx_queues;
1946         struct em_tx_queue *tx_que = adapter->tx_queues;
1947         int error, rid, i, vector = 0, rx_vectors;
1948         char buf[16];
1949
1950         /* First set up ring resources */
1951         for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) {
1952                 rid = vector + 1;
1953                 snprintf(buf, sizeof(buf), "rxq%d", i);
1954                 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
1955                 if (error) {
1956                         device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
1957                         adapter->rx_num_queues = i + 1;
1958                         goto fail;
1959                 }
1960
1961                 rx_que->msix =  vector;
1962
1963                 /*
1964                  * Set the bit to enable interrupt
1965                  * in E1000_IMS -- bits 20 and 21
1966                  * are for RX0 and RX1, note this has
1967                  * NOTHING to do with the MSI-X vector
1968                  */
1969                 if (adapter->hw.mac.type == e1000_82574) {
1970                         rx_que->eims = 1 << (20 + i);
1971                         adapter->ims |= rx_que->eims;
1972                         adapter->ivars |= (8 | rx_que->msix) << (i * 4);
1973                 } else if (adapter->hw.mac.type == e1000_82575)
1974                         rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
1975                 else
1976                         rx_que->eims = 1 << vector;
1977         }
1978         rx_vectors = vector;
1979
1980         vector = 0;
1981         for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) {
1982                 snprintf(buf, sizeof(buf), "txq%d", i);
1983                 tx_que = &adapter->tx_queues[i];
1984                 iflib_softirq_alloc_generic(ctx,
1985                     &adapter->rx_queues[i % adapter->rx_num_queues].que_irq,
1986                     IFLIB_INTR_TX, tx_que, tx_que->me, buf);
1987
1988                 tx_que->msix = (vector % adapter->rx_num_queues);
1989
1990                 /*
1991                  * Set the bit to enable interrupt
1992                  * in E1000_IMS -- bits 22 and 23
1993                  * are for TX0 and TX1, note this has
1994                  * NOTHING to do with the MSI-X vector
1995                  */
1996                 if (adapter->hw.mac.type == e1000_82574) {
1997                         tx_que->eims = 1 << (22 + i);
1998                         adapter->ims |= tx_que->eims;
1999                         adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
2000                 } else if (adapter->hw.mac.type == e1000_82575) {
2001                         tx_que->eims = E1000_EICR_TX_QUEUE0 << i;
2002                 } else {
2003                         tx_que->eims = 1 << i;
2004                 }
2005         }
2006
2007         /* Link interrupt */
2008         rid = rx_vectors + 1;
2009         error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq");
2010
2011         if (error) {
2012                 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
2013                 goto fail;
2014         }
2015         adapter->linkvec = rx_vectors;
2016         if (adapter->hw.mac.type < igb_mac_min) {
2017                 adapter->ivars |=  (8 | rx_vectors) << 16;
2018                 adapter->ivars |= 0x80000000;
2019         }
2020         return (0);
2021 fail:
2022         iflib_irq_free(ctx, &adapter->irq);
2023         rx_que = adapter->rx_queues;
2024         for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++)
2025                 iflib_irq_free(ctx, &rx_que->que_irq);
2026         return (error);
2027 }
2028
2029 static void
2030 igb_configure_queues(struct adapter *adapter)
2031 {
2032         struct e1000_hw *hw = &adapter->hw;
2033         struct em_rx_queue *rx_que;
2034         struct em_tx_queue *tx_que;
2035         u32 tmp, ivar = 0, newitr = 0;
2036
2037         /* First turn on RSS capability */
2038         if (adapter->hw.mac.type != e1000_82575)
2039                 E1000_WRITE_REG(hw, E1000_GPIE,
2040                     E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
2041                     E1000_GPIE_PBA | E1000_GPIE_NSICR);
2042
2043         /* Turn on MSI-X */
2044         switch (adapter->hw.mac.type) {
2045         case e1000_82580:
2046         case e1000_i350:
2047         case e1000_i354:
2048         case e1000_i210:
2049         case e1000_i211:
2050         case e1000_vfadapt:
2051         case e1000_vfadapt_i350:
2052                 /* RX entries */
2053                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2054                         u32 index = i >> 1;
2055                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2056                         rx_que = &adapter->rx_queues[i];
2057                         if (i & 1) {
2058                                 ivar &= 0xFF00FFFF;
2059                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2060                         } else {
2061                                 ivar &= 0xFFFFFF00;
2062                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2063                         }
2064                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2065                 }
2066                 /* TX entries */
2067                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2068                         u32 index = i >> 1;
2069                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2070                         tx_que = &adapter->tx_queues[i];
2071                         if (i & 1) {
2072                                 ivar &= 0x00FFFFFF;
2073                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2074                         } else {
2075                                 ivar &= 0xFFFF00FF;
2076                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2077                         }
2078                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2079                         adapter->que_mask |= tx_que->eims;
2080                 }
2081
2082                 /* And for the link interrupt */
2083                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2084                 adapter->link_mask = 1 << adapter->linkvec;
2085                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2086                 break;
2087         case e1000_82576:
2088                 /* RX entries */
2089                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2090                         u32 index = i & 0x7; /* Each IVAR has two entries */
2091                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2092                         rx_que = &adapter->rx_queues[i];
2093                         if (i < 8) {
2094                                 ivar &= 0xFFFFFF00;
2095                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2096                         } else {
2097                                 ivar &= 0xFF00FFFF;
2098                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2099                         }
2100                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2101                         adapter->que_mask |= rx_que->eims;
2102                 }
2103                 /* TX entries */
2104                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2105                         u32 index = i & 0x7; /* Each IVAR has two entries */
2106                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2107                         tx_que = &adapter->tx_queues[i];
2108                         if (i < 8) {
2109                                 ivar &= 0xFFFF00FF;
2110                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2111                         } else {
2112                                 ivar &= 0x00FFFFFF;
2113                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2114                         }
2115                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2116                         adapter->que_mask |= tx_que->eims;
2117                 }
2118
2119                 /* And for the link interrupt */
2120                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2121                 adapter->link_mask = 1 << adapter->linkvec;
2122                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2123                 break;
2124
2125         case e1000_82575:
2126                 /* enable MSI-X support*/
2127                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2128                 tmp |= E1000_CTRL_EXT_PBA_CLR;
2129                 /* Auto-Mask interrupts upon ICR read. */
2130                 tmp |= E1000_CTRL_EXT_EIAME;
2131                 tmp |= E1000_CTRL_EXT_IRCA;
2132                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2133
2134                 /* Queues */
2135                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2136                         rx_que = &adapter->rx_queues[i];
2137                         tmp = E1000_EICR_RX_QUEUE0 << i;
2138                         tmp |= E1000_EICR_TX_QUEUE0 << i;
2139                         rx_que->eims = tmp;
2140                         E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2141                             i, rx_que->eims);
2142                         adapter->que_mask |= rx_que->eims;
2143                 }
2144
2145                 /* Link */
2146                 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec),
2147                     E1000_EIMS_OTHER);
2148                 adapter->link_mask |= E1000_EIMS_OTHER;
2149         default:
2150                 break;
2151         }
2152
2153         /* Set the starting interrupt rate */
2154         if (em_max_interrupt_rate > 0)
2155                 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2156
2157         if (hw->mac.type == e1000_82575)
2158                 newitr |= newitr << 16;
2159         else
2160                 newitr |= E1000_EITR_CNT_IGNR;
2161
2162         for (int i = 0; i < adapter->rx_num_queues; i++) {
2163                 rx_que = &adapter->rx_queues[i];
2164                 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2165         }
2166
2167         return;
2168 }
2169
2170 static void
2171 em_free_pci_resources(if_ctx_t ctx)
2172 {
2173         struct adapter *adapter = iflib_get_softc(ctx);
2174         struct em_rx_queue *que = adapter->rx_queues;
2175         device_t dev = iflib_get_dev(ctx);
2176
2177         /* Release all MSI-X queue resources */
2178         if (adapter->intr_type == IFLIB_INTR_MSIX)
2179                 iflib_irq_free(ctx, &adapter->irq);
2180
2181         for (int i = 0; i < adapter->rx_num_queues; i++, que++) {
2182                 iflib_irq_free(ctx, &que->que_irq);
2183         }
2184
2185         if (adapter->memory != NULL) {
2186                 bus_release_resource(dev, SYS_RES_MEMORY,
2187                     rman_get_rid(adapter->memory), adapter->memory);
2188                 adapter->memory = NULL;
2189         }
2190
2191         if (adapter->flash != NULL) {
2192                 bus_release_resource(dev, SYS_RES_MEMORY,
2193                     rman_get_rid(adapter->flash), adapter->flash);
2194                 adapter->flash = NULL;
2195         }
2196
2197         if (adapter->ioport != NULL) {
2198                 bus_release_resource(dev, SYS_RES_IOPORT,
2199                     rman_get_rid(adapter->ioport), adapter->ioport);
2200                 adapter->ioport = NULL;
2201         }
2202 }
2203
2204 /* Set up MSI or MSI-X */
2205 static int
2206 em_setup_msix(if_ctx_t ctx)
2207 {
2208         struct adapter *adapter = iflib_get_softc(ctx);
2209
2210         if (adapter->hw.mac.type == e1000_82574) {
2211                 em_enable_vectors_82574(ctx);
2212         }
2213         return (0);
2214 }
2215
2216 /*********************************************************************
2217  *
2218  *  Workaround for SmartSpeed on 82541 and 82547 controllers
2219  *
2220  **********************************************************************/
2221 static void
2222 lem_smartspeed(struct adapter *adapter)
2223 {
2224         u16 phy_tmp;
2225
2226         if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) ||
2227             adapter->hw.mac.autoneg == 0 ||
2228             (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2229                 return;
2230
2231         if (adapter->smartspeed == 0) {
2232                 /* If Master/Slave config fault is asserted twice,
2233                  * we assume back-to-back */
2234                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2235                 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2236                         return;
2237                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2238                 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2239                         e1000_read_phy_reg(&adapter->hw,
2240                             PHY_1000T_CTRL, &phy_tmp);
2241                         if(phy_tmp & CR_1000T_MS_ENABLE) {
2242                                 phy_tmp &= ~CR_1000T_MS_ENABLE;
2243                                 e1000_write_phy_reg(&adapter->hw,
2244                                     PHY_1000T_CTRL, phy_tmp);
2245                                 adapter->smartspeed++;
2246                                 if(adapter->hw.mac.autoneg &&
2247                                    !e1000_copper_link_autoneg(&adapter->hw) &&
2248                                    !e1000_read_phy_reg(&adapter->hw,
2249                                     PHY_CONTROL, &phy_tmp)) {
2250                                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2251                                                     MII_CR_RESTART_AUTO_NEG);
2252                                         e1000_write_phy_reg(&adapter->hw,
2253                                             PHY_CONTROL, phy_tmp);
2254                                 }
2255                         }
2256                 }
2257                 return;
2258         } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2259                 /* If still no link, perhaps using 2/3 pair cable */
2260                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2261                 phy_tmp |= CR_1000T_MS_ENABLE;
2262                 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2263                 if(adapter->hw.mac.autoneg &&
2264                    !e1000_copper_link_autoneg(&adapter->hw) &&
2265                    !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2266                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2267                                     MII_CR_RESTART_AUTO_NEG);
2268                         e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2269                 }
2270         }
2271         /* Restart process after EM_SMARTSPEED_MAX iterations */
2272         if(adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2273                 adapter->smartspeed = 0;
2274 }
2275
2276 /*********************************************************************
2277  *
2278  *  Initialize the DMA Coalescing feature
2279  *
2280  **********************************************************************/
2281 static void
2282 igb_init_dmac(struct adapter *adapter, u32 pba)
2283 {
2284         device_t        dev = adapter->dev;
2285         struct e1000_hw *hw = &adapter->hw;
2286         u32             dmac, reg = ~E1000_DMACR_DMAC_EN;
2287         u16             hwm;
2288         u16             max_frame_size;
2289
2290         if (hw->mac.type == e1000_i211)
2291                 return;
2292
2293         max_frame_size = adapter->shared->isc_max_frame_size;
2294         if (hw->mac.type > e1000_82580) {
2295
2296                 if (adapter->dmac == 0) { /* Disabling it */
2297                         E1000_WRITE_REG(hw, E1000_DMACR, reg);
2298                         return;
2299                 } else
2300                         device_printf(dev, "DMA Coalescing enabled\n");
2301
2302                 /* Set starting threshold */
2303                 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
2304
2305                 hwm = 64 * pba - max_frame_size / 16;
2306                 if (hwm < 64 * (pba - 6))
2307                         hwm = 64 * (pba - 6);
2308                 reg = E1000_READ_REG(hw, E1000_FCRTC);
2309                 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
2310                 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
2311                     & E1000_FCRTC_RTH_COAL_MASK);
2312                 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
2313
2314
2315                 dmac = pba - max_frame_size / 512;
2316                 if (dmac < pba - 10)
2317                         dmac = pba - 10;
2318                 reg = E1000_READ_REG(hw, E1000_DMACR);
2319                 reg &= ~E1000_DMACR_DMACTHR_MASK;
2320                 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT)
2321                     & E1000_DMACR_DMACTHR_MASK);
2322
2323                 /* transition to L0x or L1 if available..*/
2324                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
2325
2326                 /* Check if status is 2.5Gb backplane connection
2327                 * before configuration of watchdog timer, which is
2328                 * in msec values in 12.8usec intervals
2329                 * watchdog timer= msec values in 32usec intervals
2330                 * for non 2.5Gb connection
2331                 */
2332                 if (hw->mac.type == e1000_i354) {
2333                         int status = E1000_READ_REG(hw, E1000_STATUS);
2334                         if ((status & E1000_STATUS_2P5_SKU) &&
2335                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2336                                 reg |= ((adapter->dmac * 5) >> 6);
2337                         else
2338                                 reg |= (adapter->dmac >> 5);
2339                 } else {
2340                         reg |= (adapter->dmac >> 5);
2341                 }
2342
2343                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2344
2345                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
2346
2347                 /* Set the interval before transition */
2348                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
2349                 if (hw->mac.type == e1000_i350)
2350                         reg |= IGB_DMCTLX_DCFLUSH_DIS;
2351                 /*
2352                 ** in 2.5Gb connection, TTLX unit is 0.4 usec
2353                 ** which is 0x4*2 = 0xA. But delay is still 4 usec
2354                 */
2355                 if (hw->mac.type == e1000_i354) {
2356                         int status = E1000_READ_REG(hw, E1000_STATUS);
2357                         if ((status & E1000_STATUS_2P5_SKU) &&
2358                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2359                                 reg |= 0xA;
2360                         else
2361                                 reg |= 0x4;
2362                 } else {
2363                         reg |= 0x4;
2364                 }
2365
2366                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
2367
2368                 /* free space in tx packet buffer to wake from DMA coal */
2369                 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE -
2370                     (2 * max_frame_size)) >> 6);
2371
2372                 /* make low power state decision controlled by DMA coal */
2373                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2374                 reg &= ~E1000_PCIEMISC_LX_DECISION;
2375                 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
2376
2377         } else if (hw->mac.type == e1000_82580) {
2378                 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2379                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
2380                     reg & ~E1000_PCIEMISC_LX_DECISION);
2381                 E1000_WRITE_REG(hw, E1000_DMACR, 0);
2382         }
2383 }
2384
2385 /*********************************************************************
2386  *
2387  *  Initialize the hardware to a configuration as specified by the
2388  *  adapter structure.
2389  *
2390  **********************************************************************/
2391 static void
2392 em_reset(if_ctx_t ctx)
2393 {
2394         device_t dev = iflib_get_dev(ctx);
2395         struct adapter *adapter = iflib_get_softc(ctx);
2396         struct ifnet *ifp = iflib_get_ifp(ctx);
2397         struct e1000_hw *hw = &adapter->hw;
2398         u16 rx_buffer_size;
2399         u32 pba;
2400
2401         INIT_DEBUGOUT("em_reset: begin");
2402         /* Let the firmware know the OS is in control */
2403         em_get_hw_control(adapter);
2404
2405         /* Set up smart power down as default off on newer adapters. */
2406         if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2407             hw->mac.type == e1000_82572)) {
2408                 u16 phy_tmp = 0;
2409
2410                 /* Speed up time to link by disabling smart power down. */
2411                 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2412                 phy_tmp &= ~IGP02E1000_PM_SPD;
2413                 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2414         }
2415
2416         /*
2417          * Packet Buffer Allocation (PBA)
2418          * Writing PBA sets the receive portion of the buffer
2419          * the remainder is used for the transmit buffer.
2420          */
2421         switch (hw->mac.type) {
2422         /* Total Packet Buffer on these is 48K */
2423         case e1000_82571:
2424         case e1000_82572:
2425         case e1000_80003es2lan:
2426                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2427                 break;
2428         case e1000_82573: /* 82573: Total Packet Buffer is 32K */
2429                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2430                 break;
2431         case e1000_82574:
2432         case e1000_82583:
2433                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2434                 break;
2435         case e1000_ich8lan:
2436                 pba = E1000_PBA_8K;
2437                 break;
2438         case e1000_ich9lan:
2439         case e1000_ich10lan:
2440                 /* Boost Receive side for jumbo frames */
2441                 if (adapter->hw.mac.max_frame_size > 4096)
2442                         pba = E1000_PBA_14K;
2443                 else
2444                         pba = E1000_PBA_10K;
2445                 break;
2446         case e1000_pchlan:
2447         case e1000_pch2lan:
2448         case e1000_pch_lpt:
2449         case e1000_pch_spt:
2450         case e1000_pch_cnp:
2451                 pba = E1000_PBA_26K;
2452                 break;
2453         case e1000_82575:
2454                 pba = E1000_PBA_32K;
2455                 break;
2456         case e1000_82576:
2457         case e1000_vfadapt:
2458                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2459                 pba &= E1000_RXPBS_SIZE_MASK_82576;
2460                 break;
2461         case e1000_82580:
2462         case e1000_i350:
2463         case e1000_i354:
2464         case e1000_vfadapt_i350:
2465                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2466                 pba = e1000_rxpbs_adjust_82580(pba);
2467                 break;
2468         case e1000_i210:
2469         case e1000_i211:
2470                 pba = E1000_PBA_34K;
2471                 break;
2472         default:
2473                 if (adapter->hw.mac.max_frame_size > 8192)
2474                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2475                 else
2476                         pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2477         }
2478
2479         /* Special needs in case of Jumbo frames */
2480         if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) {
2481                 u32 tx_space, min_tx, min_rx;
2482                 pba = E1000_READ_REG(hw, E1000_PBA);
2483                 tx_space = pba >> 16;
2484                 pba &= 0xffff;
2485                 min_tx = (adapter->hw.mac.max_frame_size +
2486                     sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
2487                 min_tx = roundup2(min_tx, 1024);
2488                 min_tx >>= 10;
2489                 min_rx = adapter->hw.mac.max_frame_size;
2490                 min_rx = roundup2(min_rx, 1024);
2491                 min_rx >>= 10;
2492                 if (tx_space < min_tx &&
2493                     ((min_tx - tx_space) < pba)) {
2494                         pba = pba - (min_tx - tx_space);
2495                         /*
2496                          * if short on rx space, rx wins
2497                          * and must trump tx adjustment
2498                          */
2499                         if (pba < min_rx)
2500                                 pba = min_rx;
2501                 }
2502                 E1000_WRITE_REG(hw, E1000_PBA, pba);
2503         }
2504
2505         if (hw->mac.type < igb_mac_min)
2506                 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
2507
2508         INIT_DEBUGOUT1("em_reset: pba=%dK",pba);
2509
2510         /*
2511          * These parameters control the automatic generation (Tx) and
2512          * response (Rx) to Ethernet PAUSE frames.
2513          * - High water mark should allow for at least two frames to be
2514          *   received after sending an XOFF.
2515          * - Low water mark works best when it is very near the high water mark.
2516          *   This allows the receiver to restart by sending XON when it has
2517          *   drained a bit. Here we use an arbitrary value of 1500 which will
2518          *   restart after one full frame is pulled from the buffer. There
2519          *   could be several smaller frames in the buffer and if so they will
2520          *   not trigger the XON until their total number reduces the buffer
2521          *   by 1500.
2522          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2523          */
2524         rx_buffer_size = (pba & 0xffff) << 10;
2525         hw->fc.high_water = rx_buffer_size -
2526             roundup2(adapter->hw.mac.max_frame_size, 1024);
2527         hw->fc.low_water = hw->fc.high_water - 1500;
2528
2529         if (adapter->fc) /* locally set flow control value? */
2530                 hw->fc.requested_mode = adapter->fc;
2531         else
2532                 hw->fc.requested_mode = e1000_fc_full;
2533
2534         if (hw->mac.type == e1000_80003es2lan)
2535                 hw->fc.pause_time = 0xFFFF;
2536         else
2537                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
2538
2539         hw->fc.send_xon = TRUE;
2540
2541         /* Device specific overrides/settings */
2542         switch (hw->mac.type) {
2543         case e1000_pchlan:
2544                 /* Workaround: no TX flow ctrl for PCH */
2545                 hw->fc.requested_mode = e1000_fc_rx_pause;
2546                 hw->fc.pause_time = 0xFFFF; /* override */
2547                 if (if_getmtu(ifp) > ETHERMTU) {
2548                         hw->fc.high_water = 0x3500;
2549                         hw->fc.low_water = 0x1500;
2550                 } else {
2551                         hw->fc.high_water = 0x5000;
2552                         hw->fc.low_water = 0x3000;
2553                 }
2554                 hw->fc.refresh_time = 0x1000;
2555                 break;
2556         case e1000_pch2lan:
2557         case e1000_pch_lpt:
2558         case e1000_pch_spt:
2559         case e1000_pch_cnp:
2560                 hw->fc.high_water = 0x5C20;
2561                 hw->fc.low_water = 0x5048;
2562                 hw->fc.pause_time = 0x0650;
2563                 hw->fc.refresh_time = 0x0400;
2564                 /* Jumbos need adjusted PBA */
2565                 if (if_getmtu(ifp) > ETHERMTU)
2566                         E1000_WRITE_REG(hw, E1000_PBA, 12);
2567                 else
2568                         E1000_WRITE_REG(hw, E1000_PBA, 26);
2569                 break;
2570         case e1000_82575:
2571         case e1000_82576:
2572                 /* 8-byte granularity */
2573                 hw->fc.low_water = hw->fc.high_water - 8;
2574                 break;
2575         case e1000_82580:
2576         case e1000_i350:
2577         case e1000_i354:
2578         case e1000_i210:
2579         case e1000_i211:
2580         case e1000_vfadapt:
2581         case e1000_vfadapt_i350:
2582                 /* 16-byte granularity */
2583                 hw->fc.low_water = hw->fc.high_water - 16;
2584                 break;
2585         case e1000_ich9lan:
2586         case e1000_ich10lan:
2587                 if (if_getmtu(ifp) > ETHERMTU) {
2588                         hw->fc.high_water = 0x2800;
2589                         hw->fc.low_water = hw->fc.high_water - 8;
2590                         break;
2591                 }
2592                 /* FALLTHROUGH */
2593         default:
2594                 if (hw->mac.type == e1000_80003es2lan)
2595                         hw->fc.pause_time = 0xFFFF;
2596                 break;
2597         }
2598
2599         /* Issue a global reset */
2600         e1000_reset_hw(hw);
2601         if (adapter->hw.mac.type >= igb_mac_min) {
2602                 E1000_WRITE_REG(hw, E1000_WUC, 0);
2603         } else {
2604                 E1000_WRITE_REG(hw, E1000_WUFC, 0);
2605                 em_disable_aspm(adapter);
2606         }
2607         if (adapter->flags & IGB_MEDIA_RESET) {
2608                 e1000_setup_init_funcs(hw, TRUE);
2609                 e1000_get_bus_info(hw);
2610                 adapter->flags &= ~IGB_MEDIA_RESET;
2611         }
2612         /* and a re-init */
2613         if (e1000_init_hw(hw) < 0) {
2614                 device_printf(dev, "Hardware Initialization Failed\n");
2615                 return;
2616         }
2617         if (adapter->hw.mac.type >= igb_mac_min)
2618                 igb_init_dmac(adapter, pba);
2619
2620         E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2621         e1000_get_phy_info(hw);
2622         e1000_check_for_link(hw);
2623 }
2624
2625 /*
2626  * Initialise the RSS mapping for NICs that support multiple transmit/
2627  * receive rings.
2628  */
2629
2630 #define RSSKEYLEN 10
2631 static void
2632 em_initialize_rss_mapping(struct adapter *adapter)
2633 {
2634         uint8_t  rss_key[4 * RSSKEYLEN];
2635         uint32_t reta = 0;
2636         struct e1000_hw *hw = &adapter->hw;
2637         int i;
2638
2639         /*
2640          * Configure RSS key
2641          */
2642         arc4rand(rss_key, sizeof(rss_key), 0);
2643         for (i = 0; i < RSSKEYLEN; ++i) {
2644                 uint32_t rssrk = 0;
2645
2646                 rssrk = EM_RSSRK_VAL(rss_key, i);
2647                 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2648         }
2649
2650         /*
2651          * Configure RSS redirect table in following fashion:
2652          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2653          */
2654         for (i = 0; i < sizeof(reta); ++i) {
2655                 uint32_t q;
2656
2657                 q = (i % adapter->rx_num_queues) << 7;
2658                 reta |= q << (8 * i);
2659         }
2660
2661         for (i = 0; i < 32; ++i)
2662                 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2663
2664         E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2665                         E1000_MRQC_RSS_FIELD_IPV4_TCP |
2666                         E1000_MRQC_RSS_FIELD_IPV4 |
2667                         E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2668                         E1000_MRQC_RSS_FIELD_IPV6_EX |
2669                         E1000_MRQC_RSS_FIELD_IPV6);
2670 }
2671
2672 static void
2673 igb_initialize_rss_mapping(struct adapter *adapter)
2674 {
2675         struct e1000_hw *hw = &adapter->hw;
2676         int i;
2677         int queue_id;
2678         u32 reta;
2679         u32 rss_key[10], mrqc, shift = 0;
2680
2681         /* XXX? */
2682         if (adapter->hw.mac.type == e1000_82575)
2683                 shift = 6;
2684
2685         /*
2686          * The redirection table controls which destination
2687          * queue each bucket redirects traffic to.
2688          * Each DWORD represents four queues, with the LSB
2689          * being the first queue in the DWORD.
2690          *
2691          * This just allocates buckets to queues using round-robin
2692          * allocation.
2693          *
2694          * NOTE: It Just Happens to line up with the default
2695          * RSS allocation method.
2696          */
2697
2698         /* Warning FM follows */
2699         reta = 0;
2700         for (i = 0; i < 128; i++) {
2701 #ifdef RSS
2702                 queue_id = rss_get_indirection_to_bucket(i);
2703                 /*
2704                  * If we have more queues than buckets, we'll
2705                  * end up mapping buckets to a subset of the
2706                  * queues.
2707                  *
2708                  * If we have more buckets than queues, we'll
2709                  * end up instead assigning multiple buckets
2710                  * to queues.
2711                  *
2712                  * Both are suboptimal, but we need to handle
2713                  * the case so we don't go out of bounds
2714                  * indexing arrays and such.
2715                  */
2716                 queue_id = queue_id % adapter->rx_num_queues;
2717 #else
2718                 queue_id = (i % adapter->rx_num_queues);
2719 #endif
2720                 /* Adjust if required */
2721                 queue_id = queue_id << shift;
2722
2723                 /*
2724                  * The low 8 bits are for hash value (n+0);
2725                  * The next 8 bits are for hash value (n+1), etc.
2726                  */
2727                 reta = reta >> 8;
2728                 reta = reta | ( ((uint32_t) queue_id) << 24);
2729                 if ((i & 3) == 3) {
2730                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2731                         reta = 0;
2732                 }
2733         }
2734
2735         /* Now fill in hash table */
2736
2737         /*
2738          * MRQC: Multiple Receive Queues Command
2739          * Set queuing to RSS control, number depends on the device.
2740          */
2741         mrqc = E1000_MRQC_ENABLE_RSS_8Q;
2742
2743 #ifdef RSS
2744         /* XXX ew typecasting */
2745         rss_getkey((uint8_t *) &rss_key);
2746 #else
2747         arc4rand(&rss_key, sizeof(rss_key), 0);
2748 #endif
2749         for (i = 0; i < 10; i++)
2750                 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]);
2751
2752         /*
2753          * Configure the RSS fields to hash upon.
2754          */
2755         mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2756             E1000_MRQC_RSS_FIELD_IPV4_TCP);
2757         mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2758             E1000_MRQC_RSS_FIELD_IPV6_TCP);
2759         mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2760             E1000_MRQC_RSS_FIELD_IPV6_UDP);
2761         mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2762             E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2763
2764         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2765 }
2766
2767 /*********************************************************************
2768  *
2769  *  Setup networking device structure and register interface media.
2770  *
2771  **********************************************************************/
2772 static int
2773 em_setup_interface(if_ctx_t ctx)
2774 {
2775         struct ifnet *ifp = iflib_get_ifp(ctx);
2776         struct adapter *adapter = iflib_get_softc(ctx);
2777         if_softc_ctx_t scctx = adapter->shared;
2778
2779         INIT_DEBUGOUT("em_setup_interface: begin");
2780
2781         /* Single Queue */
2782         if (adapter->tx_num_queues == 1) {
2783                 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
2784                 if_setsendqready(ifp);
2785         }
2786
2787         /*
2788          * Specify the media types supported by this adapter and register
2789          * callbacks to update media and link information
2790          */
2791         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
2792             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
2793                 u_char fiber_type = IFM_1000_SX;        /* default type */
2794
2795                 if (adapter->hw.mac.type == e1000_82545)
2796                         fiber_type = IFM_1000_LX;
2797                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
2798                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2799         } else {
2800                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2801                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2802                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2803                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2804                 if (adapter->hw.phy.type != e1000_phy_ife) {
2805                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2806                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2807                 }
2808         }
2809         ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2810         ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO);
2811         return (0);
2812 }
2813
2814 static int
2815 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
2816 {
2817         struct adapter *adapter = iflib_get_softc(ctx);
2818         if_softc_ctx_t scctx = adapter->shared;
2819         int error = E1000_SUCCESS;
2820         struct em_tx_queue *que;
2821         int i, j;
2822
2823         MPASS(adapter->tx_num_queues > 0);
2824         MPASS(adapter->tx_num_queues == ntxqsets);
2825
2826         /* First allocate the top level queue structs */
2827         if (!(adapter->tx_queues =
2828             (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
2829             adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2830                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2831                 return(ENOMEM);
2832         }
2833
2834         for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) {
2835                 /* Set up some basics */
2836
2837                 struct tx_ring *txr = &que->txr;
2838                 txr->adapter = que->adapter = adapter;
2839                 que->me = txr->me =  i;
2840
2841                 /* Allocate report status array */
2842                 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2843                         device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n");
2844                         error = ENOMEM;
2845                         goto fail;
2846                 }
2847                 for (j = 0; j < scctx->isc_ntxd[0]; j++)
2848                         txr->tx_rsq[j] = QIDX_INVALID;
2849                 /* get the virtual and physical address of the hardware queues */
2850                 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
2851                 txr->tx_paddr = paddrs[i*ntxqs];
2852         }
2853
2854         if (bootverbose)
2855                 device_printf(iflib_get_dev(ctx),
2856                     "allocated for %d tx_queues\n", adapter->tx_num_queues);
2857         return (0);
2858 fail:
2859         em_if_queues_free(ctx);
2860         return (error);
2861 }
2862
2863 static int
2864 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
2865 {
2866         struct adapter *adapter = iflib_get_softc(ctx);
2867         int error = E1000_SUCCESS;
2868         struct em_rx_queue *que;
2869         int i;
2870
2871         MPASS(adapter->rx_num_queues > 0);
2872         MPASS(adapter->rx_num_queues == nrxqsets);
2873
2874         /* First allocate the top level queue structs */
2875         if (!(adapter->rx_queues =
2876             (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
2877             adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2878                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2879                 error = ENOMEM;
2880                 goto fail;
2881         }
2882
2883         for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) {
2884                 /* Set up some basics */
2885                 struct rx_ring *rxr = &que->rxr;
2886                 rxr->adapter = que->adapter = adapter;
2887                 rxr->que = que;
2888                 que->me = rxr->me =  i;
2889
2890                 /* get the virtual and physical address of the hardware queues */
2891                 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
2892                 rxr->rx_paddr = paddrs[i*nrxqs];
2893         }
2894
2895         if (bootverbose)
2896                 device_printf(iflib_get_dev(ctx),
2897                     "allocated for %d rx_queues\n", adapter->rx_num_queues);
2898
2899         return (0);
2900 fail:
2901         em_if_queues_free(ctx);
2902         return (error);
2903 }
2904
2905 static void
2906 em_if_queues_free(if_ctx_t ctx)
2907 {
2908         struct adapter *adapter = iflib_get_softc(ctx);
2909         struct em_tx_queue *tx_que = adapter->tx_queues;
2910         struct em_rx_queue *rx_que = adapter->rx_queues;
2911
2912         if (tx_que != NULL) {
2913                 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
2914                         struct tx_ring *txr = &tx_que->txr;
2915                         if (txr->tx_rsq == NULL)
2916                                 break;
2917
2918                         free(txr->tx_rsq, M_DEVBUF);
2919                         txr->tx_rsq = NULL;
2920                 }
2921                 free(adapter->tx_queues, M_DEVBUF);
2922                 adapter->tx_queues = NULL;
2923         }
2924
2925         if (rx_que != NULL) {
2926                 free(adapter->rx_queues, M_DEVBUF);
2927                 adapter->rx_queues = NULL;
2928         }
2929
2930         em_release_hw_control(adapter);
2931
2932         if (adapter->mta != NULL) {
2933                 free(adapter->mta, M_DEVBUF);
2934         }
2935 }
2936
2937 /*********************************************************************
2938  *
2939  *  Enable transmit unit.
2940  *
2941  **********************************************************************/
2942 static void
2943 em_initialize_transmit_unit(if_ctx_t ctx)
2944 {
2945         struct adapter *adapter = iflib_get_softc(ctx);
2946         if_softc_ctx_t scctx = adapter->shared;
2947         struct em_tx_queue *que;
2948         struct tx_ring  *txr;
2949         struct e1000_hw *hw = &adapter->hw;
2950         u32 tctl, txdctl = 0, tarc, tipg = 0;
2951
2952         INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
2953
2954         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
2955                 u64 bus_addr;
2956                 caddr_t offp, endp;
2957
2958                 que = &adapter->tx_queues[i];
2959                 txr = &que->txr;
2960                 bus_addr = txr->tx_paddr;
2961
2962                 /* Clear checksum offload context. */
2963                 offp = (caddr_t)&txr->csum_flags;
2964                 endp = (caddr_t)(txr + 1);
2965                 bzero(offp, endp - offp);
2966
2967                 /* Base and Len of TX Ring */
2968                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
2969                     scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
2970                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
2971                     (u32)(bus_addr >> 32));
2972                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
2973                     (u32)bus_addr);
2974                 /* Init the HEAD/TAIL indices */
2975                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
2976                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
2977
2978                 HW_DEBUGOUT2("Base = %x, Length = %x\n",
2979                     E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)),
2980                     E1000_READ_REG(&adapter->hw, E1000_TDLEN(i)));
2981
2982                 txdctl = 0; /* clear txdctl */
2983                 txdctl |= 0x1f; /* PTHRESH */
2984                 txdctl |= 1 << 8; /* HTHRESH */
2985                 txdctl |= 1 << 16;/* WTHRESH */
2986                 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
2987                 txdctl |= E1000_TXDCTL_GRAN;
2988                 txdctl |= 1 << 25; /* LWTHRESH */
2989
2990                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
2991         }
2992
2993         /* Set the default values for the Tx Inter Packet Gap timer */
2994         switch (adapter->hw.mac.type) {
2995         case e1000_80003es2lan:
2996                 tipg = DEFAULT_82543_TIPG_IPGR1;
2997                 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2998                     E1000_TIPG_IPGR2_SHIFT;
2999                 break;
3000         case e1000_82542:
3001                 tipg = DEFAULT_82542_TIPG_IPGT;
3002                 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3003                 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3004                 break;
3005         default:
3006                 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
3007                     (adapter->hw.phy.media_type ==
3008                     e1000_media_type_internal_serdes))
3009                         tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
3010                 else
3011                         tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
3012                 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3013                 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3014         }
3015
3016         E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
3017         E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value);
3018
3019         if(adapter->hw.mac.type >= e1000_82540)
3020                 E1000_WRITE_REG(&adapter->hw, E1000_TADV,
3021                     adapter->tx_abs_int_delay.value);
3022
3023         if ((adapter->hw.mac.type == e1000_82571) ||
3024             (adapter->hw.mac.type == e1000_82572)) {
3025                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3026                 tarc |= TARC_SPEED_MODE_BIT;
3027                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3028         } else if (adapter->hw.mac.type == e1000_80003es2lan) {
3029                 /* errata: program both queues to unweighted RR */
3030                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3031                 tarc |= 1;
3032                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3033                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
3034                 tarc |= 1;
3035                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
3036         } else if (adapter->hw.mac.type == e1000_82574) {
3037                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3038                 tarc |= TARC_ERRATA_BIT;
3039                 if ( adapter->tx_num_queues > 1) {
3040                         tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
3041                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3042                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
3043                 } else
3044                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3045         }
3046
3047         if (adapter->tx_int_delay.value > 0)
3048                 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3049
3050         /* Program the Transmit Control Register */
3051         tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
3052         tctl &= ~E1000_TCTL_CT;
3053         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
3054                    (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
3055
3056         if (adapter->hw.mac.type >= e1000_82571)
3057                 tctl |= E1000_TCTL_MULR;
3058
3059         /* This write will effectively turn on the transmit unit. */
3060         E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
3061
3062         /* SPT and KBL errata workarounds */
3063         if (hw->mac.type == e1000_pch_spt) {
3064                 u32 reg;
3065                 reg = E1000_READ_REG(hw, E1000_IOSFPC);
3066                 reg |= E1000_RCTL_RDMTS_HEX;
3067                 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
3068                 /* i218-i219 Specification Update 1.5.4.5 */
3069                 reg = E1000_READ_REG(hw, E1000_TARC(0));
3070                 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3071                 reg |= E1000_TARC0_CB_MULTIQ_2_REQ;
3072                 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3073         }
3074 }
3075
3076 /*********************************************************************
3077  *
3078  *  Enable receive unit.
3079  *
3080  **********************************************************************/
3081
3082 static void
3083 em_initialize_receive_unit(if_ctx_t ctx)
3084 {
3085         struct adapter *adapter = iflib_get_softc(ctx);
3086         if_softc_ctx_t scctx = adapter->shared;
3087         struct ifnet *ifp = iflib_get_ifp(ctx);
3088         struct e1000_hw *hw = &adapter->hw;
3089         struct em_rx_queue *que;
3090         int i;
3091         u32 rctl, rxcsum, rfctl;
3092
3093         INIT_DEBUGOUT("em_initialize_receive_units: begin");
3094
3095         /*
3096          * Make sure receives are disabled while setting
3097          * up the descriptor ring
3098          */
3099         rctl = E1000_READ_REG(hw, E1000_RCTL);
3100         /* Do not disable if ever enabled on this hardware */
3101         if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
3102                 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3103
3104         /* Setup the Receive Control Register */
3105         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3106         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3107             E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3108             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3109
3110         /* Do not store bad packets */
3111         rctl &= ~E1000_RCTL_SBP;
3112
3113         /* Enable Long Packet receive */
3114         if (if_getmtu(ifp) > ETHERMTU)
3115                 rctl |= E1000_RCTL_LPE;
3116         else
3117                 rctl &= ~E1000_RCTL_LPE;
3118
3119         /* Strip the CRC */
3120         if (!em_disable_crc_stripping)
3121                 rctl |= E1000_RCTL_SECRC;
3122
3123         if (adapter->hw.mac.type >= e1000_82540) {
3124                 E1000_WRITE_REG(&adapter->hw, E1000_RADV,
3125                             adapter->rx_abs_int_delay.value);
3126
3127                 /*
3128                  * Set the interrupt throttling rate. Value is calculated
3129                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
3130                  */
3131                 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
3132         }
3133         E1000_WRITE_REG(&adapter->hw, E1000_RDTR,
3134             adapter->rx_int_delay.value);
3135
3136         /* Use extended rx descriptor formats */
3137         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3138         rfctl |= E1000_RFCTL_EXTEN;
3139         /*
3140          * When using MSI-X interrupts we need to throttle
3141          * using the EITR register (82574 only)
3142          */
3143         if (hw->mac.type == e1000_82574) {
3144                 for (int i = 0; i < 4; i++)
3145                         E1000_WRITE_REG(hw, E1000_EITR_82574(i),
3146                             DEFAULT_ITR);
3147                 /* Disable accelerated acknowledge */
3148                 rfctl |= E1000_RFCTL_ACK_DIS;
3149         }
3150         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3151
3152         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
3153         if (if_getcapenable(ifp) & IFCAP_RXCSUM &&
3154             adapter->hw.mac.type >= e1000_82543) {
3155                 if (adapter->tx_num_queues > 1) {
3156                         if (adapter->hw.mac.type >= igb_mac_min) {
3157                                 rxcsum |= E1000_RXCSUM_PCSD;
3158                                 if (hw->mac.type != e1000_82575)
3159                                         rxcsum |= E1000_RXCSUM_CRCOFL;
3160                         } else
3161                                 rxcsum |= E1000_RXCSUM_TUOFL |
3162                                         E1000_RXCSUM_IPOFL |
3163                                         E1000_RXCSUM_PCSD;
3164                 } else {
3165                         if (adapter->hw.mac.type >= igb_mac_min)
3166                                 rxcsum |= E1000_RXCSUM_IPPCSE;
3167                         else
3168                                 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
3169                         if (adapter->hw.mac.type > e1000_82575)
3170                                 rxcsum |= E1000_RXCSUM_CRCOFL;
3171                 }
3172         } else
3173                 rxcsum &= ~E1000_RXCSUM_TUOFL;
3174
3175         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
3176
3177         if (adapter->rx_num_queues > 1) {
3178                 if (adapter->hw.mac.type >= igb_mac_min)
3179                         igb_initialize_rss_mapping(adapter);
3180                 else
3181                         em_initialize_rss_mapping(adapter);
3182         }
3183
3184         /*
3185          * XXX TEMPORARY WORKAROUND: on some systems with 82573
3186          * long latencies are observed, like Lenovo X60. This
3187          * change eliminates the problem, but since having positive
3188          * values in RDTR is a known source of problems on other
3189          * platforms another solution is being sought.
3190          */
3191         if (hw->mac.type == e1000_82573)
3192                 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
3193
3194         for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3195                 struct rx_ring *rxr = &que->rxr;
3196                 /* Setup the Base and Length of the Rx Descriptor Ring */
3197                 u64 bus_addr = rxr->rx_paddr;
3198 #if 0
3199                 u32 rdt = adapter->rx_num_queues -1;  /* default */
3200 #endif
3201
3202                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3203                     scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
3204                 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
3205                 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
3206                 /* Setup the Head and Tail Descriptor Pointers */
3207                 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
3208                 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
3209         }
3210
3211         /*
3212          * Set PTHRESH for improved jumbo performance
3213          * According to 10.2.5.11 of Intel 82574 Datasheet,
3214          * RXDCTL(1) is written whenever RXDCTL(0) is written.
3215          * Only write to RXDCTL(1) if there is a need for different
3216          * settings.
3217          */
3218
3219         if (((adapter->hw.mac.type == e1000_ich9lan) ||
3220             (adapter->hw.mac.type == e1000_pch2lan) ||
3221             (adapter->hw.mac.type == e1000_ich10lan)) &&
3222             (if_getmtu(ifp) > ETHERMTU)) {
3223                 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
3224                 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
3225         } else if (adapter->hw.mac.type == e1000_82574) {
3226                 for (int i = 0; i < adapter->rx_num_queues; i++) {
3227                         u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3228                         rxdctl |= 0x20; /* PTHRESH */
3229                         rxdctl |= 4 << 8; /* HTHRESH */
3230                         rxdctl |= 4 << 16;/* WTHRESH */
3231                         rxdctl |= 1 << 24; /* Switch to granularity */
3232                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3233                 }
3234         } else if (adapter->hw.mac.type >= igb_mac_min) {
3235                 u32 psize, srrctl = 0;
3236
3237                 if (if_getmtu(ifp) > ETHERMTU) {
3238                         /* Set maximum packet len */
3239                         if (adapter->rx_mbuf_sz <= 4096) {
3240                                 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3241                                 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3242                         } else if (adapter->rx_mbuf_sz > 4096) {
3243                                 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3244                                 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3245                         }
3246                         psize = scctx->isc_max_frame_size;
3247                         /* are we on a vlan? */
3248                         if (ifp->if_vlantrunk != NULL)
3249                                 psize += VLAN_TAG_SIZE;
3250                         E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
3251                 } else {
3252                         srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3253                         rctl |= E1000_RCTL_SZ_2048;
3254                 }
3255
3256                 /*
3257                  * If TX flow control is disabled and there's >1 queue defined,
3258                  * enable DROP.
3259                  *
3260                  * This drops frames rather than hanging the RX MAC for all queues.
3261                  */
3262                 if ((adapter->rx_num_queues > 1) &&
3263                     (adapter->fc == e1000_fc_none ||
3264                      adapter->fc == e1000_fc_rx_pause)) {
3265                         srrctl |= E1000_SRRCTL_DROP_EN;
3266                 }
3267                         /* Setup the Base and Length of the Rx Descriptor Rings */
3268                 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3269                         struct rx_ring *rxr = &que->rxr;
3270                         u64 bus_addr = rxr->rx_paddr;
3271                         u32 rxdctl;
3272
3273 #ifdef notyet
3274                         /* Configure for header split? -- ignore for now */
3275                         rxr->hdr_split = igb_header_split;
3276 #else
3277                         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3278 #endif
3279
3280                         E1000_WRITE_REG(hw, E1000_RDLEN(i),
3281                                         scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3282                         E1000_WRITE_REG(hw, E1000_RDBAH(i),
3283                                         (uint32_t)(bus_addr >> 32));
3284                         E1000_WRITE_REG(hw, E1000_RDBAL(i),
3285                                         (uint32_t)bus_addr);
3286                         E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3287                         /* Enable this Queue */
3288                         rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3289                         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3290                         rxdctl &= 0xFFF00000;
3291                         rxdctl |= IGB_RX_PTHRESH;
3292                         rxdctl |= IGB_RX_HTHRESH << 8;
3293                         rxdctl |= IGB_RX_WTHRESH << 16;
3294                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3295                 }
3296         } else if (adapter->hw.mac.type >= e1000_pch2lan) {
3297                 if (if_getmtu(ifp) > ETHERMTU)
3298                         e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
3299                 else
3300                         e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
3301         }
3302
3303         /* Make sure VLAN Filters are off */
3304         rctl &= ~E1000_RCTL_VFE;
3305
3306         if (adapter->hw.mac.type < igb_mac_min) {
3307                 if (adapter->rx_mbuf_sz == MCLBYTES)
3308                         rctl |= E1000_RCTL_SZ_2048;
3309                 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE)
3310                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3311                 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE)
3312                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3313
3314                 /* ensure we clear use DTYPE of 00 here */
3315                 rctl &= ~0x00000C00;
3316         }
3317
3318         /* Write out the settings */
3319         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3320
3321         return;
3322 }
3323
3324 static void
3325 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3326 {
3327         struct adapter *adapter = iflib_get_softc(ctx);
3328         u32 index, bit;
3329
3330         index = (vtag >> 5) & 0x7F;
3331         bit = vtag & 0x1F;
3332         adapter->shadow_vfta[index] |= (1 << bit);
3333         ++adapter->num_vlans;
3334 }
3335
3336 static void
3337 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3338 {
3339         struct adapter *adapter = iflib_get_softc(ctx);
3340         u32 index, bit;
3341
3342         index = (vtag >> 5) & 0x7F;
3343         bit = vtag & 0x1F;
3344         adapter->shadow_vfta[index] &= ~(1 << bit);
3345         --adapter->num_vlans;
3346 }
3347
3348 static void
3349 em_setup_vlan_hw_support(struct adapter *adapter)
3350 {
3351         struct e1000_hw *hw = &adapter->hw;
3352         u32 reg;
3353
3354         /*
3355          * We get here thru init_locked, meaning
3356          * a soft reset, this has already cleared
3357          * the VFTA and other state, so if there
3358          * have been no vlan's registered do nothing.
3359          */
3360         if (adapter->num_vlans == 0)
3361                 return;
3362
3363         /*
3364          * A soft reset zero's out the VFTA, so
3365          * we need to repopulate it now.
3366          */
3367         for (int i = 0; i < EM_VFTA_SIZE; i++)
3368                 if (adapter->shadow_vfta[i] != 0)
3369                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
3370                             i, adapter->shadow_vfta[i]);
3371
3372         reg = E1000_READ_REG(hw, E1000_CTRL);
3373         reg |= E1000_CTRL_VME;
3374         E1000_WRITE_REG(hw, E1000_CTRL, reg);
3375
3376         /* Enable the Filter Table */
3377         reg = E1000_READ_REG(hw, E1000_RCTL);
3378         reg &= ~E1000_RCTL_CFIEN;
3379         reg |= E1000_RCTL_VFE;
3380         E1000_WRITE_REG(hw, E1000_RCTL, reg);
3381 }
3382
3383 static void
3384 em_if_enable_intr(if_ctx_t ctx)
3385 {
3386         struct adapter *adapter = iflib_get_softc(ctx);
3387         struct e1000_hw *hw = &adapter->hw;
3388         u32 ims_mask = IMS_ENABLE_MASK;
3389
3390         if (hw->mac.type == e1000_82574) {
3391                 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK);
3392                 ims_mask |= adapter->ims;
3393         } else if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min)  {
3394                 u32 mask = (adapter->que_mask | adapter->link_mask);
3395
3396                 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask);
3397                 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask);
3398                 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask);
3399                 ims_mask = E1000_IMS_LSC;
3400         }
3401
3402         E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3403 }
3404
3405 static void
3406 em_if_disable_intr(if_ctx_t ctx)
3407 {
3408         struct adapter *adapter = iflib_get_softc(ctx);
3409         struct e1000_hw *hw = &adapter->hw;
3410
3411         if (adapter->intr_type == IFLIB_INTR_MSIX) {
3412                 if (hw->mac.type >= igb_mac_min)
3413                         E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0);
3414                 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0);
3415         }
3416         E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
3417 }
3418
3419 /*
3420  * Bit of a misnomer, what this really means is
3421  * to enable OS management of the system... aka
3422  * to disable special hardware management features
3423  */
3424 static void
3425 em_init_manageability(struct adapter *adapter)
3426 {
3427         /* A shared code workaround */
3428 #define E1000_82542_MANC2H E1000_MANC2H
3429         if (adapter->has_manage) {
3430                 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3431                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3432
3433                 /* disable hardware interception of ARP */
3434                 manc &= ~(E1000_MANC_ARP_EN);
3435
3436                 /* enable receiving management packets to the host */
3437                 manc |= E1000_MANC_EN_MNG2HOST;
3438 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3439 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3440                 manc2h |= E1000_MNG2HOST_PORT_623;
3441                 manc2h |= E1000_MNG2HOST_PORT_664;
3442                 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3443                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3444         }
3445 }
3446
3447 /*
3448  * Give control back to hardware management
3449  * controller if there is one.
3450  */
3451 static void
3452 em_release_manageability(struct adapter *adapter)
3453 {
3454         if (adapter->has_manage) {
3455                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3456
3457                 /* re-enable hardware interception of ARP */
3458                 manc |= E1000_MANC_ARP_EN;
3459                 manc &= ~E1000_MANC_EN_MNG2HOST;
3460
3461                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3462         }
3463 }
3464
3465 /*
3466  * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3467  * For ASF and Pass Through versions of f/w this means
3468  * that the driver is loaded. For AMT version type f/w
3469  * this means that the network i/f is open.
3470  */
3471 static void
3472 em_get_hw_control(struct adapter *adapter)
3473 {
3474         u32 ctrl_ext, swsm;
3475
3476         if (adapter->vf_ifp)
3477                 return;
3478
3479         if (adapter->hw.mac.type == e1000_82573) {
3480                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3481                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3482                     swsm | E1000_SWSM_DRV_LOAD);
3483                 return;
3484         }
3485         /* else */
3486         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3487         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3488             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3489 }
3490
3491 /*
3492  * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3493  * For ASF and Pass Through versions of f/w this means that
3494  * the driver is no longer loaded. For AMT versions of the
3495  * f/w this means that the network i/f is closed.
3496  */
3497 static void
3498 em_release_hw_control(struct adapter *adapter)
3499 {
3500         u32 ctrl_ext, swsm;
3501
3502         if (!adapter->has_manage)
3503                 return;
3504
3505         if (adapter->hw.mac.type == e1000_82573) {
3506                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3507                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3508                     swsm & ~E1000_SWSM_DRV_LOAD);
3509                 return;
3510         }
3511         /* else */
3512         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3513         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3514             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3515         return;
3516 }
3517
3518 static int
3519 em_is_valid_ether_addr(u8 *addr)
3520 {
3521         char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3522
3523         if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3524                 return (FALSE);
3525         }
3526
3527         return (TRUE);
3528 }
3529
3530 /*
3531 ** Parse the interface capabilities with regard
3532 ** to both system management and wake-on-lan for
3533 ** later use.
3534 */
3535 static void
3536 em_get_wakeup(if_ctx_t ctx)
3537 {
3538         struct adapter *adapter = iflib_get_softc(ctx);
3539         device_t dev = iflib_get_dev(ctx);
3540         u16 eeprom_data = 0, device_id, apme_mask;
3541
3542         adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
3543         apme_mask = EM_EEPROM_APME;
3544
3545         switch (adapter->hw.mac.type) {
3546         case e1000_82542:
3547         case e1000_82543:
3548                 break;
3549         case e1000_82544:
3550                 e1000_read_nvm(&adapter->hw,
3551                     NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3552                 apme_mask = EM_82544_APME;
3553                 break;
3554         case e1000_82546:
3555         case e1000_82546_rev_3:
3556                 if (adapter->hw.bus.func == 1) {
3557                         e1000_read_nvm(&adapter->hw,
3558                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3559                         break;
3560                 } else
3561                         e1000_read_nvm(&adapter->hw,
3562                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3563                 break;
3564         case e1000_82573:
3565         case e1000_82583:
3566                 adapter->has_amt = TRUE;
3567                 /* FALLTHROUGH */
3568         case e1000_82571:
3569         case e1000_82572:
3570         case e1000_80003es2lan:
3571                 if (adapter->hw.bus.func == 1) {
3572                         e1000_read_nvm(&adapter->hw,
3573                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3574                         break;
3575                 } else
3576                         e1000_read_nvm(&adapter->hw,
3577                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3578                 break;
3579         case e1000_ich8lan:
3580         case e1000_ich9lan:
3581         case e1000_ich10lan:
3582         case e1000_pchlan:
3583         case e1000_pch2lan:
3584         case e1000_pch_lpt:
3585         case e1000_pch_spt:
3586         case e1000_82575:       /* listing all igb devices */
3587         case e1000_82576:
3588         case e1000_82580:
3589         case e1000_i350:
3590         case e1000_i354:
3591         case e1000_i210:
3592         case e1000_i211:
3593         case e1000_vfadapt:
3594         case e1000_vfadapt_i350:
3595                 apme_mask = E1000_WUC_APME;
3596                 adapter->has_amt = TRUE;
3597                 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
3598                 break;
3599         default:
3600                 e1000_read_nvm(&adapter->hw,
3601                     NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3602                 break;
3603         }
3604         if (eeprom_data & apme_mask)
3605                 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
3606         /*
3607          * We have the eeprom settings, now apply the special cases
3608          * where the eeprom may be wrong or the board won't support
3609          * wake on lan on a particular port
3610          */
3611         device_id = pci_get_device(dev);
3612         switch (device_id) {
3613         case E1000_DEV_ID_82546GB_PCIE:
3614                 adapter->wol = 0;
3615                 break;
3616         case E1000_DEV_ID_82546EB_FIBER:
3617         case E1000_DEV_ID_82546GB_FIBER:
3618                 /* Wake events only supported on port A for dual fiber
3619                  * regardless of eeprom setting */
3620                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3621                     E1000_STATUS_FUNC_1)
3622                         adapter->wol = 0;
3623                 break;
3624         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
3625                 /* if quad port adapter, disable WoL on all but port A */
3626                 if (global_quad_port_a != 0)
3627                         adapter->wol = 0;
3628                 /* Reset for multiple quad port adapters */
3629                 if (++global_quad_port_a == 4)
3630                         global_quad_port_a = 0;
3631                 break;
3632         case E1000_DEV_ID_82571EB_FIBER:
3633                 /* Wake events only supported on port A for dual fiber
3634                  * regardless of eeprom setting */
3635                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3636                     E1000_STATUS_FUNC_1)
3637                         adapter->wol = 0;
3638                 break;
3639         case E1000_DEV_ID_82571EB_QUAD_COPPER:
3640         case E1000_DEV_ID_82571EB_QUAD_FIBER:
3641         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
3642                 /* if quad port adapter, disable WoL on all but port A */
3643                 if (global_quad_port_a != 0)
3644                         adapter->wol = 0;
3645                 /* Reset for multiple quad port adapters */
3646                 if (++global_quad_port_a == 4)
3647                         global_quad_port_a = 0;
3648                 break;
3649         }
3650         return;
3651 }
3652
3653
3654 /*
3655  * Enable PCI Wake On Lan capability
3656  */
3657 static void
3658 em_enable_wakeup(if_ctx_t ctx)
3659 {
3660         struct adapter *adapter = iflib_get_softc(ctx);
3661         device_t dev = iflib_get_dev(ctx);
3662         if_t ifp = iflib_get_ifp(ctx);
3663         int error = 0;
3664         u32 pmc, ctrl, ctrl_ext, rctl;
3665         u16 status;
3666
3667         if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
3668                 return;
3669
3670         /*
3671          * Determine type of Wakeup: note that wol
3672          * is set with all bits on by default.
3673          */
3674         if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
3675                 adapter->wol &= ~E1000_WUFC_MAG;
3676
3677         if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
3678                 adapter->wol &= ~E1000_WUFC_EX;
3679
3680         if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
3681                 adapter->wol &= ~E1000_WUFC_MC;
3682         else {
3683                 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3684                 rctl |= E1000_RCTL_MPE;
3685                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3686         }
3687
3688         if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC)))
3689                 goto pme;
3690
3691         /* Advertise the wakeup capability */
3692         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
3693         ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
3694         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
3695
3696         /* Keep the laser running on Fiber adapters */
3697         if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3698             adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
3699                 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3700                 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
3701                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext);
3702         }
3703
3704         if ((adapter->hw.mac.type == e1000_ich8lan) ||
3705             (adapter->hw.mac.type == e1000_pchlan) ||
3706             (adapter->hw.mac.type == e1000_ich9lan) ||
3707             (adapter->hw.mac.type == e1000_ich10lan))
3708                 e1000_suspend_workarounds_ich8lan(&adapter->hw);
3709
3710         if ( adapter->hw.mac.type >= e1000_pchlan) {
3711                 error = em_enable_phy_wakeup(adapter);
3712                 if (error)
3713                         goto pme;
3714         } else {
3715                 /* Enable wakeup by the MAC */
3716                 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
3717                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
3718         }
3719
3720         if (adapter->hw.phy.type == e1000_phy_igp_3)
3721                 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
3722
3723 pme:
3724         status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
3725         status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3726         if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
3727                 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3728         pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
3729
3730         return;
3731 }
3732
3733 /*
3734  * WOL in the newer chipset interfaces (pchlan)
3735  * require thing to be copied into the phy
3736  */
3737 static int
3738 em_enable_phy_wakeup(struct adapter *adapter)
3739 {
3740         struct e1000_hw *hw = &adapter->hw;
3741         u32 mreg, ret = 0;
3742         u16 preg;
3743
3744         /* copy MAC RARs to PHY RARs */
3745         e1000_copy_rx_addrs_to_phy_ich8lan(hw);
3746
3747         /* copy MAC MTA to PHY MTA */
3748         for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
3749                 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
3750                 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
3751                 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
3752                     (u16)((mreg >> 16) & 0xFFFF));
3753         }
3754
3755         /* configure PHY Rx Control register */
3756         e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg);
3757         mreg = E1000_READ_REG(hw, E1000_RCTL);
3758         if (mreg & E1000_RCTL_UPE)
3759                 preg |= BM_RCTL_UPE;
3760         if (mreg & E1000_RCTL_MPE)
3761                 preg |= BM_RCTL_MPE;
3762         preg &= ~(BM_RCTL_MO_MASK);
3763         if (mreg & E1000_RCTL_MO_3)
3764                 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
3765                                 << BM_RCTL_MO_SHIFT);
3766         if (mreg & E1000_RCTL_BAM)
3767                 preg |= BM_RCTL_BAM;
3768         if (mreg & E1000_RCTL_PMCF)
3769                 preg |= BM_RCTL_PMCF;
3770         mreg = E1000_READ_REG(hw, E1000_CTRL);
3771         if (mreg & E1000_CTRL_RFCE)
3772                 preg |= BM_RCTL_RFCE;
3773         e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg);
3774
3775         /* enable PHY wakeup in MAC register */
3776         E1000_WRITE_REG(hw, E1000_WUC,
3777             E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
3778         E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol);
3779
3780         /* configure and enable PHY wakeup in PHY registers */
3781         e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol);
3782         e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
3783
3784         /* activate PHY wakeup */
3785         ret = hw->phy.ops.acquire(hw);
3786         if (ret) {
3787                 printf("Could not acquire PHY\n");
3788                 return ret;
3789         }
3790         e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3791                                  (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3792         ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
3793         if (ret) {
3794                 printf("Could not read PHY page 769\n");
3795                 goto out;
3796         }
3797         preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
3798         ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
3799         if (ret)
3800                 printf("Could not set PHY Host Wakeup bit\n");
3801 out:
3802         hw->phy.ops.release(hw);
3803
3804         return ret;
3805 }
3806
3807 static void
3808 em_if_led_func(if_ctx_t ctx, int onoff)
3809 {
3810         struct adapter *adapter = iflib_get_softc(ctx);
3811
3812         if (onoff) {
3813                 e1000_setup_led(&adapter->hw);
3814                 e1000_led_on(&adapter->hw);
3815         } else {
3816                 e1000_led_off(&adapter->hw);
3817                 e1000_cleanup_led(&adapter->hw);
3818         }
3819 }
3820
3821 /*
3822  * Disable the L0S and L1 LINK states
3823  */
3824 static void
3825 em_disable_aspm(struct adapter *adapter)
3826 {
3827         int base, reg;
3828         u16 link_cap,link_ctrl;
3829         device_t dev = adapter->dev;
3830
3831         switch (adapter->hw.mac.type) {
3832         case e1000_82573:
3833         case e1000_82574:
3834         case e1000_82583:
3835                 break;
3836         default:
3837                 return;
3838         }
3839         if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
3840                 return;
3841         reg = base + PCIER_LINK_CAP;
3842         link_cap = pci_read_config(dev, reg, 2);
3843         if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
3844                 return;
3845         reg = base + PCIER_LINK_CTL;
3846         link_ctrl = pci_read_config(dev, reg, 2);
3847         link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
3848         pci_write_config(dev, reg, link_ctrl, 2);
3849         return;
3850 }
3851
3852 /**********************************************************************
3853  *
3854  *  Update the board statistics counters.
3855  *
3856  **********************************************************************/
3857 static void
3858 em_update_stats_counters(struct adapter *adapter)
3859 {
3860
3861         if(adapter->hw.phy.media_type == e1000_media_type_copper ||
3862            (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3863                 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
3864                 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
3865         }
3866         adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
3867         adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
3868         adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
3869         adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
3870
3871         adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
3872         adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
3873         adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
3874         adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
3875         adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
3876         adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
3877         adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
3878         adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
3879         /*
3880          ** For watchdog management we need to know if we have been
3881          ** paused during the last interval, so capture that here.
3882         */
3883         adapter->shared->isc_pause_frames = adapter->stats.xoffrxc;
3884         adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
3885         adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
3886         adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
3887         adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
3888         adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
3889         adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
3890         adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
3891         adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
3892         adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
3893         adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
3894         adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
3895         adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
3896
3897         /* For the 64-bit byte counters the low dword must be read first. */
3898         /* Both registers clear on the read of the high dword */
3899
3900         adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) +
3901             ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32);
3902         adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) +
3903             ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32);
3904
3905         adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
3906         adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
3907         adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
3908         adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
3909         adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
3910
3911         adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
3912         adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
3913
3914         adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
3915         adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
3916         adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
3917         adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
3918         adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
3919         adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
3920         adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
3921         adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
3922         adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
3923         adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
3924
3925         /* Interrupt Counts */
3926
3927         adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC);
3928         adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC);
3929         adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC);
3930         adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC);
3931         adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC);
3932         adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC);
3933         adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC);
3934         adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC);
3935         adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC);
3936
3937         if (adapter->hw.mac.type >= e1000_82543) {
3938                 adapter->stats.algnerrc +=
3939                 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
3940                 adapter->stats.rxerrc +=
3941                 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
3942                 adapter->stats.tncrs +=
3943                 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
3944                 adapter->stats.cexterr +=
3945                 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
3946                 adapter->stats.tsctc +=
3947                 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
3948                 adapter->stats.tsctfc +=
3949                 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
3950         }
3951 }
3952
3953 static uint64_t
3954 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
3955 {
3956         struct adapter *adapter = iflib_get_softc(ctx);
3957         struct ifnet *ifp = iflib_get_ifp(ctx);
3958
3959         switch (cnt) {
3960         case IFCOUNTER_COLLISIONS:
3961                 return (adapter->stats.colc);
3962         case IFCOUNTER_IERRORS:
3963                 return (adapter->dropped_pkts + adapter->stats.rxerrc +
3964                     adapter->stats.crcerrs + adapter->stats.algnerrc +
3965                     adapter->stats.ruc + adapter->stats.roc +
3966                     adapter->stats.mpc + adapter->stats.cexterr);
3967         case IFCOUNTER_OERRORS:
3968                 return (adapter->stats.ecol + adapter->stats.latecol +
3969                     adapter->watchdog_events);
3970         default:
3971                 return (if_get_counter_default(ifp, cnt));
3972         }
3973 }
3974
3975 /* Export a single 32-bit register via a read-only sysctl. */
3976 static int
3977 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
3978 {
3979         struct adapter *adapter;
3980         u_int val;
3981
3982         adapter = oidp->oid_arg1;
3983         val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2);
3984         return (sysctl_handle_int(oidp, &val, 0, req));
3985 }
3986
3987 /*
3988  * Add sysctl variables, one per statistic, to the system.
3989  */
3990 static void
3991 em_add_hw_stats(struct adapter *adapter)
3992 {
3993         device_t dev = iflib_get_dev(adapter->ctx);
3994         struct em_tx_queue *tx_que = adapter->tx_queues;
3995         struct em_rx_queue *rx_que = adapter->rx_queues;
3996
3997         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
3998         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
3999         struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
4000         struct e1000_hw_stats *stats = &adapter->stats;
4001
4002         struct sysctl_oid *stat_node, *queue_node, *int_node;
4003         struct sysctl_oid_list *stat_list, *queue_list, *int_list;
4004
4005 #define QUEUE_NAME_LEN 32
4006         char namebuf[QUEUE_NAME_LEN];
4007
4008         /* Driver Statistics */
4009         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
4010                         CTLFLAG_RD, &adapter->dropped_pkts,
4011                         "Driver dropped packets");
4012         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
4013                         CTLFLAG_RD, &adapter->link_irq,
4014                         "Link MSI-X IRQ Handled");
4015         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
4016                         CTLFLAG_RD, &adapter->rx_overruns,
4017                         "RX overruns");
4018         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
4019                         CTLFLAG_RD, &adapter->watchdog_events,
4020                         "Watchdog timeouts");
4021         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
4022                         CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL,
4023                         em_sysctl_reg_handler, "IU",
4024                         "Device Control Register");
4025         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
4026                         CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL,
4027                         em_sysctl_reg_handler, "IU",
4028                         "Receiver Control Register");
4029         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
4030                         CTLFLAG_RD, &adapter->hw.fc.high_water, 0,
4031                         "Flow Control High Watermark");
4032         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
4033                         CTLFLAG_RD, &adapter->hw.fc.low_water, 0,
4034                         "Flow Control Low Watermark");
4035
4036         for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
4037                 struct tx_ring *txr = &tx_que->txr;
4038                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
4039                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4040                                             CTLFLAG_RD, NULL, "TX Queue Name");
4041                 queue_list = SYSCTL_CHILDREN(queue_node);
4042
4043                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
4044                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4045                                 E1000_TDH(txr->me),
4046                                 em_sysctl_reg_handler, "IU",
4047                                 "Transmit Descriptor Head");
4048                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
4049                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4050                                 E1000_TDT(txr->me),
4051                                 em_sysctl_reg_handler, "IU",
4052                                 "Transmit Descriptor Tail");
4053                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
4054                                 CTLFLAG_RD, &txr->tx_irq,
4055                                 "Queue MSI-X Transmit Interrupts");
4056         }
4057
4058         for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) {
4059                 struct rx_ring *rxr = &rx_que->rxr;
4060                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
4061                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4062                                             CTLFLAG_RD, NULL, "RX Queue Name");
4063                 queue_list = SYSCTL_CHILDREN(queue_node);
4064
4065                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
4066                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4067                                 E1000_RDH(rxr->me),
4068                                 em_sysctl_reg_handler, "IU",
4069                                 "Receive Descriptor Head");
4070                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
4071                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4072                                 E1000_RDT(rxr->me),
4073                                 em_sysctl_reg_handler, "IU",
4074                                 "Receive Descriptor Tail");
4075                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
4076                                 CTLFLAG_RD, &rxr->rx_irq,
4077                                 "Queue MSI-X Receive Interrupts");
4078         }
4079
4080         /* MAC stats get their own sub node */
4081
4082         stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
4083                                     CTLFLAG_RD, NULL, "Statistics");
4084         stat_list = SYSCTL_CHILDREN(stat_node);
4085
4086         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
4087                         CTLFLAG_RD, &stats->ecol,
4088                         "Excessive collisions");
4089         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
4090                         CTLFLAG_RD, &stats->scc,
4091                         "Single collisions");
4092         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
4093                         CTLFLAG_RD, &stats->mcc,
4094                         "Multiple collisions");
4095         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
4096                         CTLFLAG_RD, &stats->latecol,
4097                         "Late collisions");
4098         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
4099                         CTLFLAG_RD, &stats->colc,
4100                         "Collision Count");
4101         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
4102                         CTLFLAG_RD, &adapter->stats.symerrs,
4103                         "Symbol Errors");
4104         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
4105                         CTLFLAG_RD, &adapter->stats.sec,
4106                         "Sequence Errors");
4107         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
4108                         CTLFLAG_RD, &adapter->stats.dc,
4109                         "Defer Count");
4110         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
4111                         CTLFLAG_RD, &adapter->stats.mpc,
4112                         "Missed Packets");
4113         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
4114                         CTLFLAG_RD, &adapter->stats.rnbc,
4115                         "Receive No Buffers");
4116         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
4117                         CTLFLAG_RD, &adapter->stats.ruc,
4118                         "Receive Undersize");
4119         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
4120                         CTLFLAG_RD, &adapter->stats.rfc,
4121                         "Fragmented Packets Received ");
4122         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
4123                         CTLFLAG_RD, &adapter->stats.roc,
4124                         "Oversized Packets Received");
4125         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
4126                         CTLFLAG_RD, &adapter->stats.rjc,
4127                         "Recevied Jabber");
4128         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
4129                         CTLFLAG_RD, &adapter->stats.rxerrc,
4130                         "Receive Errors");
4131         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
4132                         CTLFLAG_RD, &adapter->stats.crcerrs,
4133                         "CRC errors");
4134         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
4135                         CTLFLAG_RD, &adapter->stats.algnerrc,
4136                         "Alignment Errors");
4137         /* On 82575 these are collision counts */
4138         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
4139                         CTLFLAG_RD, &adapter->stats.cexterr,
4140                         "Collision/Carrier extension errors");
4141         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
4142                         CTLFLAG_RD, &adapter->stats.xonrxc,
4143                         "XON Received");
4144         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
4145                         CTLFLAG_RD, &adapter->stats.xontxc,
4146                         "XON Transmitted");
4147         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
4148                         CTLFLAG_RD, &adapter->stats.xoffrxc,
4149                         "XOFF Received");
4150         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
4151                         CTLFLAG_RD, &adapter->stats.xofftxc,
4152                         "XOFF Transmitted");
4153
4154         /* Packet Reception Stats */
4155         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
4156                         CTLFLAG_RD, &adapter->stats.tpr,
4157                         "Total Packets Received ");
4158         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
4159                         CTLFLAG_RD, &adapter->stats.gprc,
4160                         "Good Packets Received");
4161         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
4162                         CTLFLAG_RD, &adapter->stats.bprc,
4163                         "Broadcast Packets Received");
4164         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
4165                         CTLFLAG_RD, &adapter->stats.mprc,
4166                         "Multicast Packets Received");
4167         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
4168                         CTLFLAG_RD, &adapter->stats.prc64,
4169                         "64 byte frames received ");
4170         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
4171                         CTLFLAG_RD, &adapter->stats.prc127,
4172                         "65-127 byte frames received");
4173         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
4174                         CTLFLAG_RD, &adapter->stats.prc255,
4175                         "128-255 byte frames received");
4176         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
4177                         CTLFLAG_RD, &adapter->stats.prc511,
4178                         "256-511 byte frames received");
4179         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
4180                         CTLFLAG_RD, &adapter->stats.prc1023,
4181                         "512-1023 byte frames received");
4182         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
4183                         CTLFLAG_RD, &adapter->stats.prc1522,
4184                         "1023-1522 byte frames received");
4185         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
4186                         CTLFLAG_RD, &adapter->stats.gorc,
4187                         "Good Octets Received");
4188
4189         /* Packet Transmission Stats */
4190         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
4191                         CTLFLAG_RD, &adapter->stats.gotc,
4192                         "Good Octets Transmitted");
4193         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
4194                         CTLFLAG_RD, &adapter->stats.tpt,
4195                         "Total Packets Transmitted");
4196         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
4197                         CTLFLAG_RD, &adapter->stats.gptc,
4198                         "Good Packets Transmitted");
4199         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
4200                         CTLFLAG_RD, &adapter->stats.bptc,
4201                         "Broadcast Packets Transmitted");
4202         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
4203                         CTLFLAG_RD, &adapter->stats.mptc,
4204                         "Multicast Packets Transmitted");
4205         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
4206                         CTLFLAG_RD, &adapter->stats.ptc64,
4207                         "64 byte frames transmitted ");
4208         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
4209                         CTLFLAG_RD, &adapter->stats.ptc127,
4210                         "65-127 byte frames transmitted");
4211         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
4212                         CTLFLAG_RD, &adapter->stats.ptc255,
4213                         "128-255 byte frames transmitted");
4214         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
4215                         CTLFLAG_RD, &adapter->stats.ptc511,
4216                         "256-511 byte frames transmitted");
4217         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
4218                         CTLFLAG_RD, &adapter->stats.ptc1023,
4219                         "512-1023 byte frames transmitted");
4220         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
4221                         CTLFLAG_RD, &adapter->stats.ptc1522,
4222                         "1024-1522 byte frames transmitted");
4223         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
4224                         CTLFLAG_RD, &adapter->stats.tsctc,
4225                         "TSO Contexts Transmitted");
4226         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
4227                         CTLFLAG_RD, &adapter->stats.tsctfc,
4228                         "TSO Contexts Failed");
4229
4230
4231         /* Interrupt Stats */
4232
4233         int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
4234                                     CTLFLAG_RD, NULL, "Interrupt Statistics");
4235         int_list = SYSCTL_CHILDREN(int_node);
4236
4237         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
4238                         CTLFLAG_RD, &adapter->stats.iac,
4239                         "Interrupt Assertion Count");
4240
4241         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
4242                         CTLFLAG_RD, &adapter->stats.icrxptc,
4243                         "Interrupt Cause Rx Pkt Timer Expire Count");
4244
4245         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
4246                         CTLFLAG_RD, &adapter->stats.icrxatc,
4247                         "Interrupt Cause Rx Abs Timer Expire Count");
4248
4249         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
4250                         CTLFLAG_RD, &adapter->stats.ictxptc,
4251                         "Interrupt Cause Tx Pkt Timer Expire Count");
4252
4253         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
4254                         CTLFLAG_RD, &adapter->stats.ictxatc,
4255                         "Interrupt Cause Tx Abs Timer Expire Count");
4256
4257         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
4258                         CTLFLAG_RD, &adapter->stats.ictxqec,
4259                         "Interrupt Cause Tx Queue Empty Count");
4260
4261         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
4262                         CTLFLAG_RD, &adapter->stats.ictxqmtc,
4263                         "Interrupt Cause Tx Queue Min Thresh Count");
4264
4265         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
4266                         CTLFLAG_RD, &adapter->stats.icrxdmtc,
4267                         "Interrupt Cause Rx Desc Min Thresh Count");
4268
4269         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
4270                         CTLFLAG_RD, &adapter->stats.icrxoc,
4271                         "Interrupt Cause Receiver Overrun Count");
4272 }
4273
4274 /**********************************************************************
4275  *
4276  *  This routine provides a way to dump out the adapter eeprom,
4277  *  often a useful debug/service tool. This only dumps the first
4278  *  32 words, stuff that matters is in that extent.
4279  *
4280  **********************************************************************/
4281 static int
4282 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4283 {
4284         struct adapter *adapter = (struct adapter *)arg1;
4285         int error;
4286         int result;
4287
4288         result = -1;
4289         error = sysctl_handle_int(oidp, &result, 0, req);
4290
4291         if (error || !req->newptr)
4292                 return (error);
4293
4294         /*
4295          * This value will cause a hex dump of the
4296          * first 32 16-bit words of the EEPROM to
4297          * the screen.
4298          */
4299         if (result == 1)
4300                 em_print_nvm_info(adapter);
4301
4302         return (error);
4303 }
4304
4305 static void
4306 em_print_nvm_info(struct adapter *adapter)
4307 {
4308         u16 eeprom_data;
4309         int i, j, row = 0;
4310
4311         /* Its a bit crude, but it gets the job done */
4312         printf("\nInterface EEPROM Dump:\n");
4313         printf("Offset\n0x0000  ");
4314         for (i = 0, j = 0; i < 32; i++, j++) {
4315                 if (j == 8) { /* Make the offset block */
4316                         j = 0; ++row;
4317                         printf("\n0x00%x0  ",row);
4318                 }
4319                 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
4320                 printf("%04x ", eeprom_data);
4321         }
4322         printf("\n");
4323 }
4324
4325 static int
4326 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4327 {
4328         struct em_int_delay_info *info;
4329         struct adapter *adapter;
4330         u32 regval;
4331         int error, usecs, ticks;
4332
4333         info = (struct em_int_delay_info *) arg1;
4334         usecs = info->value;
4335         error = sysctl_handle_int(oidp, &usecs, 0, req);
4336         if (error != 0 || req->newptr == NULL)
4337                 return (error);
4338         if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4339                 return (EINVAL);
4340         info->value = usecs;
4341         ticks = EM_USECS_TO_TICKS(usecs);
4342         if (info->offset == E1000_ITR)  /* units are 256ns here */
4343                 ticks *= 4;
4344
4345         adapter = info->adapter;
4346
4347         regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
4348         regval = (regval & ~0xffff) | (ticks & 0xffff);
4349         /* Handle a few special cases. */
4350         switch (info->offset) {
4351         case E1000_RDTR:
4352                 break;
4353         case E1000_TIDV:
4354                 if (ticks == 0) {
4355                         adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
4356                         /* Don't write 0 into the TIDV register. */
4357                         regval++;
4358                 } else
4359                         adapter->txd_cmd |= E1000_TXD_CMD_IDE;
4360                 break;
4361         }
4362         E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
4363         return (0);
4364 }
4365
4366 static void
4367 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
4368         const char *description, struct em_int_delay_info *info,
4369         int offset, int value)
4370 {
4371         info->adapter = adapter;
4372         info->offset = offset;
4373         info->value = value;
4374         SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev),
4375             SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4376             OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
4377             info, 0, em_sysctl_int_delay, "I", description);
4378 }
4379
4380 /*
4381  * Set flow control using sysctl:
4382  * Flow control values:
4383  *      0 - off
4384  *      1 - rx pause
4385  *      2 - tx pause
4386  *      3 - full
4387  */
4388 static int
4389 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4390 {
4391         int error;
4392         static int input = 3; /* default is full */
4393         struct adapter  *adapter = (struct adapter *) arg1;
4394
4395         error = sysctl_handle_int(oidp, &input, 0, req);
4396
4397         if ((error) || (req->newptr == NULL))
4398                 return (error);
4399
4400         if (input == adapter->fc) /* no change? */
4401                 return (error);
4402
4403         switch (input) {
4404         case e1000_fc_rx_pause:
4405         case e1000_fc_tx_pause:
4406         case e1000_fc_full:
4407         case e1000_fc_none:
4408                 adapter->hw.fc.requested_mode = input;
4409                 adapter->fc = input;
4410                 break;
4411         default:
4412                 /* Do nothing */
4413                 return (error);
4414         }
4415
4416         adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
4417         e1000_force_mac_fc(&adapter->hw);
4418         return (error);
4419 }
4420
4421 /*
4422  * Manage Energy Efficient Ethernet:
4423  * Control values:
4424  *     0/1 - enabled/disabled
4425  */
4426 static int
4427 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4428 {
4429         struct adapter *adapter = (struct adapter *) arg1;
4430         int error, value;
4431
4432         value = adapter->hw.dev_spec.ich8lan.eee_disable;
4433         error = sysctl_handle_int(oidp, &value, 0, req);
4434         if (error || req->newptr == NULL)
4435                 return (error);
4436         adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4437         em_if_init(adapter->ctx);
4438
4439         return (0);
4440 }
4441
4442 static int
4443 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4444 {
4445         struct adapter *adapter;
4446         int error;
4447         int result;
4448
4449         result = -1;
4450         error = sysctl_handle_int(oidp, &result, 0, req);
4451
4452         if (error || !req->newptr)
4453                 return (error);
4454
4455         if (result == 1) {
4456                 adapter = (struct adapter *) arg1;
4457                 em_print_debug_info(adapter);
4458         }
4459
4460         return (error);
4461 }
4462
4463 static int
4464 em_get_rs(SYSCTL_HANDLER_ARGS)
4465 {
4466         struct adapter *adapter = (struct adapter *) arg1;
4467         int error;
4468         int result;
4469
4470         result = 0;
4471         error = sysctl_handle_int(oidp, &result, 0, req);
4472
4473         if (error || !req->newptr || result != 1)
4474                 return (error);
4475         em_dump_rs(adapter);
4476
4477         return (error);
4478 }
4479
4480 static void
4481 em_if_debug(if_ctx_t ctx)
4482 {
4483         em_dump_rs(iflib_get_softc(ctx));
4484 }
4485
4486 /*
4487  * This routine is meant to be fluid, add whatever is
4488  * needed for debugging a problem.  -jfv
4489  */
4490 static void
4491 em_print_debug_info(struct adapter *adapter)
4492 {
4493         device_t dev = iflib_get_dev(adapter->ctx);
4494         struct ifnet *ifp = iflib_get_ifp(adapter->ctx);
4495         struct tx_ring *txr = &adapter->tx_queues->txr;
4496         struct rx_ring *rxr = &adapter->rx_queues->rxr;
4497
4498         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
4499                 printf("Interface is RUNNING ");
4500         else
4501                 printf("Interface is NOT RUNNING\n");
4502
4503         if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
4504                 printf("and INACTIVE\n");
4505         else
4506                 printf("and ACTIVE\n");
4507
4508         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
4509                 device_printf(dev, "TX Queue %d ------\n", i);
4510                 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
4511                         E1000_READ_REG(&adapter->hw, E1000_TDH(i)),
4512                         E1000_READ_REG(&adapter->hw, E1000_TDT(i)));
4513
4514         }
4515         for (int j=0; j < adapter->rx_num_queues; j++, rxr++) {
4516                 device_printf(dev, "RX Queue %d ------\n", j);
4517                 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
4518                         E1000_READ_REG(&adapter->hw, E1000_RDH(j)),
4519                         E1000_READ_REG(&adapter->hw, E1000_RDT(j)));
4520         }
4521 }
4522
4523 /*
4524  * 82574 only:
4525  * Write a new value to the EEPROM increasing the number of MSI-X
4526  * vectors from 3 to 5, for proper multiqueue support.
4527  */
4528 static void
4529 em_enable_vectors_82574(if_ctx_t ctx)
4530 {
4531         struct adapter *adapter = iflib_get_softc(ctx);
4532         struct e1000_hw *hw = &adapter->hw;
4533         device_t dev = iflib_get_dev(ctx);
4534         u16 edata;
4535
4536         e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4537         if (bootverbose)
4538                 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata);
4539         if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
4540                 device_printf(dev, "Writing to eeprom: increasing "
4541                     "reported MSI-X vectors from 3 to 5...\n");
4542                 edata &= ~(EM_NVM_MSIX_N_MASK);
4543                 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
4544                 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4545                 e1000_update_nvm_checksum(hw);
4546                 device_printf(dev, "Writing to eeprom: done\n");
4547         }
4548 }