sys/dev/e1000/if_em.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /* $FreeBSD$ */
  30 #include "if_em.h"
  31 #include <sys/sbuf.h>
  32 #include <machine/_inttypes.h>
  33
  34 #define em_mac_min e1000_82571
  35 #define igb_mac_min e1000_82575
  36
  37 /*********************************************************************
  38  *  Driver version:
  39  *********************************************************************/
  40 char em_driver_version[] = "7.6.1-k";
  41
  42 /*********************************************************************
  43  *  PCI Device ID Table
  44  *
  45  *  Used by probe to select devices to load on
  46  *  Last field stores an index into e1000_strings
  47  *  Last entry must be all 0s
  48  *
  49  *  { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
  50  *********************************************************************/
  51
  52 static pci_vendor_info_t em_vendor_info_array[] =
  53 {
  54         /* Intel(R) - lem-class legacy devices */
  55         PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"),
  56         PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"),
  57         PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"),
  58         PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"),
  59         PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"),
  60
  61         PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"),
  62         PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"),
  63         PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"),
  64         PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"),
  65         PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"),
  66         PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"),
  67         PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"),
  68
  69         PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"),
  70
  71         PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"),
  72         PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"),
  73
  74         PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"),
  75         PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"),
  76         PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"),
  77         PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"),
  78
  79         PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"),
  80         PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"),
  81         PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"),
  82         PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"),
  83         PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"),
  84
  85         PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"),
  86         PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"),
  87         PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"),
  88         PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"),
  89         PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"),
  90         PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"),
  91         PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"),
  92         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
  93         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
  94
  95         PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"),
  96         PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"),
  97         PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"),
  98
  99         /* Intel(R) - em-class devices */
 100         PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"),
 101         PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"),
 102         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"),
 103         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"),
 104         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"),
 105         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
 106         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
 107         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"),
 108         PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"),
 109         PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"),
 110         PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"),
 111         PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"),
 112         PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"),
 113         PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"),
 114         PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"),
 115         PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"),
 116         PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"),
 117         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"),
 118         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"),
 119         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"),
 120         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"),
 121         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"),
 122         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"),
 123         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"),
 124         PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"),
 125         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"),
 126         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"),
 127         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"),
 128         PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"),
 129         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"),
 130         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"),
 131         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"),
 132         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"),
 133         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"),
 134         PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"),
 135         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"),
 136         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"),
 137         PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"),
 138         PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"),
 139         PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"),
 140         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"),
 141         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"),
 142         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"),
 143         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"),
 144         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"),
 145         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"),
 146         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"),
 147         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"),
 148         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"),
 149         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"),
 150         PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"),
 151         PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"),
 152         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"),
 153         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"),
 154         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"),
 155         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"),
 156         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"),
 157         PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"),
 158         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"),
 159         PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"),
 160         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"),
 161         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"),
 162         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"),
 163         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"),
 164         PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"),
 165         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"),
 166         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"),
 167         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"),
 168         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"),
 169         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"),
 170         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"),
 171         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"),
 172         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"),
 173         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"),
 174         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"),
 175         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"),
 176         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"),
 177         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"),
 178         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"),
 179         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"),
 180         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"),
 181         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"),
 182         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"),
 183         PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"),
 184         PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"),
 185         PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"),
 186         PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"),
 187         PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"),
 188         PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"),
 189         PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"),
 190         PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"),
 191         PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"),
 192         PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"),
 193         PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"),
 194         PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"),
 195         PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"),
 196         PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"),
 197         /* required last entry */
 198         PVID_END
 199 };
 200
 201 static pci_vendor_info_t igb_vendor_info_array[] =
 202 {
 203         /* Intel(R) - igb-class devices */
 204         PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"),
 205         PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"),
 206         PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"),
 207         PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"),
 208         PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"),
 209         PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"),
 210         PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"),
 211         PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"),
 212         PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"),
 213         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"),
 214         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"),
 215         PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"),
 216         PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"),
 217         PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"),
 218         PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"),
 219         PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"),
 220         PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"),
 221         PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"),
 222         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"),
 223         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"),
 224         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"),
 225         PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"),
 226         PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"),
 227         PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"),
 228         PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"),
 229         PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"),
 230         PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"),
 231         PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"),
 232         PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"),
 233         PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"),
 234         PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"),
 235         PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"),
 236         PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"),
 237         PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"),
 238         PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"),
 239         PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"),
 240         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"),
 241         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"),
 242         PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"),
 243         /* required last entry */
 244         PVID_END
 245 };
 246
 247 /*********************************************************************
 248  *  Function prototypes
 249  *********************************************************************/
 250 static void     *em_register(device_t dev);
 251 static void     *igb_register(device_t dev);
 252 static int      em_if_attach_pre(if_ctx_t ctx);
 253 static int      em_if_attach_post(if_ctx_t ctx);
 254 static int      em_if_detach(if_ctx_t ctx);
 255 static int      em_if_shutdown(if_ctx_t ctx);
 256 static int      em_if_suspend(if_ctx_t ctx);
 257 static int      em_if_resume(if_ctx_t ctx);
 258
 259 static int      em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets);
 260 static int      em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets);
 261 static void     em_if_queues_free(if_ctx_t ctx);
 262
 263 static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
 264 static void     em_if_init(if_ctx_t ctx);
 265 static void     em_if_stop(if_ctx_t ctx);
 266 static void     em_if_media_status(if_ctx_t, struct ifmediareq *);
 267 static int      em_if_media_change(if_ctx_t ctx);
 268 static int      em_if_mtu_set(if_ctx_t ctx, uint32_t mtu);
 269 static void     em_if_timer(if_ctx_t ctx, uint16_t qid);
 270 static void     em_if_vlan_register(if_ctx_t ctx, u16 vtag);
 271 static void     em_if_vlan_unregister(if_ctx_t ctx, u16 vtag);
 272 static void     em_if_watchdog_reset(if_ctx_t ctx);
 273 static bool     em_if_needs_restart(if_ctx_t ctx, enum iflib_restart_event event);
 274
 275 static void     em_identify_hardware(if_ctx_t ctx);
 276 static int      em_allocate_pci_resources(if_ctx_t ctx);
 277 static void     em_free_pci_resources(if_ctx_t ctx);
 278 static void     em_reset(if_ctx_t ctx);
 279 static int      em_setup_interface(if_ctx_t ctx);
 280 static int      em_setup_msix(if_ctx_t ctx);
 281
 282 static void     em_initialize_transmit_unit(if_ctx_t ctx);
 283 static void     em_initialize_receive_unit(if_ctx_t ctx);
 284
 285 static void     em_if_intr_enable(if_ctx_t ctx);
 286 static void     em_if_intr_disable(if_ctx_t ctx);
 287 static void     igb_if_intr_enable(if_ctx_t ctx);
 288 static void     igb_if_intr_disable(if_ctx_t ctx);
 289 static int      em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 290 static int      em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
 291 static int      igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 292 static int      igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
 293 static void     em_if_multi_set(if_ctx_t ctx);
 294 static void     em_if_update_admin_status(if_ctx_t ctx);
 295 static void     em_if_debug(if_ctx_t ctx);
 296 static void     em_update_stats_counters(struct adapter *);
 297 static void     em_add_hw_stats(struct adapter *adapter);
 298 static int      em_if_set_promisc(if_ctx_t ctx, int flags);
 299 static void     em_setup_vlan_hw_support(struct adapter *);
 300 static int      em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
 301 static void     em_print_nvm_info(struct adapter *);
 302 static int      em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 303 static int      em_get_rs(SYSCTL_HANDLER_ARGS);
 304 static void     em_print_debug_info(struct adapter *);
 305 static int      em_is_valid_ether_addr(u8 *);
 306 static int      em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
 307 static void     em_add_int_delay_sysctl(struct adapter *, const char *,
 308                     const char *, struct em_int_delay_info *, int, int);
 309 /* Management and WOL Support */
 310 static void     em_init_manageability(struct adapter *);
 311 static void     em_release_manageability(struct adapter *);
 312 static void     em_get_hw_control(struct adapter *);
 313 static void     em_release_hw_control(struct adapter *);
 314 static void     em_get_wakeup(if_ctx_t ctx);
 315 static void     em_enable_wakeup(if_ctx_t ctx);
 316 static int      em_enable_phy_wakeup(struct adapter *);
 317 static void     em_disable_aspm(struct adapter *);
 318
 319 int             em_intr(void *arg);
 320
 321 /* MSI-X handlers */
 322 static int      em_if_msix_intr_assign(if_ctx_t, int);
 323 static int      em_msix_link(void *);
 324 static void     em_handle_link(void *context);
 325
 326 static void     em_enable_vectors_82574(if_ctx_t);
 327
 328 static int      em_set_flowcntl(SYSCTL_HANDLER_ARGS);
 329 static int      em_sysctl_eee(SYSCTL_HANDLER_ARGS);
 330 static void     em_if_led_func(if_ctx_t ctx, int onoff);
 331
 332 static int      em_get_regs(SYSCTL_HANDLER_ARGS);
 333
 334 static void     lem_smartspeed(struct adapter *adapter);
 335 static void     igb_configure_queues(struct adapter *adapter);
 336
 337
 338 /*********************************************************************
 339  *  FreeBSD Device Interface Entry Points
 340  *********************************************************************/
 341 static device_method_t em_methods[] = {
 342         /* Device interface */
 343         DEVMETHOD(device_register, em_register),
 344         DEVMETHOD(device_probe, iflib_device_probe),
 345         DEVMETHOD(device_attach, iflib_device_attach),
 346         DEVMETHOD(device_detach, iflib_device_detach),
 347         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 348         DEVMETHOD(device_suspend, iflib_device_suspend),
 349         DEVMETHOD(device_resume, iflib_device_resume),
 350         DEVMETHOD_END
 351 };
 352
 353 static device_method_t igb_methods[] = {
 354         /* Device interface */
 355         DEVMETHOD(device_register, igb_register),
 356         DEVMETHOD(device_probe, iflib_device_probe),
 357         DEVMETHOD(device_attach, iflib_device_attach),
 358         DEVMETHOD(device_detach, iflib_device_detach),
 359         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 360         DEVMETHOD(device_suspend, iflib_device_suspend),
 361         DEVMETHOD(device_resume, iflib_device_resume),
 362         DEVMETHOD_END
 363 };
 364
 365
 366 static driver_t em_driver = {
 367         "em", em_methods, sizeof(struct adapter),
 368 };
 369
 370 static devclass_t em_devclass;
 371 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
 372
 373 MODULE_DEPEND(em, pci, 1, 1, 1);
 374 MODULE_DEPEND(em, ether, 1, 1, 1);
 375 MODULE_DEPEND(em, iflib, 1, 1, 1);
 376
 377 IFLIB_PNP_INFO(pci, em, em_vendor_info_array);
 378
 379 static driver_t igb_driver = {
 380         "igb", igb_methods, sizeof(struct adapter),
 381 };
 382
 383 static devclass_t igb_devclass;
 384 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
 385
 386 MODULE_DEPEND(igb, pci, 1, 1, 1);
 387 MODULE_DEPEND(igb, ether, 1, 1, 1);
 388 MODULE_DEPEND(igb, iflib, 1, 1, 1);
 389
 390 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array);
 391
 392 static device_method_t em_if_methods[] = {
 393         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 394         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 395         DEVMETHOD(ifdi_detach, em_if_detach),
 396         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 397         DEVMETHOD(ifdi_suspend, em_if_suspend),
 398         DEVMETHOD(ifdi_resume, em_if_resume),
 399         DEVMETHOD(ifdi_init, em_if_init),
 400         DEVMETHOD(ifdi_stop, em_if_stop),
 401         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 402         DEVMETHOD(ifdi_intr_enable, em_if_intr_enable),
 403         DEVMETHOD(ifdi_intr_disable, em_if_intr_disable),
 404         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 405         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 406         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 407         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 408         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 409         DEVMETHOD(ifdi_media_status, em_if_media_status),
 410         DEVMETHOD(ifdi_media_change, em_if_media_change),
 411         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 412         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 413         DEVMETHOD(ifdi_timer, em_if_timer),
 414         DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
 415         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 416         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 417         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 418         DEVMETHOD(ifdi_led_func, em_if_led_func),
 419         DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable),
 420         DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable),
 421         DEVMETHOD(ifdi_debug, em_if_debug),
 422         DEVMETHOD(ifdi_needs_restart, em_if_needs_restart),
 423         DEVMETHOD_END
 424 };
 425
 426 static driver_t em_if_driver = {
 427         "em_if", em_if_methods, sizeof(struct adapter)
 428 };
 429
 430 static device_method_t igb_if_methods[] = {
 431         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 432         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 433         DEVMETHOD(ifdi_detach, em_if_detach),
 434         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 435         DEVMETHOD(ifdi_suspend, em_if_suspend),
 436         DEVMETHOD(ifdi_resume, em_if_resume),
 437         DEVMETHOD(ifdi_init, em_if_init),
 438         DEVMETHOD(ifdi_stop, em_if_stop),
 439         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 440         DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable),
 441         DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable),
 442         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 443         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 444         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 445         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 446         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 447         DEVMETHOD(ifdi_media_status, em_if_media_status),
 448         DEVMETHOD(ifdi_media_change, em_if_media_change),
 449         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 450         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 451         DEVMETHOD(ifdi_timer, em_if_timer),
 452         DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
 453         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 454         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 455         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 456         DEVMETHOD(ifdi_led_func, em_if_led_func),
 457         DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable),
 458         DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable),
 459         DEVMETHOD(ifdi_debug, em_if_debug),
 460         DEVMETHOD(ifdi_needs_restart, em_if_needs_restart),
 461         DEVMETHOD_END
 462 };
 463
 464 static driver_t igb_if_driver = {
 465         "igb_if", igb_if_methods, sizeof(struct adapter)
 466 };
 467
 468 /*********************************************************************
 469  *  Tunable default values.
 470  *********************************************************************/
 471
 472 #define EM_TICKS_TO_USECS(ticks)        ((1024 * (ticks) + 500) / 1000)
 473 #define EM_USECS_TO_TICKS(usecs)        ((1000 * (usecs) + 512) / 1024)
 474
 475 #define MAX_INTS_PER_SEC        8000
 476 #define DEFAULT_ITR             (1000000000/(MAX_INTS_PER_SEC * 256))
 477
 478 /* Allow common code without TSO */
 479 #ifndef CSUM_TSO
 480 #define CSUM_TSO        0
 481 #endif
 482
 483 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
 484     "EM driver parameters");
 485
 486 static int em_disable_crc_stripping = 0;
 487 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
 488     &em_disable_crc_stripping, 0, "Disable CRC Stripping");
 489
 490 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
 491 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
 492 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
 493     0, "Default transmit interrupt delay in usecs");
 494 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
 495     0, "Default receive interrupt delay in usecs");
 496
 497 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
 498 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
 499 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
 500     &em_tx_abs_int_delay_dflt, 0,
 501     "Default transmit interrupt delay limit in usecs");
 502 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
 503     &em_rx_abs_int_delay_dflt, 0,
 504     "Default receive interrupt delay limit in usecs");
 505
 506 static int em_smart_pwr_down = FALSE;
 507 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
 508     0, "Set to true to leave smart power down enabled on newer adapters");
 509
 510 /* Controls whether promiscuous also shows bad packets */
 511 static int em_debug_sbp = FALSE;
 512 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
 513     "Show bad packets in promiscuous mode");
 514
 515 /* How many packets rxeof tries to clean at a time */
 516 static int em_rx_process_limit = 100;
 517 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
 518     &em_rx_process_limit, 0,
 519     "Maximum number of received packets to process "
 520     "at a time, -1 means unlimited");
 521
 522 /* Energy efficient ethernet - default to OFF */
 523 static int eee_setting = 1;
 524 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
 525     "Enable Energy Efficient Ethernet");
 526
 527 /*
 528 ** Tuneable Interrupt rate
 529 */
 530 static int em_max_interrupt_rate = 8000;
 531 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
 532     &em_max_interrupt_rate, 0, "Maximum interrupts per second");
 533
 534
 535
 536 /* Global used in WOL setup with multiport cards */
 537 static int global_quad_port_a = 0;
 538
 539 extern struct if_txrx igb_txrx;
 540 extern struct if_txrx em_txrx;
 541 extern struct if_txrx lem_txrx;
 542
 543 static struct if_shared_ctx em_sctx_init = {
 544         .isc_magic = IFLIB_MAGIC,
 545         .isc_q_align = PAGE_SIZE,
 546         .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 547         .isc_tx_maxsegsize = PAGE_SIZE,
 548         .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 549         .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
 550         .isc_rx_maxsize = MJUM9BYTES,
 551         .isc_rx_nsegments = 1,
 552         .isc_rx_maxsegsize = MJUM9BYTES,
 553         .isc_nfl = 1,
 554         .isc_nrxqs = 1,
 555         .isc_ntxqs = 1,
 556         .isc_admin_intrcnt = 1,
 557         .isc_vendor_info = em_vendor_info_array,
 558         .isc_driver_version = em_driver_version,
 559         .isc_driver = &em_if_driver,
 560         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 561
 562         .isc_nrxd_min = {EM_MIN_RXD},
 563         .isc_ntxd_min = {EM_MIN_TXD},
 564         .isc_nrxd_max = {EM_MAX_RXD},
 565         .isc_ntxd_max = {EM_MAX_TXD},
 566         .isc_nrxd_default = {EM_DEFAULT_RXD},
 567         .isc_ntxd_default = {EM_DEFAULT_TXD},
 568 };
 569
 570 static struct if_shared_ctx igb_sctx_init = {
 571         .isc_magic = IFLIB_MAGIC,
 572         .isc_q_align = PAGE_SIZE,
 573         .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 574         .isc_tx_maxsegsize = PAGE_SIZE,
 575         .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 576         .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
 577         .isc_rx_maxsize = MJUM9BYTES,
 578         .isc_rx_nsegments = 1,
 579         .isc_rx_maxsegsize = MJUM9BYTES,
 580         .isc_nfl = 1,
 581         .isc_nrxqs = 1,
 582         .isc_ntxqs = 1,
 583         .isc_admin_intrcnt = 1,
 584         .isc_vendor_info = igb_vendor_info_array,
 585         .isc_driver_version = em_driver_version,
 586         .isc_driver = &igb_if_driver,
 587         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 588
 589         .isc_nrxd_min = {EM_MIN_RXD},
 590         .isc_ntxd_min = {EM_MIN_TXD},
 591         .isc_nrxd_max = {IGB_MAX_RXD},
 592         .isc_ntxd_max = {IGB_MAX_TXD},
 593         .isc_nrxd_default = {EM_DEFAULT_RXD},
 594         .isc_ntxd_default = {EM_DEFAULT_TXD},
 595 };
 596
 597 /*****************************************************************
 598  *
 599  * Dump Registers
 600  *
 601  ****************************************************************/
 602 #define IGB_REGS_LEN 739
 603
 604 static int em_get_regs(SYSCTL_HANDLER_ARGS)
 605 {
 606         struct adapter *adapter = (struct adapter *)arg1;
 607         struct e1000_hw *hw = &adapter->hw;
 608         struct sbuf *sb;
 609         u32 *regs_buff;
 610         int rc;
 611
 612         regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK);
 613         memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
 614
 615         rc = sysctl_wire_old_buffer(req, 0);
 616         MPASS(rc == 0);
 617         if (rc != 0) {
 618                 free(regs_buff, M_DEVBUF);
 619                 return (rc);
 620         }
 621
 622         sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
 623         MPASS(sb != NULL);
 624         if (sb == NULL) {
 625                 free(regs_buff, M_DEVBUF);
 626                 return (ENOMEM);
 627         }
 628
 629         /* General Registers */
 630         regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
 631         regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
 632         regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
 633         regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
 634         regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
 635         regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
 636         regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
 637         regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
 638         regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
 639         regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
 640         regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
 641         regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
 642         regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
 643         regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
 644         regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
 645         regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
 646         regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
 647         regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
 648         regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
 649         regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
 650         regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
 651         regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
 652
 653         sbuf_printf(sb, "General Registers\n");
 654         sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
 655         sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
 656         sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]);
 657
 658         sbuf_printf(sb, "Interrupt Registers\n");
 659         sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
 660
 661         sbuf_printf(sb, "RX Registers\n");
 662         sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
 663         sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
 664         sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
 665         sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
 666         sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
 667         sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
 668         sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
 669
 670         sbuf_printf(sb, "TX Registers\n");
 671         sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
 672         sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
 673         sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
 674         sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
 675         sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
 676         sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
 677         sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
 678         sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
 679         sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
 680         sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
 681         sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
 682
 683         free(regs_buff, M_DEVBUF);
 684
 685 #ifdef DUMP_DESCS
 686         {
 687                 if_softc_ctx_t scctx = adapter->shared;
 688                 struct rx_ring *rxr = &rx_que->rxr;
 689                 struct tx_ring *txr = &tx_que->txr;
 690                 int ntxd = scctx->isc_ntxd[0];
 691                 int nrxd = scctx->isc_nrxd[0];
 692                 int j;
 693
 694         for (j = 0; j < nrxd; j++) {
 695                 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
 696                 u32 length =  le32toh(rxr->rx_base[j].wb.upper.length);
 697                 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 "  Error:%d  Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
 698         }
 699
 700         for (j = 0; j < min(ntxd, 256); j++) {
 701                 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
 702
 703                 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x  eop: %d DD=%d\n",
 704                             j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
 705                             buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
 706
 707         }
 708         }
 709 #endif
 710
 711         rc = sbuf_finish(sb);
 712         sbuf_delete(sb);
 713         return(rc);
 714 }
 715
 716 static void *
 717 em_register(device_t dev)
 718 {
 719         return (&em_sctx_init);
 720 }
 721
 722 static void *
 723 igb_register(device_t dev)
 724 {
 725         return (&igb_sctx_init);
 726 }
 727
 728 static int
 729 em_set_num_queues(if_ctx_t ctx)
 730 {
 731         struct adapter *adapter = iflib_get_softc(ctx);
 732         int maxqueues;
 733
 734         /* Sanity check based on HW */
 735         switch (adapter->hw.mac.type) {
 736         case e1000_82576:
 737         case e1000_82580:
 738         case e1000_i350:
 739         case e1000_i354:
 740                 maxqueues = 8;
 741                 break;
 742         case e1000_i210:
 743         case e1000_82575:
 744                 maxqueues = 4;
 745                 break;
 746         case e1000_i211:
 747         case e1000_82574:
 748                 maxqueues = 2;
 749                 break;
 750         default:
 751                 maxqueues = 1;
 752                 break;
 753         }
 754
 755         return (maxqueues);
 756 }
 757
 758 #define LEM_CAPS                                                        \
 759     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 760     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER
 761
 762 #define EM_CAPS                                                         \
 763     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 764     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 |  \
 765     IFCAP_LRO | IFCAP_VLAN_HWTSO
 766
 767 #define IGB_CAPS                                                        \
 768     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 769     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 |  \
 770     IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\
 771     IFCAP_TSO6
 772
 773 /*********************************************************************
 774  *  Device initialization routine
 775  *
 776  *  The attach entry point is called when the driver is being loaded.
 777  *  This routine identifies the type of hardware, allocates all resources
 778  *  and initializes the hardware.
 779  *
 780  *  return 0 on success, positive on failure
 781  *********************************************************************/
 782 static int
 783 em_if_attach_pre(if_ctx_t ctx)
 784 {
 785         struct adapter *adapter;
 786         if_softc_ctx_t scctx;
 787         device_t dev;
 788         struct e1000_hw *hw;
 789         int error = 0;
 790
 791         INIT_DEBUGOUT("em_if_attach_pre: begin");
 792         dev = iflib_get_dev(ctx);
 793         adapter = iflib_get_softc(ctx);
 794
 795         adapter->ctx = adapter->osdep.ctx = ctx;
 796         adapter->dev = adapter->osdep.dev = dev;
 797         scctx = adapter->shared = iflib_get_softc_ctx(ctx);
 798         adapter->media = iflib_get_media(ctx);
 799         hw = &adapter->hw;
 800
 801         adapter->tx_process_limit = scctx->isc_ntxd[0];
 802
 803         /* SYSCTL stuff */
 804         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 805             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 806             OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
 807             adapter, 0, em_sysctl_nvm_info, "I", "NVM Information");
 808
 809         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 810             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 811             OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
 812             adapter, 0, em_sysctl_debug_info, "I", "Debug Information");
 813
 814         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 815             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 816             OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
 817             adapter, 0, em_set_flowcntl, "I", "Flow Control");
 818
 819         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 820             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 821             OID_AUTO, "reg_dump",
 822             CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 0,
 823             em_get_regs, "A", "Dump Registers");
 824
 825         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 826             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 827             OID_AUTO, "rs_dump",
 828             CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, adapter, 0,
 829             em_get_rs, "I", "Dump RS indexes");
 830
 831         /* Determine hardware and mac info */
 832         em_identify_hardware(ctx);
 833
 834         scctx->isc_tx_nsegments = EM_MAX_SCATTER;
 835         scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
 836         if (bootverbose)
 837                 device_printf(dev, "attach_pre capping queues at %d\n",
 838                     scctx->isc_ntxqsets_max);
 839
 840         if (hw->mac.type >= igb_mac_min) {
 841                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
 842                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
 843                 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
 844                 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
 845                 scctx->isc_txrx = &igb_txrx;
 846                 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
 847                 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 848                 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 849                 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS;
 850                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO |
 851                      CSUM_IP6_TCP | CSUM_IP6_UDP;
 852                 if (hw->mac.type != e1000_82575)
 853                         scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
 854                 /*
 855                 ** Some new devices, as with ixgbe, now may
 856                 ** use a different BAR, so we need to keep
 857                 ** track of which is used.
 858                 */
 859                 scctx->isc_msix_bar = pci_msix_table_bar(dev);
 860         } else if (hw->mac.type >= em_mac_min) {
 861                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 862                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
 863                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 864                 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
 865                 scctx->isc_txrx = &em_txrx;
 866                 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
 867                 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 868                 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 869                 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS;
 870                 /*
 871                  * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO}
 872                  * by default as we don't have workarounds for all associated
 873                  * silicon errata.  E. g., with several MACs such as 82573E,
 874                  * TSO only works at Gigabit speed and otherwise can cause the
 875                  * hardware to hang (which also would be next to impossible to
 876                  * work around given that already queued TSO-using descriptors
 877                  * would need to be flushed and vlan(4) reconfigured at runtime
 878                  * in case of a link speed change).  Moreover, MACs like 82579
 879                  * still can hang at Gigabit even with all publicly documented
 880                  * TSO workarounds implemented.  Generally, the penality of
 881                  * these workarounds is rather high and may involve copying
 882                  * mbuf data around so advantages of TSO lapse.  Still, TSO may
 883                  * work for a few MACs of this class - at least when sticking
 884                  * with Gigabit - in which case users may enable TSO manually.
 885                  */
 886                 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
 887                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 888                 /*
 889                  * We support MSI-X with 82574 only, but indicate to iflib(4)
 890                  * that it shall give MSI at least a try with other devices.
 891                  */
 892                 if (hw->mac.type == e1000_82574) {
 893                         scctx->isc_msix_bar = pci_msix_table_bar(dev);;
 894                 } else {
 895                         scctx->isc_msix_bar = -1;
 896                         scctx->isc_disable_msix = 1;
 897                 }
 898         } else {
 899                 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 900                 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
 901                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 902                 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
 903                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP;
 904                 scctx->isc_txrx = &lem_txrx;
 905                 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS;
 906                 if (hw->mac.type < e1000_82543)
 907                         scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
 908                 /* INTx only */
 909                 scctx->isc_msix_bar = 0;
 910         }
 911
 912         /* Setup PCI resources */
 913         if (em_allocate_pci_resources(ctx)) {
 914                 device_printf(dev, "Allocation of PCI resources failed\n");
 915                 error = ENXIO;
 916                 goto err_pci;
 917         }
 918
 919         /*
 920         ** For ICH8 and family we need to
 921         ** map the flash memory, and this
 922         ** must happen after the MAC is
 923         ** identified
 924         */
 925         if ((hw->mac.type == e1000_ich8lan) ||
 926             (hw->mac.type == e1000_ich9lan) ||
 927             (hw->mac.type == e1000_ich10lan) ||
 928             (hw->mac.type == e1000_pchlan) ||
 929             (hw->mac.type == e1000_pch2lan) ||
 930             (hw->mac.type == e1000_pch_lpt)) {
 931                 int rid = EM_BAR_TYPE_FLASH;
 932                 adapter->flash = bus_alloc_resource_any(dev,
 933                     SYS_RES_MEMORY, &rid, RF_ACTIVE);
 934                 if (adapter->flash == NULL) {
 935                         device_printf(dev, "Mapping of Flash failed\n");
 936                         error = ENXIO;
 937                         goto err_pci;
 938                 }
 939                 /* This is used in the shared code */
 940                 hw->flash_address = (u8 *)adapter->flash;
 941                 adapter->osdep.flash_bus_space_tag =
 942                     rman_get_bustag(adapter->flash);
 943                 adapter->osdep.flash_bus_space_handle =
 944                     rman_get_bushandle(adapter->flash);
 945         }
 946         /*
 947         ** In the new SPT device flash is not  a
 948         ** separate BAR, rather it is also in BAR0,
 949         ** so use the same tag and an offset handle for the
 950         ** FLASH read/write macros in the shared code.
 951         */
 952         else if (hw->mac.type >= e1000_pch_spt) {
 953                 adapter->osdep.flash_bus_space_tag =
 954                     adapter->osdep.mem_bus_space_tag;
 955                 adapter->osdep.flash_bus_space_handle =
 956                     adapter->osdep.mem_bus_space_handle
 957                     + E1000_FLASH_BASE_ADDR;
 958         }
 959
 960         /* Do Shared Code initialization */
 961         error = e1000_setup_init_funcs(hw, TRUE);
 962         if (error) {
 963                 device_printf(dev, "Setup of Shared code failed, error %d\n",
 964                     error);
 965                 error = ENXIO;
 966                 goto err_pci;
 967         }
 968
 969         em_setup_msix(ctx);
 970         e1000_get_bus_info(hw);
 971
 972         /* Set up some sysctls for the tunable interrupt delays */
 973         em_add_int_delay_sysctl(adapter, "rx_int_delay",
 974             "receive interrupt delay in usecs", &adapter->rx_int_delay,
 975             E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
 976         em_add_int_delay_sysctl(adapter, "tx_int_delay",
 977             "transmit interrupt delay in usecs", &adapter->tx_int_delay,
 978             E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
 979         em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
 980             "receive interrupt delay limit in usecs",
 981             &adapter->rx_abs_int_delay,
 982             E1000_REGISTER(hw, E1000_RADV),
 983             em_rx_abs_int_delay_dflt);
 984         em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
 985             "transmit interrupt delay limit in usecs",
 986             &adapter->tx_abs_int_delay,
 987             E1000_REGISTER(hw, E1000_TADV),
 988             em_tx_abs_int_delay_dflt);
 989         em_add_int_delay_sysctl(adapter, "itr",
 990             "interrupt delay limit in usecs/4",
 991             &adapter->tx_itr,
 992             E1000_REGISTER(hw, E1000_ITR),
 993             DEFAULT_ITR);
 994
 995         hw->mac.autoneg = DO_AUTO_NEG;
 996         hw->phy.autoneg_wait_to_complete = FALSE;
 997         hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 998
 999         if (hw->mac.type < em_mac_min) {
1000                 e1000_init_script_state_82541(hw, TRUE);
1001                 e1000_set_tbi_compatibility_82543(hw, TRUE);
1002         }
1003         /* Copper options */
1004         if (hw->phy.media_type == e1000_media_type_copper) {
1005                 hw->phy.mdix = AUTO_ALL_MODES;
1006                 hw->phy.disable_polarity_correction = FALSE;
1007                 hw->phy.ms_type = EM_MASTER_SLAVE;
1008         }
1009
1010         /*
1011          * Set the frame limits assuming
1012          * standard ethernet sized frames.
1013          */
1014         scctx->isc_max_frame_size = hw->mac.max_frame_size =
1015             ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
1016
1017         /*
1018          * This controls when hardware reports transmit completion
1019          * status.
1020          */
1021         hw->mac.report_tx_early = 1;
1022
1023         /* Allocate multicast array memory. */
1024         adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN *
1025             MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
1026         if (adapter->mta == NULL) {
1027                 device_printf(dev, "Can not allocate multicast setup array\n");
1028                 error = ENOMEM;
1029                 goto err_late;
1030         }
1031
1032         /* Check SOL/IDER usage */
1033         if (e1000_check_reset_block(hw))
1034                 device_printf(dev, "PHY reset is blocked"
1035                               " due to SOL/IDER session.\n");
1036
1037         /* Sysctl for setting Energy Efficient Ethernet */
1038         hw->dev_spec.ich8lan.eee_disable = eee_setting;
1039         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1040             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1041             OID_AUTO, "eee_control",
1042             CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
1043             adapter, 0, em_sysctl_eee, "I",
1044             "Disable Energy Efficient Ethernet");
1045
1046         /*
1047         ** Start from a known state, this is
1048         ** important in reading the nvm and
1049         ** mac from that.
1050         */
1051         e1000_reset_hw(hw);
1052
1053         /* Make sure we have a good EEPROM before we read from it */
1054         if (e1000_validate_nvm_checksum(hw) < 0) {
1055                 /*
1056                 ** Some PCI-E parts fail the first check due to
1057                 ** the link being in sleep state, call it again,
1058                 ** if it fails a second time its a real issue.
1059                 */
1060                 if (e1000_validate_nvm_checksum(hw) < 0) {
1061                         device_printf(dev,
1062                             "The EEPROM Checksum Is Not Valid\n");
1063                         error = EIO;
1064                         goto err_late;
1065                 }
1066         }
1067
1068         /* Copy the permanent MAC address out of the EEPROM */
1069         if (e1000_read_mac_addr(hw) < 0) {
1070                 device_printf(dev, "EEPROM read error while reading MAC"
1071                               " address\n");
1072                 error = EIO;
1073                 goto err_late;
1074         }
1075
1076         if (!em_is_valid_ether_addr(hw->mac.addr)) {
1077                 if (adapter->vf_ifp) {
1078                         u8 addr[ETHER_ADDR_LEN];
1079                         arc4rand(&addr, sizeof(addr), 0);
1080                         addr[0] &= 0xFE;
1081                         addr[0] |= 0x02;
1082                         bcopy(addr, hw->mac.addr, sizeof(addr));
1083                 } else {
1084                         device_printf(dev, "Invalid MAC address\n");
1085                         error = EIO;
1086                         goto err_late;
1087                 }
1088         }
1089
1090         /* Disable ULP support */
1091         e1000_disable_ulp_lpt_lp(hw, TRUE);
1092
1093         /*
1094          * Get Wake-on-Lan and Management info for later use
1095          */
1096         em_get_wakeup(ctx);
1097
1098         /* Enable only WOL MAGIC by default */
1099         scctx->isc_capenable &= ~IFCAP_WOL;
1100         if (adapter->wol != 0)
1101                 scctx->isc_capenable |= IFCAP_WOL_MAGIC;
1102
1103         iflib_set_mac(ctx, hw->mac.addr);
1104
1105         return (0);
1106
1107 err_late:
1108         em_release_hw_control(adapter);
1109 err_pci:
1110         em_free_pci_resources(ctx);
1111         free(adapter->mta, M_DEVBUF);
1112
1113         return (error);
1114 }
1115
1116 static int
1117 em_if_attach_post(if_ctx_t ctx)
1118 {
1119         struct adapter *adapter = iflib_get_softc(ctx);
1120         struct e1000_hw *hw = &adapter->hw;
1121         int error = 0;
1122
1123         /* Setup OS specific network interface */
1124         error = em_setup_interface(ctx);
1125         if (error != 0) {
1126                 device_printf(adapter->dev, "Interface setup failed: %d\n", error);
1127                 goto err_late;
1128         }
1129
1130         em_reset(ctx);
1131
1132         /* Initialize statistics */
1133         em_update_stats_counters(adapter);
1134         hw->mac.get_link_status = 1;
1135         em_if_update_admin_status(ctx);
1136         em_add_hw_stats(adapter);
1137
1138         /* Non-AMT based hardware can now take control from firmware */
1139         if (adapter->has_manage && !adapter->has_amt)
1140                 em_get_hw_control(adapter);
1141
1142         INIT_DEBUGOUT("em_if_attach_post: end");
1143
1144         return (0);
1145
1146 err_late:
1147         /* upon attach_post() error, iflib calls _if_detach() to free resources. */
1148         return (error);
1149 }
1150
1151 /*********************************************************************
1152  *  Device removal routine
1153  *
1154  *  The detach entry point is called when the driver is being removed.
1155  *  This routine stops the adapter and deallocates all the resources
1156  *  that were allocated for driver operation.
1157  *
1158  *  return 0 on success, positive on failure
1159  *********************************************************************/
1160 static int
1161 em_if_detach(if_ctx_t ctx)
1162 {
1163         struct adapter  *adapter = iflib_get_softc(ctx);
1164
1165         INIT_DEBUGOUT("em_if_detach: begin");
1166
1167         e1000_phy_hw_reset(&adapter->hw);
1168
1169         em_release_manageability(adapter);
1170         em_release_hw_control(adapter);
1171         em_free_pci_resources(ctx);
1172         free(adapter->mta, M_DEVBUF);
1173         adapter->mta = NULL;
1174
1175         return (0);
1176 }
1177
1178 /*********************************************************************
1179  *
1180  *  Shutdown entry point
1181  *
1182  **********************************************************************/
1183
1184 static int
1185 em_if_shutdown(if_ctx_t ctx)
1186 {
1187         return em_if_suspend(ctx);
1188 }
1189
1190 /*
1191  * Suspend/resume device methods.
1192  */
1193 static int
1194 em_if_suspend(if_ctx_t ctx)
1195 {
1196         struct adapter *adapter = iflib_get_softc(ctx);
1197
1198         em_release_manageability(adapter);
1199         em_release_hw_control(adapter);
1200         em_enable_wakeup(ctx);
1201         return (0);
1202 }
1203
1204 static int
1205 em_if_resume(if_ctx_t ctx)
1206 {
1207         struct adapter *adapter = iflib_get_softc(ctx);
1208
1209         if (adapter->hw.mac.type == e1000_pch2lan)
1210                 e1000_resume_workarounds_pchlan(&adapter->hw);
1211         em_if_init(ctx);
1212         em_init_manageability(adapter);
1213
1214         return(0);
1215 }
1216
1217 static int
1218 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1219 {
1220         int max_frame_size;
1221         struct adapter *adapter = iflib_get_softc(ctx);
1222         if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1223
1224         IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1225
1226         switch (adapter->hw.mac.type) {
1227         case e1000_82571:
1228         case e1000_82572:
1229         case e1000_ich9lan:
1230         case e1000_ich10lan:
1231         case e1000_pch2lan:
1232         case e1000_pch_lpt:
1233         case e1000_pch_spt:
1234         case e1000_pch_cnp:
1235         case e1000_pch_tgp:
1236         case e1000_pch_adp:
1237         case e1000_pch_mtp:
1238         case e1000_82574:
1239         case e1000_82583:
1240         case e1000_80003es2lan:
1241                 /* 9K Jumbo Frame size */
1242                 max_frame_size = 9234;
1243                 break;
1244         case e1000_pchlan:
1245                 max_frame_size = 4096;
1246                 break;
1247         case e1000_82542:
1248         case e1000_ich8lan:
1249                 /* Adapters that do not support jumbo frames */
1250                 max_frame_size = ETHER_MAX_LEN;
1251                 break;
1252         default:
1253                 if (adapter->hw.mac.type >= igb_mac_min)
1254                         max_frame_size = 9234;
1255                 else /* lem */
1256                         max_frame_size = MAX_JUMBO_FRAME_SIZE;
1257         }
1258         if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1259                 return (EINVAL);
1260         }
1261
1262         scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
1263             mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1264         return (0);
1265 }
1266
1267 /*********************************************************************
1268  *  Init entry point
1269  *
1270  *  This routine is used in two ways. It is used by the stack as
1271  *  init entry point in network interface structure. It is also used
1272  *  by the driver as a hw/sw initialization routine to get to a
1273  *  consistent state.
1274  *
1275  **********************************************************************/
1276 static void
1277 em_if_init(if_ctx_t ctx)
1278 {
1279         struct adapter *adapter = iflib_get_softc(ctx);
1280         if_softc_ctx_t scctx = adapter->shared;
1281         struct ifnet *ifp = iflib_get_ifp(ctx);
1282         struct em_tx_queue *tx_que;
1283         int i;
1284
1285         INIT_DEBUGOUT("em_if_init: begin");
1286
1287         /* Get the latest mac address, User can use a LAA */
1288         bcopy(if_getlladdr(ifp), adapter->hw.mac.addr,
1289             ETHER_ADDR_LEN);
1290
1291         /* Put the address into the Receive Address Array */
1292         e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1293
1294         /*
1295          * With the 82571 adapter, RAR[0] may be overwritten
1296          * when the other port is reset, we make a duplicate
1297          * in RAR[14] for that eventuality, this assures
1298          * the interface continues to function.
1299          */
1300         if (adapter->hw.mac.type == e1000_82571) {
1301                 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1302                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1303                     E1000_RAR_ENTRIES - 1);
1304         }
1305
1306
1307         /* Initialize the hardware */
1308         em_reset(ctx);
1309         em_if_update_admin_status(ctx);
1310
1311         for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) {
1312                 struct tx_ring *txr = &tx_que->txr;
1313
1314                 txr->tx_rs_cidx = txr->tx_rs_pidx;
1315
1316                 /* Initialize the last processed descriptor to be the end of
1317                  * the ring, rather than the start, so that we avoid an
1318                  * off-by-one error when calculating how many descriptors are
1319                  * done in the credits_update function.
1320                  */
1321                 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
1322         }
1323
1324         /* Setup VLAN support, basic and offload if available */
1325         E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1326
1327         /* Clear bad data from Rx FIFOs */
1328         if (adapter->hw.mac.type >= igb_mac_min)
1329                 e1000_rx_fifo_flush_82575(&adapter->hw);
1330
1331         /* Configure for OS presence */
1332         em_init_manageability(adapter);
1333
1334         /* Prepare transmit descriptors and buffers */
1335         em_initialize_transmit_unit(ctx);
1336
1337         /* Setup Multicast table */
1338         em_if_multi_set(ctx);
1339
1340         adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx);
1341         em_initialize_receive_unit(ctx);
1342
1343         /* Use real VLAN Filter support? */
1344         if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1345                 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
1346                         /* Use real VLAN Filter support */
1347                         em_setup_vlan_hw_support(adapter);
1348                 else {
1349                         u32 ctrl;
1350                         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1351                         ctrl |= E1000_CTRL_VME;
1352                         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1353                 }
1354         } else {
1355                 u32 ctrl;
1356                 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1357                 ctrl &= ~E1000_CTRL_VME;
1358                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1359         }
1360
1361         /* Don't lose promiscuous settings */
1362         em_if_set_promisc(ctx, if_getflags(ifp));
1363         e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1364
1365         /* MSI-X configuration for 82574 */
1366         if (adapter->hw.mac.type == e1000_82574) {
1367                 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1368
1369                 tmp |= E1000_CTRL_EXT_PBA_CLR;
1370                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1371                 /* Set the IVAR - interrupt vector routing. */
1372                 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars);
1373         } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1374                 igb_configure_queues(adapter);
1375
1376         /* this clears any pending interrupts */
1377         E1000_READ_REG(&adapter->hw, E1000_ICR);
1378         E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC);
1379
1380         /* AMT based hardware can now take control from firmware */
1381         if (adapter->has_manage && adapter->has_amt)
1382                 em_get_hw_control(adapter);
1383
1384         /* Set Energy Efficient Ethernet */
1385         if (adapter->hw.mac.type >= igb_mac_min &&
1386             adapter->hw.phy.media_type == e1000_media_type_copper) {
1387                 if (adapter->hw.mac.type == e1000_i354)
1388                         e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
1389                 else
1390                         e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
1391         }
1392 }
1393
1394 /*********************************************************************
1395  *
1396  *  Fast Legacy/MSI Combined Interrupt Service routine
1397  *
1398  *********************************************************************/
1399 int
1400 em_intr(void *arg)
1401 {
1402         struct adapter *adapter = arg;
1403         if_ctx_t ctx = adapter->ctx;
1404         u32 reg_icr;
1405
1406         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1407
1408         /* Hot eject? */
1409         if (reg_icr == 0xffffffff)
1410                 return FILTER_STRAY;
1411
1412         /* Definitely not our interrupt. */
1413         if (reg_icr == 0x0)
1414                 return FILTER_STRAY;
1415
1416         /*
1417          * Starting with the 82571 chip, bit 31 should be used to
1418          * determine whether the interrupt belongs to us.
1419          */
1420         if (adapter->hw.mac.type >= e1000_82571 &&
1421             (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1422                 return FILTER_STRAY;
1423
1424         /*
1425          * Only MSI-X interrupts have one-shot behavior by taking advantage
1426          * of the EIAC register.  Thus, explicitly disable interrupts.  This
1427          * also works around the MSI message reordering errata on certain
1428          * systems.
1429          */
1430         IFDI_INTR_DISABLE(ctx);
1431
1432         /* Link status change */
1433         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))
1434                 em_handle_link(ctx);
1435
1436         if (reg_icr & E1000_ICR_RXO)
1437                 adapter->rx_overruns++;
1438
1439         return (FILTER_SCHEDULE_THREAD);
1440 }
1441
1442 static int
1443 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1444 {
1445         struct adapter *adapter = iflib_get_softc(ctx);
1446         struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1447
1448         E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims);
1449         return (0);
1450 }
1451
1452 static int
1453 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1454 {
1455         struct adapter *adapter = iflib_get_softc(ctx);
1456         struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1457
1458         E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims);
1459         return (0);
1460 }
1461
1462 static int
1463 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1464 {
1465         struct adapter *adapter = iflib_get_softc(ctx);
1466         struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1467
1468         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims);
1469         return (0);
1470 }
1471
1472 static int
1473 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1474 {
1475         struct adapter *adapter = iflib_get_softc(ctx);
1476         struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1477
1478         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims);
1479         return (0);
1480 }
1481
1482 /*********************************************************************
1483  *
1484  *  MSI-X RX Interrupt Service routine
1485  *
1486  **********************************************************************/
1487 static int
1488 em_msix_que(void *arg)
1489 {
1490         struct em_rx_queue *que = arg;
1491
1492         ++que->irqs;
1493
1494         return (FILTER_SCHEDULE_THREAD);
1495 }
1496
1497 /*********************************************************************
1498  *
1499  *  MSI-X Link Fast Interrupt Service routine
1500  *
1501  **********************************************************************/
1502 static int
1503 em_msix_link(void *arg)
1504 {
1505         struct adapter *adapter = arg;
1506         u32 reg_icr;
1507
1508         ++adapter->link_irq;
1509         MPASS(adapter->hw.back != NULL);
1510         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1511
1512         if (reg_icr & E1000_ICR_RXO)
1513                 adapter->rx_overruns++;
1514
1515         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1516                 em_handle_link(adapter->ctx);
1517         } else if (adapter->hw.mac.type == e1000_82574) {
1518                 /* Only re-arm 82574 if em_if_update_admin_status() won't. */
1519                 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK |
1520                     E1000_IMS_LSC);
1521         }
1522
1523         if (adapter->hw.mac.type == e1000_82574) {
1524                 /*
1525                  * Because we must read the ICR for this interrupt it may
1526                  * clear other causes using autoclear, for this reason we
1527                  * simply create a soft interrupt for all these vectors.
1528                  */
1529                 if (reg_icr)
1530                         E1000_WRITE_REG(&adapter->hw, E1000_ICS, adapter->ims);
1531         } else {
1532                 /* Re-arm unconditionally */
1533                 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC);
1534                 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1535         }
1536
1537         return (FILTER_HANDLED);
1538 }
1539
1540 static void
1541 em_handle_link(void *context)
1542 {
1543         if_ctx_t ctx = context;
1544         struct adapter *adapter = iflib_get_softc(ctx);
1545
1546         adapter->hw.mac.get_link_status = 1;
1547         iflib_admin_intr_deferred(ctx);
1548 }
1549
1550 /*********************************************************************
1551  *
1552  *  Media Ioctl callback
1553  *
1554  *  This routine is called whenever the user queries the status of
1555  *  the interface using ifconfig.
1556  *
1557  **********************************************************************/
1558 static void
1559 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1560 {
1561         struct adapter *adapter = iflib_get_softc(ctx);
1562         u_char fiber_type = IFM_1000_SX;
1563
1564         INIT_DEBUGOUT("em_if_media_status: begin");
1565
1566         iflib_admin_intr_deferred(ctx);
1567
1568         ifmr->ifm_status = IFM_AVALID;
1569         ifmr->ifm_active = IFM_ETHER;
1570
1571         if (!adapter->link_active) {
1572                 return;
1573         }
1574
1575         ifmr->ifm_status |= IFM_ACTIVE;
1576
1577         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
1578             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1579                 if (adapter->hw.mac.type == e1000_82545)
1580                         fiber_type = IFM_1000_LX;
1581                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1582         } else {
1583                 switch (adapter->link_speed) {
1584                 case 10:
1585                         ifmr->ifm_active |= IFM_10_T;
1586                         break;
1587                 case 100:
1588                         ifmr->ifm_active |= IFM_100_TX;
1589                         break;
1590                 case 1000:
1591                         ifmr->ifm_active |= IFM_1000_T;
1592                         break;
1593                 }
1594                 if (adapter->link_duplex == FULL_DUPLEX)
1595                         ifmr->ifm_active |= IFM_FDX;
1596                 else
1597                         ifmr->ifm_active |= IFM_HDX;
1598         }
1599 }
1600
1601 /*********************************************************************
1602  *
1603  *  Media Ioctl callback
1604  *
1605  *  This routine is called when the user changes speed/duplex using
1606  *  media/mediopt option with ifconfig.
1607  *
1608  **********************************************************************/
1609 static int
1610 em_if_media_change(if_ctx_t ctx)
1611 {
1612         struct adapter *adapter = iflib_get_softc(ctx);
1613         struct ifmedia *ifm = iflib_get_media(ctx);
1614
1615         INIT_DEBUGOUT("em_if_media_change: begin");
1616
1617         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1618                 return (EINVAL);
1619
1620         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1621         case IFM_AUTO:
1622                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1623                 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1624                 break;
1625         case IFM_1000_LX:
1626         case IFM_1000_SX:
1627         case IFM_1000_T:
1628                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1629                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1630                 break;
1631         case IFM_100_TX:
1632                 adapter->hw.mac.autoneg = FALSE;
1633                 adapter->hw.phy.autoneg_advertised = 0;
1634                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1635                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1636                 else
1637                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1638                 break;
1639         case IFM_10_T:
1640                 adapter->hw.mac.autoneg = FALSE;
1641                 adapter->hw.phy.autoneg_advertised = 0;
1642                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1643                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1644                 else
1645                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1646                 break;
1647         default:
1648                 device_printf(adapter->dev, "Unsupported media type\n");
1649         }
1650
1651         em_if_init(ctx);
1652
1653         return (0);
1654 }
1655
1656 static int
1657 em_if_set_promisc(if_ctx_t ctx, int flags)
1658 {
1659         struct adapter *adapter = iflib_get_softc(ctx);
1660         struct ifnet *ifp = iflib_get_ifp(ctx);
1661         u32 reg_rctl;
1662         int mcnt = 0;
1663
1664         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1665         reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE);
1666         if (flags & IFF_ALLMULTI)
1667                 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1668         else
1669                 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES);
1670
1671         if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1672                 reg_rctl &= (~E1000_RCTL_MPE);
1673         E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1674
1675         if (flags & IFF_PROMISC) {
1676                 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1677                 /* Turn this on if you want to see bad packets */
1678                 if (em_debug_sbp)
1679                         reg_rctl |= E1000_RCTL_SBP;
1680                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1681         } else if (flags & IFF_ALLMULTI) {
1682                 reg_rctl |= E1000_RCTL_MPE;
1683                 reg_rctl &= ~E1000_RCTL_UPE;
1684                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1685         }
1686         return (0);
1687 }
1688
1689 static u_int
1690 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx)
1691 {
1692         u8 *mta = arg;
1693
1694         if (idx == MAX_NUM_MULTICAST_ADDRESSES)
1695                 return (0);
1696
1697         bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1698
1699         return (1);
1700 }
1701
1702 /*********************************************************************
1703  *  Multicast Update
1704  *
1705  *  This routine is called whenever multicast address list is updated.
1706  *
1707  **********************************************************************/
1708 static void
1709 em_if_multi_set(if_ctx_t ctx)
1710 {
1711         struct adapter *adapter = iflib_get_softc(ctx);
1712         struct ifnet *ifp = iflib_get_ifp(ctx);
1713         u8  *mta; /* Multicast array memory */
1714         u32 reg_rctl = 0;
1715         int mcnt = 0;
1716
1717         IOCTL_DEBUGOUT("em_set_multi: begin");
1718
1719         mta = adapter->mta;
1720         bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1721
1722         if (adapter->hw.mac.type == e1000_82542 &&
1723             adapter->hw.revision_id == E1000_REVISION_2) {
1724                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1725                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1726                         e1000_pci_clear_mwi(&adapter->hw);
1727                 reg_rctl |= E1000_RCTL_RST;
1728                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1729                 msec_delay(5);
1730         }
1731
1732         mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta);
1733
1734         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1735
1736         if (if_getflags(ifp) & IFF_PROMISC)
1737                 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1738         else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES ||
1739             if_getflags(ifp) & IFF_ALLMULTI) {
1740                 reg_rctl |= E1000_RCTL_MPE;
1741                 reg_rctl &= ~E1000_RCTL_UPE;
1742         } else
1743                 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
1744
1745         E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1746
1747         if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1748                 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
1749
1750         if (adapter->hw.mac.type == e1000_82542 &&
1751             adapter->hw.revision_id == E1000_REVISION_2) {
1752                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1753                 reg_rctl &= ~E1000_RCTL_RST;
1754                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1755                 msec_delay(5);
1756                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1757                         e1000_pci_set_mwi(&adapter->hw);
1758         }
1759 }
1760
1761 /*********************************************************************
1762  *  Timer routine
1763  *
1764  *  This routine schedules em_if_update_admin_status() to check for
1765  *  link status and to gather statistics as well as to perform some
1766  *  controller-specific hardware patting.
1767  *
1768  **********************************************************************/
1769 static void
1770 em_if_timer(if_ctx_t ctx, uint16_t qid)
1771 {
1772
1773         if (qid != 0)
1774                 return;
1775
1776         iflib_admin_intr_deferred(ctx);
1777 }
1778
1779 static void
1780 em_if_update_admin_status(if_ctx_t ctx)
1781 {
1782         struct adapter *adapter = iflib_get_softc(ctx);
1783         struct e1000_hw *hw = &adapter->hw;
1784         device_t dev = iflib_get_dev(ctx);
1785         u32 link_check, thstat, ctrl;
1786
1787         link_check = thstat = ctrl = 0;
1788         /* Get the cached link value or read phy for real */
1789         switch (hw->phy.media_type) {
1790         case e1000_media_type_copper:
1791                 if (hw->mac.get_link_status) {
1792                         if (hw->mac.type == e1000_pch_spt)
1793                                 msec_delay(50);
1794                         /* Do the work to read phy */
1795                         e1000_check_for_link(hw);
1796                         link_check = !hw->mac.get_link_status;
1797                         if (link_check) /* ESB2 fix */
1798                                 e1000_cfg_on_link_up(hw);
1799                 } else {
1800                         link_check = TRUE;
1801                 }
1802                 break;
1803         case e1000_media_type_fiber:
1804                 e1000_check_for_link(hw);
1805                 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1806                             E1000_STATUS_LU);
1807                 break;
1808         case e1000_media_type_internal_serdes:
1809                 e1000_check_for_link(hw);
1810                 link_check = hw->mac.serdes_has_link;
1811                 break;
1812         /* VF device is type_unknown */
1813         case e1000_media_type_unknown:
1814                 e1000_check_for_link(hw);
1815                 link_check = !hw->mac.get_link_status;
1816                 /* FALLTHROUGH */
1817         default:
1818                 break;
1819         }
1820
1821         /* Check for thermal downshift or shutdown */
1822         if (hw->mac.type == e1000_i350) {
1823                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1824                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1825         }
1826
1827         /* Now check for a transition */
1828         if (link_check && (adapter->link_active == 0)) {
1829                 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
1830                     &adapter->link_duplex);
1831                 /* Check if we must disable SPEED_MODE bit on PCI-E */
1832                 if ((adapter->link_speed != SPEED_1000) &&
1833                     ((hw->mac.type == e1000_82571) ||
1834                     (hw->mac.type == e1000_82572))) {
1835                         int tarc0;
1836                         tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1837                         tarc0 &= ~TARC_SPEED_MODE_BIT;
1838                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1839                 }
1840                 if (bootverbose)
1841                         device_printf(dev, "Link is up %d Mbps %s\n",
1842                             adapter->link_speed,
1843                             ((adapter->link_duplex == FULL_DUPLEX) ?
1844                             "Full Duplex" : "Half Duplex"));
1845                 adapter->link_active = 1;
1846                 adapter->smartspeed = 0;
1847                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) ==
1848                     E1000_CTRL_EXT_LINK_MODE_GMII &&
1849                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1850                         device_printf(dev, "Link: thermal downshift\n");
1851                 /* Delay Link Up for Phy update */
1852                 if (((hw->mac.type == e1000_i210) ||
1853                     (hw->mac.type == e1000_i211)) &&
1854                     (hw->phy.id == I210_I_PHY_ID))
1855                         msec_delay(I210_LINK_DELAY);
1856                 /* Reset if the media type changed. */
1857                 if (hw->dev_spec._82575.media_changed &&
1858                     hw->mac.type >= igb_mac_min) {
1859                         hw->dev_spec._82575.media_changed = false;
1860                         adapter->flags |= IGB_MEDIA_RESET;
1861                         em_reset(ctx);
1862                 }
1863                 iflib_link_state_change(ctx, LINK_STATE_UP,
1864                     IF_Mbps(adapter->link_speed));
1865         } else if (!link_check && (adapter->link_active == 1)) {
1866                 adapter->link_speed = 0;
1867                 adapter->link_duplex = 0;
1868                 adapter->link_active = 0;
1869                 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
1870         }
1871         em_update_stats_counters(adapter);
1872
1873         /* Reset LAA into RAR[0] on 82571 */
1874         if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw))
1875                 e1000_rar_set(hw, hw->mac.addr, 0);
1876
1877         if (hw->mac.type < em_mac_min)
1878                 lem_smartspeed(adapter);
1879         else if (hw->mac.type == e1000_82574 &&
1880             adapter->intr_type == IFLIB_INTR_MSIX)
1881                 E1000_WRITE_REG(hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC);
1882 }
1883
1884 static void
1885 em_if_watchdog_reset(if_ctx_t ctx)
1886 {
1887         struct adapter *adapter = iflib_get_softc(ctx);
1888
1889         /*
1890          * Just count the event; iflib(4) will already trigger a
1891          * sufficient reset of the controller.
1892          */
1893         adapter->watchdog_events++;
1894 }
1895
1896 /*********************************************************************
1897  *
1898  *  This routine disables all traffic on the adapter by issuing a
1899  *  global reset on the MAC.
1900  *
1901  **********************************************************************/
1902 static void
1903 em_if_stop(if_ctx_t ctx)
1904 {
1905         struct adapter *adapter = iflib_get_softc(ctx);
1906
1907         INIT_DEBUGOUT("em_if_stop: begin");
1908
1909         e1000_reset_hw(&adapter->hw);
1910         if (adapter->hw.mac.type >= e1000_82544)
1911                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0);
1912
1913         e1000_led_off(&adapter->hw);
1914         e1000_cleanup_led(&adapter->hw);
1915 }
1916
1917 /*********************************************************************
1918  *
1919  *  Determine hardware revision.
1920  *
1921  **********************************************************************/
1922 static void
1923 em_identify_hardware(if_ctx_t ctx)
1924 {
1925         device_t dev = iflib_get_dev(ctx);
1926         struct adapter *adapter = iflib_get_softc(ctx);
1927
1928         /* Make sure our PCI config space has the necessary stuff set */
1929         adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1930
1931         /* Save off the information about this board */
1932         adapter->hw.vendor_id = pci_get_vendor(dev);
1933         adapter->hw.device_id = pci_get_device(dev);
1934         adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1935         adapter->hw.subsystem_vendor_id =
1936             pci_read_config(dev, PCIR_SUBVEND_0, 2);
1937         adapter->hw.subsystem_device_id =
1938             pci_read_config(dev, PCIR_SUBDEV_0, 2);
1939
1940         /* Do Shared Code Init and Setup */
1941         if (e1000_set_mac_type(&adapter->hw)) {
1942                 device_printf(dev, "Setup init failure\n");
1943                 return;
1944         }
1945
1946         /* Are we a VF device? */
1947         if ((adapter->hw.mac.type == e1000_vfadapt) ||
1948             (adapter->hw.mac.type == e1000_vfadapt_i350))
1949                 adapter->vf_ifp = 1;
1950         else
1951                 adapter->vf_ifp = 0;
1952 }
1953
1954 static int
1955 em_allocate_pci_resources(if_ctx_t ctx)
1956 {
1957         struct adapter *adapter = iflib_get_softc(ctx);
1958         device_t dev = iflib_get_dev(ctx);
1959         int rid, val;
1960
1961         rid = PCIR_BAR(0);
1962         adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1963             &rid, RF_ACTIVE);
1964         if (adapter->memory == NULL) {
1965                 device_printf(dev, "Unable to allocate bus resource: memory\n");
1966                 return (ENXIO);
1967         }
1968         adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory);
1969         adapter->osdep.mem_bus_space_handle =
1970             rman_get_bushandle(adapter->memory);
1971         adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle;
1972
1973         /* Only older adapters use IO mapping */
1974         if (adapter->hw.mac.type < em_mac_min &&
1975             adapter->hw.mac.type > e1000_82543) {
1976                 /* Figure our where our IO BAR is ? */
1977                 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1978                         val = pci_read_config(dev, rid, 4);
1979                         if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1980                                 break;
1981                         }
1982                         rid += 4;
1983                         /* check for 64bit BAR */
1984                         if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1985                                 rid += 4;
1986                 }
1987                 if (rid >= PCIR_CIS) {
1988                         device_printf(dev, "Unable to locate IO BAR\n");
1989                         return (ENXIO);
1990                 }
1991                 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
1992                     &rid, RF_ACTIVE);
1993                 if (adapter->ioport == NULL) {
1994                         device_printf(dev, "Unable to allocate bus resource: "
1995                             "ioport\n");
1996                         return (ENXIO);
1997                 }
1998                 adapter->hw.io_base = 0;
1999                 adapter->osdep.io_bus_space_tag =
2000                     rman_get_bustag(adapter->ioport);
2001                 adapter->osdep.io_bus_space_handle =
2002                     rman_get_bushandle(adapter->ioport);
2003         }
2004
2005         adapter->hw.back = &adapter->osdep;
2006
2007         return (0);
2008 }
2009
2010 /*********************************************************************
2011  *
2012  *  Set up the MSI-X Interrupt handlers
2013  *
2014  **********************************************************************/
2015 static int
2016 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
2017 {
2018         struct adapter *adapter = iflib_get_softc(ctx);
2019         struct em_rx_queue *rx_que = adapter->rx_queues;
2020         struct em_tx_queue *tx_que = adapter->tx_queues;
2021         int error, rid, i, vector = 0, rx_vectors;
2022         char buf[16];
2023
2024         /* First set up ring resources */
2025         for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) {
2026                 rid = vector + 1;
2027                 snprintf(buf, sizeof(buf), "rxq%d", i);
2028                 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
2029                 if (error) {
2030                         device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
2031                         adapter->rx_num_queues = i + 1;
2032                         goto fail;
2033                 }
2034
2035                 rx_que->msix =  vector;
2036
2037                 /*
2038                  * Set the bit to enable interrupt
2039                  * in E1000_IMS -- bits 20 and 21
2040                  * are for RX0 and RX1, note this has
2041                  * NOTHING to do with the MSI-X vector
2042                  */
2043                 if (adapter->hw.mac.type == e1000_82574) {
2044                         rx_que->eims = 1 << (20 + i);
2045                         adapter->ims |= rx_que->eims;
2046                         adapter->ivars |= (8 | rx_que->msix) << (i * 4);
2047                 } else if (adapter->hw.mac.type == e1000_82575)
2048                         rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
2049                 else
2050                         rx_que->eims = 1 << vector;
2051         }
2052         rx_vectors = vector;
2053
2054         vector = 0;
2055         for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) {
2056                 snprintf(buf, sizeof(buf), "txq%d", i);
2057                 tx_que = &adapter->tx_queues[i];
2058                 iflib_softirq_alloc_generic(ctx,
2059                     &adapter->rx_queues[i % adapter->rx_num_queues].que_irq,
2060                     IFLIB_INTR_TX, tx_que, tx_que->me, buf);
2061
2062                 tx_que->msix = (vector % adapter->rx_num_queues);
2063
2064                 /*
2065                  * Set the bit to enable interrupt
2066                  * in E1000_IMS -- bits 22 and 23
2067                  * are for TX0 and TX1, note this has
2068                  * NOTHING to do with the MSI-X vector
2069                  */
2070                 if (adapter->hw.mac.type == e1000_82574) {
2071                         tx_que->eims = 1 << (22 + i);
2072                         adapter->ims |= tx_que->eims;
2073                         adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
2074                 } else if (adapter->hw.mac.type == e1000_82575) {
2075                         tx_que->eims = E1000_EICR_TX_QUEUE0 << i;
2076                 } else {
2077                         tx_que->eims = 1 << i;
2078                 }
2079         }
2080
2081         /* Link interrupt */
2082         rid = rx_vectors + 1;
2083         error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq");
2084
2085         if (error) {
2086                 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
2087                 goto fail;
2088         }
2089         adapter->linkvec = rx_vectors;
2090         if (adapter->hw.mac.type < igb_mac_min) {
2091                 adapter->ivars |=  (8 | rx_vectors) << 16;
2092                 adapter->ivars |= 0x80000000;
2093         }
2094         return (0);
2095 fail:
2096         iflib_irq_free(ctx, &adapter->irq);
2097         rx_que = adapter->rx_queues;
2098         for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++)
2099                 iflib_irq_free(ctx, &rx_que->que_irq);
2100         return (error);
2101 }
2102
2103 static void
2104 igb_configure_queues(struct adapter *adapter)
2105 {
2106         struct e1000_hw *hw = &adapter->hw;
2107         struct em_rx_queue *rx_que;
2108         struct em_tx_queue *tx_que;
2109         u32 tmp, ivar = 0, newitr = 0;
2110
2111         /* First turn on RSS capability */
2112         if (hw->mac.type != e1000_82575)
2113                 E1000_WRITE_REG(hw, E1000_GPIE,
2114                     E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
2115                     E1000_GPIE_PBA | E1000_GPIE_NSICR);
2116
2117         /* Turn on MSI-X */
2118         switch (hw->mac.type) {
2119         case e1000_82580:
2120         case e1000_i350:
2121         case e1000_i354:
2122         case e1000_i210:
2123         case e1000_i211:
2124         case e1000_vfadapt:
2125         case e1000_vfadapt_i350:
2126                 /* RX entries */
2127                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2128                         u32 index = i >> 1;
2129                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2130                         rx_que = &adapter->rx_queues[i];
2131                         if (i & 1) {
2132                                 ivar &= 0xFF00FFFF;
2133                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2134                         } else {
2135                                 ivar &= 0xFFFFFF00;
2136                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2137                         }
2138                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2139                 }
2140                 /* TX entries */
2141                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2142                         u32 index = i >> 1;
2143                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2144                         tx_que = &adapter->tx_queues[i];
2145                         if (i & 1) {
2146                                 ivar &= 0x00FFFFFF;
2147                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2148                         } else {
2149                                 ivar &= 0xFFFF00FF;
2150                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2151                         }
2152                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2153                         adapter->que_mask |= tx_que->eims;
2154                 }
2155
2156                 /* And for the link interrupt */
2157                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2158                 adapter->link_mask = 1 << adapter->linkvec;
2159                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2160                 break;
2161         case e1000_82576:
2162                 /* RX entries */
2163                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2164                         u32 index = i & 0x7; /* Each IVAR has two entries */
2165                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2166                         rx_que = &adapter->rx_queues[i];
2167                         if (i < 8) {
2168                                 ivar &= 0xFFFFFF00;
2169                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2170                         } else {
2171                                 ivar &= 0xFF00FFFF;
2172                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2173                         }
2174                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2175                         adapter->que_mask |= rx_que->eims;
2176                 }
2177                 /* TX entries */
2178                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2179                         u32 index = i & 0x7; /* Each IVAR has two entries */
2180                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2181                         tx_que = &adapter->tx_queues[i];
2182                         if (i < 8) {
2183                                 ivar &= 0xFFFF00FF;
2184                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2185                         } else {
2186                                 ivar &= 0x00FFFFFF;
2187                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2188                         }
2189                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2190                         adapter->que_mask |= tx_que->eims;
2191                 }
2192
2193                 /* And for the link interrupt */
2194                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2195                 adapter->link_mask = 1 << adapter->linkvec;
2196                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2197                 break;
2198
2199         case e1000_82575:
2200                 /* enable MSI-X support*/
2201                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2202                 tmp |= E1000_CTRL_EXT_PBA_CLR;
2203                 /* Auto-Mask interrupts upon ICR read. */
2204                 tmp |= E1000_CTRL_EXT_EIAME;
2205                 tmp |= E1000_CTRL_EXT_IRCA;
2206                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2207
2208                 /* Queues */
2209                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2210                         rx_que = &adapter->rx_queues[i];
2211                         tmp = E1000_EICR_RX_QUEUE0 << i;
2212                         tmp |= E1000_EICR_TX_QUEUE0 << i;
2213                         rx_que->eims = tmp;
2214                         E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2215                             i, rx_que->eims);
2216                         adapter->que_mask |= rx_que->eims;
2217                 }
2218
2219                 /* Link */
2220                 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec),
2221                     E1000_EIMS_OTHER);
2222                 adapter->link_mask |= E1000_EIMS_OTHER;
2223         default:
2224                 break;
2225         }
2226
2227         /* Set the starting interrupt rate */
2228         if (em_max_interrupt_rate > 0)
2229                 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2230
2231         if (hw->mac.type == e1000_82575)
2232                 newitr |= newitr << 16;
2233         else
2234                 newitr |= E1000_EITR_CNT_IGNR;
2235
2236         for (int i = 0; i < adapter->rx_num_queues; i++) {
2237                 rx_que = &adapter->rx_queues[i];
2238                 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2239         }
2240
2241         return;
2242 }
2243
2244 static void
2245 em_free_pci_resources(if_ctx_t ctx)
2246 {
2247         struct adapter *adapter = iflib_get_softc(ctx);
2248         struct em_rx_queue *que = adapter->rx_queues;
2249         device_t dev = iflib_get_dev(ctx);
2250
2251         /* Release all MSI-X queue resources */
2252         if (adapter->intr_type == IFLIB_INTR_MSIX)
2253                 iflib_irq_free(ctx, &adapter->irq);
2254
2255         if (que != NULL) {
2256                 for (int i = 0; i < adapter->rx_num_queues; i++, que++) {
2257                         iflib_irq_free(ctx, &que->que_irq);
2258                 }
2259         }
2260
2261         if (adapter->memory != NULL) {
2262                 bus_release_resource(dev, SYS_RES_MEMORY,
2263                     rman_get_rid(adapter->memory), adapter->memory);
2264                 adapter->memory = NULL;
2265         }
2266
2267         if (adapter->flash != NULL) {
2268                 bus_release_resource(dev, SYS_RES_MEMORY,
2269                     rman_get_rid(adapter->flash), adapter->flash);
2270                 adapter->flash = NULL;
2271         }
2272
2273         if (adapter->ioport != NULL) {
2274                 bus_release_resource(dev, SYS_RES_IOPORT,
2275                     rman_get_rid(adapter->ioport), adapter->ioport);
2276                 adapter->ioport = NULL;
2277         }
2278 }
2279
2280 /* Set up MSI or MSI-X */
2281 static int
2282 em_setup_msix(if_ctx_t ctx)
2283 {
2284         struct adapter *adapter = iflib_get_softc(ctx);
2285
2286         if (adapter->hw.mac.type == e1000_82574) {
2287                 em_enable_vectors_82574(ctx);
2288         }
2289         return (0);
2290 }
2291
2292 /*********************************************************************
2293  *
2294  *  Workaround for SmartSpeed on 82541 and 82547 controllers
2295  *
2296  **********************************************************************/
2297 static void
2298 lem_smartspeed(struct adapter *adapter)
2299 {
2300         u16 phy_tmp;
2301
2302         if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) ||
2303             adapter->hw.mac.autoneg == 0 ||
2304             (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2305                 return;
2306
2307         if (adapter->smartspeed == 0) {
2308                 /* If Master/Slave config fault is asserted twice,
2309                  * we assume back-to-back */
2310                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2311                 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2312                         return;
2313                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2314                 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2315                         e1000_read_phy_reg(&adapter->hw,
2316                             PHY_1000T_CTRL, &phy_tmp);
2317                         if(phy_tmp & CR_1000T_MS_ENABLE) {
2318                                 phy_tmp &= ~CR_1000T_MS_ENABLE;
2319                                 e1000_write_phy_reg(&adapter->hw,
2320                                     PHY_1000T_CTRL, phy_tmp);
2321                                 adapter->smartspeed++;
2322                                 if(adapter->hw.mac.autoneg &&
2323                                    !e1000_copper_link_autoneg(&adapter->hw) &&
2324                                    !e1000_read_phy_reg(&adapter->hw,
2325                                     PHY_CONTROL, &phy_tmp)) {
2326                                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2327                                                     MII_CR_RESTART_AUTO_NEG);
2328                                         e1000_write_phy_reg(&adapter->hw,
2329                                             PHY_CONTROL, phy_tmp);
2330                                 }
2331                         }
2332                 }
2333                 return;
2334         } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2335                 /* If still no link, perhaps using 2/3 pair cable */
2336                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2337                 phy_tmp |= CR_1000T_MS_ENABLE;
2338                 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2339                 if(adapter->hw.mac.autoneg &&
2340                    !e1000_copper_link_autoneg(&adapter->hw) &&
2341                    !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2342                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2343                                     MII_CR_RESTART_AUTO_NEG);
2344                         e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2345                 }
2346         }
2347         /* Restart process after EM_SMARTSPEED_MAX iterations */
2348         if(adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2349                 adapter->smartspeed = 0;
2350 }
2351
2352 /*********************************************************************
2353  *
2354  *  Initialize the DMA Coalescing feature
2355  *
2356  **********************************************************************/
2357 static void
2358 igb_init_dmac(struct adapter *adapter, u32 pba)
2359 {
2360         device_t        dev = adapter->dev;
2361         struct e1000_hw *hw = &adapter->hw;
2362         u32             dmac, reg = ~E1000_DMACR_DMAC_EN;
2363         u16             hwm;
2364         u16             max_frame_size;
2365
2366         if (hw->mac.type == e1000_i211)
2367                 return;
2368
2369         max_frame_size = adapter->shared->isc_max_frame_size;
2370         if (hw->mac.type > e1000_82580) {
2371
2372                 if (adapter->dmac == 0) { /* Disabling it */
2373                         E1000_WRITE_REG(hw, E1000_DMACR, reg);
2374                         return;
2375                 } else
2376                         device_printf(dev, "DMA Coalescing enabled\n");
2377
2378                 /* Set starting threshold */
2379                 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
2380
2381                 hwm = 64 * pba - max_frame_size / 16;
2382                 if (hwm < 64 * (pba - 6))
2383                         hwm = 64 * (pba - 6);
2384                 reg = E1000_READ_REG(hw, E1000_FCRTC);
2385                 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
2386                 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
2387                     & E1000_FCRTC_RTH_COAL_MASK);
2388                 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
2389
2390
2391                 dmac = pba - max_frame_size / 512;
2392                 if (dmac < pba - 10)
2393                         dmac = pba - 10;
2394                 reg = E1000_READ_REG(hw, E1000_DMACR);
2395                 reg &= ~E1000_DMACR_DMACTHR_MASK;
2396                 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT)
2397                     & E1000_DMACR_DMACTHR_MASK);
2398
2399                 /* transition to L0x or L1 if available..*/
2400                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
2401
2402                 /* Check if status is 2.5Gb backplane connection
2403                 * before configuration of watchdog timer, which is
2404                 * in msec values in 12.8usec intervals
2405                 * watchdog timer= msec values in 32usec intervals
2406                 * for non 2.5Gb connection
2407                 */
2408                 if (hw->mac.type == e1000_i354) {
2409                         int status = E1000_READ_REG(hw, E1000_STATUS);
2410                         if ((status & E1000_STATUS_2P5_SKU) &&
2411                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2412                                 reg |= ((adapter->dmac * 5) >> 6);
2413                         else
2414                                 reg |= (adapter->dmac >> 5);
2415                 } else {
2416                         reg |= (adapter->dmac >> 5);
2417                 }
2418
2419                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2420
2421                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
2422
2423                 /* Set the interval before transition */
2424                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
2425                 if (hw->mac.type == e1000_i350)
2426                         reg |= IGB_DMCTLX_DCFLUSH_DIS;
2427                 /*
2428                 ** in 2.5Gb connection, TTLX unit is 0.4 usec
2429                 ** which is 0x4*2 = 0xA. But delay is still 4 usec
2430                 */
2431                 if (hw->mac.type == e1000_i354) {
2432                         int status = E1000_READ_REG(hw, E1000_STATUS);
2433                         if ((status & E1000_STATUS_2P5_SKU) &&
2434                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2435                                 reg |= 0xA;
2436                         else
2437                                 reg |= 0x4;
2438                 } else {
2439                         reg |= 0x4;
2440                 }
2441
2442                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
2443
2444                 /* free space in tx packet buffer to wake from DMA coal */
2445                 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE -
2446                     (2 * max_frame_size)) >> 6);
2447
2448                 /* make low power state decision controlled by DMA coal */
2449                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2450                 reg &= ~E1000_PCIEMISC_LX_DECISION;
2451                 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
2452
2453         } else if (hw->mac.type == e1000_82580) {
2454                 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2455                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
2456                     reg & ~E1000_PCIEMISC_LX_DECISION);
2457                 E1000_WRITE_REG(hw, E1000_DMACR, 0);
2458         }
2459 }
2460
2461 /*********************************************************************
2462  *
2463  *  Initialize the hardware to a configuration as specified by the
2464  *  adapter structure.
2465  *
2466  **********************************************************************/
2467 static void
2468 em_reset(if_ctx_t ctx)
2469 {
2470         device_t dev = iflib_get_dev(ctx);
2471         struct adapter *adapter = iflib_get_softc(ctx);
2472         struct ifnet *ifp = iflib_get_ifp(ctx);
2473         struct e1000_hw *hw = &adapter->hw;
2474         u16 rx_buffer_size;
2475         u32 pba;
2476
2477         INIT_DEBUGOUT("em_reset: begin");
2478         /* Let the firmware know the OS is in control */
2479         em_get_hw_control(adapter);
2480
2481         /* Set up smart power down as default off on newer adapters. */
2482         if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2483             hw->mac.type == e1000_82572)) {
2484                 u16 phy_tmp = 0;
2485
2486                 /* Speed up time to link by disabling smart power down. */
2487                 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2488                 phy_tmp &= ~IGP02E1000_PM_SPD;
2489                 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2490         }
2491
2492         /*
2493          * Packet Buffer Allocation (PBA)
2494          * Writing PBA sets the receive portion of the buffer
2495          * the remainder is used for the transmit buffer.
2496          */
2497         switch (hw->mac.type) {
2498         /* 82547: Total Packet Buffer is 40K */
2499         case e1000_82547:
2500         case e1000_82547_rev_2:
2501                 if (hw->mac.max_frame_size > 8192)
2502                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
2503                 else
2504                         pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
2505                 break;
2506         /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */
2507         case e1000_82571:
2508         case e1000_82572:
2509         case e1000_80003es2lan:
2510                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2511                 break;
2512         /* 82573: Total Packet Buffer is 32K */
2513         case e1000_82573:
2514                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2515                 break;
2516         case e1000_82574:
2517         case e1000_82583:
2518                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2519                 break;
2520         case e1000_ich8lan:
2521                 pba = E1000_PBA_8K;
2522                 break;
2523         case e1000_ich9lan:
2524         case e1000_ich10lan:
2525                 /* Boost Receive side for jumbo frames */
2526                 if (hw->mac.max_frame_size > 4096)
2527                         pba = E1000_PBA_14K;
2528                 else
2529                         pba = E1000_PBA_10K;
2530                 break;
2531         case e1000_pchlan:
2532         case e1000_pch2lan:
2533         case e1000_pch_lpt:
2534         case e1000_pch_spt:
2535         case e1000_pch_cnp:
2536         case e1000_pch_tgp:
2537         case e1000_pch_adp:
2538         case e1000_pch_mtp:
2539                 pba = E1000_PBA_26K;
2540                 break;
2541         case e1000_82575:
2542                 pba = E1000_PBA_32K;
2543                 break;
2544         case e1000_82576:
2545         case e1000_vfadapt:
2546                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2547                 pba &= E1000_RXPBS_SIZE_MASK_82576;
2548                 break;
2549         case e1000_82580:
2550         case e1000_i350:
2551         case e1000_i354:
2552         case e1000_vfadapt_i350:
2553                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2554                 pba = e1000_rxpbs_adjust_82580(pba);
2555                 break;
2556         case e1000_i210:
2557         case e1000_i211:
2558                 pba = E1000_PBA_34K;
2559                 break;
2560         default:
2561                 /* Remaining devices assumed to have a Packet Buffer of 64K. */
2562                 if (hw->mac.max_frame_size > 8192)
2563                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2564                 else
2565                         pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2566         }
2567
2568         /* Special needs in case of Jumbo frames */
2569         if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) {
2570                 u32 tx_space, min_tx, min_rx;
2571                 pba = E1000_READ_REG(hw, E1000_PBA);
2572                 tx_space = pba >> 16;
2573                 pba &= 0xffff;
2574                 min_tx = (hw->mac.max_frame_size +
2575                     sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
2576                 min_tx = roundup2(min_tx, 1024);
2577                 min_tx >>= 10;
2578                 min_rx = hw->mac.max_frame_size;
2579                 min_rx = roundup2(min_rx, 1024);
2580                 min_rx >>= 10;
2581                 if (tx_space < min_tx &&
2582                     ((min_tx - tx_space) < pba)) {
2583                         pba = pba - (min_tx - tx_space);
2584                         /*
2585                          * if short on rx space, rx wins
2586                          * and must trump tx adjustment
2587                          */
2588                         if (pba < min_rx)
2589                                 pba = min_rx;
2590                 }
2591                 E1000_WRITE_REG(hw, E1000_PBA, pba);
2592         }
2593
2594         if (hw->mac.type < igb_mac_min)
2595                 E1000_WRITE_REG(hw, E1000_PBA, pba);
2596
2597         INIT_DEBUGOUT1("em_reset: pba=%dK",pba);
2598
2599         /*
2600          * These parameters control the automatic generation (Tx) and
2601          * response (Rx) to Ethernet PAUSE frames.
2602          * - High water mark should allow for at least two frames to be
2603          *   received after sending an XOFF.
2604          * - Low water mark works best when it is very near the high water mark.
2605          *   This allows the receiver to restart by sending XON when it has
2606          *   drained a bit. Here we use an arbitrary value of 1500 which will
2607          *   restart after one full frame is pulled from the buffer. There
2608          *   could be several smaller frames in the buffer and if so they will
2609          *   not trigger the XON until their total number reduces the buffer
2610          *   by 1500.
2611          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2612          */
2613         rx_buffer_size = (pba & 0xffff) << 10;
2614         hw->fc.high_water = rx_buffer_size -
2615             roundup2(hw->mac.max_frame_size, 1024);
2616         hw->fc.low_water = hw->fc.high_water - 1500;
2617
2618         if (adapter->fc) /* locally set flow control value? */
2619                 hw->fc.requested_mode = adapter->fc;
2620         else
2621                 hw->fc.requested_mode = e1000_fc_full;
2622
2623         if (hw->mac.type == e1000_80003es2lan)
2624                 hw->fc.pause_time = 0xFFFF;
2625         else
2626                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
2627
2628         hw->fc.send_xon = TRUE;
2629
2630         /* Device specific overrides/settings */
2631         switch (hw->mac.type) {
2632         case e1000_pchlan:
2633                 /* Workaround: no TX flow ctrl for PCH */
2634                 hw->fc.requested_mode = e1000_fc_rx_pause;
2635                 hw->fc.pause_time = 0xFFFF; /* override */
2636                 if (if_getmtu(ifp) > ETHERMTU) {
2637                         hw->fc.high_water = 0x3500;
2638                         hw->fc.low_water = 0x1500;
2639                 } else {
2640                         hw->fc.high_water = 0x5000;
2641                         hw->fc.low_water = 0x3000;
2642                 }
2643                 hw->fc.refresh_time = 0x1000;
2644                 break;
2645         case e1000_pch2lan:
2646         case e1000_pch_lpt:
2647         case e1000_pch_spt:
2648         case e1000_pch_cnp:
2649         case e1000_pch_tgp:
2650         case e1000_pch_adp:
2651         case e1000_pch_mtp:
2652                 hw->fc.high_water = 0x5C20;
2653                 hw->fc.low_water = 0x5048;
2654                 hw->fc.pause_time = 0x0650;
2655                 hw->fc.refresh_time = 0x0400;
2656                 /* Jumbos need adjusted PBA */
2657                 if (if_getmtu(ifp) > ETHERMTU)
2658                         E1000_WRITE_REG(hw, E1000_PBA, 12);
2659                 else
2660                         E1000_WRITE_REG(hw, E1000_PBA, 26);
2661                 break;
2662         case e1000_82575:
2663         case e1000_82576:
2664                 /* 8-byte granularity */
2665                 hw->fc.low_water = hw->fc.high_water - 8;
2666                 break;
2667         case e1000_82580:
2668         case e1000_i350:
2669         case e1000_i354:
2670         case e1000_i210:
2671         case e1000_i211:
2672         case e1000_vfadapt:
2673         case e1000_vfadapt_i350:
2674                 /* 16-byte granularity */
2675                 hw->fc.low_water = hw->fc.high_water - 16;
2676                 break;
2677         case e1000_ich9lan:
2678         case e1000_ich10lan:
2679                 if (if_getmtu(ifp) > ETHERMTU) {
2680                         hw->fc.high_water = 0x2800;
2681                         hw->fc.low_water = hw->fc.high_water - 8;
2682                         break;
2683                 }
2684                 /* FALLTHROUGH */
2685         default:
2686                 if (hw->mac.type == e1000_80003es2lan)
2687                         hw->fc.pause_time = 0xFFFF;
2688                 break;
2689         }
2690
2691         /* Issue a global reset */
2692         e1000_reset_hw(hw);
2693         if (hw->mac.type >= igb_mac_min) {
2694                 E1000_WRITE_REG(hw, E1000_WUC, 0);
2695         } else {
2696                 E1000_WRITE_REG(hw, E1000_WUFC, 0);
2697                 em_disable_aspm(adapter);
2698         }
2699         if (adapter->flags & IGB_MEDIA_RESET) {
2700                 e1000_setup_init_funcs(hw, TRUE);
2701                 e1000_get_bus_info(hw);
2702                 adapter->flags &= ~IGB_MEDIA_RESET;
2703         }
2704         /* and a re-init */
2705         if (e1000_init_hw(hw) < 0) {
2706                 device_printf(dev, "Hardware Initialization Failed\n");
2707                 return;
2708         }
2709         if (hw->mac.type >= igb_mac_min)
2710                 igb_init_dmac(adapter, pba);
2711
2712         E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2713         e1000_get_phy_info(hw);
2714         e1000_check_for_link(hw);
2715 }
2716
2717 /*
2718  * Initialise the RSS mapping for NICs that support multiple transmit/
2719  * receive rings.
2720  */
2721
2722 #define RSSKEYLEN 10
2723 static void
2724 em_initialize_rss_mapping(struct adapter *adapter)
2725 {
2726         uint8_t  rss_key[4 * RSSKEYLEN];
2727         uint32_t reta = 0;
2728         struct e1000_hw *hw = &adapter->hw;
2729         int i;
2730
2731         /*
2732          * Configure RSS key
2733          */
2734         arc4rand(rss_key, sizeof(rss_key), 0);
2735         for (i = 0; i < RSSKEYLEN; ++i) {
2736                 uint32_t rssrk = 0;
2737
2738                 rssrk = EM_RSSRK_VAL(rss_key, i);
2739                 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2740         }
2741
2742         /*
2743          * Configure RSS redirect table in following fashion:
2744          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2745          */
2746         for (i = 0; i < sizeof(reta); ++i) {
2747                 uint32_t q;
2748
2749                 q = (i % adapter->rx_num_queues) << 7;
2750                 reta |= q << (8 * i);
2751         }
2752
2753         for (i = 0; i < 32; ++i)
2754                 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2755
2756         E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2757                         E1000_MRQC_RSS_FIELD_IPV4_TCP |
2758                         E1000_MRQC_RSS_FIELD_IPV4 |
2759                         E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2760                         E1000_MRQC_RSS_FIELD_IPV6_EX |
2761                         E1000_MRQC_RSS_FIELD_IPV6);
2762 }
2763
2764 static void
2765 igb_initialize_rss_mapping(struct adapter *adapter)
2766 {
2767         struct e1000_hw *hw = &adapter->hw;
2768         int i;
2769         int queue_id;
2770         u32 reta;
2771         u32 rss_key[10], mrqc, shift = 0;
2772
2773         /* XXX? */
2774         if (hw->mac.type == e1000_82575)
2775                 shift = 6;
2776
2777         /*
2778          * The redirection table controls which destination
2779          * queue each bucket redirects traffic to.
2780          * Each DWORD represents four queues, with the LSB
2781          * being the first queue in the DWORD.
2782          *
2783          * This just allocates buckets to queues using round-robin
2784          * allocation.
2785          *
2786          * NOTE: It Just Happens to line up with the default
2787          * RSS allocation method.
2788          */
2789
2790         /* Warning FM follows */
2791         reta = 0;
2792         for (i = 0; i < 128; i++) {
2793 #ifdef RSS
2794                 queue_id = rss_get_indirection_to_bucket(i);
2795                 /*
2796                  * If we have more queues than buckets, we'll
2797                  * end up mapping buckets to a subset of the
2798                  * queues.
2799                  *
2800                  * If we have more buckets than queues, we'll
2801                  * end up instead assigning multiple buckets
2802                  * to queues.
2803                  *
2804                  * Both are suboptimal, but we need to handle
2805                  * the case so we don't go out of bounds
2806                  * indexing arrays and such.
2807                  */
2808                 queue_id = queue_id % adapter->rx_num_queues;
2809 #else
2810                 queue_id = (i % adapter->rx_num_queues);
2811 #endif
2812                 /* Adjust if required */
2813                 queue_id = queue_id << shift;
2814
2815                 /*
2816                  * The low 8 bits are for hash value (n+0);
2817                  * The next 8 bits are for hash value (n+1), etc.
2818                  */
2819                 reta = reta >> 8;
2820                 reta = reta | ( ((uint32_t) queue_id) << 24);
2821                 if ((i & 3) == 3) {
2822                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2823                         reta = 0;
2824                 }
2825         }
2826
2827         /* Now fill in hash table */
2828
2829         /*
2830          * MRQC: Multiple Receive Queues Command
2831          * Set queuing to RSS control, number depends on the device.
2832          */
2833         mrqc = E1000_MRQC_ENABLE_RSS_8Q;
2834
2835 #ifdef RSS
2836         /* XXX ew typecasting */
2837         rss_getkey((uint8_t *) &rss_key);
2838 #else
2839         arc4rand(&rss_key, sizeof(rss_key), 0);
2840 #endif
2841         for (i = 0; i < 10; i++)
2842                 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]);
2843
2844         /*
2845          * Configure the RSS fields to hash upon.
2846          */
2847         mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2848             E1000_MRQC_RSS_FIELD_IPV4_TCP);
2849         mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2850             E1000_MRQC_RSS_FIELD_IPV6_TCP);
2851         mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2852             E1000_MRQC_RSS_FIELD_IPV6_UDP);
2853         mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2854             E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2855
2856         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2857 }
2858
2859 /*********************************************************************
2860  *
2861  *  Setup networking device structure and register interface media.
2862  *
2863  **********************************************************************/
2864 static int
2865 em_setup_interface(if_ctx_t ctx)
2866 {
2867         struct ifnet *ifp = iflib_get_ifp(ctx);
2868         struct adapter *adapter = iflib_get_softc(ctx);
2869         if_softc_ctx_t scctx = adapter->shared;
2870
2871         INIT_DEBUGOUT("em_setup_interface: begin");
2872
2873         /* Single Queue */
2874         if (adapter->tx_num_queues == 1) {
2875                 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
2876                 if_setsendqready(ifp);
2877         }
2878
2879         /*
2880          * Specify the media types supported by this adapter and register
2881          * callbacks to update media and link information
2882          */
2883         if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2884             adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
2885                 u_char fiber_type = IFM_1000_SX;        /* default type */
2886
2887                 if (adapter->hw.mac.type == e1000_82545)
2888                         fiber_type = IFM_1000_LX;
2889                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
2890                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2891         } else {
2892                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2893                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2894                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2895                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2896                 if (adapter->hw.phy.type != e1000_phy_ife) {
2897                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2898                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2899                 }
2900         }
2901         ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2902         ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO);
2903         return (0);
2904 }
2905
2906 static int
2907 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
2908 {
2909         struct adapter *adapter = iflib_get_softc(ctx);
2910         if_softc_ctx_t scctx = adapter->shared;
2911         int error = E1000_SUCCESS;
2912         struct em_tx_queue *que;
2913         int i, j;
2914
2915         MPASS(adapter->tx_num_queues > 0);
2916         MPASS(adapter->tx_num_queues == ntxqsets);
2917
2918         /* First allocate the top level queue structs */
2919         if (!(adapter->tx_queues =
2920             (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
2921             adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2922                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2923                 return(ENOMEM);
2924         }
2925
2926         for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) {
2927                 /* Set up some basics */
2928
2929                 struct tx_ring *txr = &que->txr;
2930                 txr->adapter = que->adapter = adapter;
2931                 que->me = txr->me =  i;
2932
2933                 /* Allocate report status array */
2934                 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2935                         device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n");
2936                         error = ENOMEM;
2937                         goto fail;
2938                 }
2939                 for (j = 0; j < scctx->isc_ntxd[0]; j++)
2940                         txr->tx_rsq[j] = QIDX_INVALID;
2941                 /* get the virtual and physical address of the hardware queues */
2942                 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
2943                 txr->tx_paddr = paddrs[i*ntxqs];
2944         }
2945
2946         if (bootverbose)
2947                 device_printf(iflib_get_dev(ctx),
2948                     "allocated for %d tx_queues\n", adapter->tx_num_queues);
2949         return (0);
2950 fail:
2951         em_if_queues_free(ctx);
2952         return (error);
2953 }
2954
2955 static int
2956 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
2957 {
2958         struct adapter *adapter = iflib_get_softc(ctx);
2959         int error = E1000_SUCCESS;
2960         struct em_rx_queue *que;
2961         int i;
2962
2963         MPASS(adapter->rx_num_queues > 0);
2964         MPASS(adapter->rx_num_queues == nrxqsets);
2965
2966         /* First allocate the top level queue structs */
2967         if (!(adapter->rx_queues =
2968             (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
2969             adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2970                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2971                 error = ENOMEM;
2972                 goto fail;
2973         }
2974
2975         for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) {
2976                 /* Set up some basics */
2977                 struct rx_ring *rxr = &que->rxr;
2978                 rxr->adapter = que->adapter = adapter;
2979                 rxr->que = que;
2980                 que->me = rxr->me =  i;
2981
2982                 /* get the virtual and physical address of the hardware queues */
2983                 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
2984                 rxr->rx_paddr = paddrs[i*nrxqs];
2985         }
2986
2987         if (bootverbose)
2988                 device_printf(iflib_get_dev(ctx),
2989                     "allocated for %d rx_queues\n", adapter->rx_num_queues);
2990
2991         return (0);
2992 fail:
2993         em_if_queues_free(ctx);
2994         return (error);
2995 }
2996
2997 static void
2998 em_if_queues_free(if_ctx_t ctx)
2999 {
3000         struct adapter *adapter = iflib_get_softc(ctx);
3001         struct em_tx_queue *tx_que = adapter->tx_queues;
3002         struct em_rx_queue *rx_que = adapter->rx_queues;
3003
3004         if (tx_que != NULL) {
3005                 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
3006                         struct tx_ring *txr = &tx_que->txr;
3007                         if (txr->tx_rsq == NULL)
3008                                 break;
3009
3010                         free(txr->tx_rsq, M_DEVBUF);
3011                         txr->tx_rsq = NULL;
3012                 }
3013                 free(adapter->tx_queues, M_DEVBUF);
3014                 adapter->tx_queues = NULL;
3015         }
3016
3017         if (rx_que != NULL) {
3018                 free(adapter->rx_queues, M_DEVBUF);
3019                 adapter->rx_queues = NULL;
3020         }
3021 }
3022
3023 /*********************************************************************
3024  *
3025  *  Enable transmit unit.
3026  *
3027  **********************************************************************/
3028 static void
3029 em_initialize_transmit_unit(if_ctx_t ctx)
3030 {
3031         struct adapter *adapter = iflib_get_softc(ctx);
3032         if_softc_ctx_t scctx = adapter->shared;
3033         struct em_tx_queue *que;
3034         struct tx_ring  *txr;
3035         struct e1000_hw *hw = &adapter->hw;
3036         u32 tctl, txdctl = 0, tarc, tipg = 0;
3037
3038         INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
3039
3040         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
3041                 u64 bus_addr;
3042                 caddr_t offp, endp;
3043
3044                 que = &adapter->tx_queues[i];
3045                 txr = &que->txr;
3046                 bus_addr = txr->tx_paddr;
3047
3048                 /* Clear checksum offload context. */
3049                 offp = (caddr_t)&txr->csum_flags;
3050                 endp = (caddr_t)(txr + 1);
3051                 bzero(offp, endp - offp);
3052
3053                 /* Base and Len of TX Ring */
3054                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
3055                     scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
3056                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
3057                     (u32)(bus_addr >> 32));
3058                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
3059                     (u32)bus_addr);
3060                 /* Init the HEAD/TAIL indices */
3061                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
3062                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
3063
3064                 HW_DEBUGOUT2("Base = %x, Length = %x\n",
3065                     E1000_READ_REG(hw, E1000_TDBAL(i)),
3066                     E1000_READ_REG(hw, E1000_TDLEN(i)));
3067
3068                 txdctl = 0; /* clear txdctl */
3069                 txdctl |= 0x1f; /* PTHRESH */
3070                 txdctl |= 1 << 8; /* HTHRESH */
3071                 txdctl |= 1 << 16;/* WTHRESH */
3072                 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
3073                 txdctl |= E1000_TXDCTL_GRAN;
3074                 txdctl |= 1 << 25; /* LWTHRESH */
3075
3076                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
3077         }
3078
3079         /* Set the default values for the Tx Inter Packet Gap timer */
3080         switch (hw->mac.type) {
3081         case e1000_80003es2lan:
3082                 tipg = DEFAULT_82543_TIPG_IPGR1;
3083                 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
3084                     E1000_TIPG_IPGR2_SHIFT;
3085                 break;
3086         case e1000_82542:
3087                 tipg = DEFAULT_82542_TIPG_IPGT;
3088                 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3089                 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3090                 break;
3091         default:
3092                 if (hw->phy.media_type == e1000_media_type_fiber ||
3093                     hw->phy.media_type == e1000_media_type_internal_serdes)
3094                         tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
3095                 else
3096                         tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
3097                 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3098                 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3099         }
3100
3101         E1000_WRITE_REG(hw, E1000_TIPG, tipg);
3102         E1000_WRITE_REG(hw, E1000_TIDV, adapter->tx_int_delay.value);
3103
3104         if(hw->mac.type >= e1000_82540)
3105                 E1000_WRITE_REG(hw, E1000_TADV,
3106                     adapter->tx_abs_int_delay.value);
3107
3108         if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) {
3109                 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3110                 tarc |= TARC_SPEED_MODE_BIT;
3111                 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3112         } else if (hw->mac.type == e1000_80003es2lan) {
3113                 /* errata: program both queues to unweighted RR */
3114                 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3115                 tarc |= 1;
3116                 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3117                 tarc = E1000_READ_REG(hw, E1000_TARC(1));
3118                 tarc |= 1;
3119                 E1000_WRITE_REG(hw, E1000_TARC(1), tarc);
3120         } else if (hw->mac.type == e1000_82574) {
3121                 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3122                 tarc |= TARC_ERRATA_BIT;
3123                 if ( adapter->tx_num_queues > 1) {
3124                         tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
3125                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3126                         E1000_WRITE_REG(hw, E1000_TARC(1), tarc);
3127                 } else
3128                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3129         }
3130
3131         if (adapter->tx_int_delay.value > 0)
3132                 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3133
3134         /* Program the Transmit Control Register */
3135         tctl = E1000_READ_REG(hw, E1000_TCTL);
3136         tctl &= ~E1000_TCTL_CT;
3137         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
3138                    (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
3139
3140         if (hw->mac.type >= e1000_82571)
3141                 tctl |= E1000_TCTL_MULR;
3142
3143         /* This write will effectively turn on the transmit unit. */
3144         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
3145
3146         /* SPT and KBL errata workarounds */
3147         if (hw->mac.type == e1000_pch_spt) {
3148                 u32 reg;
3149                 reg = E1000_READ_REG(hw, E1000_IOSFPC);
3150                 reg |= E1000_RCTL_RDMTS_HEX;
3151                 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
3152                 /* i218-i219 Specification Update 1.5.4.5 */
3153                 reg = E1000_READ_REG(hw, E1000_TARC(0));
3154                 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3155                 reg |= E1000_TARC0_CB_MULTIQ_2_REQ;
3156                 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3157         }
3158 }
3159
3160 /*********************************************************************
3161  *
3162  *  Enable receive unit.
3163  *
3164  **********************************************************************/
3165
3166 static void
3167 em_initialize_receive_unit(if_ctx_t ctx)
3168 {
3169         struct adapter *adapter = iflib_get_softc(ctx);
3170         if_softc_ctx_t scctx = adapter->shared;
3171         struct ifnet *ifp = iflib_get_ifp(ctx);
3172         struct e1000_hw *hw = &adapter->hw;
3173         struct em_rx_queue *que;
3174         int i;
3175         u32 rctl, rxcsum, rfctl;
3176
3177         INIT_DEBUGOUT("em_initialize_receive_units: begin");
3178
3179         /*
3180          * Make sure receives are disabled while setting
3181          * up the descriptor ring
3182          */
3183         rctl = E1000_READ_REG(hw, E1000_RCTL);
3184         /* Do not disable if ever enabled on this hardware */
3185         if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
3186                 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3187
3188         /* Setup the Receive Control Register */
3189         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3190         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3191             E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3192             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3193
3194         /* Do not store bad packets */
3195         rctl &= ~E1000_RCTL_SBP;
3196
3197         /* Enable Long Packet receive */
3198         if (if_getmtu(ifp) > ETHERMTU)
3199                 rctl |= E1000_RCTL_LPE;
3200         else
3201                 rctl &= ~E1000_RCTL_LPE;
3202
3203         /* Strip the CRC */
3204         if (!em_disable_crc_stripping)
3205                 rctl |= E1000_RCTL_SECRC;
3206
3207         if (hw->mac.type >= e1000_82540) {
3208                 E1000_WRITE_REG(hw, E1000_RADV,
3209                     adapter->rx_abs_int_delay.value);
3210
3211                 /*
3212                  * Set the interrupt throttling rate. Value is calculated
3213                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
3214                  */
3215                 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
3216         }
3217         E1000_WRITE_REG(hw, E1000_RDTR, adapter->rx_int_delay.value);
3218
3219         /* Use extended rx descriptor formats */
3220         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3221         rfctl |= E1000_RFCTL_EXTEN;
3222         /*
3223          * When using MSI-X interrupts we need to throttle
3224          * using the EITR register (82574 only)
3225          */
3226         if (hw->mac.type == e1000_82574) {
3227                 for (int i = 0; i < 4; i++)
3228                         E1000_WRITE_REG(hw, E1000_EITR_82574(i),
3229                             DEFAULT_ITR);
3230                 /* Disable accelerated acknowledge */
3231                 rfctl |= E1000_RFCTL_ACK_DIS;
3232         }
3233         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3234
3235         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
3236         if (if_getcapenable(ifp) & IFCAP_RXCSUM &&
3237             hw->mac.type >= e1000_82543) {
3238                 if (adapter->tx_num_queues > 1) {
3239                         if (hw->mac.type >= igb_mac_min) {
3240                                 rxcsum |= E1000_RXCSUM_PCSD;
3241                                 if (hw->mac.type != e1000_82575)
3242                                         rxcsum |= E1000_RXCSUM_CRCOFL;
3243                         } else
3244                                 rxcsum |= E1000_RXCSUM_TUOFL |
3245                                         E1000_RXCSUM_IPOFL |
3246                                         E1000_RXCSUM_PCSD;
3247                 } else {
3248                         if (hw->mac.type >= igb_mac_min)
3249                                 rxcsum |= E1000_RXCSUM_IPPCSE;
3250                         else
3251                                 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
3252                         if (hw->mac.type > e1000_82575)
3253                                 rxcsum |= E1000_RXCSUM_CRCOFL;
3254                 }
3255         } else
3256                 rxcsum &= ~E1000_RXCSUM_TUOFL;
3257
3258         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
3259
3260         if (adapter->rx_num_queues > 1) {
3261                 if (hw->mac.type >= igb_mac_min)
3262                         igb_initialize_rss_mapping(adapter);
3263                 else
3264                         em_initialize_rss_mapping(adapter);
3265         }
3266
3267         /*
3268          * XXX TEMPORARY WORKAROUND: on some systems with 82573
3269          * long latencies are observed, like Lenovo X60. This
3270          * change eliminates the problem, but since having positive
3271          * values in RDTR is a known source of problems on other
3272          * platforms another solution is being sought.
3273          */
3274         if (hw->mac.type == e1000_82573)
3275                 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
3276
3277         for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3278                 struct rx_ring *rxr = &que->rxr;
3279                 /* Setup the Base and Length of the Rx Descriptor Ring */
3280                 u64 bus_addr = rxr->rx_paddr;
3281 #if 0
3282                 u32 rdt = adapter->rx_num_queues -1;  /* default */
3283 #endif
3284
3285                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3286                     scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
3287                 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
3288                 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
3289                 /* Setup the Head and Tail Descriptor Pointers */
3290                 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
3291                 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
3292         }
3293
3294         /*
3295          * Set PTHRESH for improved jumbo performance
3296          * According to 10.2.5.11 of Intel 82574 Datasheet,
3297          * RXDCTL(1) is written whenever RXDCTL(0) is written.
3298          * Only write to RXDCTL(1) if there is a need for different
3299          * settings.
3300          */
3301         if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan ||
3302             hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) {
3303                 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
3304                 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
3305         } else if (hw->mac.type == e1000_82574) {
3306                 for (int i = 0; i < adapter->rx_num_queues; i++) {
3307                         u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3308                         rxdctl |= 0x20; /* PTHRESH */
3309                         rxdctl |= 4 << 8; /* HTHRESH */
3310                         rxdctl |= 4 << 16;/* WTHRESH */
3311                         rxdctl |= 1 << 24; /* Switch to granularity */
3312                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3313                 }
3314         } else if (hw->mac.type >= igb_mac_min) {
3315                 u32 psize, srrctl = 0;
3316
3317                 if (if_getmtu(ifp) > ETHERMTU) {
3318                         /* Set maximum packet len */
3319                         if (adapter->rx_mbuf_sz <= 4096) {
3320                                 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3321                                 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3322                         } else if (adapter->rx_mbuf_sz > 4096) {
3323                                 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3324                                 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3325                         }
3326                         psize = scctx->isc_max_frame_size;
3327                         /* are we on a vlan? */
3328                         if (ifp->if_vlantrunk != NULL)
3329                                 psize += VLAN_TAG_SIZE;
3330                         E1000_WRITE_REG(hw, E1000_RLPML, psize);
3331                 } else {
3332                         srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3333                         rctl |= E1000_RCTL_SZ_2048;
3334                 }
3335
3336                 /*
3337                  * If TX flow control is disabled and there's >1 queue defined,
3338                  * enable DROP.
3339                  *
3340                  * This drops frames rather than hanging the RX MAC for all queues.
3341                  */
3342                 if ((adapter->rx_num_queues > 1) &&
3343                     (adapter->fc == e1000_fc_none ||
3344                      adapter->fc == e1000_fc_rx_pause)) {
3345                         srrctl |= E1000_SRRCTL_DROP_EN;
3346                 }
3347                         /* Setup the Base and Length of the Rx Descriptor Rings */
3348                 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3349                         struct rx_ring *rxr = &que->rxr;
3350                         u64 bus_addr = rxr->rx_paddr;
3351                         u32 rxdctl;
3352
3353 #ifdef notyet
3354                         /* Configure for header split? -- ignore for now */
3355                         rxr->hdr_split = igb_header_split;
3356 #else
3357                         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3358 #endif
3359
3360                         E1000_WRITE_REG(hw, E1000_RDLEN(i),
3361                                         scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3362                         E1000_WRITE_REG(hw, E1000_RDBAH(i),
3363                                         (uint32_t)(bus_addr >> 32));
3364                         E1000_WRITE_REG(hw, E1000_RDBAL(i),
3365                                         (uint32_t)bus_addr);
3366                         E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3367                         /* Enable this Queue */
3368                         rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3369                         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3370                         rxdctl &= 0xFFF00000;
3371                         rxdctl |= IGB_RX_PTHRESH;
3372                         rxdctl |= IGB_RX_HTHRESH << 8;
3373                         rxdctl |= IGB_RX_WTHRESH << 16;
3374                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3375                 }
3376         } else if (hw->mac.type >= e1000_pch2lan) {
3377                 if (if_getmtu(ifp) > ETHERMTU)
3378                         e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
3379                 else
3380                         e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
3381         }
3382
3383         /* Make sure VLAN Filters are off */
3384         rctl &= ~E1000_RCTL_VFE;
3385
3386         if (hw->mac.type < igb_mac_min) {
3387                 if (adapter->rx_mbuf_sz == MCLBYTES)
3388                         rctl |= E1000_RCTL_SZ_2048;
3389                 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE)
3390                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3391                 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE)
3392                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3393
3394                 /* ensure we clear use DTYPE of 00 here */
3395                 rctl &= ~0x00000C00;
3396         }
3397
3398         /* Write out the settings */
3399         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3400
3401         return;
3402 }
3403
3404 static void
3405 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3406 {
3407         struct adapter *adapter = iflib_get_softc(ctx);
3408         u32 index, bit;
3409
3410         index = (vtag >> 5) & 0x7F;
3411         bit = vtag & 0x1F;
3412         adapter->shadow_vfta[index] |= (1 << bit);
3413         ++adapter->num_vlans;
3414 }
3415
3416 static void
3417 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3418 {
3419         struct adapter *adapter = iflib_get_softc(ctx);
3420         u32 index, bit;
3421
3422         index = (vtag >> 5) & 0x7F;
3423         bit = vtag & 0x1F;
3424         adapter->shadow_vfta[index] &= ~(1 << bit);
3425         --adapter->num_vlans;
3426 }
3427
3428 static void
3429 em_setup_vlan_hw_support(struct adapter *adapter)
3430 {
3431         struct e1000_hw *hw = &adapter->hw;
3432         u32 reg;
3433
3434         /*
3435          * We get here thru init_locked, meaning
3436          * a soft reset, this has already cleared
3437          * the VFTA and other state, so if there
3438          * have been no vlan's registered do nothing.
3439          */
3440         if (adapter->num_vlans == 0)
3441                 return;
3442
3443         /*
3444          * A soft reset zero's out the VFTA, so
3445          * we need to repopulate it now.
3446          */
3447         for (int i = 0; i < EM_VFTA_SIZE; i++)
3448                 if (adapter->shadow_vfta[i] != 0)
3449                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
3450                             i, adapter->shadow_vfta[i]);
3451
3452         reg = E1000_READ_REG(hw, E1000_CTRL);
3453         reg |= E1000_CTRL_VME;
3454         E1000_WRITE_REG(hw, E1000_CTRL, reg);
3455
3456         /* Enable the Filter Table */
3457         reg = E1000_READ_REG(hw, E1000_RCTL);
3458         reg &= ~E1000_RCTL_CFIEN;
3459         reg |= E1000_RCTL_VFE;
3460         E1000_WRITE_REG(hw, E1000_RCTL, reg);
3461 }
3462
3463 static void
3464 em_if_intr_enable(if_ctx_t ctx)
3465 {
3466         struct adapter *adapter = iflib_get_softc(ctx);
3467         struct e1000_hw *hw = &adapter->hw;
3468         u32 ims_mask = IMS_ENABLE_MASK;
3469
3470         if (hw->mac.type == e1000_82574) {
3471                 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK);
3472                 ims_mask |= adapter->ims;
3473         }
3474         E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3475 }
3476
3477 static void
3478 em_if_intr_disable(if_ctx_t ctx)
3479 {
3480         struct adapter *adapter = iflib_get_softc(ctx);
3481         struct e1000_hw *hw = &adapter->hw;
3482
3483         if (hw->mac.type == e1000_82574)
3484                 E1000_WRITE_REG(hw, EM_EIAC, 0);
3485         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3486 }
3487
3488 static void
3489 igb_if_intr_enable(if_ctx_t ctx)
3490 {
3491         struct adapter *adapter = iflib_get_softc(ctx);
3492         struct e1000_hw *hw = &adapter->hw;
3493         u32 mask;
3494
3495         if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) {
3496                 mask = (adapter->que_mask | adapter->link_mask);
3497                 E1000_WRITE_REG(hw, E1000_EIAC, mask);
3498                 E1000_WRITE_REG(hw, E1000_EIAM, mask);
3499                 E1000_WRITE_REG(hw, E1000_EIMS, mask);
3500                 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
3501         } else
3502                 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
3503         E1000_WRITE_FLUSH(hw);
3504 }
3505
3506 static void
3507 igb_if_intr_disable(if_ctx_t ctx)
3508 {
3509         struct adapter *adapter = iflib_get_softc(ctx);
3510         struct e1000_hw *hw = &adapter->hw;
3511
3512         if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) {
3513                 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff);
3514                 E1000_WRITE_REG(hw, E1000_EIAC, 0);
3515         }
3516         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3517         E1000_WRITE_FLUSH(hw);
3518 }
3519
3520 /*
3521  * Bit of a misnomer, what this really means is
3522  * to enable OS management of the system... aka
3523  * to disable special hardware management features
3524  */
3525 static void
3526 em_init_manageability(struct adapter *adapter)
3527 {
3528         /* A shared code workaround */
3529 #define E1000_82542_MANC2H E1000_MANC2H
3530         if (adapter->has_manage) {
3531                 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3532                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3533
3534                 /* disable hardware interception of ARP */
3535                 manc &= ~(E1000_MANC_ARP_EN);
3536
3537                 /* enable receiving management packets to the host */
3538                 manc |= E1000_MANC_EN_MNG2HOST;
3539 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3540 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3541                 manc2h |= E1000_MNG2HOST_PORT_623;
3542                 manc2h |= E1000_MNG2HOST_PORT_664;
3543                 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3544                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3545         }
3546 }
3547
3548 /*
3549  * Give control back to hardware management
3550  * controller if there is one.
3551  */
3552 static void
3553 em_release_manageability(struct adapter *adapter)
3554 {
3555         if (adapter->has_manage) {
3556                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3557
3558                 /* re-enable hardware interception of ARP */
3559                 manc |= E1000_MANC_ARP_EN;
3560                 manc &= ~E1000_MANC_EN_MNG2HOST;
3561
3562                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3563         }
3564 }
3565
3566 /*
3567  * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3568  * For ASF and Pass Through versions of f/w this means
3569  * that the driver is loaded. For AMT version type f/w
3570  * this means that the network i/f is open.
3571  */
3572 static void
3573 em_get_hw_control(struct adapter *adapter)
3574 {
3575         u32 ctrl_ext, swsm;
3576
3577         if (adapter->vf_ifp)
3578                 return;
3579
3580         if (adapter->hw.mac.type == e1000_82573) {
3581                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3582                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3583                     swsm | E1000_SWSM_DRV_LOAD);
3584                 return;
3585         }
3586         /* else */
3587         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3588         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3589             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3590 }
3591
3592 /*
3593  * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3594  * For ASF and Pass Through versions of f/w this means that
3595  * the driver is no longer loaded. For AMT versions of the
3596  * f/w this means that the network i/f is closed.
3597  */
3598 static void
3599 em_release_hw_control(struct adapter *adapter)
3600 {
3601         u32 ctrl_ext, swsm;
3602
3603         if (!adapter->has_manage)
3604                 return;
3605
3606         if (adapter->hw.mac.type == e1000_82573) {
3607                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3608                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3609                     swsm & ~E1000_SWSM_DRV_LOAD);
3610                 return;
3611         }
3612         /* else */
3613         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3614         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3615             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3616         return;
3617 }
3618
3619 static int
3620 em_is_valid_ether_addr(u8 *addr)
3621 {
3622         char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3623
3624         if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3625                 return (FALSE);
3626         }
3627
3628         return (TRUE);
3629 }
3630
3631 /*
3632 ** Parse the interface capabilities with regard
3633 ** to both system management and wake-on-lan for
3634 ** later use.
3635 */
3636 static void
3637 em_get_wakeup(if_ctx_t ctx)
3638 {
3639         struct adapter *adapter = iflib_get_softc(ctx);
3640         device_t dev = iflib_get_dev(ctx);
3641         u16 eeprom_data = 0, device_id, apme_mask;
3642
3643         adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
3644         apme_mask = EM_EEPROM_APME;
3645
3646         switch (adapter->hw.mac.type) {
3647         case e1000_82542:
3648         case e1000_82543:
3649                 break;
3650         case e1000_82544:
3651                 e1000_read_nvm(&adapter->hw,
3652                     NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3653                 apme_mask = EM_82544_APME;
3654                 break;
3655         case e1000_82546:
3656         case e1000_82546_rev_3:
3657                 if (adapter->hw.bus.func == 1) {
3658                         e1000_read_nvm(&adapter->hw,
3659                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3660                         break;
3661                 } else
3662                         e1000_read_nvm(&adapter->hw,
3663                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3664                 break;
3665         case e1000_82573:
3666         case e1000_82583:
3667                 adapter->has_amt = TRUE;
3668                 /* FALLTHROUGH */
3669         case e1000_82571:
3670         case e1000_82572:
3671         case e1000_80003es2lan:
3672                 if (adapter->hw.bus.func == 1) {
3673                         e1000_read_nvm(&adapter->hw,
3674                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3675                         break;
3676                 } else
3677                         e1000_read_nvm(&adapter->hw,
3678                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3679                 break;
3680         case e1000_ich8lan:
3681         case e1000_ich9lan:
3682         case e1000_ich10lan:
3683         case e1000_pchlan:
3684         case e1000_pch2lan:
3685         case e1000_pch_lpt:
3686         case e1000_pch_spt:
3687         case e1000_82575:       /* listing all igb devices */
3688         case e1000_82576:
3689         case e1000_82580:
3690         case e1000_i350:
3691         case e1000_i354:
3692         case e1000_i210:
3693         case e1000_i211:
3694         case e1000_vfadapt:
3695         case e1000_vfadapt_i350:
3696                 apme_mask = E1000_WUC_APME;
3697                 adapter->has_amt = TRUE;
3698                 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
3699                 break;
3700         default:
3701                 e1000_read_nvm(&adapter->hw,
3702                     NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3703                 break;
3704         }
3705         if (eeprom_data & apme_mask)
3706                 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
3707         /*
3708          * We have the eeprom settings, now apply the special cases
3709          * where the eeprom may be wrong or the board won't support
3710          * wake on lan on a particular port
3711          */
3712         device_id = pci_get_device(dev);
3713         switch (device_id) {
3714         case E1000_DEV_ID_82546GB_PCIE:
3715                 adapter->wol = 0;
3716                 break;
3717         case E1000_DEV_ID_82546EB_FIBER:
3718         case E1000_DEV_ID_82546GB_FIBER:
3719                 /* Wake events only supported on port A for dual fiber
3720                  * regardless of eeprom setting */
3721                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3722                     E1000_STATUS_FUNC_1)
3723                         adapter->wol = 0;
3724                 break;
3725         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
3726                 /* if quad port adapter, disable WoL on all but port A */
3727                 if (global_quad_port_a != 0)
3728                         adapter->wol = 0;
3729                 /* Reset for multiple quad port adapters */
3730                 if (++global_quad_port_a == 4)
3731                         global_quad_port_a = 0;
3732                 break;
3733         case E1000_DEV_ID_82571EB_FIBER:
3734                 /* Wake events only supported on port A for dual fiber
3735                  * regardless of eeprom setting */
3736                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3737                     E1000_STATUS_FUNC_1)
3738                         adapter->wol = 0;
3739                 break;
3740         case E1000_DEV_ID_82571EB_QUAD_COPPER:
3741         case E1000_DEV_ID_82571EB_QUAD_FIBER:
3742         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
3743                 /* if quad port adapter, disable WoL on all but port A */
3744                 if (global_quad_port_a != 0)
3745                         adapter->wol = 0;
3746                 /* Reset for multiple quad port adapters */
3747                 if (++global_quad_port_a == 4)
3748                         global_quad_port_a = 0;
3749                 break;
3750         }
3751         return;
3752 }
3753
3754
3755 /*
3756  * Enable PCI Wake On Lan capability
3757  */
3758 static void
3759 em_enable_wakeup(if_ctx_t ctx)
3760 {
3761         struct adapter *adapter = iflib_get_softc(ctx);
3762         device_t dev = iflib_get_dev(ctx);
3763         if_t ifp = iflib_get_ifp(ctx);
3764         int error = 0;
3765         u32 pmc, ctrl, ctrl_ext, rctl;
3766         u16 status;
3767
3768         if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
3769                 return;
3770
3771         /*
3772          * Determine type of Wakeup: note that wol
3773          * is set with all bits on by default.
3774          */
3775         if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
3776                 adapter->wol &= ~E1000_WUFC_MAG;
3777
3778         if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
3779                 adapter->wol &= ~E1000_WUFC_EX;
3780
3781         if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
3782                 adapter->wol &= ~E1000_WUFC_MC;
3783         else {
3784                 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3785                 rctl |= E1000_RCTL_MPE;
3786                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3787         }
3788
3789         if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC)))
3790                 goto pme;
3791
3792         /* Advertise the wakeup capability */
3793         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
3794         ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
3795         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
3796
3797         /* Keep the laser running on Fiber adapters */
3798         if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3799             adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
3800                 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3801                 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
3802                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext);
3803         }
3804
3805         if ((adapter->hw.mac.type == e1000_ich8lan) ||
3806             (adapter->hw.mac.type == e1000_pchlan) ||
3807             (adapter->hw.mac.type == e1000_ich9lan) ||
3808             (adapter->hw.mac.type == e1000_ich10lan))
3809                 e1000_suspend_workarounds_ich8lan(&adapter->hw);
3810
3811         if ( adapter->hw.mac.type >= e1000_pchlan) {
3812                 error = em_enable_phy_wakeup(adapter);
3813                 if (error)
3814                         goto pme;
3815         } else {
3816                 /* Enable wakeup by the MAC */
3817                 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
3818                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
3819         }
3820
3821         if (adapter->hw.phy.type == e1000_phy_igp_3)
3822                 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
3823
3824 pme:
3825         status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
3826         status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3827         if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
3828                 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3829         pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
3830
3831         return;
3832 }
3833
3834 /*
3835  * WOL in the newer chipset interfaces (pchlan)
3836  * require thing to be copied into the phy
3837  */
3838 static int
3839 em_enable_phy_wakeup(struct adapter *adapter)
3840 {
3841         struct e1000_hw *hw = &adapter->hw;
3842         u32 mreg, ret = 0;
3843         u16 preg;
3844
3845         /* copy MAC RARs to PHY RARs */
3846         e1000_copy_rx_addrs_to_phy_ich8lan(hw);
3847
3848         /* copy MAC MTA to PHY MTA */
3849         for (int i = 0; i < hw->mac.mta_reg_count; i++) {
3850                 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
3851                 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
3852                 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
3853                     (u16)((mreg >> 16) & 0xFFFF));
3854         }
3855
3856         /* configure PHY Rx Control register */
3857         e1000_read_phy_reg(hw, BM_RCTL, &preg);
3858         mreg = E1000_READ_REG(hw, E1000_RCTL);
3859         if (mreg & E1000_RCTL_UPE)
3860                 preg |= BM_RCTL_UPE;
3861         if (mreg & E1000_RCTL_MPE)
3862                 preg |= BM_RCTL_MPE;
3863         preg &= ~(BM_RCTL_MO_MASK);
3864         if (mreg & E1000_RCTL_MO_3)
3865                 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
3866                                 << BM_RCTL_MO_SHIFT);
3867         if (mreg & E1000_RCTL_BAM)
3868                 preg |= BM_RCTL_BAM;
3869         if (mreg & E1000_RCTL_PMCF)
3870                 preg |= BM_RCTL_PMCF;
3871         mreg = E1000_READ_REG(hw, E1000_CTRL);
3872         if (mreg & E1000_CTRL_RFCE)
3873                 preg |= BM_RCTL_RFCE;
3874         e1000_write_phy_reg(hw, BM_RCTL, preg);
3875
3876         /* enable PHY wakeup in MAC register */
3877         E1000_WRITE_REG(hw, E1000_WUC,
3878             E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
3879         E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol);
3880
3881         /* configure and enable PHY wakeup in PHY registers */
3882         e1000_write_phy_reg(hw, BM_WUFC, adapter->wol);
3883         e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN);
3884
3885         /* activate PHY wakeup */
3886         ret = hw->phy.ops.acquire(hw);
3887         if (ret) {
3888                 printf("Could not acquire PHY\n");
3889                 return ret;
3890         }
3891         e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3892                                  (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3893         ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
3894         if (ret) {
3895                 printf("Could not read PHY page 769\n");
3896                 goto out;
3897         }
3898         preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
3899         ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
3900         if (ret)
3901                 printf("Could not set PHY Host Wakeup bit\n");
3902 out:
3903         hw->phy.ops.release(hw);
3904
3905         return ret;
3906 }
3907
3908 static void
3909 em_if_led_func(if_ctx_t ctx, int onoff)
3910 {
3911         struct adapter *adapter = iflib_get_softc(ctx);
3912
3913         if (onoff) {
3914                 e1000_setup_led(&adapter->hw);
3915                 e1000_led_on(&adapter->hw);
3916         } else {
3917                 e1000_led_off(&adapter->hw);
3918                 e1000_cleanup_led(&adapter->hw);
3919         }
3920 }
3921
3922 /*
3923  * Disable the L0S and L1 LINK states
3924  */
3925 static void
3926 em_disable_aspm(struct adapter *adapter)
3927 {
3928         int base, reg;
3929         u16 link_cap,link_ctrl;
3930         device_t dev = adapter->dev;
3931
3932         switch (adapter->hw.mac.type) {
3933         case e1000_82573:
3934         case e1000_82574:
3935         case e1000_82583:
3936                 break;
3937         default:
3938                 return;
3939         }
3940         if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
3941                 return;
3942         reg = base + PCIER_LINK_CAP;
3943         link_cap = pci_read_config(dev, reg, 2);
3944         if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
3945                 return;
3946         reg = base + PCIER_LINK_CTL;
3947         link_ctrl = pci_read_config(dev, reg, 2);
3948         link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
3949         pci_write_config(dev, reg, link_ctrl, 2);
3950         return;
3951 }
3952
3953 /**********************************************************************
3954  *
3955  *  Update the board statistics counters.
3956  *
3957  **********************************************************************/
3958 static void
3959 em_update_stats_counters(struct adapter *adapter)
3960 {
3961         u64 prev_xoffrxc = adapter->stats.xoffrxc;
3962
3963         if(adapter->hw.phy.media_type == e1000_media_type_copper ||
3964            (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3965                 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
3966                 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
3967         }
3968         adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
3969         adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
3970         adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
3971         adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
3972
3973         adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
3974         adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
3975         adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
3976         adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
3977         adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
3978         adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
3979         adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
3980         adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
3981         /*
3982          ** For watchdog management we need to know if we have been
3983          ** paused during the last interval, so capture that here.
3984         */
3985         if (adapter->stats.xoffrxc != prev_xoffrxc)
3986                 adapter->shared->isc_pause_frames = 1;
3987         adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
3988         adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
3989         adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
3990         adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
3991         adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
3992         adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
3993         adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
3994         adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
3995         adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
3996         adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
3997         adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
3998         adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
3999
4000         /* For the 64-bit byte counters the low dword must be read first. */
4001         /* Both registers clear on the read of the high dword */
4002
4003         adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) +
4004             ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32);
4005         adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) +
4006             ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32);
4007
4008         adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
4009         adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
4010         adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
4011         adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
4012         adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
4013
4014         adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
4015         adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
4016
4017         adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
4018         adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
4019         adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
4020         adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
4021         adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
4022         adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
4023         adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
4024         adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
4025         adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
4026         adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
4027
4028         /* Interrupt Counts */
4029
4030         adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC);
4031         adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC);
4032         adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC);
4033         adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC);
4034         adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC);
4035         adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC);
4036         adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC);
4037         adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC);
4038         adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC);
4039
4040         if (adapter->hw.mac.type >= e1000_82543) {
4041                 adapter->stats.algnerrc +=
4042                 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
4043                 adapter->stats.rxerrc +=
4044                 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
4045                 adapter->stats.tncrs +=
4046                 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
4047                 adapter->stats.cexterr +=
4048                 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
4049                 adapter->stats.tsctc +=
4050                 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
4051                 adapter->stats.tsctfc +=
4052                 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
4053         }
4054 }
4055
4056 static uint64_t
4057 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
4058 {
4059         struct adapter *adapter = iflib_get_softc(ctx);
4060         struct ifnet *ifp = iflib_get_ifp(ctx);
4061
4062         switch (cnt) {
4063         case IFCOUNTER_COLLISIONS:
4064                 return (adapter->stats.colc);
4065         case IFCOUNTER_IERRORS:
4066                 return (adapter->dropped_pkts + adapter->stats.rxerrc +
4067                     adapter->stats.crcerrs + adapter->stats.algnerrc +
4068                     adapter->stats.ruc + adapter->stats.roc +
4069                     adapter->stats.mpc + adapter->stats.cexterr);
4070         case IFCOUNTER_OERRORS:
4071                 return (adapter->stats.ecol + adapter->stats.latecol +
4072                     adapter->watchdog_events);
4073         default:
4074                 return (if_get_counter_default(ifp, cnt));
4075         }
4076 }
4077
4078 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized
4079  * @ctx: iflib context
4080  * @event: event code to check
4081  *
4082  * Defaults to returning true for unknown events.
4083  *
4084  * @returns true if iflib needs to reinit the interface
4085  */
4086 static bool
4087 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
4088 {
4089         switch (event) {
4090         case IFLIB_RESTART_VLAN_CONFIG:
4091         default:
4092                 return (true);
4093         }
4094 }
4095
4096 /* Export a single 32-bit register via a read-only sysctl. */
4097 static int
4098 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
4099 {
4100         struct adapter *adapter;
4101         u_int val;
4102
4103         adapter = oidp->oid_arg1;
4104         val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2);
4105         return (sysctl_handle_int(oidp, &val, 0, req));
4106 }
4107
4108 /*
4109  * Add sysctl variables, one per statistic, to the system.
4110  */
4111 static void
4112 em_add_hw_stats(struct adapter *adapter)
4113 {
4114         device_t dev = iflib_get_dev(adapter->ctx);
4115         struct em_tx_queue *tx_que = adapter->tx_queues;
4116         struct em_rx_queue *rx_que = adapter->rx_queues;
4117
4118         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
4119         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
4120         struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
4121         struct e1000_hw_stats *stats = &adapter->stats;
4122
4123         struct sysctl_oid *stat_node, *queue_node, *int_node;
4124         struct sysctl_oid_list *stat_list, *queue_list, *int_list;
4125
4126 #define QUEUE_NAME_LEN 32
4127         char namebuf[QUEUE_NAME_LEN];
4128
4129         /* Driver Statistics */
4130         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
4131                         CTLFLAG_RD, &adapter->dropped_pkts,
4132                         "Driver dropped packets");
4133         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
4134                         CTLFLAG_RD, &adapter->link_irq,
4135                         "Link MSI-X IRQ Handled");
4136         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
4137                         CTLFLAG_RD, &adapter->rx_overruns,
4138                         "RX overruns");
4139         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
4140                         CTLFLAG_RD, &adapter->watchdog_events,
4141                         "Watchdog timeouts");
4142         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
4143             CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
4144             adapter, E1000_CTRL, em_sysctl_reg_handler, "IU",
4145             "Device Control Register");
4146         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
4147             CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
4148             adapter, E1000_RCTL, em_sysctl_reg_handler, "IU",
4149             "Receiver Control Register");
4150         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
4151                         CTLFLAG_RD, &adapter->hw.fc.high_water, 0,
4152                         "Flow Control High Watermark");
4153         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
4154                         CTLFLAG_RD, &adapter->hw.fc.low_water, 0,
4155                         "Flow Control Low Watermark");
4156
4157         for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
4158                 struct tx_ring *txr = &tx_que->txr;
4159                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
4160                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4161                     CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name");
4162                 queue_list = SYSCTL_CHILDREN(queue_node);
4163
4164                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
4165                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4166                     E1000_TDH(txr->me), em_sysctl_reg_handler, "IU",
4167                     "Transmit Descriptor Head");
4168                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
4169                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4170                     E1000_TDT(txr->me), em_sysctl_reg_handler, "IU",
4171                     "Transmit Descriptor Tail");
4172                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
4173                                 CTLFLAG_RD, &txr->tx_irq,
4174                                 "Queue MSI-X Transmit Interrupts");
4175         }
4176
4177         for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) {
4178                 struct rx_ring *rxr = &rx_que->rxr;
4179                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
4180                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4181                     CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name");
4182                 queue_list = SYSCTL_CHILDREN(queue_node);
4183
4184                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
4185                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4186                     E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU",
4187                     "Receive Descriptor Head");
4188                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
4189                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4190                     E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU",
4191                     "Receive Descriptor Tail");
4192                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
4193                                 CTLFLAG_RD, &rxr->rx_irq,
4194                                 "Queue MSI-X Receive Interrupts");
4195         }
4196
4197         /* MAC stats get their own sub node */
4198
4199         stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
4200             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics");
4201         stat_list = SYSCTL_CHILDREN(stat_node);
4202
4203         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
4204                         CTLFLAG_RD, &stats->ecol,
4205                         "Excessive collisions");
4206         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
4207                         CTLFLAG_RD, &stats->scc,
4208                         "Single collisions");
4209         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
4210                         CTLFLAG_RD, &stats->mcc,
4211                         "Multiple collisions");
4212         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
4213                         CTLFLAG_RD, &stats->latecol,
4214                         "Late collisions");
4215         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
4216                         CTLFLAG_RD, &stats->colc,
4217                         "Collision Count");
4218         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
4219                         CTLFLAG_RD, &adapter->stats.symerrs,
4220                         "Symbol Errors");
4221         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
4222                         CTLFLAG_RD, &adapter->stats.sec,
4223                         "Sequence Errors");
4224         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
4225                         CTLFLAG_RD, &adapter->stats.dc,
4226                         "Defer Count");
4227         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
4228                         CTLFLAG_RD, &adapter->stats.mpc,
4229                         "Missed Packets");
4230         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
4231                         CTLFLAG_RD, &adapter->stats.rnbc,
4232                         "Receive No Buffers");
4233         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
4234                         CTLFLAG_RD, &adapter->stats.ruc,
4235                         "Receive Undersize");
4236         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
4237                         CTLFLAG_RD, &adapter->stats.rfc,
4238                         "Fragmented Packets Received ");
4239         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
4240                         CTLFLAG_RD, &adapter->stats.roc,
4241                         "Oversized Packets Received");
4242         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
4243                         CTLFLAG_RD, &adapter->stats.rjc,
4244                         "Recevied Jabber");
4245         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
4246                         CTLFLAG_RD, &adapter->stats.rxerrc,
4247                         "Receive Errors");
4248         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
4249                         CTLFLAG_RD, &adapter->stats.crcerrs,
4250                         "CRC errors");
4251         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
4252                         CTLFLAG_RD, &adapter->stats.algnerrc,
4253                         "Alignment Errors");
4254         /* On 82575 these are collision counts */
4255         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
4256                         CTLFLAG_RD, &adapter->stats.cexterr,
4257                         "Collision/Carrier extension errors");
4258         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
4259                         CTLFLAG_RD, &adapter->stats.xonrxc,
4260                         "XON Received");
4261         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
4262                         CTLFLAG_RD, &adapter->stats.xontxc,
4263                         "XON Transmitted");
4264         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
4265                         CTLFLAG_RD, &adapter->stats.xoffrxc,
4266                         "XOFF Received");
4267         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
4268                         CTLFLAG_RD, &adapter->stats.xofftxc,
4269                         "XOFF Transmitted");
4270
4271         /* Packet Reception Stats */
4272         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
4273                         CTLFLAG_RD, &adapter->stats.tpr,
4274                         "Total Packets Received ");
4275         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
4276                         CTLFLAG_RD, &adapter->stats.gprc,
4277                         "Good Packets Received");
4278         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
4279                         CTLFLAG_RD, &adapter->stats.bprc,
4280                         "Broadcast Packets Received");
4281         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
4282                         CTLFLAG_RD, &adapter->stats.mprc,
4283                         "Multicast Packets Received");
4284         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
4285                         CTLFLAG_RD, &adapter->stats.prc64,
4286                         "64 byte frames received ");
4287         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
4288                         CTLFLAG_RD, &adapter->stats.prc127,
4289                         "65-127 byte frames received");
4290         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
4291                         CTLFLAG_RD, &adapter->stats.prc255,
4292                         "128-255 byte frames received");
4293         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
4294                         CTLFLAG_RD, &adapter->stats.prc511,
4295                         "256-511 byte frames received");
4296         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
4297                         CTLFLAG_RD, &adapter->stats.prc1023,
4298                         "512-1023 byte frames received");
4299         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
4300                         CTLFLAG_RD, &adapter->stats.prc1522,
4301                         "1023-1522 byte frames received");
4302         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
4303                         CTLFLAG_RD, &adapter->stats.gorc,
4304                         "Good Octets Received");
4305
4306         /* Packet Transmission Stats */
4307         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
4308                         CTLFLAG_RD, &adapter->stats.gotc,
4309                         "Good Octets Transmitted");
4310         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
4311                         CTLFLAG_RD, &adapter->stats.tpt,
4312                         "Total Packets Transmitted");
4313         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
4314                         CTLFLAG_RD, &adapter->stats.gptc,
4315                         "Good Packets Transmitted");
4316         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
4317                         CTLFLAG_RD, &adapter->stats.bptc,
4318                         "Broadcast Packets Transmitted");
4319         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
4320                         CTLFLAG_RD, &adapter->stats.mptc,
4321                         "Multicast Packets Transmitted");
4322         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
4323                         CTLFLAG_RD, &adapter->stats.ptc64,
4324                         "64 byte frames transmitted ");
4325         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
4326                         CTLFLAG_RD, &adapter->stats.ptc127,
4327                         "65-127 byte frames transmitted");
4328         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
4329                         CTLFLAG_RD, &adapter->stats.ptc255,
4330                         "128-255 byte frames transmitted");
4331         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
4332                         CTLFLAG_RD, &adapter->stats.ptc511,
4333                         "256-511 byte frames transmitted");
4334         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
4335                         CTLFLAG_RD, &adapter->stats.ptc1023,
4336                         "512-1023 byte frames transmitted");
4337         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
4338                         CTLFLAG_RD, &adapter->stats.ptc1522,
4339                         "1024-1522 byte frames transmitted");
4340         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
4341                         CTLFLAG_RD, &adapter->stats.tsctc,
4342                         "TSO Contexts Transmitted");
4343         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
4344                         CTLFLAG_RD, &adapter->stats.tsctfc,
4345                         "TSO Contexts Failed");
4346
4347
4348         /* Interrupt Stats */
4349
4350         int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
4351             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics");
4352         int_list = SYSCTL_CHILDREN(int_node);
4353
4354         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
4355                         CTLFLAG_RD, &adapter->stats.iac,
4356                         "Interrupt Assertion Count");
4357
4358         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
4359                         CTLFLAG_RD, &adapter->stats.icrxptc,
4360                         "Interrupt Cause Rx Pkt Timer Expire Count");
4361
4362         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
4363                         CTLFLAG_RD, &adapter->stats.icrxatc,
4364                         "Interrupt Cause Rx Abs Timer Expire Count");
4365
4366         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
4367                         CTLFLAG_RD, &adapter->stats.ictxptc,
4368                         "Interrupt Cause Tx Pkt Timer Expire Count");
4369
4370         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
4371                         CTLFLAG_RD, &adapter->stats.ictxatc,
4372                         "Interrupt Cause Tx Abs Timer Expire Count");
4373
4374         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
4375                         CTLFLAG_RD, &adapter->stats.ictxqec,
4376                         "Interrupt Cause Tx Queue Empty Count");
4377
4378         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
4379                         CTLFLAG_RD, &adapter->stats.ictxqmtc,
4380                         "Interrupt Cause Tx Queue Min Thresh Count");
4381
4382         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
4383                         CTLFLAG_RD, &adapter->stats.icrxdmtc,
4384                         "Interrupt Cause Rx Desc Min Thresh Count");
4385
4386         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
4387                         CTLFLAG_RD, &adapter->stats.icrxoc,
4388                         "Interrupt Cause Receiver Overrun Count");
4389 }
4390
4391 /**********************************************************************
4392  *
4393  *  This routine provides a way to dump out the adapter eeprom,
4394  *  often a useful debug/service tool. This only dumps the first
4395  *  32 words, stuff that matters is in that extent.
4396  *
4397  **********************************************************************/
4398 static int
4399 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4400 {
4401         struct adapter *adapter = (struct adapter *)arg1;
4402         int error;
4403         int result;
4404
4405         result = -1;
4406         error = sysctl_handle_int(oidp, &result, 0, req);
4407
4408         if (error || !req->newptr)
4409                 return (error);
4410
4411         /*
4412          * This value will cause a hex dump of the
4413          * first 32 16-bit words of the EEPROM to
4414          * the screen.
4415          */
4416         if (result == 1)
4417                 em_print_nvm_info(adapter);
4418
4419         return (error);
4420 }
4421
4422 static void
4423 em_print_nvm_info(struct adapter *adapter)
4424 {
4425         u16 eeprom_data;
4426         int i, j, row = 0;
4427
4428         /* Its a bit crude, but it gets the job done */
4429         printf("\nInterface EEPROM Dump:\n");
4430         printf("Offset\n0x0000  ");
4431         for (i = 0, j = 0; i < 32; i++, j++) {
4432                 if (j == 8) { /* Make the offset block */
4433                         j = 0; ++row;
4434                         printf("\n0x00%x0  ",row);
4435                 }
4436                 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
4437                 printf("%04x ", eeprom_data);
4438         }
4439         printf("\n");
4440 }
4441
4442 static int
4443 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4444 {
4445         struct em_int_delay_info *info;
4446         struct adapter *adapter;
4447         u32 regval;
4448         int error, usecs, ticks;
4449
4450         info = (struct em_int_delay_info *) arg1;
4451         usecs = info->value;
4452         error = sysctl_handle_int(oidp, &usecs, 0, req);
4453         if (error != 0 || req->newptr == NULL)
4454                 return (error);
4455         if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4456                 return (EINVAL);
4457         info->value = usecs;
4458         ticks = EM_USECS_TO_TICKS(usecs);
4459         if (info->offset == E1000_ITR)  /* units are 256ns here */
4460                 ticks *= 4;
4461
4462         adapter = info->adapter;
4463
4464         regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
4465         regval = (regval & ~0xffff) | (ticks & 0xffff);
4466         /* Handle a few special cases. */
4467         switch (info->offset) {
4468         case E1000_RDTR:
4469                 break;
4470         case E1000_TIDV:
4471                 if (ticks == 0) {
4472                         adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
4473                         /* Don't write 0 into the TIDV register. */
4474                         regval++;
4475                 } else
4476                         adapter->txd_cmd |= E1000_TXD_CMD_IDE;
4477                 break;
4478         }
4479         E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
4480         return (0);
4481 }
4482
4483 static void
4484 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
4485         const char *description, struct em_int_delay_info *info,
4486         int offset, int value)
4487 {
4488         info->adapter = adapter;
4489         info->offset = offset;
4490         info->value = value;
4491         SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev),
4492             SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4493             OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
4494             info, 0, em_sysctl_int_delay, "I", description);
4495 }
4496
4497 /*
4498  * Set flow control using sysctl:
4499  * Flow control values:
4500  *      0 - off
4501  *      1 - rx pause
4502  *      2 - tx pause
4503  *      3 - full
4504  */
4505 static int
4506 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4507 {
4508         int error;
4509         static int input = 3; /* default is full */
4510         struct adapter  *adapter = (struct adapter *) arg1;
4511
4512         error = sysctl_handle_int(oidp, &input, 0, req);
4513
4514         if ((error) || (req->newptr == NULL))
4515                 return (error);
4516
4517         if (input == adapter->fc) /* no change? */
4518                 return (error);
4519
4520         switch (input) {
4521         case e1000_fc_rx_pause:
4522         case e1000_fc_tx_pause:
4523         case e1000_fc_full:
4524         case e1000_fc_none:
4525                 adapter->hw.fc.requested_mode = input;
4526                 adapter->fc = input;
4527                 break;
4528         default:
4529                 /* Do nothing */
4530                 return (error);
4531         }
4532
4533         adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
4534         e1000_force_mac_fc(&adapter->hw);
4535         return (error);
4536 }
4537
4538 /*
4539  * Manage Energy Efficient Ethernet:
4540  * Control values:
4541  *     0/1 - enabled/disabled
4542  */
4543 static int
4544 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4545 {
4546         struct adapter *adapter = (struct adapter *) arg1;
4547         int error, value;
4548
4549         value = adapter->hw.dev_spec.ich8lan.eee_disable;
4550         error = sysctl_handle_int(oidp, &value, 0, req);
4551         if (error || req->newptr == NULL)
4552                 return (error);
4553         adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4554         em_if_init(adapter->ctx);
4555
4556         return (0);
4557 }
4558
4559 static int
4560 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4561 {
4562         struct adapter *adapter;
4563         int error;
4564         int result;
4565
4566         result = -1;
4567         error = sysctl_handle_int(oidp, &result, 0, req);
4568
4569         if (error || !req->newptr)
4570                 return (error);
4571
4572         if (result == 1) {
4573                 adapter = (struct adapter *) arg1;
4574                 em_print_debug_info(adapter);
4575         }
4576
4577         return (error);
4578 }
4579
4580 static int
4581 em_get_rs(SYSCTL_HANDLER_ARGS)
4582 {
4583         struct adapter *adapter = (struct adapter *) arg1;
4584         int error;
4585         int result;
4586
4587         result = 0;
4588         error = sysctl_handle_int(oidp, &result, 0, req);
4589
4590         if (error || !req->newptr || result != 1)
4591                 return (error);
4592         em_dump_rs(adapter);
4593
4594         return (error);
4595 }
4596
4597 static void
4598 em_if_debug(if_ctx_t ctx)
4599 {
4600         em_dump_rs(iflib_get_softc(ctx));
4601 }
4602
4603 /*
4604  * This routine is meant to be fluid, add whatever is
4605  * needed for debugging a problem.  -jfv
4606  */
4607 static void
4608 em_print_debug_info(struct adapter *adapter)
4609 {
4610         device_t dev = iflib_get_dev(adapter->ctx);
4611         struct ifnet *ifp = iflib_get_ifp(adapter->ctx);
4612         struct tx_ring *txr = &adapter->tx_queues->txr;
4613         struct rx_ring *rxr = &adapter->rx_queues->rxr;
4614
4615         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
4616                 printf("Interface is RUNNING ");
4617         else
4618                 printf("Interface is NOT RUNNING\n");
4619
4620         if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
4621                 printf("and INACTIVE\n");
4622         else
4623                 printf("and ACTIVE\n");
4624
4625         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
4626                 device_printf(dev, "TX Queue %d ------\n", i);
4627                 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
4628                         E1000_READ_REG(&adapter->hw, E1000_TDH(i)),
4629                         E1000_READ_REG(&adapter->hw, E1000_TDT(i)));
4630
4631         }
4632         for (int j=0; j < adapter->rx_num_queues; j++, rxr++) {
4633                 device_printf(dev, "RX Queue %d ------\n", j);
4634                 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
4635                         E1000_READ_REG(&adapter->hw, E1000_RDH(j)),
4636                         E1000_READ_REG(&adapter->hw, E1000_RDT(j)));
4637         }
4638 }
4639
4640 /*
4641  * 82574 only:
4642  * Write a new value to the EEPROM increasing the number of MSI-X
4643  * vectors from 3 to 5, for proper multiqueue support.
4644  */
4645 static void
4646 em_enable_vectors_82574(if_ctx_t ctx)
4647 {
4648         struct adapter *adapter = iflib_get_softc(ctx);
4649         struct e1000_hw *hw = &adapter->hw;
4650         device_t dev = iflib_get_dev(ctx);
4651         u16 edata;
4652
4653         e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4654         if (bootverbose)
4655                 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata);
4656         if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
4657                 device_printf(dev, "Writing to eeprom: increasing "
4658                     "reported MSI-X vectors from 3 to 5...\n");
4659                 edata &= ~(EM_NVM_MSIX_N_MASK);
4660                 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
4661                 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4662                 e1000_update_nvm_checksum(hw);
4663                 device_printf(dev, "Writing to eeprom: done\n");
4664         }
4665 }