2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <machine/_inttypes.h>
34 #define em_mac_min e1000_82571
35 #define igb_mac_min e1000_82575
37 /*********************************************************************
39 *********************************************************************/
40 char em_driver_version[] = "7.6.1-k";
42 /*********************************************************************
45 * Used by probe to select devices to load on
46 * Last field stores an index into e1000_strings
47 * Last entry must be all 0s
49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
50 *********************************************************************/
52 static pci_vendor_info_t em_vendor_info_array[] =
54 /* Intel(R) - lem-class legacy devices */
55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"),
56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"),
57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"),
58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"),
59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"),
61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"),
62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"),
63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"),
64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"),
65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"),
66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"),
67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"),
69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"),
71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"),
72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"),
74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"),
75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"),
76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"),
77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"),
79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"),
80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"),
81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"),
82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"),
83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"),
85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"),
86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"),
87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"),
88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"),
89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"),
90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"),
91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"),
92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"),
96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"),
97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"),
99 /* Intel(R) - em-class devices */
100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"),
101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"),
102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"),
103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"),
104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"),
105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"),
108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"),
109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"),
110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"),
111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"),
112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"),
113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"),
114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"),
115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"),
116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"),
117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"),
118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"),
119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"),
120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"),
121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"),
122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"),
123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"),
124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"),
125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"),
126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"),
127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"),
128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"),
129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"),
130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"),
131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"),
132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"),
133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"),
134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"),
135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"),
136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"),
137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"),
138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"),
139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"),
140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"),
141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"),
142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"),
143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"),
144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"),
145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"),
146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"),
147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"),
148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"),
149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"),
150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"),
151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"),
152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"),
153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"),
154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"),
155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"),
156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"),
157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"),
158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"),
159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"),
160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"),
161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"),
162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"),
163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"),
164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"),
165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"),
166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"),
167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"),
168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"),
169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"),
170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"),
171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"),
172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"),
173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"),
174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"),
175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"),
176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"),
177 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"),
178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"),
179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"),
180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"),
181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"),
182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"),
183 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"),
184 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"),
185 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"),
186 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"),
187 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"),
188 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"),
189 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"),
190 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"),
191 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"),
192 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"),
193 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"),
194 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"),
195 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"),
196 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"),
197 /* required last entry */
201 static pci_vendor_info_t igb_vendor_info_array[] =
203 /* Intel(R) - igb-class devices */
204 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"),
205 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"),
206 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"),
207 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"),
208 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"),
209 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"),
210 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"),
211 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"),
212 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"),
213 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"),
214 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"),
215 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"),
216 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"),
217 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"),
218 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"),
219 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"),
220 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"),
221 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"),
222 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"),
223 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"),
224 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"),
225 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"),
226 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"),
227 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"),
228 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"),
229 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"),
230 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"),
231 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"),
232 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"),
233 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"),
234 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"),
235 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"),
236 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"),
237 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"),
238 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"),
239 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"),
240 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"),
241 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"),
242 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"),
243 /* required last entry */
247 /*********************************************************************
248 * Function prototypes
249 *********************************************************************/
250 static void *em_register(device_t dev);
251 static void *igb_register(device_t dev);
252 static int em_if_attach_pre(if_ctx_t ctx);
253 static int em_if_attach_post(if_ctx_t ctx);
254 static int em_if_detach(if_ctx_t ctx);
255 static int em_if_shutdown(if_ctx_t ctx);
256 static int em_if_suspend(if_ctx_t ctx);
257 static int em_if_resume(if_ctx_t ctx);
259 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets);
260 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets);
261 static void em_if_queues_free(if_ctx_t ctx);
263 static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
264 static void em_if_init(if_ctx_t ctx);
265 static void em_if_stop(if_ctx_t ctx);
266 static void em_if_media_status(if_ctx_t, struct ifmediareq *);
267 static int em_if_media_change(if_ctx_t ctx);
268 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu);
269 static void em_if_timer(if_ctx_t ctx, uint16_t qid);
270 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag);
271 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag);
272 static void em_if_watchdog_reset(if_ctx_t ctx);
273 static bool em_if_needs_restart(if_ctx_t ctx, enum iflib_restart_event event);
275 static void em_identify_hardware(if_ctx_t ctx);
276 static int em_allocate_pci_resources(if_ctx_t ctx);
277 static void em_free_pci_resources(if_ctx_t ctx);
278 static void em_reset(if_ctx_t ctx);
279 static int em_setup_interface(if_ctx_t ctx);
280 static int em_setup_msix(if_ctx_t ctx);
282 static void em_initialize_transmit_unit(if_ctx_t ctx);
283 static void em_initialize_receive_unit(if_ctx_t ctx);
285 static void em_if_intr_enable(if_ctx_t ctx);
286 static void em_if_intr_disable(if_ctx_t ctx);
287 static void igb_if_intr_enable(if_ctx_t ctx);
288 static void igb_if_intr_disable(if_ctx_t ctx);
289 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
290 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
291 static int igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
292 static int igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
293 static void em_if_multi_set(if_ctx_t ctx);
294 static void em_if_update_admin_status(if_ctx_t ctx);
295 static void em_if_debug(if_ctx_t ctx);
296 static void em_update_stats_counters(struct adapter *);
297 static void em_add_hw_stats(struct adapter *adapter);
298 static int em_if_set_promisc(if_ctx_t ctx, int flags);
299 static void em_setup_vlan_hw_support(struct adapter *);
300 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
301 static void em_print_nvm_info(struct adapter *);
302 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
303 static int em_get_rs(SYSCTL_HANDLER_ARGS);
304 static void em_print_debug_info(struct adapter *);
305 static int em_is_valid_ether_addr(u8 *);
306 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
307 static void em_add_int_delay_sysctl(struct adapter *, const char *,
308 const char *, struct em_int_delay_info *, int, int);
309 /* Management and WOL Support */
310 static void em_init_manageability(struct adapter *);
311 static void em_release_manageability(struct adapter *);
312 static void em_get_hw_control(struct adapter *);
313 static void em_release_hw_control(struct adapter *);
314 static void em_get_wakeup(if_ctx_t ctx);
315 static void em_enable_wakeup(if_ctx_t ctx);
316 static int em_enable_phy_wakeup(struct adapter *);
317 static void em_disable_aspm(struct adapter *);
319 int em_intr(void *arg);
322 static int em_if_msix_intr_assign(if_ctx_t, int);
323 static int em_msix_link(void *);
324 static void em_handle_link(void *context);
326 static void em_enable_vectors_82574(if_ctx_t);
328 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS);
329 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS);
330 static void em_if_led_func(if_ctx_t ctx, int onoff);
332 static int em_get_regs(SYSCTL_HANDLER_ARGS);
334 static void lem_smartspeed(struct adapter *adapter);
335 static void igb_configure_queues(struct adapter *adapter);
338 /*********************************************************************
339 * FreeBSD Device Interface Entry Points
340 *********************************************************************/
341 static device_method_t em_methods[] = {
342 /* Device interface */
343 DEVMETHOD(device_register, em_register),
344 DEVMETHOD(device_probe, iflib_device_probe),
345 DEVMETHOD(device_attach, iflib_device_attach),
346 DEVMETHOD(device_detach, iflib_device_detach),
347 DEVMETHOD(device_shutdown, iflib_device_shutdown),
348 DEVMETHOD(device_suspend, iflib_device_suspend),
349 DEVMETHOD(device_resume, iflib_device_resume),
353 static device_method_t igb_methods[] = {
354 /* Device interface */
355 DEVMETHOD(device_register, igb_register),
356 DEVMETHOD(device_probe, iflib_device_probe),
357 DEVMETHOD(device_attach, iflib_device_attach),
358 DEVMETHOD(device_detach, iflib_device_detach),
359 DEVMETHOD(device_shutdown, iflib_device_shutdown),
360 DEVMETHOD(device_suspend, iflib_device_suspend),
361 DEVMETHOD(device_resume, iflib_device_resume),
366 static driver_t em_driver = {
367 "em", em_methods, sizeof(struct adapter),
370 static devclass_t em_devclass;
371 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
373 MODULE_DEPEND(em, pci, 1, 1, 1);
374 MODULE_DEPEND(em, ether, 1, 1, 1);
375 MODULE_DEPEND(em, iflib, 1, 1, 1);
377 IFLIB_PNP_INFO(pci, em, em_vendor_info_array);
379 static driver_t igb_driver = {
380 "igb", igb_methods, sizeof(struct adapter),
383 static devclass_t igb_devclass;
384 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
386 MODULE_DEPEND(igb, pci, 1, 1, 1);
387 MODULE_DEPEND(igb, ether, 1, 1, 1);
388 MODULE_DEPEND(igb, iflib, 1, 1, 1);
390 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array);
392 static device_method_t em_if_methods[] = {
393 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
394 DEVMETHOD(ifdi_attach_post, em_if_attach_post),
395 DEVMETHOD(ifdi_detach, em_if_detach),
396 DEVMETHOD(ifdi_shutdown, em_if_shutdown),
397 DEVMETHOD(ifdi_suspend, em_if_suspend),
398 DEVMETHOD(ifdi_resume, em_if_resume),
399 DEVMETHOD(ifdi_init, em_if_init),
400 DEVMETHOD(ifdi_stop, em_if_stop),
401 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
402 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable),
403 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable),
404 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
405 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
406 DEVMETHOD(ifdi_queues_free, em_if_queues_free),
407 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
408 DEVMETHOD(ifdi_multi_set, em_if_multi_set),
409 DEVMETHOD(ifdi_media_status, em_if_media_status),
410 DEVMETHOD(ifdi_media_change, em_if_media_change),
411 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
412 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
413 DEVMETHOD(ifdi_timer, em_if_timer),
414 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
415 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
416 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
417 DEVMETHOD(ifdi_get_counter, em_if_get_counter),
418 DEVMETHOD(ifdi_led_func, em_if_led_func),
419 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable),
420 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable),
421 DEVMETHOD(ifdi_debug, em_if_debug),
422 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart),
426 static driver_t em_if_driver = {
427 "em_if", em_if_methods, sizeof(struct adapter)
430 static device_method_t igb_if_methods[] = {
431 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
432 DEVMETHOD(ifdi_attach_post, em_if_attach_post),
433 DEVMETHOD(ifdi_detach, em_if_detach),
434 DEVMETHOD(ifdi_shutdown, em_if_shutdown),
435 DEVMETHOD(ifdi_suspend, em_if_suspend),
436 DEVMETHOD(ifdi_resume, em_if_resume),
437 DEVMETHOD(ifdi_init, em_if_init),
438 DEVMETHOD(ifdi_stop, em_if_stop),
439 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
440 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable),
441 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable),
442 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
443 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
444 DEVMETHOD(ifdi_queues_free, em_if_queues_free),
445 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
446 DEVMETHOD(ifdi_multi_set, em_if_multi_set),
447 DEVMETHOD(ifdi_media_status, em_if_media_status),
448 DEVMETHOD(ifdi_media_change, em_if_media_change),
449 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
450 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
451 DEVMETHOD(ifdi_timer, em_if_timer),
452 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
453 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
454 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
455 DEVMETHOD(ifdi_get_counter, em_if_get_counter),
456 DEVMETHOD(ifdi_led_func, em_if_led_func),
457 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable),
458 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable),
459 DEVMETHOD(ifdi_debug, em_if_debug),
460 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart),
464 static driver_t igb_if_driver = {
465 "igb_if", igb_if_methods, sizeof(struct adapter)
468 /*********************************************************************
469 * Tunable default values.
470 *********************************************************************/
472 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000)
473 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024)
475 #define MAX_INTS_PER_SEC 8000
476 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256))
478 /* Allow common code without TSO */
483 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
484 "EM driver parameters");
486 static int em_disable_crc_stripping = 0;
487 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
488 &em_disable_crc_stripping, 0, "Disable CRC Stripping");
490 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
491 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
492 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
493 0, "Default transmit interrupt delay in usecs");
494 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
495 0, "Default receive interrupt delay in usecs");
497 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
498 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
499 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
500 &em_tx_abs_int_delay_dflt, 0,
501 "Default transmit interrupt delay limit in usecs");
502 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
503 &em_rx_abs_int_delay_dflt, 0,
504 "Default receive interrupt delay limit in usecs");
506 static int em_smart_pwr_down = FALSE;
507 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
508 0, "Set to true to leave smart power down enabled on newer adapters");
510 /* Controls whether promiscuous also shows bad packets */
511 static int em_debug_sbp = FALSE;
512 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
513 "Show bad packets in promiscuous mode");
515 /* How many packets rxeof tries to clean at a time */
516 static int em_rx_process_limit = 100;
517 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
518 &em_rx_process_limit, 0,
519 "Maximum number of received packets to process "
520 "at a time, -1 means unlimited");
522 /* Energy efficient ethernet - default to OFF */
523 static int eee_setting = 1;
524 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
525 "Enable Energy Efficient Ethernet");
528 ** Tuneable Interrupt rate
530 static int em_max_interrupt_rate = 8000;
531 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
532 &em_max_interrupt_rate, 0, "Maximum interrupts per second");
536 /* Global used in WOL setup with multiport cards */
537 static int global_quad_port_a = 0;
539 extern struct if_txrx igb_txrx;
540 extern struct if_txrx em_txrx;
541 extern struct if_txrx lem_txrx;
543 static struct if_shared_ctx em_sctx_init = {
544 .isc_magic = IFLIB_MAGIC,
545 .isc_q_align = PAGE_SIZE,
546 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
547 .isc_tx_maxsegsize = PAGE_SIZE,
548 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
549 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
550 .isc_rx_maxsize = MJUM9BYTES,
551 .isc_rx_nsegments = 1,
552 .isc_rx_maxsegsize = MJUM9BYTES,
556 .isc_admin_intrcnt = 1,
557 .isc_vendor_info = em_vendor_info_array,
558 .isc_driver_version = em_driver_version,
559 .isc_driver = &em_if_driver,
560 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
562 .isc_nrxd_min = {EM_MIN_RXD},
563 .isc_ntxd_min = {EM_MIN_TXD},
564 .isc_nrxd_max = {EM_MAX_RXD},
565 .isc_ntxd_max = {EM_MAX_TXD},
566 .isc_nrxd_default = {EM_DEFAULT_RXD},
567 .isc_ntxd_default = {EM_DEFAULT_TXD},
570 static struct if_shared_ctx igb_sctx_init = {
571 .isc_magic = IFLIB_MAGIC,
572 .isc_q_align = PAGE_SIZE,
573 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
574 .isc_tx_maxsegsize = PAGE_SIZE,
575 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
576 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
577 .isc_rx_maxsize = MJUM9BYTES,
578 .isc_rx_nsegments = 1,
579 .isc_rx_maxsegsize = MJUM9BYTES,
583 .isc_admin_intrcnt = 1,
584 .isc_vendor_info = igb_vendor_info_array,
585 .isc_driver_version = em_driver_version,
586 .isc_driver = &igb_if_driver,
587 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
589 .isc_nrxd_min = {EM_MIN_RXD},
590 .isc_ntxd_min = {EM_MIN_TXD},
591 .isc_nrxd_max = {IGB_MAX_RXD},
592 .isc_ntxd_max = {IGB_MAX_TXD},
593 .isc_nrxd_default = {EM_DEFAULT_RXD},
594 .isc_ntxd_default = {EM_DEFAULT_TXD},
597 /*****************************************************************
601 ****************************************************************/
602 #define IGB_REGS_LEN 739
604 static int em_get_regs(SYSCTL_HANDLER_ARGS)
606 struct adapter *adapter = (struct adapter *)arg1;
607 struct e1000_hw *hw = &adapter->hw;
612 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK);
613 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
615 rc = sysctl_wire_old_buffer(req, 0);
618 free(regs_buff, M_DEVBUF);
622 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
625 free(regs_buff, M_DEVBUF);
629 /* General Registers */
630 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
631 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
632 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
633 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
634 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
635 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
636 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
637 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
638 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
639 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
640 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
641 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
642 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
643 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
644 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
645 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
646 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
647 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
648 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
649 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
650 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
651 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
653 sbuf_printf(sb, "General Registers\n");
654 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
655 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
656 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]);
658 sbuf_printf(sb, "Interrupt Registers\n");
659 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
661 sbuf_printf(sb, "RX Registers\n");
662 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
663 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
664 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
665 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
666 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
667 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
668 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
670 sbuf_printf(sb, "TX Registers\n");
671 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
672 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
673 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
674 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
675 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
676 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
677 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
678 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
679 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
680 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
681 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
683 free(regs_buff, M_DEVBUF);
687 if_softc_ctx_t scctx = adapter->shared;
688 struct rx_ring *rxr = &rx_que->rxr;
689 struct tx_ring *txr = &tx_que->txr;
690 int ntxd = scctx->isc_ntxd[0];
691 int nrxd = scctx->isc_nrxd[0];
694 for (j = 0; j < nrxd; j++) {
695 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
696 u32 length = le32toh(rxr->rx_base[j].wb.upper.length);
697 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
700 for (j = 0; j < min(ntxd, 256); j++) {
701 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
703 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n",
704 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
705 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
711 rc = sbuf_finish(sb);
717 em_register(device_t dev)
719 return (&em_sctx_init);
723 igb_register(device_t dev)
725 return (&igb_sctx_init);
729 em_set_num_queues(if_ctx_t ctx)
731 struct adapter *adapter = iflib_get_softc(ctx);
734 /* Sanity check based on HW */
735 switch (adapter->hw.mac.type) {
759 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
760 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER
763 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
764 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \
765 IFCAP_LRO | IFCAP_VLAN_HWTSO
768 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
769 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \
770 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\
773 /*********************************************************************
774 * Device initialization routine
776 * The attach entry point is called when the driver is being loaded.
777 * This routine identifies the type of hardware, allocates all resources
778 * and initializes the hardware.
780 * return 0 on success, positive on failure
781 *********************************************************************/
783 em_if_attach_pre(if_ctx_t ctx)
785 struct adapter *adapter;
786 if_softc_ctx_t scctx;
791 INIT_DEBUGOUT("em_if_attach_pre: begin");
792 dev = iflib_get_dev(ctx);
793 adapter = iflib_get_softc(ctx);
795 adapter->ctx = adapter->osdep.ctx = ctx;
796 adapter->dev = adapter->osdep.dev = dev;
797 scctx = adapter->shared = iflib_get_softc_ctx(ctx);
798 adapter->media = iflib_get_media(ctx);
801 adapter->tx_process_limit = scctx->isc_ntxd[0];
804 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
805 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
806 OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
807 adapter, 0, em_sysctl_nvm_info, "I", "NVM Information");
809 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
810 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
811 OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
812 adapter, 0, em_sysctl_debug_info, "I", "Debug Information");
814 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
815 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
816 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
817 adapter, 0, em_set_flowcntl, "I", "Flow Control");
819 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
820 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
821 OID_AUTO, "reg_dump",
822 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 0,
823 em_get_regs, "A", "Dump Registers");
825 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
826 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
828 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, adapter, 0,
829 em_get_rs, "I", "Dump RS indexes");
831 /* Determine hardware and mac info */
832 em_identify_hardware(ctx);
834 scctx->isc_tx_nsegments = EM_MAX_SCATTER;
835 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
837 device_printf(dev, "attach_pre capping queues at %d\n",
838 scctx->isc_ntxqsets_max);
840 if (hw->mac.type >= igb_mac_min) {
841 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
842 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
843 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
844 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
845 scctx->isc_txrx = &igb_txrx;
846 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
847 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
848 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
849 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS;
850 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO |
851 CSUM_IP6_TCP | CSUM_IP6_UDP;
852 if (hw->mac.type != e1000_82575)
853 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
855 ** Some new devices, as with ixgbe, now may
856 ** use a different BAR, so we need to keep
857 ** track of which is used.
859 scctx->isc_msix_bar = pci_msix_table_bar(dev);
860 } else if (hw->mac.type >= em_mac_min) {
861 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
862 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
863 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
864 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
865 scctx->isc_txrx = &em_txrx;
866 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
867 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
868 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
869 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS;
871 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO}
872 * by default as we don't have workarounds for all associated
873 * silicon errata. E. g., with several MACs such as 82573E,
874 * TSO only works at Gigabit speed and otherwise can cause the
875 * hardware to hang (which also would be next to impossible to
876 * work around given that already queued TSO-using descriptors
877 * would need to be flushed and vlan(4) reconfigured at runtime
878 * in case of a link speed change). Moreover, MACs like 82579
879 * still can hang at Gigabit even with all publicly documented
880 * TSO workarounds implemented. Generally, the penality of
881 * these workarounds is rather high and may involve copying
882 * mbuf data around so advantages of TSO lapse. Still, TSO may
883 * work for a few MACs of this class - at least when sticking
884 * with Gigabit - in which case users may enable TSO manually.
886 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
887 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
889 * We support MSI-X with 82574 only, but indicate to iflib(4)
890 * that it shall give MSI at least a try with other devices.
892 if (hw->mac.type == e1000_82574) {
893 scctx->isc_msix_bar = pci_msix_table_bar(dev);;
895 scctx->isc_msix_bar = -1;
896 scctx->isc_disable_msix = 1;
899 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
900 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
901 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
902 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
903 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP;
904 scctx->isc_txrx = &lem_txrx;
905 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS;
906 if (hw->mac.type < e1000_82543)
907 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
909 scctx->isc_msix_bar = 0;
912 /* Setup PCI resources */
913 if (em_allocate_pci_resources(ctx)) {
914 device_printf(dev, "Allocation of PCI resources failed\n");
920 ** For ICH8 and family we need to
921 ** map the flash memory, and this
922 ** must happen after the MAC is
925 if ((hw->mac.type == e1000_ich8lan) ||
926 (hw->mac.type == e1000_ich9lan) ||
927 (hw->mac.type == e1000_ich10lan) ||
928 (hw->mac.type == e1000_pchlan) ||
929 (hw->mac.type == e1000_pch2lan) ||
930 (hw->mac.type == e1000_pch_lpt)) {
931 int rid = EM_BAR_TYPE_FLASH;
932 adapter->flash = bus_alloc_resource_any(dev,
933 SYS_RES_MEMORY, &rid, RF_ACTIVE);
934 if (adapter->flash == NULL) {
935 device_printf(dev, "Mapping of Flash failed\n");
939 /* This is used in the shared code */
940 hw->flash_address = (u8 *)adapter->flash;
941 adapter->osdep.flash_bus_space_tag =
942 rman_get_bustag(adapter->flash);
943 adapter->osdep.flash_bus_space_handle =
944 rman_get_bushandle(adapter->flash);
947 ** In the new SPT device flash is not a
948 ** separate BAR, rather it is also in BAR0,
949 ** so use the same tag and an offset handle for the
950 ** FLASH read/write macros in the shared code.
952 else if (hw->mac.type >= e1000_pch_spt) {
953 adapter->osdep.flash_bus_space_tag =
954 adapter->osdep.mem_bus_space_tag;
955 adapter->osdep.flash_bus_space_handle =
956 adapter->osdep.mem_bus_space_handle
957 + E1000_FLASH_BASE_ADDR;
960 /* Do Shared Code initialization */
961 error = e1000_setup_init_funcs(hw, TRUE);
963 device_printf(dev, "Setup of Shared code failed, error %d\n",
970 e1000_get_bus_info(hw);
972 /* Set up some sysctls for the tunable interrupt delays */
973 em_add_int_delay_sysctl(adapter, "rx_int_delay",
974 "receive interrupt delay in usecs", &adapter->rx_int_delay,
975 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
976 em_add_int_delay_sysctl(adapter, "tx_int_delay",
977 "transmit interrupt delay in usecs", &adapter->tx_int_delay,
978 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
979 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
980 "receive interrupt delay limit in usecs",
981 &adapter->rx_abs_int_delay,
982 E1000_REGISTER(hw, E1000_RADV),
983 em_rx_abs_int_delay_dflt);
984 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
985 "transmit interrupt delay limit in usecs",
986 &adapter->tx_abs_int_delay,
987 E1000_REGISTER(hw, E1000_TADV),
988 em_tx_abs_int_delay_dflt);
989 em_add_int_delay_sysctl(adapter, "itr",
990 "interrupt delay limit in usecs/4",
992 E1000_REGISTER(hw, E1000_ITR),
995 hw->mac.autoneg = DO_AUTO_NEG;
996 hw->phy.autoneg_wait_to_complete = FALSE;
997 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
999 if (hw->mac.type < em_mac_min) {
1000 e1000_init_script_state_82541(hw, TRUE);
1001 e1000_set_tbi_compatibility_82543(hw, TRUE);
1003 /* Copper options */
1004 if (hw->phy.media_type == e1000_media_type_copper) {
1005 hw->phy.mdix = AUTO_ALL_MODES;
1006 hw->phy.disable_polarity_correction = FALSE;
1007 hw->phy.ms_type = EM_MASTER_SLAVE;
1011 * Set the frame limits assuming
1012 * standard ethernet sized frames.
1014 scctx->isc_max_frame_size = hw->mac.max_frame_size =
1015 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
1018 * This controls when hardware reports transmit completion
1021 hw->mac.report_tx_early = 1;
1023 /* Allocate multicast array memory. */
1024 adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN *
1025 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
1026 if (adapter->mta == NULL) {
1027 device_printf(dev, "Can not allocate multicast setup array\n");
1032 /* Check SOL/IDER usage */
1033 if (e1000_check_reset_block(hw))
1034 device_printf(dev, "PHY reset is blocked"
1035 " due to SOL/IDER session.\n");
1037 /* Sysctl for setting Energy Efficient Ethernet */
1038 hw->dev_spec.ich8lan.eee_disable = eee_setting;
1039 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1040 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1041 OID_AUTO, "eee_control",
1042 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
1043 adapter, 0, em_sysctl_eee, "I",
1044 "Disable Energy Efficient Ethernet");
1047 ** Start from a known state, this is
1048 ** important in reading the nvm and
1053 /* Make sure we have a good EEPROM before we read from it */
1054 if (e1000_validate_nvm_checksum(hw) < 0) {
1056 ** Some PCI-E parts fail the first check due to
1057 ** the link being in sleep state, call it again,
1058 ** if it fails a second time its a real issue.
1060 if (e1000_validate_nvm_checksum(hw) < 0) {
1062 "The EEPROM Checksum Is Not Valid\n");
1068 /* Copy the permanent MAC address out of the EEPROM */
1069 if (e1000_read_mac_addr(hw) < 0) {
1070 device_printf(dev, "EEPROM read error while reading MAC"
1076 if (!em_is_valid_ether_addr(hw->mac.addr)) {
1077 if (adapter->vf_ifp) {
1078 u8 addr[ETHER_ADDR_LEN];
1079 arc4rand(&addr, sizeof(addr), 0);
1082 bcopy(addr, hw->mac.addr, sizeof(addr));
1084 device_printf(dev, "Invalid MAC address\n");
1090 /* Disable ULP support */
1091 e1000_disable_ulp_lpt_lp(hw, TRUE);
1094 * Get Wake-on-Lan and Management info for later use
1098 /* Enable only WOL MAGIC by default */
1099 scctx->isc_capenable &= ~IFCAP_WOL;
1100 if (adapter->wol != 0)
1101 scctx->isc_capenable |= IFCAP_WOL_MAGIC;
1103 iflib_set_mac(ctx, hw->mac.addr);
1108 em_release_hw_control(adapter);
1110 em_free_pci_resources(ctx);
1111 free(adapter->mta, M_DEVBUF);
1117 em_if_attach_post(if_ctx_t ctx)
1119 struct adapter *adapter = iflib_get_softc(ctx);
1120 struct e1000_hw *hw = &adapter->hw;
1123 /* Setup OS specific network interface */
1124 error = em_setup_interface(ctx);
1126 device_printf(adapter->dev, "Interface setup failed: %d\n", error);
1132 /* Initialize statistics */
1133 em_update_stats_counters(adapter);
1134 hw->mac.get_link_status = 1;
1135 em_if_update_admin_status(ctx);
1136 em_add_hw_stats(adapter);
1138 /* Non-AMT based hardware can now take control from firmware */
1139 if (adapter->has_manage && !adapter->has_amt)
1140 em_get_hw_control(adapter);
1142 INIT_DEBUGOUT("em_if_attach_post: end");
1147 /* upon attach_post() error, iflib calls _if_detach() to free resources. */
1151 /*********************************************************************
1152 * Device removal routine
1154 * The detach entry point is called when the driver is being removed.
1155 * This routine stops the adapter and deallocates all the resources
1156 * that were allocated for driver operation.
1158 * return 0 on success, positive on failure
1159 *********************************************************************/
1161 em_if_detach(if_ctx_t ctx)
1163 struct adapter *adapter = iflib_get_softc(ctx);
1165 INIT_DEBUGOUT("em_if_detach: begin");
1167 e1000_phy_hw_reset(&adapter->hw);
1169 em_release_manageability(adapter);
1170 em_release_hw_control(adapter);
1171 em_free_pci_resources(ctx);
1172 free(adapter->mta, M_DEVBUF);
1173 adapter->mta = NULL;
1178 /*********************************************************************
1180 * Shutdown entry point
1182 **********************************************************************/
1185 em_if_shutdown(if_ctx_t ctx)
1187 return em_if_suspend(ctx);
1191 * Suspend/resume device methods.
1194 em_if_suspend(if_ctx_t ctx)
1196 struct adapter *adapter = iflib_get_softc(ctx);
1198 em_release_manageability(adapter);
1199 em_release_hw_control(adapter);
1200 em_enable_wakeup(ctx);
1205 em_if_resume(if_ctx_t ctx)
1207 struct adapter *adapter = iflib_get_softc(ctx);
1209 if (adapter->hw.mac.type == e1000_pch2lan)
1210 e1000_resume_workarounds_pchlan(&adapter->hw);
1212 em_init_manageability(adapter);
1218 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1221 struct adapter *adapter = iflib_get_softc(ctx);
1222 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1224 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1226 switch (adapter->hw.mac.type) {
1230 case e1000_ich10lan:
1240 case e1000_80003es2lan:
1241 /* 9K Jumbo Frame size */
1242 max_frame_size = 9234;
1245 max_frame_size = 4096;
1249 /* Adapters that do not support jumbo frames */
1250 max_frame_size = ETHER_MAX_LEN;
1253 if (adapter->hw.mac.type >= igb_mac_min)
1254 max_frame_size = 9234;
1256 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1258 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1262 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
1263 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1267 /*********************************************************************
1270 * This routine is used in two ways. It is used by the stack as
1271 * init entry point in network interface structure. It is also used
1272 * by the driver as a hw/sw initialization routine to get to a
1275 **********************************************************************/
1277 em_if_init(if_ctx_t ctx)
1279 struct adapter *adapter = iflib_get_softc(ctx);
1280 if_softc_ctx_t scctx = adapter->shared;
1281 struct ifnet *ifp = iflib_get_ifp(ctx);
1282 struct em_tx_queue *tx_que;
1285 INIT_DEBUGOUT("em_if_init: begin");
1287 /* Get the latest mac address, User can use a LAA */
1288 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr,
1291 /* Put the address into the Receive Address Array */
1292 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1295 * With the 82571 adapter, RAR[0] may be overwritten
1296 * when the other port is reset, we make a duplicate
1297 * in RAR[14] for that eventuality, this assures
1298 * the interface continues to function.
1300 if (adapter->hw.mac.type == e1000_82571) {
1301 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1302 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1303 E1000_RAR_ENTRIES - 1);
1307 /* Initialize the hardware */
1309 em_if_update_admin_status(ctx);
1311 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) {
1312 struct tx_ring *txr = &tx_que->txr;
1314 txr->tx_rs_cidx = txr->tx_rs_pidx;
1316 /* Initialize the last processed descriptor to be the end of
1317 * the ring, rather than the start, so that we avoid an
1318 * off-by-one error when calculating how many descriptors are
1319 * done in the credits_update function.
1321 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
1324 /* Setup VLAN support, basic and offload if available */
1325 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1327 /* Clear bad data from Rx FIFOs */
1328 if (adapter->hw.mac.type >= igb_mac_min)
1329 e1000_rx_fifo_flush_82575(&adapter->hw);
1331 /* Configure for OS presence */
1332 em_init_manageability(adapter);
1334 /* Prepare transmit descriptors and buffers */
1335 em_initialize_transmit_unit(ctx);
1337 /* Setup Multicast table */
1338 em_if_multi_set(ctx);
1340 adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx);
1341 em_initialize_receive_unit(ctx);
1343 /* Use real VLAN Filter support? */
1344 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1345 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
1346 /* Use real VLAN Filter support */
1347 em_setup_vlan_hw_support(adapter);
1350 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1351 ctrl |= E1000_CTRL_VME;
1352 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1356 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1357 ctrl &= ~E1000_CTRL_VME;
1358 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1361 /* Don't lose promiscuous settings */
1362 em_if_set_promisc(ctx, if_getflags(ifp));
1363 e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1365 /* MSI-X configuration for 82574 */
1366 if (adapter->hw.mac.type == e1000_82574) {
1367 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1369 tmp |= E1000_CTRL_EXT_PBA_CLR;
1370 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1371 /* Set the IVAR - interrupt vector routing. */
1372 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars);
1373 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1374 igb_configure_queues(adapter);
1376 /* this clears any pending interrupts */
1377 E1000_READ_REG(&adapter->hw, E1000_ICR);
1378 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC);
1380 /* AMT based hardware can now take control from firmware */
1381 if (adapter->has_manage && adapter->has_amt)
1382 em_get_hw_control(adapter);
1384 /* Set Energy Efficient Ethernet */
1385 if (adapter->hw.mac.type >= igb_mac_min &&
1386 adapter->hw.phy.media_type == e1000_media_type_copper) {
1387 if (adapter->hw.mac.type == e1000_i354)
1388 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
1390 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
1394 /*********************************************************************
1396 * Fast Legacy/MSI Combined Interrupt Service routine
1398 *********************************************************************/
1402 struct adapter *adapter = arg;
1403 if_ctx_t ctx = adapter->ctx;
1406 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1409 if (reg_icr == 0xffffffff)
1410 return FILTER_STRAY;
1412 /* Definitely not our interrupt. */
1414 return FILTER_STRAY;
1417 * Starting with the 82571 chip, bit 31 should be used to
1418 * determine whether the interrupt belongs to us.
1420 if (adapter->hw.mac.type >= e1000_82571 &&
1421 (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1422 return FILTER_STRAY;
1425 * Only MSI-X interrupts have one-shot behavior by taking advantage
1426 * of the EIAC register. Thus, explicitly disable interrupts. This
1427 * also works around the MSI message reordering errata on certain
1430 IFDI_INTR_DISABLE(ctx);
1432 /* Link status change */
1433 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))
1434 em_handle_link(ctx);
1436 if (reg_icr & E1000_ICR_RXO)
1437 adapter->rx_overruns++;
1439 return (FILTER_SCHEDULE_THREAD);
1443 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1445 struct adapter *adapter = iflib_get_softc(ctx);
1446 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1448 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims);
1453 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1455 struct adapter *adapter = iflib_get_softc(ctx);
1456 struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1458 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims);
1463 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1465 struct adapter *adapter = iflib_get_softc(ctx);
1466 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1468 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims);
1473 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1475 struct adapter *adapter = iflib_get_softc(ctx);
1476 struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1478 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims);
1482 /*********************************************************************
1484 * MSI-X RX Interrupt Service routine
1486 **********************************************************************/
1488 em_msix_que(void *arg)
1490 struct em_rx_queue *que = arg;
1494 return (FILTER_SCHEDULE_THREAD);
1497 /*********************************************************************
1499 * MSI-X Link Fast Interrupt Service routine
1501 **********************************************************************/
1503 em_msix_link(void *arg)
1505 struct adapter *adapter = arg;
1507 bool notlink = false;
1509 ++adapter->link_irq;
1510 MPASS(adapter->hw.back != NULL);
1511 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1513 if (reg_icr & E1000_ICR_RXO)
1514 adapter->rx_overruns++;
1516 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))
1517 em_handle_link(adapter->ctx);
1521 /* Re-arm for other/spurious interrupts */
1522 if (notlink && adapter->hw.mac.type >= igb_mac_min) {
1523 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC);
1524 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1525 } else if (adapter->hw.mac.type == e1000_82574) {
1527 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC |
1530 * Because we must read the ICR for this interrupt it may
1531 * clear other causes using autoclear, for this reason we
1532 * simply create a soft interrupt for all these vectors.
1535 E1000_WRITE_REG(&adapter->hw, E1000_ICS, adapter->ims);
1538 return (FILTER_HANDLED);
1542 em_handle_link(void *context)
1544 if_ctx_t ctx = context;
1545 struct adapter *adapter = iflib_get_softc(ctx);
1547 adapter->hw.mac.get_link_status = 1;
1548 iflib_admin_intr_deferred(ctx);
1551 /*********************************************************************
1553 * Media Ioctl callback
1555 * This routine is called whenever the user queries the status of
1556 * the interface using ifconfig.
1558 **********************************************************************/
1560 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1562 struct adapter *adapter = iflib_get_softc(ctx);
1563 u_char fiber_type = IFM_1000_SX;
1565 INIT_DEBUGOUT("em_if_media_status: begin");
1567 iflib_admin_intr_deferred(ctx);
1569 ifmr->ifm_status = IFM_AVALID;
1570 ifmr->ifm_active = IFM_ETHER;
1572 if (!adapter->link_active) {
1576 ifmr->ifm_status |= IFM_ACTIVE;
1578 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
1579 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1580 if (adapter->hw.mac.type == e1000_82545)
1581 fiber_type = IFM_1000_LX;
1582 ifmr->ifm_active |= fiber_type | IFM_FDX;
1584 switch (adapter->link_speed) {
1586 ifmr->ifm_active |= IFM_10_T;
1589 ifmr->ifm_active |= IFM_100_TX;
1592 ifmr->ifm_active |= IFM_1000_T;
1595 if (adapter->link_duplex == FULL_DUPLEX)
1596 ifmr->ifm_active |= IFM_FDX;
1598 ifmr->ifm_active |= IFM_HDX;
1602 /*********************************************************************
1604 * Media Ioctl callback
1606 * This routine is called when the user changes speed/duplex using
1607 * media/mediopt option with ifconfig.
1609 **********************************************************************/
1611 em_if_media_change(if_ctx_t ctx)
1613 struct adapter *adapter = iflib_get_softc(ctx);
1614 struct ifmedia *ifm = iflib_get_media(ctx);
1616 INIT_DEBUGOUT("em_if_media_change: begin");
1618 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1621 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1623 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1624 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1629 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1630 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1633 adapter->hw.mac.autoneg = FALSE;
1634 adapter->hw.phy.autoneg_advertised = 0;
1635 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1636 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1638 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1641 adapter->hw.mac.autoneg = FALSE;
1642 adapter->hw.phy.autoneg_advertised = 0;
1643 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1644 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1646 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1649 device_printf(adapter->dev, "Unsupported media type\n");
1658 em_if_set_promisc(if_ctx_t ctx, int flags)
1660 struct adapter *adapter = iflib_get_softc(ctx);
1661 struct ifnet *ifp = iflib_get_ifp(ctx);
1665 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1666 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE);
1667 if (flags & IFF_ALLMULTI)
1668 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1670 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES);
1672 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1673 reg_rctl &= (~E1000_RCTL_MPE);
1674 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1676 if (flags & IFF_PROMISC) {
1677 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1678 /* Turn this on if you want to see bad packets */
1680 reg_rctl |= E1000_RCTL_SBP;
1681 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1682 } else if (flags & IFF_ALLMULTI) {
1683 reg_rctl |= E1000_RCTL_MPE;
1684 reg_rctl &= ~E1000_RCTL_UPE;
1685 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1691 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx)
1695 if (idx == MAX_NUM_MULTICAST_ADDRESSES)
1698 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1703 /*********************************************************************
1706 * This routine is called whenever multicast address list is updated.
1708 **********************************************************************/
1710 em_if_multi_set(if_ctx_t ctx)
1712 struct adapter *adapter = iflib_get_softc(ctx);
1713 struct ifnet *ifp = iflib_get_ifp(ctx);
1714 u8 *mta; /* Multicast array memory */
1718 IOCTL_DEBUGOUT("em_set_multi: begin");
1721 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1723 if (adapter->hw.mac.type == e1000_82542 &&
1724 adapter->hw.revision_id == E1000_REVISION_2) {
1725 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1726 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1727 e1000_pci_clear_mwi(&adapter->hw);
1728 reg_rctl |= E1000_RCTL_RST;
1729 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1733 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta);
1735 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1737 if (if_getflags(ifp) & IFF_PROMISC)
1738 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1739 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES ||
1740 if_getflags(ifp) & IFF_ALLMULTI) {
1741 reg_rctl |= E1000_RCTL_MPE;
1742 reg_rctl &= ~E1000_RCTL_UPE;
1744 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
1746 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1748 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1749 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
1751 if (adapter->hw.mac.type == e1000_82542 &&
1752 adapter->hw.revision_id == E1000_REVISION_2) {
1753 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1754 reg_rctl &= ~E1000_RCTL_RST;
1755 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1757 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1758 e1000_pci_set_mwi(&adapter->hw);
1762 /*********************************************************************
1765 * This routine schedules em_if_update_admin_status() to check for
1766 * link status and to gather statistics as well as to perform some
1767 * controller-specific hardware patting.
1769 **********************************************************************/
1771 em_if_timer(if_ctx_t ctx, uint16_t qid)
1777 iflib_admin_intr_deferred(ctx);
1781 em_if_update_admin_status(if_ctx_t ctx)
1783 struct adapter *adapter = iflib_get_softc(ctx);
1784 struct e1000_hw *hw = &adapter->hw;
1785 device_t dev = iflib_get_dev(ctx);
1786 u32 link_check, thstat, ctrl;
1788 link_check = thstat = ctrl = 0;
1789 /* Get the cached link value or read phy for real */
1790 switch (hw->phy.media_type) {
1791 case e1000_media_type_copper:
1792 if (hw->mac.get_link_status) {
1793 if (hw->mac.type == e1000_pch_spt)
1795 /* Do the work to read phy */
1796 e1000_check_for_link(hw);
1797 link_check = !hw->mac.get_link_status;
1798 if (link_check) /* ESB2 fix */
1799 e1000_cfg_on_link_up(hw);
1804 case e1000_media_type_fiber:
1805 e1000_check_for_link(hw);
1806 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1809 case e1000_media_type_internal_serdes:
1810 e1000_check_for_link(hw);
1811 link_check = hw->mac.serdes_has_link;
1813 /* VF device is type_unknown */
1814 case e1000_media_type_unknown:
1815 e1000_check_for_link(hw);
1816 link_check = !hw->mac.get_link_status;
1822 /* Check for thermal downshift or shutdown */
1823 if (hw->mac.type == e1000_i350) {
1824 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1825 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1828 /* Now check for a transition */
1829 if (link_check && (adapter->link_active == 0)) {
1830 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
1831 &adapter->link_duplex);
1832 /* Check if we must disable SPEED_MODE bit on PCI-E */
1833 if ((adapter->link_speed != SPEED_1000) &&
1834 ((hw->mac.type == e1000_82571) ||
1835 (hw->mac.type == e1000_82572))) {
1837 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1838 tarc0 &= ~TARC_SPEED_MODE_BIT;
1839 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1842 device_printf(dev, "Link is up %d Mbps %s\n",
1843 adapter->link_speed,
1844 ((adapter->link_duplex == FULL_DUPLEX) ?
1845 "Full Duplex" : "Half Duplex"));
1846 adapter->link_active = 1;
1847 adapter->smartspeed = 0;
1848 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) ==
1849 E1000_CTRL_EXT_LINK_MODE_GMII &&
1850 (thstat & E1000_THSTAT_LINK_THROTTLE))
1851 device_printf(dev, "Link: thermal downshift\n");
1852 /* Delay Link Up for Phy update */
1853 if (((hw->mac.type == e1000_i210) ||
1854 (hw->mac.type == e1000_i211)) &&
1855 (hw->phy.id == I210_I_PHY_ID))
1856 msec_delay(I210_LINK_DELAY);
1857 /* Reset if the media type changed. */
1858 if (hw->dev_spec._82575.media_changed &&
1859 hw->mac.type >= igb_mac_min) {
1860 hw->dev_spec._82575.media_changed = false;
1861 adapter->flags |= IGB_MEDIA_RESET;
1864 iflib_link_state_change(ctx, LINK_STATE_UP,
1865 IF_Mbps(adapter->link_speed));
1866 } else if (!link_check && (adapter->link_active == 1)) {
1867 adapter->link_speed = 0;
1868 adapter->link_duplex = 0;
1869 adapter->link_active = 0;
1870 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
1872 em_update_stats_counters(adapter);
1874 /* Reset LAA into RAR[0] on 82571 */
1875 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw))
1876 e1000_rar_set(hw, hw->mac.addr, 0);
1878 if (hw->mac.type < em_mac_min)
1879 lem_smartspeed(adapter);
1880 else if (hw->mac.type >= igb_mac_min &&
1881 adapter->intr_type == IFLIB_INTR_MSIX) {
1882 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC);
1883 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1884 } else if (hw->mac.type == e1000_82574 &&
1885 adapter->intr_type == IFLIB_INTR_MSIX)
1886 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
1890 em_if_watchdog_reset(if_ctx_t ctx)
1892 struct adapter *adapter = iflib_get_softc(ctx);
1895 * Just count the event; iflib(4) will already trigger a
1896 * sufficient reset of the controller.
1898 adapter->watchdog_events++;
1901 /*********************************************************************
1903 * This routine disables all traffic on the adapter by issuing a
1904 * global reset on the MAC.
1906 **********************************************************************/
1908 em_if_stop(if_ctx_t ctx)
1910 struct adapter *adapter = iflib_get_softc(ctx);
1912 INIT_DEBUGOUT("em_if_stop: begin");
1914 e1000_reset_hw(&adapter->hw);
1915 if (adapter->hw.mac.type >= e1000_82544)
1916 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0);
1918 e1000_led_off(&adapter->hw);
1919 e1000_cleanup_led(&adapter->hw);
1922 /*********************************************************************
1924 * Determine hardware revision.
1926 **********************************************************************/
1928 em_identify_hardware(if_ctx_t ctx)
1930 device_t dev = iflib_get_dev(ctx);
1931 struct adapter *adapter = iflib_get_softc(ctx);
1933 /* Make sure our PCI config space has the necessary stuff set */
1934 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1936 /* Save off the information about this board */
1937 adapter->hw.vendor_id = pci_get_vendor(dev);
1938 adapter->hw.device_id = pci_get_device(dev);
1939 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1940 adapter->hw.subsystem_vendor_id =
1941 pci_read_config(dev, PCIR_SUBVEND_0, 2);
1942 adapter->hw.subsystem_device_id =
1943 pci_read_config(dev, PCIR_SUBDEV_0, 2);
1945 /* Do Shared Code Init and Setup */
1946 if (e1000_set_mac_type(&adapter->hw)) {
1947 device_printf(dev, "Setup init failure\n");
1951 /* Are we a VF device? */
1952 if ((adapter->hw.mac.type == e1000_vfadapt) ||
1953 (adapter->hw.mac.type == e1000_vfadapt_i350))
1954 adapter->vf_ifp = 1;
1956 adapter->vf_ifp = 0;
1960 em_allocate_pci_resources(if_ctx_t ctx)
1962 struct adapter *adapter = iflib_get_softc(ctx);
1963 device_t dev = iflib_get_dev(ctx);
1967 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1969 if (adapter->memory == NULL) {
1970 device_printf(dev, "Unable to allocate bus resource: memory\n");
1973 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory);
1974 adapter->osdep.mem_bus_space_handle =
1975 rman_get_bushandle(adapter->memory);
1976 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle;
1978 /* Only older adapters use IO mapping */
1979 if (adapter->hw.mac.type < em_mac_min &&
1980 adapter->hw.mac.type > e1000_82543) {
1981 /* Figure our where our IO BAR is ? */
1982 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1983 val = pci_read_config(dev, rid, 4);
1984 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1988 /* check for 64bit BAR */
1989 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1992 if (rid >= PCIR_CIS) {
1993 device_printf(dev, "Unable to locate IO BAR\n");
1996 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
1998 if (adapter->ioport == NULL) {
1999 device_printf(dev, "Unable to allocate bus resource: "
2003 adapter->hw.io_base = 0;
2004 adapter->osdep.io_bus_space_tag =
2005 rman_get_bustag(adapter->ioport);
2006 adapter->osdep.io_bus_space_handle =
2007 rman_get_bushandle(adapter->ioport);
2010 adapter->hw.back = &adapter->osdep;
2015 /*********************************************************************
2017 * Set up the MSI-X Interrupt handlers
2019 **********************************************************************/
2021 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
2023 struct adapter *adapter = iflib_get_softc(ctx);
2024 struct em_rx_queue *rx_que = adapter->rx_queues;
2025 struct em_tx_queue *tx_que = adapter->tx_queues;
2026 int error, rid, i, vector = 0, rx_vectors;
2029 /* First set up ring resources */
2030 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) {
2032 snprintf(buf, sizeof(buf), "rxq%d", i);
2033 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
2035 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
2036 adapter->rx_num_queues = i + 1;
2040 rx_que->msix = vector;
2043 * Set the bit to enable interrupt
2044 * in E1000_IMS -- bits 20 and 21
2045 * are for RX0 and RX1, note this has
2046 * NOTHING to do with the MSI-X vector
2048 if (adapter->hw.mac.type == e1000_82574) {
2049 rx_que->eims = 1 << (20 + i);
2050 adapter->ims |= rx_que->eims;
2051 adapter->ivars |= (8 | rx_que->msix) << (i * 4);
2052 } else if (adapter->hw.mac.type == e1000_82575)
2053 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
2055 rx_que->eims = 1 << vector;
2057 rx_vectors = vector;
2060 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) {
2061 snprintf(buf, sizeof(buf), "txq%d", i);
2062 tx_que = &adapter->tx_queues[i];
2063 iflib_softirq_alloc_generic(ctx,
2064 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq,
2065 IFLIB_INTR_TX, tx_que, tx_que->me, buf);
2067 tx_que->msix = (vector % adapter->rx_num_queues);
2070 * Set the bit to enable interrupt
2071 * in E1000_IMS -- bits 22 and 23
2072 * are for TX0 and TX1, note this has
2073 * NOTHING to do with the MSI-X vector
2075 if (adapter->hw.mac.type == e1000_82574) {
2076 tx_que->eims = 1 << (22 + i);
2077 adapter->ims |= tx_que->eims;
2078 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
2079 } else if (adapter->hw.mac.type == e1000_82575) {
2080 tx_que->eims = E1000_EICR_TX_QUEUE0 << i;
2082 tx_que->eims = 1 << i;
2086 /* Link interrupt */
2087 rid = rx_vectors + 1;
2088 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq");
2091 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
2094 adapter->linkvec = rx_vectors;
2095 if (adapter->hw.mac.type < igb_mac_min) {
2096 adapter->ivars |= (8 | rx_vectors) << 16;
2097 adapter->ivars |= 0x80000000;
2098 /* Enable the "Other" interrupt type for link status change */
2099 adapter->ims |= E1000_IMS_OTHER;
2104 iflib_irq_free(ctx, &adapter->irq);
2105 rx_que = adapter->rx_queues;
2106 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++)
2107 iflib_irq_free(ctx, &rx_que->que_irq);
2112 igb_configure_queues(struct adapter *adapter)
2114 struct e1000_hw *hw = &adapter->hw;
2115 struct em_rx_queue *rx_que;
2116 struct em_tx_queue *tx_que;
2117 u32 tmp, ivar = 0, newitr = 0;
2119 /* First turn on RSS capability */
2120 if (hw->mac.type != e1000_82575)
2121 E1000_WRITE_REG(hw, E1000_GPIE,
2122 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
2123 E1000_GPIE_PBA | E1000_GPIE_NSICR);
2126 switch (hw->mac.type) {
2133 case e1000_vfadapt_i350:
2135 for (int i = 0; i < adapter->rx_num_queues; i++) {
2137 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2138 rx_que = &adapter->rx_queues[i];
2141 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2144 ivar |= rx_que->msix | E1000_IVAR_VALID;
2146 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2149 for (int i = 0; i < adapter->tx_num_queues; i++) {
2151 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2152 tx_que = &adapter->tx_queues[i];
2155 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2158 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2160 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2161 adapter->que_mask |= tx_que->eims;
2164 /* And for the link interrupt */
2165 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2166 adapter->link_mask = 1 << adapter->linkvec;
2167 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2171 for (int i = 0; i < adapter->rx_num_queues; i++) {
2172 u32 index = i & 0x7; /* Each IVAR has two entries */
2173 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2174 rx_que = &adapter->rx_queues[i];
2177 ivar |= rx_que->msix | E1000_IVAR_VALID;
2180 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2182 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2183 adapter->que_mask |= rx_que->eims;
2186 for (int i = 0; i < adapter->tx_num_queues; i++) {
2187 u32 index = i & 0x7; /* Each IVAR has two entries */
2188 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2189 tx_que = &adapter->tx_queues[i];
2192 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2195 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2197 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2198 adapter->que_mask |= tx_que->eims;
2201 /* And for the link interrupt */
2202 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2203 adapter->link_mask = 1 << adapter->linkvec;
2204 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2208 /* enable MSI-X support*/
2209 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2210 tmp |= E1000_CTRL_EXT_PBA_CLR;
2211 /* Auto-Mask interrupts upon ICR read. */
2212 tmp |= E1000_CTRL_EXT_EIAME;
2213 tmp |= E1000_CTRL_EXT_IRCA;
2214 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2217 for (int i = 0; i < adapter->rx_num_queues; i++) {
2218 rx_que = &adapter->rx_queues[i];
2219 tmp = E1000_EICR_RX_QUEUE0 << i;
2220 tmp |= E1000_EICR_TX_QUEUE0 << i;
2222 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2224 adapter->que_mask |= rx_que->eims;
2228 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec),
2230 adapter->link_mask |= E1000_EIMS_OTHER;
2235 /* Set the starting interrupt rate */
2236 if (em_max_interrupt_rate > 0)
2237 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2239 if (hw->mac.type == e1000_82575)
2240 newitr |= newitr << 16;
2242 newitr |= E1000_EITR_CNT_IGNR;
2244 for (int i = 0; i < adapter->rx_num_queues; i++) {
2245 rx_que = &adapter->rx_queues[i];
2246 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2253 em_free_pci_resources(if_ctx_t ctx)
2255 struct adapter *adapter = iflib_get_softc(ctx);
2256 struct em_rx_queue *que = adapter->rx_queues;
2257 device_t dev = iflib_get_dev(ctx);
2259 /* Release all MSI-X queue resources */
2260 if (adapter->intr_type == IFLIB_INTR_MSIX)
2261 iflib_irq_free(ctx, &adapter->irq);
2264 for (int i = 0; i < adapter->rx_num_queues; i++, que++) {
2265 iflib_irq_free(ctx, &que->que_irq);
2269 if (adapter->memory != NULL) {
2270 bus_release_resource(dev, SYS_RES_MEMORY,
2271 rman_get_rid(adapter->memory), adapter->memory);
2272 adapter->memory = NULL;
2275 if (adapter->flash != NULL) {
2276 bus_release_resource(dev, SYS_RES_MEMORY,
2277 rman_get_rid(adapter->flash), adapter->flash);
2278 adapter->flash = NULL;
2281 if (adapter->ioport != NULL) {
2282 bus_release_resource(dev, SYS_RES_IOPORT,
2283 rman_get_rid(adapter->ioport), adapter->ioport);
2284 adapter->ioport = NULL;
2288 /* Set up MSI or MSI-X */
2290 em_setup_msix(if_ctx_t ctx)
2292 struct adapter *adapter = iflib_get_softc(ctx);
2294 if (adapter->hw.mac.type == e1000_82574) {
2295 em_enable_vectors_82574(ctx);
2300 /*********************************************************************
2302 * Workaround for SmartSpeed on 82541 and 82547 controllers
2304 **********************************************************************/
2306 lem_smartspeed(struct adapter *adapter)
2310 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) ||
2311 adapter->hw.mac.autoneg == 0 ||
2312 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2315 if (adapter->smartspeed == 0) {
2316 /* If Master/Slave config fault is asserted twice,
2317 * we assume back-to-back */
2318 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2319 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2321 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2322 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2323 e1000_read_phy_reg(&adapter->hw,
2324 PHY_1000T_CTRL, &phy_tmp);
2325 if(phy_tmp & CR_1000T_MS_ENABLE) {
2326 phy_tmp &= ~CR_1000T_MS_ENABLE;
2327 e1000_write_phy_reg(&adapter->hw,
2328 PHY_1000T_CTRL, phy_tmp);
2329 adapter->smartspeed++;
2330 if(adapter->hw.mac.autoneg &&
2331 !e1000_copper_link_autoneg(&adapter->hw) &&
2332 !e1000_read_phy_reg(&adapter->hw,
2333 PHY_CONTROL, &phy_tmp)) {
2334 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2335 MII_CR_RESTART_AUTO_NEG);
2336 e1000_write_phy_reg(&adapter->hw,
2337 PHY_CONTROL, phy_tmp);
2342 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2343 /* If still no link, perhaps using 2/3 pair cable */
2344 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2345 phy_tmp |= CR_1000T_MS_ENABLE;
2346 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2347 if(adapter->hw.mac.autoneg &&
2348 !e1000_copper_link_autoneg(&adapter->hw) &&
2349 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2350 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2351 MII_CR_RESTART_AUTO_NEG);
2352 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2355 /* Restart process after EM_SMARTSPEED_MAX iterations */
2356 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2357 adapter->smartspeed = 0;
2360 /*********************************************************************
2362 * Initialize the DMA Coalescing feature
2364 **********************************************************************/
2366 igb_init_dmac(struct adapter *adapter, u32 pba)
2368 device_t dev = adapter->dev;
2369 struct e1000_hw *hw = &adapter->hw;
2370 u32 dmac, reg = ~E1000_DMACR_DMAC_EN;
2374 if (hw->mac.type == e1000_i211)
2377 max_frame_size = adapter->shared->isc_max_frame_size;
2378 if (hw->mac.type > e1000_82580) {
2380 if (adapter->dmac == 0) { /* Disabling it */
2381 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2384 device_printf(dev, "DMA Coalescing enabled\n");
2386 /* Set starting threshold */
2387 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
2389 hwm = 64 * pba - max_frame_size / 16;
2390 if (hwm < 64 * (pba - 6))
2391 hwm = 64 * (pba - 6);
2392 reg = E1000_READ_REG(hw, E1000_FCRTC);
2393 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
2394 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
2395 & E1000_FCRTC_RTH_COAL_MASK);
2396 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
2399 dmac = pba - max_frame_size / 512;
2400 if (dmac < pba - 10)
2402 reg = E1000_READ_REG(hw, E1000_DMACR);
2403 reg &= ~E1000_DMACR_DMACTHR_MASK;
2404 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT)
2405 & E1000_DMACR_DMACTHR_MASK);
2407 /* transition to L0x or L1 if available..*/
2408 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
2410 /* Check if status is 2.5Gb backplane connection
2411 * before configuration of watchdog timer, which is
2412 * in msec values in 12.8usec intervals
2413 * watchdog timer= msec values in 32usec intervals
2414 * for non 2.5Gb connection
2416 if (hw->mac.type == e1000_i354) {
2417 int status = E1000_READ_REG(hw, E1000_STATUS);
2418 if ((status & E1000_STATUS_2P5_SKU) &&
2419 (!(status & E1000_STATUS_2P5_SKU_OVER)))
2420 reg |= ((adapter->dmac * 5) >> 6);
2422 reg |= (adapter->dmac >> 5);
2424 reg |= (adapter->dmac >> 5);
2427 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2429 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
2431 /* Set the interval before transition */
2432 reg = E1000_READ_REG(hw, E1000_DMCTLX);
2433 if (hw->mac.type == e1000_i350)
2434 reg |= IGB_DMCTLX_DCFLUSH_DIS;
2436 ** in 2.5Gb connection, TTLX unit is 0.4 usec
2437 ** which is 0x4*2 = 0xA. But delay is still 4 usec
2439 if (hw->mac.type == e1000_i354) {
2440 int status = E1000_READ_REG(hw, E1000_STATUS);
2441 if ((status & E1000_STATUS_2P5_SKU) &&
2442 (!(status & E1000_STATUS_2P5_SKU_OVER)))
2450 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
2452 /* free space in tx packet buffer to wake from DMA coal */
2453 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE -
2454 (2 * max_frame_size)) >> 6);
2456 /* make low power state decision controlled by DMA coal */
2457 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2458 reg &= ~E1000_PCIEMISC_LX_DECISION;
2459 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
2461 } else if (hw->mac.type == e1000_82580) {
2462 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2463 E1000_WRITE_REG(hw, E1000_PCIEMISC,
2464 reg & ~E1000_PCIEMISC_LX_DECISION);
2465 E1000_WRITE_REG(hw, E1000_DMACR, 0);
2469 /*********************************************************************
2471 * Initialize the hardware to a configuration as specified by the
2472 * adapter structure.
2474 **********************************************************************/
2476 em_reset(if_ctx_t ctx)
2478 device_t dev = iflib_get_dev(ctx);
2479 struct adapter *adapter = iflib_get_softc(ctx);
2480 struct ifnet *ifp = iflib_get_ifp(ctx);
2481 struct e1000_hw *hw = &adapter->hw;
2485 INIT_DEBUGOUT("em_reset: begin");
2486 /* Let the firmware know the OS is in control */
2487 em_get_hw_control(adapter);
2489 /* Set up smart power down as default off on newer adapters. */
2490 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2491 hw->mac.type == e1000_82572)) {
2494 /* Speed up time to link by disabling smart power down. */
2495 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2496 phy_tmp &= ~IGP02E1000_PM_SPD;
2497 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2501 * Packet Buffer Allocation (PBA)
2502 * Writing PBA sets the receive portion of the buffer
2503 * the remainder is used for the transmit buffer.
2505 switch (hw->mac.type) {
2506 /* 82547: Total Packet Buffer is 40K */
2508 case e1000_82547_rev_2:
2509 if (hw->mac.max_frame_size > 8192)
2510 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
2512 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
2514 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */
2517 case e1000_80003es2lan:
2518 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2520 /* 82573: Total Packet Buffer is 32K */
2522 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2526 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2532 case e1000_ich10lan:
2533 /* Boost Receive side for jumbo frames */
2534 if (hw->mac.max_frame_size > 4096)
2535 pba = E1000_PBA_14K;
2537 pba = E1000_PBA_10K;
2547 pba = E1000_PBA_26K;
2550 pba = E1000_PBA_32K;
2554 pba = E1000_READ_REG(hw, E1000_RXPBS);
2555 pba &= E1000_RXPBS_SIZE_MASK_82576;
2560 case e1000_vfadapt_i350:
2561 pba = E1000_READ_REG(hw, E1000_RXPBS);
2562 pba = e1000_rxpbs_adjust_82580(pba);
2566 pba = E1000_PBA_34K;
2569 /* Remaining devices assumed to have a Packet Buffer of 64K. */
2570 if (hw->mac.max_frame_size > 8192)
2571 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2573 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2576 /* Special needs in case of Jumbo frames */
2577 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) {
2578 u32 tx_space, min_tx, min_rx;
2579 pba = E1000_READ_REG(hw, E1000_PBA);
2580 tx_space = pba >> 16;
2582 min_tx = (hw->mac.max_frame_size +
2583 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
2584 min_tx = roundup2(min_tx, 1024);
2586 min_rx = hw->mac.max_frame_size;
2587 min_rx = roundup2(min_rx, 1024);
2589 if (tx_space < min_tx &&
2590 ((min_tx - tx_space) < pba)) {
2591 pba = pba - (min_tx - tx_space);
2593 * if short on rx space, rx wins
2594 * and must trump tx adjustment
2599 E1000_WRITE_REG(hw, E1000_PBA, pba);
2602 if (hw->mac.type < igb_mac_min)
2603 E1000_WRITE_REG(hw, E1000_PBA, pba);
2605 INIT_DEBUGOUT1("em_reset: pba=%dK",pba);
2608 * These parameters control the automatic generation (Tx) and
2609 * response (Rx) to Ethernet PAUSE frames.
2610 * - High water mark should allow for at least two frames to be
2611 * received after sending an XOFF.
2612 * - Low water mark works best when it is very near the high water mark.
2613 * This allows the receiver to restart by sending XON when it has
2614 * drained a bit. Here we use an arbitrary value of 1500 which will
2615 * restart after one full frame is pulled from the buffer. There
2616 * could be several smaller frames in the buffer and if so they will
2617 * not trigger the XON until their total number reduces the buffer
2619 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2621 rx_buffer_size = (pba & 0xffff) << 10;
2622 hw->fc.high_water = rx_buffer_size -
2623 roundup2(hw->mac.max_frame_size, 1024);
2624 hw->fc.low_water = hw->fc.high_water - 1500;
2626 if (adapter->fc) /* locally set flow control value? */
2627 hw->fc.requested_mode = adapter->fc;
2629 hw->fc.requested_mode = e1000_fc_full;
2631 if (hw->mac.type == e1000_80003es2lan)
2632 hw->fc.pause_time = 0xFFFF;
2634 hw->fc.pause_time = EM_FC_PAUSE_TIME;
2636 hw->fc.send_xon = TRUE;
2638 /* Device specific overrides/settings */
2639 switch (hw->mac.type) {
2641 /* Workaround: no TX flow ctrl for PCH */
2642 hw->fc.requested_mode = e1000_fc_rx_pause;
2643 hw->fc.pause_time = 0xFFFF; /* override */
2644 if (if_getmtu(ifp) > ETHERMTU) {
2645 hw->fc.high_water = 0x3500;
2646 hw->fc.low_water = 0x1500;
2648 hw->fc.high_water = 0x5000;
2649 hw->fc.low_water = 0x3000;
2651 hw->fc.refresh_time = 0x1000;
2660 hw->fc.high_water = 0x5C20;
2661 hw->fc.low_water = 0x5048;
2662 hw->fc.pause_time = 0x0650;
2663 hw->fc.refresh_time = 0x0400;
2664 /* Jumbos need adjusted PBA */
2665 if (if_getmtu(ifp) > ETHERMTU)
2666 E1000_WRITE_REG(hw, E1000_PBA, 12);
2668 E1000_WRITE_REG(hw, E1000_PBA, 26);
2672 /* 8-byte granularity */
2673 hw->fc.low_water = hw->fc.high_water - 8;
2681 case e1000_vfadapt_i350:
2682 /* 16-byte granularity */
2683 hw->fc.low_water = hw->fc.high_water - 16;
2686 case e1000_ich10lan:
2687 if (if_getmtu(ifp) > ETHERMTU) {
2688 hw->fc.high_water = 0x2800;
2689 hw->fc.low_water = hw->fc.high_water - 8;
2694 if (hw->mac.type == e1000_80003es2lan)
2695 hw->fc.pause_time = 0xFFFF;
2699 /* Issue a global reset */
2701 if (hw->mac.type >= igb_mac_min) {
2702 E1000_WRITE_REG(hw, E1000_WUC, 0);
2704 E1000_WRITE_REG(hw, E1000_WUFC, 0);
2705 em_disable_aspm(adapter);
2707 if (adapter->flags & IGB_MEDIA_RESET) {
2708 e1000_setup_init_funcs(hw, TRUE);
2709 e1000_get_bus_info(hw);
2710 adapter->flags &= ~IGB_MEDIA_RESET;
2713 if (e1000_init_hw(hw) < 0) {
2714 device_printf(dev, "Hardware Initialization Failed\n");
2717 if (hw->mac.type >= igb_mac_min)
2718 igb_init_dmac(adapter, pba);
2720 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2721 e1000_get_phy_info(hw);
2722 e1000_check_for_link(hw);
2726 * Initialise the RSS mapping for NICs that support multiple transmit/
2730 #define RSSKEYLEN 10
2732 em_initialize_rss_mapping(struct adapter *adapter)
2734 uint8_t rss_key[4 * RSSKEYLEN];
2736 struct e1000_hw *hw = &adapter->hw;
2742 arc4rand(rss_key, sizeof(rss_key), 0);
2743 for (i = 0; i < RSSKEYLEN; ++i) {
2746 rssrk = EM_RSSRK_VAL(rss_key, i);
2747 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2751 * Configure RSS redirect table in following fashion:
2752 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2754 for (i = 0; i < sizeof(reta); ++i) {
2757 q = (i % adapter->rx_num_queues) << 7;
2758 reta |= q << (8 * i);
2761 for (i = 0; i < 32; ++i)
2762 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2764 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2765 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2766 E1000_MRQC_RSS_FIELD_IPV4 |
2767 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2768 E1000_MRQC_RSS_FIELD_IPV6_EX |
2769 E1000_MRQC_RSS_FIELD_IPV6);
2773 igb_initialize_rss_mapping(struct adapter *adapter)
2775 struct e1000_hw *hw = &adapter->hw;
2779 u32 rss_key[10], mrqc, shift = 0;
2782 if (hw->mac.type == e1000_82575)
2786 * The redirection table controls which destination
2787 * queue each bucket redirects traffic to.
2788 * Each DWORD represents four queues, with the LSB
2789 * being the first queue in the DWORD.
2791 * This just allocates buckets to queues using round-robin
2794 * NOTE: It Just Happens to line up with the default
2795 * RSS allocation method.
2798 /* Warning FM follows */
2800 for (i = 0; i < 128; i++) {
2802 queue_id = rss_get_indirection_to_bucket(i);
2804 * If we have more queues than buckets, we'll
2805 * end up mapping buckets to a subset of the
2808 * If we have more buckets than queues, we'll
2809 * end up instead assigning multiple buckets
2812 * Both are suboptimal, but we need to handle
2813 * the case so we don't go out of bounds
2814 * indexing arrays and such.
2816 queue_id = queue_id % adapter->rx_num_queues;
2818 queue_id = (i % adapter->rx_num_queues);
2820 /* Adjust if required */
2821 queue_id = queue_id << shift;
2824 * The low 8 bits are for hash value (n+0);
2825 * The next 8 bits are for hash value (n+1), etc.
2828 reta = reta | ( ((uint32_t) queue_id) << 24);
2830 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2835 /* Now fill in hash table */
2838 * MRQC: Multiple Receive Queues Command
2839 * Set queuing to RSS control, number depends on the device.
2841 mrqc = E1000_MRQC_ENABLE_RSS_8Q;
2844 /* XXX ew typecasting */
2845 rss_getkey((uint8_t *) &rss_key);
2847 arc4rand(&rss_key, sizeof(rss_key), 0);
2849 for (i = 0; i < 10; i++)
2850 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]);
2853 * Configure the RSS fields to hash upon.
2855 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2856 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2857 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2858 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2859 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2860 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2861 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2862 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2864 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2867 /*********************************************************************
2869 * Setup networking device structure and register interface media.
2871 **********************************************************************/
2873 em_setup_interface(if_ctx_t ctx)
2875 struct ifnet *ifp = iflib_get_ifp(ctx);
2876 struct adapter *adapter = iflib_get_softc(ctx);
2877 if_softc_ctx_t scctx = adapter->shared;
2879 INIT_DEBUGOUT("em_setup_interface: begin");
2882 if (adapter->tx_num_queues == 1) {
2883 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
2884 if_setsendqready(ifp);
2888 * Specify the media types supported by this adapter and register
2889 * callbacks to update media and link information
2891 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2892 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
2893 u_char fiber_type = IFM_1000_SX; /* default type */
2895 if (adapter->hw.mac.type == e1000_82545)
2896 fiber_type = IFM_1000_LX;
2897 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
2898 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2900 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2901 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2902 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2903 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2904 if (adapter->hw.phy.type != e1000_phy_ife) {
2905 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2906 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2909 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2910 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO);
2915 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
2917 struct adapter *adapter = iflib_get_softc(ctx);
2918 if_softc_ctx_t scctx = adapter->shared;
2919 int error = E1000_SUCCESS;
2920 struct em_tx_queue *que;
2923 MPASS(adapter->tx_num_queues > 0);
2924 MPASS(adapter->tx_num_queues == ntxqsets);
2926 /* First allocate the top level queue structs */
2927 if (!(adapter->tx_queues =
2928 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
2929 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2930 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2934 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) {
2935 /* Set up some basics */
2937 struct tx_ring *txr = &que->txr;
2938 txr->adapter = que->adapter = adapter;
2939 que->me = txr->me = i;
2941 /* Allocate report status array */
2942 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2943 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n");
2947 for (j = 0; j < scctx->isc_ntxd[0]; j++)
2948 txr->tx_rsq[j] = QIDX_INVALID;
2949 /* get the virtual and physical address of the hardware queues */
2950 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
2951 txr->tx_paddr = paddrs[i*ntxqs];
2955 device_printf(iflib_get_dev(ctx),
2956 "allocated for %d tx_queues\n", adapter->tx_num_queues);
2959 em_if_queues_free(ctx);
2964 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
2966 struct adapter *adapter = iflib_get_softc(ctx);
2967 int error = E1000_SUCCESS;
2968 struct em_rx_queue *que;
2971 MPASS(adapter->rx_num_queues > 0);
2972 MPASS(adapter->rx_num_queues == nrxqsets);
2974 /* First allocate the top level queue structs */
2975 if (!(adapter->rx_queues =
2976 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
2977 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2978 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2983 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) {
2984 /* Set up some basics */
2985 struct rx_ring *rxr = &que->rxr;
2986 rxr->adapter = que->adapter = adapter;
2988 que->me = rxr->me = i;
2990 /* get the virtual and physical address of the hardware queues */
2991 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
2992 rxr->rx_paddr = paddrs[i*nrxqs];
2996 device_printf(iflib_get_dev(ctx),
2997 "allocated for %d rx_queues\n", adapter->rx_num_queues);
3001 em_if_queues_free(ctx);
3006 em_if_queues_free(if_ctx_t ctx)
3008 struct adapter *adapter = iflib_get_softc(ctx);
3009 struct em_tx_queue *tx_que = adapter->tx_queues;
3010 struct em_rx_queue *rx_que = adapter->rx_queues;
3012 if (tx_que != NULL) {
3013 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
3014 struct tx_ring *txr = &tx_que->txr;
3015 if (txr->tx_rsq == NULL)
3018 free(txr->tx_rsq, M_DEVBUF);
3021 free(adapter->tx_queues, M_DEVBUF);
3022 adapter->tx_queues = NULL;
3025 if (rx_que != NULL) {
3026 free(adapter->rx_queues, M_DEVBUF);
3027 adapter->rx_queues = NULL;
3031 /*********************************************************************
3033 * Enable transmit unit.
3035 **********************************************************************/
3037 em_initialize_transmit_unit(if_ctx_t ctx)
3039 struct adapter *adapter = iflib_get_softc(ctx);
3040 if_softc_ctx_t scctx = adapter->shared;
3041 struct em_tx_queue *que;
3042 struct tx_ring *txr;
3043 struct e1000_hw *hw = &adapter->hw;
3044 u32 tctl, txdctl = 0, tarc, tipg = 0;
3046 INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
3048 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
3052 que = &adapter->tx_queues[i];
3054 bus_addr = txr->tx_paddr;
3056 /* Clear checksum offload context. */
3057 offp = (caddr_t)&txr->csum_flags;
3058 endp = (caddr_t)(txr + 1);
3059 bzero(offp, endp - offp);
3061 /* Base and Len of TX Ring */
3062 E1000_WRITE_REG(hw, E1000_TDLEN(i),
3063 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
3064 E1000_WRITE_REG(hw, E1000_TDBAH(i),
3065 (u32)(bus_addr >> 32));
3066 E1000_WRITE_REG(hw, E1000_TDBAL(i),
3068 /* Init the HEAD/TAIL indices */
3069 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
3070 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
3072 HW_DEBUGOUT2("Base = %x, Length = %x\n",
3073 E1000_READ_REG(hw, E1000_TDBAL(i)),
3074 E1000_READ_REG(hw, E1000_TDLEN(i)));
3076 txdctl = 0; /* clear txdctl */
3077 txdctl |= 0x1f; /* PTHRESH */
3078 txdctl |= 1 << 8; /* HTHRESH */
3079 txdctl |= 1 << 16;/* WTHRESH */
3080 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
3081 txdctl |= E1000_TXDCTL_GRAN;
3082 txdctl |= 1 << 25; /* LWTHRESH */
3084 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
3087 /* Set the default values for the Tx Inter Packet Gap timer */
3088 switch (hw->mac.type) {
3089 case e1000_80003es2lan:
3090 tipg = DEFAULT_82543_TIPG_IPGR1;
3091 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
3092 E1000_TIPG_IPGR2_SHIFT;
3095 tipg = DEFAULT_82542_TIPG_IPGT;
3096 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3097 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3100 if (hw->phy.media_type == e1000_media_type_fiber ||
3101 hw->phy.media_type == e1000_media_type_internal_serdes)
3102 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
3104 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
3105 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3106 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3109 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
3110 E1000_WRITE_REG(hw, E1000_TIDV, adapter->tx_int_delay.value);
3112 if(hw->mac.type >= e1000_82540)
3113 E1000_WRITE_REG(hw, E1000_TADV,
3114 adapter->tx_abs_int_delay.value);
3116 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) {
3117 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3118 tarc |= TARC_SPEED_MODE_BIT;
3119 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3120 } else if (hw->mac.type == e1000_80003es2lan) {
3121 /* errata: program both queues to unweighted RR */
3122 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3124 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3125 tarc = E1000_READ_REG(hw, E1000_TARC(1));
3127 E1000_WRITE_REG(hw, E1000_TARC(1), tarc);
3128 } else if (hw->mac.type == e1000_82574) {
3129 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3130 tarc |= TARC_ERRATA_BIT;
3131 if ( adapter->tx_num_queues > 1) {
3132 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
3133 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3134 E1000_WRITE_REG(hw, E1000_TARC(1), tarc);
3136 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3139 if (adapter->tx_int_delay.value > 0)
3140 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3142 /* Program the Transmit Control Register */
3143 tctl = E1000_READ_REG(hw, E1000_TCTL);
3144 tctl &= ~E1000_TCTL_CT;
3145 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
3146 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
3148 if (hw->mac.type >= e1000_82571)
3149 tctl |= E1000_TCTL_MULR;
3151 /* This write will effectively turn on the transmit unit. */
3152 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
3154 /* SPT and KBL errata workarounds */
3155 if (hw->mac.type == e1000_pch_spt) {
3157 reg = E1000_READ_REG(hw, E1000_IOSFPC);
3158 reg |= E1000_RCTL_RDMTS_HEX;
3159 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
3160 /* i218-i219 Specification Update 1.5.4.5 */
3161 reg = E1000_READ_REG(hw, E1000_TARC(0));
3162 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3163 reg |= E1000_TARC0_CB_MULTIQ_2_REQ;
3164 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3168 /*********************************************************************
3170 * Enable receive unit.
3172 **********************************************************************/
3175 em_initialize_receive_unit(if_ctx_t ctx)
3177 struct adapter *adapter = iflib_get_softc(ctx);
3178 if_softc_ctx_t scctx = adapter->shared;
3179 struct ifnet *ifp = iflib_get_ifp(ctx);
3180 struct e1000_hw *hw = &adapter->hw;
3181 struct em_rx_queue *que;
3183 u32 rctl, rxcsum, rfctl;
3185 INIT_DEBUGOUT("em_initialize_receive_units: begin");
3188 * Make sure receives are disabled while setting
3189 * up the descriptor ring
3191 rctl = E1000_READ_REG(hw, E1000_RCTL);
3192 /* Do not disable if ever enabled on this hardware */
3193 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
3194 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3196 /* Setup the Receive Control Register */
3197 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3198 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3199 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3200 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3202 /* Do not store bad packets */
3203 rctl &= ~E1000_RCTL_SBP;
3205 /* Enable Long Packet receive */
3206 if (if_getmtu(ifp) > ETHERMTU)
3207 rctl |= E1000_RCTL_LPE;
3209 rctl &= ~E1000_RCTL_LPE;
3212 if (!em_disable_crc_stripping)
3213 rctl |= E1000_RCTL_SECRC;
3215 if (hw->mac.type >= e1000_82540) {
3216 E1000_WRITE_REG(hw, E1000_RADV,
3217 adapter->rx_abs_int_delay.value);
3220 * Set the interrupt throttling rate. Value is calculated
3221 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
3223 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
3225 E1000_WRITE_REG(hw, E1000_RDTR, adapter->rx_int_delay.value);
3227 /* Use extended rx descriptor formats */
3228 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3229 rfctl |= E1000_RFCTL_EXTEN;
3231 * When using MSI-X interrupts we need to throttle
3232 * using the EITR register (82574 only)
3234 if (hw->mac.type == e1000_82574) {
3235 for (int i = 0; i < 4; i++)
3236 E1000_WRITE_REG(hw, E1000_EITR_82574(i),
3238 /* Disable accelerated acknowledge */
3239 rfctl |= E1000_RFCTL_ACK_DIS;
3241 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3243 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
3244 if (if_getcapenable(ifp) & IFCAP_RXCSUM &&
3245 hw->mac.type >= e1000_82543) {
3246 if (adapter->tx_num_queues > 1) {
3247 if (hw->mac.type >= igb_mac_min) {
3248 rxcsum |= E1000_RXCSUM_PCSD;
3249 if (hw->mac.type != e1000_82575)
3250 rxcsum |= E1000_RXCSUM_CRCOFL;
3252 rxcsum |= E1000_RXCSUM_TUOFL |
3253 E1000_RXCSUM_IPOFL |
3256 if (hw->mac.type >= igb_mac_min)
3257 rxcsum |= E1000_RXCSUM_IPPCSE;
3259 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
3260 if (hw->mac.type > e1000_82575)
3261 rxcsum |= E1000_RXCSUM_CRCOFL;
3264 rxcsum &= ~E1000_RXCSUM_TUOFL;
3266 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
3268 if (adapter->rx_num_queues > 1) {
3269 if (hw->mac.type >= igb_mac_min)
3270 igb_initialize_rss_mapping(adapter);
3272 em_initialize_rss_mapping(adapter);
3276 * XXX TEMPORARY WORKAROUND: on some systems with 82573
3277 * long latencies are observed, like Lenovo X60. This
3278 * change eliminates the problem, but since having positive
3279 * values in RDTR is a known source of problems on other
3280 * platforms another solution is being sought.
3282 if (hw->mac.type == e1000_82573)
3283 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
3285 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3286 struct rx_ring *rxr = &que->rxr;
3287 /* Setup the Base and Length of the Rx Descriptor Ring */
3288 u64 bus_addr = rxr->rx_paddr;
3290 u32 rdt = adapter->rx_num_queues -1; /* default */
3293 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3294 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
3295 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
3296 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
3297 /* Setup the Head and Tail Descriptor Pointers */
3298 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
3299 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
3303 * Set PTHRESH for improved jumbo performance
3304 * According to 10.2.5.11 of Intel 82574 Datasheet,
3305 * RXDCTL(1) is written whenever RXDCTL(0) is written.
3306 * Only write to RXDCTL(1) if there is a need for different
3309 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan ||
3310 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) {
3311 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
3312 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
3313 } else if (hw->mac.type == e1000_82574) {
3314 for (int i = 0; i < adapter->rx_num_queues; i++) {
3315 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3316 rxdctl |= 0x20; /* PTHRESH */
3317 rxdctl |= 4 << 8; /* HTHRESH */
3318 rxdctl |= 4 << 16;/* WTHRESH */
3319 rxdctl |= 1 << 24; /* Switch to granularity */
3320 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3322 } else if (hw->mac.type >= igb_mac_min) {
3323 u32 psize, srrctl = 0;
3325 if (if_getmtu(ifp) > ETHERMTU) {
3326 /* Set maximum packet len */
3327 if (adapter->rx_mbuf_sz <= 4096) {
3328 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3329 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3330 } else if (adapter->rx_mbuf_sz > 4096) {
3331 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3332 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3334 psize = scctx->isc_max_frame_size;
3335 /* are we on a vlan? */
3336 if (ifp->if_vlantrunk != NULL)
3337 psize += VLAN_TAG_SIZE;
3338 E1000_WRITE_REG(hw, E1000_RLPML, psize);
3340 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3341 rctl |= E1000_RCTL_SZ_2048;
3345 * If TX flow control is disabled and there's >1 queue defined,
3348 * This drops frames rather than hanging the RX MAC for all queues.
3350 if ((adapter->rx_num_queues > 1) &&
3351 (adapter->fc == e1000_fc_none ||
3352 adapter->fc == e1000_fc_rx_pause)) {
3353 srrctl |= E1000_SRRCTL_DROP_EN;
3355 /* Setup the Base and Length of the Rx Descriptor Rings */
3356 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3357 struct rx_ring *rxr = &que->rxr;
3358 u64 bus_addr = rxr->rx_paddr;
3362 /* Configure for header split? -- ignore for now */
3363 rxr->hdr_split = igb_header_split;
3365 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3368 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3369 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3370 E1000_WRITE_REG(hw, E1000_RDBAH(i),
3371 (uint32_t)(bus_addr >> 32));
3372 E1000_WRITE_REG(hw, E1000_RDBAL(i),
3373 (uint32_t)bus_addr);
3374 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3375 /* Enable this Queue */
3376 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3377 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3378 rxdctl &= 0xFFF00000;
3379 rxdctl |= IGB_RX_PTHRESH;
3380 rxdctl |= IGB_RX_HTHRESH << 8;
3381 rxdctl |= IGB_RX_WTHRESH << 16;
3382 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3384 } else if (hw->mac.type >= e1000_pch2lan) {
3385 if (if_getmtu(ifp) > ETHERMTU)
3386 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
3388 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
3391 /* Make sure VLAN Filters are off */
3392 rctl &= ~E1000_RCTL_VFE;
3394 if (hw->mac.type < igb_mac_min) {
3395 if (adapter->rx_mbuf_sz == MCLBYTES)
3396 rctl |= E1000_RCTL_SZ_2048;
3397 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE)
3398 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3399 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE)
3400 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3402 /* ensure we clear use DTYPE of 00 here */
3403 rctl &= ~0x00000C00;
3406 /* Write out the settings */
3407 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3413 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3415 struct adapter *adapter = iflib_get_softc(ctx);
3418 index = (vtag >> 5) & 0x7F;
3420 adapter->shadow_vfta[index] |= (1 << bit);
3421 ++adapter->num_vlans;
3425 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3427 struct adapter *adapter = iflib_get_softc(ctx);
3430 index = (vtag >> 5) & 0x7F;
3432 adapter->shadow_vfta[index] &= ~(1 << bit);
3433 --adapter->num_vlans;
3437 em_setup_vlan_hw_support(struct adapter *adapter)
3439 struct e1000_hw *hw = &adapter->hw;
3443 * We get here thru init_locked, meaning
3444 * a soft reset, this has already cleared
3445 * the VFTA and other state, so if there
3446 * have been no vlan's registered do nothing.
3448 if (adapter->num_vlans == 0)
3452 * A soft reset zero's out the VFTA, so
3453 * we need to repopulate it now.
3455 for (int i = 0; i < EM_VFTA_SIZE; i++)
3456 if (adapter->shadow_vfta[i] != 0)
3457 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
3458 i, adapter->shadow_vfta[i]);
3460 reg = E1000_READ_REG(hw, E1000_CTRL);
3461 reg |= E1000_CTRL_VME;
3462 E1000_WRITE_REG(hw, E1000_CTRL, reg);
3464 /* Enable the Filter Table */
3465 reg = E1000_READ_REG(hw, E1000_RCTL);
3466 reg &= ~E1000_RCTL_CFIEN;
3467 reg |= E1000_RCTL_VFE;
3468 E1000_WRITE_REG(hw, E1000_RCTL, reg);
3472 em_if_intr_enable(if_ctx_t ctx)
3474 struct adapter *adapter = iflib_get_softc(ctx);
3475 struct e1000_hw *hw = &adapter->hw;
3476 u32 ims_mask = IMS_ENABLE_MASK;
3478 if (adapter->intr_type == IFLIB_INTR_MSIX) {
3479 E1000_WRITE_REG(hw, EM_EIAC, adapter->ims);
3480 ims_mask |= adapter->ims;
3482 E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3486 em_if_intr_disable(if_ctx_t ctx)
3488 struct adapter *adapter = iflib_get_softc(ctx);
3489 struct e1000_hw *hw = &adapter->hw;
3491 if (adapter->intr_type == IFLIB_INTR_MSIX)
3492 E1000_WRITE_REG(hw, EM_EIAC, 0);
3493 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3497 igb_if_intr_enable(if_ctx_t ctx)
3499 struct adapter *adapter = iflib_get_softc(ctx);
3500 struct e1000_hw *hw = &adapter->hw;
3503 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) {
3504 mask = (adapter->que_mask | adapter->link_mask);
3505 E1000_WRITE_REG(hw, E1000_EIAC, mask);
3506 E1000_WRITE_REG(hw, E1000_EIAM, mask);
3507 E1000_WRITE_REG(hw, E1000_EIMS, mask);
3508 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
3510 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
3511 E1000_WRITE_FLUSH(hw);
3515 igb_if_intr_disable(if_ctx_t ctx)
3517 struct adapter *adapter = iflib_get_softc(ctx);
3518 struct e1000_hw *hw = &adapter->hw;
3520 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) {
3521 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff);
3522 E1000_WRITE_REG(hw, E1000_EIAC, 0);
3524 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3525 E1000_WRITE_FLUSH(hw);
3529 * Bit of a misnomer, what this really means is
3530 * to enable OS management of the system... aka
3531 * to disable special hardware management features
3534 em_init_manageability(struct adapter *adapter)
3536 /* A shared code workaround */
3537 #define E1000_82542_MANC2H E1000_MANC2H
3538 if (adapter->has_manage) {
3539 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3540 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3542 /* disable hardware interception of ARP */
3543 manc &= ~(E1000_MANC_ARP_EN);
3545 /* enable receiving management packets to the host */
3546 manc |= E1000_MANC_EN_MNG2HOST;
3547 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3548 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3549 manc2h |= E1000_MNG2HOST_PORT_623;
3550 manc2h |= E1000_MNG2HOST_PORT_664;
3551 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3552 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3557 * Give control back to hardware management
3558 * controller if there is one.
3561 em_release_manageability(struct adapter *adapter)
3563 if (adapter->has_manage) {
3564 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3566 /* re-enable hardware interception of ARP */
3567 manc |= E1000_MANC_ARP_EN;
3568 manc &= ~E1000_MANC_EN_MNG2HOST;
3570 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3575 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3576 * For ASF and Pass Through versions of f/w this means
3577 * that the driver is loaded. For AMT version type f/w
3578 * this means that the network i/f is open.
3581 em_get_hw_control(struct adapter *adapter)
3585 if (adapter->vf_ifp)
3588 if (adapter->hw.mac.type == e1000_82573) {
3589 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3590 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3591 swsm | E1000_SWSM_DRV_LOAD);
3595 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3596 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3597 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3601 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3602 * For ASF and Pass Through versions of f/w this means that
3603 * the driver is no longer loaded. For AMT versions of the
3604 * f/w this means that the network i/f is closed.
3607 em_release_hw_control(struct adapter *adapter)
3611 if (!adapter->has_manage)
3614 if (adapter->hw.mac.type == e1000_82573) {
3615 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3616 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3617 swsm & ~E1000_SWSM_DRV_LOAD);
3621 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3622 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3623 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3628 em_is_valid_ether_addr(u8 *addr)
3630 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3632 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3640 ** Parse the interface capabilities with regard
3641 ** to both system management and wake-on-lan for
3645 em_get_wakeup(if_ctx_t ctx)
3647 struct adapter *adapter = iflib_get_softc(ctx);
3648 device_t dev = iflib_get_dev(ctx);
3649 u16 eeprom_data = 0, device_id, apme_mask;
3651 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
3652 apme_mask = EM_EEPROM_APME;
3654 switch (adapter->hw.mac.type) {
3659 e1000_read_nvm(&adapter->hw,
3660 NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3661 apme_mask = EM_82544_APME;
3664 case e1000_82546_rev_3:
3665 if (adapter->hw.bus.func == 1) {
3666 e1000_read_nvm(&adapter->hw,
3667 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3670 e1000_read_nvm(&adapter->hw,
3671 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3675 adapter->has_amt = TRUE;
3679 case e1000_80003es2lan:
3680 if (adapter->hw.bus.func == 1) {
3681 e1000_read_nvm(&adapter->hw,
3682 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3685 e1000_read_nvm(&adapter->hw,
3686 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3690 case e1000_ich10lan:
3695 case e1000_82575: /* listing all igb devices */
3703 case e1000_vfadapt_i350:
3704 apme_mask = E1000_WUC_APME;
3705 adapter->has_amt = TRUE;
3706 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
3709 e1000_read_nvm(&adapter->hw,
3710 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3713 if (eeprom_data & apme_mask)
3714 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
3716 * We have the eeprom settings, now apply the special cases
3717 * where the eeprom may be wrong or the board won't support
3718 * wake on lan on a particular port
3720 device_id = pci_get_device(dev);
3721 switch (device_id) {
3722 case E1000_DEV_ID_82546GB_PCIE:
3725 case E1000_DEV_ID_82546EB_FIBER:
3726 case E1000_DEV_ID_82546GB_FIBER:
3727 /* Wake events only supported on port A for dual fiber
3728 * regardless of eeprom setting */
3729 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3730 E1000_STATUS_FUNC_1)
3733 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
3734 /* if quad port adapter, disable WoL on all but port A */
3735 if (global_quad_port_a != 0)
3737 /* Reset for multiple quad port adapters */
3738 if (++global_quad_port_a == 4)
3739 global_quad_port_a = 0;
3741 case E1000_DEV_ID_82571EB_FIBER:
3742 /* Wake events only supported on port A for dual fiber
3743 * regardless of eeprom setting */
3744 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3745 E1000_STATUS_FUNC_1)
3748 case E1000_DEV_ID_82571EB_QUAD_COPPER:
3749 case E1000_DEV_ID_82571EB_QUAD_FIBER:
3750 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
3751 /* if quad port adapter, disable WoL on all but port A */
3752 if (global_quad_port_a != 0)
3754 /* Reset for multiple quad port adapters */
3755 if (++global_quad_port_a == 4)
3756 global_quad_port_a = 0;
3764 * Enable PCI Wake On Lan capability
3767 em_enable_wakeup(if_ctx_t ctx)
3769 struct adapter *adapter = iflib_get_softc(ctx);
3770 device_t dev = iflib_get_dev(ctx);
3771 if_t ifp = iflib_get_ifp(ctx);
3773 u32 pmc, ctrl, ctrl_ext, rctl;
3776 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
3780 * Determine type of Wakeup: note that wol
3781 * is set with all bits on by default.
3783 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
3784 adapter->wol &= ~E1000_WUFC_MAG;
3786 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
3787 adapter->wol &= ~E1000_WUFC_EX;
3789 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
3790 adapter->wol &= ~E1000_WUFC_MC;
3792 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3793 rctl |= E1000_RCTL_MPE;
3794 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3797 if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC)))
3800 /* Advertise the wakeup capability */
3801 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
3802 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
3803 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
3805 /* Keep the laser running on Fiber adapters */
3806 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3807 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
3808 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3809 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
3810 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext);
3813 if ((adapter->hw.mac.type == e1000_ich8lan) ||
3814 (adapter->hw.mac.type == e1000_pchlan) ||
3815 (adapter->hw.mac.type == e1000_ich9lan) ||
3816 (adapter->hw.mac.type == e1000_ich10lan))
3817 e1000_suspend_workarounds_ich8lan(&adapter->hw);
3819 if ( adapter->hw.mac.type >= e1000_pchlan) {
3820 error = em_enable_phy_wakeup(adapter);
3824 /* Enable wakeup by the MAC */
3825 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
3826 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
3829 if (adapter->hw.phy.type == e1000_phy_igp_3)
3830 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
3833 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
3834 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3835 if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
3836 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3837 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
3843 * WOL in the newer chipset interfaces (pchlan)
3844 * require thing to be copied into the phy
3847 em_enable_phy_wakeup(struct adapter *adapter)
3849 struct e1000_hw *hw = &adapter->hw;
3853 /* copy MAC RARs to PHY RARs */
3854 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
3856 /* copy MAC MTA to PHY MTA */
3857 for (int i = 0; i < hw->mac.mta_reg_count; i++) {
3858 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
3859 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
3860 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
3861 (u16)((mreg >> 16) & 0xFFFF));
3864 /* configure PHY Rx Control register */
3865 e1000_read_phy_reg(hw, BM_RCTL, &preg);
3866 mreg = E1000_READ_REG(hw, E1000_RCTL);
3867 if (mreg & E1000_RCTL_UPE)
3868 preg |= BM_RCTL_UPE;
3869 if (mreg & E1000_RCTL_MPE)
3870 preg |= BM_RCTL_MPE;
3871 preg &= ~(BM_RCTL_MO_MASK);
3872 if (mreg & E1000_RCTL_MO_3)
3873 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
3874 << BM_RCTL_MO_SHIFT);
3875 if (mreg & E1000_RCTL_BAM)
3876 preg |= BM_RCTL_BAM;
3877 if (mreg & E1000_RCTL_PMCF)
3878 preg |= BM_RCTL_PMCF;
3879 mreg = E1000_READ_REG(hw, E1000_CTRL);
3880 if (mreg & E1000_CTRL_RFCE)
3881 preg |= BM_RCTL_RFCE;
3882 e1000_write_phy_reg(hw, BM_RCTL, preg);
3884 /* enable PHY wakeup in MAC register */
3885 E1000_WRITE_REG(hw, E1000_WUC,
3886 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
3887 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol);
3889 /* configure and enable PHY wakeup in PHY registers */
3890 e1000_write_phy_reg(hw, BM_WUFC, adapter->wol);
3891 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN);
3893 /* activate PHY wakeup */
3894 ret = hw->phy.ops.acquire(hw);
3896 printf("Could not acquire PHY\n");
3899 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3900 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3901 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
3903 printf("Could not read PHY page 769\n");
3906 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
3907 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
3909 printf("Could not set PHY Host Wakeup bit\n");
3911 hw->phy.ops.release(hw);
3917 em_if_led_func(if_ctx_t ctx, int onoff)
3919 struct adapter *adapter = iflib_get_softc(ctx);
3922 e1000_setup_led(&adapter->hw);
3923 e1000_led_on(&adapter->hw);
3925 e1000_led_off(&adapter->hw);
3926 e1000_cleanup_led(&adapter->hw);
3931 * Disable the L0S and L1 LINK states
3934 em_disable_aspm(struct adapter *adapter)
3937 u16 link_cap,link_ctrl;
3938 device_t dev = adapter->dev;
3940 switch (adapter->hw.mac.type) {
3948 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
3950 reg = base + PCIER_LINK_CAP;
3951 link_cap = pci_read_config(dev, reg, 2);
3952 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
3954 reg = base + PCIER_LINK_CTL;
3955 link_ctrl = pci_read_config(dev, reg, 2);
3956 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
3957 pci_write_config(dev, reg, link_ctrl, 2);
3961 /**********************************************************************
3963 * Update the board statistics counters.
3965 **********************************************************************/
3967 em_update_stats_counters(struct adapter *adapter)
3969 u64 prev_xoffrxc = adapter->stats.xoffrxc;
3971 if(adapter->hw.phy.media_type == e1000_media_type_copper ||
3972 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3973 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
3974 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
3976 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
3977 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
3978 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
3979 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
3981 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
3982 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
3983 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
3984 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
3985 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
3986 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
3987 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
3988 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
3990 ** For watchdog management we need to know if we have been
3991 ** paused during the last interval, so capture that here.
3993 if (adapter->stats.xoffrxc != prev_xoffrxc)
3994 adapter->shared->isc_pause_frames = 1;
3995 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
3996 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
3997 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
3998 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
3999 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
4000 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
4001 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
4002 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
4003 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
4004 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
4005 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
4006 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
4008 /* For the 64-bit byte counters the low dword must be read first. */
4009 /* Both registers clear on the read of the high dword */
4011 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) +
4012 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32);
4013 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) +
4014 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32);
4016 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
4017 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
4018 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
4019 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
4020 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
4022 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
4023 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
4025 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
4026 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
4027 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
4028 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
4029 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
4030 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
4031 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
4032 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
4033 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
4034 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
4036 /* Interrupt Counts */
4038 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC);
4039 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC);
4040 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC);
4041 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC);
4042 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC);
4043 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC);
4044 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC);
4045 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC);
4046 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC);
4048 if (adapter->hw.mac.type >= e1000_82543) {
4049 adapter->stats.algnerrc +=
4050 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
4051 adapter->stats.rxerrc +=
4052 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
4053 adapter->stats.tncrs +=
4054 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
4055 adapter->stats.cexterr +=
4056 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
4057 adapter->stats.tsctc +=
4058 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
4059 adapter->stats.tsctfc +=
4060 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
4065 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
4067 struct adapter *adapter = iflib_get_softc(ctx);
4068 struct ifnet *ifp = iflib_get_ifp(ctx);
4071 case IFCOUNTER_COLLISIONS:
4072 return (adapter->stats.colc);
4073 case IFCOUNTER_IERRORS:
4074 return (adapter->dropped_pkts + adapter->stats.rxerrc +
4075 adapter->stats.crcerrs + adapter->stats.algnerrc +
4076 adapter->stats.ruc + adapter->stats.roc +
4077 adapter->stats.mpc + adapter->stats.cexterr);
4078 case IFCOUNTER_OERRORS:
4079 return (adapter->stats.ecol + adapter->stats.latecol +
4080 adapter->watchdog_events);
4082 return (if_get_counter_default(ifp, cnt));
4086 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized
4087 * @ctx: iflib context
4088 * @event: event code to check
4090 * Defaults to returning true for unknown events.
4092 * @returns true if iflib needs to reinit the interface
4095 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
4098 case IFLIB_RESTART_VLAN_CONFIG:
4104 /* Export a single 32-bit register via a read-only sysctl. */
4106 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
4108 struct adapter *adapter;
4111 adapter = oidp->oid_arg1;
4112 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2);
4113 return (sysctl_handle_int(oidp, &val, 0, req));
4117 * Add sysctl variables, one per statistic, to the system.
4120 em_add_hw_stats(struct adapter *adapter)
4122 device_t dev = iflib_get_dev(adapter->ctx);
4123 struct em_tx_queue *tx_que = adapter->tx_queues;
4124 struct em_rx_queue *rx_que = adapter->rx_queues;
4126 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
4127 struct sysctl_oid *tree = device_get_sysctl_tree(dev);
4128 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
4129 struct e1000_hw_stats *stats = &adapter->stats;
4131 struct sysctl_oid *stat_node, *queue_node, *int_node;
4132 struct sysctl_oid_list *stat_list, *queue_list, *int_list;
4134 #define QUEUE_NAME_LEN 32
4135 char namebuf[QUEUE_NAME_LEN];
4137 /* Driver Statistics */
4138 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
4139 CTLFLAG_RD, &adapter->dropped_pkts,
4140 "Driver dropped packets");
4141 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
4142 CTLFLAG_RD, &adapter->link_irq,
4143 "Link MSI-X IRQ Handled");
4144 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
4145 CTLFLAG_RD, &adapter->rx_overruns,
4147 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
4148 CTLFLAG_RD, &adapter->watchdog_events,
4149 "Watchdog timeouts");
4150 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
4151 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
4152 adapter, E1000_CTRL, em_sysctl_reg_handler, "IU",
4153 "Device Control Register");
4154 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
4155 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
4156 adapter, E1000_RCTL, em_sysctl_reg_handler, "IU",
4157 "Receiver Control Register");
4158 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
4159 CTLFLAG_RD, &adapter->hw.fc.high_water, 0,
4160 "Flow Control High Watermark");
4161 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
4162 CTLFLAG_RD, &adapter->hw.fc.low_water, 0,
4163 "Flow Control Low Watermark");
4165 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
4166 struct tx_ring *txr = &tx_que->txr;
4167 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
4168 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4169 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name");
4170 queue_list = SYSCTL_CHILDREN(queue_node);
4172 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
4173 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4174 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU",
4175 "Transmit Descriptor Head");
4176 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
4177 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4178 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU",
4179 "Transmit Descriptor Tail");
4180 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
4181 CTLFLAG_RD, &txr->tx_irq,
4182 "Queue MSI-X Transmit Interrupts");
4185 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) {
4186 struct rx_ring *rxr = &rx_que->rxr;
4187 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
4188 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4189 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name");
4190 queue_list = SYSCTL_CHILDREN(queue_node);
4192 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
4193 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4194 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU",
4195 "Receive Descriptor Head");
4196 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
4197 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4198 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU",
4199 "Receive Descriptor Tail");
4200 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
4201 CTLFLAG_RD, &rxr->rx_irq,
4202 "Queue MSI-X Receive Interrupts");
4205 /* MAC stats get their own sub node */
4207 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
4208 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics");
4209 stat_list = SYSCTL_CHILDREN(stat_node);
4211 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
4212 CTLFLAG_RD, &stats->ecol,
4213 "Excessive collisions");
4214 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
4215 CTLFLAG_RD, &stats->scc,
4216 "Single collisions");
4217 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
4218 CTLFLAG_RD, &stats->mcc,
4219 "Multiple collisions");
4220 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
4221 CTLFLAG_RD, &stats->latecol,
4223 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
4224 CTLFLAG_RD, &stats->colc,
4226 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
4227 CTLFLAG_RD, &adapter->stats.symerrs,
4229 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
4230 CTLFLAG_RD, &adapter->stats.sec,
4232 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
4233 CTLFLAG_RD, &adapter->stats.dc,
4235 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
4236 CTLFLAG_RD, &adapter->stats.mpc,
4238 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
4239 CTLFLAG_RD, &adapter->stats.rnbc,
4240 "Receive No Buffers");
4241 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
4242 CTLFLAG_RD, &adapter->stats.ruc,
4243 "Receive Undersize");
4244 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
4245 CTLFLAG_RD, &adapter->stats.rfc,
4246 "Fragmented Packets Received ");
4247 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
4248 CTLFLAG_RD, &adapter->stats.roc,
4249 "Oversized Packets Received");
4250 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
4251 CTLFLAG_RD, &adapter->stats.rjc,
4253 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
4254 CTLFLAG_RD, &adapter->stats.rxerrc,
4256 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
4257 CTLFLAG_RD, &adapter->stats.crcerrs,
4259 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
4260 CTLFLAG_RD, &adapter->stats.algnerrc,
4261 "Alignment Errors");
4262 /* On 82575 these are collision counts */
4263 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
4264 CTLFLAG_RD, &adapter->stats.cexterr,
4265 "Collision/Carrier extension errors");
4266 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
4267 CTLFLAG_RD, &adapter->stats.xonrxc,
4269 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
4270 CTLFLAG_RD, &adapter->stats.xontxc,
4272 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
4273 CTLFLAG_RD, &adapter->stats.xoffrxc,
4275 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
4276 CTLFLAG_RD, &adapter->stats.xofftxc,
4277 "XOFF Transmitted");
4279 /* Packet Reception Stats */
4280 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
4281 CTLFLAG_RD, &adapter->stats.tpr,
4282 "Total Packets Received ");
4283 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
4284 CTLFLAG_RD, &adapter->stats.gprc,
4285 "Good Packets Received");
4286 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
4287 CTLFLAG_RD, &adapter->stats.bprc,
4288 "Broadcast Packets Received");
4289 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
4290 CTLFLAG_RD, &adapter->stats.mprc,
4291 "Multicast Packets Received");
4292 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
4293 CTLFLAG_RD, &adapter->stats.prc64,
4294 "64 byte frames received ");
4295 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
4296 CTLFLAG_RD, &adapter->stats.prc127,
4297 "65-127 byte frames received");
4298 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
4299 CTLFLAG_RD, &adapter->stats.prc255,
4300 "128-255 byte frames received");
4301 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
4302 CTLFLAG_RD, &adapter->stats.prc511,
4303 "256-511 byte frames received");
4304 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
4305 CTLFLAG_RD, &adapter->stats.prc1023,
4306 "512-1023 byte frames received");
4307 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
4308 CTLFLAG_RD, &adapter->stats.prc1522,
4309 "1023-1522 byte frames received");
4310 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
4311 CTLFLAG_RD, &adapter->stats.gorc,
4312 "Good Octets Received");
4314 /* Packet Transmission Stats */
4315 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
4316 CTLFLAG_RD, &adapter->stats.gotc,
4317 "Good Octets Transmitted");
4318 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
4319 CTLFLAG_RD, &adapter->stats.tpt,
4320 "Total Packets Transmitted");
4321 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
4322 CTLFLAG_RD, &adapter->stats.gptc,
4323 "Good Packets Transmitted");
4324 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
4325 CTLFLAG_RD, &adapter->stats.bptc,
4326 "Broadcast Packets Transmitted");
4327 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
4328 CTLFLAG_RD, &adapter->stats.mptc,
4329 "Multicast Packets Transmitted");
4330 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
4331 CTLFLAG_RD, &adapter->stats.ptc64,
4332 "64 byte frames transmitted ");
4333 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
4334 CTLFLAG_RD, &adapter->stats.ptc127,
4335 "65-127 byte frames transmitted");
4336 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
4337 CTLFLAG_RD, &adapter->stats.ptc255,
4338 "128-255 byte frames transmitted");
4339 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
4340 CTLFLAG_RD, &adapter->stats.ptc511,
4341 "256-511 byte frames transmitted");
4342 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
4343 CTLFLAG_RD, &adapter->stats.ptc1023,
4344 "512-1023 byte frames transmitted");
4345 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
4346 CTLFLAG_RD, &adapter->stats.ptc1522,
4347 "1024-1522 byte frames transmitted");
4348 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
4349 CTLFLAG_RD, &adapter->stats.tsctc,
4350 "TSO Contexts Transmitted");
4351 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
4352 CTLFLAG_RD, &adapter->stats.tsctfc,
4353 "TSO Contexts Failed");
4356 /* Interrupt Stats */
4358 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
4359 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics");
4360 int_list = SYSCTL_CHILDREN(int_node);
4362 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
4363 CTLFLAG_RD, &adapter->stats.iac,
4364 "Interrupt Assertion Count");
4366 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
4367 CTLFLAG_RD, &adapter->stats.icrxptc,
4368 "Interrupt Cause Rx Pkt Timer Expire Count");
4370 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
4371 CTLFLAG_RD, &adapter->stats.icrxatc,
4372 "Interrupt Cause Rx Abs Timer Expire Count");
4374 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
4375 CTLFLAG_RD, &adapter->stats.ictxptc,
4376 "Interrupt Cause Tx Pkt Timer Expire Count");
4378 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
4379 CTLFLAG_RD, &adapter->stats.ictxatc,
4380 "Interrupt Cause Tx Abs Timer Expire Count");
4382 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
4383 CTLFLAG_RD, &adapter->stats.ictxqec,
4384 "Interrupt Cause Tx Queue Empty Count");
4386 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
4387 CTLFLAG_RD, &adapter->stats.ictxqmtc,
4388 "Interrupt Cause Tx Queue Min Thresh Count");
4390 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
4391 CTLFLAG_RD, &adapter->stats.icrxdmtc,
4392 "Interrupt Cause Rx Desc Min Thresh Count");
4394 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
4395 CTLFLAG_RD, &adapter->stats.icrxoc,
4396 "Interrupt Cause Receiver Overrun Count");
4399 /**********************************************************************
4401 * This routine provides a way to dump out the adapter eeprom,
4402 * often a useful debug/service tool. This only dumps the first
4403 * 32 words, stuff that matters is in that extent.
4405 **********************************************************************/
4407 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4409 struct adapter *adapter = (struct adapter *)arg1;
4414 error = sysctl_handle_int(oidp, &result, 0, req);
4416 if (error || !req->newptr)
4420 * This value will cause a hex dump of the
4421 * first 32 16-bit words of the EEPROM to
4425 em_print_nvm_info(adapter);
4431 em_print_nvm_info(struct adapter *adapter)
4436 /* Its a bit crude, but it gets the job done */
4437 printf("\nInterface EEPROM Dump:\n");
4438 printf("Offset\n0x0000 ");
4439 for (i = 0, j = 0; i < 32; i++, j++) {
4440 if (j == 8) { /* Make the offset block */
4442 printf("\n0x00%x0 ",row);
4444 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
4445 printf("%04x ", eeprom_data);
4451 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4453 struct em_int_delay_info *info;
4454 struct adapter *adapter;
4456 int error, usecs, ticks;
4458 info = (struct em_int_delay_info *) arg1;
4459 usecs = info->value;
4460 error = sysctl_handle_int(oidp, &usecs, 0, req);
4461 if (error != 0 || req->newptr == NULL)
4463 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4465 info->value = usecs;
4466 ticks = EM_USECS_TO_TICKS(usecs);
4467 if (info->offset == E1000_ITR) /* units are 256ns here */
4470 adapter = info->adapter;
4472 regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
4473 regval = (regval & ~0xffff) | (ticks & 0xffff);
4474 /* Handle a few special cases. */
4475 switch (info->offset) {
4480 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
4481 /* Don't write 0 into the TIDV register. */
4484 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
4487 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
4492 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
4493 const char *description, struct em_int_delay_info *info,
4494 int offset, int value)
4496 info->adapter = adapter;
4497 info->offset = offset;
4498 info->value = value;
4499 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev),
4500 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4501 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
4502 info, 0, em_sysctl_int_delay, "I", description);
4506 * Set flow control using sysctl:
4507 * Flow control values:
4514 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4517 static int input = 3; /* default is full */
4518 struct adapter *adapter = (struct adapter *) arg1;
4520 error = sysctl_handle_int(oidp, &input, 0, req);
4522 if ((error) || (req->newptr == NULL))
4525 if (input == adapter->fc) /* no change? */
4529 case e1000_fc_rx_pause:
4530 case e1000_fc_tx_pause:
4533 adapter->hw.fc.requested_mode = input;
4534 adapter->fc = input;
4541 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
4542 e1000_force_mac_fc(&adapter->hw);
4547 * Manage Energy Efficient Ethernet:
4549 * 0/1 - enabled/disabled
4552 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4554 struct adapter *adapter = (struct adapter *) arg1;
4557 value = adapter->hw.dev_spec.ich8lan.eee_disable;
4558 error = sysctl_handle_int(oidp, &value, 0, req);
4559 if (error || req->newptr == NULL)
4561 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4562 em_if_init(adapter->ctx);
4568 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4570 struct adapter *adapter;
4575 error = sysctl_handle_int(oidp, &result, 0, req);
4577 if (error || !req->newptr)
4581 adapter = (struct adapter *) arg1;
4582 em_print_debug_info(adapter);
4589 em_get_rs(SYSCTL_HANDLER_ARGS)
4591 struct adapter *adapter = (struct adapter *) arg1;
4596 error = sysctl_handle_int(oidp, &result, 0, req);
4598 if (error || !req->newptr || result != 1)
4600 em_dump_rs(adapter);
4606 em_if_debug(if_ctx_t ctx)
4608 em_dump_rs(iflib_get_softc(ctx));
4612 * This routine is meant to be fluid, add whatever is
4613 * needed for debugging a problem. -jfv
4616 em_print_debug_info(struct adapter *adapter)
4618 device_t dev = iflib_get_dev(adapter->ctx);
4619 struct ifnet *ifp = iflib_get_ifp(adapter->ctx);
4620 struct tx_ring *txr = &adapter->tx_queues->txr;
4621 struct rx_ring *rxr = &adapter->rx_queues->rxr;
4623 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
4624 printf("Interface is RUNNING ");
4626 printf("Interface is NOT RUNNING\n");
4628 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
4629 printf("and INACTIVE\n");
4631 printf("and ACTIVE\n");
4633 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
4634 device_printf(dev, "TX Queue %d ------\n", i);
4635 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
4636 E1000_READ_REG(&adapter->hw, E1000_TDH(i)),
4637 E1000_READ_REG(&adapter->hw, E1000_TDT(i)));
4640 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) {
4641 device_printf(dev, "RX Queue %d ------\n", j);
4642 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
4643 E1000_READ_REG(&adapter->hw, E1000_RDH(j)),
4644 E1000_READ_REG(&adapter->hw, E1000_RDT(j)));
4650 * Write a new value to the EEPROM increasing the number of MSI-X
4651 * vectors from 3 to 5, for proper multiqueue support.
4654 em_enable_vectors_82574(if_ctx_t ctx)
4656 struct adapter *adapter = iflib_get_softc(ctx);
4657 struct e1000_hw *hw = &adapter->hw;
4658 device_t dev = iflib_get_dev(ctx);
4661 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4663 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata);
4664 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
4665 device_printf(dev, "Writing to eeprom: increasing "
4666 "reported MSI-X vectors from 3 to 5...\n");
4667 edata &= ~(EM_NVM_MSIX_N_MASK);
4668 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
4669 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4670 e1000_update_nvm_checksum(hw);
4671 device_printf(dev, "Writing to eeprom: done\n");