2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <machine/_inttypes.h>
34 #define em_mac_min e1000_82547
35 #define igb_mac_min e1000_82575
37 /*********************************************************************
39 *********************************************************************/
40 char em_driver_version[] = "7.6.1-k";
42 /*********************************************************************
45 * Used by probe to select devices to load on
46 * Last field stores an index into e1000_strings
47 * Last entry must be all 0s
49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
50 *********************************************************************/
52 static pci_vendor_info_t em_vendor_info_array[] =
54 /* Intel(R) PRO/1000 Network Connection - Legacy em*/
55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"),
56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"),
57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"),
58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"),
59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"),
61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"),
62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"),
63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"),
64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"),
66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"),
67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"),
71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"),
72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"),
79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"),
80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"),
81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"),
82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"),
83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"),
85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"),
89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"),
90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"),
91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"),
92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"),
95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"),
96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"),
99 /* Intel(R) PRO/1000 Network Connection - em */
100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"),
103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"),
104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"),
105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"),
107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"),
108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"),
110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"),
113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"),
114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"),
115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"),
116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"),
117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"),
118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"),
119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"),
120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"),
121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"),
124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"),
125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"),
127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"),
128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"),
129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"),
132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"),
133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"),
134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"),
135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"),
137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"),
138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"),
139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"),
140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"),
141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"),
142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"),
143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"),
144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"),
145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"),
146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"),
147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"),
148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"),
149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"),
150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"),
151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"),
152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"),
153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"),
154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"),
155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"),
156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"),
157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"),
158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"),
159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"),
160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"),
161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"),
162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"),
163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"),
164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"),
165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"),
166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"),
167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"),
168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"),
169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) PRO/1000 Network Connection"),
170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) PRO/1000 Network Connection"),
171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) PRO/1000 Network Connection"),
172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) PRO/1000 Network Connection"),
173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) PRO/1000 Network Connection"),
174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) PRO/1000 Network Connection"),
175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) PRO/1000 Network Connection"),
176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) PRO/1000 Network Connection"),
177 /* required last entry */
181 static pci_vendor_info_t igb_vendor_info_array[] =
183 /* Intel(R) PRO/1000 Network Connection - igb */
184 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
185 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
186 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
187 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"),
188 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
189 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
190 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
191 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
192 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"),
193 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
194 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"),
195 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
196 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
197 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
198 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
199 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
200 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"),
201 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
202 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
203 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
204 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"),
205 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"),
206 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
207 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
208 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
209 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
210 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
211 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
212 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"),
213 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"),
214 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
215 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
216 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
217 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
218 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
219 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
220 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
221 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
222 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
223 /* required last entry */
227 /*********************************************************************
228 * Function prototypes
229 *********************************************************************/
230 static void *em_register(device_t dev);
231 static void *igb_register(device_t dev);
232 static int em_if_attach_pre(if_ctx_t ctx);
233 static int em_if_attach_post(if_ctx_t ctx);
234 static int em_if_detach(if_ctx_t ctx);
235 static int em_if_shutdown(if_ctx_t ctx);
236 static int em_if_suspend(if_ctx_t ctx);
237 static int em_if_resume(if_ctx_t ctx);
239 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets);
240 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets);
241 static void em_if_queues_free(if_ctx_t ctx);
243 static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
244 static void em_if_init(if_ctx_t ctx);
245 static void em_if_stop(if_ctx_t ctx);
246 static void em_if_media_status(if_ctx_t, struct ifmediareq *);
247 static int em_if_media_change(if_ctx_t ctx);
248 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu);
249 static void em_if_timer(if_ctx_t ctx, uint16_t qid);
250 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag);
251 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag);
253 static void em_identify_hardware(if_ctx_t ctx);
254 static int em_allocate_pci_resources(if_ctx_t ctx);
255 static void em_free_pci_resources(if_ctx_t ctx);
256 static void em_reset(if_ctx_t ctx);
257 static int em_setup_interface(if_ctx_t ctx);
258 static int em_setup_msix(if_ctx_t ctx);
260 static void em_initialize_transmit_unit(if_ctx_t ctx);
261 static void em_initialize_receive_unit(if_ctx_t ctx);
263 static void em_if_enable_intr(if_ctx_t ctx);
264 static void em_if_disable_intr(if_ctx_t ctx);
265 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
266 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
267 static void em_if_multi_set(if_ctx_t ctx);
268 static void em_if_update_admin_status(if_ctx_t ctx);
269 static void em_if_debug(if_ctx_t ctx);
270 static void em_update_stats_counters(struct adapter *);
271 static void em_add_hw_stats(struct adapter *adapter);
272 static int em_if_set_promisc(if_ctx_t ctx, int flags);
273 static void em_setup_vlan_hw_support(struct adapter *);
274 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
275 static void em_print_nvm_info(struct adapter *);
276 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
277 static int em_get_rs(SYSCTL_HANDLER_ARGS);
278 static void em_print_debug_info(struct adapter *);
279 static int em_is_valid_ether_addr(u8 *);
280 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
281 static void em_add_int_delay_sysctl(struct adapter *, const char *,
282 const char *, struct em_int_delay_info *, int, int);
283 /* Management and WOL Support */
284 static void em_init_manageability(struct adapter *);
285 static void em_release_manageability(struct adapter *);
286 static void em_get_hw_control(struct adapter *);
287 static void em_release_hw_control(struct adapter *);
288 static void em_get_wakeup(if_ctx_t ctx);
289 static void em_enable_wakeup(if_ctx_t ctx);
290 static int em_enable_phy_wakeup(struct adapter *);
291 static void em_disable_aspm(struct adapter *);
293 int em_intr(void *arg);
294 static void em_disable_promisc(if_ctx_t ctx);
297 static int em_if_msix_intr_assign(if_ctx_t, int);
298 static int em_msix_link(void *);
299 static void em_handle_link(void *context);
301 static void em_enable_vectors_82574(if_ctx_t);
303 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS);
304 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS);
305 static void em_if_led_func(if_ctx_t ctx, int onoff);
307 static int em_get_regs(SYSCTL_HANDLER_ARGS);
309 static void lem_smartspeed(struct adapter *adapter);
310 static void igb_configure_queues(struct adapter *adapter);
313 /*********************************************************************
314 * FreeBSD Device Interface Entry Points
315 *********************************************************************/
316 static device_method_t em_methods[] = {
317 /* Device interface */
318 DEVMETHOD(device_register, em_register),
319 DEVMETHOD(device_probe, iflib_device_probe),
320 DEVMETHOD(device_attach, iflib_device_attach),
321 DEVMETHOD(device_detach, iflib_device_detach),
322 DEVMETHOD(device_shutdown, iflib_device_shutdown),
323 DEVMETHOD(device_suspend, iflib_device_suspend),
324 DEVMETHOD(device_resume, iflib_device_resume),
328 static device_method_t igb_methods[] = {
329 /* Device interface */
330 DEVMETHOD(device_register, igb_register),
331 DEVMETHOD(device_probe, iflib_device_probe),
332 DEVMETHOD(device_attach, iflib_device_attach),
333 DEVMETHOD(device_detach, iflib_device_detach),
334 DEVMETHOD(device_shutdown, iflib_device_shutdown),
335 DEVMETHOD(device_suspend, iflib_device_suspend),
336 DEVMETHOD(device_resume, iflib_device_resume),
341 static driver_t em_driver = {
342 "em", em_methods, sizeof(struct adapter),
345 static devclass_t em_devclass;
346 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
348 MODULE_DEPEND(em, pci, 1, 1, 1);
349 MODULE_DEPEND(em, ether, 1, 1, 1);
350 MODULE_DEPEND(em, iflib, 1, 1, 1);
352 IFLIB_PNP_INFO(pci, em, em_vendor_info_array);
354 static driver_t igb_driver = {
355 "igb", igb_methods, sizeof(struct adapter),
358 static devclass_t igb_devclass;
359 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
361 MODULE_DEPEND(igb, pci, 1, 1, 1);
362 MODULE_DEPEND(igb, ether, 1, 1, 1);
363 MODULE_DEPEND(igb, iflib, 1, 1, 1);
365 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array);
367 static device_method_t em_if_methods[] = {
368 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
369 DEVMETHOD(ifdi_attach_post, em_if_attach_post),
370 DEVMETHOD(ifdi_detach, em_if_detach),
371 DEVMETHOD(ifdi_shutdown, em_if_shutdown),
372 DEVMETHOD(ifdi_suspend, em_if_suspend),
373 DEVMETHOD(ifdi_resume, em_if_resume),
374 DEVMETHOD(ifdi_init, em_if_init),
375 DEVMETHOD(ifdi_stop, em_if_stop),
376 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
377 DEVMETHOD(ifdi_intr_enable, em_if_enable_intr),
378 DEVMETHOD(ifdi_intr_disable, em_if_disable_intr),
379 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
380 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
381 DEVMETHOD(ifdi_queues_free, em_if_queues_free),
382 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
383 DEVMETHOD(ifdi_multi_set, em_if_multi_set),
384 DEVMETHOD(ifdi_media_status, em_if_media_status),
385 DEVMETHOD(ifdi_media_change, em_if_media_change),
386 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
387 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
388 DEVMETHOD(ifdi_timer, em_if_timer),
389 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
390 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
391 DEVMETHOD(ifdi_get_counter, em_if_get_counter),
392 DEVMETHOD(ifdi_led_func, em_if_led_func),
393 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable),
394 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable),
395 DEVMETHOD(ifdi_debug, em_if_debug),
400 * note that if (adapter->msix_mem) is replaced by:
401 * if (adapter->intr_type == IFLIB_INTR_MSIX)
403 static driver_t em_if_driver = {
404 "em_if", em_if_methods, sizeof(struct adapter)
407 /*********************************************************************
408 * Tunable default values.
409 *********************************************************************/
411 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000)
412 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024)
414 #define MAX_INTS_PER_SEC 8000
415 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256))
417 /* Allow common code without TSO */
422 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters");
424 static int em_disable_crc_stripping = 0;
425 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
426 &em_disable_crc_stripping, 0, "Disable CRC Stripping");
428 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
429 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
430 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
431 0, "Default transmit interrupt delay in usecs");
432 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
433 0, "Default receive interrupt delay in usecs");
435 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
436 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
437 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
438 &em_tx_abs_int_delay_dflt, 0,
439 "Default transmit interrupt delay limit in usecs");
440 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
441 &em_rx_abs_int_delay_dflt, 0,
442 "Default receive interrupt delay limit in usecs");
444 static int em_smart_pwr_down = FALSE;
445 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
446 0, "Set to true to leave smart power down enabled on newer adapters");
448 /* Controls whether promiscuous also shows bad packets */
449 static int em_debug_sbp = TRUE;
450 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
451 "Show bad packets in promiscuous mode");
453 /* How many packets rxeof tries to clean at a time */
454 static int em_rx_process_limit = 100;
455 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
456 &em_rx_process_limit, 0,
457 "Maximum number of received packets to process "
458 "at a time, -1 means unlimited");
460 /* Energy efficient ethernet - default to OFF */
461 static int eee_setting = 1;
462 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
463 "Enable Energy Efficient Ethernet");
466 ** Tuneable Interrupt rate
468 static int em_max_interrupt_rate = 8000;
469 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
470 &em_max_interrupt_rate, 0, "Maximum interrupts per second");
474 /* Global used in WOL setup with multiport cards */
475 static int global_quad_port_a = 0;
477 extern struct if_txrx igb_txrx;
478 extern struct if_txrx em_txrx;
479 extern struct if_txrx lem_txrx;
481 static struct if_shared_ctx em_sctx_init = {
482 .isc_magic = IFLIB_MAGIC,
483 .isc_q_align = PAGE_SIZE,
484 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
485 .isc_tx_maxsegsize = PAGE_SIZE,
486 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
487 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
488 .isc_rx_maxsize = MJUM9BYTES,
489 .isc_rx_nsegments = 1,
490 .isc_rx_maxsegsize = MJUM9BYTES,
494 .isc_admin_intrcnt = 1,
495 .isc_vendor_info = em_vendor_info_array,
496 .isc_driver_version = em_driver_version,
497 .isc_driver = &em_if_driver,
498 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
500 .isc_nrxd_min = {EM_MIN_RXD},
501 .isc_ntxd_min = {EM_MIN_TXD},
502 .isc_nrxd_max = {EM_MAX_RXD},
503 .isc_ntxd_max = {EM_MAX_TXD},
504 .isc_nrxd_default = {EM_DEFAULT_RXD},
505 .isc_ntxd_default = {EM_DEFAULT_TXD},
508 if_shared_ctx_t em_sctx = &em_sctx_init;
510 static struct if_shared_ctx igb_sctx_init = {
511 .isc_magic = IFLIB_MAGIC,
512 .isc_q_align = PAGE_SIZE,
513 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
514 .isc_tx_maxsegsize = PAGE_SIZE,
515 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
516 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
517 .isc_rx_maxsize = MJUM9BYTES,
518 .isc_rx_nsegments = 1,
519 .isc_rx_maxsegsize = MJUM9BYTES,
523 .isc_admin_intrcnt = 1,
524 .isc_vendor_info = igb_vendor_info_array,
525 .isc_driver_version = em_driver_version,
526 .isc_driver = &em_if_driver,
527 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
529 .isc_nrxd_min = {EM_MIN_RXD},
530 .isc_ntxd_min = {EM_MIN_TXD},
531 .isc_nrxd_max = {IGB_MAX_RXD},
532 .isc_ntxd_max = {IGB_MAX_TXD},
533 .isc_nrxd_default = {EM_DEFAULT_RXD},
534 .isc_ntxd_default = {EM_DEFAULT_TXD},
537 if_shared_ctx_t igb_sctx = &igb_sctx_init;
539 /*****************************************************************
543 ****************************************************************/
544 #define IGB_REGS_LEN 739
546 static int em_get_regs(SYSCTL_HANDLER_ARGS)
548 struct adapter *adapter = (struct adapter *)arg1;
549 struct e1000_hw *hw = &adapter->hw;
554 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK);
555 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
557 rc = sysctl_wire_old_buffer(req, 0);
560 free(regs_buff, M_DEVBUF);
564 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
567 free(regs_buff, M_DEVBUF);
571 /* General Registers */
572 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
573 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
574 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
575 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
576 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
577 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
578 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
579 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
580 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
581 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
582 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
583 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
584 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
585 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
586 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
587 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
588 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
589 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
590 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
591 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
592 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
593 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
595 sbuf_printf(sb, "General Registers\n");
596 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
597 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
598 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]);
600 sbuf_printf(sb, "Interrupt Registers\n");
601 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
603 sbuf_printf(sb, "RX Registers\n");
604 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
605 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
606 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
607 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
608 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
609 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
610 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
612 sbuf_printf(sb, "TX Registers\n");
613 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
614 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
615 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
616 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
617 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
618 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
619 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
620 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
621 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
622 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
623 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
625 free(regs_buff, M_DEVBUF);
629 if_softc_ctx_t scctx = adapter->shared;
630 struct rx_ring *rxr = &rx_que->rxr;
631 struct tx_ring *txr = &tx_que->txr;
632 int ntxd = scctx->isc_ntxd[0];
633 int nrxd = scctx->isc_nrxd[0];
636 for (j = 0; j < nrxd; j++) {
637 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
638 u32 length = le32toh(rxr->rx_base[j].wb.upper.length);
639 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
642 for (j = 0; j < min(ntxd, 256); j++) {
643 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
645 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n",
646 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
647 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
653 rc = sbuf_finish(sb);
659 em_register(device_t dev)
665 igb_register(device_t dev)
671 em_set_num_queues(if_ctx_t ctx)
673 struct adapter *adapter = iflib_get_softc(ctx);
676 /* Sanity check based on HW */
677 switch (adapter->hw.mac.type) {
701 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
702 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER
705 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
706 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \
707 IFCAP_LRO | IFCAP_VLAN_HWTSO
710 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
711 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \
712 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\
715 /*********************************************************************
716 * Device initialization routine
718 * The attach entry point is called when the driver is being loaded.
719 * This routine identifies the type of hardware, allocates all resources
720 * and initializes the hardware.
722 * return 0 on success, positive on failure
723 *********************************************************************/
726 em_if_attach_pre(if_ctx_t ctx)
728 struct adapter *adapter;
729 if_softc_ctx_t scctx;
734 INIT_DEBUGOUT("em_if_attach_pre begin");
735 dev = iflib_get_dev(ctx);
736 adapter = iflib_get_softc(ctx);
738 if (resource_disabled("em", device_get_unit(dev))) {
739 device_printf(dev, "Disabled by device hint\n");
743 adapter->ctx = adapter->osdep.ctx = ctx;
744 adapter->dev = adapter->osdep.dev = dev;
745 scctx = adapter->shared = iflib_get_softc_ctx(ctx);
746 adapter->media = iflib_get_media(ctx);
749 adapter->tx_process_limit = scctx->isc_ntxd[0];
752 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
753 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
754 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
755 em_sysctl_nvm_info, "I", "NVM Information");
757 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
758 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
759 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
760 em_sysctl_debug_info, "I", "Debug Information");
762 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
763 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
764 OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
765 em_set_flowcntl, "I", "Flow Control");
767 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
768 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
769 OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0,
770 em_get_regs, "A", "Dump Registers");
772 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
773 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
774 OID_AUTO, "rs_dump", CTLTYPE_INT | CTLFLAG_RW, adapter, 0,
775 em_get_rs, "I", "Dump RS indexes");
777 /* Determine hardware and mac info */
778 em_identify_hardware(ctx);
780 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR);
781 scctx->isc_tx_nsegments = EM_MAX_SCATTER;
782 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
783 device_printf(dev, "attach_pre capping queues at %d\n", scctx->isc_ntxqsets_max);
785 if (adapter->hw.mac.type >= igb_mac_min) {
788 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
789 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
790 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
791 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
792 scctx->isc_txrx = &igb_txrx;
793 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
794 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
795 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
796 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS;
797 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO |
798 CSUM_IP6_TCP | CSUM_IP6_UDP;
799 if (adapter->hw.mac.type != e1000_82575)
800 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
803 ** Some new devices, as with ixgbe, now may
804 ** use a different BAR, so we need to keep
805 ** track of which is used.
807 try_second_bar = pci_read_config(dev, scctx->isc_msix_bar, 4);
808 if (try_second_bar == 0)
809 scctx->isc_msix_bar += 4;
810 } else if (adapter->hw.mac.type >= em_mac_min) {
811 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
812 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
813 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
814 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
815 scctx->isc_txrx = &em_txrx;
816 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
817 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
818 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
819 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS;
821 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO}
822 * by default as we don't have workarounds for all associated
823 * silicon errata. E. g., with several MACs such as 82573E,
824 * TSO only works at Gigabit speed and otherwise can cause the
825 * hardware to hang (which also would be next to impossible to
826 * work around given that already queued TSO-using descriptors
827 * would need to be flushed and vlan(4) reconfigured at runtime
828 * in case of a link speed change). Moreover, MACs like 82579
829 * still can hang at Gigabit even with all publicly documented
830 * TSO workarounds implemented. Generally, the penality of
831 * these workarounds is rather high and may involve copying
832 * mbuf data around so advantages of TSO lapse. Still, TSO may
833 * work for a few MACs of this class - at least when sticking
834 * with Gigabit - in which case users may enable TSO manually.
836 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
837 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
839 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
840 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
841 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
842 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
843 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP;
844 scctx->isc_txrx = &lem_txrx;
845 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS;
846 if (adapter->hw.mac.type < e1000_82543)
847 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
848 scctx->isc_msix_bar = 0;
851 /* Setup PCI resources */
852 if (em_allocate_pci_resources(ctx)) {
853 device_printf(dev, "Allocation of PCI resources failed\n");
859 ** For ICH8 and family we need to
860 ** map the flash memory, and this
861 ** must happen after the MAC is
864 if ((hw->mac.type == e1000_ich8lan) ||
865 (hw->mac.type == e1000_ich9lan) ||
866 (hw->mac.type == e1000_ich10lan) ||
867 (hw->mac.type == e1000_pchlan) ||
868 (hw->mac.type == e1000_pch2lan) ||
869 (hw->mac.type == e1000_pch_lpt)) {
870 int rid = EM_BAR_TYPE_FLASH;
871 adapter->flash = bus_alloc_resource_any(dev,
872 SYS_RES_MEMORY, &rid, RF_ACTIVE);
873 if (adapter->flash == NULL) {
874 device_printf(dev, "Mapping of Flash failed\n");
878 /* This is used in the shared code */
879 hw->flash_address = (u8 *)adapter->flash;
880 adapter->osdep.flash_bus_space_tag =
881 rman_get_bustag(adapter->flash);
882 adapter->osdep.flash_bus_space_handle =
883 rman_get_bushandle(adapter->flash);
886 ** In the new SPT device flash is not a
887 ** separate BAR, rather it is also in BAR0,
888 ** so use the same tag and an offset handle for the
889 ** FLASH read/write macros in the shared code.
891 else if (hw->mac.type >= e1000_pch_spt) {
892 adapter->osdep.flash_bus_space_tag =
893 adapter->osdep.mem_bus_space_tag;
894 adapter->osdep.flash_bus_space_handle =
895 adapter->osdep.mem_bus_space_handle
896 + E1000_FLASH_BASE_ADDR;
899 /* Do Shared Code initialization */
900 error = e1000_setup_init_funcs(hw, TRUE);
902 device_printf(dev, "Setup of Shared code failed, error %d\n",
909 e1000_get_bus_info(hw);
911 /* Set up some sysctls for the tunable interrupt delays */
912 em_add_int_delay_sysctl(adapter, "rx_int_delay",
913 "receive interrupt delay in usecs", &adapter->rx_int_delay,
914 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
915 em_add_int_delay_sysctl(adapter, "tx_int_delay",
916 "transmit interrupt delay in usecs", &adapter->tx_int_delay,
917 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
918 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
919 "receive interrupt delay limit in usecs",
920 &adapter->rx_abs_int_delay,
921 E1000_REGISTER(hw, E1000_RADV),
922 em_rx_abs_int_delay_dflt);
923 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
924 "transmit interrupt delay limit in usecs",
925 &adapter->tx_abs_int_delay,
926 E1000_REGISTER(hw, E1000_TADV),
927 em_tx_abs_int_delay_dflt);
928 em_add_int_delay_sysctl(adapter, "itr",
929 "interrupt delay limit in usecs/4",
931 E1000_REGISTER(hw, E1000_ITR),
934 hw->mac.autoneg = DO_AUTO_NEG;
935 hw->phy.autoneg_wait_to_complete = FALSE;
936 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
938 if (adapter->hw.mac.type < em_mac_min) {
939 e1000_init_script_state_82541(&adapter->hw, TRUE);
940 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
943 if (hw->phy.media_type == e1000_media_type_copper) {
944 hw->phy.mdix = AUTO_ALL_MODES;
945 hw->phy.disable_polarity_correction = FALSE;
946 hw->phy.ms_type = EM_MASTER_SLAVE;
950 * Set the frame limits assuming
951 * standard ethernet sized frames.
953 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
954 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
957 * This controls when hardware reports transmit completion
960 hw->mac.report_tx_early = 1;
962 /* Allocate multicast array memory. */
963 adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN *
964 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
965 if (adapter->mta == NULL) {
966 device_printf(dev, "Can not allocate multicast setup array\n");
971 /* Check SOL/IDER usage */
972 if (e1000_check_reset_block(hw))
973 device_printf(dev, "PHY reset is blocked"
974 " due to SOL/IDER session.\n");
976 /* Sysctl for setting Energy Efficient Ethernet */
977 hw->dev_spec.ich8lan.eee_disable = eee_setting;
978 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
979 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
980 OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW,
981 adapter, 0, em_sysctl_eee, "I",
982 "Disable Energy Efficient Ethernet");
985 ** Start from a known state, this is
986 ** important in reading the nvm and
991 /* Make sure we have a good EEPROM before we read from it */
992 if (e1000_validate_nvm_checksum(hw) < 0) {
994 ** Some PCI-E parts fail the first check due to
995 ** the link being in sleep state, call it again,
996 ** if it fails a second time its a real issue.
998 if (e1000_validate_nvm_checksum(hw) < 0) {
1000 "The EEPROM Checksum Is Not Valid\n");
1006 /* Copy the permanent MAC address out of the EEPROM */
1007 if (e1000_read_mac_addr(hw) < 0) {
1008 device_printf(dev, "EEPROM read error while reading MAC"
1014 if (!em_is_valid_ether_addr(hw->mac.addr)) {
1015 device_printf(dev, "Invalid MAC address\n");
1020 /* Disable ULP support */
1021 e1000_disable_ulp_lpt_lp(hw, TRUE);
1024 * Get Wake-on-Lan and Management info for later use
1028 /* Enable only WOL MAGIC by default */
1029 scctx->isc_capenable &= ~IFCAP_WOL;
1030 if (adapter->wol != 0)
1031 scctx->isc_capenable |= IFCAP_WOL_MAGIC;
1033 iflib_set_mac(ctx, hw->mac.addr);
1038 em_release_hw_control(adapter);
1040 em_free_pci_resources(ctx);
1041 free(adapter->mta, M_DEVBUF);
1047 em_if_attach_post(if_ctx_t ctx)
1049 struct adapter *adapter = iflib_get_softc(ctx);
1050 struct e1000_hw *hw = &adapter->hw;
1053 /* Setup OS specific network interface */
1054 error = em_setup_interface(ctx);
1061 /* Initialize statistics */
1062 em_update_stats_counters(adapter);
1063 hw->mac.get_link_status = 1;
1064 em_if_update_admin_status(ctx);
1065 em_add_hw_stats(adapter);
1067 /* Non-AMT based hardware can now take control from firmware */
1068 if (adapter->has_manage && !adapter->has_amt)
1069 em_get_hw_control(adapter);
1071 INIT_DEBUGOUT("em_if_attach_post: end");
1076 em_release_hw_control(adapter);
1077 em_free_pci_resources(ctx);
1078 em_if_queues_free(ctx);
1079 free(adapter->mta, M_DEVBUF);
1084 /*********************************************************************
1085 * Device removal routine
1087 * The detach entry point is called when the driver is being removed.
1088 * This routine stops the adapter and deallocates all the resources
1089 * that were allocated for driver operation.
1091 * return 0 on success, positive on failure
1092 *********************************************************************/
1095 em_if_detach(if_ctx_t ctx)
1097 struct adapter *adapter = iflib_get_softc(ctx);
1099 INIT_DEBUGOUT("em_detach: begin");
1101 e1000_phy_hw_reset(&adapter->hw);
1103 em_release_manageability(adapter);
1104 em_release_hw_control(adapter);
1105 em_free_pci_resources(ctx);
1110 /*********************************************************************
1112 * Shutdown entry point
1114 **********************************************************************/
1117 em_if_shutdown(if_ctx_t ctx)
1119 return em_if_suspend(ctx);
1123 * Suspend/resume device methods.
1126 em_if_suspend(if_ctx_t ctx)
1128 struct adapter *adapter = iflib_get_softc(ctx);
1130 em_release_manageability(adapter);
1131 em_release_hw_control(adapter);
1132 em_enable_wakeup(ctx);
1137 em_if_resume(if_ctx_t ctx)
1139 struct adapter *adapter = iflib_get_softc(ctx);
1141 if (adapter->hw.mac.type == e1000_pch2lan)
1142 e1000_resume_workarounds_pchlan(&adapter->hw);
1144 em_init_manageability(adapter);
1150 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1153 struct adapter *adapter = iflib_get_softc(ctx);
1154 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1156 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1158 switch (adapter->hw.mac.type) {
1162 case e1000_ich10lan:
1169 case e1000_80003es2lan:
1170 /* 9K Jumbo Frame size */
1171 max_frame_size = 9234;
1174 max_frame_size = 4096;
1178 /* Adapters that do not support jumbo frames */
1179 max_frame_size = ETHER_MAX_LEN;
1182 if (adapter->hw.mac.type >= igb_mac_min)
1183 max_frame_size = 9234;
1185 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1187 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1191 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
1192 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1196 /*********************************************************************
1199 * This routine is used in two ways. It is used by the stack as
1200 * init entry point in network interface structure. It is also used
1201 * by the driver as a hw/sw initialization routine to get to a
1204 * return 0 on success, positive on failure
1205 **********************************************************************/
1208 em_if_init(if_ctx_t ctx)
1210 struct adapter *adapter = iflib_get_softc(ctx);
1211 struct ifnet *ifp = iflib_get_ifp(ctx);
1212 struct em_tx_queue *tx_que;
1214 INIT_DEBUGOUT("em_if_init: begin");
1216 /* Get the latest mac address, User can use a LAA */
1217 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr,
1220 /* Put the address into the Receive Address Array */
1221 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1224 * With the 82571 adapter, RAR[0] may be overwritten
1225 * when the other port is reset, we make a duplicate
1226 * in RAR[14] for that eventuality, this assures
1227 * the interface continues to function.
1229 if (adapter->hw.mac.type == e1000_82571) {
1230 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1231 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1232 E1000_RAR_ENTRIES - 1);
1236 /* Initialize the hardware */
1238 em_if_update_admin_status(ctx);
1240 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) {
1241 struct tx_ring *txr = &tx_que->txr;
1243 txr->tx_rs_cidx = txr->tx_rs_pidx = txr->tx_cidx_processed = 0;
1246 /* Setup VLAN support, basic and offload if available */
1247 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1249 /* Clear bad data from Rx FIFOs */
1250 if (adapter->hw.mac.type >= igb_mac_min)
1251 e1000_rx_fifo_flush_82575(&adapter->hw);
1253 /* Configure for OS presence */
1254 em_init_manageability(adapter);
1256 /* Prepare transmit descriptors and buffers */
1257 em_initialize_transmit_unit(ctx);
1259 /* Setup Multicast table */
1260 em_if_multi_set(ctx);
1263 * Figure out the desired mbuf
1264 * pool for doing jumbos
1266 if (adapter->hw.mac.max_frame_size <= 2048)
1267 adapter->rx_mbuf_sz = MCLBYTES;
1268 #ifndef CONTIGMALLOC_WORKS
1270 adapter->rx_mbuf_sz = MJUMPAGESIZE;
1272 else if (adapter->hw.mac.max_frame_size <= 4096)
1273 adapter->rx_mbuf_sz = MJUMPAGESIZE;
1275 adapter->rx_mbuf_sz = MJUM9BYTES;
1277 em_initialize_receive_unit(ctx);
1279 /* Use real VLAN Filter support? */
1280 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1281 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
1282 /* Use real VLAN Filter support */
1283 em_setup_vlan_hw_support(adapter);
1286 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1287 ctrl |= E1000_CTRL_VME;
1288 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1292 /* Don't lose promiscuous settings */
1293 em_if_set_promisc(ctx, IFF_PROMISC);
1294 e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1296 /* MSI/X configuration for 82574 */
1297 if (adapter->hw.mac.type == e1000_82574) {
1298 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1300 tmp |= E1000_CTRL_EXT_PBA_CLR;
1301 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1302 /* Set the IVAR - interrupt vector routing. */
1303 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars);
1304 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1305 igb_configure_queues(adapter);
1307 /* this clears any pending interrupts */
1308 E1000_READ_REG(&adapter->hw, E1000_ICR);
1309 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC);
1311 /* AMT based hardware can now take control from firmware */
1312 if (adapter->has_manage && adapter->has_amt)
1313 em_get_hw_control(adapter);
1315 /* Set Energy Efficient Ethernet */
1316 if (adapter->hw.mac.type >= igb_mac_min &&
1317 adapter->hw.phy.media_type == e1000_media_type_copper) {
1318 if (adapter->hw.mac.type == e1000_i354)
1319 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
1321 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
1325 /*********************************************************************
1327 * Fast Legacy/MSI Combined Interrupt Service routine
1329 *********************************************************************/
1333 struct adapter *adapter = arg;
1334 if_ctx_t ctx = adapter->ctx;
1337 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1339 if (adapter->intr_type != IFLIB_INTR_LEGACY)
1342 if (reg_icr == 0xffffffff)
1343 return FILTER_STRAY;
1345 /* Definitely not our interrupt. */
1347 return FILTER_STRAY;
1350 * Starting with the 82571 chip, bit 31 should be used to
1351 * determine whether the interrupt belongs to us.
1353 if (adapter->hw.mac.type >= e1000_82571 &&
1354 (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1355 return FILTER_STRAY;
1358 /* Link status change */
1359 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1360 adapter->hw.mac.get_link_status = 1;
1361 iflib_admin_intr_deferred(ctx);
1364 if (reg_icr & E1000_ICR_RXO)
1365 adapter->rx_overruns++;
1367 return (FILTER_SCHEDULE_THREAD);
1371 igb_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq)
1373 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims);
1377 em_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq)
1379 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims);
1383 igb_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq)
1385 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims);
1389 em_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq)
1391 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims);
1395 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1397 struct adapter *adapter = iflib_get_softc(ctx);
1398 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1400 if (adapter->hw.mac.type >= igb_mac_min)
1401 igb_rx_enable_queue(adapter, rxq);
1403 em_rx_enable_queue(adapter, rxq);
1408 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1410 struct adapter *adapter = iflib_get_softc(ctx);
1411 struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1413 if (adapter->hw.mac.type >= igb_mac_min)
1414 igb_tx_enable_queue(adapter, txq);
1416 em_tx_enable_queue(adapter, txq);
1420 /*********************************************************************
1422 * MSIX RX Interrupt Service routine
1424 **********************************************************************/
1426 em_msix_que(void *arg)
1428 struct em_rx_queue *que = arg;
1432 return (FILTER_SCHEDULE_THREAD);
1435 /*********************************************************************
1437 * MSIX Link Fast Interrupt Service routine
1439 **********************************************************************/
1441 em_msix_link(void *arg)
1443 struct adapter *adapter = arg;
1446 ++adapter->link_irq;
1447 MPASS(adapter->hw.back != NULL);
1448 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1450 if (reg_icr & E1000_ICR_RXO)
1451 adapter->rx_overruns++;
1453 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1454 em_handle_link(adapter->ctx);
1456 E1000_WRITE_REG(&adapter->hw, E1000_IMS,
1457 EM_MSIX_LINK | E1000_IMS_LSC);
1458 if (adapter->hw.mac.type >= igb_mac_min)
1459 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1463 * Because we must read the ICR for this interrupt
1464 * it may clear other causes using autoclear, for
1465 * this reason we simply create a soft interrupt
1466 * for all these vectors.
1468 if (reg_icr && adapter->hw.mac.type < igb_mac_min) {
1469 E1000_WRITE_REG(&adapter->hw,
1470 E1000_ICS, adapter->ims);
1473 return (FILTER_HANDLED);
1477 em_handle_link(void *context)
1479 if_ctx_t ctx = context;
1480 struct adapter *adapter = iflib_get_softc(ctx);
1482 adapter->hw.mac.get_link_status = 1;
1483 iflib_admin_intr_deferred(ctx);
1487 /*********************************************************************
1489 * Media Ioctl callback
1491 * This routine is called whenever the user queries the status of
1492 * the interface using ifconfig.
1494 **********************************************************************/
1496 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1498 struct adapter *adapter = iflib_get_softc(ctx);
1499 u_char fiber_type = IFM_1000_SX;
1501 INIT_DEBUGOUT("em_if_media_status: begin");
1503 iflib_admin_intr_deferred(ctx);
1505 ifmr->ifm_status = IFM_AVALID;
1506 ifmr->ifm_active = IFM_ETHER;
1508 if (!adapter->link_active) {
1512 ifmr->ifm_status |= IFM_ACTIVE;
1514 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
1515 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1516 if (adapter->hw.mac.type == e1000_82545)
1517 fiber_type = IFM_1000_LX;
1518 ifmr->ifm_active |= fiber_type | IFM_FDX;
1520 switch (adapter->link_speed) {
1522 ifmr->ifm_active |= IFM_10_T;
1525 ifmr->ifm_active |= IFM_100_TX;
1528 ifmr->ifm_active |= IFM_1000_T;
1531 if (adapter->link_duplex == FULL_DUPLEX)
1532 ifmr->ifm_active |= IFM_FDX;
1534 ifmr->ifm_active |= IFM_HDX;
1538 /*********************************************************************
1540 * Media Ioctl callback
1542 * This routine is called when the user changes speed/duplex using
1543 * media/mediopt option with ifconfig.
1545 **********************************************************************/
1547 em_if_media_change(if_ctx_t ctx)
1549 struct adapter *adapter = iflib_get_softc(ctx);
1550 struct ifmedia *ifm = iflib_get_media(ctx);
1552 INIT_DEBUGOUT("em_if_media_change: begin");
1554 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1557 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1559 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1560 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1565 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1566 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1569 adapter->hw.mac.autoneg = FALSE;
1570 adapter->hw.phy.autoneg_advertised = 0;
1571 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1572 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1574 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1577 adapter->hw.mac.autoneg = FALSE;
1578 adapter->hw.phy.autoneg_advertised = 0;
1579 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1580 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1582 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1585 device_printf(adapter->dev, "Unsupported media type\n");
1594 em_if_set_promisc(if_ctx_t ctx, int flags)
1596 struct adapter *adapter = iflib_get_softc(ctx);
1599 em_disable_promisc(ctx);
1601 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1603 if (flags & IFF_PROMISC) {
1604 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1605 /* Turn this on if you want to see bad packets */
1607 reg_rctl |= E1000_RCTL_SBP;
1608 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1609 } else if (flags & IFF_ALLMULTI) {
1610 reg_rctl |= E1000_RCTL_MPE;
1611 reg_rctl &= ~E1000_RCTL_UPE;
1612 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1618 em_disable_promisc(if_ctx_t ctx)
1620 struct adapter *adapter = iflib_get_softc(ctx);
1621 struct ifnet *ifp = iflib_get_ifp(ctx);
1625 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1626 reg_rctl &= (~E1000_RCTL_UPE);
1627 if (if_getflags(ifp) & IFF_ALLMULTI)
1628 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1630 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES);
1631 /* Don't disable if in MAX groups */
1632 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1633 reg_rctl &= (~E1000_RCTL_MPE);
1634 reg_rctl &= (~E1000_RCTL_SBP);
1635 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1639 /*********************************************************************
1642 * This routine is called whenever multicast address list is updated.
1644 **********************************************************************/
1647 em_if_multi_set(if_ctx_t ctx)
1649 struct adapter *adapter = iflib_get_softc(ctx);
1650 struct ifnet *ifp = iflib_get_ifp(ctx);
1652 u8 *mta; /* Multicast array memory */
1655 IOCTL_DEBUGOUT("em_set_multi: begin");
1658 bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1660 if (adapter->hw.mac.type == e1000_82542 &&
1661 adapter->hw.revision_id == E1000_REVISION_2) {
1662 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1663 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1664 e1000_pci_clear_mwi(&adapter->hw);
1665 reg_rctl |= E1000_RCTL_RST;
1666 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1670 if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES);
1672 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1673 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1674 reg_rctl |= E1000_RCTL_MPE;
1675 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1677 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
1679 if (adapter->hw.mac.type == e1000_82542 &&
1680 adapter->hw.revision_id == E1000_REVISION_2) {
1681 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1682 reg_rctl &= ~E1000_RCTL_RST;
1683 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1685 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1686 e1000_pci_set_mwi(&adapter->hw);
1691 /*********************************************************************
1694 * This routine checks for link status and updates statistics.
1696 **********************************************************************/
1699 em_if_timer(if_ctx_t ctx, uint16_t qid)
1701 struct adapter *adapter = iflib_get_softc(ctx);
1702 struct em_rx_queue *que;
1709 iflib_admin_intr_deferred(ctx);
1711 /* Mask to use in the irq trigger */
1712 if (adapter->intr_type == IFLIB_INTR_MSIX) {
1713 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++)
1714 trigger |= que->eims;
1716 trigger = E1000_ICS_RXDMT0;
1722 em_if_update_admin_status(if_ctx_t ctx)
1724 struct adapter *adapter = iflib_get_softc(ctx);
1725 struct e1000_hw *hw = &adapter->hw;
1726 device_t dev = iflib_get_dev(ctx);
1727 u32 link_check, thstat, ctrl;
1729 link_check = thstat = ctrl = 0;
1730 /* Get the cached link value or read phy for real */
1731 switch (hw->phy.media_type) {
1732 case e1000_media_type_copper:
1733 if (hw->mac.get_link_status) {
1734 if (hw->mac.type == e1000_pch_spt)
1736 /* Do the work to read phy */
1737 e1000_check_for_link(hw);
1738 link_check = !hw->mac.get_link_status;
1739 if (link_check) /* ESB2 fix */
1740 e1000_cfg_on_link_up(hw);
1745 case e1000_media_type_fiber:
1746 e1000_check_for_link(hw);
1747 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1750 case e1000_media_type_internal_serdes:
1751 e1000_check_for_link(hw);
1752 link_check = adapter->hw.mac.serdes_has_link;
1754 /* VF device is type_unknown */
1755 case e1000_media_type_unknown:
1756 e1000_check_for_link(hw);
1757 link_check = !hw->mac.get_link_status;
1763 /* Check for thermal downshift or shutdown */
1764 if (hw->mac.type == e1000_i350) {
1765 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1766 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1769 /* Now check for a transition */
1770 if (link_check && (adapter->link_active == 0)) {
1771 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
1772 &adapter->link_duplex);
1773 /* Check if we must disable SPEED_MODE bit on PCI-E */
1774 if ((adapter->link_speed != SPEED_1000) &&
1775 ((hw->mac.type == e1000_82571) ||
1776 (hw->mac.type == e1000_82572))) {
1778 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1779 tarc0 &= ~TARC_SPEED_MODE_BIT;
1780 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1783 device_printf(dev, "Link is up %d Mbps %s\n",
1784 adapter->link_speed,
1785 ((adapter->link_duplex == FULL_DUPLEX) ?
1786 "Full Duplex" : "Half Duplex"));
1787 adapter->link_active = 1;
1788 adapter->smartspeed = 0;
1789 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) ==
1790 E1000_CTRL_EXT_LINK_MODE_GMII &&
1791 (thstat & E1000_THSTAT_LINK_THROTTLE))
1792 device_printf(dev, "Link: thermal downshift\n");
1793 /* Delay Link Up for Phy update */
1794 if (((hw->mac.type == e1000_i210) ||
1795 (hw->mac.type == e1000_i211)) &&
1796 (hw->phy.id == I210_I_PHY_ID))
1797 msec_delay(I210_LINK_DELAY);
1798 /* Reset if the media type changed. */
1799 if ((hw->dev_spec._82575.media_changed) &&
1800 (adapter->hw.mac.type >= igb_mac_min)) {
1801 hw->dev_spec._82575.media_changed = false;
1802 adapter->flags |= IGB_MEDIA_RESET;
1805 iflib_link_state_change(ctx, LINK_STATE_UP,
1806 IF_Mbps(adapter->link_speed));
1807 } else if (!link_check && (adapter->link_active == 1)) {
1808 adapter->link_speed = 0;
1809 adapter->link_duplex = 0;
1810 adapter->link_active = 0;
1811 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
1813 em_update_stats_counters(adapter);
1815 /* Reset LAA into RAR[0] on 82571 */
1816 if ((adapter->hw.mac.type == e1000_82571) &&
1817 e1000_get_laa_state_82571(&adapter->hw))
1818 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1820 if (adapter->hw.mac.type < em_mac_min)
1821 lem_smartspeed(adapter);
1823 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC);
1826 /*********************************************************************
1828 * This routine disables all traffic on the adapter by issuing a
1829 * global reset on the MAC and deallocates TX/RX buffers.
1831 * This routine should always be called with BOTH the CORE
1833 **********************************************************************/
1836 em_if_stop(if_ctx_t ctx)
1838 struct adapter *adapter = iflib_get_softc(ctx);
1840 INIT_DEBUGOUT("em_stop: begin");
1842 e1000_reset_hw(&adapter->hw);
1843 if (adapter->hw.mac.type >= e1000_82544)
1844 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0);
1846 e1000_led_off(&adapter->hw);
1847 e1000_cleanup_led(&adapter->hw);
1851 /*********************************************************************
1853 * Determine hardware revision.
1855 **********************************************************************/
1857 em_identify_hardware(if_ctx_t ctx)
1859 device_t dev = iflib_get_dev(ctx);
1860 struct adapter *adapter = iflib_get_softc(ctx);
1862 /* Make sure our PCI config space has the necessary stuff set */
1863 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1865 /* Save off the information about this board */
1866 adapter->hw.vendor_id = pci_get_vendor(dev);
1867 adapter->hw.device_id = pci_get_device(dev);
1868 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1869 adapter->hw.subsystem_vendor_id =
1870 pci_read_config(dev, PCIR_SUBVEND_0, 2);
1871 adapter->hw.subsystem_device_id =
1872 pci_read_config(dev, PCIR_SUBDEV_0, 2);
1874 /* Do Shared Code Init and Setup */
1875 if (e1000_set_mac_type(&adapter->hw)) {
1876 device_printf(dev, "Setup init failure\n");
1882 em_allocate_pci_resources(if_ctx_t ctx)
1884 struct adapter *adapter = iflib_get_softc(ctx);
1885 device_t dev = iflib_get_dev(ctx);
1889 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1891 if (adapter->memory == NULL) {
1892 device_printf(dev, "Unable to allocate bus resource: memory\n");
1895 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory);
1896 adapter->osdep.mem_bus_space_handle =
1897 rman_get_bushandle(adapter->memory);
1898 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle;
1900 /* Only older adapters use IO mapping */
1901 if (adapter->hw.mac.type < em_mac_min &&
1902 adapter->hw.mac.type > e1000_82543) {
1903 /* Figure our where our IO BAR is ? */
1904 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1905 val = pci_read_config(dev, rid, 4);
1906 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1907 adapter->io_rid = rid;
1911 /* check for 64bit BAR */
1912 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1915 if (rid >= PCIR_CIS) {
1916 device_printf(dev, "Unable to locate IO BAR\n");
1919 adapter->ioport = bus_alloc_resource_any(dev,
1920 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE);
1921 if (adapter->ioport == NULL) {
1922 device_printf(dev, "Unable to allocate bus resource: "
1926 adapter->hw.io_base = 0;
1927 adapter->osdep.io_bus_space_tag =
1928 rman_get_bustag(adapter->ioport);
1929 adapter->osdep.io_bus_space_handle =
1930 rman_get_bushandle(adapter->ioport);
1933 adapter->hw.back = &adapter->osdep;
1938 /*********************************************************************
1940 * Setup the MSIX Interrupt handlers
1942 **********************************************************************/
1944 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
1946 struct adapter *adapter = iflib_get_softc(ctx);
1947 struct em_rx_queue *rx_que = adapter->rx_queues;
1948 struct em_tx_queue *tx_que = adapter->tx_queues;
1949 int error, rid, i, vector = 0, rx_vectors;
1952 /* First set up ring resources */
1953 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) {
1955 snprintf(buf, sizeof(buf), "rxq%d", i);
1956 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
1958 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
1959 adapter->rx_num_queues = i + 1;
1963 rx_que->msix = vector;
1966 * Set the bit to enable interrupt
1967 * in E1000_IMS -- bits 20 and 21
1968 * are for RX0 and RX1, note this has
1969 * NOTHING to do with the MSIX vector
1971 if (adapter->hw.mac.type == e1000_82574) {
1972 rx_que->eims = 1 << (20 + i);
1973 adapter->ims |= rx_que->eims;
1974 adapter->ivars |= (8 | rx_que->msix) << (i * 4);
1975 } else if (adapter->hw.mac.type == e1000_82575)
1976 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
1978 rx_que->eims = 1 << vector;
1980 rx_vectors = vector;
1983 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) {
1984 snprintf(buf, sizeof(buf), "txq%d", i);
1985 tx_que = &adapter->tx_queues[i];
1986 iflib_softirq_alloc_generic(ctx,
1987 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq,
1988 IFLIB_INTR_TX, tx_que, tx_que->me, buf);
1990 tx_que->msix = (vector % adapter->tx_num_queues);
1993 * Set the bit to enable interrupt
1994 * in E1000_IMS -- bits 22 and 23
1995 * are for TX0 and TX1, note this has
1996 * NOTHING to do with the MSIX vector
1998 if (adapter->hw.mac.type == e1000_82574) {
1999 tx_que->eims = 1 << (22 + i);
2000 adapter->ims |= tx_que->eims;
2001 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
2002 } else if (adapter->hw.mac.type == e1000_82575) {
2003 tx_que->eims = E1000_EICR_TX_QUEUE0 << (i % adapter->tx_num_queues);
2005 tx_que->eims = 1 << (i % adapter->tx_num_queues);
2009 /* Link interrupt */
2010 rid = rx_vectors + 1;
2011 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq");
2014 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
2017 adapter->linkvec = rx_vectors;
2018 if (adapter->hw.mac.type < igb_mac_min) {
2019 adapter->ivars |= (8 | rx_vectors) << 16;
2020 adapter->ivars |= 0x80000000;
2024 iflib_irq_free(ctx, &adapter->irq);
2025 rx_que = adapter->rx_queues;
2026 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++)
2027 iflib_irq_free(ctx, &rx_que->que_irq);
2032 igb_configure_queues(struct adapter *adapter)
2034 struct e1000_hw *hw = &adapter->hw;
2035 struct em_rx_queue *rx_que;
2036 struct em_tx_queue *tx_que;
2037 u32 tmp, ivar = 0, newitr = 0;
2039 /* First turn on RSS capability */
2040 if (adapter->hw.mac.type != e1000_82575)
2041 E1000_WRITE_REG(hw, E1000_GPIE,
2042 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
2043 E1000_GPIE_PBA | E1000_GPIE_NSICR);
2046 switch (adapter->hw.mac.type) {
2053 case e1000_vfadapt_i350:
2055 for (int i = 0; i < adapter->rx_num_queues; i++) {
2057 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2058 rx_que = &adapter->rx_queues[i];
2061 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2064 ivar |= rx_que->msix | E1000_IVAR_VALID;
2066 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2069 for (int i = 0; i < adapter->tx_num_queues; i++) {
2071 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2072 tx_que = &adapter->tx_queues[i];
2075 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2078 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2080 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2081 adapter->que_mask |= tx_que->eims;
2084 /* And for the link interrupt */
2085 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2086 adapter->link_mask = 1 << adapter->linkvec;
2087 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2091 for (int i = 0; i < adapter->rx_num_queues; i++) {
2092 u32 index = i & 0x7; /* Each IVAR has two entries */
2093 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2094 rx_que = &adapter->rx_queues[i];
2097 ivar |= rx_que->msix | E1000_IVAR_VALID;
2100 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2102 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2103 adapter->que_mask |= rx_que->eims;
2106 for (int i = 0; i < adapter->tx_num_queues; i++) {
2107 u32 index = i & 0x7; /* Each IVAR has two entries */
2108 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2109 tx_que = &adapter->tx_queues[i];
2112 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2115 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2117 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2118 adapter->que_mask |= tx_que->eims;
2121 /* And for the link interrupt */
2122 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2123 adapter->link_mask = 1 << adapter->linkvec;
2124 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2128 /* enable MSI-X support*/
2129 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2130 tmp |= E1000_CTRL_EXT_PBA_CLR;
2131 /* Auto-Mask interrupts upon ICR read. */
2132 tmp |= E1000_CTRL_EXT_EIAME;
2133 tmp |= E1000_CTRL_EXT_IRCA;
2134 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2137 for (int i = 0; i < adapter->rx_num_queues; i++) {
2138 rx_que = &adapter->rx_queues[i];
2139 tmp = E1000_EICR_RX_QUEUE0 << i;
2140 tmp |= E1000_EICR_TX_QUEUE0 << i;
2142 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2144 adapter->que_mask |= rx_que->eims;
2148 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec),
2150 adapter->link_mask |= E1000_EIMS_OTHER;
2155 /* Set the starting interrupt rate */
2156 if (em_max_interrupt_rate > 0)
2157 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2159 if (hw->mac.type == e1000_82575)
2160 newitr |= newitr << 16;
2162 newitr |= E1000_EITR_CNT_IGNR;
2164 for (int i = 0; i < adapter->rx_num_queues; i++) {
2165 rx_que = &adapter->rx_queues[i];
2166 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2173 em_free_pci_resources(if_ctx_t ctx)
2175 struct adapter *adapter = iflib_get_softc(ctx);
2176 struct em_rx_queue *que = adapter->rx_queues;
2177 device_t dev = iflib_get_dev(ctx);
2179 /* Release all msix queue resources */
2180 if (adapter->intr_type == IFLIB_INTR_MSIX)
2181 iflib_irq_free(ctx, &adapter->irq);
2183 for (int i = 0; i < adapter->rx_num_queues; i++, que++) {
2184 iflib_irq_free(ctx, &que->que_irq);
2187 /* First release all the interrupt resources */
2188 if (adapter->memory != NULL) {
2189 bus_release_resource(dev, SYS_RES_MEMORY,
2190 PCIR_BAR(0), adapter->memory);
2191 adapter->memory = NULL;
2194 if (adapter->flash != NULL) {
2195 bus_release_resource(dev, SYS_RES_MEMORY,
2196 EM_FLASH, adapter->flash);
2197 adapter->flash = NULL;
2199 if (adapter->ioport != NULL)
2200 bus_release_resource(dev, SYS_RES_IOPORT,
2201 adapter->io_rid, adapter->ioport);
2204 /* Setup MSI or MSI/X */
2206 em_setup_msix(if_ctx_t ctx)
2208 struct adapter *adapter = iflib_get_softc(ctx);
2210 if (adapter->hw.mac.type == e1000_82574) {
2211 em_enable_vectors_82574(ctx);
2216 /*********************************************************************
2218 * Initialize the hardware to a configuration
2219 * as specified by the adapter structure.
2221 **********************************************************************/
2224 lem_smartspeed(struct adapter *adapter)
2228 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) ||
2229 adapter->hw.mac.autoneg == 0 ||
2230 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2233 if (adapter->smartspeed == 0) {
2234 /* If Master/Slave config fault is asserted twice,
2235 * we assume back-to-back */
2236 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2237 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2239 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2240 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2241 e1000_read_phy_reg(&adapter->hw,
2242 PHY_1000T_CTRL, &phy_tmp);
2243 if(phy_tmp & CR_1000T_MS_ENABLE) {
2244 phy_tmp &= ~CR_1000T_MS_ENABLE;
2245 e1000_write_phy_reg(&adapter->hw,
2246 PHY_1000T_CTRL, phy_tmp);
2247 adapter->smartspeed++;
2248 if(adapter->hw.mac.autoneg &&
2249 !e1000_copper_link_autoneg(&adapter->hw) &&
2250 !e1000_read_phy_reg(&adapter->hw,
2251 PHY_CONTROL, &phy_tmp)) {
2252 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2253 MII_CR_RESTART_AUTO_NEG);
2254 e1000_write_phy_reg(&adapter->hw,
2255 PHY_CONTROL, phy_tmp);
2260 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2261 /* If still no link, perhaps using 2/3 pair cable */
2262 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2263 phy_tmp |= CR_1000T_MS_ENABLE;
2264 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2265 if(adapter->hw.mac.autoneg &&
2266 !e1000_copper_link_autoneg(&adapter->hw) &&
2267 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2268 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2269 MII_CR_RESTART_AUTO_NEG);
2270 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2273 /* Restart process after EM_SMARTSPEED_MAX iterations */
2274 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2275 adapter->smartspeed = 0;
2278 /*********************************************************************
2280 * Initialize the DMA Coalescing feature
2282 **********************************************************************/
2284 igb_init_dmac(struct adapter *adapter, u32 pba)
2286 device_t dev = adapter->dev;
2287 struct e1000_hw *hw = &adapter->hw;
2288 u32 dmac, reg = ~E1000_DMACR_DMAC_EN;
2292 if (hw->mac.type == e1000_i211)
2295 max_frame_size = adapter->shared->isc_max_frame_size;
2296 if (hw->mac.type > e1000_82580) {
2298 if (adapter->dmac == 0) { /* Disabling it */
2299 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2302 device_printf(dev, "DMA Coalescing enabled\n");
2304 /* Set starting threshold */
2305 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
2307 hwm = 64 * pba - max_frame_size / 16;
2308 if (hwm < 64 * (pba - 6))
2309 hwm = 64 * (pba - 6);
2310 reg = E1000_READ_REG(hw, E1000_FCRTC);
2311 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
2312 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
2313 & E1000_FCRTC_RTH_COAL_MASK);
2314 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
2317 dmac = pba - max_frame_size / 512;
2318 if (dmac < pba - 10)
2320 reg = E1000_READ_REG(hw, E1000_DMACR);
2321 reg &= ~E1000_DMACR_DMACTHR_MASK;
2322 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT)
2323 & E1000_DMACR_DMACTHR_MASK);
2325 /* transition to L0x or L1 if available..*/
2326 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
2328 /* Check if status is 2.5Gb backplane connection
2329 * before configuration of watchdog timer, which is
2330 * in msec values in 12.8usec intervals
2331 * watchdog timer= msec values in 32usec intervals
2332 * for non 2.5Gb connection
2334 if (hw->mac.type == e1000_i354) {
2335 int status = E1000_READ_REG(hw, E1000_STATUS);
2336 if ((status & E1000_STATUS_2P5_SKU) &&
2337 (!(status & E1000_STATUS_2P5_SKU_OVER)))
2338 reg |= ((adapter->dmac * 5) >> 6);
2340 reg |= (adapter->dmac >> 5);
2342 reg |= (adapter->dmac >> 5);
2345 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2347 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
2349 /* Set the interval before transition */
2350 reg = E1000_READ_REG(hw, E1000_DMCTLX);
2351 if (hw->mac.type == e1000_i350)
2352 reg |= IGB_DMCTLX_DCFLUSH_DIS;
2354 ** in 2.5Gb connection, TTLX unit is 0.4 usec
2355 ** which is 0x4*2 = 0xA. But delay is still 4 usec
2357 if (hw->mac.type == e1000_i354) {
2358 int status = E1000_READ_REG(hw, E1000_STATUS);
2359 if ((status & E1000_STATUS_2P5_SKU) &&
2360 (!(status & E1000_STATUS_2P5_SKU_OVER)))
2368 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
2370 /* free space in tx packet buffer to wake from DMA coal */
2371 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE -
2372 (2 * max_frame_size)) >> 6);
2374 /* make low power state decision controlled by DMA coal */
2375 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2376 reg &= ~E1000_PCIEMISC_LX_DECISION;
2377 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
2379 } else if (hw->mac.type == e1000_82580) {
2380 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2381 E1000_WRITE_REG(hw, E1000_PCIEMISC,
2382 reg & ~E1000_PCIEMISC_LX_DECISION);
2383 E1000_WRITE_REG(hw, E1000_DMACR, 0);
2388 em_reset(if_ctx_t ctx)
2390 device_t dev = iflib_get_dev(ctx);
2391 struct adapter *adapter = iflib_get_softc(ctx);
2392 struct ifnet *ifp = iflib_get_ifp(ctx);
2393 struct e1000_hw *hw = &adapter->hw;
2397 INIT_DEBUGOUT("em_reset: begin");
2398 /* Let the firmware know the OS is in control */
2399 em_get_hw_control(adapter);
2401 /* Set up smart power down as default off on newer adapters. */
2402 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2403 hw->mac.type == e1000_82572)) {
2406 /* Speed up time to link by disabling smart power down. */
2407 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2408 phy_tmp &= ~IGP02E1000_PM_SPD;
2409 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2413 * Packet Buffer Allocation (PBA)
2414 * Writing PBA sets the receive portion of the buffer
2415 * the remainder is used for the transmit buffer.
2417 switch (hw->mac.type) {
2418 /* Total Packet Buffer on these is 48K */
2421 case e1000_80003es2lan:
2422 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2424 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
2425 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2429 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2435 case e1000_ich10lan:
2436 /* Boost Receive side for jumbo frames */
2437 if (adapter->hw.mac.max_frame_size > 4096)
2438 pba = E1000_PBA_14K;
2440 pba = E1000_PBA_10K;
2447 pba = E1000_PBA_26K;
2450 pba = E1000_PBA_32K;
2454 pba = E1000_READ_REG(hw, E1000_RXPBS);
2455 pba &= E1000_RXPBS_SIZE_MASK_82576;
2460 case e1000_vfadapt_i350:
2461 pba = E1000_READ_REG(hw, E1000_RXPBS);
2462 pba = e1000_rxpbs_adjust_82580(pba);
2466 pba = E1000_PBA_34K;
2469 if (adapter->hw.mac.max_frame_size > 8192)
2470 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2472 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2475 /* Special needs in case of Jumbo frames */
2476 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) {
2477 u32 tx_space, min_tx, min_rx;
2478 pba = E1000_READ_REG(hw, E1000_PBA);
2479 tx_space = pba >> 16;
2481 min_tx = (adapter->hw.mac.max_frame_size +
2482 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
2483 min_tx = roundup2(min_tx, 1024);
2485 min_rx = adapter->hw.mac.max_frame_size;
2486 min_rx = roundup2(min_rx, 1024);
2488 if (tx_space < min_tx &&
2489 ((min_tx - tx_space) < pba)) {
2490 pba = pba - (min_tx - tx_space);
2492 * if short on rx space, rx wins
2493 * and must trump tx adjustment
2498 E1000_WRITE_REG(hw, E1000_PBA, pba);
2501 if (hw->mac.type < igb_mac_min)
2502 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
2504 INIT_DEBUGOUT1("em_reset: pba=%dK",pba);
2507 * These parameters control the automatic generation (Tx) and
2508 * response (Rx) to Ethernet PAUSE frames.
2509 * - High water mark should allow for at least two frames to be
2510 * received after sending an XOFF.
2511 * - Low water mark works best when it is very near the high water mark.
2512 * This allows the receiver to restart by sending XON when it has
2513 * drained a bit. Here we use an arbitrary value of 1500 which will
2514 * restart after one full frame is pulled from the buffer. There
2515 * could be several smaller frames in the buffer and if so they will
2516 * not trigger the XON until their total number reduces the buffer
2518 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2520 rx_buffer_size = (pba & 0xffff) << 10;
2521 hw->fc.high_water = rx_buffer_size -
2522 roundup2(adapter->hw.mac.max_frame_size, 1024);
2523 hw->fc.low_water = hw->fc.high_water - 1500;
2525 if (adapter->fc) /* locally set flow control value? */
2526 hw->fc.requested_mode = adapter->fc;
2528 hw->fc.requested_mode = e1000_fc_full;
2530 if (hw->mac.type == e1000_80003es2lan)
2531 hw->fc.pause_time = 0xFFFF;
2533 hw->fc.pause_time = EM_FC_PAUSE_TIME;
2535 hw->fc.send_xon = TRUE;
2537 /* Device specific overrides/settings */
2538 switch (hw->mac.type) {
2540 /* Workaround: no TX flow ctrl for PCH */
2541 hw->fc.requested_mode = e1000_fc_rx_pause;
2542 hw->fc.pause_time = 0xFFFF; /* override */
2543 if (if_getmtu(ifp) > ETHERMTU) {
2544 hw->fc.high_water = 0x3500;
2545 hw->fc.low_water = 0x1500;
2547 hw->fc.high_water = 0x5000;
2548 hw->fc.low_water = 0x3000;
2550 hw->fc.refresh_time = 0x1000;
2556 hw->fc.high_water = 0x5C20;
2557 hw->fc.low_water = 0x5048;
2558 hw->fc.pause_time = 0x0650;
2559 hw->fc.refresh_time = 0x0400;
2560 /* Jumbos need adjusted PBA */
2561 if (if_getmtu(ifp) > ETHERMTU)
2562 E1000_WRITE_REG(hw, E1000_PBA, 12);
2564 E1000_WRITE_REG(hw, E1000_PBA, 26);
2568 /* 8-byte granularity */
2569 hw->fc.low_water = hw->fc.high_water - 8;
2577 case e1000_vfadapt_i350:
2578 /* 16-byte granularity */
2579 hw->fc.low_water = hw->fc.high_water - 16;
2582 case e1000_ich10lan:
2583 if (if_getmtu(ifp) > ETHERMTU) {
2584 hw->fc.high_water = 0x2800;
2585 hw->fc.low_water = hw->fc.high_water - 8;
2590 if (hw->mac.type == e1000_80003es2lan)
2591 hw->fc.pause_time = 0xFFFF;
2595 /* Issue a global reset */
2597 if (adapter->hw.mac.type >= igb_mac_min) {
2598 E1000_WRITE_REG(hw, E1000_WUC, 0);
2600 E1000_WRITE_REG(hw, E1000_WUFC, 0);
2601 em_disable_aspm(adapter);
2603 if (adapter->flags & IGB_MEDIA_RESET) {
2604 e1000_setup_init_funcs(hw, TRUE);
2605 e1000_get_bus_info(hw);
2606 adapter->flags &= ~IGB_MEDIA_RESET;
2609 if (e1000_init_hw(hw) < 0) {
2610 device_printf(dev, "Hardware Initialization Failed\n");
2613 if (adapter->hw.mac.type >= igb_mac_min)
2614 igb_init_dmac(adapter, pba);
2616 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2617 e1000_get_phy_info(hw);
2618 e1000_check_for_link(hw);
2621 #define RSSKEYLEN 10
2623 em_initialize_rss_mapping(struct adapter *adapter)
2625 uint8_t rss_key[4 * RSSKEYLEN];
2627 struct e1000_hw *hw = &adapter->hw;
2633 arc4rand(rss_key, sizeof(rss_key), 0);
2634 for (i = 0; i < RSSKEYLEN; ++i) {
2637 rssrk = EM_RSSRK_VAL(rss_key, i);
2638 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2642 * Configure RSS redirect table in following fashion:
2643 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2645 for (i = 0; i < sizeof(reta); ++i) {
2648 q = (i % adapter->rx_num_queues) << 7;
2649 reta |= q << (8 * i);
2652 for (i = 0; i < 32; ++i)
2653 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2655 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2656 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2657 E1000_MRQC_RSS_FIELD_IPV4 |
2658 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2659 E1000_MRQC_RSS_FIELD_IPV6_EX |
2660 E1000_MRQC_RSS_FIELD_IPV6);
2665 igb_initialize_rss_mapping(struct adapter *adapter)
2667 struct e1000_hw *hw = &adapter->hw;
2671 u32 rss_key[10], mrqc, shift = 0;
2674 if (adapter->hw.mac.type == e1000_82575)
2678 * The redirection table controls which destination
2679 * queue each bucket redirects traffic to.
2680 * Each DWORD represents four queues, with the LSB
2681 * being the first queue in the DWORD.
2683 * This just allocates buckets to queues using round-robin
2686 * NOTE: It Just Happens to line up with the default
2687 * RSS allocation method.
2690 /* Warning FM follows */
2692 for (i = 0; i < 128; i++) {
2694 queue_id = rss_get_indirection_to_bucket(i);
2696 * If we have more queues than buckets, we'll
2697 * end up mapping buckets to a subset of the
2700 * If we have more buckets than queues, we'll
2701 * end up instead assigning multiple buckets
2704 * Both are suboptimal, but we need to handle
2705 * the case so we don't go out of bounds
2706 * indexing arrays and such.
2708 queue_id = queue_id % adapter->rx_num_queues;
2710 queue_id = (i % adapter->rx_num_queues);
2712 /* Adjust if required */
2713 queue_id = queue_id << shift;
2716 * The low 8 bits are for hash value (n+0);
2717 * The next 8 bits are for hash value (n+1), etc.
2720 reta = reta | ( ((uint32_t) queue_id) << 24);
2722 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2727 /* Now fill in hash table */
2730 * MRQC: Multiple Receive Queues Command
2731 * Set queuing to RSS control, number depends on the device.
2733 mrqc = E1000_MRQC_ENABLE_RSS_8Q;
2736 /* XXX ew typecasting */
2737 rss_getkey((uint8_t *) &rss_key);
2739 arc4rand(&rss_key, sizeof(rss_key), 0);
2741 for (i = 0; i < 10; i++)
2742 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]);
2745 * Configure the RSS fields to hash upon.
2747 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2748 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2749 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2750 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2751 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2752 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2753 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2754 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2756 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2759 /*********************************************************************
2761 * Setup networking device structure and register an interface.
2763 **********************************************************************/
2765 em_setup_interface(if_ctx_t ctx)
2767 struct ifnet *ifp = iflib_get_ifp(ctx);
2768 struct adapter *adapter = iflib_get_softc(ctx);
2769 if_softc_ctx_t scctx = adapter->shared;
2771 INIT_DEBUGOUT("em_setup_interface: begin");
2774 if (adapter->tx_num_queues == 1) {
2775 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
2776 if_setsendqready(ifp);
2780 * Specify the media types supported by this adapter and register
2781 * callbacks to update media and link information
2783 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
2784 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
2785 u_char fiber_type = IFM_1000_SX; /* default type */
2787 if (adapter->hw.mac.type == e1000_82545)
2788 fiber_type = IFM_1000_LX;
2789 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
2790 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2792 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2793 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2794 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2795 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2796 if (adapter->hw.phy.type != e1000_phy_ife) {
2797 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2798 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2801 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2802 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO);
2807 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
2809 struct adapter *adapter = iflib_get_softc(ctx);
2810 if_softc_ctx_t scctx = adapter->shared;
2811 int error = E1000_SUCCESS;
2812 struct em_tx_queue *que;
2815 MPASS(adapter->tx_num_queues > 0);
2816 MPASS(adapter->tx_num_queues == ntxqsets);
2818 /* First allocate the top level queue structs */
2819 if (!(adapter->tx_queues =
2820 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
2821 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2822 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2826 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) {
2827 /* Set up some basics */
2829 struct tx_ring *txr = &que->txr;
2830 txr->adapter = que->adapter = adapter;
2831 que->me = txr->me = i;
2833 /* Allocate report status array */
2834 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2835 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n");
2839 for (j = 0; j < scctx->isc_ntxd[0]; j++)
2840 txr->tx_rsq[j] = QIDX_INVALID;
2841 /* get the virtual and physical address of the hardware queues */
2842 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
2843 txr->tx_paddr = paddrs[i*ntxqs];
2846 device_printf(iflib_get_dev(ctx), "allocated for %d tx_queues\n", adapter->tx_num_queues);
2849 em_if_queues_free(ctx);
2854 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
2856 struct adapter *adapter = iflib_get_softc(ctx);
2857 int error = E1000_SUCCESS;
2858 struct em_rx_queue *que;
2861 MPASS(adapter->rx_num_queues > 0);
2862 MPASS(adapter->rx_num_queues == nrxqsets);
2864 /* First allocate the top level queue structs */
2865 if (!(adapter->rx_queues =
2866 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
2867 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2868 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2873 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) {
2874 /* Set up some basics */
2875 struct rx_ring *rxr = &que->rxr;
2876 rxr->adapter = que->adapter = adapter;
2878 que->me = rxr->me = i;
2880 /* get the virtual and physical address of the hardware queues */
2881 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
2882 rxr->rx_paddr = paddrs[i*nrxqs];
2885 device_printf(iflib_get_dev(ctx), "allocated for %d rx_queues\n", adapter->rx_num_queues);
2889 em_if_queues_free(ctx);
2894 em_if_queues_free(if_ctx_t ctx)
2896 struct adapter *adapter = iflib_get_softc(ctx);
2897 struct em_tx_queue *tx_que = adapter->tx_queues;
2898 struct em_rx_queue *rx_que = adapter->rx_queues;
2900 if (tx_que != NULL) {
2901 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
2902 struct tx_ring *txr = &tx_que->txr;
2903 if (txr->tx_rsq == NULL)
2906 free(txr->tx_rsq, M_DEVBUF);
2909 free(adapter->tx_queues, M_DEVBUF);
2910 adapter->tx_queues = NULL;
2913 if (rx_que != NULL) {
2914 free(adapter->rx_queues, M_DEVBUF);
2915 adapter->rx_queues = NULL;
2918 em_release_hw_control(adapter);
2920 if (adapter->mta != NULL) {
2921 free(adapter->mta, M_DEVBUF);
2925 /*********************************************************************
2927 * Enable transmit unit.
2929 **********************************************************************/
2931 em_initialize_transmit_unit(if_ctx_t ctx)
2933 struct adapter *adapter = iflib_get_softc(ctx);
2934 if_softc_ctx_t scctx = adapter->shared;
2935 struct em_tx_queue *que;
2936 struct tx_ring *txr;
2937 struct e1000_hw *hw = &adapter->hw;
2938 u32 tctl, txdctl = 0, tarc, tipg = 0;
2940 INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
2942 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
2946 que = &adapter->tx_queues[i];
2948 bus_addr = txr->tx_paddr;
2950 /* Clear checksum offload context. */
2951 offp = (caddr_t)&txr->csum_flags;
2952 endp = (caddr_t)(txr + 1);
2953 bzero(offp, endp - offp);
2955 /* Base and Len of TX Ring */
2956 E1000_WRITE_REG(hw, E1000_TDLEN(i),
2957 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
2958 E1000_WRITE_REG(hw, E1000_TDBAH(i),
2959 (u32)(bus_addr >> 32));
2960 E1000_WRITE_REG(hw, E1000_TDBAL(i),
2962 /* Init the HEAD/TAIL indices */
2963 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
2964 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
2966 HW_DEBUGOUT2("Base = %x, Length = %x\n",
2967 E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)),
2968 E1000_READ_REG(&adapter->hw, E1000_TDLEN(i)));
2970 txdctl = 0; /* clear txdctl */
2971 txdctl |= 0x1f; /* PTHRESH */
2972 txdctl |= 1 << 8; /* HTHRESH */
2973 txdctl |= 1 << 16;/* WTHRESH */
2974 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
2975 txdctl |= E1000_TXDCTL_GRAN;
2976 txdctl |= 1 << 25; /* LWTHRESH */
2978 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
2981 /* Set the default values for the Tx Inter Packet Gap timer */
2982 switch (adapter->hw.mac.type) {
2983 case e1000_80003es2lan:
2984 tipg = DEFAULT_82543_TIPG_IPGR1;
2985 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2986 E1000_TIPG_IPGR2_SHIFT;
2989 tipg = DEFAULT_82542_TIPG_IPGT;
2990 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2991 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2994 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
2995 (adapter->hw.phy.media_type ==
2996 e1000_media_type_internal_serdes))
2997 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2999 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
3000 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3001 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3004 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
3005 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value);
3007 if(adapter->hw.mac.type >= e1000_82540)
3008 E1000_WRITE_REG(&adapter->hw, E1000_TADV,
3009 adapter->tx_abs_int_delay.value);
3011 if ((adapter->hw.mac.type == e1000_82571) ||
3012 (adapter->hw.mac.type == e1000_82572)) {
3013 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3014 tarc |= TARC_SPEED_MODE_BIT;
3015 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3016 } else if (adapter->hw.mac.type == e1000_80003es2lan) {
3017 /* errata: program both queues to unweighted RR */
3018 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3020 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3021 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
3023 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
3024 } else if (adapter->hw.mac.type == e1000_82574) {
3025 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3026 tarc |= TARC_ERRATA_BIT;
3027 if ( adapter->tx_num_queues > 1) {
3028 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
3029 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3030 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
3032 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3035 if (adapter->tx_int_delay.value > 0)
3036 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3038 /* Program the Transmit Control Register */
3039 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
3040 tctl &= ~E1000_TCTL_CT;
3041 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
3042 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
3044 if (adapter->hw.mac.type >= e1000_82571)
3045 tctl |= E1000_TCTL_MULR;
3047 /* This write will effectively turn on the transmit unit. */
3048 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
3050 /* SPT and KBL errata workarounds */
3051 if (hw->mac.type == e1000_pch_spt) {
3053 reg = E1000_READ_REG(hw, E1000_IOSFPC);
3054 reg |= E1000_RCTL_RDMTS_HEX;
3055 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
3056 /* i218-i219 Specification Update 1.5.4.5 */
3057 reg = E1000_READ_REG(hw, E1000_TARC(0));
3058 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3059 reg |= E1000_TARC0_CB_MULTIQ_2_REQ;
3060 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3064 /*********************************************************************
3066 * Enable receive unit.
3068 **********************************************************************/
3071 em_initialize_receive_unit(if_ctx_t ctx)
3073 struct adapter *adapter = iflib_get_softc(ctx);
3074 if_softc_ctx_t scctx = adapter->shared;
3075 struct ifnet *ifp = iflib_get_ifp(ctx);
3076 struct e1000_hw *hw = &adapter->hw;
3077 struct em_rx_queue *que;
3079 u32 rctl, rxcsum, rfctl;
3081 INIT_DEBUGOUT("em_initialize_receive_units: begin");
3084 * Make sure receives are disabled while setting
3085 * up the descriptor ring
3087 rctl = E1000_READ_REG(hw, E1000_RCTL);
3088 /* Do not disable if ever enabled on this hardware */
3089 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
3090 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3092 /* Setup the Receive Control Register */
3093 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3094 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3095 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3096 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3098 /* Do not store bad packets */
3099 rctl &= ~E1000_RCTL_SBP;
3101 /* Enable Long Packet receive */
3102 if (if_getmtu(ifp) > ETHERMTU)
3103 rctl |= E1000_RCTL_LPE;
3105 rctl &= ~E1000_RCTL_LPE;
3108 if (!em_disable_crc_stripping)
3109 rctl |= E1000_RCTL_SECRC;
3111 if (adapter->hw.mac.type >= e1000_82540) {
3112 E1000_WRITE_REG(&adapter->hw, E1000_RADV,
3113 adapter->rx_abs_int_delay.value);
3116 * Set the interrupt throttling rate. Value is calculated
3117 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
3119 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
3121 E1000_WRITE_REG(&adapter->hw, E1000_RDTR,
3122 adapter->rx_int_delay.value);
3124 /* Use extended rx descriptor formats */
3125 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3126 rfctl |= E1000_RFCTL_EXTEN;
3128 * When using MSIX interrupts we need to throttle
3129 * using the EITR register (82574 only)
3131 if (hw->mac.type == e1000_82574) {
3132 for (int i = 0; i < 4; i++)
3133 E1000_WRITE_REG(hw, E1000_EITR_82574(i),
3135 /* Disable accelerated acknowledge */
3136 rfctl |= E1000_RFCTL_ACK_DIS;
3138 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3140 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
3141 if (if_getcapenable(ifp) & IFCAP_RXCSUM &&
3142 adapter->hw.mac.type >= e1000_82543) {
3143 if (adapter->tx_num_queues > 1) {
3144 if (adapter->hw.mac.type >= igb_mac_min) {
3145 rxcsum |= E1000_RXCSUM_PCSD;
3146 if (hw->mac.type != e1000_82575)
3147 rxcsum |= E1000_RXCSUM_CRCOFL;
3149 rxcsum |= E1000_RXCSUM_TUOFL |
3150 E1000_RXCSUM_IPOFL |
3153 if (adapter->hw.mac.type >= igb_mac_min)
3154 rxcsum |= E1000_RXCSUM_IPPCSE;
3156 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
3157 if (adapter->hw.mac.type > e1000_82575)
3158 rxcsum |= E1000_RXCSUM_CRCOFL;
3161 rxcsum &= ~E1000_RXCSUM_TUOFL;
3163 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
3165 if (adapter->rx_num_queues > 1) {
3166 if (adapter->hw.mac.type >= igb_mac_min)
3167 igb_initialize_rss_mapping(adapter);
3169 em_initialize_rss_mapping(adapter);
3173 * XXX TEMPORARY WORKAROUND: on some systems with 82573
3174 * long latencies are observed, like Lenovo X60. This
3175 * change eliminates the problem, but since having positive
3176 * values in RDTR is a known source of problems on other
3177 * platforms another solution is being sought.
3179 if (hw->mac.type == e1000_82573)
3180 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
3182 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3183 struct rx_ring *rxr = &que->rxr;
3184 /* Setup the Base and Length of the Rx Descriptor Ring */
3185 u64 bus_addr = rxr->rx_paddr;
3187 u32 rdt = adapter->rx_num_queues -1; /* default */
3190 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3191 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
3192 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
3193 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
3194 /* Setup the Head and Tail Descriptor Pointers */
3195 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
3196 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
3200 * Set PTHRESH for improved jumbo performance
3201 * According to 10.2.5.11 of Intel 82574 Datasheet,
3202 * RXDCTL(1) is written whenever RXDCTL(0) is written.
3203 * Only write to RXDCTL(1) if there is a need for different
3207 if (((adapter->hw.mac.type == e1000_ich9lan) ||
3208 (adapter->hw.mac.type == e1000_pch2lan) ||
3209 (adapter->hw.mac.type == e1000_ich10lan)) &&
3210 (if_getmtu(ifp) > ETHERMTU)) {
3211 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
3212 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
3213 } else if (adapter->hw.mac.type == e1000_82574) {
3214 for (int i = 0; i < adapter->rx_num_queues; i++) {
3215 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3216 rxdctl |= 0x20; /* PTHRESH */
3217 rxdctl |= 4 << 8; /* HTHRESH */
3218 rxdctl |= 4 << 16;/* WTHRESH */
3219 rxdctl |= 1 << 24; /* Switch to granularity */
3220 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3222 } else if (adapter->hw.mac.type >= igb_mac_min) {
3223 u32 psize, srrctl = 0;
3225 if (if_getmtu(ifp) > ETHERMTU) {
3226 /* Set maximum packet len */
3227 if (adapter->rx_mbuf_sz <= 4096) {
3228 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3229 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3230 } else if (adapter->rx_mbuf_sz > 4096) {
3231 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3232 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3234 psize = scctx->isc_max_frame_size;
3235 /* are we on a vlan? */
3236 if (ifp->if_vlantrunk != NULL)
3237 psize += VLAN_TAG_SIZE;
3238 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
3240 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3241 rctl |= E1000_RCTL_SZ_2048;
3245 * If TX flow control is disabled and there's >1 queue defined,
3248 * This drops frames rather than hanging the RX MAC for all queues.
3250 if ((adapter->rx_num_queues > 1) &&
3251 (adapter->fc == e1000_fc_none ||
3252 adapter->fc == e1000_fc_rx_pause)) {
3253 srrctl |= E1000_SRRCTL_DROP_EN;
3255 /* Setup the Base and Length of the Rx Descriptor Rings */
3256 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3257 struct rx_ring *rxr = &que->rxr;
3258 u64 bus_addr = rxr->rx_paddr;
3262 /* Configure for header split? -- ignore for now */
3263 rxr->hdr_split = igb_header_split;
3265 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3268 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3269 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3270 E1000_WRITE_REG(hw, E1000_RDBAH(i),
3271 (uint32_t)(bus_addr >> 32));
3272 E1000_WRITE_REG(hw, E1000_RDBAL(i),
3273 (uint32_t)bus_addr);
3274 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3275 /* Enable this Queue */
3276 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3277 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3278 rxdctl &= 0xFFF00000;
3279 rxdctl |= IGB_RX_PTHRESH;
3280 rxdctl |= IGB_RX_HTHRESH << 8;
3281 rxdctl |= IGB_RX_WTHRESH << 16;
3282 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3284 } else if (adapter->hw.mac.type >= e1000_pch2lan) {
3285 if (if_getmtu(ifp) > ETHERMTU)
3286 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
3288 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
3291 /* Make sure VLAN Filters are off */
3292 rctl &= ~E1000_RCTL_VFE;
3294 if (adapter->hw.mac.type < igb_mac_min) {
3295 if (adapter->rx_mbuf_sz == MCLBYTES)
3296 rctl |= E1000_RCTL_SZ_2048;
3297 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE)
3298 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3299 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE)
3300 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3302 /* ensure we clear use DTYPE of 00 here */
3303 rctl &= ~0x00000C00;
3306 /* Write out the settings */
3307 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3313 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3315 struct adapter *adapter = iflib_get_softc(ctx);
3318 index = (vtag >> 5) & 0x7F;
3320 adapter->shadow_vfta[index] |= (1 << bit);
3321 ++adapter->num_vlans;
3325 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3327 struct adapter *adapter = iflib_get_softc(ctx);
3330 index = (vtag >> 5) & 0x7F;
3332 adapter->shadow_vfta[index] &= ~(1 << bit);
3333 --adapter->num_vlans;
3337 em_setup_vlan_hw_support(struct adapter *adapter)
3339 struct e1000_hw *hw = &adapter->hw;
3343 * We get here thru init_locked, meaning
3344 * a soft reset, this has already cleared
3345 * the VFTA and other state, so if there
3346 * have been no vlan's registered do nothing.
3348 if (adapter->num_vlans == 0)
3352 * A soft reset zero's out the VFTA, so
3353 * we need to repopulate it now.
3355 for (int i = 0; i < EM_VFTA_SIZE; i++)
3356 if (adapter->shadow_vfta[i] != 0)
3357 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
3358 i, adapter->shadow_vfta[i]);
3360 reg = E1000_READ_REG(hw, E1000_CTRL);
3361 reg |= E1000_CTRL_VME;
3362 E1000_WRITE_REG(hw, E1000_CTRL, reg);
3364 /* Enable the Filter Table */
3365 reg = E1000_READ_REG(hw, E1000_RCTL);
3366 reg &= ~E1000_RCTL_CFIEN;
3367 reg |= E1000_RCTL_VFE;
3368 E1000_WRITE_REG(hw, E1000_RCTL, reg);
3372 em_if_enable_intr(if_ctx_t ctx)
3374 struct adapter *adapter = iflib_get_softc(ctx);
3375 struct e1000_hw *hw = &adapter->hw;
3376 u32 ims_mask = IMS_ENABLE_MASK;
3378 if (hw->mac.type == e1000_82574) {
3379 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK);
3380 ims_mask |= adapter->ims;
3381 } else if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min) {
3382 u32 mask = (adapter->que_mask | adapter->link_mask);
3384 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask);
3385 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask);
3386 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask);
3387 ims_mask = E1000_IMS_LSC;
3390 E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3394 em_if_disable_intr(if_ctx_t ctx)
3396 struct adapter *adapter = iflib_get_softc(ctx);
3397 struct e1000_hw *hw = &adapter->hw;
3399 if (adapter->intr_type == IFLIB_INTR_MSIX) {
3400 if (hw->mac.type >= igb_mac_min)
3401 E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0);
3402 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0);
3404 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
3408 * Bit of a misnomer, what this really means is
3409 * to enable OS management of the system... aka
3410 * to disable special hardware management features
3413 em_init_manageability(struct adapter *adapter)
3415 /* A shared code workaround */
3416 #define E1000_82542_MANC2H E1000_MANC2H
3417 if (adapter->has_manage) {
3418 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3419 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3421 /* disable hardware interception of ARP */
3422 manc &= ~(E1000_MANC_ARP_EN);
3424 /* enable receiving management packets to the host */
3425 manc |= E1000_MANC_EN_MNG2HOST;
3426 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3427 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3428 manc2h |= E1000_MNG2HOST_PORT_623;
3429 manc2h |= E1000_MNG2HOST_PORT_664;
3430 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3431 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3436 * Give control back to hardware management
3437 * controller if there is one.
3440 em_release_manageability(struct adapter *adapter)
3442 if (adapter->has_manage) {
3443 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3445 /* re-enable hardware interception of ARP */
3446 manc |= E1000_MANC_ARP_EN;
3447 manc &= ~E1000_MANC_EN_MNG2HOST;
3449 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3454 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3455 * For ASF and Pass Through versions of f/w this means
3456 * that the driver is loaded. For AMT version type f/w
3457 * this means that the network i/f is open.
3460 em_get_hw_control(struct adapter *adapter)
3464 if (adapter->vf_ifp)
3467 if (adapter->hw.mac.type == e1000_82573) {
3468 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3469 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3470 swsm | E1000_SWSM_DRV_LOAD);
3474 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3475 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3476 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3480 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3481 * For ASF and Pass Through versions of f/w this means that
3482 * the driver is no longer loaded. For AMT versions of the
3483 * f/w this means that the network i/f is closed.
3486 em_release_hw_control(struct adapter *adapter)
3490 if (!adapter->has_manage)
3493 if (adapter->hw.mac.type == e1000_82573) {
3494 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3495 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3496 swsm & ~E1000_SWSM_DRV_LOAD);
3500 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3501 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3502 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3507 em_is_valid_ether_addr(u8 *addr)
3509 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3511 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3519 ** Parse the interface capabilities with regard
3520 ** to both system management and wake-on-lan for
3524 em_get_wakeup(if_ctx_t ctx)
3526 struct adapter *adapter = iflib_get_softc(ctx);
3527 device_t dev = iflib_get_dev(ctx);
3528 u16 eeprom_data = 0, device_id, apme_mask;
3530 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
3531 apme_mask = EM_EEPROM_APME;
3533 switch (adapter->hw.mac.type) {
3538 e1000_read_nvm(&adapter->hw,
3539 NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3540 apme_mask = EM_82544_APME;
3543 case e1000_82546_rev_3:
3544 if (adapter->hw.bus.func == 1) {
3545 e1000_read_nvm(&adapter->hw,
3546 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3549 e1000_read_nvm(&adapter->hw,
3550 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3554 adapter->has_amt = TRUE;
3558 case e1000_80003es2lan:
3559 if (adapter->hw.bus.func == 1) {
3560 e1000_read_nvm(&adapter->hw,
3561 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3564 e1000_read_nvm(&adapter->hw,
3565 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3569 case e1000_ich10lan:
3574 case e1000_82575: /* listing all igb devices */
3582 case e1000_vfadapt_i350:
3583 apme_mask = E1000_WUC_APME;
3584 adapter->has_amt = TRUE;
3585 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
3588 e1000_read_nvm(&adapter->hw,
3589 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3592 if (eeprom_data & apme_mask)
3593 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
3595 * We have the eeprom settings, now apply the special cases
3596 * where the eeprom may be wrong or the board won't support
3597 * wake on lan on a particular port
3599 device_id = pci_get_device(dev);
3600 switch (device_id) {
3601 case E1000_DEV_ID_82546GB_PCIE:
3604 case E1000_DEV_ID_82546EB_FIBER:
3605 case E1000_DEV_ID_82546GB_FIBER:
3606 /* Wake events only supported on port A for dual fiber
3607 * regardless of eeprom setting */
3608 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3609 E1000_STATUS_FUNC_1)
3612 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
3613 /* if quad port adapter, disable WoL on all but port A */
3614 if (global_quad_port_a != 0)
3616 /* Reset for multiple quad port adapters */
3617 if (++global_quad_port_a == 4)
3618 global_quad_port_a = 0;
3620 case E1000_DEV_ID_82571EB_FIBER:
3621 /* Wake events only supported on port A for dual fiber
3622 * regardless of eeprom setting */
3623 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3624 E1000_STATUS_FUNC_1)
3627 case E1000_DEV_ID_82571EB_QUAD_COPPER:
3628 case E1000_DEV_ID_82571EB_QUAD_FIBER:
3629 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
3630 /* if quad port adapter, disable WoL on all but port A */
3631 if (global_quad_port_a != 0)
3633 /* Reset for multiple quad port adapters */
3634 if (++global_quad_port_a == 4)
3635 global_quad_port_a = 0;
3643 * Enable PCI Wake On Lan capability
3646 em_enable_wakeup(if_ctx_t ctx)
3648 struct adapter *adapter = iflib_get_softc(ctx);
3649 device_t dev = iflib_get_dev(ctx);
3650 if_t ifp = iflib_get_ifp(ctx);
3652 u32 pmc, ctrl, ctrl_ext, rctl;
3655 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
3659 * Determine type of Wakeup: note that wol
3660 * is set with all bits on by default.
3662 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
3663 adapter->wol &= ~E1000_WUFC_MAG;
3665 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
3666 adapter->wol &= ~E1000_WUFC_EX;
3668 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
3669 adapter->wol &= ~E1000_WUFC_MC;
3671 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3672 rctl |= E1000_RCTL_MPE;
3673 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3676 if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC)))
3679 /* Advertise the wakeup capability */
3680 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
3681 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
3682 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
3684 /* Keep the laser running on Fiber adapters */
3685 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3686 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
3687 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3688 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
3689 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext);
3692 if ((adapter->hw.mac.type == e1000_ich8lan) ||
3693 (adapter->hw.mac.type == e1000_pchlan) ||
3694 (adapter->hw.mac.type == e1000_ich9lan) ||
3695 (adapter->hw.mac.type == e1000_ich10lan))
3696 e1000_suspend_workarounds_ich8lan(&adapter->hw);
3698 if ( adapter->hw.mac.type >= e1000_pchlan) {
3699 error = em_enable_phy_wakeup(adapter);
3703 /* Enable wakeup by the MAC */
3704 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
3705 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
3708 if (adapter->hw.phy.type == e1000_phy_igp_3)
3709 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
3712 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
3713 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3714 if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
3715 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3716 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
3722 * WOL in the newer chipset interfaces (pchlan)
3723 * require thing to be copied into the phy
3726 em_enable_phy_wakeup(struct adapter *adapter)
3728 struct e1000_hw *hw = &adapter->hw;
3732 /* copy MAC RARs to PHY RARs */
3733 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
3735 /* copy MAC MTA to PHY MTA */
3736 for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
3737 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
3738 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
3739 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
3740 (u16)((mreg >> 16) & 0xFFFF));
3743 /* configure PHY Rx Control register */
3744 e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg);
3745 mreg = E1000_READ_REG(hw, E1000_RCTL);
3746 if (mreg & E1000_RCTL_UPE)
3747 preg |= BM_RCTL_UPE;
3748 if (mreg & E1000_RCTL_MPE)
3749 preg |= BM_RCTL_MPE;
3750 preg &= ~(BM_RCTL_MO_MASK);
3751 if (mreg & E1000_RCTL_MO_3)
3752 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
3753 << BM_RCTL_MO_SHIFT);
3754 if (mreg & E1000_RCTL_BAM)
3755 preg |= BM_RCTL_BAM;
3756 if (mreg & E1000_RCTL_PMCF)
3757 preg |= BM_RCTL_PMCF;
3758 mreg = E1000_READ_REG(hw, E1000_CTRL);
3759 if (mreg & E1000_CTRL_RFCE)
3760 preg |= BM_RCTL_RFCE;
3761 e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg);
3763 /* enable PHY wakeup in MAC register */
3764 E1000_WRITE_REG(hw, E1000_WUC,
3765 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
3766 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol);
3768 /* configure and enable PHY wakeup in PHY registers */
3769 e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol);
3770 e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
3772 /* activate PHY wakeup */
3773 ret = hw->phy.ops.acquire(hw);
3775 printf("Could not acquire PHY\n");
3778 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3779 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3780 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
3782 printf("Could not read PHY page 769\n");
3785 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
3786 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
3788 printf("Could not set PHY Host Wakeup bit\n");
3790 hw->phy.ops.release(hw);
3796 em_if_led_func(if_ctx_t ctx, int onoff)
3798 struct adapter *adapter = iflib_get_softc(ctx);
3801 e1000_setup_led(&adapter->hw);
3802 e1000_led_on(&adapter->hw);
3804 e1000_led_off(&adapter->hw);
3805 e1000_cleanup_led(&adapter->hw);
3810 * Disable the L0S and L1 LINK states
3813 em_disable_aspm(struct adapter *adapter)
3816 u16 link_cap,link_ctrl;
3817 device_t dev = adapter->dev;
3819 switch (adapter->hw.mac.type) {
3827 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
3829 reg = base + PCIER_LINK_CAP;
3830 link_cap = pci_read_config(dev, reg, 2);
3831 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
3833 reg = base + PCIER_LINK_CTL;
3834 link_ctrl = pci_read_config(dev, reg, 2);
3835 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
3836 pci_write_config(dev, reg, link_ctrl, 2);
3840 /**********************************************************************
3842 * Update the board statistics counters.
3844 **********************************************************************/
3846 em_update_stats_counters(struct adapter *adapter)
3849 if(adapter->hw.phy.media_type == e1000_media_type_copper ||
3850 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3851 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
3852 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
3854 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
3855 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
3856 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
3857 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
3859 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
3860 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
3861 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
3862 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
3863 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
3864 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
3865 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
3866 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
3868 ** For watchdog management we need to know if we have been
3869 ** paused during the last interval, so capture that here.
3871 adapter->shared->isc_pause_frames = adapter->stats.xoffrxc;
3872 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
3873 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
3874 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
3875 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
3876 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
3877 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
3878 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
3879 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
3880 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
3881 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
3882 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
3883 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
3885 /* For the 64-bit byte counters the low dword must be read first. */
3886 /* Both registers clear on the read of the high dword */
3888 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) +
3889 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32);
3890 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) +
3891 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32);
3893 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
3894 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
3895 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
3896 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
3897 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
3899 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
3900 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
3902 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
3903 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
3904 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
3905 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
3906 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
3907 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
3908 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
3909 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
3910 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
3911 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
3913 /* Interrupt Counts */
3915 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC);
3916 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC);
3917 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC);
3918 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC);
3919 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC);
3920 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC);
3921 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC);
3922 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC);
3923 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC);
3925 if (adapter->hw.mac.type >= e1000_82543) {
3926 adapter->stats.algnerrc +=
3927 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
3928 adapter->stats.rxerrc +=
3929 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
3930 adapter->stats.tncrs +=
3931 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
3932 adapter->stats.cexterr +=
3933 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
3934 adapter->stats.tsctc +=
3935 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
3936 adapter->stats.tsctfc +=
3937 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
3942 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
3944 struct adapter *adapter = iflib_get_softc(ctx);
3945 struct ifnet *ifp = iflib_get_ifp(ctx);
3948 case IFCOUNTER_COLLISIONS:
3949 return (adapter->stats.colc);
3950 case IFCOUNTER_IERRORS:
3951 return (adapter->dropped_pkts + adapter->stats.rxerrc +
3952 adapter->stats.crcerrs + adapter->stats.algnerrc +
3953 adapter->stats.ruc + adapter->stats.roc +
3954 adapter->stats.mpc + adapter->stats.cexterr);
3955 case IFCOUNTER_OERRORS:
3956 return (adapter->stats.ecol + adapter->stats.latecol +
3957 adapter->watchdog_events);
3959 return (if_get_counter_default(ifp, cnt));
3963 /* Export a single 32-bit register via a read-only sysctl. */
3965 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
3967 struct adapter *adapter;
3970 adapter = oidp->oid_arg1;
3971 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2);
3972 return (sysctl_handle_int(oidp, &val, 0, req));
3976 * Add sysctl variables, one per statistic, to the system.
3979 em_add_hw_stats(struct adapter *adapter)
3981 device_t dev = iflib_get_dev(adapter->ctx);
3982 struct em_tx_queue *tx_que = adapter->tx_queues;
3983 struct em_rx_queue *rx_que = adapter->rx_queues;
3985 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
3986 struct sysctl_oid *tree = device_get_sysctl_tree(dev);
3987 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
3988 struct e1000_hw_stats *stats = &adapter->stats;
3990 struct sysctl_oid *stat_node, *queue_node, *int_node;
3991 struct sysctl_oid_list *stat_list, *queue_list, *int_list;
3993 #define QUEUE_NAME_LEN 32
3994 char namebuf[QUEUE_NAME_LEN];
3996 /* Driver Statistics */
3997 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
3998 CTLFLAG_RD, &adapter->dropped_pkts,
3999 "Driver dropped packets");
4000 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
4001 CTLFLAG_RD, &adapter->link_irq,
4002 "Link MSIX IRQ Handled");
4003 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "mbuf_defrag_fail",
4004 CTLFLAG_RD, &adapter->mbuf_defrag_failed,
4005 "Defragmenting mbuf chain failed");
4006 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "tx_dma_fail",
4007 CTLFLAG_RD, &adapter->no_tx_dma_setup,
4008 "Driver tx dma failure in xmit");
4009 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
4010 CTLFLAG_RD, &adapter->rx_overruns,
4012 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
4013 CTLFLAG_RD, &adapter->watchdog_events,
4014 "Watchdog timeouts");
4015 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
4016 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL,
4017 em_sysctl_reg_handler, "IU",
4018 "Device Control Register");
4019 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
4020 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL,
4021 em_sysctl_reg_handler, "IU",
4022 "Receiver Control Register");
4023 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
4024 CTLFLAG_RD, &adapter->hw.fc.high_water, 0,
4025 "Flow Control High Watermark");
4026 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
4027 CTLFLAG_RD, &adapter->hw.fc.low_water, 0,
4028 "Flow Control Low Watermark");
4030 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
4031 struct tx_ring *txr = &tx_que->txr;
4032 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
4033 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4034 CTLFLAG_RD, NULL, "TX Queue Name");
4035 queue_list = SYSCTL_CHILDREN(queue_node);
4037 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
4038 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4040 em_sysctl_reg_handler, "IU",
4041 "Transmit Descriptor Head");
4042 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
4043 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4045 em_sysctl_reg_handler, "IU",
4046 "Transmit Descriptor Tail");
4047 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
4048 CTLFLAG_RD, &txr->tx_irq,
4049 "Queue MSI-X Transmit Interrupts");
4052 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) {
4053 struct rx_ring *rxr = &rx_que->rxr;
4054 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
4055 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4056 CTLFLAG_RD, NULL, "RX Queue Name");
4057 queue_list = SYSCTL_CHILDREN(queue_node);
4059 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
4060 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4062 em_sysctl_reg_handler, "IU",
4063 "Receive Descriptor Head");
4064 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
4065 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4067 em_sysctl_reg_handler, "IU",
4068 "Receive Descriptor Tail");
4069 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
4070 CTLFLAG_RD, &rxr->rx_irq,
4071 "Queue MSI-X Receive Interrupts");
4074 /* MAC stats get their own sub node */
4076 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
4077 CTLFLAG_RD, NULL, "Statistics");
4078 stat_list = SYSCTL_CHILDREN(stat_node);
4080 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
4081 CTLFLAG_RD, &stats->ecol,
4082 "Excessive collisions");
4083 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
4084 CTLFLAG_RD, &stats->scc,
4085 "Single collisions");
4086 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
4087 CTLFLAG_RD, &stats->mcc,
4088 "Multiple collisions");
4089 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
4090 CTLFLAG_RD, &stats->latecol,
4092 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
4093 CTLFLAG_RD, &stats->colc,
4095 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
4096 CTLFLAG_RD, &adapter->stats.symerrs,
4098 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
4099 CTLFLAG_RD, &adapter->stats.sec,
4101 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
4102 CTLFLAG_RD, &adapter->stats.dc,
4104 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
4105 CTLFLAG_RD, &adapter->stats.mpc,
4107 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
4108 CTLFLAG_RD, &adapter->stats.rnbc,
4109 "Receive No Buffers");
4110 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
4111 CTLFLAG_RD, &adapter->stats.ruc,
4112 "Receive Undersize");
4113 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
4114 CTLFLAG_RD, &adapter->stats.rfc,
4115 "Fragmented Packets Received ");
4116 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
4117 CTLFLAG_RD, &adapter->stats.roc,
4118 "Oversized Packets Received");
4119 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
4120 CTLFLAG_RD, &adapter->stats.rjc,
4122 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
4123 CTLFLAG_RD, &adapter->stats.rxerrc,
4125 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
4126 CTLFLAG_RD, &adapter->stats.crcerrs,
4128 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
4129 CTLFLAG_RD, &adapter->stats.algnerrc,
4130 "Alignment Errors");
4131 /* On 82575 these are collision counts */
4132 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
4133 CTLFLAG_RD, &adapter->stats.cexterr,
4134 "Collision/Carrier extension errors");
4135 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
4136 CTLFLAG_RD, &adapter->stats.xonrxc,
4138 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
4139 CTLFLAG_RD, &adapter->stats.xontxc,
4141 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
4142 CTLFLAG_RD, &adapter->stats.xoffrxc,
4144 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
4145 CTLFLAG_RD, &adapter->stats.xofftxc,
4146 "XOFF Transmitted");
4148 /* Packet Reception Stats */
4149 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
4150 CTLFLAG_RD, &adapter->stats.tpr,
4151 "Total Packets Received ");
4152 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
4153 CTLFLAG_RD, &adapter->stats.gprc,
4154 "Good Packets Received");
4155 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
4156 CTLFLAG_RD, &adapter->stats.bprc,
4157 "Broadcast Packets Received");
4158 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
4159 CTLFLAG_RD, &adapter->stats.mprc,
4160 "Multicast Packets Received");
4161 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
4162 CTLFLAG_RD, &adapter->stats.prc64,
4163 "64 byte frames received ");
4164 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
4165 CTLFLAG_RD, &adapter->stats.prc127,
4166 "65-127 byte frames received");
4167 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
4168 CTLFLAG_RD, &adapter->stats.prc255,
4169 "128-255 byte frames received");
4170 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
4171 CTLFLAG_RD, &adapter->stats.prc511,
4172 "256-511 byte frames received");
4173 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
4174 CTLFLAG_RD, &adapter->stats.prc1023,
4175 "512-1023 byte frames received");
4176 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
4177 CTLFLAG_RD, &adapter->stats.prc1522,
4178 "1023-1522 byte frames received");
4179 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
4180 CTLFLAG_RD, &adapter->stats.gorc,
4181 "Good Octets Received");
4183 /* Packet Transmission Stats */
4184 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
4185 CTLFLAG_RD, &adapter->stats.gotc,
4186 "Good Octets Transmitted");
4187 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
4188 CTLFLAG_RD, &adapter->stats.tpt,
4189 "Total Packets Transmitted");
4190 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
4191 CTLFLAG_RD, &adapter->stats.gptc,
4192 "Good Packets Transmitted");
4193 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
4194 CTLFLAG_RD, &adapter->stats.bptc,
4195 "Broadcast Packets Transmitted");
4196 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
4197 CTLFLAG_RD, &adapter->stats.mptc,
4198 "Multicast Packets Transmitted");
4199 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
4200 CTLFLAG_RD, &adapter->stats.ptc64,
4201 "64 byte frames transmitted ");
4202 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
4203 CTLFLAG_RD, &adapter->stats.ptc127,
4204 "65-127 byte frames transmitted");
4205 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
4206 CTLFLAG_RD, &adapter->stats.ptc255,
4207 "128-255 byte frames transmitted");
4208 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
4209 CTLFLAG_RD, &adapter->stats.ptc511,
4210 "256-511 byte frames transmitted");
4211 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
4212 CTLFLAG_RD, &adapter->stats.ptc1023,
4213 "512-1023 byte frames transmitted");
4214 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
4215 CTLFLAG_RD, &adapter->stats.ptc1522,
4216 "1024-1522 byte frames transmitted");
4217 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
4218 CTLFLAG_RD, &adapter->stats.tsctc,
4219 "TSO Contexts Transmitted");
4220 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
4221 CTLFLAG_RD, &adapter->stats.tsctfc,
4222 "TSO Contexts Failed");
4225 /* Interrupt Stats */
4227 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
4228 CTLFLAG_RD, NULL, "Interrupt Statistics");
4229 int_list = SYSCTL_CHILDREN(int_node);
4231 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
4232 CTLFLAG_RD, &adapter->stats.iac,
4233 "Interrupt Assertion Count");
4235 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
4236 CTLFLAG_RD, &adapter->stats.icrxptc,
4237 "Interrupt Cause Rx Pkt Timer Expire Count");
4239 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
4240 CTLFLAG_RD, &adapter->stats.icrxatc,
4241 "Interrupt Cause Rx Abs Timer Expire Count");
4243 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
4244 CTLFLAG_RD, &adapter->stats.ictxptc,
4245 "Interrupt Cause Tx Pkt Timer Expire Count");
4247 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
4248 CTLFLAG_RD, &adapter->stats.ictxatc,
4249 "Interrupt Cause Tx Abs Timer Expire Count");
4251 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
4252 CTLFLAG_RD, &adapter->stats.ictxqec,
4253 "Interrupt Cause Tx Queue Empty Count");
4255 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
4256 CTLFLAG_RD, &adapter->stats.ictxqmtc,
4257 "Interrupt Cause Tx Queue Min Thresh Count");
4259 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
4260 CTLFLAG_RD, &adapter->stats.icrxdmtc,
4261 "Interrupt Cause Rx Desc Min Thresh Count");
4263 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
4264 CTLFLAG_RD, &adapter->stats.icrxoc,
4265 "Interrupt Cause Receiver Overrun Count");
4268 /**********************************************************************
4270 * This routine provides a way to dump out the adapter eeprom,
4271 * often a useful debug/service tool. This only dumps the first
4272 * 32 words, stuff that matters is in that extent.
4274 **********************************************************************/
4276 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4278 struct adapter *adapter = (struct adapter *)arg1;
4283 error = sysctl_handle_int(oidp, &result, 0, req);
4285 if (error || !req->newptr)
4289 * This value will cause a hex dump of the
4290 * first 32 16-bit words of the EEPROM to
4294 em_print_nvm_info(adapter);
4300 em_print_nvm_info(struct adapter *adapter)
4305 /* Its a bit crude, but it gets the job done */
4306 printf("\nInterface EEPROM Dump:\n");
4307 printf("Offset\n0x0000 ");
4308 for (i = 0, j = 0; i < 32; i++, j++) {
4309 if (j == 8) { /* Make the offset block */
4311 printf("\n0x00%x0 ",row);
4313 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
4314 printf("%04x ", eeprom_data);
4320 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4322 struct em_int_delay_info *info;
4323 struct adapter *adapter;
4325 int error, usecs, ticks;
4327 info = (struct em_int_delay_info *) arg1;
4328 usecs = info->value;
4329 error = sysctl_handle_int(oidp, &usecs, 0, req);
4330 if (error != 0 || req->newptr == NULL)
4332 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4334 info->value = usecs;
4335 ticks = EM_USECS_TO_TICKS(usecs);
4336 if (info->offset == E1000_ITR) /* units are 256ns here */
4339 adapter = info->adapter;
4341 regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
4342 regval = (regval & ~0xffff) | (ticks & 0xffff);
4343 /* Handle a few special cases. */
4344 switch (info->offset) {
4349 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
4350 /* Don't write 0 into the TIDV register. */
4353 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
4356 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
4361 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
4362 const char *description, struct em_int_delay_info *info,
4363 int offset, int value)
4365 info->adapter = adapter;
4366 info->offset = offset;
4367 info->value = value;
4368 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev),
4369 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4370 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
4371 info, 0, em_sysctl_int_delay, "I", description);
4375 * Set flow control using sysctl:
4376 * Flow control values:
4383 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4386 static int input = 3; /* default is full */
4387 struct adapter *adapter = (struct adapter *) arg1;
4389 error = sysctl_handle_int(oidp, &input, 0, req);
4391 if ((error) || (req->newptr == NULL))
4394 if (input == adapter->fc) /* no change? */
4398 case e1000_fc_rx_pause:
4399 case e1000_fc_tx_pause:
4402 adapter->hw.fc.requested_mode = input;
4403 adapter->fc = input;
4410 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
4411 e1000_force_mac_fc(&adapter->hw);
4416 * Manage Energy Efficient Ethernet:
4418 * 0/1 - enabled/disabled
4421 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4423 struct adapter *adapter = (struct adapter *) arg1;
4426 value = adapter->hw.dev_spec.ich8lan.eee_disable;
4427 error = sysctl_handle_int(oidp, &value, 0, req);
4428 if (error || req->newptr == NULL)
4430 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4431 em_if_init(adapter->ctx);
4437 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4439 struct adapter *adapter;
4444 error = sysctl_handle_int(oidp, &result, 0, req);
4446 if (error || !req->newptr)
4450 adapter = (struct adapter *) arg1;
4451 em_print_debug_info(adapter);
4458 em_get_rs(SYSCTL_HANDLER_ARGS)
4460 struct adapter *adapter = (struct adapter *) arg1;
4465 error = sysctl_handle_int(oidp, &result, 0, req);
4467 if (error || !req->newptr || result != 1)
4469 em_dump_rs(adapter);
4475 em_if_debug(if_ctx_t ctx)
4477 em_dump_rs(iflib_get_softc(ctx));
4481 * This routine is meant to be fluid, add whatever is
4482 * needed for debugging a problem. -jfv
4485 em_print_debug_info(struct adapter *adapter)
4487 device_t dev = iflib_get_dev(adapter->ctx);
4488 struct ifnet *ifp = iflib_get_ifp(adapter->ctx);
4489 struct tx_ring *txr = &adapter->tx_queues->txr;
4490 struct rx_ring *rxr = &adapter->rx_queues->rxr;
4492 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
4493 printf("Interface is RUNNING ");
4495 printf("Interface is NOT RUNNING\n");
4497 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
4498 printf("and INACTIVE\n");
4500 printf("and ACTIVE\n");
4502 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
4503 device_printf(dev, "TX Queue %d ------\n", i);
4504 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
4505 E1000_READ_REG(&adapter->hw, E1000_TDH(i)),
4506 E1000_READ_REG(&adapter->hw, E1000_TDT(i)));
4509 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) {
4510 device_printf(dev, "RX Queue %d ------\n", j);
4511 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
4512 E1000_READ_REG(&adapter->hw, E1000_RDH(j)),
4513 E1000_READ_REG(&adapter->hw, E1000_RDT(j)));
4519 * Write a new value to the EEPROM increasing the number of MSIX
4520 * vectors from 3 to 5, for proper multiqueue support.
4523 em_enable_vectors_82574(if_ctx_t ctx)
4525 struct adapter *adapter = iflib_get_softc(ctx);
4526 struct e1000_hw *hw = &adapter->hw;
4527 device_t dev = iflib_get_dev(ctx);
4530 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4531 printf("Current cap: %#06x\n", edata);
4532 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
4533 device_printf(dev, "Writing to eeprom: increasing "
4534 "reported MSIX vectors from 3 to 5...\n");
4535 edata &= ~(EM_NVM_MSIX_N_MASK);
4536 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
4537 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4538 e1000_update_nvm_checksum(hw);
4539 device_printf(dev, "Writing to eeprom: done\n");