sys/dev/e1000/if_em.c

   1 /*-
   2  * Copyright (c) 2016 Matt Macy <mmacy@nextbsd.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 /* $FreeBSD$ */
  28 #include "if_em.h"
  29 #include <sys/sbuf.h>
  30 #include <machine/_inttypes.h>
  31
  32 #define em_mac_min e1000_82547
  33 #define igb_mac_min e1000_82575
  34
  35 /*********************************************************************
  36  *  Driver version:
  37  *********************************************************************/
  38 char em_driver_version[] = "7.6.1-k";
  39
  40 /*********************************************************************
  41  *  PCI Device ID Table
  42  *
  43  *  Used by probe to select devices to load on
  44  *  Last field stores an index into e1000_strings
  45  *  Last entry must be all 0s
  46  *
  47  *  { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
  48  *********************************************************************/
  49
  50 static pci_vendor_info_t em_vendor_info_array[] =
  51 {
  52         /* Intel(R) PRO/1000 Network Connection - Legacy em*/
  53         PVID(0x8086, E1000_DEV_ID_82540EM,  "Intel(R) PRO/1000 Network Connection"),
  54         PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"),
  55         PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"),
  56         PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"),
  57         PVID(0x8086, E1000_DEV_ID_82540EP_LP,  "Intel(R) PRO/1000 Network Connection"),
  58
  59         PVID(0x8086, E1000_DEV_ID_82541EI,  "Intel(R) PRO/1000 Network Connection"),
  60         PVID(0x8086, E1000_DEV_ID_82541ER,  "Intel(R) PRO/1000 Network Connection"),
  61         PVID(0x8086, E1000_DEV_ID_82541ER_LOM,  "Intel(R) PRO/1000 Network Connection"),
  62         PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE,   "Intel(R) PRO/1000 Network Connection"),
  63         PVID(0x8086, E1000_DEV_ID_82541GI,   "Intel(R) PRO/1000 Network Connection"),
  64         PVID(0x8086, E1000_DEV_ID_82541GI_LF,   "Intel(R) PRO/1000 Network Connection"),
  65         PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE,  "Intel(R) PRO/1000 Network Connection"),
  66
  67         PVID(0x8086, E1000_DEV_ID_82542,  "Intel(R) PRO/1000 Network Connection"),
  68
  69         PVID(0x8086, E1000_DEV_ID_82543GC_FIBER,  "Intel(R) PRO/1000 Network Connection"),
  70         PVID(0x8086, E1000_DEV_ID_82543GC_COPPER,  "Intel(R) PRO/1000 Network Connection"),
  71
  72         PVID(0x8086, E1000_DEV_ID_82544EI_COPPER,  "Intel(R) PRO/1000 Network Connection"),
  73         PVID(0x8086, E1000_DEV_ID_82544EI_FIBER,  "Intel(R) PRO/1000 Network Connection"),
  74         PVID(0x8086, E1000_DEV_ID_82544GC_COPPER,  "Intel(R) PRO/1000 Network Connection"),
  75         PVID(0x8086, E1000_DEV_ID_82544GC_LOM,  "Intel(R) PRO/1000 Network Connection"),
  76
  77         PVID(0x8086, E1000_DEV_ID_82545EM_COPPER,  "Intel(R) PRO/1000 Network Connection"),
  78         PVID(0x8086, E1000_DEV_ID_82545EM_FIBER,  "Intel(R) PRO/1000 Network Connection"),
  79         PVID(0x8086, E1000_DEV_ID_82545GM_COPPER,  "Intel(R) PRO/1000 Network Connection"),
  80         PVID(0x8086, E1000_DEV_ID_82545GM_FIBER,  "Intel(R) PRO/1000 Network Connection"),
  81         PVID(0x8086, E1000_DEV_ID_82545GM_SERDES,  "Intel(R) PRO/1000 Network Connection"),
  82
  83         PVID(0x8086, E1000_DEV_ID_82546EB_COPPER,  "Intel(R) PRO/1000 Network Connection"),
  84         PVID(0x8086, E1000_DEV_ID_82546EB_FIBER,  "Intel(R) PRO/1000 Network Connection"),
  85         PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER,  "Intel(R) PRO/1000 Network Connection"),
  86         PVID(0x8086, E1000_DEV_ID_82546GB_COPPER,  "Intel(R) PRO/1000 Network Connection"),
  87         PVID(0x8086, E1000_DEV_ID_82546GB_FIBER,  "Intel(R) PRO/1000 Network Connection"),
  88         PVID(0x8086, E1000_DEV_ID_82546GB_SERDES,  "Intel(R) PRO/1000 Network Connection"),
  89         PVID(0x8086, E1000_DEV_ID_82546GB_PCIE,  "Intel(R) PRO/1000 Network Connection"),
  90         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER,  "Intel(R) PRO/1000 Network Connection"),
  91         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3,  "Intel(R) PRO/1000 Network Connection"),
  92
  93         PVID(0x8086, E1000_DEV_ID_82547EI,  "Intel(R) PRO/1000 Network Connection"),
  94         PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE,  "Intel(R) PRO/1000 Network Connection"),
  95         PVID(0x8086, E1000_DEV_ID_82547GI,  "Intel(R) PRO/1000 Network Connection"),
  96
  97         /* Intel(R) PRO/1000 Network Connection - em */
  98         PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  99         PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
 100         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"),
 101         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"),
 102         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"),
 103         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 104         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"),
 105         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"),
 106         PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 107         PVID(0x8086, E1000_DEV_ID_82572EI,              "Intel(R) PRO/1000 Network Connection"),
 108         PVID(0x8086, E1000_DEV_ID_82572EI_COPPER,       "Intel(R) PRO/1000 Network Connection"),
 109         PVID(0x8086, E1000_DEV_ID_82572EI_FIBER,        "Intel(R) PRO/1000 Network Connection"),
 110         PVID(0x8086, E1000_DEV_ID_82572EI_SERDES,       "Intel(R) PRO/1000 Network Connection"),
 111         PVID(0x8086, E1000_DEV_ID_82573E,               "Intel(R) PRO/1000 Network Connection"),
 112         PVID(0x8086, E1000_DEV_ID_82573E_IAMT,  "Intel(R) PRO/1000 Network Connection"),
 113         PVID(0x8086, E1000_DEV_ID_82573L,               "Intel(R) PRO/1000 Network Connection"),
 114         PVID(0x8086, E1000_DEV_ID_82583V,               "Intel(R) PRO/1000 Network Connection"),
 115         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"),
 116         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"),
 117         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"),
 118         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"),
 119         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT,       "Intel(R) PRO/1000 Network Connection"),
 120         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 121         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C,   "Intel(R) PRO/1000 Network Connection"),
 122         PVID(0x8086, E1000_DEV_ID_ICH8_IFE,     "Intel(R) PRO/1000 Network Connection"),
 123         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT,  "Intel(R) PRO/1000 Network Connection"),
 124         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G,   "Intel(R) PRO/1000 Network Connection"),
 125         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M,   "Intel(R) PRO/1000 Network Connection"),
 126         PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3,        "Intel(R) PRO/1000 Network Connection"),
 127         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT,       "Intel(R) PRO/1000 Network Connection"),
 128         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 129         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C,   "Intel(R) PRO/1000 Network Connection"),
 130         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M,   "Intel(R) PRO/1000 Network Connection"),
 131         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"),
 132         PVID(0x8086, E1000_DEV_ID_ICH9_IFE,     "Intel(R) PRO/1000 Network Connection"),
 133         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT,  "Intel(R) PRO/1000 Network Connection"),
 134         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G,   "Intel(R) PRO/1000 Network Connection"),
 135         PVID(0x8086, E1000_DEV_ID_ICH9_BM,              "Intel(R) PRO/1000 Network Connection"),
 136         PVID(0x8086, E1000_DEV_ID_82574L,               "Intel(R) PRO/1000 Network Connection"),
 137         PVID(0x8086, E1000_DEV_ID_82574LA,              "Intel(R) PRO/1000 Network Connection"),
 138         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM,        "Intel(R) PRO/1000 Network Connection"),
 139         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF,        "Intel(R) PRO/1000 Network Connection"),
 140         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"),
 141         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM,        "Intel(R) PRO/1000 Network Connection"),
 142         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF,        "Intel(R) PRO/1000 Network Connection"),
 143         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"),
 144         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM,  "Intel(R) PRO/1000 Network Connection"),
 145         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC,  "Intel(R) PRO/1000 Network Connection"),
 146         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM,  "Intel(R) PRO/1000 Network Connection"),
 147         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC,  "Intel(R) PRO/1000 Network Connection"),
 148         PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM,   "Intel(R) PRO/1000 Network Connection"),
 149         PVID(0x8086, E1000_DEV_ID_PCH2_LV_V,    "Intel(R) PRO/1000 Network Connection"),
 150         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM,      "Intel(R) PRO/1000 Network Connection"),
 151         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V,       "Intel(R) PRO/1000 Network Connection"),
 152         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"),
 153         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"),
 154         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"),
 155         PVID(0x8086, E1000_DEV_ID_PCH_I218_V2,  "Intel(R) PRO/1000 Network Connection"),
 156         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"),
 157         PVID(0x8086, E1000_DEV_ID_PCH_I218_V3,  "Intel(R) PRO/1000 Network Connection"),
 158         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"),
 159         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V,  "Intel(R) PRO/1000 Network Connection"),
 160         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"),
 161         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"),
 162         PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"),
 163         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"),
 164         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"),
 165         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"),
 166         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"),
 167         /* required last entry */
 168         PVID_END
 169 };
 170
 171 static pci_vendor_info_t igb_vendor_info_array[] =
 172 {
 173         /* Intel(R) PRO/1000 Network Connection - em */
 174         PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 175         PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 176         PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 177         PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 178         PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 179         PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 180         PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 181         PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 182         PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 183         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 184         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 185         PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 186         PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 187         PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 188         PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 189         PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 190         PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 191         PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 192         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 193         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 194         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 195         PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 196         PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 197         PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 198         PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 199         PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 200         PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 201         PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 202         PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 203         PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 204         PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 205         PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 206         PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 207         PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 208         PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 209         PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 210         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 211         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 212         PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 213         /* required last entry */
 214         PVID_END
 215 };
 216
 217 /*********************************************************************
 218  *  Function prototypes
 219  *********************************************************************/
 220 static void     *em_register(device_t dev);
 221 static void     *igb_register(device_t dev);
 222 static int      em_if_attach_pre(if_ctx_t ctx);
 223 static int      em_if_attach_post(if_ctx_t ctx);
 224 static int      em_if_detach(if_ctx_t ctx);
 225 static int      em_if_shutdown(if_ctx_t ctx);
 226 static int      em_if_suspend(if_ctx_t ctx);
 227 static int      em_if_resume(if_ctx_t ctx);
 228
 229 static int      em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets);
 230 static int      em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets);
 231 static void     em_if_queues_free(if_ctx_t ctx);
 232
 233 static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
 234 static void     em_if_init(if_ctx_t ctx);
 235 static void     em_if_stop(if_ctx_t ctx);
 236 static void     em_if_media_status(if_ctx_t, struct ifmediareq *);
 237 static int      em_if_media_change(if_ctx_t ctx);
 238 static int      em_if_mtu_set(if_ctx_t ctx, uint32_t mtu);
 239 static void     em_if_timer(if_ctx_t ctx, uint16_t qid);
 240 static void     em_if_vlan_register(if_ctx_t ctx, u16 vtag);
 241 static void     em_if_vlan_unregister(if_ctx_t ctx, u16 vtag);
 242
 243 static void     em_identify_hardware(if_ctx_t ctx);
 244 static int      em_allocate_pci_resources(if_ctx_t ctx);
 245 static void     em_free_pci_resources(if_ctx_t ctx);
 246 static void     em_reset(if_ctx_t ctx);
 247 static int      em_setup_interface(if_ctx_t ctx);
 248 static int      em_setup_msix(if_ctx_t ctx);
 249
 250 static void     em_initialize_transmit_unit(if_ctx_t ctx);
 251 static void     em_initialize_receive_unit(if_ctx_t ctx);
 252
 253 static void     em_if_enable_intr(if_ctx_t ctx);
 254 static void     em_if_disable_intr(if_ctx_t ctx);
 255 static int      em_if_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 256 static void     em_if_multi_set(if_ctx_t ctx);
 257 static void     em_if_update_admin_status(if_ctx_t ctx);
 258 static void     em_update_stats_counters(struct adapter *);
 259 static void     em_add_hw_stats(struct adapter *adapter);
 260 static int      em_if_set_promisc(if_ctx_t ctx, int flags);
 261 static void     em_setup_vlan_hw_support(struct adapter *);
 262 static int      em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
 263 static void     em_print_nvm_info(struct adapter *);
 264 static int      em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 265 static void     em_print_debug_info(struct adapter *);
 266 static int      em_is_valid_ether_addr(u8 *);
 267 static int      em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
 268 static void     em_add_int_delay_sysctl(struct adapter *, const char *,
 269                     const char *, struct em_int_delay_info *, int, int);
 270 /* Management and WOL Support */
 271 static void     em_init_manageability(struct adapter *);
 272 static void     em_release_manageability(struct adapter *);
 273 static void     em_get_hw_control(struct adapter *);
 274 static void     em_release_hw_control(struct adapter *);
 275 static void     em_get_wakeup(if_ctx_t ctx);
 276 static void     em_enable_wakeup(if_ctx_t ctx);
 277 static int      em_enable_phy_wakeup(struct adapter *);
 278 static void     em_disable_aspm(struct adapter *);
 279
 280 int             em_intr(void *arg);
 281 static void     em_disable_promisc(if_ctx_t ctx);
 282
 283 /* MSIX handlers */
 284 static int      em_if_msix_intr_assign(if_ctx_t, int);
 285 static int      em_msix_link(void *);
 286 static void     em_handle_link(void *context);
 287
 288 static void     em_enable_vectors_82574(if_ctx_t);
 289
 290 static void     em_set_sysctl_value(struct adapter *, const char *,
 291                     const char *, int *, int);
 292 static int      em_set_flowcntl(SYSCTL_HANDLER_ARGS);
 293 static int      em_sysctl_eee(SYSCTL_HANDLER_ARGS);
 294 static void     em_if_led_func(if_ctx_t ctx, int onoff);
 295
 296 static void     em_init_tx_ring(struct em_tx_queue *que);
 297 static int      em_get_regs(SYSCTL_HANDLER_ARGS);
 298
 299 static void     lem_smartspeed(struct adapter *adapter);
 300 static void     igb_configure_queues(struct adapter *adapter);
 301
 302
 303 /*********************************************************************
 304  *  FreeBSD Device Interface Entry Points
 305  *********************************************************************/
 306 static device_method_t em_methods[] = {
 307         /* Device interface */
 308   DEVMETHOD(device_register, em_register),
 309   DEVMETHOD(device_probe, iflib_device_probe),
 310   DEVMETHOD(device_attach, iflib_device_attach),
 311   DEVMETHOD(device_detach, iflib_device_detach),
 312   DEVMETHOD(device_shutdown, iflib_device_shutdown),
 313   DEVMETHOD(device_suspend, iflib_device_suspend),
 314   DEVMETHOD(device_resume, iflib_device_resume),
 315   DEVMETHOD_END
 316 };
 317
 318 static device_method_t igb_methods[] = {
 319         /* Device interface */
 320   DEVMETHOD(device_register, igb_register),
 321   DEVMETHOD(device_probe, iflib_device_probe),
 322   DEVMETHOD(device_attach, iflib_device_attach),
 323   DEVMETHOD(device_detach, iflib_device_detach),
 324   DEVMETHOD(device_shutdown, iflib_device_shutdown),
 325   DEVMETHOD(device_suspend, iflib_device_suspend),
 326   DEVMETHOD(device_resume, iflib_device_resume),
 327   DEVMETHOD_END
 328 };
 329
 330
 331 static driver_t em_driver = {
 332         "em", em_methods, sizeof(struct adapter),
 333 };
 334
 335 static devclass_t em_devclass;
 336 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
 337
 338 MODULE_DEPEND(em, pci, 1, 1, 1);
 339 MODULE_DEPEND(em, ether, 1, 1, 1);
 340 MODULE_DEPEND(em, iflib, 1, 1, 1);
 341
 342 static driver_t igb_driver = {
 343         "igb", igb_methods, sizeof(struct adapter),
 344 };
 345
 346 static devclass_t igb_devclass;
 347 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
 348
 349 MODULE_DEPEND(igb, pci, 1, 1, 1);
 350 MODULE_DEPEND(igb, ether, 1, 1, 1);
 351 MODULE_DEPEND(igb, iflib, 1, 1, 1);
 352
 353
 354 static device_method_t em_if_methods[] = {
 355         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 356         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 357         DEVMETHOD(ifdi_detach, em_if_detach),
 358         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 359         DEVMETHOD(ifdi_suspend, em_if_suspend),
 360         DEVMETHOD(ifdi_resume, em_if_resume),
 361         DEVMETHOD(ifdi_init, em_if_init),
 362         DEVMETHOD(ifdi_stop, em_if_stop),
 363         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 364         DEVMETHOD(ifdi_intr_enable, em_if_enable_intr),
 365         DEVMETHOD(ifdi_intr_disable, em_if_disable_intr),
 366         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 367         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 368         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 369         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 370         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 371         DEVMETHOD(ifdi_media_status, em_if_media_status),
 372         DEVMETHOD(ifdi_media_change, em_if_media_change),
 373         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 374         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 375         DEVMETHOD(ifdi_timer, em_if_timer),
 376         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 377         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 378         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 379         DEVMETHOD(ifdi_led_func, em_if_led_func),
 380         DEVMETHOD(ifdi_queue_intr_enable, em_if_queue_intr_enable),
 381         DEVMETHOD_END
 382 };
 383
 384   /*
 385  * note that if (adapter->msix_mem) is replaced by:
 386  * if (adapter->intr_type == IFLIB_INTR_MSIX)
 387  */
 388 static driver_t em_if_driver = {
 389   "em_if", em_if_methods, sizeof(struct adapter)
 390 };
 391
 392 /*********************************************************************
 393  *  Tunable default values.
 394  *********************************************************************/
 395
 396 #define EM_TICKS_TO_USECS(ticks)        ((1024 * (ticks) + 500) / 1000)
 397 #define EM_USECS_TO_TICKS(usecs)        ((1000 * (usecs) + 512) / 1024)
 398 #define M_TSO_LEN                       66
 399
 400 #define MAX_INTS_PER_SEC        8000
 401 #define DEFAULT_ITR             (1000000000/(MAX_INTS_PER_SEC * 256))
 402
 403 /* Allow common code without TSO */
 404 #ifndef CSUM_TSO
 405 #define CSUM_TSO        0
 406 #endif
 407
 408 #define TSO_WORKAROUND  4
 409
 410 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters");
 411
 412 static int em_disable_crc_stripping = 0;
 413 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
 414     &em_disable_crc_stripping, 0, "Disable CRC Stripping");
 415
 416 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
 417 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
 418 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
 419     0, "Default transmit interrupt delay in usecs");
 420 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
 421     0, "Default receive interrupt delay in usecs");
 422
 423 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
 424 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
 425 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
 426     &em_tx_abs_int_delay_dflt, 0,
 427     "Default transmit interrupt delay limit in usecs");
 428 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
 429     &em_rx_abs_int_delay_dflt, 0,
 430     "Default receive interrupt delay limit in usecs");
 431
 432 static int em_smart_pwr_down = FALSE;
 433 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
 434     0, "Set to true to leave smart power down enabled on newer adapters");
 435
 436 /* Controls whether promiscuous also shows bad packets */
 437 static int em_debug_sbp = TRUE;
 438 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
 439     "Show bad packets in promiscuous mode");
 440
 441 /* How many packets rxeof tries to clean at a time */
 442 static int em_rx_process_limit = 100;
 443 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
 444     &em_rx_process_limit, 0,
 445     "Maximum number of received packets to process "
 446     "at a time, -1 means unlimited");
 447
 448 /* Energy efficient ethernet - default to OFF */
 449 static int eee_setting = 1;
 450 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
 451     "Enable Energy Efficient Ethernet");
 452
 453 /*
 454 ** Tuneable Interrupt rate
 455 */
 456 static int em_max_interrupt_rate = 8000;
 457 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
 458     &em_max_interrupt_rate, 0, "Maximum interrupts per second");
 459
 460
 461
 462 /* Global used in WOL setup with multiport cards */
 463 static int global_quad_port_a = 0;
 464
 465 extern struct if_txrx igb_txrx;
 466 extern struct if_txrx em_txrx;
 467 extern struct if_txrx lem_txrx;
 468
 469 static struct if_shared_ctx em_sctx_init = {
 470         .isc_magic = IFLIB_MAGIC,
 471         .isc_q_align = PAGE_SIZE,
 472         .isc_tx_maxsize = EM_TSO_SIZE,
 473         .isc_tx_maxsegsize = PAGE_SIZE,
 474         .isc_rx_maxsize = MJUM9BYTES,
 475         .isc_rx_nsegments = 1,
 476         .isc_rx_maxsegsize = MJUM9BYTES,
 477         .isc_nfl = 1,
 478         .isc_nrxqs = 1,
 479         .isc_ntxqs = 1,
 480         .isc_admin_intrcnt = 1,
 481         .isc_vendor_info = em_vendor_info_array,
 482         .isc_driver_version = em_driver_version,
 483         .isc_driver = &em_if_driver,
 484         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP,
 485
 486         .isc_nrxd_min = {EM_MIN_RXD},
 487         .isc_ntxd_min = {EM_MIN_TXD},
 488         .isc_nrxd_max = {EM_MAX_RXD},
 489         .isc_ntxd_max = {EM_MAX_TXD},
 490         .isc_nrxd_default = {EM_DEFAULT_RXD},
 491         .isc_ntxd_default = {EM_DEFAULT_TXD},
 492 };
 493
 494 if_shared_ctx_t em_sctx = &em_sctx_init;
 495
 496
 497 static struct if_shared_ctx igb_sctx_init = {
 498         .isc_magic = IFLIB_MAGIC,
 499         .isc_q_align = PAGE_SIZE,
 500         .isc_tx_maxsize = EM_TSO_SIZE,
 501         .isc_tx_maxsegsize = PAGE_SIZE,
 502         .isc_rx_maxsize = MJUM9BYTES,
 503         .isc_rx_nsegments = 1,
 504         .isc_rx_maxsegsize = MJUM9BYTES,
 505         .isc_nfl = 1,
 506         .isc_nrxqs = 1,
 507         .isc_ntxqs = 1,
 508         .isc_admin_intrcnt = 1,
 509         .isc_vendor_info = igb_vendor_info_array,
 510         .isc_driver_version = em_driver_version,
 511         .isc_driver = &em_if_driver,
 512         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP,
 513
 514         .isc_nrxd_min = {EM_MIN_RXD},
 515         .isc_ntxd_min = {EM_MIN_TXD},
 516         .isc_nrxd_max = {EM_MAX_RXD},
 517         .isc_ntxd_max = {EM_MAX_TXD},
 518         .isc_nrxd_default = {EM_DEFAULT_RXD},
 519         .isc_ntxd_default = {EM_DEFAULT_TXD},
 520 };
 521
 522 if_shared_ctx_t igb_sctx = &igb_sctx_init;
 523
 524 /*****************************************************************
 525  *
 526  * Dump Registers
 527  *
 528  ****************************************************************/
 529 #define IGB_REGS_LEN 739
 530
 531 static int em_get_regs(SYSCTL_HANDLER_ARGS)
 532 {
 533         struct adapter *adapter = (struct adapter *)arg1;
 534         struct e1000_hw *hw = &adapter->hw;
 535
 536         struct sbuf *sb;
 537         u32 *regs_buff = (u32 *)malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_NOWAIT);
 538         int rc;
 539
 540         memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
 541
 542         rc = sysctl_wire_old_buffer(req, 0);
 543         MPASS(rc == 0);
 544         if (rc != 0)
 545           return (rc);
 546
 547         sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
 548         MPASS(sb != NULL);
 549         if (sb == NULL)
 550                 return (ENOMEM);
 551
 552         /* General Registers */
 553         regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
 554         regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
 555         regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
 556         regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
 557         regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
 558         regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
 559         regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
 560         regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
 561         regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
 562         regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
 563         regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
 564         regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
 565         regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
 566         regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
 567         regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
 568         regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
 569         regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
 570         regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
 571         regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
 572         regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
 573         regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
 574         regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
 575
 576         sbuf_printf(sb, "General Registers\n");
 577         sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
 578         sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
 579         sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]);
 580
 581         sbuf_printf(sb, "Interrupt Registers\n");
 582         sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
 583
 584         sbuf_printf(sb, "RX Registers\n");
 585         sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
 586         sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
 587         sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
 588         sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
 589         sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
 590         sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
 591         sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
 592
 593         sbuf_printf(sb, "TX Registers\n");
 594         sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
 595         sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
 596         sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
 597         sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
 598         sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
 599         sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
 600         sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
 601         sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
 602         sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
 603         sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
 604         sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
 605
 606 #ifdef DUMP_DESCS
 607         {
 608                 if_softc_ctx_t scctx = adapter->shared;
 609                 struct rx_ring *rxr = &rx_que->rxr;
 610                 struct tx_ring *txr = &tx_que->txr;
 611                 int ntxd = scctx->isc_ntxd[0];
 612                 int nrxd = scctx->isc_nrxd[0];
 613                 int j;
 614
 615         for (j = 0; j < nrxd; j++) {
 616                 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
 617                 u32 length =  le32toh(rxr->rx_base[j].wb.upper.length);
 618                 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 "  Error:%d  Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
 619         }
 620
 621         for (j = 0; j < min(ntxd, 256); j++) {
 622                 struct em_txbuffer *buf = &txr->tx_buffers[j];
 623                 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
 624
 625                 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x  eop: %d DD=%d\n",
 626                             j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
 627                             buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
 628
 629         }
 630         }
 631 #endif
 632
 633         rc = sbuf_finish(sb);
 634         sbuf_delete(sb);
 635         return(rc);
 636 }
 637
 638 static void *
 639 em_register(device_t dev)
 640 {
 641         return (em_sctx);
 642 }
 643
 644 static void *
 645 igb_register(device_t dev)
 646 {
 647         return (igb_sctx);
 648 }
 649
 650 static void
 651 em_init_tx_ring(struct em_tx_queue *que)
 652 {
 653         struct adapter *sc = que->adapter;
 654         if_softc_ctx_t scctx = sc->shared;
 655         struct tx_ring *txr = &que->txr;
 656         struct em_txbuffer *tx_buffer;
 657
 658         tx_buffer = txr->tx_buffers;
 659         for (int i = 0; i < scctx->isc_ntxd[0]; i++, tx_buffer++) {
 660                 tx_buffer->eop = -1;
 661         }
 662 }
 663
 664 static int
 665 em_set_num_queues(if_ctx_t ctx)
 666 {
 667         struct adapter *adapter = iflib_get_softc(ctx);
 668         int maxqueues;
 669
 670         /* Sanity check based on HW */
 671         switch (adapter->hw.mac.type) {
 672                 case e1000_82576:
 673                 case e1000_82580:
 674                 case e1000_i350:
 675                 case e1000_i354:
 676                         maxqueues = 8;
 677                         break;
 678                 case e1000_i210:
 679                 case e1000_82575:
 680                         maxqueues = 4;
 681                         break;
 682                 case e1000_i211:
 683                 case e1000_82574:
 684                         maxqueues = 2;
 685                         break;
 686                 default:
 687                         maxqueues = 1;
 688                         break;
 689         }
 690
 691         return (maxqueues);
 692 }
 693
 694
 695 #define EM_CAPS                                                         \
 696         IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \
 697         IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | \
 698         IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU;
 699
 700 #define IGB_CAPS                                                        \
 701         IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \
 702         IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM | \
 703         IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU | IFCAP_TXCSUM_IPV6 | IFCAP_HWCSUM_IPV6 | IFCAP_JUMBO_MTU;
 704
 705 /*********************************************************************
 706  *  Device initialization routine
 707  *
 708  *  The attach entry point is called when the driver is being loaded.
 709  *  This routine identifies the type of hardware, allocates all resources
 710  *  and initializes the hardware.
 711  *
 712  *  return 0 on success, positive on failure
 713  *********************************************************************/
 714
 715 static int
 716 em_if_attach_pre(if_ctx_t ctx)
 717 {
 718         struct adapter  *adapter;
 719         if_softc_ctx_t scctx;
 720         device_t        dev;
 721         struct e1000_hw *hw;
 722         int             error = 0;
 723
 724         INIT_DEBUGOUT("em_if_attach_pre begin");
 725         dev = iflib_get_dev(ctx);
 726         adapter = iflib_get_softc(ctx);
 727
 728         if (resource_disabled("em", device_get_unit(dev))) {
 729                 device_printf(dev, "Disabled by device hint\n");
 730                 return (ENXIO);
 731         }
 732
 733         adapter->ctx = ctx;
 734         adapter->dev = adapter->osdep.dev = dev;
 735         scctx = adapter->shared = iflib_get_softc_ctx(ctx);
 736         adapter->media = iflib_get_media(ctx);
 737         hw = &adapter->hw;
 738
 739         adapter->tx_process_limit = scctx->isc_ntxd[0];
 740
 741         /* SYSCTL stuff */
 742         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 743             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 744             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 745             em_sysctl_nvm_info, "I", "NVM Information");
 746
 747         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 748             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 749             OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 750             em_sysctl_debug_info, "I", "Debug Information");
 751
 752         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 753             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 754             OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 755             em_set_flowcntl, "I", "Flow Control");
 756
 757         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 758             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 759             OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0,
 760             em_get_regs, "A", "Dump Registers");
 761
 762         /* Determine hardware and mac info */
 763         em_identify_hardware(ctx);
 764
 765         /* Set isc_msix_bar */
 766         scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR);
 767         scctx->isc_tx_nsegments = EM_MAX_SCATTER;
 768         scctx->isc_tx_tso_segments_max = scctx->isc_tx_nsegments;
 769         scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 770         scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 771         scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
 772         device_printf(dev, "attach_pre capping queues at %d\n", scctx->isc_ntxqsets_max);
 773
 774         scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 775
 776
 777         if (adapter->hw.mac.type >= igb_mac_min) {
 778                 int try_second_bar;
 779
 780                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
 781                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
 782                 scctx->isc_txrx = &igb_txrx;
 783                 scctx->isc_capenable = IGB_CAPS;
 784                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | CSUM_IP6_TCP \
 785                         | CSUM_IP6_UDP | CSUM_IP6_TCP;
 786                 if (adapter->hw.mac.type != e1000_82575)
 787                         scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
 788
 789                 /*
 790                 ** Some new devices, as with ixgbe, now may
 791                 ** use a different BAR, so we need to keep
 792                 ** track of which is used.
 793                 */
 794                 try_second_bar = pci_read_config(dev, scctx->isc_msix_bar, 4);
 795                 if (try_second_bar == 0)
 796                         scctx->isc_msix_bar += 4;
 797
 798         } else if (adapter->hw.mac.type >= em_mac_min) {
 799                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 800                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
 801                 scctx->isc_txrx = &em_txrx;
 802                 scctx->isc_capenable = EM_CAPS;
 803                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 804         } else {
 805                 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 806                 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
 807                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 808                 scctx->isc_txrx = &lem_txrx;
 809                 scctx->isc_capenable = EM_CAPS;
 810                 if (adapter->hw.mac.type < e1000_82543)
 811                         scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
 812                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 813                 scctx->isc_msix_bar = 0;
 814         }
 815
 816         /* Setup PCI resources */
 817         if (em_allocate_pci_resources(ctx)) {
 818                 device_printf(dev, "Allocation of PCI resources failed\n");
 819                 error = ENXIO;
 820                 goto err_pci;
 821         }
 822
 823         /*
 824         ** For ICH8 and family we need to
 825         ** map the flash memory, and this
 826         ** must happen after the MAC is
 827         ** identified
 828         */
 829         if ((hw->mac.type == e1000_ich8lan) ||
 830             (hw->mac.type == e1000_ich9lan) ||
 831             (hw->mac.type == e1000_ich10lan) ||
 832             (hw->mac.type == e1000_pchlan) ||
 833             (hw->mac.type == e1000_pch2lan) ||
 834             (hw->mac.type == e1000_pch_lpt)) {
 835                 int rid = EM_BAR_TYPE_FLASH;
 836                 adapter->flash = bus_alloc_resource_any(dev,
 837                     SYS_RES_MEMORY, &rid, RF_ACTIVE);
 838                 if (adapter->flash == NULL) {
 839                         device_printf(dev, "Mapping of Flash failed\n");
 840                         error = ENXIO;
 841                         goto err_pci;
 842                 }
 843                 /* This is used in the shared code */
 844                 hw->flash_address = (u8 *)adapter->flash;
 845                 adapter->osdep.flash_bus_space_tag =
 846                     rman_get_bustag(adapter->flash);
 847                 adapter->osdep.flash_bus_space_handle =
 848                     rman_get_bushandle(adapter->flash);
 849         }
 850         /*
 851         ** In the new SPT device flash is not  a
 852         ** separate BAR, rather it is also in BAR0,
 853         ** so use the same tag and an offset handle for the
 854         ** FLASH read/write macros in the shared code.
 855         */
 856         else if (hw->mac.type == e1000_pch_spt) {
 857                 adapter->osdep.flash_bus_space_tag =
 858                     adapter->osdep.mem_bus_space_tag;
 859                 adapter->osdep.flash_bus_space_handle =
 860                     adapter->osdep.mem_bus_space_handle
 861                     + E1000_FLASH_BASE_ADDR;
 862         }
 863
 864         /* Do Shared Code initialization */
 865         error = e1000_setup_init_funcs(hw, TRUE);
 866         if (error) {
 867                 device_printf(dev, "Setup of Shared code failed, error %d\n",
 868                     error);
 869                 error = ENXIO;
 870                 goto err_pci;
 871         }
 872
 873         em_setup_msix(ctx);
 874         e1000_get_bus_info(hw);
 875
 876         /* Set up some sysctls for the tunable interrupt delays */
 877         em_add_int_delay_sysctl(adapter, "rx_int_delay",
 878             "receive interrupt delay in usecs", &adapter->rx_int_delay,
 879             E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
 880         em_add_int_delay_sysctl(adapter, "tx_int_delay",
 881             "transmit interrupt delay in usecs", &adapter->tx_int_delay,
 882             E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
 883         em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
 884             "receive interrupt delay limit in usecs",
 885             &adapter->rx_abs_int_delay,
 886             E1000_REGISTER(hw, E1000_RADV),
 887             em_rx_abs_int_delay_dflt);
 888         em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
 889             "transmit interrupt delay limit in usecs",
 890             &adapter->tx_abs_int_delay,
 891             E1000_REGISTER(hw, E1000_TADV),
 892             em_tx_abs_int_delay_dflt);
 893         em_add_int_delay_sysctl(adapter, "itr",
 894             "interrupt delay limit in usecs/4",
 895             &adapter->tx_itr,
 896             E1000_REGISTER(hw, E1000_ITR),
 897             DEFAULT_ITR);
 898
 899         /* Sysctl for limiting the amount of work done in the taskqueue */
 900         em_set_sysctl_value(adapter, "rx_processing_limit",
 901             "max number of rx packets to process", &adapter->rx_process_limit,
 902             em_rx_process_limit);
 903
 904         hw->mac.autoneg = DO_AUTO_NEG;
 905         hw->phy.autoneg_wait_to_complete = FALSE;
 906         hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 907
 908         if (adapter->hw.mac.type < em_mac_min) {
 909                 e1000_init_script_state_82541(&adapter->hw, TRUE);
 910                 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
 911         }
 912         /* Copper options */
 913         if (hw->phy.media_type == e1000_media_type_copper) {
 914                 hw->phy.mdix = AUTO_ALL_MODES;
 915                 hw->phy.disable_polarity_correction = FALSE;
 916                 hw->phy.ms_type = EM_MASTER_SLAVE;
 917         }
 918
 919         /*
 920          * Set the frame limits assuming
 921          * standard ethernet sized frames.
 922          */
 923         adapter->hw.mac.max_frame_size =
 924             ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
 925
 926         /*
 927          * This controls when hardware reports transmit completion
 928          * status.
 929          */
 930         hw->mac.report_tx_early = 1;
 931
 932         /* Allocate multicast array memory. */
 933         adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN *
 934             MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
 935         if (adapter->mta == NULL) {
 936                 device_printf(dev, "Can not allocate multicast setup array\n");
 937                 error = ENOMEM;
 938                 goto err_late;
 939         }
 940
 941         /* Check SOL/IDER usage */
 942         if (e1000_check_reset_block(hw))
 943                 device_printf(dev, "PHY reset is blocked"
 944                     " due to SOL/IDER session.\n");
 945
 946         /* Sysctl for setting Energy Efficient Ethernet */
 947         hw->dev_spec.ich8lan.eee_disable = eee_setting;
 948         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 949             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 950             OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW,
 951             adapter, 0, em_sysctl_eee, "I",
 952             "Disable Energy Efficient Ethernet");
 953
 954         /*
 955         ** Start from a known state, this is
 956         ** important in reading the nvm and
 957         ** mac from that.
 958         */
 959         e1000_reset_hw(hw);
 960
 961         /* Make sure we have a good EEPROM before we read from it */
 962         if (e1000_validate_nvm_checksum(hw) < 0) {
 963                 /*
 964                 ** Some PCI-E parts fail the first check due to
 965                 ** the link being in sleep state, call it again,
 966                 ** if it fails a second time its a real issue.
 967                 */
 968                 if (e1000_validate_nvm_checksum(hw) < 0) {
 969                         device_printf(dev,
 970                             "The EEPROM Checksum Is Not Valid\n");
 971                         error = EIO;
 972                         goto err_late;
 973                 }
 974         }
 975
 976         /* Copy the permanent MAC address out of the EEPROM */
 977         if (e1000_read_mac_addr(hw) < 0) {
 978                 device_printf(dev, "EEPROM read error while reading MAC"
 979                     " address\n");
 980                 error = EIO;
 981                 goto err_late;
 982         }
 983
 984         if (!em_is_valid_ether_addr(hw->mac.addr)) {
 985                 device_printf(dev, "Invalid MAC address\n");
 986                 error = EIO;
 987                 goto err_late;
 988         }
 989
 990         /* Disable ULP support */
 991         e1000_disable_ulp_lpt_lp(hw, TRUE);
 992
 993         /*
 994          * Get Wake-on-Lan and Management info for later use
 995          */
 996         em_get_wakeup(ctx);
 997
 998         iflib_set_mac(ctx, hw->mac.addr);
 999
1000         return (0);
1001
1002 err_late:
1003         em_release_hw_control(adapter);
1004 err_pci:
1005         em_free_pci_resources(ctx);
1006         free(adapter->mta, M_DEVBUF);
1007
1008         return (error);
1009 }
1010
1011 static int
1012 em_if_attach_post(if_ctx_t ctx)
1013 {
1014         struct adapter *adapter = iflib_get_softc(ctx);
1015         struct e1000_hw *hw = &adapter->hw;
1016         int error = 0;
1017
1018         /* Setup OS specific network interface */
1019         error = em_setup_interface(ctx);
1020         if (error != 0) {
1021                 goto err_late;
1022         }
1023
1024         em_reset(ctx);
1025
1026         /* Initialize statistics */
1027         em_update_stats_counters(adapter);
1028         hw->mac.get_link_status = 1;
1029         em_if_update_admin_status(ctx);
1030         em_add_hw_stats(adapter);
1031
1032         /* Non-AMT based hardware can now take control from firmware */
1033         if (adapter->has_manage && !adapter->has_amt)
1034                 em_get_hw_control(adapter);
1035
1036         INIT_DEBUGOUT("em_if_attach_post: end");
1037
1038         return (error);
1039
1040 err_late:
1041         em_release_hw_control(adapter);
1042         em_free_pci_resources(ctx);
1043         em_if_queues_free(ctx);
1044         free(adapter->mta, M_DEVBUF);
1045
1046         return (error);
1047 }
1048
1049 /*********************************************************************
1050  *  Device removal routine
1051  *
1052  *  The detach entry point is called when the driver is being removed.
1053  *  This routine stops the adapter and deallocates all the resources
1054  *  that were allocated for driver operation.
1055  *
1056  *  return 0 on success, positive on failure
1057  *********************************************************************/
1058
1059 static int
1060 em_if_detach(if_ctx_t ctx)
1061 {
1062         struct adapter  *adapter = iflib_get_softc(ctx);
1063
1064         INIT_DEBUGOUT("em_detach: begin");
1065
1066         e1000_phy_hw_reset(&adapter->hw);
1067
1068         em_release_manageability(adapter);
1069         em_release_hw_control(adapter);
1070         em_free_pci_resources(ctx);
1071
1072         return (0);
1073 }
1074
1075 /*********************************************************************
1076  *
1077  *  Shutdown entry point
1078  *
1079  **********************************************************************/
1080
1081 static int
1082 em_if_shutdown(if_ctx_t ctx)
1083 {
1084         return em_if_suspend(ctx);
1085 }
1086
1087 /*
1088  * Suspend/resume device methods.
1089  */
1090 static int
1091 em_if_suspend(if_ctx_t ctx)
1092 {
1093         struct adapter *adapter = iflib_get_softc(ctx);
1094
1095         em_release_manageability(adapter);
1096         em_release_hw_control(adapter);
1097         em_enable_wakeup(ctx);
1098         return (0);
1099 }
1100
1101 static int
1102 em_if_resume(if_ctx_t ctx)
1103 {
1104         struct adapter *adapter = iflib_get_softc(ctx);
1105
1106         if (adapter->hw.mac.type == e1000_pch2lan)
1107                 e1000_resume_workarounds_pchlan(&adapter->hw);
1108         em_if_init(ctx);
1109         em_init_manageability(adapter);
1110
1111         return(0);
1112 }
1113
1114 static int
1115 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1116 {
1117   int max_frame_size;
1118   struct adapter *adapter = iflib_get_softc(ctx);
1119   struct ifnet *ifp = iflib_get_ifp(ctx);
1120
1121   IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1122
1123   switch (adapter->hw.mac.type) {
1124   case e1000_82571:
1125   case e1000_82572:
1126   case e1000_ich9lan:
1127   case e1000_ich10lan:
1128   case e1000_pch2lan:
1129   case e1000_pch_lpt:
1130   case e1000_pch_spt:
1131   case e1000_82574:
1132   case e1000_82583:
1133   case e1000_80003es2lan:       /* 9K Jumbo Frame size */
1134           max_frame_size = 9234;
1135           break;
1136   case e1000_pchlan:
1137           max_frame_size = 4096;
1138           break;
1139           /* Adapters that do not support jumbo frames */
1140   case e1000_ich8lan:
1141           max_frame_size = ETHER_MAX_LEN;
1142           break;
1143   default:
1144           max_frame_size = MAX_JUMBO_FRAME_SIZE;
1145   }
1146   if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1147           return (EINVAL);
1148   }
1149
1150   adapter->hw.mac.max_frame_size = if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN;
1151   return (0);
1152 }
1153
1154 /*********************************************************************
1155  *  Init entry point
1156  *
1157  *  This routine is used in two ways. It is used by the stack as
1158  *  init entry point in network interface structure. It is also used
1159  *  by the driver as a hw/sw initialization routine to get to a
1160  *  consistent state.
1161  *
1162  *  return 0 on success, positive on failure
1163  **********************************************************************/
1164
1165 static void
1166 em_if_init(if_ctx_t ctx)
1167 {
1168         struct adapter *adapter = iflib_get_softc(ctx);
1169         struct ifnet *ifp = iflib_get_ifp(ctx);
1170
1171         INIT_DEBUGOUT("em_if_init: begin");
1172
1173         /* Get the latest mac address, User can use a LAA */
1174         bcopy(if_getlladdr(ifp), adapter->hw.mac.addr,
1175               ETHER_ADDR_LEN);
1176
1177         /* Put the address into the Receive Address Array */
1178         e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1179
1180         /*
1181          * With the 82571 adapter, RAR[0] may be overwritten
1182          * when the other port is reset, we make a duplicate
1183          * in RAR[14] for that eventuality, this assures
1184          * the interface continues to function.
1185          */
1186         if (adapter->hw.mac.type == e1000_82571) {
1187                 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1188                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1189                     E1000_RAR_ENTRIES - 1);
1190         }
1191
1192         /* Initialize the hardware */
1193         em_reset(ctx);
1194         em_if_update_admin_status(ctx);
1195
1196         /* Setup VLAN support, basic and offload if available */
1197         E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1198
1199         /* Clear bad data from Rx FIFOs */
1200         if (adapter->hw.mac.type >= igb_mac_min)
1201                 e1000_rx_fifo_flush_82575(&adapter->hw);
1202
1203         /* Configure for OS presence */
1204         em_init_manageability(adapter);
1205
1206         /* Prepare transmit descriptors and buffers */
1207         em_initialize_transmit_unit(ctx);
1208
1209         /* Setup Multicast table */
1210         em_if_multi_set(ctx);
1211
1212         /*
1213         ** Figure out the desired mbuf
1214         ** pool for doing jumbos
1215         */
1216         if (adapter->hw.mac.max_frame_size <= 2048)
1217                 adapter->rx_mbuf_sz = MCLBYTES;
1218         else if (adapter->hw.mac.max_frame_size <= 4096)
1219                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
1220         else
1221                 adapter->rx_mbuf_sz = MJUM9BYTES;
1222
1223         em_initialize_receive_unit(ctx);
1224
1225         /* Use real VLAN Filter support? */
1226         if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1227                 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
1228                         /* Use real VLAN Filter support */
1229                         em_setup_vlan_hw_support(adapter);
1230                 else {
1231                         u32 ctrl;
1232                         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1233                         ctrl |= E1000_CTRL_VME;
1234                         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1235                 }
1236         }
1237
1238         /* Don't lose promiscuous settings */
1239         em_if_set_promisc(ctx, IFF_PROMISC);
1240         e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1241
1242         /* MSI/X configuration for 82574 */
1243         if (adapter->hw.mac.type == e1000_82574) {
1244                 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1245
1246                 tmp |= E1000_CTRL_EXT_PBA_CLR;
1247                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1248                 /* Set the IVAR - interrupt vector routing. */
1249                 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars);
1250         } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1251                 igb_configure_queues(adapter);
1252
1253         /* this clears any pending interrupts */
1254         E1000_READ_REG(&adapter->hw, E1000_ICR);
1255         E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC);
1256
1257         /* AMT based hardware can now take control from firmware */
1258         if (adapter->has_manage && adapter->has_amt)
1259                 em_get_hw_control(adapter);
1260
1261         /* Set Energy Efficient Ethernet */
1262         if (adapter->hw.mac.type >= igb_mac_min &&
1263             adapter->hw.phy.media_type == e1000_media_type_copper) {
1264                 if (adapter->hw.mac.type == e1000_i354)
1265                         e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
1266                 else
1267                         e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
1268         }
1269 }
1270
1271 /*********************************************************************
1272  *
1273  *  Fast Legacy/MSI Combined Interrupt Service routine
1274  *
1275  *********************************************************************/
1276 int
1277 em_intr(void *arg)
1278 {
1279         struct adapter  *adapter = arg;
1280         if_ctx_t ctx = adapter->ctx;
1281         u32             reg_icr;
1282
1283         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1284
1285         if (adapter->intr_type != IFLIB_INTR_LEGACY)
1286                 goto skip_stray;
1287         /* Hot eject?  */
1288         if (reg_icr == 0xffffffff)
1289                 return FILTER_STRAY;
1290
1291         /* Definitely not our interrupt.  */
1292         if (reg_icr == 0x0)
1293                 return FILTER_STRAY;
1294
1295         /*
1296          * Starting with the 82571 chip, bit 31 should be used to
1297          * determine whether the interrupt belongs to us.
1298          */
1299         if (adapter->hw.mac.type >= e1000_82571 &&
1300             (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1301                 return FILTER_STRAY;
1302
1303 skip_stray:
1304         /* Link status change */
1305         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1306                 adapter->hw.mac.get_link_status = 1;
1307                 iflib_admin_intr_deferred(ctx);
1308         }
1309
1310         if (reg_icr & E1000_ICR_RXO)
1311                 adapter->rx_overruns++;
1312
1313         return (FILTER_SCHEDULE_THREAD);
1314 }
1315
1316 static void
1317 igb_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq)
1318 {
1319         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims);
1320 }
1321
1322 static void
1323 em_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq)
1324 {
1325         E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims);
1326 }
1327
1328 static int
1329 em_if_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1330 {
1331         struct adapter  *adapter = iflib_get_softc(ctx);
1332         struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1333
1334         if (adapter->hw.mac.type >= igb_mac_min)
1335                 igb_enable_queue(adapter, rxq);
1336         else
1337                 em_enable_queue(adapter, rxq);
1338         return (0);
1339 }
1340
1341 /*********************************************************************
1342  *
1343  *  MSIX RX Interrupt Service routine
1344  *
1345  **********************************************************************/
1346 static int
1347 em_msix_que(void *arg)
1348 {
1349         struct em_rx_queue *que = arg;
1350
1351         ++que->irqs;
1352
1353         return (FILTER_SCHEDULE_THREAD);
1354 }
1355
1356 /*********************************************************************
1357  *
1358  *  MSIX Link Fast Interrupt Service routine
1359  *
1360  **********************************************************************/
1361 static int
1362 em_msix_link(void *arg)
1363 {
1364         struct adapter  *adapter = arg;
1365         u32             reg_icr;
1366
1367         ++adapter->link_irq;
1368         MPASS(adapter->hw.back != NULL);
1369         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1370
1371         if (reg_icr & E1000_ICR_RXO)
1372                 adapter->rx_overruns++;
1373
1374         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1375                 em_handle_link(adapter->ctx);
1376         } else {
1377                 E1000_WRITE_REG(&adapter->hw, E1000_IMS,
1378                                 EM_MSIX_LINK | E1000_IMS_LSC);
1379                 if (adapter->hw.mac.type >= igb_mac_min)
1380                         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1381
1382         }
1383
1384         /*
1385         ** Because we must read the ICR for this interrupt
1386         ** it may clear other causes using autoclear, for
1387         ** this reason we simply create a soft interrupt
1388         ** for all these vectors.
1389         */
1390         if (reg_icr && adapter->hw.mac.type < igb_mac_min) {
1391                 E1000_WRITE_REG(&adapter->hw,
1392                         E1000_ICS, adapter->ims);
1393         }
1394
1395         return (FILTER_HANDLED);
1396 }
1397
1398 static void
1399 em_handle_link(void *context)
1400 {
1401         if_ctx_t ctx = context;
1402         struct adapter  *adapter = iflib_get_softc(ctx);
1403
1404         adapter->hw.mac.get_link_status = 1;
1405         iflib_admin_intr_deferred(ctx);
1406 }
1407
1408
1409 /*********************************************************************
1410  *
1411  *  Media Ioctl callback
1412  *
1413  *  This routine is called whenever the user queries the status of
1414  *  the interface using ifconfig.
1415  *
1416  **********************************************************************/
1417 static void
1418 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1419 {
1420   struct adapter *adapter = iflib_get_softc(ctx);
1421   u_char fiber_type = IFM_1000_SX;
1422
1423   INIT_DEBUGOUT("em_if_media_status: begin");
1424
1425         iflib_admin_intr_deferred(ctx);
1426
1427         ifmr->ifm_status = IFM_AVALID;
1428         ifmr->ifm_active = IFM_ETHER;
1429
1430         if (!adapter->link_active) {
1431                 return;
1432         }
1433
1434         ifmr->ifm_status |= IFM_ACTIVE;
1435
1436         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
1437             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1438                 if (adapter->hw.mac.type == e1000_82545)
1439                         fiber_type = IFM_1000_LX;
1440                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1441         } else {
1442                 switch (adapter->link_speed) {
1443                 case 10:
1444                         ifmr->ifm_active |= IFM_10_T;
1445                         break;
1446                 case 100:
1447                         ifmr->ifm_active |= IFM_100_TX;
1448                         break;
1449                 case 1000:
1450                         ifmr->ifm_active |= IFM_1000_T;
1451                         break;
1452                 }
1453                 if (adapter->link_duplex == FULL_DUPLEX)
1454                         ifmr->ifm_active |= IFM_FDX;
1455                 else
1456                         ifmr->ifm_active |= IFM_HDX;
1457         }
1458 }
1459
1460 /*********************************************************************
1461  *
1462  *  Media Ioctl callback
1463  *
1464  *  This routine is called when the user changes speed/duplex using
1465  *  media/mediopt option with ifconfig.
1466  *
1467  **********************************************************************/
1468 static int
1469 em_if_media_change(if_ctx_t ctx)
1470 {
1471         struct adapter *adapter = iflib_get_softc(ctx);
1472         struct ifmedia  *ifm = iflib_get_media(ctx);
1473
1474         INIT_DEBUGOUT("em_if_media_change: begin");
1475
1476         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1477                 return (EINVAL);
1478
1479         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1480         case IFM_AUTO:
1481                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1482                 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1483                 break;
1484         case IFM_1000_LX:
1485         case IFM_1000_SX:
1486         case IFM_1000_T:
1487                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1488                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1489                 break;
1490         case IFM_100_TX:
1491                 adapter->hw.mac.autoneg = FALSE;
1492                 adapter->hw.phy.autoneg_advertised = 0;
1493                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1494                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1495                 else
1496                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1497                 break;
1498         case IFM_10_T:
1499                 adapter->hw.mac.autoneg = FALSE;
1500                 adapter->hw.phy.autoneg_advertised = 0;
1501                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1502                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1503                 else
1504                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1505                 break;
1506         default:
1507                 device_printf(adapter->dev, "Unsupported media type\n");
1508         }
1509
1510         em_if_init(ctx);
1511
1512         return (0);
1513 }
1514
1515 static int
1516 em_if_set_promisc(if_ctx_t ctx, int flags)
1517 {
1518         struct adapter *adapter = iflib_get_softc(ctx);
1519         u32             reg_rctl;
1520
1521         em_disable_promisc(ctx);
1522
1523         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1524
1525         if (flags & IFF_PROMISC) {
1526                 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1527                 /* Turn this on if you want to see bad packets */
1528                 if (em_debug_sbp)
1529                         reg_rctl |= E1000_RCTL_SBP;
1530                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1531         } else if (flags & IFF_ALLMULTI) {
1532                 reg_rctl |= E1000_RCTL_MPE;
1533                 reg_rctl &= ~E1000_RCTL_UPE;
1534                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1535         }
1536         return (0);
1537 }
1538
1539 static void
1540 em_disable_promisc(if_ctx_t ctx)
1541 {
1542         struct adapter *adapter = iflib_get_softc(ctx);
1543         struct ifnet *ifp = iflib_get_ifp(ctx);
1544         u32             reg_rctl;
1545         int             mcnt = 0;
1546
1547         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1548         reg_rctl &=  (~E1000_RCTL_UPE);
1549         if (if_getflags(ifp) & IFF_ALLMULTI)
1550                 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1551         else
1552                 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES);
1553         /* Don't disable if in MAX groups */
1554         if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1555                 reg_rctl &=  (~E1000_RCTL_MPE);
1556         reg_rctl &=  (~E1000_RCTL_SBP);
1557         E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1558 }
1559
1560
1561 /*********************************************************************
1562  *  Multicast Update
1563  *
1564  *  This routine is called whenever multicast address list is updated.
1565  *
1566  **********************************************************************/
1567
1568 static void
1569 em_if_multi_set(if_ctx_t ctx)
1570 {
1571         struct adapter *adapter = iflib_get_softc(ctx);
1572         struct ifnet *ifp = iflib_get_ifp(ctx);
1573         u32 reg_rctl = 0;
1574         u8  *mta; /* Multicast array memory */
1575         int mcnt = 0;
1576
1577         IOCTL_DEBUGOUT("em_set_multi: begin");
1578
1579         mta = adapter->mta;
1580         bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1581
1582         if (adapter->hw.mac.type == e1000_82542 &&
1583             adapter->hw.revision_id == E1000_REVISION_2) {
1584                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1585                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1586                         e1000_pci_clear_mwi(&adapter->hw);
1587                 reg_rctl |= E1000_RCTL_RST;
1588                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1589                 msec_delay(5);
1590         }
1591
1592         if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES);
1593
1594         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1595                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1596                 reg_rctl |= E1000_RCTL_MPE;
1597                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1598         } else
1599                 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
1600
1601         if (adapter->hw.mac.type == e1000_82542 &&
1602             adapter->hw.revision_id == E1000_REVISION_2) {
1603                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1604                 reg_rctl &= ~E1000_RCTL_RST;
1605                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1606                 msec_delay(5);
1607                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1608                         e1000_pci_set_mwi(&adapter->hw);
1609         }
1610 }
1611
1612
1613 /*********************************************************************
1614  *  Timer routine
1615  *
1616  *  This routine checks for link status and updates statistics.
1617  *
1618  **********************************************************************/
1619
1620 static void
1621 em_if_timer(if_ctx_t ctx, uint16_t qid)
1622 {
1623         struct adapter  *adapter = iflib_get_softc(ctx);
1624         struct em_rx_queue *que;
1625         int i;
1626         int trigger = 0;
1627
1628         if (qid != 0) {
1629                 /* XXX all this stuff is per-adapter */
1630                 return;
1631         }
1632
1633         em_if_update_admin_status(ctx);
1634         em_update_stats_counters(adapter);
1635
1636         /* Reset LAA into RAR[0] on 82571 */
1637         if ((adapter->hw.mac.type == e1000_82571) &&
1638             e1000_get_laa_state_82571(&adapter->hw))
1639                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1640
1641         if (adapter->hw.mac.type < em_mac_min)
1642                 lem_smartspeed(adapter);
1643
1644         /* Mask to use in the irq trigger */
1645         if (adapter->intr_type == IFLIB_INTR_MSIX) {
1646                 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++)
1647                         trigger |= que->eims;
1648         } else {
1649                 trigger = E1000_ICS_RXDMT0;
1650         }
1651 }
1652
1653
1654 static void
1655 em_if_update_admin_status(if_ctx_t ctx)
1656 {
1657         struct adapter *adapter = iflib_get_softc(ctx);
1658         struct e1000_hw *hw = &adapter->hw;
1659         struct ifnet *ifp = iflib_get_ifp(ctx);
1660         device_t dev = iflib_get_dev(ctx);
1661         u32 link_check = 0;
1662
1663         /* Get the cached link value or read phy for real */
1664         switch (hw->phy.media_type) {
1665         case e1000_media_type_copper:
1666                 if (hw->mac.get_link_status) {
1667                         if (hw->mac.type == e1000_pch_spt)
1668                                 msec_delay(50);
1669                         /* Do the work to read phy */
1670                         e1000_check_for_link(hw);
1671                         link_check = !hw->mac.get_link_status;
1672                         if (link_check) /* ESB2 fix */
1673                                 e1000_cfg_on_link_up(hw);
1674                 } else {
1675                         link_check = TRUE;
1676                 }
1677                 break;
1678         case e1000_media_type_fiber:
1679                 e1000_check_for_link(hw);
1680                 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1681                                  E1000_STATUS_LU);
1682                 break;
1683         case e1000_media_type_internal_serdes:
1684                 e1000_check_for_link(hw);
1685                 link_check = adapter->hw.mac.serdes_has_link;
1686                 break;
1687         default:
1688         case e1000_media_type_unknown:
1689                 break;
1690         }
1691
1692         /* Now check for a transition */
1693         if (link_check && (adapter->link_active == 0)) {
1694                 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
1695                     &adapter->link_duplex);
1696                 /* Check if we must disable SPEED_MODE bit on PCI-E */
1697                 if ((adapter->link_speed != SPEED_1000) &&
1698                     ((hw->mac.type == e1000_82571) ||
1699                     (hw->mac.type == e1000_82572))) {
1700                         int tarc0;
1701                         tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1702                         tarc0 &= ~TARC_SPEED_MODE_BIT;
1703                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1704                 }
1705                 if (bootverbose)
1706                         device_printf(dev, "Link is up %d Mbps %s\n",
1707                             adapter->link_speed,
1708                             ((adapter->link_duplex == FULL_DUPLEX) ?
1709                             "Full Duplex" : "Half Duplex"));
1710                 adapter->link_active = 1;
1711                 adapter->smartspeed = 0;
1712                 if_setbaudrate(ifp, adapter->link_speed * 1000000);
1713                 iflib_link_state_change(ctx, LINK_STATE_UP, ifp->if_baudrate);
1714                 printf("Link state changed to up\n");
1715         } else if (!link_check && (adapter->link_active == 1)) {
1716                 if_setbaudrate(ifp, 0);
1717                 adapter->link_speed = 0;
1718                 adapter->link_duplex = 0;
1719                 if (bootverbose)
1720                         device_printf(dev, "Link is Down\n");
1721                 adapter->link_active = 0;
1722                 iflib_link_state_change(ctx, LINK_STATE_DOWN, ifp->if_baudrate);
1723                 printf("link state changed to down\n");
1724         }
1725
1726         E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC);
1727 }
1728
1729 /*********************************************************************
1730  *
1731  *  This routine disables all traffic on the adapter by issuing a
1732  *  global reset on the MAC and deallocates TX/RX buffers.
1733  *
1734  *  This routine should always be called with BOTH the CORE
1735  *  and TX locks.
1736  **********************************************************************/
1737
1738 static void
1739 em_if_stop(if_ctx_t ctx)
1740 {
1741         struct adapter *adapter = iflib_get_softc(ctx);
1742
1743         INIT_DEBUGOUT("em_stop: begin");
1744
1745         e1000_reset_hw(&adapter->hw);
1746         if (adapter->hw.mac.type >= e1000_82544)
1747                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0);
1748
1749         e1000_led_off(&adapter->hw);
1750         e1000_cleanup_led(&adapter->hw);
1751 }
1752
1753
1754 /*********************************************************************
1755  *
1756  *  Determine hardware revision.
1757  *
1758  **********************************************************************/
1759 static void
1760 em_identify_hardware(if_ctx_t ctx)
1761 {
1762         device_t dev = iflib_get_dev(ctx);
1763         struct adapter *adapter = iflib_get_softc(ctx);
1764
1765         /* Make sure our PCI config space has the necessary stuff set */
1766         adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1767
1768         /* Save off the information about this board */
1769         adapter->hw.vendor_id = pci_get_vendor(dev);
1770         adapter->hw.device_id = pci_get_device(dev);
1771         adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1772         adapter->hw.subsystem_vendor_id =
1773             pci_read_config(dev, PCIR_SUBVEND_0, 2);
1774         adapter->hw.subsystem_device_id =
1775             pci_read_config(dev, PCIR_SUBDEV_0, 2);
1776
1777         /* Do Shared Code Init and Setup */
1778         if (e1000_set_mac_type(&adapter->hw)) {
1779                 device_printf(dev, "Setup init failure\n");
1780                 return;
1781         }
1782 }
1783
1784 static int
1785 em_allocate_pci_resources(if_ctx_t ctx)
1786 {
1787         struct adapter *adapter = iflib_get_softc(ctx);
1788         device_t        dev = iflib_get_dev(ctx);
1789         int             rid, val;
1790
1791         rid = PCIR_BAR(0);
1792         adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1793             &rid, RF_ACTIVE);
1794         if (adapter->memory == NULL) {
1795                 device_printf(dev, "Unable to allocate bus resource: memory\n");
1796                 return (ENXIO);
1797         }
1798         adapter->osdep.mem_bus_space_tag =
1799             rman_get_bustag(adapter->memory);
1800         adapter->osdep.mem_bus_space_handle =
1801             rman_get_bushandle(adapter->memory);
1802         adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle;
1803
1804         /* Only older adapters use IO mapping */
1805         if (adapter->hw.mac.type < em_mac_min &&
1806             adapter->hw.mac.type > e1000_82543) {
1807                 /* Figure our where our IO BAR is ? */
1808                 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1809                         val = pci_read_config(dev, rid, 4);
1810                         if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1811                                 adapter->io_rid = rid;
1812                                 break;
1813                         }
1814                         rid += 4;
1815                         /* check for 64bit BAR */
1816                         if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1817                                 rid += 4;
1818                 }
1819                 if (rid >= PCIR_CIS) {
1820                         device_printf(dev, "Unable to locate IO BAR\n");
1821                         return (ENXIO);
1822                 }
1823                 adapter->ioport = bus_alloc_resource_any(dev,
1824                     SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE);
1825                 if (adapter->ioport == NULL) {
1826                         device_printf(dev, "Unable to allocate bus resource: "
1827                             "ioport\n");
1828                         return (ENXIO);
1829                 }
1830                 adapter->hw.io_base = 0;
1831                 adapter->osdep.io_bus_space_tag =
1832                     rman_get_bustag(adapter->ioport);
1833                 adapter->osdep.io_bus_space_handle =
1834                     rman_get_bushandle(adapter->ioport);
1835         }
1836
1837         adapter->hw.back = &adapter->osdep;
1838
1839         return (0);
1840 }
1841
1842 /*********************************************************************
1843  *
1844  *  Setup the MSIX Interrupt handlers
1845  *
1846  **********************************************************************/
1847 static int
1848 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
1849 {
1850         struct adapter     *adapter = iflib_get_softc(ctx);
1851         struct em_rx_queue *rx_que = adapter->rx_queues;
1852         struct em_tx_queue *tx_que = adapter->tx_queues;
1853         int                error, rid, i, vector = 0;
1854         char buf[16];
1855
1856         /* First set up ring resources */
1857         for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) {
1858                 rid = vector +1;
1859                 snprintf(buf, sizeof(buf), "rxq%d", i);
1860                 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RX, em_msix_que, rx_que, rx_que->me, buf);
1861                 if (error) {
1862                         device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
1863                         adapter->rx_num_queues = i + 1;
1864                         goto fail;
1865                 }
1866
1867                 rx_que->msix =  vector;
1868
1869                 /*
1870                 ** Set the bit to enable interrupt
1871                 ** in E1000_IMS -- bits 20 and 21
1872                 ** are for RX0 and RX1, note this has
1873                 ** NOTHING to do with the MSIX vector
1874                 */
1875                 if (adapter->hw.mac.type == e1000_82574) {
1876                         rx_que->eims = 1 << (20 + i);
1877                         adapter->ims |= rx_que->eims;
1878                         adapter->ivars |= (8 | rx_que->msix) << (i * 4);
1879                 } else if (adapter->hw.mac.type == e1000_82575)
1880                         rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
1881                 else
1882                         rx_que->eims = 1 << vector;
1883         }
1884
1885         for (i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
1886                 rid = vector + 1;
1887                 snprintf(buf, sizeof(buf), "txq%d", i);
1888                 tx_que = &adapter->tx_queues[i];
1889                 iflib_softirq_alloc_generic(ctx, rid, IFLIB_INTR_TX, tx_que, tx_que->me, buf);
1890
1891                 tx_que->msix = vector;
1892
1893                   /*
1894                 ** Set the bit to enable interrupt
1895                 ** in E1000_IMS -- bits 22 and 23
1896                 ** are for TX0 and TX1, note this has
1897                 ** NOTHING to do with the MSIX vector
1898                 */
1899                 if (adapter->hw.mac.type < igb_mac_min) {
1900                         tx_que->eims = 1 << (22 + i);
1901                         adapter->ims |= tx_que->eims;
1902                         adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
1903                 } if (adapter->hw.mac.type == e1000_82575)
1904                         tx_que->eims = E1000_EICR_TX_QUEUE0 << (i %  adapter->tx_num_queues);
1905                 else
1906                         tx_que->eims = 1 << (i %  adapter->tx_num_queues);
1907         }
1908
1909         /* Link interrupt */
1910         rid = vector + 1;
1911         error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq");
1912
1913         if (error) {
1914                 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
1915                 goto fail;
1916         }
1917         adapter->linkvec = vector;
1918         if (adapter->hw.mac.type < igb_mac_min) {
1919                 adapter->ivars |=  (8 | vector) << 16;
1920                 adapter->ivars |= 0x80000000;
1921         }
1922         return (0);
1923  fail:
1924         iflib_irq_free(ctx, &adapter->irq);
1925         rx_que = adapter->rx_queues;
1926         for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++)
1927                 iflib_irq_free(ctx, &rx_que->que_irq);
1928         return (error);
1929 }
1930
1931 static void
1932 igb_configure_queues(struct adapter *adapter)
1933 {
1934         struct  e1000_hw        *hw = &adapter->hw;
1935         struct  em_rx_queue     *rx_que;
1936         struct  em_tx_queue    *tx_que;
1937         u32                     tmp, ivar = 0, newitr = 0;
1938
1939         /* First turn on RSS capability */
1940         if (adapter->hw.mac.type != e1000_82575)
1941                 E1000_WRITE_REG(hw, E1000_GPIE,
1942                     E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
1943                     E1000_GPIE_PBA | E1000_GPIE_NSICR);
1944
1945         /* Turn on MSIX */
1946         switch (adapter->hw.mac.type) {
1947         case e1000_82580:
1948         case e1000_i350:
1949         case e1000_i354:
1950         case e1000_i210:
1951         case e1000_i211:
1952         case e1000_vfadapt:
1953         case e1000_vfadapt_i350:
1954                 /* RX entries */
1955                 for (int i = 0; i < adapter->rx_num_queues; i++) {
1956                         u32 index = i >> 1;
1957                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
1958                         rx_que = &adapter->rx_queues[i];
1959                         if (i & 1) {
1960                                 ivar &= 0xFF00FFFF;
1961                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
1962                         } else {
1963                                 ivar &= 0xFFFFFF00;
1964                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
1965                         }
1966                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
1967                 }
1968                 /* TX entries */
1969                 for (int i = 0; i < adapter->tx_num_queues; i++) {
1970                         u32 index = i >> 1;
1971                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
1972                         tx_que = &adapter->tx_queues[i];
1973                         if (i & 1) {
1974                                 ivar &= 0x00FFFFFF;
1975                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
1976                         } else {
1977                                 ivar &= 0xFFFF00FF;
1978                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
1979                         }
1980                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
1981                         adapter->que_mask |= tx_que->eims;
1982                 }
1983
1984                 /* And for the link interrupt */
1985                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
1986                 adapter->link_mask = 1 << adapter->linkvec;
1987                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
1988                 break;
1989         case e1000_82576:
1990                 /* RX entries */
1991                 for (int i = 0; i < adapter->rx_num_queues; i++) {
1992                         u32 index = i & 0x7; /* Each IVAR has two entries */
1993                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
1994                         rx_que = &adapter->rx_queues[i];
1995                         if (i < 8) {
1996                                 ivar &= 0xFFFFFF00;
1997                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
1998                         } else {
1999                                 ivar &= 0xFF00FFFF;
2000                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2001                         }
2002                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2003                         adapter->que_mask |= rx_que->eims;
2004                 }
2005                 /* TX entries */
2006                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2007                         u32 index = i & 0x7; /* Each IVAR has two entries */
2008                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2009                         tx_que = &adapter->tx_queues[i];
2010                         if (i < 8) {
2011                                 ivar &= 0xFFFF00FF;
2012                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2013                         } else {
2014                                 ivar &= 0x00FFFFFF;
2015                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2016                         }
2017                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2018                         adapter->que_mask |= tx_que->eims;
2019                 }
2020
2021                 /* And for the link interrupt */
2022                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2023                 adapter->link_mask = 1 << adapter->linkvec;
2024                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2025                 break;
2026
2027         case e1000_82575:
2028                 /* enable MSI-X support*/
2029                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2030                 tmp |= E1000_CTRL_EXT_PBA_CLR;
2031                 /* Auto-Mask interrupts upon ICR read. */
2032                 tmp |= E1000_CTRL_EXT_EIAME;
2033                 tmp |= E1000_CTRL_EXT_IRCA;
2034                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2035
2036                 /* Queues */
2037                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2038                         rx_que = &adapter->rx_queues[i];
2039                         tmp = E1000_EICR_RX_QUEUE0 << i;
2040                         tmp |= E1000_EICR_TX_QUEUE0 << i;
2041                         rx_que->eims = tmp;
2042                         E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2043                             i, rx_que->eims);
2044                         adapter->que_mask |= rx_que->eims;
2045                 }
2046
2047                 /* Link */
2048                 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec),
2049                     E1000_EIMS_OTHER);
2050                 adapter->link_mask |= E1000_EIMS_OTHER;
2051         default:
2052                 break;
2053         }
2054
2055         /* Set the starting interrupt rate */
2056         if (em_max_interrupt_rate > 0)
2057                 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2058
2059         if (hw->mac.type == e1000_82575)
2060                 newitr |= newitr << 16;
2061         else
2062                 newitr |= E1000_EITR_CNT_IGNR;
2063
2064         for (int i = 0; i < adapter->rx_num_queues; i++) {
2065                 rx_que = &adapter->rx_queues[i];
2066                 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2067         }
2068
2069         return;
2070 }
2071
2072 static void
2073 em_free_pci_resources(if_ctx_t ctx)
2074 {
2075         struct adapter *adapter = iflib_get_softc(ctx);
2076         struct          em_rx_queue *que = adapter->rx_queues;
2077         device_t        dev = iflib_get_dev(ctx);
2078
2079         /* Release all msix queue resources */
2080         if (adapter->intr_type == IFLIB_INTR_MSIX)
2081                 iflib_irq_free(ctx, &adapter->irq);
2082
2083         for (int i = 0; i < adapter->rx_num_queues; i++, que++) {
2084                 iflib_irq_free(ctx, &que->que_irq);
2085         }
2086
2087
2088         /* First release all the interrupt resources */
2089         if (adapter->memory != NULL) {
2090                 bus_release_resource(dev, SYS_RES_MEMORY,
2091                                      PCIR_BAR(0), adapter->memory);
2092                 adapter->memory = NULL;
2093         }
2094
2095         if (adapter->flash != NULL) {
2096                 bus_release_resource(dev, SYS_RES_MEMORY,
2097                                      EM_FLASH, adapter->flash);
2098                 adapter->flash = NULL;
2099         }
2100         if (adapter->ioport != NULL)
2101                 bus_release_resource(dev, SYS_RES_IOPORT,
2102                     adapter->io_rid, adapter->ioport);
2103 }
2104
2105 /* Setup MSI or MSI/X */
2106 static int
2107 em_setup_msix(if_ctx_t ctx)
2108 {
2109         struct adapter *adapter = iflib_get_softc(ctx);
2110
2111         if (adapter->hw.mac.type == e1000_82574) {
2112                 em_enable_vectors_82574(ctx);
2113         }
2114         return (0);
2115 }
2116
2117 /*********************************************************************
2118  *
2119  *  Initialize the hardware to a configuration
2120  *  as specified by the adapter structure.
2121  *
2122  **********************************************************************/
2123
2124 static void
2125 lem_smartspeed(struct adapter *adapter)
2126 {
2127         u16 phy_tmp;
2128
2129         if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) ||
2130             adapter->hw.mac.autoneg == 0 ||
2131             (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2132                 return;
2133
2134         if (adapter->smartspeed == 0) {
2135                 /* If Master/Slave config fault is asserted twice,
2136                  * we assume back-to-back */
2137                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2138                 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2139                         return;
2140                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2141                 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2142                         e1000_read_phy_reg(&adapter->hw,
2143                             PHY_1000T_CTRL, &phy_tmp);
2144                         if(phy_tmp & CR_1000T_MS_ENABLE) {
2145                                 phy_tmp &= ~CR_1000T_MS_ENABLE;
2146                                 e1000_write_phy_reg(&adapter->hw,
2147                                     PHY_1000T_CTRL, phy_tmp);
2148                                 adapter->smartspeed++;
2149                                 if(adapter->hw.mac.autoneg &&
2150                                    !e1000_copper_link_autoneg(&adapter->hw) &&
2151                                    !e1000_read_phy_reg(&adapter->hw,
2152                                     PHY_CONTROL, &phy_tmp)) {
2153                                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2154                                                     MII_CR_RESTART_AUTO_NEG);
2155                                         e1000_write_phy_reg(&adapter->hw,
2156                                             PHY_CONTROL, phy_tmp);
2157                                 }
2158                         }
2159                 }
2160                 return;
2161         } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2162                 /* If still no link, perhaps using 2/3 pair cable */
2163                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2164                 phy_tmp |= CR_1000T_MS_ENABLE;
2165                 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2166                 if(adapter->hw.mac.autoneg &&
2167                    !e1000_copper_link_autoneg(&adapter->hw) &&
2168                    !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2169                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2170                                     MII_CR_RESTART_AUTO_NEG);
2171                         e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2172                 }
2173         }
2174         /* Restart process after EM_SMARTSPEED_MAX iterations */
2175         if(adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2176                 adapter->smartspeed = 0;
2177 }
2178
2179
2180 static void
2181 em_reset(if_ctx_t ctx)
2182 {
2183         device_t        dev = iflib_get_dev(ctx);
2184         struct adapter *adapter = iflib_get_softc(ctx);
2185         struct ifnet *ifp = iflib_get_ifp(ctx);
2186         struct e1000_hw *hw = &adapter->hw;
2187         u16             rx_buffer_size;
2188         u32             pba;
2189
2190         INIT_DEBUGOUT("em_reset: begin");
2191
2192         /* Set up smart power down as default off on newer adapters. */
2193         if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2194             hw->mac.type == e1000_82572)) {
2195                 u16 phy_tmp = 0;
2196
2197                 /* Speed up time to link by disabling smart power down. */
2198                 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2199                 phy_tmp &= ~IGP02E1000_PM_SPD;
2200                 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2201         }
2202
2203         /*
2204          * Packet Buffer Allocation (PBA)
2205          * Writing PBA sets the receive portion of the buffer
2206          * the remainder is used for the transmit buffer.
2207          */
2208         switch (hw->mac.type) {
2209         /* Total Packet Buffer on these is 48K */
2210         case e1000_82571:
2211         case e1000_82572:
2212         case e1000_80003es2lan:
2213                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2214                 break;
2215         case e1000_82573: /* 82573: Total Packet Buffer is 32K */
2216                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2217                 break;
2218         case e1000_82574:
2219         case e1000_82583:
2220                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2221                 break;
2222         case e1000_ich8lan:
2223                 pba = E1000_PBA_8K;
2224                 break;
2225         case e1000_ich9lan:
2226         case e1000_ich10lan:
2227                 /* Boost Receive side for jumbo frames */
2228                 if (adapter->hw.mac.max_frame_size > 4096)
2229                         pba = E1000_PBA_14K;
2230                 else
2231                         pba = E1000_PBA_10K;
2232                 break;
2233         case e1000_pchlan:
2234         case e1000_pch2lan:
2235         case e1000_pch_lpt:
2236         case e1000_pch_spt:
2237                 pba = E1000_PBA_26K;
2238                 break;
2239         default:
2240                 if (adapter->hw.mac.max_frame_size > 8192)
2241                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2242                 else
2243                         pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2244         }
2245         E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
2246
2247         /*
2248          * These parameters control the automatic generation (Tx) and
2249          * response (Rx) to Ethernet PAUSE frames.
2250          * - High water mark should allow for at least two frames to be
2251          *   received after sending an XOFF.
2252          * - Low water mark works best when it is very near the high water mark.
2253          *   This allows the receiver to restart by sending XON when it has
2254          *   drained a bit. Here we use an arbitrary value of 1500 which will
2255          *   restart after one full frame is pulled from the buffer. There
2256          *   could be several smaller frames in the buffer and if so they will
2257          *   not trigger the XON until their total number reduces the buffer
2258          *   by 1500.
2259          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2260          */
2261         rx_buffer_size = ((E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10 );
2262         hw->fc.high_water = rx_buffer_size -
2263             roundup2(adapter->hw.mac.max_frame_size, 1024);
2264         hw->fc.low_water = hw->fc.high_water - 1500;
2265
2266         if (adapter->fc) /* locally set flow control value? */
2267                 hw->fc.requested_mode = adapter->fc;
2268         else
2269                 hw->fc.requested_mode = e1000_fc_full;
2270
2271         if (hw->mac.type == e1000_80003es2lan)
2272                 hw->fc.pause_time = 0xFFFF;
2273         else
2274                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
2275
2276         hw->fc.send_xon = TRUE;
2277
2278         /* Device specific overrides/settings */
2279         switch (hw->mac.type) {
2280         case e1000_pchlan:
2281                 /* Workaround: no TX flow ctrl for PCH */
2282                 hw->fc.requested_mode = e1000_fc_rx_pause;
2283                 hw->fc.pause_time = 0xFFFF; /* override */
2284                 if (if_getmtu(ifp) > ETHERMTU) {
2285                         hw->fc.high_water = 0x3500;
2286                         hw->fc.low_water = 0x1500;
2287                 } else {
2288                         hw->fc.high_water = 0x5000;
2289                         hw->fc.low_water = 0x3000;
2290                 }
2291                 hw->fc.refresh_time = 0x1000;
2292                 break;
2293         case e1000_pch2lan:
2294         case e1000_pch_lpt:
2295         case e1000_pch_spt:
2296                 hw->fc.high_water = 0x5C20;
2297                 hw->fc.low_water = 0x5048;
2298                 hw->fc.pause_time = 0x0650;
2299                 hw->fc.refresh_time = 0x0400;
2300                 /* Jumbos need adjusted PBA */
2301                 if (if_getmtu(ifp) > ETHERMTU)
2302                         E1000_WRITE_REG(hw, E1000_PBA, 12);
2303                 else
2304                         E1000_WRITE_REG(hw, E1000_PBA, 26);
2305                 break;
2306         case e1000_ich9lan:
2307         case e1000_ich10lan:
2308                 if (if_getmtu(ifp) > ETHERMTU) {
2309                         hw->fc.high_water = 0x2800;
2310                         hw->fc.low_water = hw->fc.high_water - 8;
2311                         break;
2312                 }
2313                 /* else fall thru */
2314         default:
2315                 if (hw->mac.type == e1000_80003es2lan)
2316                         hw->fc.pause_time = 0xFFFF;
2317                 break;
2318         }
2319
2320         /* Issue a global reset */
2321         e1000_reset_hw(hw);
2322         E1000_WRITE_REG(hw, E1000_WUFC, 0);
2323         em_disable_aspm(adapter);
2324         /* and a re-init */
2325         if (e1000_init_hw(hw) < 0) {
2326                 device_printf(dev, "Hardware Initialization Failed\n");
2327                 return;
2328         }
2329
2330         E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2331         e1000_get_phy_info(hw);
2332         e1000_check_for_link(hw);
2333 }
2334
2335 #define RSSKEYLEN 10
2336 static void
2337 em_initialize_rss_mapping(struct adapter *adapter)
2338 {
2339         uint8_t  rss_key[4 * RSSKEYLEN];
2340         uint32_t reta = 0;
2341         struct e1000_hw *hw = &adapter->hw;
2342         int i;
2343
2344         /*
2345          * Configure RSS key
2346          */
2347         arc4rand(rss_key, sizeof(rss_key), 0);
2348         for (i = 0; i < RSSKEYLEN; ++i) {
2349                 uint32_t rssrk = 0;
2350
2351                 rssrk = EM_RSSRK_VAL(rss_key, i);
2352                 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2353         }
2354
2355         /*
2356          * Configure RSS redirect table in following fashion:
2357          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2358          */
2359         for (i = 0; i < sizeof(reta); ++i) {
2360                 uint32_t q;
2361
2362                 q = (i % adapter->rx_num_queues) << 7;
2363                 reta |= q << (8 * i);
2364         }
2365
2366         for (i = 0; i < 32; ++i)
2367                 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2368
2369         E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2370                         E1000_MRQC_RSS_FIELD_IPV4_TCP |
2371                         E1000_MRQC_RSS_FIELD_IPV4 |
2372                         E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2373                         E1000_MRQC_RSS_FIELD_IPV6_EX |
2374                         E1000_MRQC_RSS_FIELD_IPV6);
2375
2376 }
2377
2378 static void
2379 igb_initialize_rss_mapping(struct adapter *adapter)
2380 {
2381         struct e1000_hw *hw = &adapter->hw;
2382         int i;
2383         int queue_id;
2384         u32 reta;
2385         u32 rss_key[10], mrqc, shift = 0;
2386
2387         /* XXX? */
2388         if (adapter->hw.mac.type == e1000_82575)
2389                 shift = 6;
2390
2391         /*
2392          * The redirection table controls which destination
2393          * queue each bucket redirects traffic to.
2394          * Each DWORD represents four queues, with the LSB
2395          * being the first queue in the DWORD.
2396          *
2397          * This just allocates buckets to queues using round-robin
2398          * allocation.
2399          *
2400          * NOTE: It Just Happens to line up with the default
2401          * RSS allocation method.
2402          */
2403
2404         /* Warning FM follows */
2405         reta = 0;
2406         for (i = 0; i < 128; i++) {
2407 #ifdef  RSS
2408                 queue_id = rss_get_indirection_to_bucket(i);
2409                 /*
2410                  * If we have more queues than buckets, we'll
2411                  * end up mapping buckets to a subset of the
2412                  * queues.
2413                  *
2414                  * If we have more buckets than queues, we'll
2415                  * end up instead assigning multiple buckets
2416                  * to queues.
2417                  *
2418                  * Both are suboptimal, but we need to handle
2419                  * the case so we don't go out of bounds
2420                  * indexing arrays and such.
2421                  */
2422                 queue_id = queue_id % adapter->rx_num_queues;
2423 #else
2424                 queue_id = (i % adapter->rx_num_queues);
2425 #endif
2426                 /* Adjust if required */
2427                 queue_id = queue_id << shift;
2428
2429                 /*
2430                  * The low 8 bits are for hash value (n+0);
2431                  * The next 8 bits are for hash value (n+1), etc.
2432                  */
2433                 reta = reta >> 8;
2434                 reta = reta | ( ((uint32_t) queue_id) << 24);
2435                 if ((i & 3) == 3) {
2436                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2437                         reta = 0;
2438                 }
2439         }
2440
2441         /* Now fill in hash table */
2442
2443         /*
2444          * MRQC: Multiple Receive Queues Command
2445          * Set queuing to RSS control, number depends on the device.
2446          */
2447         mrqc = E1000_MRQC_ENABLE_RSS_8Q;
2448
2449 #ifdef  RSS
2450         /* XXX ew typecasting */
2451         rss_getkey((uint8_t *) &rss_key);
2452 #else
2453         arc4rand(&rss_key, sizeof(rss_key), 0);
2454 #endif
2455         for (i = 0; i < 10; i++)
2456                 E1000_WRITE_REG_ARRAY(hw,
2457                     E1000_RSSRK(0), i, rss_key[i]);
2458
2459         /*
2460          * Configure the RSS fields to hash upon.
2461          */
2462         mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2463             E1000_MRQC_RSS_FIELD_IPV4_TCP);
2464         mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2465             E1000_MRQC_RSS_FIELD_IPV6_TCP);
2466         mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2467             E1000_MRQC_RSS_FIELD_IPV6_UDP);
2468         mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2469             E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2470
2471         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2472 }
2473
2474 /*********************************************************************
2475  *
2476  *  Setup networking device structure and register an interface.
2477  *
2478  **********************************************************************/
2479 static int
2480 em_setup_interface(if_ctx_t ctx)
2481 {
2482         struct ifnet *ifp = iflib_get_ifp(ctx);
2483         struct adapter *adapter = iflib_get_softc(ctx);
2484         if_softc_ctx_t scctx = adapter->shared;
2485         uint64_t cap = 0;
2486
2487         INIT_DEBUGOUT("em_setup_interface: begin");
2488
2489         /* TSO parameters */
2490         if_sethwtsomax(ifp, IP_MAXPACKET);
2491         /* Take m_pullup(9)'s in em_xmit() w/ TSO into acount. */
2492         if_sethwtsomaxsegcount(ifp, EM_MAX_SCATTER - 5);
2493         if_sethwtsomaxsegsize(ifp, EM_TSO_SEG_SIZE);
2494
2495         /* Single Queue */
2496         if (adapter->tx_num_queues == 1) {
2497           if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
2498           if_setsendqready(ifp);
2499         }
2500
2501         cap = IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4;
2502         cap |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU;
2503
2504         /*
2505          * Tell the upper layer(s) we
2506          * support full VLAN capability
2507          */
2508         if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
2509         if_setcapabilitiesbit(ifp, cap, 0);
2510
2511         /*
2512         ** Don't turn this on by default, if vlans are
2513         ** created on another pseudo device (eg. lagg)
2514         ** then vlan events are not passed thru, breaking
2515         ** operation, but with HW FILTER off it works. If
2516         ** using vlans directly on the em driver you can
2517         ** enable this and get full hardware tag filtering.
2518         */
2519         if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWFILTER,0);
2520
2521         /* Enable only WOL MAGIC by default */
2522         if (adapter->wol) {
2523                 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC,
2524                              IFCAP_WOL_MCAST| IFCAP_WOL_UCAST);
2525         } else {
2526                 if_setcapenablebit(ifp, 0, IFCAP_WOL_MAGIC |
2527                              IFCAP_WOL_MCAST| IFCAP_WOL_UCAST);
2528         }
2529
2530         /*
2531          * Specify the media types supported by this adapter and register
2532          * callbacks to update media and link information
2533          */
2534         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
2535             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
2536                 u_char fiber_type = IFM_1000_SX;        /* default type */
2537
2538                 if (adapter->hw.mac.type == e1000_82545)
2539                         fiber_type = IFM_1000_LX;
2540                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
2541                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2542         } else {
2543                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2544                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2545                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2546                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2547                 if (adapter->hw.phy.type != e1000_phy_ife) {
2548                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2549                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2550                 }
2551         }
2552         ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2553         ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO);
2554         return (0);
2555 }
2556
2557 static int
2558 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
2559 {
2560         struct adapter *adapter = iflib_get_softc(ctx);
2561         if_softc_ctx_t scctx = adapter->shared;
2562         int error = E1000_SUCCESS;
2563         struct em_tx_queue *que;
2564         int i;
2565
2566         MPASS(adapter->tx_num_queues > 0);
2567         MPASS(adapter->tx_num_queues == ntxqsets);
2568
2569         /* First allocate the top level queue structs */
2570         if (!(adapter->tx_queues =
2571             (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
2572             adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2573                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2574                 return(ENOMEM);
2575         }
2576
2577         for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) {
2578              /* Set up some basics */
2579              struct tx_ring *txr = &que->txr;
2580              txr->adapter = que->adapter = adapter;
2581              txr->que = que;
2582              que->me = txr->me =  i;
2583
2584              /* Allocate transmit buffer memory */
2585           if (!(txr->tx_buffers = (struct em_txbuffer *) malloc(sizeof(struct em_txbuffer) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2586                device_printf(iflib_get_dev(ctx), "failed to allocate tx_buffer memory\n");
2587                error = ENOMEM;
2588                goto fail;
2589           }
2590
2591           /* get the virtual and physical address of the hardware queues */
2592           txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
2593           txr->tx_paddr = paddrs[i*ntxqs];
2594
2595         }
2596
2597         device_printf(iflib_get_dev(ctx), "allocated for %d tx_queues\n", adapter->tx_num_queues);
2598         return (0);
2599  fail:
2600         em_if_queues_free(ctx);
2601         return (error);
2602 }
2603
2604 static int
2605 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
2606 {
2607         struct adapter *adapter = iflib_get_softc(ctx);
2608         int error = E1000_SUCCESS;
2609         struct em_rx_queue *que;
2610         int i;
2611
2612         MPASS(adapter->rx_num_queues > 0);
2613         MPASS(adapter->rx_num_queues == nrxqsets);
2614
2615         /* First allocate the top level queue structs */
2616         if (!(adapter->rx_queues =
2617             (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
2618             adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2619                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2620                 error = ENOMEM;
2621                 goto fail;
2622         }
2623
2624         for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) {
2625                 /* Set up some basics */
2626                 struct rx_ring *rxr = &que->rxr;
2627                 rxr->adapter = que->adapter = adapter;
2628                 rxr->que = que;
2629                 que->me = rxr->me =  i;
2630
2631                 /* get the virtual and physical address of the hardware queues */
2632                 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
2633                 rxr->rx_paddr = paddrs[i*nrxqs];
2634         }
2635
2636         device_printf(iflib_get_dev(ctx), "allocated for %d rx_queues\n", adapter->rx_num_queues);
2637
2638         return (0);
2639 fail:
2640         em_if_queues_free(ctx);
2641         return (error);
2642 }
2643
2644 static void
2645 em_if_queues_free(if_ctx_t ctx)
2646 {
2647         struct adapter *adapter = iflib_get_softc(ctx);
2648         struct em_tx_queue *tx_que = adapter->tx_queues;
2649         struct em_rx_queue *rx_que = adapter->rx_queues;
2650
2651         if (tx_que != NULL) {
2652           for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
2653                 struct tx_ring *txr = &tx_que->txr;
2654                 if (txr->tx_buffers == NULL)
2655                         break;
2656
2657                 free(txr->tx_buffers, M_DEVBUF);
2658                 txr->tx_buffers = NULL;
2659           }
2660           free(adapter->tx_queues, M_DEVBUF);
2661           adapter->tx_queues = NULL;
2662         }
2663
2664         if (rx_que != NULL) {
2665           free(adapter->rx_queues, M_DEVBUF);
2666           adapter->rx_queues = NULL;
2667         }
2668
2669         em_release_hw_control(adapter);
2670
2671         if (adapter->mta != NULL) {
2672                 free(adapter->mta, M_DEVBUF);
2673         }
2674 }
2675
2676 /*********************************************************************
2677  *
2678  *  Enable transmit unit.
2679  *
2680  **********************************************************************/
2681 static void
2682 em_initialize_transmit_unit(if_ctx_t ctx)
2683 {
2684         struct adapter *adapter = iflib_get_softc(ctx);
2685         if_softc_ctx_t scctx = adapter->shared;
2686         struct em_tx_queue *que;
2687         struct tx_ring  *txr;
2688         struct e1000_hw *hw = &adapter->hw;
2689         u32 tctl, txdctl = 0, tarc, tipg = 0;
2690
2691          INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
2692
2693         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
2694                 u64 bus_addr;
2695                 caddr_t offp, endp;
2696
2697                 que = &adapter->tx_queues[i];
2698                 txr = &que->txr;
2699                 bus_addr = txr->tx_paddr;
2700
2701                 /*Enable all queues */
2702                 em_init_tx_ring(que);
2703
2704                 /* Clear checksum offload context. */
2705                 offp = (caddr_t)&txr->csum_flags;
2706                 endp = (caddr_t)(txr + 1);
2707                 bzero(offp, endp - offp);
2708
2709                 /* Base and Len of TX Ring */
2710                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
2711                     scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
2712                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
2713                     (u32)(bus_addr >> 32));
2714                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
2715                     (u32)bus_addr);
2716                 /* Init the HEAD/TAIL indices */
2717                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
2718                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
2719
2720                 HW_DEBUGOUT2("Base = %x, Length = %x\n",
2721                     E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)),
2722                     E1000_READ_REG(&adapter->hw, E1000_TDLEN(i)));
2723
2724                 txdctl = 0; /* clear txdctl */
2725                 txdctl |= 0x1f; /* PTHRESH */
2726                 txdctl |= 1 << 8; /* HTHRESH */
2727                 txdctl |= 1 << 16;/* WTHRESH */
2728                 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
2729                 txdctl |= E1000_TXDCTL_GRAN;
2730                 txdctl |= 1 << 25; /* LWTHRESH */
2731
2732                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
2733         }
2734
2735         /* Set the default values for the Tx Inter Packet Gap timer */
2736         switch (adapter->hw.mac.type) {
2737         case e1000_80003es2lan:
2738                 tipg = DEFAULT_82543_TIPG_IPGR1;
2739                 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2740                     E1000_TIPG_IPGR2_SHIFT;
2741                 break;
2742         case e1000_82542:
2743                 tipg = DEFAULT_82542_TIPG_IPGT;
2744                 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2745                 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2746                 break;
2747         default:
2748                 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
2749                     (adapter->hw.phy.media_type ==
2750                     e1000_media_type_internal_serdes))
2751                         tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2752                 else
2753                         tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2754                 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2755                 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2756         }
2757
2758         E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
2759         E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value);
2760
2761         if(adapter->hw.mac.type >= e1000_82540)
2762                 E1000_WRITE_REG(&adapter->hw, E1000_TADV,
2763                     adapter->tx_abs_int_delay.value);
2764
2765         if ((adapter->hw.mac.type == e1000_82571) ||
2766             (adapter->hw.mac.type == e1000_82572)) {
2767                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2768                 tarc |= TARC_SPEED_MODE_BIT;
2769                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2770         } else if (adapter->hw.mac.type == e1000_80003es2lan) {
2771                 /* errata: program both queues to unweighted RR */
2772                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2773                 tarc |= 1;
2774                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2775                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
2776                 tarc |= 1;
2777                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
2778         } else if (adapter->hw.mac.type == e1000_82574) {
2779                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2780                 tarc |= TARC_ERRATA_BIT;
2781                 if ( adapter->tx_num_queues > 1) {
2782                         tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
2783                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2784                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
2785                 } else
2786                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2787         }
2788
2789         if (adapter->tx_int_delay.value > 0)
2790                 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2791
2792         /* Program the Transmit Control Register */
2793         tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
2794         tctl &= ~E1000_TCTL_CT;
2795         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2796                    (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
2797
2798         if (adapter->hw.mac.type >= e1000_82571)
2799                 tctl |= E1000_TCTL_MULR;
2800
2801         /* This write will effectively turn on the transmit unit. */
2802         E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
2803
2804         if (hw->mac.type == e1000_pch_spt) {
2805                 u32 reg;
2806                 reg = E1000_READ_REG(hw, E1000_IOSFPC);
2807                 reg |= E1000_RCTL_RDMTS_HEX;
2808                 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
2809                 reg = E1000_READ_REG(hw, E1000_TARC(0));
2810                 reg |= E1000_TARC0_CB_MULTIQ_3_REQ;
2811                 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
2812         }
2813 }
2814
2815 /*********************************************************************
2816  *
2817  *  Enable receive unit.
2818  *
2819  **********************************************************************/
2820
2821 static void
2822 em_initialize_receive_unit(if_ctx_t ctx)
2823 {
2824         struct adapter *adapter = iflib_get_softc(ctx);
2825         if_softc_ctx_t scctx = adapter->shared;
2826         struct ifnet *ifp = iflib_get_ifp(ctx);
2827         struct e1000_hw *hw = &adapter->hw;
2828         struct em_rx_queue *que;
2829         int i;
2830         u32     rctl, rxcsum, rfctl;
2831
2832         INIT_DEBUGOUT("em_initialize_receive_units: begin");
2833
2834         /*
2835          * Make sure receives are disabled while setting
2836          * up the descriptor ring
2837          */
2838         rctl = E1000_READ_REG(hw, E1000_RCTL);
2839         /* Do not disable if ever enabled on this hardware */
2840         if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
2841                 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2842
2843         /* Setup the Receive Control Register */
2844         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2845         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
2846             E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
2847             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2848
2849         /* Do not store bad packets */
2850         rctl &= ~E1000_RCTL_SBP;
2851
2852         /* Enable Long Packet receive */
2853         if (if_getmtu(ifp) > ETHERMTU)
2854                 rctl |= E1000_RCTL_LPE;
2855         else
2856                 rctl &= ~E1000_RCTL_LPE;
2857
2858         /* Strip the CRC */
2859         if (!em_disable_crc_stripping)
2860                 rctl |= E1000_RCTL_SECRC;
2861
2862         if (adapter->hw.mac.type >= e1000_82540) {
2863                 E1000_WRITE_REG(&adapter->hw, E1000_RADV,
2864                                 adapter->rx_abs_int_delay.value);
2865
2866                 /*
2867                  * Set the interrupt throttling rate. Value is calculated
2868                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
2869                  */
2870                 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
2871         }
2872         E1000_WRITE_REG(&adapter->hw, E1000_RDTR,
2873             adapter->rx_int_delay.value);
2874
2875         /* Use extended rx descriptor formats */
2876         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2877         rfctl |= E1000_RFCTL_EXTEN;
2878         /*
2879         ** When using MSIX interrupts we need to throttle
2880         ** using the EITR register (82574 only)
2881         */
2882         if (hw->mac.type == e1000_82574) {
2883                 for (int i = 0; i < 4; i++)
2884                         E1000_WRITE_REG(hw, E1000_EITR_82574(i),
2885                             DEFAULT_ITR);
2886                 /* Disable accelerated acknowledge */
2887                 rfctl |= E1000_RFCTL_ACK_DIS;
2888         }
2889         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2890
2891         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2892         if (if_getcapenable(ifp) & IFCAP_RXCSUM &&
2893             adapter->hw.mac.type >= e1000_82543) {
2894                 if (adapter->tx_num_queues > 1) {
2895                         if (adapter->hw.mac.type >= igb_mac_min) {
2896                                 rxcsum |= E1000_RXCSUM_PCSD;
2897                                 if (hw->mac.type != e1000_82575)
2898                                         rxcsum |= E1000_RXCSUM_CRCOFL;
2899                         } else
2900                                 rxcsum |= E1000_RXCSUM_TUOFL |
2901                                         E1000_RXCSUM_IPOFL |
2902                                         E1000_RXCSUM_PCSD;
2903                 } else {
2904                         if (adapter->hw.mac.type >= igb_mac_min)
2905                                 rxcsum |= E1000_RXCSUM_IPPCSE;
2906                         else
2907                                 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
2908                         if (adapter->hw.mac.type > e1000_82575)
2909                                 rxcsum |= E1000_RXCSUM_CRCOFL;
2910                 }
2911         } else
2912                 rxcsum &= ~E1000_RXCSUM_TUOFL;
2913
2914         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2915
2916         if (adapter->rx_num_queues > 1) {
2917                 if (adapter->hw.mac.type >= igb_mac_min)
2918                         igb_initialize_rss_mapping(adapter);
2919                 else
2920                         em_initialize_rss_mapping(adapter);
2921         }
2922
2923         /*
2924         ** XXX TEMPORARY WORKAROUND: on some systems with 82573
2925         ** long latencies are observed, like Lenovo X60. This
2926         ** change eliminates the problem, but since having positive
2927         ** values in RDTR is a known source of problems on other
2928         ** platforms another solution is being sought.
2929         */
2930         if (hw->mac.type == e1000_82573)
2931                 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
2932
2933         for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
2934                 struct rx_ring *rxr = &que->rxr;
2935                 /* Setup the Base and Length of the Rx Descriptor Ring */
2936                 u64 bus_addr = rxr->rx_paddr;
2937 #if 0
2938                 u32 rdt = adapter->rx_num_queues -1;  /* default */
2939 #endif
2940
2941                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2942                     scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
2943                 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
2944                 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
2945                 /* Setup the Head and Tail Descriptor Pointers */
2946                 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
2947                 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
2948         }
2949
2950         /*
2951          * Set PTHRESH for improved jumbo performance
2952          * According to 10.2.5.11 of Intel 82574 Datasheet,
2953          * RXDCTL(1) is written whenever RXDCTL(0) is written.
2954          * Only write to RXDCTL(1) if there is a need for different
2955          * settings.
2956          */
2957
2958         if (((adapter->hw.mac.type == e1000_ich9lan) ||
2959             (adapter->hw.mac.type == e1000_pch2lan) ||
2960             (adapter->hw.mac.type == e1000_ich10lan)) &&
2961             (if_getmtu(ifp) > ETHERMTU)) {
2962                 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
2963                 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
2964         } else if (adapter->hw.mac.type == e1000_82574) {
2965                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2966                         u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2967                         rxdctl |= 0x20; /* PTHRESH */
2968                         rxdctl |= 4 << 8; /* HTHRESH */
2969                         rxdctl |= 4 << 16;/* WTHRESH */
2970                         rxdctl |= 1 << 24; /* Switch to granularity */
2971                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2972                 }
2973         } else if (adapter->hw.mac.type >= igb_mac_min) {
2974                 u32 psize, srrctl = 0;
2975
2976                 if (ifp->if_mtu > ETHERMTU) {
2977                         rctl |= E1000_RCTL_LPE;
2978
2979                         /* Set maximum packet len */
2980                         psize = scctx->isc_max_frame_size;
2981                         if (psize <= 4096) {
2982                                 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2983                                 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2984                         } else if (psize > 4096) {
2985                                 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2986                                 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2987                         }
2988
2989                         /* are we on a vlan? */
2990                         if (ifp->if_vlantrunk != NULL)
2991                                 psize += VLAN_TAG_SIZE;
2992                         E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2993                 } else {
2994                         rctl &= ~E1000_RCTL_LPE;
2995                         srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2996                         rctl |= E1000_RCTL_SZ_2048;
2997                 }
2998
2999                 /*
3000                  * If TX flow control is disabled and there's >1 queue defined,
3001                  * enable DROP.
3002                  *
3003                  * This drops frames rather than hanging the RX MAC for all queues.
3004                  */
3005                 if ((adapter->rx_num_queues > 1) &&
3006                     (adapter->fc == e1000_fc_none ||
3007                      adapter->fc == e1000_fc_rx_pause)) {
3008                         srrctl |= E1000_SRRCTL_DROP_EN;
3009                 }
3010                         /* Setup the Base and Length of the Rx Descriptor Rings */
3011                 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3012                         struct rx_ring *rxr = &que->rxr;
3013                         u64 bus_addr = rxr->rx_paddr;
3014                         u32 rxdctl;
3015
3016 #ifdef notyet
3017                         /* Configure for header split? -- ignore for now */
3018                         rxr->hdr_split = igb_header_split;
3019 #else
3020                         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3021 #endif
3022
3023
3024                         E1000_WRITE_REG(hw, E1000_RDLEN(i),
3025                                         scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3026                         E1000_WRITE_REG(hw, E1000_RDBAH(i),
3027                                         (uint32_t)(bus_addr >> 32));
3028                         E1000_WRITE_REG(hw, E1000_RDBAL(i),
3029                                         (uint32_t)bus_addr);
3030                         E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3031                         /* Enable this Queue */
3032                         rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3033                         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3034                         rxdctl &= 0xFFF00000;
3035                         rxdctl |= IGB_RX_PTHRESH;
3036                         rxdctl |= IGB_RX_HTHRESH << 8;
3037                         rxdctl |= IGB_RX_WTHRESH << 16;
3038                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3039                 }
3040         }
3041         if (adapter->hw.mac.type >= e1000_pch2lan) {
3042                 if (if_getmtu(ifp) > ETHERMTU)
3043                         e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
3044                 else
3045                         e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
3046         }
3047
3048         /* Make sure VLAN Filters are off */
3049         rctl &= ~E1000_RCTL_VFE;
3050
3051         if (adapter->rx_mbuf_sz == MCLBYTES)
3052                 rctl |= E1000_RCTL_SZ_2048;
3053         else if (adapter->rx_mbuf_sz == MJUMPAGESIZE)
3054                 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3055         else if (adapter->rx_mbuf_sz > MJUMPAGESIZE)
3056                 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3057
3058         /* ensure we clear use DTYPE of 00 here */
3059         rctl &= ~0x00000C00;
3060         /* Write out the settings */
3061         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3062
3063         return;
3064 }
3065
3066 static void
3067 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3068 {
3069         struct adapter  *adapter = iflib_get_softc(ctx);
3070         u32             index, bit;
3071
3072         index = (vtag >> 5) & 0x7F;
3073         bit = vtag & 0x1F;
3074         adapter->shadow_vfta[index] |= (1 << bit);
3075         ++adapter->num_vlans;
3076 }
3077
3078 static void
3079 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3080 {
3081         struct adapter  *adapter = iflib_get_softc(ctx);
3082         u32             index, bit;
3083
3084         index = (vtag >> 5) & 0x7F;
3085         bit = vtag & 0x1F;
3086         adapter->shadow_vfta[index] &= ~(1 << bit);
3087         --adapter->num_vlans;
3088 }
3089
3090 static void
3091 em_setup_vlan_hw_support(struct adapter *adapter)
3092 {
3093         struct e1000_hw *hw = &adapter->hw;
3094         u32             reg;
3095
3096         /*
3097         ** We get here thru init_locked, meaning
3098         ** a soft reset, this has already cleared
3099         ** the VFTA and other state, so if there
3100         ** have been no vlan's registered do nothing.
3101         */
3102         if (adapter->num_vlans == 0)
3103                 return;
3104
3105         /*
3106         ** A soft reset zero's out the VFTA, so
3107         ** we need to repopulate it now.
3108         */
3109         for (int i = 0; i < EM_VFTA_SIZE; i++)
3110                 if (adapter->shadow_vfta[i] != 0)
3111                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
3112                             i, adapter->shadow_vfta[i]);
3113
3114         reg = E1000_READ_REG(hw, E1000_CTRL);
3115         reg |= E1000_CTRL_VME;
3116         E1000_WRITE_REG(hw, E1000_CTRL, reg);
3117
3118         /* Enable the Filter Table */
3119         reg = E1000_READ_REG(hw, E1000_RCTL);
3120         reg &= ~E1000_RCTL_CFIEN;
3121         reg |= E1000_RCTL_VFE;
3122         E1000_WRITE_REG(hw, E1000_RCTL, reg);
3123 }
3124
3125 static void
3126 em_if_enable_intr(if_ctx_t ctx)
3127 {
3128         struct adapter *adapter = iflib_get_softc(ctx);
3129         struct e1000_hw *hw = &adapter->hw;
3130         u32 ims_mask = IMS_ENABLE_MASK;
3131
3132         if (hw->mac.type == e1000_82574) {
3133                 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK);
3134                 ims_mask |= adapter->ims;
3135         } if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min)  {
3136                 u32 mask = (adapter->que_mask | adapter->link_mask);
3137
3138                 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask);
3139                 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask);
3140                 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask);
3141                 ims_mask = E1000_IMS_LSC;
3142         }
3143
3144         E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3145 }
3146
3147 static void
3148 em_if_disable_intr(if_ctx_t ctx)
3149 {
3150         struct adapter *adapter = iflib_get_softc(ctx);
3151         struct e1000_hw *hw = &adapter->hw;
3152
3153         if (adapter->intr_type == IFLIB_INTR_MSIX) {
3154                 if (hw->mac.type >= igb_mac_min)
3155                         E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0);
3156                 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0);
3157         }
3158         E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
3159 }
3160
3161 /*
3162  * Bit of a misnomer, what this really means is
3163  * to enable OS management of the system... aka
3164  * to disable special hardware management features
3165  */
3166 static void
3167 em_init_manageability(struct adapter *adapter)
3168 {
3169         /* A shared code workaround */
3170 #define E1000_82542_MANC2H E1000_MANC2H
3171         if (adapter->has_manage) {
3172                 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3173                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3174
3175                 /* disable hardware interception of ARP */
3176                 manc &= ~(E1000_MANC_ARP_EN);
3177
3178                 /* enable receiving management packets to the host */
3179                 manc |= E1000_MANC_EN_MNG2HOST;
3180 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3181 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3182                 manc2h |= E1000_MNG2HOST_PORT_623;
3183                 manc2h |= E1000_MNG2HOST_PORT_664;
3184                 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3185                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3186         }
3187 }
3188
3189 /*
3190  * Give control back to hardware management
3191  * controller if there is one.
3192  */
3193 static void
3194 em_release_manageability(struct adapter *adapter)
3195 {
3196         if (adapter->has_manage) {
3197                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3198
3199                 /* re-enable hardware interception of ARP */
3200                 manc |= E1000_MANC_ARP_EN;
3201                 manc &= ~E1000_MANC_EN_MNG2HOST;
3202
3203                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3204         }
3205 }
3206
3207 /*
3208  * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3209  * For ASF and Pass Through versions of f/w this means
3210  * that the driver is loaded. For AMT version type f/w
3211  * this means that the network i/f is open.
3212  */
3213 static void
3214 em_get_hw_control(struct adapter *adapter)
3215 {
3216         u32 ctrl_ext, swsm;
3217
3218         if (adapter->hw.mac.type == e1000_82573) {
3219                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3220                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3221                     swsm | E1000_SWSM_DRV_LOAD);
3222                 return;
3223         }
3224         /* else */
3225         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3226         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3227             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3228         return;
3229 }
3230
3231 /*
3232  * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3233  * For ASF and Pass Through versions of f/w this means that
3234  * the driver is no longer loaded. For AMT versions of the
3235  * f/w this means that the network i/f is closed.
3236  */
3237 static void
3238 em_release_hw_control(struct adapter *adapter)
3239 {
3240         u32 ctrl_ext, swsm;
3241
3242         if (!adapter->has_manage)
3243                 return;
3244
3245         if (adapter->hw.mac.type == e1000_82573) {
3246                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3247                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3248                     swsm & ~E1000_SWSM_DRV_LOAD);
3249                 return;
3250         }
3251         /* else */
3252         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3253         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3254             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3255         return;
3256 }
3257
3258 static int
3259 em_is_valid_ether_addr(u8 *addr)
3260 {
3261         char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3262
3263         if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3264                 return (FALSE);
3265         }
3266
3267         return (TRUE);
3268 }
3269
3270 /*
3271 ** Parse the interface capabilities with regard
3272 ** to both system management and wake-on-lan for
3273 ** later use.
3274 */
3275 static void
3276 em_get_wakeup(if_ctx_t ctx)
3277 {
3278         struct adapter  *adapter = iflib_get_softc(ctx);
3279         device_t dev = iflib_get_dev(ctx);
3280         u16             eeprom_data = 0, device_id, apme_mask;
3281
3282         adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
3283         apme_mask = EM_EEPROM_APME;
3284
3285         switch (adapter->hw.mac.type) {
3286         case e1000_82542:
3287         case e1000_82543:
3288                 break;
3289         case e1000_82544:
3290                 e1000_read_nvm(&adapter->hw,
3291                     NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3292                 apme_mask = EM_82544_APME;
3293                 break;
3294         case e1000_82546:
3295         case e1000_82546_rev_3:
3296                 if (adapter->hw.bus.func == 1) {
3297                         e1000_read_nvm(&adapter->hw,
3298                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3299                         break;
3300                 } else
3301                         e1000_read_nvm(&adapter->hw,
3302                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3303                 break;
3304         case e1000_82573:
3305         case e1000_82583:
3306                 adapter->has_amt = TRUE;
3307                 /* Falls thru */
3308         case e1000_82571:
3309         case e1000_82572:
3310         case e1000_80003es2lan:
3311                 if (adapter->hw.bus.func == 1) {
3312                         e1000_read_nvm(&adapter->hw,
3313                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3314                         break;
3315                 } else
3316                         e1000_read_nvm(&adapter->hw,
3317                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3318                 break;
3319         case e1000_ich8lan:
3320         case e1000_ich9lan:
3321         case e1000_ich10lan:
3322         case e1000_pchlan:
3323         case e1000_pch2lan:
3324         case e1000_pch_lpt:
3325         case e1000_pch_spt:
3326         case e1000_82575:       /* listing all igb devices */
3327         case e1000_82576:
3328         case e1000_82580:
3329         case e1000_i350:
3330         case e1000_i354:
3331         case e1000_i210:
3332         case e1000_i211:
3333         case e1000_vfadapt:
3334         case e1000_vfadapt_i350:
3335                 apme_mask = E1000_WUC_APME;
3336                 adapter->has_amt = TRUE;
3337                 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
3338                 break;
3339         default:
3340                 e1000_read_nvm(&adapter->hw,
3341                     NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3342                 break;
3343         }
3344         if (eeprom_data & apme_mask)
3345                 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
3346         /*
3347          * We have the eeprom settings, now apply the special cases
3348          * where the eeprom may be wrong or the board won't support
3349          * wake on lan on a particular port
3350          */
3351         device_id = pci_get_device(dev);
3352         switch (device_id) {
3353         case E1000_DEV_ID_82546GB_PCIE:
3354                 adapter->wol = 0;
3355                 break;
3356         case E1000_DEV_ID_82546EB_FIBER:
3357         case E1000_DEV_ID_82546GB_FIBER:
3358                 /* Wake events only supported on port A for dual fiber
3359                  * regardless of eeprom setting */
3360                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3361                     E1000_STATUS_FUNC_1)
3362                         adapter->wol = 0;
3363                 break;
3364         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
3365                 /* if quad port adapter, disable WoL on all but port A */
3366                 if (global_quad_port_a != 0)
3367                         adapter->wol = 0;
3368                 /* Reset for multiple quad port adapters */
3369                 if (++global_quad_port_a == 4)
3370                         global_quad_port_a = 0;
3371                 break;
3372         case E1000_DEV_ID_82571EB_FIBER:
3373                 /* Wake events only supported on port A for dual fiber
3374                  * regardless of eeprom setting */
3375                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3376                     E1000_STATUS_FUNC_1)
3377                         adapter->wol = 0;
3378                 break;
3379         case E1000_DEV_ID_82571EB_QUAD_COPPER:
3380         case E1000_DEV_ID_82571EB_QUAD_FIBER:
3381         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
3382                 /* if quad port adapter, disable WoL on all but port A */
3383                 if (global_quad_port_a != 0)
3384                         adapter->wol = 0;
3385                 /* Reset for multiple quad port adapters */
3386                 if (++global_quad_port_a == 4)
3387                         global_quad_port_a = 0;
3388                 break;
3389         }
3390         return;
3391 }
3392
3393
3394 /*
3395  * Enable PCI Wake On Lan capability
3396  */
3397 static void
3398 em_enable_wakeup(if_ctx_t ctx)
3399 {
3400         struct adapter  *adapter = iflib_get_softc(ctx);
3401         device_t dev = iflib_get_dev(ctx);
3402         if_t ifp = iflib_get_ifp(ctx);
3403         u32             pmc, ctrl, ctrl_ext, rctl, wuc;
3404         u16             status;
3405
3406         if ((pci_find_cap(dev, PCIY_PMG, &pmc) != 0))
3407                 return;
3408
3409         /* Advertise the wakeup capability */
3410         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
3411         ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
3412         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
3413         wuc = E1000_READ_REG(&adapter->hw, E1000_WUC);
3414         wuc |= (E1000_WUC_PME_EN | E1000_WUC_APME);
3415         E1000_WRITE_REG(&adapter->hw, E1000_WUC, wuc);
3416
3417         if ((adapter->hw.mac.type == e1000_ich8lan) ||
3418             (adapter->hw.mac.type == e1000_pchlan) ||
3419             (adapter->hw.mac.type == e1000_ich9lan) ||
3420             (adapter->hw.mac.type == e1000_ich10lan))
3421                 e1000_suspend_workarounds_ich8lan(&adapter->hw);
3422
3423         /* Keep the laser running on Fiber adapters */
3424         if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3425             adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
3426                 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3427                 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
3428                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext);
3429         }
3430
3431         /*
3432         ** Determine type of Wakeup: note that wol
3433         ** is set with all bits on by default.
3434         */
3435         if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
3436                 adapter->wol &= ~E1000_WUFC_MAG;
3437
3438         if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
3439                 adapter->wol &= ~E1000_WUFC_EX;
3440
3441         if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
3442                 adapter->wol &= ~E1000_WUFC_MC;
3443         else {
3444                 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3445                 rctl |= E1000_RCTL_MPE;
3446                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3447         }
3448
3449         if ( adapter->hw.mac.type >= e1000_pchlan) {
3450                 if (em_enable_phy_wakeup(adapter))
3451                         return;
3452         } else {
3453                 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
3454                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
3455         }
3456
3457         if (adapter->hw.phy.type == e1000_phy_igp_3)
3458                 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
3459
3460         /* Request PME */
3461         status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
3462         status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3463         if (if_getcapenable(ifp) & IFCAP_WOL)
3464                 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3465         pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
3466
3467         return;
3468 }
3469
3470 /*
3471 ** WOL in the newer chipset interfaces (pchlan)
3472 ** require thing to be copied into the phy
3473 */
3474 static int
3475 em_enable_phy_wakeup(struct adapter *adapter)
3476 {
3477         struct e1000_hw *hw = &adapter->hw;
3478         u32 mreg, ret = 0;
3479         u16 preg;
3480
3481         /* copy MAC RARs to PHY RARs */
3482         e1000_copy_rx_addrs_to_phy_ich8lan(hw);
3483
3484         /* copy MAC MTA to PHY MTA */
3485         for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
3486                 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
3487                 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
3488                 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
3489                     (u16)((mreg >> 16) & 0xFFFF));
3490         }
3491
3492         /* configure PHY Rx Control register */
3493         e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg);
3494         mreg = E1000_READ_REG(hw, E1000_RCTL);
3495         if (mreg & E1000_RCTL_UPE)
3496                 preg |= BM_RCTL_UPE;
3497         if (mreg & E1000_RCTL_MPE)
3498                 preg |= BM_RCTL_MPE;
3499         preg &= ~(BM_RCTL_MO_MASK);
3500         if (mreg & E1000_RCTL_MO_3)
3501                 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
3502                                 << BM_RCTL_MO_SHIFT);
3503         if (mreg & E1000_RCTL_BAM)
3504                 preg |= BM_RCTL_BAM;
3505         if (mreg & E1000_RCTL_PMCF)
3506                 preg |= BM_RCTL_PMCF;
3507         mreg = E1000_READ_REG(hw, E1000_CTRL);
3508         if (mreg & E1000_CTRL_RFCE)
3509                 preg |= BM_RCTL_RFCE;
3510         e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg);
3511
3512         /* enable PHY wakeup in MAC register */
3513         E1000_WRITE_REG(hw, E1000_WUC,
3514             E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
3515         E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol);
3516
3517         /* configure and enable PHY wakeup in PHY registers */
3518         e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol);
3519         e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
3520
3521         /* activate PHY wakeup */
3522         ret = hw->phy.ops.acquire(hw);
3523         if (ret) {
3524                 printf("Could not acquire PHY\n");
3525                 return ret;
3526         }
3527         e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3528                                  (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3529         ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
3530         if (ret) {
3531                 printf("Could not read PHY page 769\n");
3532                 goto out;
3533         }
3534         preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
3535         ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
3536         if (ret)
3537                 printf("Could not set PHY Host Wakeup bit\n");
3538 out:
3539         hw->phy.ops.release(hw);
3540
3541         return ret;
3542 }
3543
3544 static void
3545 em_if_led_func(if_ctx_t ctx, int onoff)
3546 {
3547         struct adapter  *adapter = iflib_get_softc(ctx);
3548
3549         if (onoff) {
3550                 e1000_setup_led(&adapter->hw);
3551                 e1000_led_on(&adapter->hw);
3552         } else {
3553                 e1000_led_off(&adapter->hw);
3554                 e1000_cleanup_led(&adapter->hw);
3555         }
3556 }
3557
3558 /*
3559 ** Disable the L0S and L1 LINK states
3560 */
3561 static void
3562 em_disable_aspm(struct adapter *adapter)
3563 {
3564         int             base, reg;
3565         u16             link_cap,link_ctrl;
3566         device_t        dev = adapter->dev;
3567
3568         switch (adapter->hw.mac.type) {
3569                 case e1000_82573:
3570                 case e1000_82574:
3571                 case e1000_82583:
3572                         break;
3573                 default:
3574                         return;
3575         }
3576         if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
3577                 return;
3578         reg = base + PCIER_LINK_CAP;
3579         link_cap = pci_read_config(dev, reg, 2);
3580         if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
3581                 return;
3582         reg = base + PCIER_LINK_CTL;
3583         link_ctrl = pci_read_config(dev, reg, 2);
3584         link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
3585         pci_write_config(dev, reg, link_ctrl, 2);
3586         return;
3587 }
3588
3589 /**********************************************************************
3590  *
3591  *  Update the board statistics counters.
3592  *
3593  **********************************************************************/
3594 static void
3595 em_update_stats_counters(struct adapter *adapter)
3596 {
3597
3598         if(adapter->hw.phy.media_type == e1000_media_type_copper ||
3599            (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3600                 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
3601                 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
3602         }
3603         adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
3604         adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
3605         adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
3606         adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
3607
3608         adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
3609         adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
3610         adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
3611         adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
3612         adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
3613         adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
3614         adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
3615         adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
3616         adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
3617         adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
3618         adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
3619         adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
3620         adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
3621         adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
3622         adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
3623         adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
3624         adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
3625         adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
3626         adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
3627         adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
3628
3629         /* For the 64-bit byte counters the low dword must be read first. */
3630         /* Both registers clear on the read of the high dword */
3631
3632         adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) +
3633             ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32);
3634         adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) +
3635             ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32);
3636
3637         adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
3638         adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
3639         adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
3640         adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
3641         adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
3642
3643         adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
3644         adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
3645
3646         adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
3647         adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
3648         adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
3649         adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
3650         adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
3651         adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
3652         adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
3653         adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
3654         adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
3655         adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
3656
3657         /* Interrupt Counts */
3658
3659         adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC);
3660         adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC);
3661         adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC);
3662         adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC);
3663         adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC);
3664         adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC);
3665         adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC);
3666         adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC);
3667         adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC);
3668
3669         if (adapter->hw.mac.type >= e1000_82543) {
3670                 adapter->stats.algnerrc +=
3671                 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
3672                 adapter->stats.rxerrc +=
3673                 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
3674                 adapter->stats.tncrs +=
3675                 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
3676                 adapter->stats.cexterr +=
3677                 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
3678                 adapter->stats.tsctc +=
3679                 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
3680                 adapter->stats.tsctfc +=
3681                 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
3682         }
3683 }
3684
3685 static uint64_t
3686 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
3687 {
3688         struct adapter *adapter = iflib_get_softc(ctx);
3689         struct ifnet *ifp = iflib_get_ifp(ctx);
3690
3691         switch (cnt) {
3692         case IFCOUNTER_COLLISIONS:
3693                 return (adapter->stats.colc);
3694         case IFCOUNTER_IERRORS:
3695                 return (adapter->dropped_pkts + adapter->stats.rxerrc +
3696                     adapter->stats.crcerrs + adapter->stats.algnerrc +
3697                     adapter->stats.ruc + adapter->stats.roc +
3698                     adapter->stats.mpc + adapter->stats.cexterr);
3699         case IFCOUNTER_OERRORS:
3700                 return (adapter->stats.ecol + adapter->stats.latecol +
3701                     adapter->watchdog_events);
3702         default:
3703                 return (if_get_counter_default(ifp, cnt));
3704         }
3705 }
3706
3707 /* Export a single 32-bit register via a read-only sysctl. */
3708 static int
3709 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
3710 {
3711         struct adapter *adapter;
3712         u_int val;
3713
3714         adapter = oidp->oid_arg1;
3715         val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2);
3716         return (sysctl_handle_int(oidp, &val, 0, req));
3717 }
3718
3719 /*
3720  * Add sysctl variables, one per statistic, to the system.
3721  */
3722 static void
3723 em_add_hw_stats(struct adapter *adapter)
3724 {
3725         device_t dev = iflib_get_dev(adapter->ctx);
3726         struct em_tx_queue *tx_que = adapter->tx_queues;
3727         struct em_rx_queue *rx_que = adapter->rx_queues;
3728
3729         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
3730         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
3731         struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
3732         struct e1000_hw_stats *stats = &adapter->stats;
3733
3734         struct sysctl_oid *stat_node, *queue_node, *int_node;
3735         struct sysctl_oid_list *stat_list, *queue_list, *int_list;
3736
3737 #define QUEUE_NAME_LEN 32
3738         char namebuf[QUEUE_NAME_LEN];
3739
3740         /* Driver Statistics */
3741         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
3742                         CTLFLAG_RD, &adapter->dropped_pkts,
3743                         "Driver dropped packets");
3744         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
3745                         CTLFLAG_RD, &adapter->link_irq,
3746                         "Link MSIX IRQ Handled");
3747         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "mbuf_defrag_fail",
3748                          CTLFLAG_RD, &adapter->mbuf_defrag_failed,
3749                          "Defragmenting mbuf chain failed");
3750         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "tx_dma_fail",
3751                         CTLFLAG_RD, &adapter->no_tx_dma_setup,
3752                         "Driver tx dma failure in xmit");
3753         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
3754                         CTLFLAG_RD, &adapter->rx_overruns,
3755                         "RX overruns");
3756         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
3757                         CTLFLAG_RD, &adapter->watchdog_events,
3758                         "Watchdog timeouts");
3759
3760         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
3761                         CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL,
3762                         em_sysctl_reg_handler, "IU",
3763                         "Device Control Register");
3764         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
3765                         CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL,
3766                         em_sysctl_reg_handler, "IU",
3767                         "Receiver Control Register");
3768         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
3769                         CTLFLAG_RD, &adapter->hw.fc.high_water, 0,
3770                         "Flow Control High Watermark");
3771         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
3772                         CTLFLAG_RD, &adapter->hw.fc.low_water, 0,
3773                         "Flow Control Low Watermark");
3774
3775         for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
3776                 struct tx_ring *txr = &tx_que->txr;
3777                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
3778                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
3779                                             CTLFLAG_RD, NULL, "TX Queue Name");
3780                 queue_list = SYSCTL_CHILDREN(queue_node);
3781
3782                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
3783                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
3784                                 E1000_TDH(txr->me),
3785                                 em_sysctl_reg_handler, "IU",
3786                                 "Transmit Descriptor Head");
3787                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
3788                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
3789                                 E1000_TDT(txr->me),
3790                                 em_sysctl_reg_handler, "IU",
3791                                 "Transmit Descriptor Tail");
3792                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
3793                                 CTLFLAG_RD, &txr->tx_irq,
3794                                 "Queue MSI-X Transmit Interrupts");
3795                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "no_desc_avail",
3796                                 CTLFLAG_RD, &txr->no_desc_avail,
3797                                 "Queue No Descriptor Available");
3798         }
3799
3800         for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) {
3801                 struct rx_ring *rxr = &rx_que->rxr;
3802                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
3803                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
3804                                             CTLFLAG_RD, NULL, "RX Queue Name");
3805                 queue_list = SYSCTL_CHILDREN(queue_node);
3806
3807                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
3808                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
3809                                 E1000_RDH(rxr->me),
3810                                 em_sysctl_reg_handler, "IU",
3811                                 "Receive Descriptor Head");
3812                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
3813                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
3814                                 E1000_RDT(rxr->me),
3815                                 em_sysctl_reg_handler, "IU",
3816                                 "Receive Descriptor Tail");
3817                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
3818                                 CTLFLAG_RD, &rxr->rx_irq,
3819                                 "Queue MSI-X Receive Interrupts");
3820         }
3821
3822         /* MAC stats get their own sub node */
3823
3824         stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
3825                                     CTLFLAG_RD, NULL, "Statistics");
3826         stat_list = SYSCTL_CHILDREN(stat_node);
3827
3828         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
3829                         CTLFLAG_RD, &stats->ecol,
3830                         "Excessive collisions");
3831         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
3832                         CTLFLAG_RD, &stats->scc,
3833                         "Single collisions");
3834         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
3835                         CTLFLAG_RD, &stats->mcc,
3836                         "Multiple collisions");
3837         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
3838                         CTLFLAG_RD, &stats->latecol,
3839                         "Late collisions");
3840         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
3841                         CTLFLAG_RD, &stats->colc,
3842                         "Collision Count");
3843         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
3844                         CTLFLAG_RD, &adapter->stats.symerrs,
3845                         "Symbol Errors");
3846         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
3847                         CTLFLAG_RD, &adapter->stats.sec,
3848                         "Sequence Errors");
3849         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
3850                         CTLFLAG_RD, &adapter->stats.dc,
3851                         "Defer Count");
3852         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
3853                         CTLFLAG_RD, &adapter->stats.mpc,
3854                         "Missed Packets");
3855         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
3856                         CTLFLAG_RD, &adapter->stats.rnbc,
3857                         "Receive No Buffers");
3858         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
3859                         CTLFLAG_RD, &adapter->stats.ruc,
3860                         "Receive Undersize");
3861         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
3862                         CTLFLAG_RD, &adapter->stats.rfc,
3863                         "Fragmented Packets Received ");
3864         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
3865                         CTLFLAG_RD, &adapter->stats.roc,
3866                         "Oversized Packets Received");
3867         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
3868                         CTLFLAG_RD, &adapter->stats.rjc,
3869                         "Recevied Jabber");
3870         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
3871                         CTLFLAG_RD, &adapter->stats.rxerrc,
3872                         "Receive Errors");
3873         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
3874                         CTLFLAG_RD, &adapter->stats.crcerrs,
3875                         "CRC errors");
3876         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
3877                         CTLFLAG_RD, &adapter->stats.algnerrc,
3878                         "Alignment Errors");
3879         /* On 82575 these are collision counts */
3880         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
3881                         CTLFLAG_RD, &adapter->stats.cexterr,
3882                         "Collision/Carrier extension errors");
3883         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
3884                         CTLFLAG_RD, &adapter->stats.xonrxc,
3885                         "XON Received");
3886         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
3887                         CTLFLAG_RD, &adapter->stats.xontxc,
3888                         "XON Transmitted");
3889         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
3890                         CTLFLAG_RD, &adapter->stats.xoffrxc,
3891                         "XOFF Received");
3892         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
3893                         CTLFLAG_RD, &adapter->stats.xofftxc,
3894                         "XOFF Transmitted");
3895
3896         /* Packet Reception Stats */
3897         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
3898                         CTLFLAG_RD, &adapter->stats.tpr,
3899                         "Total Packets Received ");
3900         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
3901                         CTLFLAG_RD, &adapter->stats.gprc,
3902                         "Good Packets Received");
3903         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
3904                         CTLFLAG_RD, &adapter->stats.bprc,
3905                         "Broadcast Packets Received");
3906         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
3907                         CTLFLAG_RD, &adapter->stats.mprc,
3908                         "Multicast Packets Received");
3909         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
3910                         CTLFLAG_RD, &adapter->stats.prc64,
3911                         "64 byte frames received ");
3912         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
3913                         CTLFLAG_RD, &adapter->stats.prc127,
3914                         "65-127 byte frames received");
3915         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
3916                         CTLFLAG_RD, &adapter->stats.prc255,
3917                         "128-255 byte frames received");
3918         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
3919                         CTLFLAG_RD, &adapter->stats.prc511,
3920                         "256-511 byte frames received");
3921         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
3922                         CTLFLAG_RD, &adapter->stats.prc1023,
3923                         "512-1023 byte frames received");
3924         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
3925                         CTLFLAG_RD, &adapter->stats.prc1522,
3926                         "1023-1522 byte frames received");
3927         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
3928                         CTLFLAG_RD, &adapter->stats.gorc,
3929                         "Good Octets Received");
3930
3931         /* Packet Transmission Stats */
3932         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
3933                         CTLFLAG_RD, &adapter->stats.gotc,
3934                         "Good Octets Transmitted");
3935         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
3936                         CTLFLAG_RD, &adapter->stats.tpt,
3937                         "Total Packets Transmitted");
3938         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
3939                         CTLFLAG_RD, &adapter->stats.gptc,
3940                         "Good Packets Transmitted");
3941         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
3942                         CTLFLAG_RD, &adapter->stats.bptc,
3943                         "Broadcast Packets Transmitted");
3944         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
3945                         CTLFLAG_RD, &adapter->stats.mptc,
3946                         "Multicast Packets Transmitted");
3947         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
3948                         CTLFLAG_RD, &adapter->stats.ptc64,
3949                         "64 byte frames transmitted ");
3950         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
3951                         CTLFLAG_RD, &adapter->stats.ptc127,
3952                         "65-127 byte frames transmitted");
3953         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
3954                         CTLFLAG_RD, &adapter->stats.ptc255,
3955                         "128-255 byte frames transmitted");
3956         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
3957                         CTLFLAG_RD, &adapter->stats.ptc511,
3958                         "256-511 byte frames transmitted");
3959         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
3960                         CTLFLAG_RD, &adapter->stats.ptc1023,
3961                         "512-1023 byte frames transmitted");
3962         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
3963                         CTLFLAG_RD, &adapter->stats.ptc1522,
3964                         "1024-1522 byte frames transmitted");
3965         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
3966                         CTLFLAG_RD, &adapter->stats.tsctc,
3967                         "TSO Contexts Transmitted");
3968         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
3969                         CTLFLAG_RD, &adapter->stats.tsctfc,
3970                         "TSO Contexts Failed");
3971
3972
3973         /* Interrupt Stats */
3974
3975         int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
3976                                     CTLFLAG_RD, NULL, "Interrupt Statistics");
3977         int_list = SYSCTL_CHILDREN(int_node);
3978
3979         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
3980                         CTLFLAG_RD, &adapter->stats.iac,
3981                         "Interrupt Assertion Count");
3982
3983         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
3984                         CTLFLAG_RD, &adapter->stats.icrxptc,
3985                         "Interrupt Cause Rx Pkt Timer Expire Count");
3986
3987         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
3988                         CTLFLAG_RD, &adapter->stats.icrxatc,
3989                         "Interrupt Cause Rx Abs Timer Expire Count");
3990
3991         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
3992                         CTLFLAG_RD, &adapter->stats.ictxptc,
3993                         "Interrupt Cause Tx Pkt Timer Expire Count");
3994
3995         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
3996                         CTLFLAG_RD, &adapter->stats.ictxatc,
3997                         "Interrupt Cause Tx Abs Timer Expire Count");
3998
3999         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
4000                         CTLFLAG_RD, &adapter->stats.ictxqec,
4001                         "Interrupt Cause Tx Queue Empty Count");
4002
4003         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
4004                         CTLFLAG_RD, &adapter->stats.ictxqmtc,
4005                         "Interrupt Cause Tx Queue Min Thresh Count");
4006
4007         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
4008                         CTLFLAG_RD, &adapter->stats.icrxdmtc,
4009                         "Interrupt Cause Rx Desc Min Thresh Count");
4010
4011         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
4012                         CTLFLAG_RD, &adapter->stats.icrxoc,
4013                         "Interrupt Cause Receiver Overrun Count");
4014 }
4015
4016 /**********************************************************************
4017  *
4018  *  This routine provides a way to dump out the adapter eeprom,
4019  *  often a useful debug/service tool. This only dumps the first
4020  *  32 words, stuff that matters is in that extent.
4021  *
4022  **********************************************************************/
4023 static int
4024 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4025 {
4026         struct adapter *adapter = (struct adapter *)arg1;
4027         int error;
4028         int result;
4029
4030         result = -1;
4031         error = sysctl_handle_int(oidp, &result, 0, req);
4032
4033         if (error || !req->newptr)
4034                 return (error);
4035
4036         /*
4037          * This value will cause a hex dump of the
4038          * first 32 16-bit words of the EEPROM to
4039          * the screen.
4040          */
4041         if (result == 1)
4042                 em_print_nvm_info(adapter);
4043
4044         return (error);
4045 }
4046
4047 static void
4048 em_print_nvm_info(struct adapter *adapter)
4049 {
4050         u16     eeprom_data;
4051         int     i, j, row = 0;
4052
4053         /* Its a bit crude, but it gets the job done */
4054         printf("\nInterface EEPROM Dump:\n");
4055         printf("Offset\n0x0000  ");
4056         for (i = 0, j = 0; i < 32; i++, j++) {
4057                 if (j == 8) { /* Make the offset block */
4058                         j = 0; ++row;
4059                         printf("\n0x00%x0  ",row);
4060                 }
4061                 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
4062                 printf("%04x ", eeprom_data);
4063         }
4064         printf("\n");
4065 }
4066
4067 static int
4068 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4069 {
4070         struct em_int_delay_info *info;
4071         struct adapter *adapter;
4072         u32 regval;
4073         int error, usecs, ticks;
4074
4075         info = (struct em_int_delay_info *)arg1;
4076         usecs = info->value;
4077         error = sysctl_handle_int(oidp, &usecs, 0, req);
4078         if (error != 0 || req->newptr == NULL)
4079                 return (error);
4080         if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4081                 return (EINVAL);
4082         info->value = usecs;
4083         ticks = EM_USECS_TO_TICKS(usecs);
4084         if (info->offset == E1000_ITR)  /* units are 256ns here */
4085                 ticks *= 4;
4086
4087         adapter = info->adapter;
4088
4089         regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
4090         regval = (regval & ~0xffff) | (ticks & 0xffff);
4091         /* Handle a few special cases. */
4092         switch (info->offset) {
4093         case E1000_RDTR:
4094                 break;
4095         case E1000_TIDV:
4096                 if (ticks == 0) {
4097                         adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
4098                         /* Don't write 0 into the TIDV register. */
4099                         regval++;
4100                 } else
4101                         adapter->txd_cmd |= E1000_TXD_CMD_IDE;
4102                 break;
4103         }
4104         E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
4105         return (0);
4106 }
4107
4108 static void
4109 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
4110         const char *description, struct em_int_delay_info *info,
4111         int offset, int value)
4112 {
4113         info->adapter = adapter;
4114         info->offset = offset;
4115         info->value = value;
4116         SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev),
4117             SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4118             OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
4119             info, 0, em_sysctl_int_delay, "I", description);
4120 }
4121
4122 static void
4123 em_set_sysctl_value(struct adapter *adapter, const char *name,
4124         const char *description, int *limit, int value)
4125 {
4126         *limit = value;
4127         SYSCTL_ADD_INT(device_get_sysctl_ctx(adapter->dev),
4128             SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4129             OID_AUTO, name, CTLFLAG_RW, limit, value, description);
4130 }
4131
4132
4133 /*
4134 ** Set flow control using sysctl:
4135 ** Flow control values:
4136 **      0 - off
4137 **      1 - rx pause
4138 **      2 - tx pause
4139 **      3 - full
4140 */
4141 static int
4142 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4143 {
4144         int             error;
4145         static int      input = 3; /* default is full */
4146         struct adapter  *adapter = (struct adapter *) arg1;
4147
4148         error = sysctl_handle_int(oidp, &input, 0, req);
4149
4150         if ((error) || (req->newptr == NULL))
4151                 return (error);
4152
4153         if (input == adapter->fc) /* no change? */
4154                 return (error);
4155
4156         switch (input) {
4157                 case e1000_fc_rx_pause:
4158                 case e1000_fc_tx_pause:
4159                 case e1000_fc_full:
4160                 case e1000_fc_none:
4161                         adapter->hw.fc.requested_mode = input;
4162                         adapter->fc = input;
4163                         break;
4164                 default:
4165                         /* Do nothing */
4166                         return (error);
4167         }
4168
4169         adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
4170         e1000_force_mac_fc(&adapter->hw);
4171         return (error);
4172 }
4173
4174 /*
4175 ** Manage Energy Efficient Ethernet:
4176 ** Control values:
4177 **     0/1 - enabled/disabled
4178 */
4179 static int
4180 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4181 {
4182        struct adapter *adapter = (struct adapter *) arg1;
4183        int             error, value;
4184
4185        value = adapter->hw.dev_spec.ich8lan.eee_disable;
4186        error = sysctl_handle_int(oidp, &value, 0, req);
4187        if (error || req->newptr == NULL)
4188                return (error);
4189        adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4190        em_if_init(adapter->ctx);
4191
4192        return (0);
4193 }
4194
4195 static int
4196 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4197 {
4198         struct adapter *adapter;
4199         int error;
4200         int result;
4201
4202         result = -1;
4203         error = sysctl_handle_int(oidp, &result, 0, req);
4204
4205         if (error || !req->newptr)
4206                 return (error);
4207
4208         if (result == 1) {
4209                 adapter = (struct adapter *)arg1;
4210                 em_print_debug_info(adapter);
4211         }
4212
4213         return (error);
4214 }
4215
4216 /*
4217 ** This routine is meant to be fluid, add whatever is
4218 ** needed for debugging a problem.  -jfv
4219 */
4220 static void
4221 em_print_debug_info(struct adapter *adapter)
4222 {
4223         device_t dev = adapter->dev;
4224         struct tx_ring *txr = &adapter->tx_queues->txr;
4225         struct rx_ring *rxr = &adapter->rx_queues->rxr;
4226
4227         if (if_getdrvflags(adapter->ifp) & IFF_DRV_RUNNING)
4228                 printf("Interface is RUNNING ");
4229         else
4230                 printf("Interface is NOT RUNNING\n");
4231
4232         if (if_getdrvflags(adapter->ifp) & IFF_DRV_OACTIVE)
4233                 printf("and INACTIVE\n");
4234         else
4235                 printf("and ACTIVE\n");
4236
4237         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
4238                 device_printf(dev, "TX Queue %d ------\n", i);
4239                 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
4240                         E1000_READ_REG(&adapter->hw, E1000_TDH(i)),
4241                         E1000_READ_REG(&adapter->hw, E1000_TDT(i)));
4242
4243         }
4244         for (int j=0; j < adapter->rx_num_queues; j++, rxr++) {
4245                 device_printf(dev, "RX Queue %d ------\n", j);
4246                 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
4247                         E1000_READ_REG(&adapter->hw, E1000_RDH(j)),
4248                         E1000_READ_REG(&adapter->hw, E1000_RDT(j)));
4249         }
4250 }
4251
4252
4253 /*
4254  * 82574 only:
4255  * Write a new value to the EEPROM increasing the number of MSIX
4256  * vectors from 3 to 5, for proper multiqueue support.
4257  */
4258 static void
4259 em_enable_vectors_82574(if_ctx_t ctx)
4260 {
4261         struct adapter *adapter = iflib_get_softc(ctx);
4262         struct e1000_hw *hw = &adapter->hw;
4263         device_t dev = iflib_get_dev(ctx);
4264         u16 edata;
4265
4266         e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4267         printf("Current cap: %#06x\n", edata);
4268         if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
4269                 device_printf(dev, "Writing to eeprom: increasing "
4270                     "reported MSIX vectors from 3 to 5...\n");
4271                 edata &= ~(EM_NVM_MSIX_N_MASK);
4272                 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
4273                 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4274                 e1000_update_nvm_checksum(hw);
4275                 device_printf(dev, "Writing to eeprom: done\n");
4276         }
4277 }
4278
4279
4280 #ifdef DDB
4281 DB_COMMAND(em_reset_dev, em_ddb_reset_dev)
4282 {
4283         devclass_t      dc;
4284         int max_em;
4285
4286         dc = devclass_find("em");
4287         max_em = devclass_get_maxunit(dc);
4288
4289         for (int index = 0; index < (max_em - 1); index++) {
4290                 device_t dev;
4291                 dev = devclass_get_device(dc, index);
4292                 if (device_get_driver(dev) == &em_driver) {
4293                         struct adapter *adapter = device_get_softc(dev);
4294                         em_if_init(adapter->ctx);
4295                 }
4296         }
4297 }
4298 DB_COMMAND(em_dump_queue, em_ddb_dump_queue)
4299 {
4300         devclass_t      dc;
4301         int max_em;
4302
4303         dc = devclass_find("em");
4304         max_em = devclass_get_maxunit(dc);
4305
4306         for (int index = 0; index < (max_em - 1); index++) {
4307                 device_t dev;
4308                 dev = devclass_get_device(dc, index);
4309                 if (device_get_driver(dev) == &em_driver)
4310                         em_print_debug_info(device_get_softc(dev));
4311         }
4312
4313 }
4314 #endif