2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <machine/_inttypes.h>
34 #define em_mac_min e1000_82571
35 #define igb_mac_min e1000_82575
37 /*********************************************************************
39 *********************************************************************/
40 char em_driver_version[] = "7.6.1-k";
42 /*********************************************************************
45 * Used by probe to select devices to load on
46 * Last field stores an index into e1000_strings
47 * Last entry must be all 0s
49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
50 *********************************************************************/
52 static pci_vendor_info_t em_vendor_info_array[] =
54 /* Intel(R) - lem-class legacy devices */
55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"),
56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"),
57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"),
58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"),
59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"),
61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"),
62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"),
63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"),
64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"),
65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"),
66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"),
67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"),
69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"),
71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"),
72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"),
74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"),
75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"),
76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"),
77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"),
79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"),
80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"),
81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"),
82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"),
83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"),
85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"),
86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"),
87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"),
88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"),
89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"),
90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"),
91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"),
92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"),
96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"),
97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"),
99 /* Intel(R) - em-class devices */
100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"),
101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"),
102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"),
103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"),
104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"),
105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"),
108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"),
109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"),
110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"),
111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"),
112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"),
113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"),
114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"),
115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"),
116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"),
117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"),
118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"),
119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"),
120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"),
121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"),
122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"),
123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"),
124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"),
125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"),
126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"),
127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"),
128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"),
129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"),
130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"),
131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"),
132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"),
133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"),
134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"),
135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"),
136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"),
137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"),
138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"),
139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"),
140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"),
141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"),
142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"),
143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"),
144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"),
145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"),
146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"),
147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"),
148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"),
149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"),
150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"),
151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"),
152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"),
153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"),
154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"),
155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"),
156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"),
157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"),
158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"),
159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"),
160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"),
161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"),
162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"),
163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"),
164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"),
165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"),
166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"),
167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"),
168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"),
169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"),
170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"),
171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"),
172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"),
173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"),
174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"),
175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"),
176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"),
177 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"),
178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"),
179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"),
180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"),
181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"),
182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"),
183 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"),
184 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"),
185 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"),
186 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"),
187 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"),
188 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"),
189 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"),
190 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"),
191 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"),
192 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"),
193 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"),
194 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"),
195 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"),
196 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"),
197 /* required last entry */
201 static pci_vendor_info_t igb_vendor_info_array[] =
203 /* Intel(R) - igb-class devices */
204 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"),
205 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"),
206 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"),
207 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"),
208 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"),
209 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"),
210 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"),
211 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"),
212 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"),
213 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"),
214 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"),
215 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"),
216 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"),
217 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"),
218 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"),
219 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"),
220 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"),
221 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"),
222 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"),
223 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"),
224 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"),
225 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"),
226 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"),
227 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"),
228 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"),
229 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"),
230 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"),
231 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"),
232 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"),
233 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"),
234 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"),
235 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"),
236 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"),
237 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"),
238 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"),
239 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"),
240 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"),
241 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"),
242 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"),
243 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"),
244 /* required last entry */
248 /*********************************************************************
249 * Function prototypes
250 *********************************************************************/
251 static void *em_register(device_t dev);
252 static void *igb_register(device_t dev);
253 static int em_if_attach_pre(if_ctx_t ctx);
254 static int em_if_attach_post(if_ctx_t ctx);
255 static int em_if_detach(if_ctx_t ctx);
256 static int em_if_shutdown(if_ctx_t ctx);
257 static int em_if_suspend(if_ctx_t ctx);
258 static int em_if_resume(if_ctx_t ctx);
260 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets);
261 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets);
262 static void em_if_queues_free(if_ctx_t ctx);
264 static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
265 static void em_if_init(if_ctx_t ctx);
266 static void em_if_stop(if_ctx_t ctx);
267 static void em_if_media_status(if_ctx_t, struct ifmediareq *);
268 static int em_if_media_change(if_ctx_t ctx);
269 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu);
270 static void em_if_timer(if_ctx_t ctx, uint16_t qid);
271 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag);
272 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag);
273 static void em_if_watchdog_reset(if_ctx_t ctx);
274 static bool em_if_needs_restart(if_ctx_t ctx, enum iflib_restart_event event);
276 static void em_identify_hardware(if_ctx_t ctx);
277 static int em_allocate_pci_resources(if_ctx_t ctx);
278 static void em_free_pci_resources(if_ctx_t ctx);
279 static void em_reset(if_ctx_t ctx);
280 static int em_setup_interface(if_ctx_t ctx);
281 static int em_setup_msix(if_ctx_t ctx);
283 static void em_initialize_transmit_unit(if_ctx_t ctx);
284 static void em_initialize_receive_unit(if_ctx_t ctx);
286 static void em_if_intr_enable(if_ctx_t ctx);
287 static void em_if_intr_disable(if_ctx_t ctx);
288 static void igb_if_intr_enable(if_ctx_t ctx);
289 static void igb_if_intr_disable(if_ctx_t ctx);
290 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
291 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
292 static int igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
293 static int igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
294 static void em_if_multi_set(if_ctx_t ctx);
295 static void em_if_update_admin_status(if_ctx_t ctx);
296 static void em_if_debug(if_ctx_t ctx);
297 static void em_update_stats_counters(struct adapter *);
298 static void em_add_hw_stats(struct adapter *adapter);
299 static int em_if_set_promisc(if_ctx_t ctx, int flags);
300 static bool em_if_vlan_filter_capable(struct adapter *);
301 static bool em_if_vlan_filter_used(struct adapter *);
302 static void em_if_vlan_filter_enable(struct adapter *);
303 static void em_if_vlan_filter_disable(struct adapter *);
304 static void em_if_vlan_filter_write(struct adapter *);
305 static void em_setup_vlan_hw_support(struct adapter *);
306 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
307 static void em_print_nvm_info(struct adapter *);
308 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
309 static int em_get_rs(SYSCTL_HANDLER_ARGS);
310 static void em_print_debug_info(struct adapter *);
311 static int em_is_valid_ether_addr(u8 *);
312 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
313 static void em_add_int_delay_sysctl(struct adapter *, const char *,
314 const char *, struct em_int_delay_info *, int, int);
315 /* Management and WOL Support */
316 static void em_init_manageability(struct adapter *);
317 static void em_release_manageability(struct adapter *);
318 static void em_get_hw_control(struct adapter *);
319 static void em_release_hw_control(struct adapter *);
320 static void em_get_wakeup(if_ctx_t ctx);
321 static void em_enable_wakeup(if_ctx_t ctx);
322 static int em_enable_phy_wakeup(struct adapter *);
323 static void em_disable_aspm(struct adapter *);
325 int em_intr(void *arg);
328 static int em_if_msix_intr_assign(if_ctx_t, int);
329 static int em_msix_link(void *);
330 static void em_handle_link(void *context);
332 static void em_enable_vectors_82574(if_ctx_t);
334 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS);
335 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS);
336 static void em_if_led_func(if_ctx_t ctx, int onoff);
338 static int em_get_regs(SYSCTL_HANDLER_ARGS);
340 static void lem_smartspeed(struct adapter *adapter);
341 static void igb_configure_queues(struct adapter *adapter);
344 /*********************************************************************
345 * FreeBSD Device Interface Entry Points
346 *********************************************************************/
347 static device_method_t em_methods[] = {
348 /* Device interface */
349 DEVMETHOD(device_register, em_register),
350 DEVMETHOD(device_probe, iflib_device_probe),
351 DEVMETHOD(device_attach, iflib_device_attach),
352 DEVMETHOD(device_detach, iflib_device_detach),
353 DEVMETHOD(device_shutdown, iflib_device_shutdown),
354 DEVMETHOD(device_suspend, iflib_device_suspend),
355 DEVMETHOD(device_resume, iflib_device_resume),
359 static device_method_t igb_methods[] = {
360 /* Device interface */
361 DEVMETHOD(device_register, igb_register),
362 DEVMETHOD(device_probe, iflib_device_probe),
363 DEVMETHOD(device_attach, iflib_device_attach),
364 DEVMETHOD(device_detach, iflib_device_detach),
365 DEVMETHOD(device_shutdown, iflib_device_shutdown),
366 DEVMETHOD(device_suspend, iflib_device_suspend),
367 DEVMETHOD(device_resume, iflib_device_resume),
372 static driver_t em_driver = {
373 "em", em_methods, sizeof(struct adapter),
376 static devclass_t em_devclass;
377 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
379 MODULE_DEPEND(em, pci, 1, 1, 1);
380 MODULE_DEPEND(em, ether, 1, 1, 1);
381 MODULE_DEPEND(em, iflib, 1, 1, 1);
383 IFLIB_PNP_INFO(pci, em, em_vendor_info_array);
385 static driver_t igb_driver = {
386 "igb", igb_methods, sizeof(struct adapter),
389 static devclass_t igb_devclass;
390 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
392 MODULE_DEPEND(igb, pci, 1, 1, 1);
393 MODULE_DEPEND(igb, ether, 1, 1, 1);
394 MODULE_DEPEND(igb, iflib, 1, 1, 1);
396 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array);
398 static device_method_t em_if_methods[] = {
399 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
400 DEVMETHOD(ifdi_attach_post, em_if_attach_post),
401 DEVMETHOD(ifdi_detach, em_if_detach),
402 DEVMETHOD(ifdi_shutdown, em_if_shutdown),
403 DEVMETHOD(ifdi_suspend, em_if_suspend),
404 DEVMETHOD(ifdi_resume, em_if_resume),
405 DEVMETHOD(ifdi_init, em_if_init),
406 DEVMETHOD(ifdi_stop, em_if_stop),
407 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
408 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable),
409 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable),
410 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
411 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
412 DEVMETHOD(ifdi_queues_free, em_if_queues_free),
413 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
414 DEVMETHOD(ifdi_multi_set, em_if_multi_set),
415 DEVMETHOD(ifdi_media_status, em_if_media_status),
416 DEVMETHOD(ifdi_media_change, em_if_media_change),
417 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
418 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
419 DEVMETHOD(ifdi_timer, em_if_timer),
420 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
421 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
422 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
423 DEVMETHOD(ifdi_get_counter, em_if_get_counter),
424 DEVMETHOD(ifdi_led_func, em_if_led_func),
425 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable),
426 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable),
427 DEVMETHOD(ifdi_debug, em_if_debug),
428 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart),
432 static driver_t em_if_driver = {
433 "em_if", em_if_methods, sizeof(struct adapter)
436 static device_method_t igb_if_methods[] = {
437 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
438 DEVMETHOD(ifdi_attach_post, em_if_attach_post),
439 DEVMETHOD(ifdi_detach, em_if_detach),
440 DEVMETHOD(ifdi_shutdown, em_if_shutdown),
441 DEVMETHOD(ifdi_suspend, em_if_suspend),
442 DEVMETHOD(ifdi_resume, em_if_resume),
443 DEVMETHOD(ifdi_init, em_if_init),
444 DEVMETHOD(ifdi_stop, em_if_stop),
445 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
446 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable),
447 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable),
448 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
449 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
450 DEVMETHOD(ifdi_queues_free, em_if_queues_free),
451 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
452 DEVMETHOD(ifdi_multi_set, em_if_multi_set),
453 DEVMETHOD(ifdi_media_status, em_if_media_status),
454 DEVMETHOD(ifdi_media_change, em_if_media_change),
455 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
456 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
457 DEVMETHOD(ifdi_timer, em_if_timer),
458 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
459 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
460 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
461 DEVMETHOD(ifdi_get_counter, em_if_get_counter),
462 DEVMETHOD(ifdi_led_func, em_if_led_func),
463 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable),
464 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable),
465 DEVMETHOD(ifdi_debug, em_if_debug),
466 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart),
470 static driver_t igb_if_driver = {
471 "igb_if", igb_if_methods, sizeof(struct adapter)
474 /*********************************************************************
475 * Tunable default values.
476 *********************************************************************/
478 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000)
479 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024)
481 #define MAX_INTS_PER_SEC 8000
482 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256))
484 /* Allow common code without TSO */
489 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
490 "EM driver parameters");
492 static int em_disable_crc_stripping = 0;
493 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
494 &em_disable_crc_stripping, 0, "Disable CRC Stripping");
496 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
497 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
498 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
499 0, "Default transmit interrupt delay in usecs");
500 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
501 0, "Default receive interrupt delay in usecs");
503 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
504 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
505 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
506 &em_tx_abs_int_delay_dflt, 0,
507 "Default transmit interrupt delay limit in usecs");
508 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
509 &em_rx_abs_int_delay_dflt, 0,
510 "Default receive interrupt delay limit in usecs");
512 static int em_smart_pwr_down = FALSE;
513 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
514 0, "Set to true to leave smart power down enabled on newer adapters");
516 /* Controls whether promiscuous also shows bad packets */
517 static int em_debug_sbp = FALSE;
518 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
519 "Show bad packets in promiscuous mode");
521 /* How many packets rxeof tries to clean at a time */
522 static int em_rx_process_limit = 100;
523 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
524 &em_rx_process_limit, 0,
525 "Maximum number of received packets to process "
526 "at a time, -1 means unlimited");
528 /* Energy efficient ethernet - default to OFF */
529 static int eee_setting = 1;
530 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
531 "Enable Energy Efficient Ethernet");
534 ** Tuneable Interrupt rate
536 static int em_max_interrupt_rate = 8000;
537 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
538 &em_max_interrupt_rate, 0, "Maximum interrupts per second");
542 /* Global used in WOL setup with multiport cards */
543 static int global_quad_port_a = 0;
545 extern struct if_txrx igb_txrx;
546 extern struct if_txrx em_txrx;
547 extern struct if_txrx lem_txrx;
549 static struct if_shared_ctx em_sctx_init = {
550 .isc_magic = IFLIB_MAGIC,
551 .isc_q_align = PAGE_SIZE,
552 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
553 .isc_tx_maxsegsize = PAGE_SIZE,
554 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
555 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
556 .isc_rx_maxsize = MJUM9BYTES,
557 .isc_rx_nsegments = 1,
558 .isc_rx_maxsegsize = MJUM9BYTES,
562 .isc_admin_intrcnt = 1,
563 .isc_vendor_info = em_vendor_info_array,
564 .isc_driver_version = em_driver_version,
565 .isc_driver = &em_if_driver,
566 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
568 .isc_nrxd_min = {EM_MIN_RXD},
569 .isc_ntxd_min = {EM_MIN_TXD},
570 .isc_nrxd_max = {EM_MAX_RXD},
571 .isc_ntxd_max = {EM_MAX_TXD},
572 .isc_nrxd_default = {EM_DEFAULT_RXD},
573 .isc_ntxd_default = {EM_DEFAULT_TXD},
576 static struct if_shared_ctx igb_sctx_init = {
577 .isc_magic = IFLIB_MAGIC,
578 .isc_q_align = PAGE_SIZE,
579 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
580 .isc_tx_maxsegsize = PAGE_SIZE,
581 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
582 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
583 .isc_rx_maxsize = MJUM9BYTES,
584 .isc_rx_nsegments = 1,
585 .isc_rx_maxsegsize = MJUM9BYTES,
589 .isc_admin_intrcnt = 1,
590 .isc_vendor_info = igb_vendor_info_array,
591 .isc_driver_version = em_driver_version,
592 .isc_driver = &igb_if_driver,
593 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
595 .isc_nrxd_min = {EM_MIN_RXD},
596 .isc_ntxd_min = {EM_MIN_TXD},
597 .isc_nrxd_max = {IGB_MAX_RXD},
598 .isc_ntxd_max = {IGB_MAX_TXD},
599 .isc_nrxd_default = {EM_DEFAULT_RXD},
600 .isc_ntxd_default = {EM_DEFAULT_TXD},
603 /*****************************************************************
607 ****************************************************************/
608 #define IGB_REGS_LEN 739
610 static int em_get_regs(SYSCTL_HANDLER_ARGS)
612 struct adapter *adapter = (struct adapter *)arg1;
613 struct e1000_hw *hw = &adapter->hw;
618 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK);
619 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
621 rc = sysctl_wire_old_buffer(req, 0);
624 free(regs_buff, M_DEVBUF);
628 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
631 free(regs_buff, M_DEVBUF);
635 /* General Registers */
636 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
637 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
638 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
639 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
640 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
641 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
642 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
643 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
644 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
645 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
646 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
647 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
648 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
649 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
650 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
651 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
652 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
653 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
654 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
655 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
656 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
657 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
659 sbuf_printf(sb, "General Registers\n");
660 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
661 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
662 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]);
664 sbuf_printf(sb, "Interrupt Registers\n");
665 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
667 sbuf_printf(sb, "RX Registers\n");
668 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
669 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
670 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
671 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
672 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
673 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
674 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
676 sbuf_printf(sb, "TX Registers\n");
677 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
678 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
679 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
680 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
681 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
682 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
683 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
684 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
685 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
686 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
687 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
689 free(regs_buff, M_DEVBUF);
693 if_softc_ctx_t scctx = adapter->shared;
694 struct rx_ring *rxr = &rx_que->rxr;
695 struct tx_ring *txr = &tx_que->txr;
696 int ntxd = scctx->isc_ntxd[0];
697 int nrxd = scctx->isc_nrxd[0];
700 for (j = 0; j < nrxd; j++) {
701 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
702 u32 length = le32toh(rxr->rx_base[j].wb.upper.length);
703 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
706 for (j = 0; j < min(ntxd, 256); j++) {
707 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
709 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n",
710 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
711 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
717 rc = sbuf_finish(sb);
723 em_register(device_t dev)
725 return (&em_sctx_init);
729 igb_register(device_t dev)
731 return (&igb_sctx_init);
735 em_set_num_queues(if_ctx_t ctx)
737 struct adapter *adapter = iflib_get_softc(ctx);
740 /* Sanity check based on HW */
741 switch (adapter->hw.mac.type) {
765 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
766 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER
769 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
770 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \
771 IFCAP_LRO | IFCAP_VLAN_HWTSO
774 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
775 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \
776 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\
779 /*********************************************************************
780 * Device initialization routine
782 * The attach entry point is called when the driver is being loaded.
783 * This routine identifies the type of hardware, allocates all resources
784 * and initializes the hardware.
786 * return 0 on success, positive on failure
787 *********************************************************************/
789 em_if_attach_pre(if_ctx_t ctx)
791 struct adapter *adapter;
792 if_softc_ctx_t scctx;
797 INIT_DEBUGOUT("em_if_attach_pre: begin");
798 dev = iflib_get_dev(ctx);
799 adapter = iflib_get_softc(ctx);
801 adapter->ctx = adapter->osdep.ctx = ctx;
802 adapter->dev = adapter->osdep.dev = dev;
803 scctx = adapter->shared = iflib_get_softc_ctx(ctx);
804 adapter->media = iflib_get_media(ctx);
807 adapter->tx_process_limit = scctx->isc_ntxd[0];
810 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
811 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
812 OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
813 adapter, 0, em_sysctl_nvm_info, "I", "NVM Information");
815 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
816 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
817 OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
818 adapter, 0, em_sysctl_debug_info, "I", "Debug Information");
820 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
821 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
822 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
823 adapter, 0, em_set_flowcntl, "I", "Flow Control");
825 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
826 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
827 OID_AUTO, "reg_dump",
828 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 0,
829 em_get_regs, "A", "Dump Registers");
831 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
832 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
834 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, adapter, 0,
835 em_get_rs, "I", "Dump RS indexes");
837 /* Determine hardware and mac info */
838 em_identify_hardware(ctx);
840 scctx->isc_tx_nsegments = EM_MAX_SCATTER;
841 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
843 device_printf(dev, "attach_pre capping queues at %d\n",
844 scctx->isc_ntxqsets_max);
846 if (hw->mac.type >= igb_mac_min) {
847 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
848 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
849 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
850 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
851 scctx->isc_txrx = &igb_txrx;
852 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
853 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
854 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
855 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS;
856 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO |
857 CSUM_IP6_TCP | CSUM_IP6_UDP;
858 if (hw->mac.type != e1000_82575)
859 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
861 ** Some new devices, as with ixgbe, now may
862 ** use a different BAR, so we need to keep
863 ** track of which is used.
865 scctx->isc_msix_bar = pci_msix_table_bar(dev);
866 } else if (hw->mac.type >= em_mac_min) {
867 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
868 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
869 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
870 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
871 scctx->isc_txrx = &em_txrx;
872 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
873 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
874 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
875 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS;
877 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO}
878 * by default as we don't have workarounds for all associated
879 * silicon errata. E. g., with several MACs such as 82573E,
880 * TSO only works at Gigabit speed and otherwise can cause the
881 * hardware to hang (which also would be next to impossible to
882 * work around given that already queued TSO-using descriptors
883 * would need to be flushed and vlan(4) reconfigured at runtime
884 * in case of a link speed change). Moreover, MACs like 82579
885 * still can hang at Gigabit even with all publicly documented
886 * TSO workarounds implemented. Generally, the penality of
887 * these workarounds is rather high and may involve copying
888 * mbuf data around so advantages of TSO lapse. Still, TSO may
889 * work for a few MACs of this class - at least when sticking
890 * with Gigabit - in which case users may enable TSO manually.
892 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
893 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
895 * We support MSI-X with 82574 only, but indicate to iflib(4)
896 * that it shall give MSI at least a try with other devices.
898 if (hw->mac.type == e1000_82574) {
899 scctx->isc_msix_bar = pci_msix_table_bar(dev);;
901 scctx->isc_msix_bar = -1;
902 scctx->isc_disable_msix = 1;
905 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
906 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
907 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
908 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
909 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP;
910 scctx->isc_txrx = &lem_txrx;
911 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS;
912 if (hw->mac.type < e1000_82543)
913 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
914 /* 82541ER doesn't do HW tagging */
915 if (hw->device_id == E1000_DEV_ID_82541ER || hw->device_id == E1000_DEV_ID_82541ER_LOM)
916 scctx->isc_capenable &= ~IFCAP_VLAN_HWTAGGING;
918 scctx->isc_msix_bar = 0;
921 /* Setup PCI resources */
922 if (em_allocate_pci_resources(ctx)) {
923 device_printf(dev, "Allocation of PCI resources failed\n");
929 ** For ICH8 and family we need to
930 ** map the flash memory, and this
931 ** must happen after the MAC is
934 if ((hw->mac.type == e1000_ich8lan) ||
935 (hw->mac.type == e1000_ich9lan) ||
936 (hw->mac.type == e1000_ich10lan) ||
937 (hw->mac.type == e1000_pchlan) ||
938 (hw->mac.type == e1000_pch2lan) ||
939 (hw->mac.type == e1000_pch_lpt)) {
940 int rid = EM_BAR_TYPE_FLASH;
941 adapter->flash = bus_alloc_resource_any(dev,
942 SYS_RES_MEMORY, &rid, RF_ACTIVE);
943 if (adapter->flash == NULL) {
944 device_printf(dev, "Mapping of Flash failed\n");
948 /* This is used in the shared code */
949 hw->flash_address = (u8 *)adapter->flash;
950 adapter->osdep.flash_bus_space_tag =
951 rman_get_bustag(adapter->flash);
952 adapter->osdep.flash_bus_space_handle =
953 rman_get_bushandle(adapter->flash);
956 ** In the new SPT device flash is not a
957 ** separate BAR, rather it is also in BAR0,
958 ** so use the same tag and an offset handle for the
959 ** FLASH read/write macros in the shared code.
961 else if (hw->mac.type >= e1000_pch_spt) {
962 adapter->osdep.flash_bus_space_tag =
963 adapter->osdep.mem_bus_space_tag;
964 adapter->osdep.flash_bus_space_handle =
965 adapter->osdep.mem_bus_space_handle
966 + E1000_FLASH_BASE_ADDR;
969 /* Do Shared Code initialization */
970 error = e1000_setup_init_funcs(hw, TRUE);
972 device_printf(dev, "Setup of Shared code failed, error %d\n",
979 e1000_get_bus_info(hw);
981 /* Set up some sysctls for the tunable interrupt delays */
982 em_add_int_delay_sysctl(adapter, "rx_int_delay",
983 "receive interrupt delay in usecs", &adapter->rx_int_delay,
984 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
985 em_add_int_delay_sysctl(adapter, "tx_int_delay",
986 "transmit interrupt delay in usecs", &adapter->tx_int_delay,
987 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
988 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
989 "receive interrupt delay limit in usecs",
990 &adapter->rx_abs_int_delay,
991 E1000_REGISTER(hw, E1000_RADV),
992 em_rx_abs_int_delay_dflt);
993 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
994 "transmit interrupt delay limit in usecs",
995 &adapter->tx_abs_int_delay,
996 E1000_REGISTER(hw, E1000_TADV),
997 em_tx_abs_int_delay_dflt);
998 em_add_int_delay_sysctl(adapter, "itr",
999 "interrupt delay limit in usecs/4",
1001 E1000_REGISTER(hw, E1000_ITR),
1004 hw->mac.autoneg = DO_AUTO_NEG;
1005 hw->phy.autoneg_wait_to_complete = FALSE;
1006 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1008 if (hw->mac.type < em_mac_min) {
1009 e1000_init_script_state_82541(hw, TRUE);
1010 e1000_set_tbi_compatibility_82543(hw, TRUE);
1012 /* Copper options */
1013 if (hw->phy.media_type == e1000_media_type_copper) {
1014 hw->phy.mdix = AUTO_ALL_MODES;
1015 hw->phy.disable_polarity_correction = FALSE;
1016 hw->phy.ms_type = EM_MASTER_SLAVE;
1020 * Set the frame limits assuming
1021 * standard ethernet sized frames.
1023 scctx->isc_max_frame_size = hw->mac.max_frame_size =
1024 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
1027 * This controls when hardware reports transmit completion
1030 hw->mac.report_tx_early = 1;
1032 /* Allocate multicast array memory. */
1033 adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN *
1034 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
1035 if (adapter->mta == NULL) {
1036 device_printf(dev, "Can not allocate multicast setup array\n");
1041 /* Check SOL/IDER usage */
1042 if (e1000_check_reset_block(hw))
1043 device_printf(dev, "PHY reset is blocked"
1044 " due to SOL/IDER session.\n");
1046 /* Sysctl for setting Energy Efficient Ethernet */
1047 hw->dev_spec.ich8lan.eee_disable = eee_setting;
1048 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1049 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1050 OID_AUTO, "eee_control",
1051 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
1052 adapter, 0, em_sysctl_eee, "I",
1053 "Disable Energy Efficient Ethernet");
1056 ** Start from a known state, this is
1057 ** important in reading the nvm and
1062 /* Make sure we have a good EEPROM before we read from it */
1063 if (e1000_validate_nvm_checksum(hw) < 0) {
1065 ** Some PCI-E parts fail the first check due to
1066 ** the link being in sleep state, call it again,
1067 ** if it fails a second time its a real issue.
1069 if (e1000_validate_nvm_checksum(hw) < 0) {
1071 "The EEPROM Checksum Is Not Valid\n");
1077 /* Copy the permanent MAC address out of the EEPROM */
1078 if (e1000_read_mac_addr(hw) < 0) {
1079 device_printf(dev, "EEPROM read error while reading MAC"
1085 if (!em_is_valid_ether_addr(hw->mac.addr)) {
1086 if (adapter->vf_ifp) {
1087 ether_gen_addr(iflib_get_ifp(ctx),
1088 (struct ether_addr *)hw->mac.addr);
1090 device_printf(dev, "Invalid MAC address\n");
1096 /* Disable ULP support */
1097 e1000_disable_ulp_lpt_lp(hw, TRUE);
1100 * Get Wake-on-Lan and Management info for later use
1104 /* Enable only WOL MAGIC by default */
1105 scctx->isc_capenable &= ~IFCAP_WOL;
1106 if (adapter->wol != 0)
1107 scctx->isc_capenable |= IFCAP_WOL_MAGIC;
1109 iflib_set_mac(ctx, hw->mac.addr);
1114 em_release_hw_control(adapter);
1116 em_free_pci_resources(ctx);
1117 free(adapter->mta, M_DEVBUF);
1123 em_if_attach_post(if_ctx_t ctx)
1125 struct adapter *adapter = iflib_get_softc(ctx);
1126 struct e1000_hw *hw = &adapter->hw;
1129 /* Setup OS specific network interface */
1130 error = em_setup_interface(ctx);
1132 device_printf(adapter->dev, "Interface setup failed: %d\n", error);
1138 /* Initialize statistics */
1139 em_update_stats_counters(adapter);
1140 hw->mac.get_link_status = 1;
1141 em_if_update_admin_status(ctx);
1142 em_add_hw_stats(adapter);
1144 /* Non-AMT based hardware can now take control from firmware */
1145 if (adapter->has_manage && !adapter->has_amt)
1146 em_get_hw_control(adapter);
1148 INIT_DEBUGOUT("em_if_attach_post: end");
1153 /* upon attach_post() error, iflib calls _if_detach() to free resources. */
1157 /*********************************************************************
1158 * Device removal routine
1160 * The detach entry point is called when the driver is being removed.
1161 * This routine stops the adapter and deallocates all the resources
1162 * that were allocated for driver operation.
1164 * return 0 on success, positive on failure
1165 *********************************************************************/
1167 em_if_detach(if_ctx_t ctx)
1169 struct adapter *adapter = iflib_get_softc(ctx);
1171 INIT_DEBUGOUT("em_if_detach: begin");
1173 e1000_phy_hw_reset(&adapter->hw);
1175 em_release_manageability(adapter);
1176 em_release_hw_control(adapter);
1177 em_free_pci_resources(ctx);
1178 free(adapter->mta, M_DEVBUF);
1179 adapter->mta = NULL;
1184 /*********************************************************************
1186 * Shutdown entry point
1188 **********************************************************************/
1191 em_if_shutdown(if_ctx_t ctx)
1193 return em_if_suspend(ctx);
1197 * Suspend/resume device methods.
1200 em_if_suspend(if_ctx_t ctx)
1202 struct adapter *adapter = iflib_get_softc(ctx);
1204 em_release_manageability(adapter);
1205 em_release_hw_control(adapter);
1206 em_enable_wakeup(ctx);
1211 em_if_resume(if_ctx_t ctx)
1213 struct adapter *adapter = iflib_get_softc(ctx);
1215 if (adapter->hw.mac.type == e1000_pch2lan)
1216 e1000_resume_workarounds_pchlan(&adapter->hw);
1218 em_init_manageability(adapter);
1224 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1227 struct adapter *adapter = iflib_get_softc(ctx);
1228 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1230 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1232 switch (adapter->hw.mac.type) {
1236 case e1000_ich10lan:
1246 case e1000_80003es2lan:
1247 /* 9K Jumbo Frame size */
1248 max_frame_size = 9234;
1251 max_frame_size = 4096;
1255 /* Adapters that do not support jumbo frames */
1256 max_frame_size = ETHER_MAX_LEN;
1259 if (adapter->hw.mac.type >= igb_mac_min)
1260 max_frame_size = 9234;
1262 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1264 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1268 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
1269 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1273 /*********************************************************************
1276 * This routine is used in two ways. It is used by the stack as
1277 * init entry point in network interface structure. It is also used
1278 * by the driver as a hw/sw initialization routine to get to a
1281 **********************************************************************/
1283 em_if_init(if_ctx_t ctx)
1285 struct adapter *adapter = iflib_get_softc(ctx);
1286 if_softc_ctx_t scctx = adapter->shared;
1287 struct ifnet *ifp = iflib_get_ifp(ctx);
1288 struct em_tx_queue *tx_que;
1291 INIT_DEBUGOUT("em_if_init: begin");
1293 /* Get the latest mac address, User can use a LAA */
1294 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr,
1297 /* Put the address into the Receive Address Array */
1298 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1301 * With the 82571 adapter, RAR[0] may be overwritten
1302 * when the other port is reset, we make a duplicate
1303 * in RAR[14] for that eventuality, this assures
1304 * the interface continues to function.
1306 if (adapter->hw.mac.type == e1000_82571) {
1307 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1308 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1309 E1000_RAR_ENTRIES - 1);
1313 /* Initialize the hardware */
1315 em_if_update_admin_status(ctx);
1317 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) {
1318 struct tx_ring *txr = &tx_que->txr;
1320 txr->tx_rs_cidx = txr->tx_rs_pidx;
1322 /* Initialize the last processed descriptor to be the end of
1323 * the ring, rather than the start, so that we avoid an
1324 * off-by-one error when calculating how many descriptors are
1325 * done in the credits_update function.
1327 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
1330 /* Setup VLAN support, basic and offload if available */
1331 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1333 /* Clear bad data from Rx FIFOs */
1334 if (adapter->hw.mac.type >= igb_mac_min)
1335 e1000_rx_fifo_flush_base(&adapter->hw);
1337 /* Configure for OS presence */
1338 em_init_manageability(adapter);
1340 /* Prepare transmit descriptors and buffers */
1341 em_initialize_transmit_unit(ctx);
1343 /* Setup Multicast table */
1344 em_if_multi_set(ctx);
1346 adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx);
1347 em_initialize_receive_unit(ctx);
1349 /* Set up VLAN support and filter */
1350 em_setup_vlan_hw_support(adapter);
1352 /* Don't lose promiscuous settings */
1353 em_if_set_promisc(ctx, if_getflags(ifp));
1354 e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1356 /* MSI-X configuration for 82574 */
1357 if (adapter->hw.mac.type == e1000_82574) {
1358 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1360 tmp |= E1000_CTRL_EXT_PBA_CLR;
1361 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1362 /* Set the IVAR - interrupt vector routing. */
1363 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars);
1364 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1365 igb_configure_queues(adapter);
1367 /* this clears any pending interrupts */
1368 E1000_READ_REG(&adapter->hw, E1000_ICR);
1369 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC);
1371 /* AMT based hardware can now take control from firmware */
1372 if (adapter->has_manage && adapter->has_amt)
1373 em_get_hw_control(adapter);
1375 /* Set Energy Efficient Ethernet */
1376 if (adapter->hw.mac.type >= igb_mac_min &&
1377 adapter->hw.phy.media_type == e1000_media_type_copper) {
1378 if (adapter->hw.mac.type == e1000_i354)
1379 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
1381 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
1385 /*********************************************************************
1387 * Fast Legacy/MSI Combined Interrupt Service routine
1389 *********************************************************************/
1393 struct adapter *adapter = arg;
1394 if_ctx_t ctx = adapter->ctx;
1397 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1400 if (reg_icr == 0xffffffff)
1401 return FILTER_STRAY;
1403 /* Definitely not our interrupt. */
1405 return FILTER_STRAY;
1408 * Starting with the 82571 chip, bit 31 should be used to
1409 * determine whether the interrupt belongs to us.
1411 if (adapter->hw.mac.type >= e1000_82571 &&
1412 (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1413 return FILTER_STRAY;
1416 * Only MSI-X interrupts have one-shot behavior by taking advantage
1417 * of the EIAC register. Thus, explicitly disable interrupts. This
1418 * also works around the MSI message reordering errata on certain
1421 IFDI_INTR_DISABLE(ctx);
1423 /* Link status change */
1424 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))
1425 em_handle_link(ctx);
1427 if (reg_icr & E1000_ICR_RXO)
1428 adapter->rx_overruns++;
1430 return (FILTER_SCHEDULE_THREAD);
1434 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1436 struct adapter *adapter = iflib_get_softc(ctx);
1437 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1439 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims);
1444 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1446 struct adapter *adapter = iflib_get_softc(ctx);
1447 struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1449 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims);
1454 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1456 struct adapter *adapter = iflib_get_softc(ctx);
1457 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1459 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims);
1464 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1466 struct adapter *adapter = iflib_get_softc(ctx);
1467 struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1469 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims);
1473 /*********************************************************************
1475 * MSI-X RX Interrupt Service routine
1477 **********************************************************************/
1479 em_msix_que(void *arg)
1481 struct em_rx_queue *que = arg;
1485 return (FILTER_SCHEDULE_THREAD);
1488 /*********************************************************************
1490 * MSI-X Link Fast Interrupt Service routine
1492 **********************************************************************/
1494 em_msix_link(void *arg)
1496 struct adapter *adapter = arg;
1498 bool notlink = false;
1500 ++adapter->link_irq;
1501 MPASS(adapter->hw.back != NULL);
1502 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1504 if (reg_icr & E1000_ICR_RXO)
1505 adapter->rx_overruns++;
1507 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))
1508 em_handle_link(adapter->ctx);
1512 /* Re-arm for other/spurious interrupts */
1513 if (notlink && adapter->hw.mac.type >= igb_mac_min) {
1514 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC);
1515 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1516 } else if (adapter->hw.mac.type == e1000_82574) {
1518 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC |
1521 * Because we must read the ICR for this interrupt it may
1522 * clear other causes using autoclear, for this reason we
1523 * simply create a soft interrupt for all these vectors.
1526 E1000_WRITE_REG(&adapter->hw, E1000_ICS, adapter->ims);
1529 return (FILTER_HANDLED);
1533 em_handle_link(void *context)
1535 if_ctx_t ctx = context;
1536 struct adapter *adapter = iflib_get_softc(ctx);
1538 adapter->hw.mac.get_link_status = 1;
1539 iflib_admin_intr_deferred(ctx);
1542 /*********************************************************************
1544 * Media Ioctl callback
1546 * This routine is called whenever the user queries the status of
1547 * the interface using ifconfig.
1549 **********************************************************************/
1551 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1553 struct adapter *adapter = iflib_get_softc(ctx);
1554 u_char fiber_type = IFM_1000_SX;
1556 INIT_DEBUGOUT("em_if_media_status: begin");
1558 iflib_admin_intr_deferred(ctx);
1560 ifmr->ifm_status = IFM_AVALID;
1561 ifmr->ifm_active = IFM_ETHER;
1563 if (!adapter->link_active) {
1567 ifmr->ifm_status |= IFM_ACTIVE;
1569 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
1570 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1571 if (adapter->hw.mac.type == e1000_82545)
1572 fiber_type = IFM_1000_LX;
1573 ifmr->ifm_active |= fiber_type | IFM_FDX;
1575 switch (adapter->link_speed) {
1577 ifmr->ifm_active |= IFM_10_T;
1580 ifmr->ifm_active |= IFM_100_TX;
1583 ifmr->ifm_active |= IFM_1000_T;
1586 if (adapter->link_duplex == FULL_DUPLEX)
1587 ifmr->ifm_active |= IFM_FDX;
1589 ifmr->ifm_active |= IFM_HDX;
1593 /*********************************************************************
1595 * Media Ioctl callback
1597 * This routine is called when the user changes speed/duplex using
1598 * media/mediopt option with ifconfig.
1600 **********************************************************************/
1602 em_if_media_change(if_ctx_t ctx)
1604 struct adapter *adapter = iflib_get_softc(ctx);
1605 struct ifmedia *ifm = iflib_get_media(ctx);
1607 INIT_DEBUGOUT("em_if_media_change: begin");
1609 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1612 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1614 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1615 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1620 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1621 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1624 adapter->hw.mac.autoneg = FALSE;
1625 adapter->hw.phy.autoneg_advertised = 0;
1626 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1627 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1629 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1632 adapter->hw.mac.autoneg = FALSE;
1633 adapter->hw.phy.autoneg_advertised = 0;
1634 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1635 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1637 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1640 device_printf(adapter->dev, "Unsupported media type\n");
1649 em_if_set_promisc(if_ctx_t ctx, int flags)
1651 struct adapter *adapter = iflib_get_softc(ctx);
1652 struct ifnet *ifp = iflib_get_ifp(ctx);
1656 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1657 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE);
1658 if (flags & IFF_ALLMULTI)
1659 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1661 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES);
1663 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1664 reg_rctl &= (~E1000_RCTL_MPE);
1665 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1667 if (flags & IFF_PROMISC) {
1668 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1669 em_if_vlan_filter_disable(adapter);
1670 /* Turn this on if you want to see bad packets */
1672 reg_rctl |= E1000_RCTL_SBP;
1673 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1675 if (flags & IFF_ALLMULTI) {
1676 reg_rctl |= E1000_RCTL_MPE;
1677 reg_rctl &= ~E1000_RCTL_UPE;
1678 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1680 if (em_if_vlan_filter_used(adapter))
1681 em_if_vlan_filter_enable(adapter);
1687 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx)
1691 if (idx == MAX_NUM_MULTICAST_ADDRESSES)
1694 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1699 /*********************************************************************
1702 * This routine is called whenever multicast address list is updated.
1704 **********************************************************************/
1706 em_if_multi_set(if_ctx_t ctx)
1708 struct adapter *adapter = iflib_get_softc(ctx);
1709 struct ifnet *ifp = iflib_get_ifp(ctx);
1710 u8 *mta; /* Multicast array memory */
1714 IOCTL_DEBUGOUT("em_set_multi: begin");
1717 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1719 if (adapter->hw.mac.type == e1000_82542 &&
1720 adapter->hw.revision_id == E1000_REVISION_2) {
1721 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1722 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1723 e1000_pci_clear_mwi(&adapter->hw);
1724 reg_rctl |= E1000_RCTL_RST;
1725 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1729 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta);
1731 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1733 if (if_getflags(ifp) & IFF_PROMISC)
1734 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1735 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES ||
1736 if_getflags(ifp) & IFF_ALLMULTI) {
1737 reg_rctl |= E1000_RCTL_MPE;
1738 reg_rctl &= ~E1000_RCTL_UPE;
1740 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
1742 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1744 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1745 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
1747 if (adapter->hw.mac.type == e1000_82542 &&
1748 adapter->hw.revision_id == E1000_REVISION_2) {
1749 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1750 reg_rctl &= ~E1000_RCTL_RST;
1751 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1753 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1754 e1000_pci_set_mwi(&adapter->hw);
1758 /*********************************************************************
1761 * This routine schedules em_if_update_admin_status() to check for
1762 * link status and to gather statistics as well as to perform some
1763 * controller-specific hardware patting.
1765 **********************************************************************/
1767 em_if_timer(if_ctx_t ctx, uint16_t qid)
1773 iflib_admin_intr_deferred(ctx);
1777 em_if_update_admin_status(if_ctx_t ctx)
1779 struct adapter *adapter = iflib_get_softc(ctx);
1780 struct e1000_hw *hw = &adapter->hw;
1781 device_t dev = iflib_get_dev(ctx);
1782 u32 link_check, thstat, ctrl;
1784 link_check = thstat = ctrl = 0;
1785 /* Get the cached link value or read phy for real */
1786 switch (hw->phy.media_type) {
1787 case e1000_media_type_copper:
1788 if (hw->mac.get_link_status) {
1789 if (hw->mac.type == e1000_pch_spt)
1791 /* Do the work to read phy */
1792 e1000_check_for_link(hw);
1793 link_check = !hw->mac.get_link_status;
1794 if (link_check) /* ESB2 fix */
1795 e1000_cfg_on_link_up(hw);
1800 case e1000_media_type_fiber:
1801 e1000_check_for_link(hw);
1802 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1805 case e1000_media_type_internal_serdes:
1806 e1000_check_for_link(hw);
1807 link_check = hw->mac.serdes_has_link;
1809 /* VF device is type_unknown */
1810 case e1000_media_type_unknown:
1811 e1000_check_for_link(hw);
1812 link_check = !hw->mac.get_link_status;
1818 /* Check for thermal downshift or shutdown */
1819 if (hw->mac.type == e1000_i350) {
1820 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1821 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1824 /* Now check for a transition */
1825 if (link_check && (adapter->link_active == 0)) {
1826 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
1827 &adapter->link_duplex);
1828 /* Check if we must disable SPEED_MODE bit on PCI-E */
1829 if ((adapter->link_speed != SPEED_1000) &&
1830 ((hw->mac.type == e1000_82571) ||
1831 (hw->mac.type == e1000_82572))) {
1833 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1834 tarc0 &= ~TARC_SPEED_MODE_BIT;
1835 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1838 device_printf(dev, "Link is up %d Mbps %s\n",
1839 adapter->link_speed,
1840 ((adapter->link_duplex == FULL_DUPLEX) ?
1841 "Full Duplex" : "Half Duplex"));
1842 adapter->link_active = 1;
1843 adapter->smartspeed = 0;
1844 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) ==
1845 E1000_CTRL_EXT_LINK_MODE_GMII &&
1846 (thstat & E1000_THSTAT_LINK_THROTTLE))
1847 device_printf(dev, "Link: thermal downshift\n");
1848 /* Delay Link Up for Phy update */
1849 if (((hw->mac.type == e1000_i210) ||
1850 (hw->mac.type == e1000_i211)) &&
1851 (hw->phy.id == I210_I_PHY_ID))
1852 msec_delay(I210_LINK_DELAY);
1853 /* Reset if the media type changed. */
1854 if (hw->dev_spec._82575.media_changed &&
1855 hw->mac.type >= igb_mac_min) {
1856 hw->dev_spec._82575.media_changed = false;
1857 adapter->flags |= IGB_MEDIA_RESET;
1860 iflib_link_state_change(ctx, LINK_STATE_UP,
1861 IF_Mbps(adapter->link_speed));
1862 } else if (!link_check && (adapter->link_active == 1)) {
1863 adapter->link_speed = 0;
1864 adapter->link_duplex = 0;
1865 adapter->link_active = 0;
1866 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
1868 em_update_stats_counters(adapter);
1870 /* Reset LAA into RAR[0] on 82571 */
1871 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw))
1872 e1000_rar_set(hw, hw->mac.addr, 0);
1874 if (hw->mac.type < em_mac_min)
1875 lem_smartspeed(adapter);
1876 else if (hw->mac.type >= igb_mac_min &&
1877 adapter->intr_type == IFLIB_INTR_MSIX) {
1878 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC);
1879 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1880 } else if (hw->mac.type == e1000_82574 &&
1881 adapter->intr_type == IFLIB_INTR_MSIX)
1882 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
1886 em_if_watchdog_reset(if_ctx_t ctx)
1888 struct adapter *adapter = iflib_get_softc(ctx);
1891 * Just count the event; iflib(4) will already trigger a
1892 * sufficient reset of the controller.
1894 adapter->watchdog_events++;
1897 /*********************************************************************
1899 * This routine disables all traffic on the adapter by issuing a
1900 * global reset on the MAC.
1902 **********************************************************************/
1904 em_if_stop(if_ctx_t ctx)
1906 struct adapter *adapter = iflib_get_softc(ctx);
1908 INIT_DEBUGOUT("em_if_stop: begin");
1910 e1000_reset_hw(&adapter->hw);
1911 if (adapter->hw.mac.type >= e1000_82544)
1912 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0);
1914 e1000_led_off(&adapter->hw);
1915 e1000_cleanup_led(&adapter->hw);
1918 /*********************************************************************
1920 * Determine hardware revision.
1922 **********************************************************************/
1924 em_identify_hardware(if_ctx_t ctx)
1926 device_t dev = iflib_get_dev(ctx);
1927 struct adapter *adapter = iflib_get_softc(ctx);
1929 /* Make sure our PCI config space has the necessary stuff set */
1930 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1932 /* Save off the information about this board */
1933 adapter->hw.vendor_id = pci_get_vendor(dev);
1934 adapter->hw.device_id = pci_get_device(dev);
1935 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1936 adapter->hw.subsystem_vendor_id =
1937 pci_read_config(dev, PCIR_SUBVEND_0, 2);
1938 adapter->hw.subsystem_device_id =
1939 pci_read_config(dev, PCIR_SUBDEV_0, 2);
1941 /* Do Shared Code Init and Setup */
1942 if (e1000_set_mac_type(&adapter->hw)) {
1943 device_printf(dev, "Setup init failure\n");
1947 /* Are we a VF device? */
1948 if ((adapter->hw.mac.type == e1000_vfadapt) ||
1949 (adapter->hw.mac.type == e1000_vfadapt_i350))
1950 adapter->vf_ifp = 1;
1952 adapter->vf_ifp = 0;
1956 em_allocate_pci_resources(if_ctx_t ctx)
1958 struct adapter *adapter = iflib_get_softc(ctx);
1959 device_t dev = iflib_get_dev(ctx);
1963 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1965 if (adapter->memory == NULL) {
1966 device_printf(dev, "Unable to allocate bus resource: memory\n");
1969 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory);
1970 adapter->osdep.mem_bus_space_handle =
1971 rman_get_bushandle(adapter->memory);
1972 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle;
1974 /* Only older adapters use IO mapping */
1975 if (adapter->hw.mac.type < em_mac_min &&
1976 adapter->hw.mac.type > e1000_82543) {
1977 /* Figure our where our IO BAR is ? */
1978 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1979 val = pci_read_config(dev, rid, 4);
1980 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1984 /* check for 64bit BAR */
1985 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1988 if (rid >= PCIR_CIS) {
1989 device_printf(dev, "Unable to locate IO BAR\n");
1992 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
1994 if (adapter->ioport == NULL) {
1995 device_printf(dev, "Unable to allocate bus resource: "
1999 adapter->hw.io_base = 0;
2000 adapter->osdep.io_bus_space_tag =
2001 rman_get_bustag(adapter->ioport);
2002 adapter->osdep.io_bus_space_handle =
2003 rman_get_bushandle(adapter->ioport);
2006 adapter->hw.back = &adapter->osdep;
2011 /*********************************************************************
2013 * Set up the MSI-X Interrupt handlers
2015 **********************************************************************/
2017 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
2019 struct adapter *adapter = iflib_get_softc(ctx);
2020 struct em_rx_queue *rx_que = adapter->rx_queues;
2021 struct em_tx_queue *tx_que = adapter->tx_queues;
2022 int error, rid, i, vector = 0, rx_vectors;
2025 /* First set up ring resources */
2026 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) {
2028 snprintf(buf, sizeof(buf), "rxq%d", i);
2029 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
2031 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
2032 adapter->rx_num_queues = i + 1;
2036 rx_que->msix = vector;
2039 * Set the bit to enable interrupt
2040 * in E1000_IMS -- bits 20 and 21
2041 * are for RX0 and RX1, note this has
2042 * NOTHING to do with the MSI-X vector
2044 if (adapter->hw.mac.type == e1000_82574) {
2045 rx_que->eims = 1 << (20 + i);
2046 adapter->ims |= rx_que->eims;
2047 adapter->ivars |= (8 | rx_que->msix) << (i * 4);
2048 } else if (adapter->hw.mac.type == e1000_82575)
2049 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
2051 rx_que->eims = 1 << vector;
2053 rx_vectors = vector;
2056 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) {
2057 snprintf(buf, sizeof(buf), "txq%d", i);
2058 tx_que = &adapter->tx_queues[i];
2059 iflib_softirq_alloc_generic(ctx,
2060 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq,
2061 IFLIB_INTR_TX, tx_que, tx_que->me, buf);
2063 tx_que->msix = (vector % adapter->rx_num_queues);
2066 * Set the bit to enable interrupt
2067 * in E1000_IMS -- bits 22 and 23
2068 * are for TX0 and TX1, note this has
2069 * NOTHING to do with the MSI-X vector
2071 if (adapter->hw.mac.type == e1000_82574) {
2072 tx_que->eims = 1 << (22 + i);
2073 adapter->ims |= tx_que->eims;
2074 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
2075 } else if (adapter->hw.mac.type == e1000_82575) {
2076 tx_que->eims = E1000_EICR_TX_QUEUE0 << i;
2078 tx_que->eims = 1 << i;
2082 /* Link interrupt */
2083 rid = rx_vectors + 1;
2084 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq");
2087 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
2090 adapter->linkvec = rx_vectors;
2091 if (adapter->hw.mac.type < igb_mac_min) {
2092 adapter->ivars |= (8 | rx_vectors) << 16;
2093 adapter->ivars |= 0x80000000;
2094 /* Enable the "Other" interrupt type for link status change */
2095 adapter->ims |= E1000_IMS_OTHER;
2100 iflib_irq_free(ctx, &adapter->irq);
2101 rx_que = adapter->rx_queues;
2102 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++)
2103 iflib_irq_free(ctx, &rx_que->que_irq);
2108 igb_configure_queues(struct adapter *adapter)
2110 struct e1000_hw *hw = &adapter->hw;
2111 struct em_rx_queue *rx_que;
2112 struct em_tx_queue *tx_que;
2113 u32 tmp, ivar = 0, newitr = 0;
2115 /* First turn on RSS capability */
2116 if (hw->mac.type != e1000_82575)
2117 E1000_WRITE_REG(hw, E1000_GPIE,
2118 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
2119 E1000_GPIE_PBA | E1000_GPIE_NSICR);
2122 switch (hw->mac.type) {
2129 case e1000_vfadapt_i350:
2131 for (int i = 0; i < adapter->rx_num_queues; i++) {
2133 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2134 rx_que = &adapter->rx_queues[i];
2137 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2140 ivar |= rx_que->msix | E1000_IVAR_VALID;
2142 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2145 for (int i = 0; i < adapter->tx_num_queues; i++) {
2147 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2148 tx_que = &adapter->tx_queues[i];
2151 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2154 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2156 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2157 adapter->que_mask |= tx_que->eims;
2160 /* And for the link interrupt */
2161 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2162 adapter->link_mask = 1 << adapter->linkvec;
2163 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2167 for (int i = 0; i < adapter->rx_num_queues; i++) {
2168 u32 index = i & 0x7; /* Each IVAR has two entries */
2169 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2170 rx_que = &adapter->rx_queues[i];
2173 ivar |= rx_que->msix | E1000_IVAR_VALID;
2176 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2178 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2179 adapter->que_mask |= rx_que->eims;
2182 for (int i = 0; i < adapter->tx_num_queues; i++) {
2183 u32 index = i & 0x7; /* Each IVAR has two entries */
2184 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2185 tx_que = &adapter->tx_queues[i];
2188 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2191 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2193 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2194 adapter->que_mask |= tx_que->eims;
2197 /* And for the link interrupt */
2198 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2199 adapter->link_mask = 1 << adapter->linkvec;
2200 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2204 /* enable MSI-X support*/
2205 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2206 tmp |= E1000_CTRL_EXT_PBA_CLR;
2207 /* Auto-Mask interrupts upon ICR read. */
2208 tmp |= E1000_CTRL_EXT_EIAME;
2209 tmp |= E1000_CTRL_EXT_IRCA;
2210 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2213 for (int i = 0; i < adapter->rx_num_queues; i++) {
2214 rx_que = &adapter->rx_queues[i];
2215 tmp = E1000_EICR_RX_QUEUE0 << i;
2216 tmp |= E1000_EICR_TX_QUEUE0 << i;
2218 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2220 adapter->que_mask |= rx_que->eims;
2224 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec),
2226 adapter->link_mask |= E1000_EIMS_OTHER;
2231 /* Set the starting interrupt rate */
2232 if (em_max_interrupt_rate > 0)
2233 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2235 if (hw->mac.type == e1000_82575)
2236 newitr |= newitr << 16;
2238 newitr |= E1000_EITR_CNT_IGNR;
2240 for (int i = 0; i < adapter->rx_num_queues; i++) {
2241 rx_que = &adapter->rx_queues[i];
2242 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2249 em_free_pci_resources(if_ctx_t ctx)
2251 struct adapter *adapter = iflib_get_softc(ctx);
2252 struct em_rx_queue *que = adapter->rx_queues;
2253 device_t dev = iflib_get_dev(ctx);
2255 /* Release all MSI-X queue resources */
2256 if (adapter->intr_type == IFLIB_INTR_MSIX)
2257 iflib_irq_free(ctx, &adapter->irq);
2260 for (int i = 0; i < adapter->rx_num_queues; i++, que++) {
2261 iflib_irq_free(ctx, &que->que_irq);
2265 if (adapter->memory != NULL) {
2266 bus_release_resource(dev, SYS_RES_MEMORY,
2267 rman_get_rid(adapter->memory), adapter->memory);
2268 adapter->memory = NULL;
2271 if (adapter->flash != NULL) {
2272 bus_release_resource(dev, SYS_RES_MEMORY,
2273 rman_get_rid(adapter->flash), adapter->flash);
2274 adapter->flash = NULL;
2277 if (adapter->ioport != NULL) {
2278 bus_release_resource(dev, SYS_RES_IOPORT,
2279 rman_get_rid(adapter->ioport), adapter->ioport);
2280 adapter->ioport = NULL;
2284 /* Set up MSI or MSI-X */
2286 em_setup_msix(if_ctx_t ctx)
2288 struct adapter *adapter = iflib_get_softc(ctx);
2290 if (adapter->hw.mac.type == e1000_82574) {
2291 em_enable_vectors_82574(ctx);
2296 /*********************************************************************
2298 * Workaround for SmartSpeed on 82541 and 82547 controllers
2300 **********************************************************************/
2302 lem_smartspeed(struct adapter *adapter)
2306 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) ||
2307 adapter->hw.mac.autoneg == 0 ||
2308 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2311 if (adapter->smartspeed == 0) {
2312 /* If Master/Slave config fault is asserted twice,
2313 * we assume back-to-back */
2314 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2315 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2317 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2318 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2319 e1000_read_phy_reg(&adapter->hw,
2320 PHY_1000T_CTRL, &phy_tmp);
2321 if(phy_tmp & CR_1000T_MS_ENABLE) {
2322 phy_tmp &= ~CR_1000T_MS_ENABLE;
2323 e1000_write_phy_reg(&adapter->hw,
2324 PHY_1000T_CTRL, phy_tmp);
2325 adapter->smartspeed++;
2326 if(adapter->hw.mac.autoneg &&
2327 !e1000_copper_link_autoneg(&adapter->hw) &&
2328 !e1000_read_phy_reg(&adapter->hw,
2329 PHY_CONTROL, &phy_tmp)) {
2330 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2331 MII_CR_RESTART_AUTO_NEG);
2332 e1000_write_phy_reg(&adapter->hw,
2333 PHY_CONTROL, phy_tmp);
2338 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2339 /* If still no link, perhaps using 2/3 pair cable */
2340 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2341 phy_tmp |= CR_1000T_MS_ENABLE;
2342 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2343 if(adapter->hw.mac.autoneg &&
2344 !e1000_copper_link_autoneg(&adapter->hw) &&
2345 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2346 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2347 MII_CR_RESTART_AUTO_NEG);
2348 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2351 /* Restart process after EM_SMARTSPEED_MAX iterations */
2352 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2353 adapter->smartspeed = 0;
2356 /*********************************************************************
2358 * Initialize the DMA Coalescing feature
2360 **********************************************************************/
2362 igb_init_dmac(struct adapter *adapter, u32 pba)
2364 device_t dev = adapter->dev;
2365 struct e1000_hw *hw = &adapter->hw;
2366 u32 dmac, reg = ~E1000_DMACR_DMAC_EN;
2370 if (hw->mac.type == e1000_i211)
2373 max_frame_size = adapter->shared->isc_max_frame_size;
2374 if (hw->mac.type > e1000_82580) {
2376 if (adapter->dmac == 0) { /* Disabling it */
2377 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2380 device_printf(dev, "DMA Coalescing enabled\n");
2382 /* Set starting threshold */
2383 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
2385 hwm = 64 * pba - max_frame_size / 16;
2386 if (hwm < 64 * (pba - 6))
2387 hwm = 64 * (pba - 6);
2388 reg = E1000_READ_REG(hw, E1000_FCRTC);
2389 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
2390 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
2391 & E1000_FCRTC_RTH_COAL_MASK);
2392 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
2395 dmac = pba - max_frame_size / 512;
2396 if (dmac < pba - 10)
2398 reg = E1000_READ_REG(hw, E1000_DMACR);
2399 reg &= ~E1000_DMACR_DMACTHR_MASK;
2400 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT)
2401 & E1000_DMACR_DMACTHR_MASK);
2403 /* transition to L0x or L1 if available..*/
2404 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
2406 /* Check if status is 2.5Gb backplane connection
2407 * before configuration of watchdog timer, which is
2408 * in msec values in 12.8usec intervals
2409 * watchdog timer= msec values in 32usec intervals
2410 * for non 2.5Gb connection
2412 if (hw->mac.type == e1000_i354) {
2413 int status = E1000_READ_REG(hw, E1000_STATUS);
2414 if ((status & E1000_STATUS_2P5_SKU) &&
2415 (!(status & E1000_STATUS_2P5_SKU_OVER)))
2416 reg |= ((adapter->dmac * 5) >> 6);
2418 reg |= (adapter->dmac >> 5);
2420 reg |= (adapter->dmac >> 5);
2423 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2425 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
2427 /* Set the interval before transition */
2428 reg = E1000_READ_REG(hw, E1000_DMCTLX);
2429 if (hw->mac.type == e1000_i350)
2430 reg |= IGB_DMCTLX_DCFLUSH_DIS;
2432 ** in 2.5Gb connection, TTLX unit is 0.4 usec
2433 ** which is 0x4*2 = 0xA. But delay is still 4 usec
2435 if (hw->mac.type == e1000_i354) {
2436 int status = E1000_READ_REG(hw, E1000_STATUS);
2437 if ((status & E1000_STATUS_2P5_SKU) &&
2438 (!(status & E1000_STATUS_2P5_SKU_OVER)))
2446 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
2448 /* free space in tx packet buffer to wake from DMA coal */
2449 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE -
2450 (2 * max_frame_size)) >> 6);
2452 /* make low power state decision controlled by DMA coal */
2453 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2454 reg &= ~E1000_PCIEMISC_LX_DECISION;
2455 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
2457 } else if (hw->mac.type == e1000_82580) {
2458 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2459 E1000_WRITE_REG(hw, E1000_PCIEMISC,
2460 reg & ~E1000_PCIEMISC_LX_DECISION);
2461 E1000_WRITE_REG(hw, E1000_DMACR, 0);
2465 /*********************************************************************
2467 * Initialize the hardware to a configuration as specified by the
2468 * adapter structure.
2470 **********************************************************************/
2472 em_reset(if_ctx_t ctx)
2474 device_t dev = iflib_get_dev(ctx);
2475 struct adapter *adapter = iflib_get_softc(ctx);
2476 struct ifnet *ifp = iflib_get_ifp(ctx);
2477 struct e1000_hw *hw = &adapter->hw;
2481 INIT_DEBUGOUT("em_reset: begin");
2482 /* Let the firmware know the OS is in control */
2483 em_get_hw_control(adapter);
2485 /* Set up smart power down as default off on newer adapters. */
2486 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2487 hw->mac.type == e1000_82572)) {
2490 /* Speed up time to link by disabling smart power down. */
2491 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2492 phy_tmp &= ~IGP02E1000_PM_SPD;
2493 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2497 * Packet Buffer Allocation (PBA)
2498 * Writing PBA sets the receive portion of the buffer
2499 * the remainder is used for the transmit buffer.
2501 switch (hw->mac.type) {
2502 /* 82547: Total Packet Buffer is 40K */
2504 case e1000_82547_rev_2:
2505 if (hw->mac.max_frame_size > 8192)
2506 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
2508 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
2510 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */
2513 case e1000_80003es2lan:
2514 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2516 /* 82573: Total Packet Buffer is 32K */
2518 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2522 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2528 case e1000_ich10lan:
2529 /* Boost Receive side for jumbo frames */
2530 if (hw->mac.max_frame_size > 4096)
2531 pba = E1000_PBA_14K;
2533 pba = E1000_PBA_10K;
2543 pba = E1000_PBA_26K;
2546 pba = E1000_PBA_32K;
2550 pba = E1000_READ_REG(hw, E1000_RXPBS);
2551 pba &= E1000_RXPBS_SIZE_MASK_82576;
2556 case e1000_vfadapt_i350:
2557 pba = E1000_READ_REG(hw, E1000_RXPBS);
2558 pba = e1000_rxpbs_adjust_82580(pba);
2562 pba = E1000_PBA_34K;
2565 /* Remaining devices assumed to have a Packet Buffer of 64K. */
2566 if (hw->mac.max_frame_size > 8192)
2567 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2569 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2572 /* Special needs in case of Jumbo frames */
2573 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) {
2574 u32 tx_space, min_tx, min_rx;
2575 pba = E1000_READ_REG(hw, E1000_PBA);
2576 tx_space = pba >> 16;
2578 min_tx = (hw->mac.max_frame_size +
2579 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
2580 min_tx = roundup2(min_tx, 1024);
2582 min_rx = hw->mac.max_frame_size;
2583 min_rx = roundup2(min_rx, 1024);
2585 if (tx_space < min_tx &&
2586 ((min_tx - tx_space) < pba)) {
2587 pba = pba - (min_tx - tx_space);
2589 * if short on rx space, rx wins
2590 * and must trump tx adjustment
2595 E1000_WRITE_REG(hw, E1000_PBA, pba);
2598 if (hw->mac.type < igb_mac_min)
2599 E1000_WRITE_REG(hw, E1000_PBA, pba);
2601 INIT_DEBUGOUT1("em_reset: pba=%dK",pba);
2604 * These parameters control the automatic generation (Tx) and
2605 * response (Rx) to Ethernet PAUSE frames.
2606 * - High water mark should allow for at least two frames to be
2607 * received after sending an XOFF.
2608 * - Low water mark works best when it is very near the high water mark.
2609 * This allows the receiver to restart by sending XON when it has
2610 * drained a bit. Here we use an arbitrary value of 1500 which will
2611 * restart after one full frame is pulled from the buffer. There
2612 * could be several smaller frames in the buffer and if so they will
2613 * not trigger the XON until their total number reduces the buffer
2615 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2617 rx_buffer_size = (pba & 0xffff) << 10;
2618 hw->fc.high_water = rx_buffer_size -
2619 roundup2(hw->mac.max_frame_size, 1024);
2620 hw->fc.low_water = hw->fc.high_water - 1500;
2622 if (adapter->fc) /* locally set flow control value? */
2623 hw->fc.requested_mode = adapter->fc;
2625 hw->fc.requested_mode = e1000_fc_full;
2627 if (hw->mac.type == e1000_80003es2lan)
2628 hw->fc.pause_time = 0xFFFF;
2630 hw->fc.pause_time = EM_FC_PAUSE_TIME;
2632 hw->fc.send_xon = TRUE;
2634 /* Device specific overrides/settings */
2635 switch (hw->mac.type) {
2637 /* Workaround: no TX flow ctrl for PCH */
2638 hw->fc.requested_mode = e1000_fc_rx_pause;
2639 hw->fc.pause_time = 0xFFFF; /* override */
2640 if (if_getmtu(ifp) > ETHERMTU) {
2641 hw->fc.high_water = 0x3500;
2642 hw->fc.low_water = 0x1500;
2644 hw->fc.high_water = 0x5000;
2645 hw->fc.low_water = 0x3000;
2647 hw->fc.refresh_time = 0x1000;
2656 hw->fc.high_water = 0x5C20;
2657 hw->fc.low_water = 0x5048;
2658 hw->fc.pause_time = 0x0650;
2659 hw->fc.refresh_time = 0x0400;
2660 /* Jumbos need adjusted PBA */
2661 if (if_getmtu(ifp) > ETHERMTU)
2662 E1000_WRITE_REG(hw, E1000_PBA, 12);
2664 E1000_WRITE_REG(hw, E1000_PBA, 26);
2668 /* 8-byte granularity */
2669 hw->fc.low_water = hw->fc.high_water - 8;
2677 case e1000_vfadapt_i350:
2678 /* 16-byte granularity */
2679 hw->fc.low_water = hw->fc.high_water - 16;
2682 case e1000_ich10lan:
2683 if (if_getmtu(ifp) > ETHERMTU) {
2684 hw->fc.high_water = 0x2800;
2685 hw->fc.low_water = hw->fc.high_water - 8;
2690 if (hw->mac.type == e1000_80003es2lan)
2691 hw->fc.pause_time = 0xFFFF;
2695 /* Issue a global reset */
2697 if (hw->mac.type >= igb_mac_min) {
2698 E1000_WRITE_REG(hw, E1000_WUC, 0);
2700 E1000_WRITE_REG(hw, E1000_WUFC, 0);
2701 em_disable_aspm(adapter);
2703 if (adapter->flags & IGB_MEDIA_RESET) {
2704 e1000_setup_init_funcs(hw, TRUE);
2705 e1000_get_bus_info(hw);
2706 adapter->flags &= ~IGB_MEDIA_RESET;
2709 if (e1000_init_hw(hw) < 0) {
2710 device_printf(dev, "Hardware Initialization Failed\n");
2713 if (hw->mac.type >= igb_mac_min)
2714 igb_init_dmac(adapter, pba);
2716 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2717 e1000_get_phy_info(hw);
2718 e1000_check_for_link(hw);
2722 * Initialise the RSS mapping for NICs that support multiple transmit/
2726 #define RSSKEYLEN 10
2728 em_initialize_rss_mapping(struct adapter *adapter)
2730 uint8_t rss_key[4 * RSSKEYLEN];
2732 struct e1000_hw *hw = &adapter->hw;
2738 arc4rand(rss_key, sizeof(rss_key), 0);
2739 for (i = 0; i < RSSKEYLEN; ++i) {
2742 rssrk = EM_RSSRK_VAL(rss_key, i);
2743 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2747 * Configure RSS redirect table in following fashion:
2748 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2750 for (i = 0; i < sizeof(reta); ++i) {
2753 q = (i % adapter->rx_num_queues) << 7;
2754 reta |= q << (8 * i);
2757 for (i = 0; i < 32; ++i)
2758 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2760 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2761 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2762 E1000_MRQC_RSS_FIELD_IPV4 |
2763 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2764 E1000_MRQC_RSS_FIELD_IPV6_EX |
2765 E1000_MRQC_RSS_FIELD_IPV6);
2769 igb_initialize_rss_mapping(struct adapter *adapter)
2771 struct e1000_hw *hw = &adapter->hw;
2775 u32 rss_key[10], mrqc, shift = 0;
2778 if (hw->mac.type == e1000_82575)
2782 * The redirection table controls which destination
2783 * queue each bucket redirects traffic to.
2784 * Each DWORD represents four queues, with the LSB
2785 * being the first queue in the DWORD.
2787 * This just allocates buckets to queues using round-robin
2790 * NOTE: It Just Happens to line up with the default
2791 * RSS allocation method.
2794 /* Warning FM follows */
2796 for (i = 0; i < 128; i++) {
2798 queue_id = rss_get_indirection_to_bucket(i);
2800 * If we have more queues than buckets, we'll
2801 * end up mapping buckets to a subset of the
2804 * If we have more buckets than queues, we'll
2805 * end up instead assigning multiple buckets
2808 * Both are suboptimal, but we need to handle
2809 * the case so we don't go out of bounds
2810 * indexing arrays and such.
2812 queue_id = queue_id % adapter->rx_num_queues;
2814 queue_id = (i % adapter->rx_num_queues);
2816 /* Adjust if required */
2817 queue_id = queue_id << shift;
2820 * The low 8 bits are for hash value (n+0);
2821 * The next 8 bits are for hash value (n+1), etc.
2824 reta = reta | ( ((uint32_t) queue_id) << 24);
2826 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2831 /* Now fill in hash table */
2834 * MRQC: Multiple Receive Queues Command
2835 * Set queuing to RSS control, number depends on the device.
2837 mrqc = E1000_MRQC_ENABLE_RSS_MQ;
2840 /* XXX ew typecasting */
2841 rss_getkey((uint8_t *) &rss_key);
2843 arc4rand(&rss_key, sizeof(rss_key), 0);
2845 for (i = 0; i < 10; i++)
2846 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]);
2849 * Configure the RSS fields to hash upon.
2851 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2852 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2853 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2854 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2855 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2856 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2857 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2858 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2860 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2863 /*********************************************************************
2865 * Setup networking device structure and register interface media.
2867 **********************************************************************/
2869 em_setup_interface(if_ctx_t ctx)
2871 struct ifnet *ifp = iflib_get_ifp(ctx);
2872 struct adapter *adapter = iflib_get_softc(ctx);
2873 if_softc_ctx_t scctx = adapter->shared;
2875 INIT_DEBUGOUT("em_setup_interface: begin");
2878 if (adapter->tx_num_queues == 1) {
2879 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
2880 if_setsendqready(ifp);
2884 * Specify the media types supported by this adapter and register
2885 * callbacks to update media and link information
2887 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2888 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
2889 u_char fiber_type = IFM_1000_SX; /* default type */
2891 if (adapter->hw.mac.type == e1000_82545)
2892 fiber_type = IFM_1000_LX;
2893 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
2894 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2896 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2897 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2898 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2899 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2900 if (adapter->hw.phy.type != e1000_phy_ife) {
2901 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2902 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2905 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2906 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO);
2911 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
2913 struct adapter *adapter = iflib_get_softc(ctx);
2914 if_softc_ctx_t scctx = adapter->shared;
2915 int error = E1000_SUCCESS;
2916 struct em_tx_queue *que;
2919 MPASS(adapter->tx_num_queues > 0);
2920 MPASS(adapter->tx_num_queues == ntxqsets);
2922 /* First allocate the top level queue structs */
2923 if (!(adapter->tx_queues =
2924 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
2925 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2926 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2930 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) {
2931 /* Set up some basics */
2933 struct tx_ring *txr = &que->txr;
2934 txr->adapter = que->adapter = adapter;
2935 que->me = txr->me = i;
2937 /* Allocate report status array */
2938 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2939 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n");
2943 for (j = 0; j < scctx->isc_ntxd[0]; j++)
2944 txr->tx_rsq[j] = QIDX_INVALID;
2945 /* get the virtual and physical address of the hardware queues */
2946 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
2947 txr->tx_paddr = paddrs[i*ntxqs];
2951 device_printf(iflib_get_dev(ctx),
2952 "allocated for %d tx_queues\n", adapter->tx_num_queues);
2955 em_if_queues_free(ctx);
2960 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
2962 struct adapter *adapter = iflib_get_softc(ctx);
2963 int error = E1000_SUCCESS;
2964 struct em_rx_queue *que;
2967 MPASS(adapter->rx_num_queues > 0);
2968 MPASS(adapter->rx_num_queues == nrxqsets);
2970 /* First allocate the top level queue structs */
2971 if (!(adapter->rx_queues =
2972 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
2973 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2974 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2979 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) {
2980 /* Set up some basics */
2981 struct rx_ring *rxr = &que->rxr;
2982 rxr->adapter = que->adapter = adapter;
2984 que->me = rxr->me = i;
2986 /* get the virtual and physical address of the hardware queues */
2987 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
2988 rxr->rx_paddr = paddrs[i*nrxqs];
2992 device_printf(iflib_get_dev(ctx),
2993 "allocated for %d rx_queues\n", adapter->rx_num_queues);
2997 em_if_queues_free(ctx);
3002 em_if_queues_free(if_ctx_t ctx)
3004 struct adapter *adapter = iflib_get_softc(ctx);
3005 struct em_tx_queue *tx_que = adapter->tx_queues;
3006 struct em_rx_queue *rx_que = adapter->rx_queues;
3008 if (tx_que != NULL) {
3009 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
3010 struct tx_ring *txr = &tx_que->txr;
3011 if (txr->tx_rsq == NULL)
3014 free(txr->tx_rsq, M_DEVBUF);
3017 free(adapter->tx_queues, M_DEVBUF);
3018 adapter->tx_queues = NULL;
3021 if (rx_que != NULL) {
3022 free(adapter->rx_queues, M_DEVBUF);
3023 adapter->rx_queues = NULL;
3027 /*********************************************************************
3029 * Enable transmit unit.
3031 **********************************************************************/
3033 em_initialize_transmit_unit(if_ctx_t ctx)
3035 struct adapter *adapter = iflib_get_softc(ctx);
3036 if_softc_ctx_t scctx = adapter->shared;
3037 struct em_tx_queue *que;
3038 struct tx_ring *txr;
3039 struct e1000_hw *hw = &adapter->hw;
3040 u32 tctl, txdctl = 0, tarc, tipg = 0;
3042 INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
3044 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
3048 que = &adapter->tx_queues[i];
3050 bus_addr = txr->tx_paddr;
3052 /* Clear checksum offload context. */
3053 offp = (caddr_t)&txr->csum_flags;
3054 endp = (caddr_t)(txr + 1);
3055 bzero(offp, endp - offp);
3057 /* Base and Len of TX Ring */
3058 E1000_WRITE_REG(hw, E1000_TDLEN(i),
3059 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
3060 E1000_WRITE_REG(hw, E1000_TDBAH(i),
3061 (u32)(bus_addr >> 32));
3062 E1000_WRITE_REG(hw, E1000_TDBAL(i),
3064 /* Init the HEAD/TAIL indices */
3065 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
3066 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
3068 HW_DEBUGOUT2("Base = %x, Length = %x\n",
3069 E1000_READ_REG(hw, E1000_TDBAL(i)),
3070 E1000_READ_REG(hw, E1000_TDLEN(i)));
3072 txdctl = 0; /* clear txdctl */
3073 txdctl |= 0x1f; /* PTHRESH */
3074 txdctl |= 1 << 8; /* HTHRESH */
3075 txdctl |= 1 << 16;/* WTHRESH */
3076 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
3077 txdctl |= E1000_TXDCTL_GRAN;
3078 txdctl |= 1 << 25; /* LWTHRESH */
3080 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
3083 /* Set the default values for the Tx Inter Packet Gap timer */
3084 switch (hw->mac.type) {
3085 case e1000_80003es2lan:
3086 tipg = DEFAULT_82543_TIPG_IPGR1;
3087 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
3088 E1000_TIPG_IPGR2_SHIFT;
3091 tipg = DEFAULT_82542_TIPG_IPGT;
3092 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3093 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3096 if (hw->phy.media_type == e1000_media_type_fiber ||
3097 hw->phy.media_type == e1000_media_type_internal_serdes)
3098 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
3100 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
3101 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3102 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3105 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
3106 E1000_WRITE_REG(hw, E1000_TIDV, adapter->tx_int_delay.value);
3108 if(hw->mac.type >= e1000_82540)
3109 E1000_WRITE_REG(hw, E1000_TADV,
3110 adapter->tx_abs_int_delay.value);
3112 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) {
3113 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3114 tarc |= TARC_SPEED_MODE_BIT;
3115 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3116 } else if (hw->mac.type == e1000_80003es2lan) {
3117 /* errata: program both queues to unweighted RR */
3118 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3120 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3121 tarc = E1000_READ_REG(hw, E1000_TARC(1));
3123 E1000_WRITE_REG(hw, E1000_TARC(1), tarc);
3124 } else if (hw->mac.type == e1000_82574) {
3125 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3126 tarc |= TARC_ERRATA_BIT;
3127 if ( adapter->tx_num_queues > 1) {
3128 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
3129 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3130 E1000_WRITE_REG(hw, E1000_TARC(1), tarc);
3132 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3135 if (adapter->tx_int_delay.value > 0)
3136 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3138 /* Program the Transmit Control Register */
3139 tctl = E1000_READ_REG(hw, E1000_TCTL);
3140 tctl &= ~E1000_TCTL_CT;
3141 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
3142 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
3144 if (hw->mac.type >= e1000_82571)
3145 tctl |= E1000_TCTL_MULR;
3147 /* This write will effectively turn on the transmit unit. */
3148 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
3150 /* SPT and KBL errata workarounds */
3151 if (hw->mac.type == e1000_pch_spt) {
3153 reg = E1000_READ_REG(hw, E1000_IOSFPC);
3154 reg |= E1000_RCTL_RDMTS_HEX;
3155 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
3156 /* i218-i219 Specification Update 1.5.4.5 */
3157 reg = E1000_READ_REG(hw, E1000_TARC(0));
3158 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3159 reg |= E1000_TARC0_CB_MULTIQ_2_REQ;
3160 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3164 /*********************************************************************
3166 * Enable receive unit.
3168 **********************************************************************/
3169 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1)
3172 em_initialize_receive_unit(if_ctx_t ctx)
3174 struct adapter *adapter = iflib_get_softc(ctx);
3175 if_softc_ctx_t scctx = adapter->shared;
3176 struct ifnet *ifp = iflib_get_ifp(ctx);
3177 struct e1000_hw *hw = &adapter->hw;
3178 struct em_rx_queue *que;
3180 uint32_t rctl, rxcsum;
3182 INIT_DEBUGOUT("em_initialize_receive_units: begin");
3185 * Make sure receives are disabled while setting
3186 * up the descriptor ring
3188 rctl = E1000_READ_REG(hw, E1000_RCTL);
3189 /* Do not disable if ever enabled on this hardware */
3190 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
3191 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3193 /* Setup the Receive Control Register */
3194 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3195 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3196 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3197 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3199 /* Do not store bad packets */
3200 rctl &= ~E1000_RCTL_SBP;
3202 /* Enable Long Packet receive */
3203 if (if_getmtu(ifp) > ETHERMTU)
3204 rctl |= E1000_RCTL_LPE;
3206 rctl &= ~E1000_RCTL_LPE;
3209 if (!em_disable_crc_stripping)
3210 rctl |= E1000_RCTL_SECRC;
3212 if (hw->mac.type >= e1000_82540) {
3213 E1000_WRITE_REG(hw, E1000_RADV,
3214 adapter->rx_abs_int_delay.value);
3217 * Set the interrupt throttling rate. Value is calculated
3218 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
3220 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
3222 E1000_WRITE_REG(hw, E1000_RDTR, adapter->rx_int_delay.value);
3224 if (hw->mac.type >= em_mac_min) {
3226 /* Use extended rx descriptor formats */
3227 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3228 rfctl |= E1000_RFCTL_EXTEN;
3231 * When using MSI-X interrupts we need to throttle
3232 * using the EITR register (82574 only)
3234 if (hw->mac.type == e1000_82574) {
3235 for (int i = 0; i < 4; i++)
3236 E1000_WRITE_REG(hw, E1000_EITR_82574(i),
3238 /* Disable accelerated acknowledge */
3239 rfctl |= E1000_RFCTL_ACK_DIS;
3241 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3244 /* Set up L3 and L4 csum Rx descriptor offloads */
3245 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
3246 if (scctx->isc_capenable & IFCAP_RXCSUM) {
3247 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
3248 if (hw->mac.type > e1000_82575)
3249 rxcsum |= E1000_RXCSUM_CRCOFL;
3250 else if (hw->mac.type < em_mac_min &&
3251 scctx->isc_capenable & IFCAP_HWCSUM_IPV6)
3252 rxcsum |= E1000_RXCSUM_IPV6OFL;
3254 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
3255 if (hw->mac.type > e1000_82575)
3256 rxcsum &= ~E1000_RXCSUM_CRCOFL;
3257 else if (hw->mac.type < em_mac_min)
3258 rxcsum &= ~E1000_RXCSUM_IPV6OFL;
3261 if (adapter->rx_num_queues > 1) {
3262 /* RSS hash needed in the Rx descriptor */
3263 rxcsum |= E1000_RXCSUM_PCSD;
3265 if (hw->mac.type >= igb_mac_min)
3266 igb_initialize_rss_mapping(adapter);
3268 em_initialize_rss_mapping(adapter);
3270 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
3273 * XXX TEMPORARY WORKAROUND: on some systems with 82573
3274 * long latencies are observed, like Lenovo X60. This
3275 * change eliminates the problem, but since having positive
3276 * values in RDTR is a known source of problems on other
3277 * platforms another solution is being sought.
3279 if (hw->mac.type == e1000_82573)
3280 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
3282 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3283 struct rx_ring *rxr = &que->rxr;
3284 /* Setup the Base and Length of the Rx Descriptor Ring */
3285 u64 bus_addr = rxr->rx_paddr;
3287 u32 rdt = adapter->rx_num_queues -1; /* default */
3290 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3291 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
3292 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
3293 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
3294 /* Setup the Head and Tail Descriptor Pointers */
3295 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
3296 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
3300 * Set PTHRESH for improved jumbo performance
3301 * According to 10.2.5.11 of Intel 82574 Datasheet,
3302 * RXDCTL(1) is written whenever RXDCTL(0) is written.
3303 * Only write to RXDCTL(1) if there is a need for different
3306 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan ||
3307 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) {
3308 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
3309 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
3310 } else if (hw->mac.type == e1000_82574) {
3311 for (int i = 0; i < adapter->rx_num_queues; i++) {
3312 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3313 rxdctl |= 0x20; /* PTHRESH */
3314 rxdctl |= 4 << 8; /* HTHRESH */
3315 rxdctl |= 4 << 16;/* WTHRESH */
3316 rxdctl |= 1 << 24; /* Switch to granularity */
3317 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3319 } else if (hw->mac.type >= igb_mac_min) {
3320 u32 psize, srrctl = 0;
3322 if (if_getmtu(ifp) > ETHERMTU) {
3323 psize = scctx->isc_max_frame_size;
3324 /* are we on a vlan? */
3325 if (ifp->if_vlantrunk != NULL)
3326 psize += VLAN_TAG_SIZE;
3328 if (adapter->vf_ifp)
3329 e1000_rlpml_set_vf(hw, psize);
3331 E1000_WRITE_REG(hw, E1000_RLPML, psize);
3334 /* Set maximum packet buffer len */
3335 srrctl |= (adapter->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >>
3336 E1000_SRRCTL_BSIZEPKT_SHIFT;
3339 * If TX flow control is disabled and there's >1 queue defined,
3342 * This drops frames rather than hanging the RX MAC for all queues.
3344 if ((adapter->rx_num_queues > 1) &&
3345 (adapter->fc == e1000_fc_none ||
3346 adapter->fc == e1000_fc_rx_pause)) {
3347 srrctl |= E1000_SRRCTL_DROP_EN;
3349 /* Setup the Base and Length of the Rx Descriptor Rings */
3350 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3351 struct rx_ring *rxr = &que->rxr;
3352 u64 bus_addr = rxr->rx_paddr;
3356 /* Configure for header split? -- ignore for now */
3357 rxr->hdr_split = igb_header_split;
3359 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3362 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3363 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3364 E1000_WRITE_REG(hw, E1000_RDBAH(i),
3365 (uint32_t)(bus_addr >> 32));
3366 E1000_WRITE_REG(hw, E1000_RDBAL(i),
3367 (uint32_t)bus_addr);
3368 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3369 /* Enable this Queue */
3370 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3371 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3372 rxdctl &= 0xFFF00000;
3373 rxdctl |= IGB_RX_PTHRESH;
3374 rxdctl |= IGB_RX_HTHRESH << 8;
3375 rxdctl |= IGB_RX_WTHRESH << 16;
3376 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3378 } else if (hw->mac.type >= e1000_pch2lan) {
3379 if (if_getmtu(ifp) > ETHERMTU)
3380 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
3382 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
3385 /* Make sure VLAN Filters are off */
3386 rctl &= ~E1000_RCTL_VFE;
3388 /* Set up packet buffer size, overridden by per queue srrctl on igb */
3389 if (hw->mac.type < igb_mac_min) {
3390 if (adapter->rx_mbuf_sz > 2048 && adapter->rx_mbuf_sz <= 4096)
3391 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3392 else if (adapter->rx_mbuf_sz > 4096 && adapter->rx_mbuf_sz <= 8192)
3393 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3394 else if (adapter->rx_mbuf_sz > 8192)
3395 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX;
3397 rctl |= E1000_RCTL_SZ_2048;
3398 rctl &= ~E1000_RCTL_BSEX;
3401 rctl |= E1000_RCTL_SZ_2048;
3404 * rctl bits 11:10 are as follows
3408 * and should be 00 on all of the above
3410 rctl &= ~0x00000C00;
3412 /* Write out the settings */
3413 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3419 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3421 struct adapter *adapter = iflib_get_softc(ctx);
3424 index = (vtag >> 5) & 0x7F;
3426 adapter->shadow_vfta[index] |= (1 << bit);
3427 ++adapter->num_vlans;
3428 em_if_vlan_filter_write(adapter);
3432 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3434 struct adapter *adapter = iflib_get_softc(ctx);
3437 index = (vtag >> 5) & 0x7F;
3439 adapter->shadow_vfta[index] &= ~(1 << bit);
3440 --adapter->num_vlans;
3441 em_if_vlan_filter_write(adapter);
3445 em_if_vlan_filter_capable(struct adapter *adapter)
3447 if_softc_ctx_t scctx = adapter->shared;
3449 if ((scctx->isc_capenable & IFCAP_VLAN_HWFILTER) &&
3450 !em_disable_crc_stripping)
3457 em_if_vlan_filter_used(struct adapter *adapter)
3459 if (!em_if_vlan_filter_capable(adapter))
3462 for (int i = 0; i < EM_VFTA_SIZE; i++)
3463 if (adapter->shadow_vfta[i] != 0)
3470 em_if_vlan_filter_enable(struct adapter *adapter)
3472 struct e1000_hw *hw = &adapter->hw;
3475 reg = E1000_READ_REG(hw, E1000_RCTL);
3476 reg &= ~E1000_RCTL_CFIEN;
3477 reg |= E1000_RCTL_VFE;
3478 E1000_WRITE_REG(hw, E1000_RCTL, reg);
3482 em_if_vlan_filter_disable(struct adapter *adapter)
3484 struct e1000_hw *hw = &adapter->hw;
3487 reg = E1000_READ_REG(hw, E1000_RCTL);
3488 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
3489 E1000_WRITE_REG(hw, E1000_RCTL, reg);
3493 em_if_vlan_filter_write(struct adapter *adapter)
3495 struct e1000_hw *hw = &adapter->hw;
3497 if (adapter->vf_ifp)
3500 /* Disable interrupts for lem-class devices during the filter change */
3501 if (hw->mac.type < em_mac_min)
3502 em_if_intr_disable(adapter->ctx);
3504 for (int i = 0; i < EM_VFTA_SIZE; i++)
3505 if (adapter->shadow_vfta[i] != 0) {
3506 /* XXXKB: incomplete VF support, we return early above */
3507 if (adapter->vf_ifp)
3508 e1000_vfta_set_vf(hw, adapter->shadow_vfta[i], TRUE);
3510 e1000_write_vfta(hw, i, adapter->shadow_vfta[i]);
3513 /* Re-enable interrupts for lem-class devices */
3514 if (hw->mac.type < em_mac_min)
3515 em_if_intr_enable(adapter->ctx);
3519 em_setup_vlan_hw_support(struct adapter *adapter)
3521 if_softc_ctx_t scctx = adapter->shared;
3522 struct e1000_hw *hw = &adapter->hw;
3525 /* XXXKB: Return early if we are a VF until VF decap and filter management
3526 * is ready and tested.
3528 if (adapter->vf_ifp)
3531 if (scctx->isc_capenable & IFCAP_VLAN_HWTAGGING &&
3532 !em_disable_crc_stripping) {
3533 reg = E1000_READ_REG(hw, E1000_CTRL);
3534 reg |= E1000_CTRL_VME;
3535 E1000_WRITE_REG(hw, E1000_CTRL, reg);
3537 reg = E1000_READ_REG(hw, E1000_CTRL);
3538 reg &= ~E1000_CTRL_VME;
3539 E1000_WRITE_REG(hw, E1000_CTRL, reg);
3542 /* If we aren't doing HW filtering, we're done */
3543 if (!em_if_vlan_filter_capable(adapter)) {
3544 em_if_vlan_filter_disable(adapter);
3549 * A soft reset zero's out the VFTA, so
3550 * we need to repopulate it now.
3552 em_if_vlan_filter_write(adapter);
3554 /* Enable the Filter Table */
3555 em_if_vlan_filter_enable(adapter);
3559 em_if_intr_enable(if_ctx_t ctx)
3561 struct adapter *adapter = iflib_get_softc(ctx);
3562 struct e1000_hw *hw = &adapter->hw;
3563 u32 ims_mask = IMS_ENABLE_MASK;
3565 if (adapter->intr_type == IFLIB_INTR_MSIX) {
3566 E1000_WRITE_REG(hw, EM_EIAC, adapter->ims);
3567 ims_mask |= adapter->ims;
3569 E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3570 E1000_WRITE_FLUSH(hw);
3574 em_if_intr_disable(if_ctx_t ctx)
3576 struct adapter *adapter = iflib_get_softc(ctx);
3577 struct e1000_hw *hw = &adapter->hw;
3579 if (adapter->intr_type == IFLIB_INTR_MSIX)
3580 E1000_WRITE_REG(hw, EM_EIAC, 0);
3581 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3582 E1000_WRITE_FLUSH(hw);
3586 igb_if_intr_enable(if_ctx_t ctx)
3588 struct adapter *adapter = iflib_get_softc(ctx);
3589 struct e1000_hw *hw = &adapter->hw;
3592 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) {
3593 mask = (adapter->que_mask | adapter->link_mask);
3594 E1000_WRITE_REG(hw, E1000_EIAC, mask);
3595 E1000_WRITE_REG(hw, E1000_EIAM, mask);
3596 E1000_WRITE_REG(hw, E1000_EIMS, mask);
3597 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
3599 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
3600 E1000_WRITE_FLUSH(hw);
3604 igb_if_intr_disable(if_ctx_t ctx)
3606 struct adapter *adapter = iflib_get_softc(ctx);
3607 struct e1000_hw *hw = &adapter->hw;
3609 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) {
3610 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff);
3611 E1000_WRITE_REG(hw, E1000_EIAC, 0);
3613 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3614 E1000_WRITE_FLUSH(hw);
3618 * Bit of a misnomer, what this really means is
3619 * to enable OS management of the system... aka
3620 * to disable special hardware management features
3623 em_init_manageability(struct adapter *adapter)
3625 /* A shared code workaround */
3626 #define E1000_82542_MANC2H E1000_MANC2H
3627 if (adapter->has_manage) {
3628 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3629 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3631 /* disable hardware interception of ARP */
3632 manc &= ~(E1000_MANC_ARP_EN);
3634 /* enable receiving management packets to the host */
3635 manc |= E1000_MANC_EN_MNG2HOST;
3636 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3637 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3638 manc2h |= E1000_MNG2HOST_PORT_623;
3639 manc2h |= E1000_MNG2HOST_PORT_664;
3640 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3641 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3646 * Give control back to hardware management
3647 * controller if there is one.
3650 em_release_manageability(struct adapter *adapter)
3652 if (adapter->has_manage) {
3653 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3655 /* re-enable hardware interception of ARP */
3656 manc |= E1000_MANC_ARP_EN;
3657 manc &= ~E1000_MANC_EN_MNG2HOST;
3659 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3664 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3665 * For ASF and Pass Through versions of f/w this means
3666 * that the driver is loaded. For AMT version type f/w
3667 * this means that the network i/f is open.
3670 em_get_hw_control(struct adapter *adapter)
3674 if (adapter->vf_ifp)
3677 if (adapter->hw.mac.type == e1000_82573) {
3678 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3679 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3680 swsm | E1000_SWSM_DRV_LOAD);
3684 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3685 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3686 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3690 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3691 * For ASF and Pass Through versions of f/w this means that
3692 * the driver is no longer loaded. For AMT versions of the
3693 * f/w this means that the network i/f is closed.
3696 em_release_hw_control(struct adapter *adapter)
3700 if (!adapter->has_manage)
3703 if (adapter->hw.mac.type == e1000_82573) {
3704 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3705 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3706 swsm & ~E1000_SWSM_DRV_LOAD);
3710 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3711 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3712 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3717 em_is_valid_ether_addr(u8 *addr)
3719 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3721 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3729 ** Parse the interface capabilities with regard
3730 ** to both system management and wake-on-lan for
3734 em_get_wakeup(if_ctx_t ctx)
3736 struct adapter *adapter = iflib_get_softc(ctx);
3737 device_t dev = iflib_get_dev(ctx);
3738 u16 eeprom_data = 0, device_id, apme_mask;
3740 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
3741 apme_mask = EM_EEPROM_APME;
3743 switch (adapter->hw.mac.type) {
3748 e1000_read_nvm(&adapter->hw,
3749 NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3750 apme_mask = EM_82544_APME;
3753 case e1000_82546_rev_3:
3754 if (adapter->hw.bus.func == 1) {
3755 e1000_read_nvm(&adapter->hw,
3756 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3759 e1000_read_nvm(&adapter->hw,
3760 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3764 adapter->has_amt = TRUE;
3768 case e1000_80003es2lan:
3769 if (adapter->hw.bus.func == 1) {
3770 e1000_read_nvm(&adapter->hw,
3771 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3774 e1000_read_nvm(&adapter->hw,
3775 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3779 case e1000_ich10lan:
3784 case e1000_82575: /* listing all igb devices */
3792 case e1000_vfadapt_i350:
3793 apme_mask = E1000_WUC_APME;
3794 adapter->has_amt = TRUE;
3795 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
3798 e1000_read_nvm(&adapter->hw,
3799 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3802 if (eeprom_data & apme_mask)
3803 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
3805 * We have the eeprom settings, now apply the special cases
3806 * where the eeprom may be wrong or the board won't support
3807 * wake on lan on a particular port
3809 device_id = pci_get_device(dev);
3810 switch (device_id) {
3811 case E1000_DEV_ID_82546GB_PCIE:
3814 case E1000_DEV_ID_82546EB_FIBER:
3815 case E1000_DEV_ID_82546GB_FIBER:
3816 /* Wake events only supported on port A for dual fiber
3817 * regardless of eeprom setting */
3818 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3819 E1000_STATUS_FUNC_1)
3822 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
3823 /* if quad port adapter, disable WoL on all but port A */
3824 if (global_quad_port_a != 0)
3826 /* Reset for multiple quad port adapters */
3827 if (++global_quad_port_a == 4)
3828 global_quad_port_a = 0;
3830 case E1000_DEV_ID_82571EB_FIBER:
3831 /* Wake events only supported on port A for dual fiber
3832 * regardless of eeprom setting */
3833 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3834 E1000_STATUS_FUNC_1)
3837 case E1000_DEV_ID_82571EB_QUAD_COPPER:
3838 case E1000_DEV_ID_82571EB_QUAD_FIBER:
3839 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
3840 /* if quad port adapter, disable WoL on all but port A */
3841 if (global_quad_port_a != 0)
3843 /* Reset for multiple quad port adapters */
3844 if (++global_quad_port_a == 4)
3845 global_quad_port_a = 0;
3853 * Enable PCI Wake On Lan capability
3856 em_enable_wakeup(if_ctx_t ctx)
3858 struct adapter *adapter = iflib_get_softc(ctx);
3859 device_t dev = iflib_get_dev(ctx);
3860 if_t ifp = iflib_get_ifp(ctx);
3862 u32 pmc, ctrl, ctrl_ext, rctl;
3865 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
3869 * Determine type of Wakeup: note that wol
3870 * is set with all bits on by default.
3872 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
3873 adapter->wol &= ~E1000_WUFC_MAG;
3875 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
3876 adapter->wol &= ~E1000_WUFC_EX;
3878 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
3879 adapter->wol &= ~E1000_WUFC_MC;
3881 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3882 rctl |= E1000_RCTL_MPE;
3883 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3886 if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC)))
3889 /* Advertise the wakeup capability */
3890 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
3891 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
3892 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
3894 /* Keep the laser running on Fiber adapters */
3895 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3896 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
3897 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3898 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
3899 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext);
3902 if ((adapter->hw.mac.type == e1000_ich8lan) ||
3903 (adapter->hw.mac.type == e1000_pchlan) ||
3904 (adapter->hw.mac.type == e1000_ich9lan) ||
3905 (adapter->hw.mac.type == e1000_ich10lan))
3906 e1000_suspend_workarounds_ich8lan(&adapter->hw);
3908 if ( adapter->hw.mac.type >= e1000_pchlan) {
3909 error = em_enable_phy_wakeup(adapter);
3913 /* Enable wakeup by the MAC */
3914 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
3915 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
3918 if (adapter->hw.phy.type == e1000_phy_igp_3)
3919 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
3922 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
3923 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3924 if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
3925 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3926 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
3932 * WOL in the newer chipset interfaces (pchlan)
3933 * require thing to be copied into the phy
3936 em_enable_phy_wakeup(struct adapter *adapter)
3938 struct e1000_hw *hw = &adapter->hw;
3942 /* copy MAC RARs to PHY RARs */
3943 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
3945 /* copy MAC MTA to PHY MTA */
3946 for (int i = 0; i < hw->mac.mta_reg_count; i++) {
3947 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
3948 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
3949 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
3950 (u16)((mreg >> 16) & 0xFFFF));
3953 /* configure PHY Rx Control register */
3954 e1000_read_phy_reg(hw, BM_RCTL, &preg);
3955 mreg = E1000_READ_REG(hw, E1000_RCTL);
3956 if (mreg & E1000_RCTL_UPE)
3957 preg |= BM_RCTL_UPE;
3958 if (mreg & E1000_RCTL_MPE)
3959 preg |= BM_RCTL_MPE;
3960 preg &= ~(BM_RCTL_MO_MASK);
3961 if (mreg & E1000_RCTL_MO_3)
3962 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
3963 << BM_RCTL_MO_SHIFT);
3964 if (mreg & E1000_RCTL_BAM)
3965 preg |= BM_RCTL_BAM;
3966 if (mreg & E1000_RCTL_PMCF)
3967 preg |= BM_RCTL_PMCF;
3968 mreg = E1000_READ_REG(hw, E1000_CTRL);
3969 if (mreg & E1000_CTRL_RFCE)
3970 preg |= BM_RCTL_RFCE;
3971 e1000_write_phy_reg(hw, BM_RCTL, preg);
3973 /* enable PHY wakeup in MAC register */
3974 E1000_WRITE_REG(hw, E1000_WUC,
3975 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
3976 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol);
3978 /* configure and enable PHY wakeup in PHY registers */
3979 e1000_write_phy_reg(hw, BM_WUFC, adapter->wol);
3980 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN);
3982 /* activate PHY wakeup */
3983 ret = hw->phy.ops.acquire(hw);
3985 printf("Could not acquire PHY\n");
3988 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3989 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3990 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
3992 printf("Could not read PHY page 769\n");
3995 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
3996 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
3998 printf("Could not set PHY Host Wakeup bit\n");
4000 hw->phy.ops.release(hw);
4006 em_if_led_func(if_ctx_t ctx, int onoff)
4008 struct adapter *adapter = iflib_get_softc(ctx);
4011 e1000_setup_led(&adapter->hw);
4012 e1000_led_on(&adapter->hw);
4014 e1000_led_off(&adapter->hw);
4015 e1000_cleanup_led(&adapter->hw);
4020 * Disable the L0S and L1 LINK states
4023 em_disable_aspm(struct adapter *adapter)
4026 u16 link_cap,link_ctrl;
4027 device_t dev = adapter->dev;
4029 switch (adapter->hw.mac.type) {
4037 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
4039 reg = base + PCIER_LINK_CAP;
4040 link_cap = pci_read_config(dev, reg, 2);
4041 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
4043 reg = base + PCIER_LINK_CTL;
4044 link_ctrl = pci_read_config(dev, reg, 2);
4045 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
4046 pci_write_config(dev, reg, link_ctrl, 2);
4050 /**********************************************************************
4052 * Update the board statistics counters.
4054 **********************************************************************/
4056 em_update_stats_counters(struct adapter *adapter)
4058 u64 prev_xoffrxc = adapter->stats.xoffrxc;
4060 if(adapter->hw.phy.media_type == e1000_media_type_copper ||
4061 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
4062 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
4063 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
4065 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
4066 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
4067 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
4068 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
4070 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
4071 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
4072 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
4073 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
4074 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
4075 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
4076 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
4077 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
4079 ** For watchdog management we need to know if we have been
4080 ** paused during the last interval, so capture that here.
4082 if (adapter->stats.xoffrxc != prev_xoffrxc)
4083 adapter->shared->isc_pause_frames = 1;
4084 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
4085 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
4086 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
4087 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
4088 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
4089 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
4090 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
4091 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
4092 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
4093 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
4094 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
4095 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
4097 /* For the 64-bit byte counters the low dword must be read first. */
4098 /* Both registers clear on the read of the high dword */
4100 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) +
4101 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32);
4102 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) +
4103 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32);
4105 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
4106 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
4107 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
4108 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
4109 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
4111 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
4112 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
4114 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
4115 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
4116 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
4117 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
4118 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
4119 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
4120 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
4121 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
4122 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
4123 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
4125 /* Interrupt Counts */
4127 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC);
4128 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC);
4129 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC);
4130 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC);
4131 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC);
4132 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC);
4133 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC);
4134 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC);
4135 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC);
4137 if (adapter->hw.mac.type >= e1000_82543) {
4138 adapter->stats.algnerrc +=
4139 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
4140 adapter->stats.rxerrc +=
4141 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
4142 adapter->stats.tncrs +=
4143 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
4144 adapter->stats.cexterr +=
4145 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
4146 adapter->stats.tsctc +=
4147 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
4148 adapter->stats.tsctfc +=
4149 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
4154 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
4156 struct adapter *adapter = iflib_get_softc(ctx);
4157 struct ifnet *ifp = iflib_get_ifp(ctx);
4160 case IFCOUNTER_COLLISIONS:
4161 return (adapter->stats.colc);
4162 case IFCOUNTER_IERRORS:
4163 return (adapter->dropped_pkts + adapter->stats.rxerrc +
4164 adapter->stats.crcerrs + adapter->stats.algnerrc +
4165 adapter->stats.ruc + adapter->stats.roc +
4166 adapter->stats.mpc + adapter->stats.cexterr);
4167 case IFCOUNTER_OERRORS:
4168 return (adapter->stats.ecol + adapter->stats.latecol +
4169 adapter->watchdog_events);
4171 return (if_get_counter_default(ifp, cnt));
4175 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized
4176 * @ctx: iflib context
4177 * @event: event code to check
4179 * Defaults to returning true for unknown events.
4181 * @returns true if iflib needs to reinit the interface
4184 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
4187 case IFLIB_RESTART_VLAN_CONFIG:
4194 /* Export a single 32-bit register via a read-only sysctl. */
4196 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
4198 struct adapter *adapter;
4201 adapter = oidp->oid_arg1;
4202 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2);
4203 return (sysctl_handle_int(oidp, &val, 0, req));
4207 * Add sysctl variables, one per statistic, to the system.
4210 em_add_hw_stats(struct adapter *adapter)
4212 device_t dev = iflib_get_dev(adapter->ctx);
4213 struct em_tx_queue *tx_que = adapter->tx_queues;
4214 struct em_rx_queue *rx_que = adapter->rx_queues;
4216 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
4217 struct sysctl_oid *tree = device_get_sysctl_tree(dev);
4218 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
4219 struct e1000_hw_stats *stats = &adapter->stats;
4221 struct sysctl_oid *stat_node, *queue_node, *int_node;
4222 struct sysctl_oid_list *stat_list, *queue_list, *int_list;
4224 #define QUEUE_NAME_LEN 32
4225 char namebuf[QUEUE_NAME_LEN];
4227 /* Driver Statistics */
4228 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
4229 CTLFLAG_RD, &adapter->dropped_pkts,
4230 "Driver dropped packets");
4231 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
4232 CTLFLAG_RD, &adapter->link_irq,
4233 "Link MSI-X IRQ Handled");
4234 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
4235 CTLFLAG_RD, &adapter->rx_overruns,
4237 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
4238 CTLFLAG_RD, &adapter->watchdog_events,
4239 "Watchdog timeouts");
4240 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
4241 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
4242 adapter, E1000_CTRL, em_sysctl_reg_handler, "IU",
4243 "Device Control Register");
4244 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
4245 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
4246 adapter, E1000_RCTL, em_sysctl_reg_handler, "IU",
4247 "Receiver Control Register");
4248 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
4249 CTLFLAG_RD, &adapter->hw.fc.high_water, 0,
4250 "Flow Control High Watermark");
4251 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
4252 CTLFLAG_RD, &adapter->hw.fc.low_water, 0,
4253 "Flow Control Low Watermark");
4255 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
4256 struct tx_ring *txr = &tx_que->txr;
4257 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
4258 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4259 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name");
4260 queue_list = SYSCTL_CHILDREN(queue_node);
4262 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
4263 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4264 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU",
4265 "Transmit Descriptor Head");
4266 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
4267 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4268 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU",
4269 "Transmit Descriptor Tail");
4270 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
4271 CTLFLAG_RD, &txr->tx_irq,
4272 "Queue MSI-X Transmit Interrupts");
4275 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) {
4276 struct rx_ring *rxr = &rx_que->rxr;
4277 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
4278 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4279 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name");
4280 queue_list = SYSCTL_CHILDREN(queue_node);
4282 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
4283 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4284 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU",
4285 "Receive Descriptor Head");
4286 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
4287 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4288 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU",
4289 "Receive Descriptor Tail");
4290 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
4291 CTLFLAG_RD, &rxr->rx_irq,
4292 "Queue MSI-X Receive Interrupts");
4295 /* MAC stats get their own sub node */
4297 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
4298 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics");
4299 stat_list = SYSCTL_CHILDREN(stat_node);
4301 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
4302 CTLFLAG_RD, &stats->ecol,
4303 "Excessive collisions");
4304 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
4305 CTLFLAG_RD, &stats->scc,
4306 "Single collisions");
4307 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
4308 CTLFLAG_RD, &stats->mcc,
4309 "Multiple collisions");
4310 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
4311 CTLFLAG_RD, &stats->latecol,
4313 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
4314 CTLFLAG_RD, &stats->colc,
4316 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
4317 CTLFLAG_RD, &adapter->stats.symerrs,
4319 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
4320 CTLFLAG_RD, &adapter->stats.sec,
4322 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
4323 CTLFLAG_RD, &adapter->stats.dc,
4325 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
4326 CTLFLAG_RD, &adapter->stats.mpc,
4328 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
4329 CTLFLAG_RD, &adapter->stats.rnbc,
4330 "Receive No Buffers");
4331 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
4332 CTLFLAG_RD, &adapter->stats.ruc,
4333 "Receive Undersize");
4334 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
4335 CTLFLAG_RD, &adapter->stats.rfc,
4336 "Fragmented Packets Received ");
4337 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
4338 CTLFLAG_RD, &adapter->stats.roc,
4339 "Oversized Packets Received");
4340 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
4341 CTLFLAG_RD, &adapter->stats.rjc,
4343 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
4344 CTLFLAG_RD, &adapter->stats.rxerrc,
4346 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
4347 CTLFLAG_RD, &adapter->stats.crcerrs,
4349 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
4350 CTLFLAG_RD, &adapter->stats.algnerrc,
4351 "Alignment Errors");
4352 /* On 82575 these are collision counts */
4353 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
4354 CTLFLAG_RD, &adapter->stats.cexterr,
4355 "Collision/Carrier extension errors");
4356 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
4357 CTLFLAG_RD, &adapter->stats.xonrxc,
4359 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
4360 CTLFLAG_RD, &adapter->stats.xontxc,
4362 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
4363 CTLFLAG_RD, &adapter->stats.xoffrxc,
4365 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
4366 CTLFLAG_RD, &adapter->stats.xofftxc,
4367 "XOFF Transmitted");
4369 /* Packet Reception Stats */
4370 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
4371 CTLFLAG_RD, &adapter->stats.tpr,
4372 "Total Packets Received ");
4373 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
4374 CTLFLAG_RD, &adapter->stats.gprc,
4375 "Good Packets Received");
4376 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
4377 CTLFLAG_RD, &adapter->stats.bprc,
4378 "Broadcast Packets Received");
4379 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
4380 CTLFLAG_RD, &adapter->stats.mprc,
4381 "Multicast Packets Received");
4382 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
4383 CTLFLAG_RD, &adapter->stats.prc64,
4384 "64 byte frames received ");
4385 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
4386 CTLFLAG_RD, &adapter->stats.prc127,
4387 "65-127 byte frames received");
4388 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
4389 CTLFLAG_RD, &adapter->stats.prc255,
4390 "128-255 byte frames received");
4391 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
4392 CTLFLAG_RD, &adapter->stats.prc511,
4393 "256-511 byte frames received");
4394 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
4395 CTLFLAG_RD, &adapter->stats.prc1023,
4396 "512-1023 byte frames received");
4397 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
4398 CTLFLAG_RD, &adapter->stats.prc1522,
4399 "1023-1522 byte frames received");
4400 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
4401 CTLFLAG_RD, &adapter->stats.gorc,
4402 "Good Octets Received");
4404 /* Packet Transmission Stats */
4405 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
4406 CTLFLAG_RD, &adapter->stats.gotc,
4407 "Good Octets Transmitted");
4408 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
4409 CTLFLAG_RD, &adapter->stats.tpt,
4410 "Total Packets Transmitted");
4411 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
4412 CTLFLAG_RD, &adapter->stats.gptc,
4413 "Good Packets Transmitted");
4414 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
4415 CTLFLAG_RD, &adapter->stats.bptc,
4416 "Broadcast Packets Transmitted");
4417 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
4418 CTLFLAG_RD, &adapter->stats.mptc,
4419 "Multicast Packets Transmitted");
4420 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
4421 CTLFLAG_RD, &adapter->stats.ptc64,
4422 "64 byte frames transmitted ");
4423 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
4424 CTLFLAG_RD, &adapter->stats.ptc127,
4425 "65-127 byte frames transmitted");
4426 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
4427 CTLFLAG_RD, &adapter->stats.ptc255,
4428 "128-255 byte frames transmitted");
4429 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
4430 CTLFLAG_RD, &adapter->stats.ptc511,
4431 "256-511 byte frames transmitted");
4432 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
4433 CTLFLAG_RD, &adapter->stats.ptc1023,
4434 "512-1023 byte frames transmitted");
4435 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
4436 CTLFLAG_RD, &adapter->stats.ptc1522,
4437 "1024-1522 byte frames transmitted");
4438 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
4439 CTLFLAG_RD, &adapter->stats.tsctc,
4440 "TSO Contexts Transmitted");
4441 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
4442 CTLFLAG_RD, &adapter->stats.tsctfc,
4443 "TSO Contexts Failed");
4446 /* Interrupt Stats */
4448 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
4449 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics");
4450 int_list = SYSCTL_CHILDREN(int_node);
4452 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
4453 CTLFLAG_RD, &adapter->stats.iac,
4454 "Interrupt Assertion Count");
4456 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
4457 CTLFLAG_RD, &adapter->stats.icrxptc,
4458 "Interrupt Cause Rx Pkt Timer Expire Count");
4460 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
4461 CTLFLAG_RD, &adapter->stats.icrxatc,
4462 "Interrupt Cause Rx Abs Timer Expire Count");
4464 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
4465 CTLFLAG_RD, &adapter->stats.ictxptc,
4466 "Interrupt Cause Tx Pkt Timer Expire Count");
4468 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
4469 CTLFLAG_RD, &adapter->stats.ictxatc,
4470 "Interrupt Cause Tx Abs Timer Expire Count");
4472 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
4473 CTLFLAG_RD, &adapter->stats.ictxqec,
4474 "Interrupt Cause Tx Queue Empty Count");
4476 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
4477 CTLFLAG_RD, &adapter->stats.ictxqmtc,
4478 "Interrupt Cause Tx Queue Min Thresh Count");
4480 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
4481 CTLFLAG_RD, &adapter->stats.icrxdmtc,
4482 "Interrupt Cause Rx Desc Min Thresh Count");
4484 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
4485 CTLFLAG_RD, &adapter->stats.icrxoc,
4486 "Interrupt Cause Receiver Overrun Count");
4489 /**********************************************************************
4491 * This routine provides a way to dump out the adapter eeprom,
4492 * often a useful debug/service tool. This only dumps the first
4493 * 32 words, stuff that matters is in that extent.
4495 **********************************************************************/
4497 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4499 struct adapter *adapter = (struct adapter *)arg1;
4504 error = sysctl_handle_int(oidp, &result, 0, req);
4506 if (error || !req->newptr)
4510 * This value will cause a hex dump of the
4511 * first 32 16-bit words of the EEPROM to
4515 em_print_nvm_info(adapter);
4521 em_print_nvm_info(struct adapter *adapter)
4526 /* Its a bit crude, but it gets the job done */
4527 printf("\nInterface EEPROM Dump:\n");
4528 printf("Offset\n0x0000 ");
4529 for (i = 0, j = 0; i < 32; i++, j++) {
4530 if (j == 8) { /* Make the offset block */
4532 printf("\n0x00%x0 ",row);
4534 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
4535 printf("%04x ", eeprom_data);
4541 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4543 struct em_int_delay_info *info;
4544 struct adapter *adapter;
4546 int error, usecs, ticks;
4548 info = (struct em_int_delay_info *) arg1;
4549 usecs = info->value;
4550 error = sysctl_handle_int(oidp, &usecs, 0, req);
4551 if (error != 0 || req->newptr == NULL)
4553 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4555 info->value = usecs;
4556 ticks = EM_USECS_TO_TICKS(usecs);
4557 if (info->offset == E1000_ITR) /* units are 256ns here */
4560 adapter = info->adapter;
4562 regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
4563 regval = (regval & ~0xffff) | (ticks & 0xffff);
4564 /* Handle a few special cases. */
4565 switch (info->offset) {
4570 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
4571 /* Don't write 0 into the TIDV register. */
4574 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
4577 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
4582 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
4583 const char *description, struct em_int_delay_info *info,
4584 int offset, int value)
4586 info->adapter = adapter;
4587 info->offset = offset;
4588 info->value = value;
4589 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev),
4590 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4591 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
4592 info, 0, em_sysctl_int_delay, "I", description);
4596 * Set flow control using sysctl:
4597 * Flow control values:
4604 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4607 static int input = 3; /* default is full */
4608 struct adapter *adapter = (struct adapter *) arg1;
4610 error = sysctl_handle_int(oidp, &input, 0, req);
4612 if ((error) || (req->newptr == NULL))
4615 if (input == adapter->fc) /* no change? */
4619 case e1000_fc_rx_pause:
4620 case e1000_fc_tx_pause:
4623 adapter->hw.fc.requested_mode = input;
4624 adapter->fc = input;
4631 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
4632 e1000_force_mac_fc(&adapter->hw);
4637 * Manage Energy Efficient Ethernet:
4639 * 0/1 - enabled/disabled
4642 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4644 struct adapter *adapter = (struct adapter *) arg1;
4647 value = adapter->hw.dev_spec.ich8lan.eee_disable;
4648 error = sysctl_handle_int(oidp, &value, 0, req);
4649 if (error || req->newptr == NULL)
4651 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4652 em_if_init(adapter->ctx);
4658 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4660 struct adapter *adapter;
4665 error = sysctl_handle_int(oidp, &result, 0, req);
4667 if (error || !req->newptr)
4671 adapter = (struct adapter *) arg1;
4672 em_print_debug_info(adapter);
4679 em_get_rs(SYSCTL_HANDLER_ARGS)
4681 struct adapter *adapter = (struct adapter *) arg1;
4686 error = sysctl_handle_int(oidp, &result, 0, req);
4688 if (error || !req->newptr || result != 1)
4690 em_dump_rs(adapter);
4696 em_if_debug(if_ctx_t ctx)
4698 em_dump_rs(iflib_get_softc(ctx));
4702 * This routine is meant to be fluid, add whatever is
4703 * needed for debugging a problem. -jfv
4706 em_print_debug_info(struct adapter *adapter)
4708 device_t dev = iflib_get_dev(adapter->ctx);
4709 struct ifnet *ifp = iflib_get_ifp(adapter->ctx);
4710 struct tx_ring *txr = &adapter->tx_queues->txr;
4711 struct rx_ring *rxr = &adapter->rx_queues->rxr;
4713 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
4714 printf("Interface is RUNNING ");
4716 printf("Interface is NOT RUNNING\n");
4718 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
4719 printf("and INACTIVE\n");
4721 printf("and ACTIVE\n");
4723 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
4724 device_printf(dev, "TX Queue %d ------\n", i);
4725 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
4726 E1000_READ_REG(&adapter->hw, E1000_TDH(i)),
4727 E1000_READ_REG(&adapter->hw, E1000_TDT(i)));
4730 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) {
4731 device_printf(dev, "RX Queue %d ------\n", j);
4732 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
4733 E1000_READ_REG(&adapter->hw, E1000_RDH(j)),
4734 E1000_READ_REG(&adapter->hw, E1000_RDT(j)));
4740 * Write a new value to the EEPROM increasing the number of MSI-X
4741 * vectors from 3 to 5, for proper multiqueue support.
4744 em_enable_vectors_82574(if_ctx_t ctx)
4746 struct adapter *adapter = iflib_get_softc(ctx);
4747 struct e1000_hw *hw = &adapter->hw;
4748 device_t dev = iflib_get_dev(ctx);
4751 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4753 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata);
4754 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
4755 device_printf(dev, "Writing to eeprom: increasing "
4756 "reported MSI-X vectors from 3 to 5...\n");
4757 edata &= ~(EM_NVM_MSIX_N_MASK);
4758 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
4759 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4760 e1000_update_nvm_checksum(hw);
4761 device_printf(dev, "Writing to eeprom: done\n");