sys/dev/e1000/if_em.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /* $FreeBSD$ */
  30 #include "if_em.h"
  31 #include <sys/sbuf.h>
  32 #include <machine/_inttypes.h>
  33
  34 #define em_mac_min e1000_82547
  35 #define igb_mac_min e1000_82575
  36
  37 /*********************************************************************
  38  *  Driver version:
  39  *********************************************************************/
  40 char em_driver_version[] = "7.6.1-k";
  41
  42 /*********************************************************************
  43  *  PCI Device ID Table
  44  *
  45  *  Used by probe to select devices to load on
  46  *  Last field stores an index into e1000_strings
  47  *  Last entry must be all 0s
  48  *
  49  *  { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
  50  *********************************************************************/
  51
  52 static pci_vendor_info_t em_vendor_info_array[] =
  53 {
  54         /* Intel(R) PRO/1000 Network Connection - Legacy em*/
  55         PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"),
  56         PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"),
  57         PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"),
  58         PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"),
  59         PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"),
  60
  61         PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"),
  62         PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"),
  63         PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"),
  64         PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  65         PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"),
  66         PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"),
  67         PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  68
  69         PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"),
  70
  71         PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"),
  72         PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
  73
  74         PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
  75         PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
  76         PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
  77         PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"),
  78
  79         PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"),
  80         PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"),
  81         PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"),
  82         PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"),
  83         PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"),
  84
  85         PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  86         PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
  87         PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
  88         PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  89         PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"),
  90         PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"),
  91         PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"),
  92         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
  93         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"),
  94
  95         PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"),
  96         PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  97         PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"),
  98
  99         /* Intel(R) PRO/1000 Network Connection - em */
 100         PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
 101         PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
 102         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"),
 103         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"),
 104         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"),
 105         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 106         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"),
 107         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"),
 108         PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 109         PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"),
 110         PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
 111         PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
 112         PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"),
 113         PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"),
 114         PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"),
 115         PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"),
 116         PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"),
 117         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"),
 118         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"),
 119         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"),
 120         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"),
 121         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
 122         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 123         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"),
 124         PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"),
 125         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
 126         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"),
 127         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"),
 128         PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"),
 129         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
 130         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 131         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"),
 132         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"),
 133         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"),
 134         PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"),
 135         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
 136         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"),
 137         PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"),
 138         PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"),
 139         PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"),
 140         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"),
 141         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"),
 142         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"),
 143         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"),
 144         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"),
 145         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"),
 146         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"),
 147         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"),
 148         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"),
 149         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"),
 150         PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"),
 151         PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"),
 152         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"),
 153         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"),
 154         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"),
 155         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"),
 156         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"),
 157         PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"),
 158         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"),
 159         PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"),
 160         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"),
 161         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"),
 162         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"),
 163         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"),
 164         PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"),
 165         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"),
 166         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"),
 167         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"),
 168         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"),
 169         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) PRO/1000 Network Connection"),
 170         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) PRO/1000 Network Connection"),
 171         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) PRO/1000 Network Connection"),
 172         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) PRO/1000 Network Connection"),
 173         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) PRO/1000 Network Connection"),
 174         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) PRO/1000 Network Connection"),
 175         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) PRO/1000 Network Connection"),
 176         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) PRO/1000 Network Connection"),
 177         /* required last entry */
 178         PVID_END
 179 };
 180
 181 static pci_vendor_info_t igb_vendor_info_array[] =
 182 {
 183         /* Intel(R) PRO/1000 Network Connection - igb */
 184         PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 185         PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 186         PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 187         PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 188         PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 189         PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 190         PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 191         PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 192         PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 193         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 194         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 195         PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 196         PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 197         PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 198         PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 199         PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 200         PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 201         PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 202         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 203         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 204         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 205         PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 206         PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 207         PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 208         PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 209         PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 210         PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 211         PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 212         PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 213         PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 214         PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 215         PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 216         PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 217         PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 218         PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 219         PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 220         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 221         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 222         PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 223         /* required last entry */
 224         PVID_END
 225 };
 226
 227 /*********************************************************************
 228  *  Function prototypes
 229  *********************************************************************/
 230 static void     *em_register(device_t dev);
 231 static void     *igb_register(device_t dev);
 232 static int      em_if_attach_pre(if_ctx_t ctx);
 233 static int      em_if_attach_post(if_ctx_t ctx);
 234 static int      em_if_detach(if_ctx_t ctx);
 235 static int      em_if_shutdown(if_ctx_t ctx);
 236 static int      em_if_suspend(if_ctx_t ctx);
 237 static int      em_if_resume(if_ctx_t ctx);
 238
 239 static int      em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets);
 240 static int      em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets);
 241 static void     em_if_queues_free(if_ctx_t ctx);
 242
 243 static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
 244 static void     em_if_init(if_ctx_t ctx);
 245 static void     em_if_stop(if_ctx_t ctx);
 246 static void     em_if_media_status(if_ctx_t, struct ifmediareq *);
 247 static int      em_if_media_change(if_ctx_t ctx);
 248 static int      em_if_mtu_set(if_ctx_t ctx, uint32_t mtu);
 249 static void     em_if_timer(if_ctx_t ctx, uint16_t qid);
 250 static void     em_if_vlan_register(if_ctx_t ctx, u16 vtag);
 251 static void     em_if_vlan_unregister(if_ctx_t ctx, u16 vtag);
 252 static void     em_if_watchdog_reset(if_ctx_t ctx);
 253
 254 static void     em_identify_hardware(if_ctx_t ctx);
 255 static int      em_allocate_pci_resources(if_ctx_t ctx);
 256 static void     em_free_pci_resources(if_ctx_t ctx);
 257 static void     em_reset(if_ctx_t ctx);
 258 static int      em_setup_interface(if_ctx_t ctx);
 259 static int      em_setup_msix(if_ctx_t ctx);
 260
 261 static void     em_initialize_transmit_unit(if_ctx_t ctx);
 262 static void     em_initialize_receive_unit(if_ctx_t ctx);
 263
 264 static void     em_if_intr_enable(if_ctx_t ctx);
 265 static void     em_if_intr_disable(if_ctx_t ctx);
 266 static void     igb_if_intr_enable(if_ctx_t ctx);
 267 static void     igb_if_intr_disable(if_ctx_t ctx);
 268 static int      em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 269 static int      em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
 270 static int      igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 271 static int      igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
 272 static void     em_if_multi_set(if_ctx_t ctx);
 273 static void     em_if_update_admin_status(if_ctx_t ctx);
 274 static void     em_if_debug(if_ctx_t ctx);
 275 static void     em_update_stats_counters(struct adapter *);
 276 static void     em_add_hw_stats(struct adapter *adapter);
 277 static int      em_if_set_promisc(if_ctx_t ctx, int flags);
 278 static void     em_setup_vlan_hw_support(struct adapter *);
 279 static int      em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
 280 static void     em_print_nvm_info(struct adapter *);
 281 static int      em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 282 static int      em_get_rs(SYSCTL_HANDLER_ARGS);
 283 static void     em_print_debug_info(struct adapter *);
 284 static int      em_is_valid_ether_addr(u8 *);
 285 static int      em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
 286 static void     em_add_int_delay_sysctl(struct adapter *, const char *,
 287                     const char *, struct em_int_delay_info *, int, int);
 288 /* Management and WOL Support */
 289 static void     em_init_manageability(struct adapter *);
 290 static void     em_release_manageability(struct adapter *);
 291 static void     em_get_hw_control(struct adapter *);
 292 static void     em_release_hw_control(struct adapter *);
 293 static void     em_get_wakeup(if_ctx_t ctx);
 294 static void     em_enable_wakeup(if_ctx_t ctx);
 295 static int      em_enable_phy_wakeup(struct adapter *);
 296 static void     em_disable_aspm(struct adapter *);
 297
 298 int             em_intr(void *arg);
 299 static void     em_disable_promisc(if_ctx_t ctx);
 300
 301 /* MSI-X handlers */
 302 static int      em_if_msix_intr_assign(if_ctx_t, int);
 303 static int      em_msix_link(void *);
 304 static void     em_handle_link(void *context);
 305
 306 static void     em_enable_vectors_82574(if_ctx_t);
 307
 308 static int      em_set_flowcntl(SYSCTL_HANDLER_ARGS);
 309 static int      em_sysctl_eee(SYSCTL_HANDLER_ARGS);
 310 static void     em_if_led_func(if_ctx_t ctx, int onoff);
 311
 312 static int      em_get_regs(SYSCTL_HANDLER_ARGS);
 313
 314 static void     lem_smartspeed(struct adapter *adapter);
 315 static void     igb_configure_queues(struct adapter *adapter);
 316
 317
 318 /*********************************************************************
 319  *  FreeBSD Device Interface Entry Points
 320  *********************************************************************/
 321 static device_method_t em_methods[] = {
 322         /* Device interface */
 323         DEVMETHOD(device_register, em_register),
 324         DEVMETHOD(device_probe, iflib_device_probe),
 325         DEVMETHOD(device_attach, iflib_device_attach),
 326         DEVMETHOD(device_detach, iflib_device_detach),
 327         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 328         DEVMETHOD(device_suspend, iflib_device_suspend),
 329         DEVMETHOD(device_resume, iflib_device_resume),
 330         DEVMETHOD_END
 331 };
 332
 333 static device_method_t igb_methods[] = {
 334         /* Device interface */
 335         DEVMETHOD(device_register, igb_register),
 336         DEVMETHOD(device_probe, iflib_device_probe),
 337         DEVMETHOD(device_attach, iflib_device_attach),
 338         DEVMETHOD(device_detach, iflib_device_detach),
 339         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 340         DEVMETHOD(device_suspend, iflib_device_suspend),
 341         DEVMETHOD(device_resume, iflib_device_resume),
 342         DEVMETHOD_END
 343 };
 344
 345
 346 static driver_t em_driver = {
 347         "em", em_methods, sizeof(struct adapter),
 348 };
 349
 350 static devclass_t em_devclass;
 351 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
 352
 353 MODULE_DEPEND(em, pci, 1, 1, 1);
 354 MODULE_DEPEND(em, ether, 1, 1, 1);
 355 MODULE_DEPEND(em, iflib, 1, 1, 1);
 356
 357 IFLIB_PNP_INFO(pci, em, em_vendor_info_array);
 358
 359 static driver_t igb_driver = {
 360         "igb", igb_methods, sizeof(struct adapter),
 361 };
 362
 363 static devclass_t igb_devclass;
 364 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
 365
 366 MODULE_DEPEND(igb, pci, 1, 1, 1);
 367 MODULE_DEPEND(igb, ether, 1, 1, 1);
 368 MODULE_DEPEND(igb, iflib, 1, 1, 1);
 369
 370 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array);
 371
 372 static device_method_t em_if_methods[] = {
 373         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 374         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 375         DEVMETHOD(ifdi_detach, em_if_detach),
 376         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 377         DEVMETHOD(ifdi_suspend, em_if_suspend),
 378         DEVMETHOD(ifdi_resume, em_if_resume),
 379         DEVMETHOD(ifdi_init, em_if_init),
 380         DEVMETHOD(ifdi_stop, em_if_stop),
 381         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 382         DEVMETHOD(ifdi_intr_enable, em_if_intr_enable),
 383         DEVMETHOD(ifdi_intr_disable, em_if_intr_disable),
 384         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 385         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 386         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 387         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 388         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 389         DEVMETHOD(ifdi_media_status, em_if_media_status),
 390         DEVMETHOD(ifdi_media_change, em_if_media_change),
 391         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 392         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 393         DEVMETHOD(ifdi_timer, em_if_timer),
 394         DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
 395         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 396         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 397         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 398         DEVMETHOD(ifdi_led_func, em_if_led_func),
 399         DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable),
 400         DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable),
 401         DEVMETHOD(ifdi_debug, em_if_debug),
 402         DEVMETHOD_END
 403 };
 404
 405 static driver_t em_if_driver = {
 406         "em_if", em_if_methods, sizeof(struct adapter)
 407 };
 408
 409 static device_method_t igb_if_methods[] = {
 410         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 411         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 412         DEVMETHOD(ifdi_detach, em_if_detach),
 413         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 414         DEVMETHOD(ifdi_suspend, em_if_suspend),
 415         DEVMETHOD(ifdi_resume, em_if_resume),
 416         DEVMETHOD(ifdi_init, em_if_init),
 417         DEVMETHOD(ifdi_stop, em_if_stop),
 418         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 419         DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable),
 420         DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable),
 421         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 422         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 423         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 424         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 425         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 426         DEVMETHOD(ifdi_media_status, em_if_media_status),
 427         DEVMETHOD(ifdi_media_change, em_if_media_change),
 428         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 429         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 430         DEVMETHOD(ifdi_timer, em_if_timer),
 431         DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
 432         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 433         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 434         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 435         DEVMETHOD(ifdi_led_func, em_if_led_func),
 436         DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable),
 437         DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable),
 438         DEVMETHOD(ifdi_debug, em_if_debug),
 439         DEVMETHOD_END
 440 };
 441
 442 static driver_t igb_if_driver = {
 443         "igb_if", igb_if_methods, sizeof(struct adapter)
 444 };
 445
 446 /*********************************************************************
 447  *  Tunable default values.
 448  *********************************************************************/
 449
 450 #define EM_TICKS_TO_USECS(ticks)        ((1024 * (ticks) + 500) / 1000)
 451 #define EM_USECS_TO_TICKS(usecs)        ((1000 * (usecs) + 512) / 1024)
 452
 453 #define MAX_INTS_PER_SEC        8000
 454 #define DEFAULT_ITR             (1000000000/(MAX_INTS_PER_SEC * 256))
 455
 456 /* Allow common code without TSO */
 457 #ifndef CSUM_TSO
 458 #define CSUM_TSO        0
 459 #endif
 460
 461 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters");
 462
 463 static int em_disable_crc_stripping = 0;
 464 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
 465     &em_disable_crc_stripping, 0, "Disable CRC Stripping");
 466
 467 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
 468 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
 469 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
 470     0, "Default transmit interrupt delay in usecs");
 471 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
 472     0, "Default receive interrupt delay in usecs");
 473
 474 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
 475 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
 476 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
 477     &em_tx_abs_int_delay_dflt, 0,
 478     "Default transmit interrupt delay limit in usecs");
 479 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
 480     &em_rx_abs_int_delay_dflt, 0,
 481     "Default receive interrupt delay limit in usecs");
 482
 483 static int em_smart_pwr_down = FALSE;
 484 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
 485     0, "Set to true to leave smart power down enabled on newer adapters");
 486
 487 /* Controls whether promiscuous also shows bad packets */
 488 static int em_debug_sbp = TRUE;
 489 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
 490     "Show bad packets in promiscuous mode");
 491
 492 /* How many packets rxeof tries to clean at a time */
 493 static int em_rx_process_limit = 100;
 494 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
 495     &em_rx_process_limit, 0,
 496     "Maximum number of received packets to process "
 497     "at a time, -1 means unlimited");
 498
 499 /* Energy efficient ethernet - default to OFF */
 500 static int eee_setting = 1;
 501 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
 502     "Enable Energy Efficient Ethernet");
 503
 504 /*
 505 ** Tuneable Interrupt rate
 506 */
 507 static int em_max_interrupt_rate = 8000;
 508 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
 509     &em_max_interrupt_rate, 0, "Maximum interrupts per second");
 510
 511
 512
 513 /* Global used in WOL setup with multiport cards */
 514 static int global_quad_port_a = 0;
 515
 516 extern struct if_txrx igb_txrx;
 517 extern struct if_txrx em_txrx;
 518 extern struct if_txrx lem_txrx;
 519
 520 static struct if_shared_ctx em_sctx_init = {
 521         .isc_magic = IFLIB_MAGIC,
 522         .isc_q_align = PAGE_SIZE,
 523         .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 524         .isc_tx_maxsegsize = PAGE_SIZE,
 525         .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 526         .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
 527         .isc_rx_maxsize = MJUM9BYTES,
 528         .isc_rx_nsegments = 1,
 529         .isc_rx_maxsegsize = MJUM9BYTES,
 530         .isc_nfl = 1,
 531         .isc_nrxqs = 1,
 532         .isc_ntxqs = 1,
 533         .isc_admin_intrcnt = 1,
 534         .isc_vendor_info = em_vendor_info_array,
 535         .isc_driver_version = em_driver_version,
 536         .isc_driver = &em_if_driver,
 537         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 538
 539         .isc_nrxd_min = {EM_MIN_RXD},
 540         .isc_ntxd_min = {EM_MIN_TXD},
 541         .isc_nrxd_max = {EM_MAX_RXD},
 542         .isc_ntxd_max = {EM_MAX_TXD},
 543         .isc_nrxd_default = {EM_DEFAULT_RXD},
 544         .isc_ntxd_default = {EM_DEFAULT_TXD},
 545 };
 546
 547 if_shared_ctx_t em_sctx = &em_sctx_init;
 548
 549 static struct if_shared_ctx igb_sctx_init = {
 550         .isc_magic = IFLIB_MAGIC,
 551         .isc_q_align = PAGE_SIZE,
 552         .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 553         .isc_tx_maxsegsize = PAGE_SIZE,
 554         .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 555         .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
 556         .isc_rx_maxsize = MJUM9BYTES,
 557         .isc_rx_nsegments = 1,
 558         .isc_rx_maxsegsize = MJUM9BYTES,
 559         .isc_nfl = 1,
 560         .isc_nrxqs = 1,
 561         .isc_ntxqs = 1,
 562         .isc_admin_intrcnt = 1,
 563         .isc_vendor_info = igb_vendor_info_array,
 564         .isc_driver_version = em_driver_version,
 565         .isc_driver = &igb_if_driver,
 566         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 567
 568         .isc_nrxd_min = {EM_MIN_RXD},
 569         .isc_ntxd_min = {EM_MIN_TXD},
 570         .isc_nrxd_max = {IGB_MAX_RXD},
 571         .isc_ntxd_max = {IGB_MAX_TXD},
 572         .isc_nrxd_default = {EM_DEFAULT_RXD},
 573         .isc_ntxd_default = {EM_DEFAULT_TXD},
 574 };
 575
 576 if_shared_ctx_t igb_sctx = &igb_sctx_init;
 577
 578 /*****************************************************************
 579  *
 580  * Dump Registers
 581  *
 582  ****************************************************************/
 583 #define IGB_REGS_LEN 739
 584
 585 static int em_get_regs(SYSCTL_HANDLER_ARGS)
 586 {
 587         struct adapter *adapter = (struct adapter *)arg1;
 588         struct e1000_hw *hw = &adapter->hw;
 589         struct sbuf *sb;
 590         u32 *regs_buff;
 591         int rc;
 592
 593         regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK);
 594         memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
 595
 596         rc = sysctl_wire_old_buffer(req, 0);
 597         MPASS(rc == 0);
 598         if (rc != 0) {
 599                 free(regs_buff, M_DEVBUF);
 600                 return (rc);
 601         }
 602
 603         sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
 604         MPASS(sb != NULL);
 605         if (sb == NULL) {
 606                 free(regs_buff, M_DEVBUF);
 607                 return (ENOMEM);
 608         }
 609
 610         /* General Registers */
 611         regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
 612         regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
 613         regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
 614         regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
 615         regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
 616         regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
 617         regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
 618         regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
 619         regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
 620         regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
 621         regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
 622         regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
 623         regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
 624         regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
 625         regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
 626         regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
 627         regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
 628         regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
 629         regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
 630         regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
 631         regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
 632         regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
 633
 634         sbuf_printf(sb, "General Registers\n");
 635         sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
 636         sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
 637         sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]);
 638
 639         sbuf_printf(sb, "Interrupt Registers\n");
 640         sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
 641
 642         sbuf_printf(sb, "RX Registers\n");
 643         sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
 644         sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
 645         sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
 646         sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
 647         sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
 648         sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
 649         sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
 650
 651         sbuf_printf(sb, "TX Registers\n");
 652         sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
 653         sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
 654         sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
 655         sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
 656         sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
 657         sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
 658         sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
 659         sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
 660         sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
 661         sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
 662         sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
 663
 664         free(regs_buff, M_DEVBUF);
 665
 666 #ifdef DUMP_DESCS
 667         {
 668                 if_softc_ctx_t scctx = adapter->shared;
 669                 struct rx_ring *rxr = &rx_que->rxr;
 670                 struct tx_ring *txr = &tx_que->txr;
 671                 int ntxd = scctx->isc_ntxd[0];
 672                 int nrxd = scctx->isc_nrxd[0];
 673                 int j;
 674
 675         for (j = 0; j < nrxd; j++) {
 676                 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
 677                 u32 length =  le32toh(rxr->rx_base[j].wb.upper.length);
 678                 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 "  Error:%d  Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
 679         }
 680
 681         for (j = 0; j < min(ntxd, 256); j++) {
 682                 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
 683
 684                 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x  eop: %d DD=%d\n",
 685                             j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
 686                             buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
 687
 688         }
 689         }
 690 #endif
 691
 692         rc = sbuf_finish(sb);
 693         sbuf_delete(sb);
 694         return(rc);
 695 }
 696
 697 static void *
 698 em_register(device_t dev)
 699 {
 700         return (em_sctx);
 701 }
 702
 703 static void *
 704 igb_register(device_t dev)
 705 {
 706         return (igb_sctx);
 707 }
 708
 709 static int
 710 em_set_num_queues(if_ctx_t ctx)
 711 {
 712         struct adapter *adapter = iflib_get_softc(ctx);
 713         int maxqueues;
 714
 715         /* Sanity check based on HW */
 716         switch (adapter->hw.mac.type) {
 717         case e1000_82576:
 718         case e1000_82580:
 719         case e1000_i350:
 720         case e1000_i354:
 721                 maxqueues = 8;
 722                 break;
 723         case e1000_i210:
 724         case e1000_82575:
 725                 maxqueues = 4;
 726                 break;
 727         case e1000_i211:
 728         case e1000_82574:
 729                 maxqueues = 2;
 730                 break;
 731         default:
 732                 maxqueues = 1;
 733                 break;
 734         }
 735
 736         return (maxqueues);
 737 }
 738
 739 #define LEM_CAPS                                                        \
 740     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 741     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER
 742
 743 #define EM_CAPS                                                         \
 744     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 745     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 |  \
 746     IFCAP_LRO | IFCAP_VLAN_HWTSO
 747
 748 #define IGB_CAPS                                                        \
 749     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 750     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 |  \
 751     IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\
 752     IFCAP_TSO6
 753
 754 /*********************************************************************
 755  *  Device initialization routine
 756  *
 757  *  The attach entry point is called when the driver is being loaded.
 758  *  This routine identifies the type of hardware, allocates all resources
 759  *  and initializes the hardware.
 760  *
 761  *  return 0 on success, positive on failure
 762  *********************************************************************/
 763 static int
 764 em_if_attach_pre(if_ctx_t ctx)
 765 {
 766         struct adapter *adapter;
 767         if_softc_ctx_t scctx;
 768         device_t dev;
 769         struct e1000_hw *hw;
 770         int error = 0;
 771
 772         INIT_DEBUGOUT("em_if_attach_pre: begin");
 773         dev = iflib_get_dev(ctx);
 774         adapter = iflib_get_softc(ctx);
 775
 776         adapter->ctx = adapter->osdep.ctx = ctx;
 777         adapter->dev = adapter->osdep.dev = dev;
 778         scctx = adapter->shared = iflib_get_softc_ctx(ctx);
 779         adapter->media = iflib_get_media(ctx);
 780         hw = &adapter->hw;
 781
 782         adapter->tx_process_limit = scctx->isc_ntxd[0];
 783
 784         /* SYSCTL stuff */
 785         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 786             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 787             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 788             em_sysctl_nvm_info, "I", "NVM Information");
 789
 790         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 791             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 792             OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 793             em_sysctl_debug_info, "I", "Debug Information");
 794
 795         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 796             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 797             OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 798             em_set_flowcntl, "I", "Flow Control");
 799
 800         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 801             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 802             OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0,
 803             em_get_regs, "A", "Dump Registers");
 804
 805         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 806             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 807             OID_AUTO, "rs_dump", CTLTYPE_INT | CTLFLAG_RW, adapter, 0,
 808             em_get_rs, "I", "Dump RS indexes");
 809
 810         /* Determine hardware and mac info */
 811         em_identify_hardware(ctx);
 812
 813         scctx->isc_tx_nsegments = EM_MAX_SCATTER;
 814         scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
 815         if (bootverbose)
 816                 device_printf(dev, "attach_pre capping queues at %d\n",
 817                     scctx->isc_ntxqsets_max);
 818
 819         if (adapter->hw.mac.type >= igb_mac_min) {
 820                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
 821                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
 822                 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
 823                 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
 824                 scctx->isc_txrx = &igb_txrx;
 825                 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
 826                 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 827                 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 828                 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS;
 829                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO |
 830                      CSUM_IP6_TCP | CSUM_IP6_UDP;
 831                 if (adapter->hw.mac.type != e1000_82575)
 832                         scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
 833                 /*
 834                 ** Some new devices, as with ixgbe, now may
 835                 ** use a different BAR, so we need to keep
 836                 ** track of which is used.
 837                 */
 838                 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR);
 839                 if (pci_read_config(dev, scctx->isc_msix_bar, 4) == 0)
 840                         scctx->isc_msix_bar += 4;
 841         } else if (adapter->hw.mac.type >= em_mac_min) {
 842                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 843                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
 844                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 845                 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
 846                 scctx->isc_txrx = &em_txrx;
 847                 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
 848                 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 849                 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 850                 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS;
 851                 /*
 852                  * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO}
 853                  * by default as we don't have workarounds for all associated
 854                  * silicon errata.  E. g., with several MACs such as 82573E,
 855                  * TSO only works at Gigabit speed and otherwise can cause the
 856                  * hardware to hang (which also would be next to impossible to
 857                  * work around given that already queued TSO-using descriptors
 858                  * would need to be flushed and vlan(4) reconfigured at runtime
 859                  * in case of a link speed change).  Moreover, MACs like 82579
 860                  * still can hang at Gigabit even with all publicly documented
 861                  * TSO workarounds implemented.  Generally, the penality of
 862                  * these workarounds is rather high and may involve copying
 863                  * mbuf data around so advantages of TSO lapse.  Still, TSO may
 864                  * work for a few MACs of this class - at least when sticking
 865                  * with Gigabit - in which case users may enable TSO manually.
 866                  */
 867                 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
 868                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 869                 /*
 870                  * We support MSI-X with 82574 only, but indicate to iflib(4)
 871                  * that it shall give MSI at least a try with other devices.
 872                  */
 873                 if (adapter->hw.mac.type == e1000_82574) {
 874                         scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR);
 875                 } else {
 876                         scctx->isc_msix_bar = -1;
 877                         scctx->isc_disable_msix = 1;
 878                 }
 879         } else {
 880                 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 881                 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
 882                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 883                 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
 884                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP;
 885                 scctx->isc_txrx = &lem_txrx;
 886                 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS;
 887                 if (adapter->hw.mac.type < e1000_82543)
 888                         scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
 889                 /* INTx only */
 890                 scctx->isc_msix_bar = 0;
 891         }
 892
 893         /* Setup PCI resources */
 894         if (em_allocate_pci_resources(ctx)) {
 895                 device_printf(dev, "Allocation of PCI resources failed\n");
 896                 error = ENXIO;
 897                 goto err_pci;
 898         }
 899
 900         /*
 901         ** For ICH8 and family we need to
 902         ** map the flash memory, and this
 903         ** must happen after the MAC is
 904         ** identified
 905         */
 906         if ((hw->mac.type == e1000_ich8lan) ||
 907             (hw->mac.type == e1000_ich9lan) ||
 908             (hw->mac.type == e1000_ich10lan) ||
 909             (hw->mac.type == e1000_pchlan) ||
 910             (hw->mac.type == e1000_pch2lan) ||
 911             (hw->mac.type == e1000_pch_lpt)) {
 912                 int rid = EM_BAR_TYPE_FLASH;
 913                 adapter->flash = bus_alloc_resource_any(dev,
 914                     SYS_RES_MEMORY, &rid, RF_ACTIVE);
 915                 if (adapter->flash == NULL) {
 916                         device_printf(dev, "Mapping of Flash failed\n");
 917                         error = ENXIO;
 918                         goto err_pci;
 919                 }
 920                 /* This is used in the shared code */
 921                 hw->flash_address = (u8 *)adapter->flash;
 922                 adapter->osdep.flash_bus_space_tag =
 923                     rman_get_bustag(adapter->flash);
 924                 adapter->osdep.flash_bus_space_handle =
 925                     rman_get_bushandle(adapter->flash);
 926         }
 927         /*
 928         ** In the new SPT device flash is not  a
 929         ** separate BAR, rather it is also in BAR0,
 930         ** so use the same tag and an offset handle for the
 931         ** FLASH read/write macros in the shared code.
 932         */
 933         else if (hw->mac.type >= e1000_pch_spt) {
 934                 adapter->osdep.flash_bus_space_tag =
 935                     adapter->osdep.mem_bus_space_tag;
 936                 adapter->osdep.flash_bus_space_handle =
 937                     adapter->osdep.mem_bus_space_handle
 938                     + E1000_FLASH_BASE_ADDR;
 939         }
 940
 941         /* Do Shared Code initialization */
 942         error = e1000_setup_init_funcs(hw, TRUE);
 943         if (error) {
 944                 device_printf(dev, "Setup of Shared code failed, error %d\n",
 945                     error);
 946                 error = ENXIO;
 947                 goto err_pci;
 948         }
 949
 950         em_setup_msix(ctx);
 951         e1000_get_bus_info(hw);
 952
 953         /* Set up some sysctls for the tunable interrupt delays */
 954         em_add_int_delay_sysctl(adapter, "rx_int_delay",
 955             "receive interrupt delay in usecs", &adapter->rx_int_delay,
 956             E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
 957         em_add_int_delay_sysctl(adapter, "tx_int_delay",
 958             "transmit interrupt delay in usecs", &adapter->tx_int_delay,
 959             E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
 960         em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
 961             "receive interrupt delay limit in usecs",
 962             &adapter->rx_abs_int_delay,
 963             E1000_REGISTER(hw, E1000_RADV),
 964             em_rx_abs_int_delay_dflt);
 965         em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
 966             "transmit interrupt delay limit in usecs",
 967             &adapter->tx_abs_int_delay,
 968             E1000_REGISTER(hw, E1000_TADV),
 969             em_tx_abs_int_delay_dflt);
 970         em_add_int_delay_sysctl(adapter, "itr",
 971             "interrupt delay limit in usecs/4",
 972             &adapter->tx_itr,
 973             E1000_REGISTER(hw, E1000_ITR),
 974             DEFAULT_ITR);
 975
 976         hw->mac.autoneg = DO_AUTO_NEG;
 977         hw->phy.autoneg_wait_to_complete = FALSE;
 978         hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 979
 980         if (adapter->hw.mac.type < em_mac_min) {
 981                 e1000_init_script_state_82541(&adapter->hw, TRUE);
 982                 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
 983         }
 984         /* Copper options */
 985         if (hw->phy.media_type == e1000_media_type_copper) {
 986                 hw->phy.mdix = AUTO_ALL_MODES;
 987                 hw->phy.disable_polarity_correction = FALSE;
 988                 hw->phy.ms_type = EM_MASTER_SLAVE;
 989         }
 990
 991         /*
 992          * Set the frame limits assuming
 993          * standard ethernet sized frames.
 994          */
 995         scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
 996             ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
 997
 998         /*
 999          * This controls when hardware reports transmit completion
1000          * status.
1001          */
1002         hw->mac.report_tx_early = 1;
1003
1004         /* Allocate multicast array memory. */
1005         adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN *
1006             MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
1007         if (adapter->mta == NULL) {
1008                 device_printf(dev, "Can not allocate multicast setup array\n");
1009                 error = ENOMEM;
1010                 goto err_late;
1011         }
1012
1013         /* Check SOL/IDER usage */
1014         if (e1000_check_reset_block(hw))
1015                 device_printf(dev, "PHY reset is blocked"
1016                               " due to SOL/IDER session.\n");
1017
1018         /* Sysctl for setting Energy Efficient Ethernet */
1019         hw->dev_spec.ich8lan.eee_disable = eee_setting;
1020         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1021             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1022             OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW,
1023             adapter, 0, em_sysctl_eee, "I",
1024             "Disable Energy Efficient Ethernet");
1025
1026         /*
1027         ** Start from a known state, this is
1028         ** important in reading the nvm and
1029         ** mac from that.
1030         */
1031         e1000_reset_hw(hw);
1032
1033         /* Make sure we have a good EEPROM before we read from it */
1034         if (e1000_validate_nvm_checksum(hw) < 0) {
1035                 /*
1036                 ** Some PCI-E parts fail the first check due to
1037                 ** the link being in sleep state, call it again,
1038                 ** if it fails a second time its a real issue.
1039                 */
1040                 if (e1000_validate_nvm_checksum(hw) < 0) {
1041                         device_printf(dev,
1042                             "The EEPROM Checksum Is Not Valid\n");
1043                         error = EIO;
1044                         goto err_late;
1045                 }
1046         }
1047
1048         /* Copy the permanent MAC address out of the EEPROM */
1049         if (e1000_read_mac_addr(hw) < 0) {
1050                 device_printf(dev, "EEPROM read error while reading MAC"
1051                               " address\n");
1052                 error = EIO;
1053                 goto err_late;
1054         }
1055
1056         if (!em_is_valid_ether_addr(hw->mac.addr)) {
1057                 device_printf(dev, "Invalid MAC address\n");
1058                 error = EIO;
1059                 goto err_late;
1060         }
1061
1062         /* Disable ULP support */
1063         e1000_disable_ulp_lpt_lp(hw, TRUE);
1064
1065         /*
1066          * Get Wake-on-Lan and Management info for later use
1067          */
1068         em_get_wakeup(ctx);
1069
1070         /* Enable only WOL MAGIC by default */
1071         scctx->isc_capenable &= ~IFCAP_WOL;
1072         if (adapter->wol != 0)
1073                 scctx->isc_capenable |= IFCAP_WOL_MAGIC;
1074
1075         iflib_set_mac(ctx, hw->mac.addr);
1076
1077         return (0);
1078
1079 err_late:
1080         em_release_hw_control(adapter);
1081 err_pci:
1082         em_free_pci_resources(ctx);
1083         free(adapter->mta, M_DEVBUF);
1084
1085         return (error);
1086 }
1087
1088 static int
1089 em_if_attach_post(if_ctx_t ctx)
1090 {
1091         struct adapter *adapter = iflib_get_softc(ctx);
1092         struct e1000_hw *hw = &adapter->hw;
1093         int error = 0;
1094
1095         /* Setup OS specific network interface */
1096         error = em_setup_interface(ctx);
1097         if (error != 0) {
1098                 goto err_late;
1099         }
1100
1101         em_reset(ctx);
1102
1103         /* Initialize statistics */
1104         em_update_stats_counters(adapter);
1105         hw->mac.get_link_status = 1;
1106         em_if_update_admin_status(ctx);
1107         em_add_hw_stats(adapter);
1108
1109         /* Non-AMT based hardware can now take control from firmware */
1110         if (adapter->has_manage && !adapter->has_amt)
1111                 em_get_hw_control(adapter);
1112
1113         INIT_DEBUGOUT("em_if_attach_post: end");
1114
1115         return (error);
1116
1117 err_late:
1118         em_release_hw_control(adapter);
1119         em_free_pci_resources(ctx);
1120         em_if_queues_free(ctx);
1121         free(adapter->mta, M_DEVBUF);
1122
1123         return (error);
1124 }
1125
1126 /*********************************************************************
1127  *  Device removal routine
1128  *
1129  *  The detach entry point is called when the driver is being removed.
1130  *  This routine stops the adapter and deallocates all the resources
1131  *  that were allocated for driver operation.
1132  *
1133  *  return 0 on success, positive on failure
1134  *********************************************************************/
1135 static int
1136 em_if_detach(if_ctx_t ctx)
1137 {
1138         struct adapter  *adapter = iflib_get_softc(ctx);
1139
1140         INIT_DEBUGOUT("em_if_detach: begin");
1141
1142         e1000_phy_hw_reset(&adapter->hw);
1143
1144         em_release_manageability(adapter);
1145         em_release_hw_control(adapter);
1146         em_free_pci_resources(ctx);
1147
1148         return (0);
1149 }
1150
1151 /*********************************************************************
1152  *
1153  *  Shutdown entry point
1154  *
1155  **********************************************************************/
1156
1157 static int
1158 em_if_shutdown(if_ctx_t ctx)
1159 {
1160         return em_if_suspend(ctx);
1161 }
1162
1163 /*
1164  * Suspend/resume device methods.
1165  */
1166 static int
1167 em_if_suspend(if_ctx_t ctx)
1168 {
1169         struct adapter *adapter = iflib_get_softc(ctx);
1170
1171         em_release_manageability(adapter);
1172         em_release_hw_control(adapter);
1173         em_enable_wakeup(ctx);
1174         return (0);
1175 }
1176
1177 static int
1178 em_if_resume(if_ctx_t ctx)
1179 {
1180         struct adapter *adapter = iflib_get_softc(ctx);
1181
1182         if (adapter->hw.mac.type == e1000_pch2lan)
1183                 e1000_resume_workarounds_pchlan(&adapter->hw);
1184         em_if_init(ctx);
1185         em_init_manageability(adapter);
1186
1187         return(0);
1188 }
1189
1190 static int
1191 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1192 {
1193         int max_frame_size;
1194         struct adapter *adapter = iflib_get_softc(ctx);
1195         if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1196
1197          IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1198
1199         switch (adapter->hw.mac.type) {
1200         case e1000_82571:
1201         case e1000_82572:
1202         case e1000_ich9lan:
1203         case e1000_ich10lan:
1204         case e1000_pch2lan:
1205         case e1000_pch_lpt:
1206         case e1000_pch_spt:
1207         case e1000_pch_cnp:
1208         case e1000_82574:
1209         case e1000_82583:
1210         case e1000_80003es2lan:
1211                 /* 9K Jumbo Frame size */
1212                 max_frame_size = 9234;
1213                 break;
1214         case e1000_pchlan:
1215                 max_frame_size = 4096;
1216                 break;
1217         case e1000_82542:
1218         case e1000_ich8lan:
1219                 /* Adapters that do not support jumbo frames */
1220                 max_frame_size = ETHER_MAX_LEN;
1221                 break;
1222         default:
1223                 if (adapter->hw.mac.type >= igb_mac_min)
1224                         max_frame_size = 9234;
1225                 else /* lem */
1226                         max_frame_size = MAX_JUMBO_FRAME_SIZE;
1227         }
1228         if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1229                 return (EINVAL);
1230         }
1231
1232         scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
1233             mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1234         return (0);
1235 }
1236
1237 /*********************************************************************
1238  *  Init entry point
1239  *
1240  *  This routine is used in two ways. It is used by the stack as
1241  *  init entry point in network interface structure. It is also used
1242  *  by the driver as a hw/sw initialization routine to get to a
1243  *  consistent state.
1244  *
1245  **********************************************************************/
1246 static void
1247 em_if_init(if_ctx_t ctx)
1248 {
1249         struct adapter *adapter = iflib_get_softc(ctx);
1250         if_softc_ctx_t scctx = adapter->shared;
1251         struct ifnet *ifp = iflib_get_ifp(ctx);
1252         struct em_tx_queue *tx_que;
1253         int i;
1254
1255         INIT_DEBUGOUT("em_if_init: begin");
1256
1257         /* Get the latest mac address, User can use a LAA */
1258         bcopy(if_getlladdr(ifp), adapter->hw.mac.addr,
1259             ETHER_ADDR_LEN);
1260
1261         /* Put the address into the Receive Address Array */
1262         e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1263
1264         /*
1265          * With the 82571 adapter, RAR[0] may be overwritten
1266          * when the other port is reset, we make a duplicate
1267          * in RAR[14] for that eventuality, this assures
1268          * the interface continues to function.
1269          */
1270         if (adapter->hw.mac.type == e1000_82571) {
1271                 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1272                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1273                     E1000_RAR_ENTRIES - 1);
1274         }
1275
1276
1277         /* Initialize the hardware */
1278         em_reset(ctx);
1279         em_if_update_admin_status(ctx);
1280
1281         for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) {
1282                 struct tx_ring *txr = &tx_que->txr;
1283
1284                 txr->tx_rs_cidx = txr->tx_rs_pidx;
1285
1286                 /* Initialize the last processed descriptor to be the end of
1287                  * the ring, rather than the start, so that we avoid an
1288                  * off-by-one error when calculating how many descriptors are
1289                  * done in the credits_update function.
1290                  */
1291                 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
1292         }
1293
1294         /* Setup VLAN support, basic and offload if available */
1295         E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1296
1297         /* Clear bad data from Rx FIFOs */
1298         if (adapter->hw.mac.type >= igb_mac_min)
1299                 e1000_rx_fifo_flush_82575(&adapter->hw);
1300
1301         /* Configure for OS presence */
1302         em_init_manageability(adapter);
1303
1304         /* Prepare transmit descriptors and buffers */
1305         em_initialize_transmit_unit(ctx);
1306
1307         /* Setup Multicast table */
1308         em_if_multi_set(ctx);
1309
1310         adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx);
1311         em_initialize_receive_unit(ctx);
1312
1313         /* Use real VLAN Filter support? */
1314         if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1315                 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
1316                         /* Use real VLAN Filter support */
1317                         em_setup_vlan_hw_support(adapter);
1318                 else {
1319                         u32 ctrl;
1320                         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1321                         ctrl |= E1000_CTRL_VME;
1322                         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1323                 }
1324         }
1325
1326         /* Don't lose promiscuous settings */
1327         em_if_set_promisc(ctx, IFF_PROMISC);
1328         e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1329
1330         /* MSI-X configuration for 82574 */
1331         if (adapter->hw.mac.type == e1000_82574) {
1332                 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1333
1334                 tmp |= E1000_CTRL_EXT_PBA_CLR;
1335                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1336                 /* Set the IVAR - interrupt vector routing. */
1337                 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars);
1338         } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1339                 igb_configure_queues(adapter);
1340
1341         /* this clears any pending interrupts */
1342         E1000_READ_REG(&adapter->hw, E1000_ICR);
1343         E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC);
1344
1345         /* AMT based hardware can now take control from firmware */
1346         if (adapter->has_manage && adapter->has_amt)
1347                 em_get_hw_control(adapter);
1348
1349         /* Set Energy Efficient Ethernet */
1350         if (adapter->hw.mac.type >= igb_mac_min &&
1351             adapter->hw.phy.media_type == e1000_media_type_copper) {
1352                 if (adapter->hw.mac.type == e1000_i354)
1353                         e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
1354                 else
1355                         e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
1356         }
1357 }
1358
1359 /*********************************************************************
1360  *
1361  *  Fast Legacy/MSI Combined Interrupt Service routine
1362  *
1363  *********************************************************************/
1364 int
1365 em_intr(void *arg)
1366 {
1367         struct adapter *adapter = arg;
1368         if_ctx_t ctx = adapter->ctx;
1369         u32 reg_icr;
1370
1371         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1372
1373         /* Hot eject? */
1374         if (reg_icr == 0xffffffff)
1375                 return FILTER_STRAY;
1376
1377         /* Definitely not our interrupt. */
1378         if (reg_icr == 0x0)
1379                 return FILTER_STRAY;
1380
1381         /*
1382          * Starting with the 82571 chip, bit 31 should be used to
1383          * determine whether the interrupt belongs to us.
1384          */
1385         if (adapter->hw.mac.type >= e1000_82571 &&
1386             (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1387                 return FILTER_STRAY;
1388
1389         /*
1390          * Only MSI-X interrupts have one-shot behavior by taking advantage
1391          * of the EIAC register.  Thus, explicitly disable interrupts.  This
1392          * also works around the MSI message reordering errata on certain
1393          * systems.
1394          */
1395         IFDI_INTR_DISABLE(ctx);
1396
1397         /* Link status change */
1398         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))
1399                 em_handle_link(ctx);
1400
1401         if (reg_icr & E1000_ICR_RXO)
1402                 adapter->rx_overruns++;
1403
1404         return (FILTER_SCHEDULE_THREAD);
1405 }
1406
1407 static int
1408 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1409 {
1410         struct adapter *adapter = iflib_get_softc(ctx);
1411         struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1412
1413         E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims);
1414         return (0);
1415 }
1416
1417 static int
1418 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1419 {
1420         struct adapter *adapter = iflib_get_softc(ctx);
1421         struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1422
1423         E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims);
1424         return (0);
1425 }
1426
1427 static int
1428 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1429 {
1430         struct adapter *adapter = iflib_get_softc(ctx);
1431         struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1432
1433         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims);
1434         return (0);
1435 }
1436
1437 static int
1438 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1439 {
1440         struct adapter *adapter = iflib_get_softc(ctx);
1441         struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1442
1443         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims);
1444         return (0);
1445 }
1446
1447 /*********************************************************************
1448  *
1449  *  MSI-X RX Interrupt Service routine
1450  *
1451  **********************************************************************/
1452 static int
1453 em_msix_que(void *arg)
1454 {
1455         struct em_rx_queue *que = arg;
1456
1457         ++que->irqs;
1458
1459         return (FILTER_SCHEDULE_THREAD);
1460 }
1461
1462 /*********************************************************************
1463  *
1464  *  MSI-X Link Fast Interrupt Service routine
1465  *
1466  **********************************************************************/
1467 static int
1468 em_msix_link(void *arg)
1469 {
1470         struct adapter *adapter = arg;
1471         u32 reg_icr;
1472
1473         ++adapter->link_irq;
1474         MPASS(adapter->hw.back != NULL);
1475         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1476
1477         if (reg_icr & E1000_ICR_RXO)
1478                 adapter->rx_overruns++;
1479
1480         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1481                 em_handle_link(adapter->ctx);
1482         } else if (adapter->hw.mac.type == e1000_82574) {
1483                 /* Only re-arm 82574 if em_if_update_admin_status() won't. */
1484                 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK |
1485                     E1000_IMS_LSC);
1486         }
1487
1488         if (adapter->hw.mac.type == e1000_82574) {
1489                 /*
1490                  * Because we must read the ICR for this interrupt it may
1491                  * clear other causes using autoclear, for this reason we
1492                  * simply create a soft interrupt for all these vectors.
1493                  */
1494                 if (reg_icr)
1495                         E1000_WRITE_REG(&adapter->hw, E1000_ICS, adapter->ims);
1496         } else {
1497                 /* Re-arm unconditionally */
1498                 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC);
1499                 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1500         }
1501
1502         return (FILTER_HANDLED);
1503 }
1504
1505 static void
1506 em_handle_link(void *context)
1507 {
1508         if_ctx_t ctx = context;
1509         struct adapter *adapter = iflib_get_softc(ctx);
1510
1511         adapter->hw.mac.get_link_status = 1;
1512         iflib_admin_intr_deferred(ctx);
1513 }
1514
1515 /*********************************************************************
1516  *
1517  *  Media Ioctl callback
1518  *
1519  *  This routine is called whenever the user queries the status of
1520  *  the interface using ifconfig.
1521  *
1522  **********************************************************************/
1523 static void
1524 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1525 {
1526         struct adapter *adapter = iflib_get_softc(ctx);
1527         u_char fiber_type = IFM_1000_SX;
1528
1529         INIT_DEBUGOUT("em_if_media_status: begin");
1530
1531         iflib_admin_intr_deferred(ctx);
1532
1533         ifmr->ifm_status = IFM_AVALID;
1534         ifmr->ifm_active = IFM_ETHER;
1535
1536         if (!adapter->link_active) {
1537                 return;
1538         }
1539
1540         ifmr->ifm_status |= IFM_ACTIVE;
1541
1542         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
1543             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1544                 if (adapter->hw.mac.type == e1000_82545)
1545                         fiber_type = IFM_1000_LX;
1546                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1547         } else {
1548                 switch (adapter->link_speed) {
1549                 case 10:
1550                         ifmr->ifm_active |= IFM_10_T;
1551                         break;
1552                 case 100:
1553                         ifmr->ifm_active |= IFM_100_TX;
1554                         break;
1555                 case 1000:
1556                         ifmr->ifm_active |= IFM_1000_T;
1557                         break;
1558                 }
1559                 if (adapter->link_duplex == FULL_DUPLEX)
1560                         ifmr->ifm_active |= IFM_FDX;
1561                 else
1562                         ifmr->ifm_active |= IFM_HDX;
1563         }
1564 }
1565
1566 /*********************************************************************
1567  *
1568  *  Media Ioctl callback
1569  *
1570  *  This routine is called when the user changes speed/duplex using
1571  *  media/mediopt option with ifconfig.
1572  *
1573  **********************************************************************/
1574 static int
1575 em_if_media_change(if_ctx_t ctx)
1576 {
1577         struct adapter *adapter = iflib_get_softc(ctx);
1578         struct ifmedia *ifm = iflib_get_media(ctx);
1579
1580         INIT_DEBUGOUT("em_if_media_change: begin");
1581
1582         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1583                 return (EINVAL);
1584
1585         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1586         case IFM_AUTO:
1587                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1588                 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1589                 break;
1590         case IFM_1000_LX:
1591         case IFM_1000_SX:
1592         case IFM_1000_T:
1593                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1594                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1595                 break;
1596         case IFM_100_TX:
1597                 adapter->hw.mac.autoneg = FALSE;
1598                 adapter->hw.phy.autoneg_advertised = 0;
1599                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1600                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1601                 else
1602                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1603                 break;
1604         case IFM_10_T:
1605                 adapter->hw.mac.autoneg = FALSE;
1606                 adapter->hw.phy.autoneg_advertised = 0;
1607                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1608                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1609                 else
1610                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1611                 break;
1612         default:
1613                 device_printf(adapter->dev, "Unsupported media type\n");
1614         }
1615
1616         em_if_init(ctx);
1617
1618         return (0);
1619 }
1620
1621 static int
1622 em_if_set_promisc(if_ctx_t ctx, int flags)
1623 {
1624         struct adapter *adapter = iflib_get_softc(ctx);
1625         u32 reg_rctl;
1626
1627         em_disable_promisc(ctx);
1628
1629         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1630
1631         if (flags & IFF_PROMISC) {
1632                 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1633                 /* Turn this on if you want to see bad packets */
1634                 if (em_debug_sbp)
1635                         reg_rctl |= E1000_RCTL_SBP;
1636                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1637         } else if (flags & IFF_ALLMULTI) {
1638                 reg_rctl |= E1000_RCTL_MPE;
1639                 reg_rctl &= ~E1000_RCTL_UPE;
1640                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1641         }
1642         return (0);
1643 }
1644
1645 static void
1646 em_disable_promisc(if_ctx_t ctx)
1647 {
1648         struct adapter *adapter = iflib_get_softc(ctx);
1649         struct ifnet *ifp = iflib_get_ifp(ctx);
1650         u32 reg_rctl;
1651         int mcnt = 0;
1652
1653         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1654         reg_rctl &= (~E1000_RCTL_UPE);
1655         if (if_getflags(ifp) & IFF_ALLMULTI)
1656                 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1657         else
1658                 mcnt = if_llmaddr_count(ifp);
1659         /* Don't disable if in MAX groups */
1660         if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1661                 reg_rctl &=  (~E1000_RCTL_MPE);
1662         reg_rctl &=  (~E1000_RCTL_SBP);
1663         E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1664 }
1665
1666
1667 static u_int
1668 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1669 {
1670         u8 *mta = arg;
1671
1672         if (cnt == MAX_NUM_MULTICAST_ADDRESSES)
1673                 return (1);
1674
1675         bcopy(LLADDR(sdl), &mta[cnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1676
1677         return (1);
1678 }
1679
1680 /*********************************************************************
1681  *  Multicast Update
1682  *
1683  *  This routine is called whenever multicast address list is updated.
1684  *
1685  **********************************************************************/
1686
1687 static void
1688 em_if_multi_set(if_ctx_t ctx)
1689 {
1690         struct adapter *adapter = iflib_get_softc(ctx);
1691         struct ifnet *ifp = iflib_get_ifp(ctx);
1692         u32 reg_rctl = 0;
1693         u8  *mta; /* Multicast array memory */
1694         int mcnt = 0;
1695
1696         IOCTL_DEBUGOUT("em_set_multi: begin");
1697
1698         mta = adapter->mta;
1699         bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1700
1701         if (adapter->hw.mac.type == e1000_82542 &&
1702             adapter->hw.revision_id == E1000_REVISION_2) {
1703                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1704                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1705                         e1000_pci_clear_mwi(&adapter->hw);
1706                 reg_rctl |= E1000_RCTL_RST;
1707                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1708                 msec_delay(5);
1709         }
1710
1711         mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta);
1712
1713         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1714                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1715                 reg_rctl |= E1000_RCTL_MPE;
1716                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1717         } else
1718                 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
1719
1720         if (adapter->hw.mac.type == e1000_82542 &&
1721             adapter->hw.revision_id == E1000_REVISION_2) {
1722                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1723                 reg_rctl &= ~E1000_RCTL_RST;
1724                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1725                 msec_delay(5);
1726                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1727                         e1000_pci_set_mwi(&adapter->hw);
1728         }
1729 }
1730
1731 /*********************************************************************
1732  *  Timer routine
1733  *
1734  *  This routine schedules em_if_update_admin_status() to check for
1735  *  link status and to gather statistics as well as to perform some
1736  *  controller-specific hardware patting.
1737  *
1738  **********************************************************************/
1739 static void
1740 em_if_timer(if_ctx_t ctx, uint16_t qid)
1741 {
1742
1743         if (qid != 0)
1744                 return;
1745
1746         iflib_admin_intr_deferred(ctx);
1747 }
1748
1749 static void
1750 em_if_update_admin_status(if_ctx_t ctx)
1751 {
1752         struct adapter *adapter = iflib_get_softc(ctx);
1753         struct e1000_hw *hw = &adapter->hw;
1754         device_t dev = iflib_get_dev(ctx);
1755         u32 link_check, thstat, ctrl;
1756
1757         link_check = thstat = ctrl = 0;
1758         /* Get the cached link value or read phy for real */
1759         switch (hw->phy.media_type) {
1760         case e1000_media_type_copper:
1761                 if (hw->mac.get_link_status) {
1762                         if (hw->mac.type == e1000_pch_spt)
1763                                 msec_delay(50);
1764                         /* Do the work to read phy */
1765                         e1000_check_for_link(hw);
1766                         link_check = !hw->mac.get_link_status;
1767                         if (link_check) /* ESB2 fix */
1768                                 e1000_cfg_on_link_up(hw);
1769                 } else {
1770                         link_check = TRUE;
1771                 }
1772                 break;
1773         case e1000_media_type_fiber:
1774                 e1000_check_for_link(hw);
1775                 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1776                             E1000_STATUS_LU);
1777                 break;
1778         case e1000_media_type_internal_serdes:
1779                 e1000_check_for_link(hw);
1780                 link_check = adapter->hw.mac.serdes_has_link;
1781                 break;
1782         /* VF device is type_unknown */
1783         case e1000_media_type_unknown:
1784                 e1000_check_for_link(hw);
1785                 link_check = !hw->mac.get_link_status;
1786                 /* FALLTHROUGH */
1787         default:
1788                 break;
1789         }
1790
1791         /* Check for thermal downshift or shutdown */
1792         if (hw->mac.type == e1000_i350) {
1793                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1794                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1795         }
1796
1797         /* Now check for a transition */
1798         if (link_check && (adapter->link_active == 0)) {
1799                 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
1800                     &adapter->link_duplex);
1801                 /* Check if we must disable SPEED_MODE bit on PCI-E */
1802                 if ((adapter->link_speed != SPEED_1000) &&
1803                     ((hw->mac.type == e1000_82571) ||
1804                     (hw->mac.type == e1000_82572))) {
1805                         int tarc0;
1806                         tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1807                         tarc0 &= ~TARC_SPEED_MODE_BIT;
1808                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1809                 }
1810                 if (bootverbose)
1811                         device_printf(dev, "Link is up %d Mbps %s\n",
1812                             adapter->link_speed,
1813                             ((adapter->link_duplex == FULL_DUPLEX) ?
1814                             "Full Duplex" : "Half Duplex"));
1815                 adapter->link_active = 1;
1816                 adapter->smartspeed = 0;
1817                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) ==
1818                     E1000_CTRL_EXT_LINK_MODE_GMII &&
1819                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1820                         device_printf(dev, "Link: thermal downshift\n");
1821                 /* Delay Link Up for Phy update */
1822                 if (((hw->mac.type == e1000_i210) ||
1823                     (hw->mac.type == e1000_i211)) &&
1824                     (hw->phy.id == I210_I_PHY_ID))
1825                         msec_delay(I210_LINK_DELAY);
1826                 /* Reset if the media type changed. */
1827                 if ((hw->dev_spec._82575.media_changed) &&
1828                         (adapter->hw.mac.type >= igb_mac_min)) {
1829                         hw->dev_spec._82575.media_changed = false;
1830                         adapter->flags |= IGB_MEDIA_RESET;
1831                         em_reset(ctx);
1832                 }
1833                 iflib_link_state_change(ctx, LINK_STATE_UP,
1834                     IF_Mbps(adapter->link_speed));
1835         } else if (!link_check && (adapter->link_active == 1)) {
1836                 adapter->link_speed = 0;
1837                 adapter->link_duplex = 0;
1838                 adapter->link_active = 0;
1839                 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
1840         }
1841         em_update_stats_counters(adapter);
1842
1843         /* Reset LAA into RAR[0] on 82571 */
1844         if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw))
1845                 e1000_rar_set(hw, hw->mac.addr, 0);
1846
1847         if (hw->mac.type < em_mac_min)
1848                 lem_smartspeed(adapter);
1849         else if (hw->mac.type == e1000_82574 &&
1850             adapter->intr_type == IFLIB_INTR_MSIX)
1851                 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK |
1852                     E1000_IMS_LSC);
1853 }
1854
1855 static void
1856 em_if_watchdog_reset(if_ctx_t ctx)
1857 {
1858         struct adapter *adapter = iflib_get_softc(ctx);
1859
1860         /*
1861          * Just count the event; iflib(4) will already trigger a
1862          * sufficient reset of the controller.
1863          */
1864         adapter->watchdog_events++;
1865 }
1866
1867 /*********************************************************************
1868  *
1869  *  This routine disables all traffic on the adapter by issuing a
1870  *  global reset on the MAC.
1871  *
1872  **********************************************************************/
1873 static void
1874 em_if_stop(if_ctx_t ctx)
1875 {
1876         struct adapter *adapter = iflib_get_softc(ctx);
1877
1878         INIT_DEBUGOUT("em_if_stop: begin");
1879
1880         e1000_reset_hw(&adapter->hw);
1881         if (adapter->hw.mac.type >= e1000_82544)
1882                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0);
1883
1884         e1000_led_off(&adapter->hw);
1885         e1000_cleanup_led(&adapter->hw);
1886 }
1887
1888 /*********************************************************************
1889  *
1890  *  Determine hardware revision.
1891  *
1892  **********************************************************************/
1893 static void
1894 em_identify_hardware(if_ctx_t ctx)
1895 {
1896         device_t dev = iflib_get_dev(ctx);
1897         struct adapter *adapter = iflib_get_softc(ctx);
1898
1899         /* Make sure our PCI config space has the necessary stuff set */
1900         adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1901
1902         /* Save off the information about this board */
1903         adapter->hw.vendor_id = pci_get_vendor(dev);
1904         adapter->hw.device_id = pci_get_device(dev);
1905         adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1906         adapter->hw.subsystem_vendor_id =
1907             pci_read_config(dev, PCIR_SUBVEND_0, 2);
1908         adapter->hw.subsystem_device_id =
1909             pci_read_config(dev, PCIR_SUBDEV_0, 2);
1910
1911         /* Do Shared Code Init and Setup */
1912         if (e1000_set_mac_type(&adapter->hw)) {
1913                 device_printf(dev, "Setup init failure\n");
1914                 return;
1915         }
1916 }
1917
1918 static int
1919 em_allocate_pci_resources(if_ctx_t ctx)
1920 {
1921         struct adapter *adapter = iflib_get_softc(ctx);
1922         device_t dev = iflib_get_dev(ctx);
1923         int rid, val;
1924
1925         rid = PCIR_BAR(0);
1926         adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1927             &rid, RF_ACTIVE);
1928         if (adapter->memory == NULL) {
1929                 device_printf(dev, "Unable to allocate bus resource: memory\n");
1930                 return (ENXIO);
1931         }
1932         adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory);
1933         adapter->osdep.mem_bus_space_handle =
1934             rman_get_bushandle(adapter->memory);
1935         adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle;
1936
1937         /* Only older adapters use IO mapping */
1938         if (adapter->hw.mac.type < em_mac_min &&
1939             adapter->hw.mac.type > e1000_82543) {
1940                 /* Figure our where our IO BAR is ? */
1941                 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1942                         val = pci_read_config(dev, rid, 4);
1943                         if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1944                                 break;
1945                         }
1946                         rid += 4;
1947                         /* check for 64bit BAR */
1948                         if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1949                                 rid += 4;
1950                 }
1951                 if (rid >= PCIR_CIS) {
1952                         device_printf(dev, "Unable to locate IO BAR\n");
1953                         return (ENXIO);
1954                 }
1955                 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
1956                     &rid, RF_ACTIVE);
1957                 if (adapter->ioport == NULL) {
1958                         device_printf(dev, "Unable to allocate bus resource: "
1959                             "ioport\n");
1960                         return (ENXIO);
1961                 }
1962                 adapter->hw.io_base = 0;
1963                 adapter->osdep.io_bus_space_tag =
1964                     rman_get_bustag(adapter->ioport);
1965                 adapter->osdep.io_bus_space_handle =
1966                     rman_get_bushandle(adapter->ioport);
1967         }
1968
1969         adapter->hw.back = &adapter->osdep;
1970
1971         return (0);
1972 }
1973
1974 /*********************************************************************
1975  *
1976  *  Set up the MSI-X Interrupt handlers
1977  *
1978  **********************************************************************/
1979 static int
1980 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
1981 {
1982         struct adapter *adapter = iflib_get_softc(ctx);
1983         struct em_rx_queue *rx_que = adapter->rx_queues;
1984         struct em_tx_queue *tx_que = adapter->tx_queues;
1985         int error, rid, i, vector = 0, rx_vectors;
1986         char buf[16];
1987
1988         /* First set up ring resources */
1989         for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) {
1990                 rid = vector + 1;
1991                 snprintf(buf, sizeof(buf), "rxq%d", i);
1992                 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
1993                 if (error) {
1994                         device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
1995                         adapter->rx_num_queues = i + 1;
1996                         goto fail;
1997                 }
1998
1999                 rx_que->msix =  vector;
2000
2001                 /*
2002                  * Set the bit to enable interrupt
2003                  * in E1000_IMS -- bits 20 and 21
2004                  * are for RX0 and RX1, note this has
2005                  * NOTHING to do with the MSI-X vector
2006                  */
2007                 if (adapter->hw.mac.type == e1000_82574) {
2008                         rx_que->eims = 1 << (20 + i);
2009                         adapter->ims |= rx_que->eims;
2010                         adapter->ivars |= (8 | rx_que->msix) << (i * 4);
2011                 } else if (adapter->hw.mac.type == e1000_82575)
2012                         rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
2013                 else
2014                         rx_que->eims = 1 << vector;
2015         }
2016         rx_vectors = vector;
2017
2018         vector = 0;
2019         for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) {
2020                 snprintf(buf, sizeof(buf), "txq%d", i);
2021                 tx_que = &adapter->tx_queues[i];
2022                 iflib_softirq_alloc_generic(ctx,
2023                     &adapter->rx_queues[i % adapter->rx_num_queues].que_irq,
2024                     IFLIB_INTR_TX, tx_que, tx_que->me, buf);
2025
2026                 tx_que->msix = (vector % adapter->rx_num_queues);
2027
2028                 /*
2029                  * Set the bit to enable interrupt
2030                  * in E1000_IMS -- bits 22 and 23
2031                  * are for TX0 and TX1, note this has
2032                  * NOTHING to do with the MSI-X vector
2033                  */
2034                 if (adapter->hw.mac.type == e1000_82574) {
2035                         tx_que->eims = 1 << (22 + i);
2036                         adapter->ims |= tx_que->eims;
2037                         adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
2038                 } else if (adapter->hw.mac.type == e1000_82575) {
2039                         tx_que->eims = E1000_EICR_TX_QUEUE0 << i;
2040                 } else {
2041                         tx_que->eims = 1 << i;
2042                 }
2043         }
2044
2045         /* Link interrupt */
2046         rid = rx_vectors + 1;
2047         error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq");
2048
2049         if (error) {
2050                 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
2051                 goto fail;
2052         }
2053         adapter->linkvec = rx_vectors;
2054         if (adapter->hw.mac.type < igb_mac_min) {
2055                 adapter->ivars |=  (8 | rx_vectors) << 16;
2056                 adapter->ivars |= 0x80000000;
2057         }
2058         return (0);
2059 fail:
2060         iflib_irq_free(ctx, &adapter->irq);
2061         rx_que = adapter->rx_queues;
2062         for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++)
2063                 iflib_irq_free(ctx, &rx_que->que_irq);
2064         return (error);
2065 }
2066
2067 static void
2068 igb_configure_queues(struct adapter *adapter)
2069 {
2070         struct e1000_hw *hw = &adapter->hw;
2071         struct em_rx_queue *rx_que;
2072         struct em_tx_queue *tx_que;
2073         u32 tmp, ivar = 0, newitr = 0;
2074
2075         /* First turn on RSS capability */
2076         if (adapter->hw.mac.type != e1000_82575)
2077                 E1000_WRITE_REG(hw, E1000_GPIE,
2078                     E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
2079                     E1000_GPIE_PBA | E1000_GPIE_NSICR);
2080
2081         /* Turn on MSI-X */
2082         switch (adapter->hw.mac.type) {
2083         case e1000_82580:
2084         case e1000_i350:
2085         case e1000_i354:
2086         case e1000_i210:
2087         case e1000_i211:
2088         case e1000_vfadapt:
2089         case e1000_vfadapt_i350:
2090                 /* RX entries */
2091                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2092                         u32 index = i >> 1;
2093                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2094                         rx_que = &adapter->rx_queues[i];
2095                         if (i & 1) {
2096                                 ivar &= 0xFF00FFFF;
2097                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2098                         } else {
2099                                 ivar &= 0xFFFFFF00;
2100                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2101                         }
2102                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2103                 }
2104                 /* TX entries */
2105                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2106                         u32 index = i >> 1;
2107                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2108                         tx_que = &adapter->tx_queues[i];
2109                         if (i & 1) {
2110                                 ivar &= 0x00FFFFFF;
2111                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2112                         } else {
2113                                 ivar &= 0xFFFF00FF;
2114                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2115                         }
2116                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2117                         adapter->que_mask |= tx_que->eims;
2118                 }
2119
2120                 /* And for the link interrupt */
2121                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2122                 adapter->link_mask = 1 << adapter->linkvec;
2123                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2124                 break;
2125         case e1000_82576:
2126                 /* RX entries */
2127                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2128                         u32 index = i & 0x7; /* Each IVAR has two entries */
2129                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2130                         rx_que = &adapter->rx_queues[i];
2131                         if (i < 8) {
2132                                 ivar &= 0xFFFFFF00;
2133                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2134                         } else {
2135                                 ivar &= 0xFF00FFFF;
2136                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2137                         }
2138                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2139                         adapter->que_mask |= rx_que->eims;
2140                 }
2141                 /* TX entries */
2142                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2143                         u32 index = i & 0x7; /* Each IVAR has two entries */
2144                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2145                         tx_que = &adapter->tx_queues[i];
2146                         if (i < 8) {
2147                                 ivar &= 0xFFFF00FF;
2148                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2149                         } else {
2150                                 ivar &= 0x00FFFFFF;
2151                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2152                         }
2153                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2154                         adapter->que_mask |= tx_que->eims;
2155                 }
2156
2157                 /* And for the link interrupt */
2158                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2159                 adapter->link_mask = 1 << adapter->linkvec;
2160                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2161                 break;
2162
2163         case e1000_82575:
2164                 /* enable MSI-X support*/
2165                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2166                 tmp |= E1000_CTRL_EXT_PBA_CLR;
2167                 /* Auto-Mask interrupts upon ICR read. */
2168                 tmp |= E1000_CTRL_EXT_EIAME;
2169                 tmp |= E1000_CTRL_EXT_IRCA;
2170                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2171
2172                 /* Queues */
2173                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2174                         rx_que = &adapter->rx_queues[i];
2175                         tmp = E1000_EICR_RX_QUEUE0 << i;
2176                         tmp |= E1000_EICR_TX_QUEUE0 << i;
2177                         rx_que->eims = tmp;
2178                         E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2179                             i, rx_que->eims);
2180                         adapter->que_mask |= rx_que->eims;
2181                 }
2182
2183                 /* Link */
2184                 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec),
2185                     E1000_EIMS_OTHER);
2186                 adapter->link_mask |= E1000_EIMS_OTHER;
2187         default:
2188                 break;
2189         }
2190
2191         /* Set the starting interrupt rate */
2192         if (em_max_interrupt_rate > 0)
2193                 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2194
2195         if (hw->mac.type == e1000_82575)
2196                 newitr |= newitr << 16;
2197         else
2198                 newitr |= E1000_EITR_CNT_IGNR;
2199
2200         for (int i = 0; i < adapter->rx_num_queues; i++) {
2201                 rx_que = &adapter->rx_queues[i];
2202                 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2203         }
2204
2205         return;
2206 }
2207
2208 static void
2209 em_free_pci_resources(if_ctx_t ctx)
2210 {
2211         struct adapter *adapter = iflib_get_softc(ctx);
2212         struct em_rx_queue *que = adapter->rx_queues;
2213         device_t dev = iflib_get_dev(ctx);
2214
2215         /* Release all MSI-X queue resources */
2216         if (adapter->intr_type == IFLIB_INTR_MSIX)
2217                 iflib_irq_free(ctx, &adapter->irq);
2218
2219         for (int i = 0; i < adapter->rx_num_queues; i++, que++) {
2220                 iflib_irq_free(ctx, &que->que_irq);
2221         }
2222
2223         if (adapter->memory != NULL) {
2224                 bus_release_resource(dev, SYS_RES_MEMORY,
2225                     rman_get_rid(adapter->memory), adapter->memory);
2226                 adapter->memory = NULL;
2227         }
2228
2229         if (adapter->flash != NULL) {
2230                 bus_release_resource(dev, SYS_RES_MEMORY,
2231                     rman_get_rid(adapter->flash), adapter->flash);
2232                 adapter->flash = NULL;
2233         }
2234
2235         if (adapter->ioport != NULL) {
2236                 bus_release_resource(dev, SYS_RES_IOPORT,
2237                     rman_get_rid(adapter->ioport), adapter->ioport);
2238                 adapter->ioport = NULL;
2239         }
2240 }
2241
2242 /* Set up MSI or MSI-X */
2243 static int
2244 em_setup_msix(if_ctx_t ctx)
2245 {
2246         struct adapter *adapter = iflib_get_softc(ctx);
2247
2248         if (adapter->hw.mac.type == e1000_82574) {
2249                 em_enable_vectors_82574(ctx);
2250         }
2251         return (0);
2252 }
2253
2254 /*********************************************************************
2255  *
2256  *  Workaround for SmartSpeed on 82541 and 82547 controllers
2257  *
2258  **********************************************************************/
2259 static void
2260 lem_smartspeed(struct adapter *adapter)
2261 {
2262         u16 phy_tmp;
2263
2264         if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) ||
2265             adapter->hw.mac.autoneg == 0 ||
2266             (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2267                 return;
2268
2269         if (adapter->smartspeed == 0) {
2270                 /* If Master/Slave config fault is asserted twice,
2271                  * we assume back-to-back */
2272                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2273                 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2274                         return;
2275                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2276                 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2277                         e1000_read_phy_reg(&adapter->hw,
2278                             PHY_1000T_CTRL, &phy_tmp);
2279                         if(phy_tmp & CR_1000T_MS_ENABLE) {
2280                                 phy_tmp &= ~CR_1000T_MS_ENABLE;
2281                                 e1000_write_phy_reg(&adapter->hw,
2282                                     PHY_1000T_CTRL, phy_tmp);
2283                                 adapter->smartspeed++;
2284                                 if(adapter->hw.mac.autoneg &&
2285                                    !e1000_copper_link_autoneg(&adapter->hw) &&
2286                                    !e1000_read_phy_reg(&adapter->hw,
2287                                     PHY_CONTROL, &phy_tmp)) {
2288                                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2289                                                     MII_CR_RESTART_AUTO_NEG);
2290                                         e1000_write_phy_reg(&adapter->hw,
2291                                             PHY_CONTROL, phy_tmp);
2292                                 }
2293                         }
2294                 }
2295                 return;
2296         } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2297                 /* If still no link, perhaps using 2/3 pair cable */
2298                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2299                 phy_tmp |= CR_1000T_MS_ENABLE;
2300                 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2301                 if(adapter->hw.mac.autoneg &&
2302                    !e1000_copper_link_autoneg(&adapter->hw) &&
2303                    !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2304                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2305                                     MII_CR_RESTART_AUTO_NEG);
2306                         e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2307                 }
2308         }
2309         /* Restart process after EM_SMARTSPEED_MAX iterations */
2310         if(adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2311                 adapter->smartspeed = 0;
2312 }
2313
2314 /*********************************************************************
2315  *
2316  *  Initialize the DMA Coalescing feature
2317  *
2318  **********************************************************************/
2319 static void
2320 igb_init_dmac(struct adapter *adapter, u32 pba)
2321 {
2322         device_t        dev = adapter->dev;
2323         struct e1000_hw *hw = &adapter->hw;
2324         u32             dmac, reg = ~E1000_DMACR_DMAC_EN;
2325         u16             hwm;
2326         u16             max_frame_size;
2327
2328         if (hw->mac.type == e1000_i211)
2329                 return;
2330
2331         max_frame_size = adapter->shared->isc_max_frame_size;
2332         if (hw->mac.type > e1000_82580) {
2333
2334                 if (adapter->dmac == 0) { /* Disabling it */
2335                         E1000_WRITE_REG(hw, E1000_DMACR, reg);
2336                         return;
2337                 } else
2338                         device_printf(dev, "DMA Coalescing enabled\n");
2339
2340                 /* Set starting threshold */
2341                 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
2342
2343                 hwm = 64 * pba - max_frame_size / 16;
2344                 if (hwm < 64 * (pba - 6))
2345                         hwm = 64 * (pba - 6);
2346                 reg = E1000_READ_REG(hw, E1000_FCRTC);
2347                 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
2348                 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
2349                     & E1000_FCRTC_RTH_COAL_MASK);
2350                 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
2351
2352
2353                 dmac = pba - max_frame_size / 512;
2354                 if (dmac < pba - 10)
2355                         dmac = pba - 10;
2356                 reg = E1000_READ_REG(hw, E1000_DMACR);
2357                 reg &= ~E1000_DMACR_DMACTHR_MASK;
2358                 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT)
2359                     & E1000_DMACR_DMACTHR_MASK);
2360
2361                 /* transition to L0x or L1 if available..*/
2362                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
2363
2364                 /* Check if status is 2.5Gb backplane connection
2365                 * before configuration of watchdog timer, which is
2366                 * in msec values in 12.8usec intervals
2367                 * watchdog timer= msec values in 32usec intervals
2368                 * for non 2.5Gb connection
2369                 */
2370                 if (hw->mac.type == e1000_i354) {
2371                         int status = E1000_READ_REG(hw, E1000_STATUS);
2372                         if ((status & E1000_STATUS_2P5_SKU) &&
2373                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2374                                 reg |= ((adapter->dmac * 5) >> 6);
2375                         else
2376                                 reg |= (adapter->dmac >> 5);
2377                 } else {
2378                         reg |= (adapter->dmac >> 5);
2379                 }
2380
2381                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2382
2383                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
2384
2385                 /* Set the interval before transition */
2386                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
2387                 if (hw->mac.type == e1000_i350)
2388                         reg |= IGB_DMCTLX_DCFLUSH_DIS;
2389                 /*
2390                 ** in 2.5Gb connection, TTLX unit is 0.4 usec
2391                 ** which is 0x4*2 = 0xA. But delay is still 4 usec
2392                 */
2393                 if (hw->mac.type == e1000_i354) {
2394                         int status = E1000_READ_REG(hw, E1000_STATUS);
2395                         if ((status & E1000_STATUS_2P5_SKU) &&
2396                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2397                                 reg |= 0xA;
2398                         else
2399                                 reg |= 0x4;
2400                 } else {
2401                         reg |= 0x4;
2402                 }
2403
2404                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
2405
2406                 /* free space in tx packet buffer to wake from DMA coal */
2407                 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE -
2408                     (2 * max_frame_size)) >> 6);
2409
2410                 /* make low power state decision controlled by DMA coal */
2411                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2412                 reg &= ~E1000_PCIEMISC_LX_DECISION;
2413                 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
2414
2415         } else if (hw->mac.type == e1000_82580) {
2416                 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2417                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
2418                     reg & ~E1000_PCIEMISC_LX_DECISION);
2419                 E1000_WRITE_REG(hw, E1000_DMACR, 0);
2420         }
2421 }
2422
2423 /*********************************************************************
2424  *
2425  *  Initialize the hardware to a configuration as specified by the
2426  *  adapter structure.
2427  *
2428  **********************************************************************/
2429 static void
2430 em_reset(if_ctx_t ctx)
2431 {
2432         device_t dev = iflib_get_dev(ctx);
2433         struct adapter *adapter = iflib_get_softc(ctx);
2434         struct ifnet *ifp = iflib_get_ifp(ctx);
2435         struct e1000_hw *hw = &adapter->hw;
2436         u16 rx_buffer_size;
2437         u32 pba;
2438
2439         INIT_DEBUGOUT("em_reset: begin");
2440         /* Let the firmware know the OS is in control */
2441         em_get_hw_control(adapter);
2442
2443         /* Set up smart power down as default off on newer adapters. */
2444         if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2445             hw->mac.type == e1000_82572)) {
2446                 u16 phy_tmp = 0;
2447
2448                 /* Speed up time to link by disabling smart power down. */
2449                 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2450                 phy_tmp &= ~IGP02E1000_PM_SPD;
2451                 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2452         }
2453
2454         /*
2455          * Packet Buffer Allocation (PBA)
2456          * Writing PBA sets the receive portion of the buffer
2457          * the remainder is used for the transmit buffer.
2458          */
2459         switch (hw->mac.type) {
2460         /* Total Packet Buffer on these is 48K */
2461         case e1000_82571:
2462         case e1000_82572:
2463         case e1000_80003es2lan:
2464                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2465                 break;
2466         case e1000_82573: /* 82573: Total Packet Buffer is 32K */
2467                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2468                 break;
2469         case e1000_82574:
2470         case e1000_82583:
2471                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2472                 break;
2473         case e1000_ich8lan:
2474                 pba = E1000_PBA_8K;
2475                 break;
2476         case e1000_ich9lan:
2477         case e1000_ich10lan:
2478                 /* Boost Receive side for jumbo frames */
2479                 if (adapter->hw.mac.max_frame_size > 4096)
2480                         pba = E1000_PBA_14K;
2481                 else
2482                         pba = E1000_PBA_10K;
2483                 break;
2484         case e1000_pchlan:
2485         case e1000_pch2lan:
2486         case e1000_pch_lpt:
2487         case e1000_pch_spt:
2488         case e1000_pch_cnp:
2489                 pba = E1000_PBA_26K;
2490                 break;
2491         case e1000_82575:
2492                 pba = E1000_PBA_32K;
2493                 break;
2494         case e1000_82576:
2495         case e1000_vfadapt:
2496                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2497                 pba &= E1000_RXPBS_SIZE_MASK_82576;
2498                 break;
2499         case e1000_82580:
2500         case e1000_i350:
2501         case e1000_i354:
2502         case e1000_vfadapt_i350:
2503                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2504                 pba = e1000_rxpbs_adjust_82580(pba);
2505                 break;
2506         case e1000_i210:
2507         case e1000_i211:
2508                 pba = E1000_PBA_34K;
2509                 break;
2510         default:
2511                 if (adapter->hw.mac.max_frame_size > 8192)
2512                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2513                 else
2514                         pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2515         }
2516
2517         /* Special needs in case of Jumbo frames */
2518         if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) {
2519                 u32 tx_space, min_tx, min_rx;
2520                 pba = E1000_READ_REG(hw, E1000_PBA);
2521                 tx_space = pba >> 16;
2522                 pba &= 0xffff;
2523                 min_tx = (adapter->hw.mac.max_frame_size +
2524                     sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
2525                 min_tx = roundup2(min_tx, 1024);
2526                 min_tx >>= 10;
2527                 min_rx = adapter->hw.mac.max_frame_size;
2528                 min_rx = roundup2(min_rx, 1024);
2529                 min_rx >>= 10;
2530                 if (tx_space < min_tx &&
2531                     ((min_tx - tx_space) < pba)) {
2532                         pba = pba - (min_tx - tx_space);
2533                         /*
2534                          * if short on rx space, rx wins
2535                          * and must trump tx adjustment
2536                          */
2537                         if (pba < min_rx)
2538                                 pba = min_rx;
2539                 }
2540                 E1000_WRITE_REG(hw, E1000_PBA, pba);
2541         }
2542
2543         if (hw->mac.type < igb_mac_min)
2544                 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
2545
2546         INIT_DEBUGOUT1("em_reset: pba=%dK",pba);
2547
2548         /*
2549          * These parameters control the automatic generation (Tx) and
2550          * response (Rx) to Ethernet PAUSE frames.
2551          * - High water mark should allow for at least two frames to be
2552          *   received after sending an XOFF.
2553          * - Low water mark works best when it is very near the high water mark.
2554          *   This allows the receiver to restart by sending XON when it has
2555          *   drained a bit. Here we use an arbitrary value of 1500 which will
2556          *   restart after one full frame is pulled from the buffer. There
2557          *   could be several smaller frames in the buffer and if so they will
2558          *   not trigger the XON until their total number reduces the buffer
2559          *   by 1500.
2560          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2561          */
2562         rx_buffer_size = (pba & 0xffff) << 10;
2563         hw->fc.high_water = rx_buffer_size -
2564             roundup2(adapter->hw.mac.max_frame_size, 1024);
2565         hw->fc.low_water = hw->fc.high_water - 1500;
2566
2567         if (adapter->fc) /* locally set flow control value? */
2568                 hw->fc.requested_mode = adapter->fc;
2569         else
2570                 hw->fc.requested_mode = e1000_fc_full;
2571
2572         if (hw->mac.type == e1000_80003es2lan)
2573                 hw->fc.pause_time = 0xFFFF;
2574         else
2575                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
2576
2577         hw->fc.send_xon = TRUE;
2578
2579         /* Device specific overrides/settings */
2580         switch (hw->mac.type) {
2581         case e1000_pchlan:
2582                 /* Workaround: no TX flow ctrl for PCH */
2583                 hw->fc.requested_mode = e1000_fc_rx_pause;
2584                 hw->fc.pause_time = 0xFFFF; /* override */
2585                 if (if_getmtu(ifp) > ETHERMTU) {
2586                         hw->fc.high_water = 0x3500;
2587                         hw->fc.low_water = 0x1500;
2588                 } else {
2589                         hw->fc.high_water = 0x5000;
2590                         hw->fc.low_water = 0x3000;
2591                 }
2592                 hw->fc.refresh_time = 0x1000;
2593                 break;
2594         case e1000_pch2lan:
2595         case e1000_pch_lpt:
2596         case e1000_pch_spt:
2597         case e1000_pch_cnp:
2598                 hw->fc.high_water = 0x5C20;
2599                 hw->fc.low_water = 0x5048;
2600                 hw->fc.pause_time = 0x0650;
2601                 hw->fc.refresh_time = 0x0400;
2602                 /* Jumbos need adjusted PBA */
2603                 if (if_getmtu(ifp) > ETHERMTU)
2604                         E1000_WRITE_REG(hw, E1000_PBA, 12);
2605                 else
2606                         E1000_WRITE_REG(hw, E1000_PBA, 26);
2607                 break;
2608         case e1000_82575:
2609         case e1000_82576:
2610                 /* 8-byte granularity */
2611                 hw->fc.low_water = hw->fc.high_water - 8;
2612                 break;
2613         case e1000_82580:
2614         case e1000_i350:
2615         case e1000_i354:
2616         case e1000_i210:
2617         case e1000_i211:
2618         case e1000_vfadapt:
2619         case e1000_vfadapt_i350:
2620                 /* 16-byte granularity */
2621                 hw->fc.low_water = hw->fc.high_water - 16;
2622                 break;
2623         case e1000_ich9lan:
2624         case e1000_ich10lan:
2625                 if (if_getmtu(ifp) > ETHERMTU) {
2626                         hw->fc.high_water = 0x2800;
2627                         hw->fc.low_water = hw->fc.high_water - 8;
2628                         break;
2629                 }
2630                 /* FALLTHROUGH */
2631         default:
2632                 if (hw->mac.type == e1000_80003es2lan)
2633                         hw->fc.pause_time = 0xFFFF;
2634                 break;
2635         }
2636
2637         /* Issue a global reset */
2638         e1000_reset_hw(hw);
2639         if (adapter->hw.mac.type >= igb_mac_min) {
2640                 E1000_WRITE_REG(hw, E1000_WUC, 0);
2641         } else {
2642                 E1000_WRITE_REG(hw, E1000_WUFC, 0);
2643                 em_disable_aspm(adapter);
2644         }
2645         if (adapter->flags & IGB_MEDIA_RESET) {
2646                 e1000_setup_init_funcs(hw, TRUE);
2647                 e1000_get_bus_info(hw);
2648                 adapter->flags &= ~IGB_MEDIA_RESET;
2649         }
2650         /* and a re-init */
2651         if (e1000_init_hw(hw) < 0) {
2652                 device_printf(dev, "Hardware Initialization Failed\n");
2653                 return;
2654         }
2655         if (adapter->hw.mac.type >= igb_mac_min)
2656                 igb_init_dmac(adapter, pba);
2657
2658         E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2659         e1000_get_phy_info(hw);
2660         e1000_check_for_link(hw);
2661 }
2662
2663 /*
2664  * Initialise the RSS mapping for NICs that support multiple transmit/
2665  * receive rings.
2666  */
2667
2668 #define RSSKEYLEN 10
2669 static void
2670 em_initialize_rss_mapping(struct adapter *adapter)
2671 {
2672         uint8_t  rss_key[4 * RSSKEYLEN];
2673         uint32_t reta = 0;
2674         struct e1000_hw *hw = &adapter->hw;
2675         int i;
2676
2677         /*
2678          * Configure RSS key
2679          */
2680         arc4rand(rss_key, sizeof(rss_key), 0);
2681         for (i = 0; i < RSSKEYLEN; ++i) {
2682                 uint32_t rssrk = 0;
2683
2684                 rssrk = EM_RSSRK_VAL(rss_key, i);
2685                 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2686         }
2687
2688         /*
2689          * Configure RSS redirect table in following fashion:
2690          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2691          */
2692         for (i = 0; i < sizeof(reta); ++i) {
2693                 uint32_t q;
2694
2695                 q = (i % adapter->rx_num_queues) << 7;
2696                 reta |= q << (8 * i);
2697         }
2698
2699         for (i = 0; i < 32; ++i)
2700                 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2701
2702         E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2703                         E1000_MRQC_RSS_FIELD_IPV4_TCP |
2704                         E1000_MRQC_RSS_FIELD_IPV4 |
2705                         E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2706                         E1000_MRQC_RSS_FIELD_IPV6_EX |
2707                         E1000_MRQC_RSS_FIELD_IPV6);
2708 }
2709
2710 static void
2711 igb_initialize_rss_mapping(struct adapter *adapter)
2712 {
2713         struct e1000_hw *hw = &adapter->hw;
2714         int i;
2715         int queue_id;
2716         u32 reta;
2717         u32 rss_key[10], mrqc, shift = 0;
2718
2719         /* XXX? */
2720         if (adapter->hw.mac.type == e1000_82575)
2721                 shift = 6;
2722
2723         /*
2724          * The redirection table controls which destination
2725          * queue each bucket redirects traffic to.
2726          * Each DWORD represents four queues, with the LSB
2727          * being the first queue in the DWORD.
2728          *
2729          * This just allocates buckets to queues using round-robin
2730          * allocation.
2731          *
2732          * NOTE: It Just Happens to line up with the default
2733          * RSS allocation method.
2734          */
2735
2736         /* Warning FM follows */
2737         reta = 0;
2738         for (i = 0; i < 128; i++) {
2739 #ifdef RSS
2740                 queue_id = rss_get_indirection_to_bucket(i);
2741                 /*
2742                  * If we have more queues than buckets, we'll
2743                  * end up mapping buckets to a subset of the
2744                  * queues.
2745                  *
2746                  * If we have more buckets than queues, we'll
2747                  * end up instead assigning multiple buckets
2748                  * to queues.
2749                  *
2750                  * Both are suboptimal, but we need to handle
2751                  * the case so we don't go out of bounds
2752                  * indexing arrays and such.
2753                  */
2754                 queue_id = queue_id % adapter->rx_num_queues;
2755 #else
2756                 queue_id = (i % adapter->rx_num_queues);
2757 #endif
2758                 /* Adjust if required */
2759                 queue_id = queue_id << shift;
2760
2761                 /*
2762                  * The low 8 bits are for hash value (n+0);
2763                  * The next 8 bits are for hash value (n+1), etc.
2764                  */
2765                 reta = reta >> 8;
2766                 reta = reta | ( ((uint32_t) queue_id) << 24);
2767                 if ((i & 3) == 3) {
2768                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2769                         reta = 0;
2770                 }
2771         }
2772
2773         /* Now fill in hash table */
2774
2775         /*
2776          * MRQC: Multiple Receive Queues Command
2777          * Set queuing to RSS control, number depends on the device.
2778          */
2779         mrqc = E1000_MRQC_ENABLE_RSS_8Q;
2780
2781 #ifdef RSS
2782         /* XXX ew typecasting */
2783         rss_getkey((uint8_t *) &rss_key);
2784 #else
2785         arc4rand(&rss_key, sizeof(rss_key), 0);
2786 #endif
2787         for (i = 0; i < 10; i++)
2788                 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]);
2789
2790         /*
2791          * Configure the RSS fields to hash upon.
2792          */
2793         mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2794             E1000_MRQC_RSS_FIELD_IPV4_TCP);
2795         mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2796             E1000_MRQC_RSS_FIELD_IPV6_TCP);
2797         mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2798             E1000_MRQC_RSS_FIELD_IPV6_UDP);
2799         mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2800             E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2801
2802         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2803 }
2804
2805 /*********************************************************************
2806  *
2807  *  Setup networking device structure and register interface media.
2808  *
2809  **********************************************************************/
2810 static int
2811 em_setup_interface(if_ctx_t ctx)
2812 {
2813         struct ifnet *ifp = iflib_get_ifp(ctx);
2814         struct adapter *adapter = iflib_get_softc(ctx);
2815         if_softc_ctx_t scctx = adapter->shared;
2816
2817         INIT_DEBUGOUT("em_setup_interface: begin");
2818
2819         /* Single Queue */
2820         if (adapter->tx_num_queues == 1) {
2821                 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
2822                 if_setsendqready(ifp);
2823         }
2824
2825         /*
2826          * Specify the media types supported by this adapter and register
2827          * callbacks to update media and link information
2828          */
2829         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
2830             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
2831                 u_char fiber_type = IFM_1000_SX;        /* default type */
2832
2833                 if (adapter->hw.mac.type == e1000_82545)
2834                         fiber_type = IFM_1000_LX;
2835                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
2836                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2837         } else {
2838                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2839                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2840                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2841                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2842                 if (adapter->hw.phy.type != e1000_phy_ife) {
2843                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2844                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2845                 }
2846         }
2847         ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2848         ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO);
2849         return (0);
2850 }
2851
2852 static int
2853 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
2854 {
2855         struct adapter *adapter = iflib_get_softc(ctx);
2856         if_softc_ctx_t scctx = adapter->shared;
2857         int error = E1000_SUCCESS;
2858         struct em_tx_queue *que;
2859         int i, j;
2860
2861         MPASS(adapter->tx_num_queues > 0);
2862         MPASS(adapter->tx_num_queues == ntxqsets);
2863
2864         /* First allocate the top level queue structs */
2865         if (!(adapter->tx_queues =
2866             (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
2867             adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2868                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2869                 return(ENOMEM);
2870         }
2871
2872         for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) {
2873                 /* Set up some basics */
2874
2875                 struct tx_ring *txr = &que->txr;
2876                 txr->adapter = que->adapter = adapter;
2877                 que->me = txr->me =  i;
2878
2879                 /* Allocate report status array */
2880                 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2881                         device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n");
2882                         error = ENOMEM;
2883                         goto fail;
2884                 }
2885                 for (j = 0; j < scctx->isc_ntxd[0]; j++)
2886                         txr->tx_rsq[j] = QIDX_INVALID;
2887                 /* get the virtual and physical address of the hardware queues */
2888                 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
2889                 txr->tx_paddr = paddrs[i*ntxqs];
2890         }
2891
2892         if (bootverbose)
2893                 device_printf(iflib_get_dev(ctx),
2894                     "allocated for %d tx_queues\n", adapter->tx_num_queues);
2895         return (0);
2896 fail:
2897         em_if_queues_free(ctx);
2898         return (error);
2899 }
2900
2901 static int
2902 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
2903 {
2904         struct adapter *adapter = iflib_get_softc(ctx);
2905         int error = E1000_SUCCESS;
2906         struct em_rx_queue *que;
2907         int i;
2908
2909         MPASS(adapter->rx_num_queues > 0);
2910         MPASS(adapter->rx_num_queues == nrxqsets);
2911
2912         /* First allocate the top level queue structs */
2913         if (!(adapter->rx_queues =
2914             (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
2915             adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2916                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2917                 error = ENOMEM;
2918                 goto fail;
2919         }
2920
2921         for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) {
2922                 /* Set up some basics */
2923                 struct rx_ring *rxr = &que->rxr;
2924                 rxr->adapter = que->adapter = adapter;
2925                 rxr->que = que;
2926                 que->me = rxr->me =  i;
2927
2928                 /* get the virtual and physical address of the hardware queues */
2929                 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
2930                 rxr->rx_paddr = paddrs[i*nrxqs];
2931         }
2932
2933         if (bootverbose)
2934                 device_printf(iflib_get_dev(ctx),
2935                     "allocated for %d rx_queues\n", adapter->rx_num_queues);
2936
2937         return (0);
2938 fail:
2939         em_if_queues_free(ctx);
2940         return (error);
2941 }
2942
2943 static void
2944 em_if_queues_free(if_ctx_t ctx)
2945 {
2946         struct adapter *adapter = iflib_get_softc(ctx);
2947         struct em_tx_queue *tx_que = adapter->tx_queues;
2948         struct em_rx_queue *rx_que = adapter->rx_queues;
2949
2950         if (tx_que != NULL) {
2951                 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
2952                         struct tx_ring *txr = &tx_que->txr;
2953                         if (txr->tx_rsq == NULL)
2954                                 break;
2955
2956                         free(txr->tx_rsq, M_DEVBUF);
2957                         txr->tx_rsq = NULL;
2958                 }
2959                 free(adapter->tx_queues, M_DEVBUF);
2960                 adapter->tx_queues = NULL;
2961         }
2962
2963         if (rx_que != NULL) {
2964                 free(adapter->rx_queues, M_DEVBUF);
2965                 adapter->rx_queues = NULL;
2966         }
2967
2968         em_release_hw_control(adapter);
2969
2970         if (adapter->mta != NULL) {
2971                 free(adapter->mta, M_DEVBUF);
2972         }
2973 }
2974
2975 /*********************************************************************
2976  *
2977  *  Enable transmit unit.
2978  *
2979  **********************************************************************/
2980 static void
2981 em_initialize_transmit_unit(if_ctx_t ctx)
2982 {
2983         struct adapter *adapter = iflib_get_softc(ctx);
2984         if_softc_ctx_t scctx = adapter->shared;
2985         struct em_tx_queue *que;
2986         struct tx_ring  *txr;
2987         struct e1000_hw *hw = &adapter->hw;
2988         u32 tctl, txdctl = 0, tarc, tipg = 0;
2989
2990         INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
2991
2992         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
2993                 u64 bus_addr;
2994                 caddr_t offp, endp;
2995
2996                 que = &adapter->tx_queues[i];
2997                 txr = &que->txr;
2998                 bus_addr = txr->tx_paddr;
2999
3000                 /* Clear checksum offload context. */
3001                 offp = (caddr_t)&txr->csum_flags;
3002                 endp = (caddr_t)(txr + 1);
3003                 bzero(offp, endp - offp);
3004
3005                 /* Base and Len of TX Ring */
3006                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
3007                     scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
3008                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
3009                     (u32)(bus_addr >> 32));
3010                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
3011                     (u32)bus_addr);
3012                 /* Init the HEAD/TAIL indices */
3013                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
3014                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
3015
3016                 HW_DEBUGOUT2("Base = %x, Length = %x\n",
3017                     E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)),
3018                     E1000_READ_REG(&adapter->hw, E1000_TDLEN(i)));
3019
3020                 txdctl = 0; /* clear txdctl */
3021                 txdctl |= 0x1f; /* PTHRESH */
3022                 txdctl |= 1 << 8; /* HTHRESH */
3023                 txdctl |= 1 << 16;/* WTHRESH */
3024                 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
3025                 txdctl |= E1000_TXDCTL_GRAN;
3026                 txdctl |= 1 << 25; /* LWTHRESH */
3027
3028                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
3029         }
3030
3031         /* Set the default values for the Tx Inter Packet Gap timer */
3032         switch (adapter->hw.mac.type) {
3033         case e1000_80003es2lan:
3034                 tipg = DEFAULT_82543_TIPG_IPGR1;
3035                 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
3036                     E1000_TIPG_IPGR2_SHIFT;
3037                 break;
3038         case e1000_82542:
3039                 tipg = DEFAULT_82542_TIPG_IPGT;
3040                 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3041                 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3042                 break;
3043         default:
3044                 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
3045                     (adapter->hw.phy.media_type ==
3046                     e1000_media_type_internal_serdes))
3047                         tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
3048                 else
3049                         tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
3050                 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3051                 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3052         }
3053
3054         E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
3055         E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value);
3056
3057         if(adapter->hw.mac.type >= e1000_82540)
3058                 E1000_WRITE_REG(&adapter->hw, E1000_TADV,
3059                     adapter->tx_abs_int_delay.value);
3060
3061         if ((adapter->hw.mac.type == e1000_82571) ||
3062             (adapter->hw.mac.type == e1000_82572)) {
3063                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3064                 tarc |= TARC_SPEED_MODE_BIT;
3065                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3066         } else if (adapter->hw.mac.type == e1000_80003es2lan) {
3067                 /* errata: program both queues to unweighted RR */
3068                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3069                 tarc |= 1;
3070                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3071                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
3072                 tarc |= 1;
3073                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
3074         } else if (adapter->hw.mac.type == e1000_82574) {
3075                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3076                 tarc |= TARC_ERRATA_BIT;
3077                 if ( adapter->tx_num_queues > 1) {
3078                         tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
3079                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3080                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
3081                 } else
3082                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3083         }
3084
3085         if (adapter->tx_int_delay.value > 0)
3086                 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3087
3088         /* Program the Transmit Control Register */
3089         tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
3090         tctl &= ~E1000_TCTL_CT;
3091         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
3092                    (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
3093
3094         if (adapter->hw.mac.type >= e1000_82571)
3095                 tctl |= E1000_TCTL_MULR;
3096
3097         /* This write will effectively turn on the transmit unit. */
3098         E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
3099
3100         /* SPT and KBL errata workarounds */
3101         if (hw->mac.type == e1000_pch_spt) {
3102                 u32 reg;
3103                 reg = E1000_READ_REG(hw, E1000_IOSFPC);
3104                 reg |= E1000_RCTL_RDMTS_HEX;
3105                 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
3106                 /* i218-i219 Specification Update 1.5.4.5 */
3107                 reg = E1000_READ_REG(hw, E1000_TARC(0));
3108                 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3109                 reg |= E1000_TARC0_CB_MULTIQ_2_REQ;
3110                 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3111         }
3112 }
3113
3114 /*********************************************************************
3115  *
3116  *  Enable receive unit.
3117  *
3118  **********************************************************************/
3119
3120 static void
3121 em_initialize_receive_unit(if_ctx_t ctx)
3122 {
3123         struct adapter *adapter = iflib_get_softc(ctx);
3124         if_softc_ctx_t scctx = adapter->shared;
3125         struct ifnet *ifp = iflib_get_ifp(ctx);
3126         struct e1000_hw *hw = &adapter->hw;
3127         struct em_rx_queue *que;
3128         int i;
3129         u32 rctl, rxcsum, rfctl;
3130
3131         INIT_DEBUGOUT("em_initialize_receive_units: begin");
3132
3133         /*
3134          * Make sure receives are disabled while setting
3135          * up the descriptor ring
3136          */
3137         rctl = E1000_READ_REG(hw, E1000_RCTL);
3138         /* Do not disable if ever enabled on this hardware */
3139         if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
3140                 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3141
3142         /* Setup the Receive Control Register */
3143         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3144         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3145             E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3146             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3147
3148         /* Do not store bad packets */
3149         rctl &= ~E1000_RCTL_SBP;
3150
3151         /* Enable Long Packet receive */
3152         if (if_getmtu(ifp) > ETHERMTU)
3153                 rctl |= E1000_RCTL_LPE;
3154         else
3155                 rctl &= ~E1000_RCTL_LPE;
3156
3157         /* Strip the CRC */
3158         if (!em_disable_crc_stripping)
3159                 rctl |= E1000_RCTL_SECRC;
3160
3161         if (adapter->hw.mac.type >= e1000_82540) {
3162                 E1000_WRITE_REG(&adapter->hw, E1000_RADV,
3163                             adapter->rx_abs_int_delay.value);
3164
3165                 /*
3166                  * Set the interrupt throttling rate. Value is calculated
3167                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
3168                  */
3169                 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
3170         }
3171         E1000_WRITE_REG(&adapter->hw, E1000_RDTR,
3172             adapter->rx_int_delay.value);
3173
3174         /* Use extended rx descriptor formats */
3175         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3176         rfctl |= E1000_RFCTL_EXTEN;
3177         /*
3178          * When using MSI-X interrupts we need to throttle
3179          * using the EITR register (82574 only)
3180          */
3181         if (hw->mac.type == e1000_82574) {
3182                 for (int i = 0; i < 4; i++)
3183                         E1000_WRITE_REG(hw, E1000_EITR_82574(i),
3184                             DEFAULT_ITR);
3185                 /* Disable accelerated acknowledge */
3186                 rfctl |= E1000_RFCTL_ACK_DIS;
3187         }
3188         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3189
3190         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
3191         if (if_getcapenable(ifp) & IFCAP_RXCSUM &&
3192             adapter->hw.mac.type >= e1000_82543) {
3193                 if (adapter->tx_num_queues > 1) {
3194                         if (adapter->hw.mac.type >= igb_mac_min) {
3195                                 rxcsum |= E1000_RXCSUM_PCSD;
3196                                 if (hw->mac.type != e1000_82575)
3197                                         rxcsum |= E1000_RXCSUM_CRCOFL;
3198                         } else
3199                                 rxcsum |= E1000_RXCSUM_TUOFL |
3200                                         E1000_RXCSUM_IPOFL |
3201                                         E1000_RXCSUM_PCSD;
3202                 } else {
3203                         if (adapter->hw.mac.type >= igb_mac_min)
3204                                 rxcsum |= E1000_RXCSUM_IPPCSE;
3205                         else
3206                                 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
3207                         if (adapter->hw.mac.type > e1000_82575)
3208                                 rxcsum |= E1000_RXCSUM_CRCOFL;
3209                 }
3210         } else
3211                 rxcsum &= ~E1000_RXCSUM_TUOFL;
3212
3213         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
3214
3215         if (adapter->rx_num_queues > 1) {
3216                 if (adapter->hw.mac.type >= igb_mac_min)
3217                         igb_initialize_rss_mapping(adapter);
3218                 else
3219                         em_initialize_rss_mapping(adapter);
3220         }
3221
3222         /*
3223          * XXX TEMPORARY WORKAROUND: on some systems with 82573
3224          * long latencies are observed, like Lenovo X60. This
3225          * change eliminates the problem, but since having positive
3226          * values in RDTR is a known source of problems on other
3227          * platforms another solution is being sought.
3228          */
3229         if (hw->mac.type == e1000_82573)
3230                 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
3231
3232         for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3233                 struct rx_ring *rxr = &que->rxr;
3234                 /* Setup the Base and Length of the Rx Descriptor Ring */
3235                 u64 bus_addr = rxr->rx_paddr;
3236 #if 0
3237                 u32 rdt = adapter->rx_num_queues -1;  /* default */
3238 #endif
3239
3240                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3241                     scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
3242                 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
3243                 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
3244                 /* Setup the Head and Tail Descriptor Pointers */
3245                 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
3246                 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
3247         }
3248
3249         /*
3250          * Set PTHRESH for improved jumbo performance
3251          * According to 10.2.5.11 of Intel 82574 Datasheet,
3252          * RXDCTL(1) is written whenever RXDCTL(0) is written.
3253          * Only write to RXDCTL(1) if there is a need for different
3254          * settings.
3255          */
3256
3257         if (((adapter->hw.mac.type == e1000_ich9lan) ||
3258             (adapter->hw.mac.type == e1000_pch2lan) ||
3259             (adapter->hw.mac.type == e1000_ich10lan)) &&
3260             (if_getmtu(ifp) > ETHERMTU)) {
3261                 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
3262                 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
3263         } else if (adapter->hw.mac.type == e1000_82574) {
3264                 for (int i = 0; i < adapter->rx_num_queues; i++) {
3265                         u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3266                         rxdctl |= 0x20; /* PTHRESH */
3267                         rxdctl |= 4 << 8; /* HTHRESH */
3268                         rxdctl |= 4 << 16;/* WTHRESH */
3269                         rxdctl |= 1 << 24; /* Switch to granularity */
3270                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3271                 }
3272         } else if (adapter->hw.mac.type >= igb_mac_min) {
3273                 u32 psize, srrctl = 0;
3274
3275                 if (if_getmtu(ifp) > ETHERMTU) {
3276                         /* Set maximum packet len */
3277                         if (adapter->rx_mbuf_sz <= 4096) {
3278                                 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3279                                 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3280                         } else if (adapter->rx_mbuf_sz > 4096) {
3281                                 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3282                                 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3283                         }
3284                         psize = scctx->isc_max_frame_size;
3285                         /* are we on a vlan? */
3286                         if (ifp->if_vlantrunk != NULL)
3287                                 psize += VLAN_TAG_SIZE;
3288                         E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
3289                 } else {
3290                         srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3291                         rctl |= E1000_RCTL_SZ_2048;
3292                 }
3293
3294                 /*
3295                  * If TX flow control is disabled and there's >1 queue defined,
3296                  * enable DROP.
3297                  *
3298                  * This drops frames rather than hanging the RX MAC for all queues.
3299                  */
3300                 if ((adapter->rx_num_queues > 1) &&
3301                     (adapter->fc == e1000_fc_none ||
3302                      adapter->fc == e1000_fc_rx_pause)) {
3303                         srrctl |= E1000_SRRCTL_DROP_EN;
3304                 }
3305                         /* Setup the Base and Length of the Rx Descriptor Rings */
3306                 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3307                         struct rx_ring *rxr = &que->rxr;
3308                         u64 bus_addr = rxr->rx_paddr;
3309                         u32 rxdctl;
3310
3311 #ifdef notyet
3312                         /* Configure for header split? -- ignore for now */
3313                         rxr->hdr_split = igb_header_split;
3314 #else
3315                         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3316 #endif
3317
3318                         E1000_WRITE_REG(hw, E1000_RDLEN(i),
3319                                         scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3320                         E1000_WRITE_REG(hw, E1000_RDBAH(i),
3321                                         (uint32_t)(bus_addr >> 32));
3322                         E1000_WRITE_REG(hw, E1000_RDBAL(i),
3323                                         (uint32_t)bus_addr);
3324                         E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3325                         /* Enable this Queue */
3326                         rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3327                         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3328                         rxdctl &= 0xFFF00000;
3329                         rxdctl |= IGB_RX_PTHRESH;
3330                         rxdctl |= IGB_RX_HTHRESH << 8;
3331                         rxdctl |= IGB_RX_WTHRESH << 16;
3332                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3333                 }
3334         } else if (adapter->hw.mac.type >= e1000_pch2lan) {
3335                 if (if_getmtu(ifp) > ETHERMTU)
3336                         e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
3337                 else
3338                         e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
3339         }
3340
3341         /* Make sure VLAN Filters are off */
3342         rctl &= ~E1000_RCTL_VFE;
3343
3344         if (adapter->hw.mac.type < igb_mac_min) {
3345                 if (adapter->rx_mbuf_sz == MCLBYTES)
3346                         rctl |= E1000_RCTL_SZ_2048;
3347                 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE)
3348                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3349                 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE)
3350                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3351
3352                 /* ensure we clear use DTYPE of 00 here */
3353                 rctl &= ~0x00000C00;
3354         }
3355
3356         /* Write out the settings */
3357         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3358
3359         return;
3360 }
3361
3362 static void
3363 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3364 {
3365         struct adapter *adapter = iflib_get_softc(ctx);
3366         u32 index, bit;
3367
3368         index = (vtag >> 5) & 0x7F;
3369         bit = vtag & 0x1F;
3370         adapter->shadow_vfta[index] |= (1 << bit);
3371         ++adapter->num_vlans;
3372 }
3373
3374 static void
3375 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3376 {
3377         struct adapter *adapter = iflib_get_softc(ctx);
3378         u32 index, bit;
3379
3380         index = (vtag >> 5) & 0x7F;
3381         bit = vtag & 0x1F;
3382         adapter->shadow_vfta[index] &= ~(1 << bit);
3383         --adapter->num_vlans;
3384 }
3385
3386 static void
3387 em_setup_vlan_hw_support(struct adapter *adapter)
3388 {
3389         struct e1000_hw *hw = &adapter->hw;
3390         u32 reg;
3391
3392         /*
3393          * We get here thru init_locked, meaning
3394          * a soft reset, this has already cleared
3395          * the VFTA and other state, so if there
3396          * have been no vlan's registered do nothing.
3397          */
3398         if (adapter->num_vlans == 0)
3399                 return;
3400
3401         /*
3402          * A soft reset zero's out the VFTA, so
3403          * we need to repopulate it now.
3404          */
3405         for (int i = 0; i < EM_VFTA_SIZE; i++)
3406                 if (adapter->shadow_vfta[i] != 0)
3407                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
3408                             i, adapter->shadow_vfta[i]);
3409
3410         reg = E1000_READ_REG(hw, E1000_CTRL);
3411         reg |= E1000_CTRL_VME;
3412         E1000_WRITE_REG(hw, E1000_CTRL, reg);
3413
3414         /* Enable the Filter Table */
3415         reg = E1000_READ_REG(hw, E1000_RCTL);
3416         reg &= ~E1000_RCTL_CFIEN;
3417         reg |= E1000_RCTL_VFE;
3418         E1000_WRITE_REG(hw, E1000_RCTL, reg);
3419 }
3420
3421 static void
3422 em_if_intr_enable(if_ctx_t ctx)
3423 {
3424         struct adapter *adapter = iflib_get_softc(ctx);
3425         struct e1000_hw *hw = &adapter->hw;
3426         u32 ims_mask = IMS_ENABLE_MASK;
3427
3428         if (hw->mac.type == e1000_82574) {
3429                 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK);
3430                 ims_mask |= adapter->ims;
3431         }
3432         E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3433 }
3434
3435 static void
3436 em_if_intr_disable(if_ctx_t ctx)
3437 {
3438         struct adapter *adapter = iflib_get_softc(ctx);
3439         struct e1000_hw *hw = &adapter->hw;
3440
3441         if (hw->mac.type == e1000_82574)
3442                 E1000_WRITE_REG(hw, EM_EIAC, 0);
3443         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3444 }
3445
3446 static void
3447 igb_if_intr_enable(if_ctx_t ctx)
3448 {
3449         struct adapter *adapter = iflib_get_softc(ctx);
3450         struct e1000_hw *hw = &adapter->hw;
3451         u32 mask;
3452
3453         if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) {
3454                 mask = (adapter->que_mask | adapter->link_mask);
3455                 E1000_WRITE_REG(hw, E1000_EIAC, mask);
3456                 E1000_WRITE_REG(hw, E1000_EIAM, mask);
3457                 E1000_WRITE_REG(hw, E1000_EIMS, mask);
3458                 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
3459         } else
3460                 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
3461         E1000_WRITE_FLUSH(hw);
3462 }
3463
3464 static void
3465 igb_if_intr_disable(if_ctx_t ctx)
3466 {
3467         struct adapter *adapter = iflib_get_softc(ctx);
3468         struct e1000_hw *hw = &adapter->hw;
3469
3470         if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) {
3471                 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff);
3472                 E1000_WRITE_REG(hw, E1000_EIAC, 0);
3473         }
3474         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3475         E1000_WRITE_FLUSH(hw);
3476 }
3477
3478 /*
3479  * Bit of a misnomer, what this really means is
3480  * to enable OS management of the system... aka
3481  * to disable special hardware management features
3482  */
3483 static void
3484 em_init_manageability(struct adapter *adapter)
3485 {
3486         /* A shared code workaround */
3487 #define E1000_82542_MANC2H E1000_MANC2H
3488         if (adapter->has_manage) {
3489                 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3490                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3491
3492                 /* disable hardware interception of ARP */
3493                 manc &= ~(E1000_MANC_ARP_EN);
3494
3495                 /* enable receiving management packets to the host */
3496                 manc |= E1000_MANC_EN_MNG2HOST;
3497 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3498 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3499                 manc2h |= E1000_MNG2HOST_PORT_623;
3500                 manc2h |= E1000_MNG2HOST_PORT_664;
3501                 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3502                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3503         }
3504 }
3505
3506 /*
3507  * Give control back to hardware management
3508  * controller if there is one.
3509  */
3510 static void
3511 em_release_manageability(struct adapter *adapter)
3512 {
3513         if (adapter->has_manage) {
3514                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3515
3516                 /* re-enable hardware interception of ARP */
3517                 manc |= E1000_MANC_ARP_EN;
3518                 manc &= ~E1000_MANC_EN_MNG2HOST;
3519
3520                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3521         }
3522 }
3523
3524 /*
3525  * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3526  * For ASF and Pass Through versions of f/w this means
3527  * that the driver is loaded. For AMT version type f/w
3528  * this means that the network i/f is open.
3529  */
3530 static void
3531 em_get_hw_control(struct adapter *adapter)
3532 {
3533         u32 ctrl_ext, swsm;
3534
3535         if (adapter->vf_ifp)
3536                 return;
3537
3538         if (adapter->hw.mac.type == e1000_82573) {
3539                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3540                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3541                     swsm | E1000_SWSM_DRV_LOAD);
3542                 return;
3543         }
3544         /* else */
3545         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3546         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3547             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3548 }
3549
3550 /*
3551  * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3552  * For ASF and Pass Through versions of f/w this means that
3553  * the driver is no longer loaded. For AMT versions of the
3554  * f/w this means that the network i/f is closed.
3555  */
3556 static void
3557 em_release_hw_control(struct adapter *adapter)
3558 {
3559         u32 ctrl_ext, swsm;
3560
3561         if (!adapter->has_manage)
3562                 return;
3563
3564         if (adapter->hw.mac.type == e1000_82573) {
3565                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3566                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3567                     swsm & ~E1000_SWSM_DRV_LOAD);
3568                 return;
3569         }
3570         /* else */
3571         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3572         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3573             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3574         return;
3575 }
3576
3577 static int
3578 em_is_valid_ether_addr(u8 *addr)
3579 {
3580         char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3581
3582         if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3583                 return (FALSE);
3584         }
3585
3586         return (TRUE);
3587 }
3588
3589 /*
3590 ** Parse the interface capabilities with regard
3591 ** to both system management and wake-on-lan for
3592 ** later use.
3593 */
3594 static void
3595 em_get_wakeup(if_ctx_t ctx)
3596 {
3597         struct adapter *adapter = iflib_get_softc(ctx);
3598         device_t dev = iflib_get_dev(ctx);
3599         u16 eeprom_data = 0, device_id, apme_mask;
3600
3601         adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
3602         apme_mask = EM_EEPROM_APME;
3603
3604         switch (adapter->hw.mac.type) {
3605         case e1000_82542:
3606         case e1000_82543:
3607                 break;
3608         case e1000_82544:
3609                 e1000_read_nvm(&adapter->hw,
3610                     NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3611                 apme_mask = EM_82544_APME;
3612                 break;
3613         case e1000_82546:
3614         case e1000_82546_rev_3:
3615                 if (adapter->hw.bus.func == 1) {
3616                         e1000_read_nvm(&adapter->hw,
3617                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3618                         break;
3619                 } else
3620                         e1000_read_nvm(&adapter->hw,
3621                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3622                 break;
3623         case e1000_82573:
3624         case e1000_82583:
3625                 adapter->has_amt = TRUE;
3626                 /* FALLTHROUGH */
3627         case e1000_82571:
3628         case e1000_82572:
3629         case e1000_80003es2lan:
3630                 if (adapter->hw.bus.func == 1) {
3631                         e1000_read_nvm(&adapter->hw,
3632                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3633                         break;
3634                 } else
3635                         e1000_read_nvm(&adapter->hw,
3636                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3637                 break;
3638         case e1000_ich8lan:
3639         case e1000_ich9lan:
3640         case e1000_ich10lan:
3641         case e1000_pchlan:
3642         case e1000_pch2lan:
3643         case e1000_pch_lpt:
3644         case e1000_pch_spt:
3645         case e1000_82575:       /* listing all igb devices */
3646         case e1000_82576:
3647         case e1000_82580:
3648         case e1000_i350:
3649         case e1000_i354:
3650         case e1000_i210:
3651         case e1000_i211:
3652         case e1000_vfadapt:
3653         case e1000_vfadapt_i350:
3654                 apme_mask = E1000_WUC_APME;
3655                 adapter->has_amt = TRUE;
3656                 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
3657                 break;
3658         default:
3659                 e1000_read_nvm(&adapter->hw,
3660                     NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3661                 break;
3662         }
3663         if (eeprom_data & apme_mask)
3664                 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
3665         /*
3666          * We have the eeprom settings, now apply the special cases
3667          * where the eeprom may be wrong or the board won't support
3668          * wake on lan on a particular port
3669          */
3670         device_id = pci_get_device(dev);
3671         switch (device_id) {
3672         case E1000_DEV_ID_82546GB_PCIE:
3673                 adapter->wol = 0;
3674                 break;
3675         case E1000_DEV_ID_82546EB_FIBER:
3676         case E1000_DEV_ID_82546GB_FIBER:
3677                 /* Wake events only supported on port A for dual fiber
3678                  * regardless of eeprom setting */
3679                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3680                     E1000_STATUS_FUNC_1)
3681                         adapter->wol = 0;
3682                 break;
3683         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
3684                 /* if quad port adapter, disable WoL on all but port A */
3685                 if (global_quad_port_a != 0)
3686                         adapter->wol = 0;
3687                 /* Reset for multiple quad port adapters */
3688                 if (++global_quad_port_a == 4)
3689                         global_quad_port_a = 0;
3690                 break;
3691         case E1000_DEV_ID_82571EB_FIBER:
3692                 /* Wake events only supported on port A for dual fiber
3693                  * regardless of eeprom setting */
3694                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3695                     E1000_STATUS_FUNC_1)
3696                         adapter->wol = 0;
3697                 break;
3698         case E1000_DEV_ID_82571EB_QUAD_COPPER:
3699         case E1000_DEV_ID_82571EB_QUAD_FIBER:
3700         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
3701                 /* if quad port adapter, disable WoL on all but port A */
3702                 if (global_quad_port_a != 0)
3703                         adapter->wol = 0;
3704                 /* Reset for multiple quad port adapters */
3705                 if (++global_quad_port_a == 4)
3706                         global_quad_port_a = 0;
3707                 break;
3708         }
3709         return;
3710 }
3711
3712
3713 /*
3714  * Enable PCI Wake On Lan capability
3715  */
3716 static void
3717 em_enable_wakeup(if_ctx_t ctx)
3718 {
3719         struct adapter *adapter = iflib_get_softc(ctx);
3720         device_t dev = iflib_get_dev(ctx);
3721         if_t ifp = iflib_get_ifp(ctx);
3722         int error = 0;
3723         u32 pmc, ctrl, ctrl_ext, rctl;
3724         u16 status;
3725
3726         if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
3727                 return;
3728
3729         /*
3730          * Determine type of Wakeup: note that wol
3731          * is set with all bits on by default.
3732          */
3733         if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
3734                 adapter->wol &= ~E1000_WUFC_MAG;
3735
3736         if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
3737                 adapter->wol &= ~E1000_WUFC_EX;
3738
3739         if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
3740                 adapter->wol &= ~E1000_WUFC_MC;
3741         else {
3742                 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3743                 rctl |= E1000_RCTL_MPE;
3744                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3745         }
3746
3747         if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC)))
3748                 goto pme;
3749
3750         /* Advertise the wakeup capability */
3751         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
3752         ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
3753         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
3754
3755         /* Keep the laser running on Fiber adapters */
3756         if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3757             adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
3758                 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3759                 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
3760                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext);
3761         }
3762
3763         if ((adapter->hw.mac.type == e1000_ich8lan) ||
3764             (adapter->hw.mac.type == e1000_pchlan) ||
3765             (adapter->hw.mac.type == e1000_ich9lan) ||
3766             (adapter->hw.mac.type == e1000_ich10lan))
3767                 e1000_suspend_workarounds_ich8lan(&adapter->hw);
3768
3769         if ( adapter->hw.mac.type >= e1000_pchlan) {
3770                 error = em_enable_phy_wakeup(adapter);
3771                 if (error)
3772                         goto pme;
3773         } else {
3774                 /* Enable wakeup by the MAC */
3775                 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
3776                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
3777         }
3778
3779         if (adapter->hw.phy.type == e1000_phy_igp_3)
3780                 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
3781
3782 pme:
3783         status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
3784         status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3785         if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
3786                 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3787         pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
3788
3789         return;
3790 }
3791
3792 /*
3793  * WOL in the newer chipset interfaces (pchlan)
3794  * require thing to be copied into the phy
3795  */
3796 static int
3797 em_enable_phy_wakeup(struct adapter *adapter)
3798 {
3799         struct e1000_hw *hw = &adapter->hw;
3800         u32 mreg, ret = 0;
3801         u16 preg;
3802
3803         /* copy MAC RARs to PHY RARs */
3804         e1000_copy_rx_addrs_to_phy_ich8lan(hw);
3805
3806         /* copy MAC MTA to PHY MTA */
3807         for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
3808                 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
3809                 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
3810                 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
3811                     (u16)((mreg >> 16) & 0xFFFF));
3812         }
3813
3814         /* configure PHY Rx Control register */
3815         e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg);
3816         mreg = E1000_READ_REG(hw, E1000_RCTL);
3817         if (mreg & E1000_RCTL_UPE)
3818                 preg |= BM_RCTL_UPE;
3819         if (mreg & E1000_RCTL_MPE)
3820                 preg |= BM_RCTL_MPE;
3821         preg &= ~(BM_RCTL_MO_MASK);
3822         if (mreg & E1000_RCTL_MO_3)
3823                 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
3824                                 << BM_RCTL_MO_SHIFT);
3825         if (mreg & E1000_RCTL_BAM)
3826                 preg |= BM_RCTL_BAM;
3827         if (mreg & E1000_RCTL_PMCF)
3828                 preg |= BM_RCTL_PMCF;
3829         mreg = E1000_READ_REG(hw, E1000_CTRL);
3830         if (mreg & E1000_CTRL_RFCE)
3831                 preg |= BM_RCTL_RFCE;
3832         e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg);
3833
3834         /* enable PHY wakeup in MAC register */
3835         E1000_WRITE_REG(hw, E1000_WUC,
3836             E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
3837         E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol);
3838
3839         /* configure and enable PHY wakeup in PHY registers */
3840         e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol);
3841         e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
3842
3843         /* activate PHY wakeup */
3844         ret = hw->phy.ops.acquire(hw);
3845         if (ret) {
3846                 printf("Could not acquire PHY\n");
3847                 return ret;
3848         }
3849         e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3850                                  (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3851         ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
3852         if (ret) {
3853                 printf("Could not read PHY page 769\n");
3854                 goto out;
3855         }
3856         preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
3857         ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
3858         if (ret)
3859                 printf("Could not set PHY Host Wakeup bit\n");
3860 out:
3861         hw->phy.ops.release(hw);
3862
3863         return ret;
3864 }
3865
3866 static void
3867 em_if_led_func(if_ctx_t ctx, int onoff)
3868 {
3869         struct adapter *adapter = iflib_get_softc(ctx);
3870
3871         if (onoff) {
3872                 e1000_setup_led(&adapter->hw);
3873                 e1000_led_on(&adapter->hw);
3874         } else {
3875                 e1000_led_off(&adapter->hw);
3876                 e1000_cleanup_led(&adapter->hw);
3877         }
3878 }
3879
3880 /*
3881  * Disable the L0S and L1 LINK states
3882  */
3883 static void
3884 em_disable_aspm(struct adapter *adapter)
3885 {
3886         int base, reg;
3887         u16 link_cap,link_ctrl;
3888         device_t dev = adapter->dev;
3889
3890         switch (adapter->hw.mac.type) {
3891         case e1000_82573:
3892         case e1000_82574:
3893         case e1000_82583:
3894                 break;
3895         default:
3896                 return;
3897         }
3898         if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
3899                 return;
3900         reg = base + PCIER_LINK_CAP;
3901         link_cap = pci_read_config(dev, reg, 2);
3902         if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
3903                 return;
3904         reg = base + PCIER_LINK_CTL;
3905         link_ctrl = pci_read_config(dev, reg, 2);
3906         link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
3907         pci_write_config(dev, reg, link_ctrl, 2);
3908         return;
3909 }
3910
3911 /**********************************************************************
3912  *
3913  *  Update the board statistics counters.
3914  *
3915  **********************************************************************/
3916 static void
3917 em_update_stats_counters(struct adapter *adapter)
3918 {
3919         u64 prev_xoffrxc = adapter->stats.xoffrxc;
3920
3921         if(adapter->hw.phy.media_type == e1000_media_type_copper ||
3922            (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3923                 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
3924                 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
3925         }
3926         adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
3927         adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
3928         adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
3929         adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
3930
3931         adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
3932         adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
3933         adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
3934         adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
3935         adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
3936         adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
3937         adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
3938         adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
3939         /*
3940          ** For watchdog management we need to know if we have been
3941          ** paused during the last interval, so capture that here.
3942         */
3943         if (adapter->stats.xoffrxc != prev_xoffrxc)
3944                 adapter->shared->isc_pause_frames = 1;
3945         adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
3946         adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
3947         adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
3948         adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
3949         adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
3950         adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
3951         adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
3952         adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
3953         adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
3954         adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
3955         adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
3956         adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
3957
3958         /* For the 64-bit byte counters the low dword must be read first. */
3959         /* Both registers clear on the read of the high dword */
3960
3961         adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) +
3962             ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32);
3963         adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) +
3964             ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32);
3965
3966         adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
3967         adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
3968         adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
3969         adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
3970         adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
3971
3972         adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
3973         adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
3974
3975         adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
3976         adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
3977         adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
3978         adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
3979         adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
3980         adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
3981         adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
3982         adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
3983         adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
3984         adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
3985
3986         /* Interrupt Counts */
3987
3988         adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC);
3989         adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC);
3990         adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC);
3991         adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC);
3992         adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC);
3993         adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC);
3994         adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC);
3995         adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC);
3996         adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC);
3997
3998         if (adapter->hw.mac.type >= e1000_82543) {
3999                 adapter->stats.algnerrc +=
4000                 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
4001                 adapter->stats.rxerrc +=
4002                 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
4003                 adapter->stats.tncrs +=
4004                 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
4005                 adapter->stats.cexterr +=
4006                 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
4007                 adapter->stats.tsctc +=
4008                 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
4009                 adapter->stats.tsctfc +=
4010                 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
4011         }
4012 }
4013
4014 static uint64_t
4015 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
4016 {
4017         struct adapter *adapter = iflib_get_softc(ctx);
4018         struct ifnet *ifp = iflib_get_ifp(ctx);
4019
4020         switch (cnt) {
4021         case IFCOUNTER_COLLISIONS:
4022                 return (adapter->stats.colc);
4023         case IFCOUNTER_IERRORS:
4024                 return (adapter->dropped_pkts + adapter->stats.rxerrc +
4025                     adapter->stats.crcerrs + adapter->stats.algnerrc +
4026                     adapter->stats.ruc + adapter->stats.roc +
4027                     adapter->stats.mpc + adapter->stats.cexterr);
4028         case IFCOUNTER_OERRORS:
4029                 return (adapter->stats.ecol + adapter->stats.latecol +
4030                     adapter->watchdog_events);
4031         default:
4032                 return (if_get_counter_default(ifp, cnt));
4033         }
4034 }
4035
4036 /* Export a single 32-bit register via a read-only sysctl. */
4037 static int
4038 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
4039 {
4040         struct adapter *adapter;
4041         u_int val;
4042
4043         adapter = oidp->oid_arg1;
4044         val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2);
4045         return (sysctl_handle_int(oidp, &val, 0, req));
4046 }
4047
4048 /*
4049  * Add sysctl variables, one per statistic, to the system.
4050  */
4051 static void
4052 em_add_hw_stats(struct adapter *adapter)
4053 {
4054         device_t dev = iflib_get_dev(adapter->ctx);
4055         struct em_tx_queue *tx_que = adapter->tx_queues;
4056         struct em_rx_queue *rx_que = adapter->rx_queues;
4057
4058         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
4059         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
4060         struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
4061         struct e1000_hw_stats *stats = &adapter->stats;
4062
4063         struct sysctl_oid *stat_node, *queue_node, *int_node;
4064         struct sysctl_oid_list *stat_list, *queue_list, *int_list;
4065
4066 #define QUEUE_NAME_LEN 32
4067         char namebuf[QUEUE_NAME_LEN];
4068
4069         /* Driver Statistics */
4070         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
4071                         CTLFLAG_RD, &adapter->dropped_pkts,
4072                         "Driver dropped packets");
4073         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
4074                         CTLFLAG_RD, &adapter->link_irq,
4075                         "Link MSI-X IRQ Handled");
4076         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
4077                         CTLFLAG_RD, &adapter->rx_overruns,
4078                         "RX overruns");
4079         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
4080                         CTLFLAG_RD, &adapter->watchdog_events,
4081                         "Watchdog timeouts");
4082         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
4083                         CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL,
4084                         em_sysctl_reg_handler, "IU",
4085                         "Device Control Register");
4086         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
4087                         CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL,
4088                         em_sysctl_reg_handler, "IU",
4089                         "Receiver Control Register");
4090         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
4091                         CTLFLAG_RD, &adapter->hw.fc.high_water, 0,
4092                         "Flow Control High Watermark");
4093         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
4094                         CTLFLAG_RD, &adapter->hw.fc.low_water, 0,
4095                         "Flow Control Low Watermark");
4096
4097         for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
4098                 struct tx_ring *txr = &tx_que->txr;
4099                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
4100                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4101                                             CTLFLAG_RD, NULL, "TX Queue Name");
4102                 queue_list = SYSCTL_CHILDREN(queue_node);
4103
4104                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
4105                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4106                                 E1000_TDH(txr->me),
4107                                 em_sysctl_reg_handler, "IU",
4108                                 "Transmit Descriptor Head");
4109                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
4110                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4111                                 E1000_TDT(txr->me),
4112                                 em_sysctl_reg_handler, "IU",
4113                                 "Transmit Descriptor Tail");
4114                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
4115                                 CTLFLAG_RD, &txr->tx_irq,
4116                                 "Queue MSI-X Transmit Interrupts");
4117         }
4118
4119         for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) {
4120                 struct rx_ring *rxr = &rx_que->rxr;
4121                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
4122                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4123                                             CTLFLAG_RD, NULL, "RX Queue Name");
4124                 queue_list = SYSCTL_CHILDREN(queue_node);
4125
4126                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
4127                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4128                                 E1000_RDH(rxr->me),
4129                                 em_sysctl_reg_handler, "IU",
4130                                 "Receive Descriptor Head");
4131                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
4132                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4133                                 E1000_RDT(rxr->me),
4134                                 em_sysctl_reg_handler, "IU",
4135                                 "Receive Descriptor Tail");
4136                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
4137                                 CTLFLAG_RD, &rxr->rx_irq,
4138                                 "Queue MSI-X Receive Interrupts");
4139         }
4140
4141         /* MAC stats get their own sub node */
4142
4143         stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
4144                                     CTLFLAG_RD, NULL, "Statistics");
4145         stat_list = SYSCTL_CHILDREN(stat_node);
4146
4147         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
4148                         CTLFLAG_RD, &stats->ecol,
4149                         "Excessive collisions");
4150         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
4151                         CTLFLAG_RD, &stats->scc,
4152                         "Single collisions");
4153         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
4154                         CTLFLAG_RD, &stats->mcc,
4155                         "Multiple collisions");
4156         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
4157                         CTLFLAG_RD, &stats->latecol,
4158                         "Late collisions");
4159         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
4160                         CTLFLAG_RD, &stats->colc,
4161                         "Collision Count");
4162         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
4163                         CTLFLAG_RD, &adapter->stats.symerrs,
4164                         "Symbol Errors");
4165         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
4166                         CTLFLAG_RD, &adapter->stats.sec,
4167                         "Sequence Errors");
4168         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
4169                         CTLFLAG_RD, &adapter->stats.dc,
4170                         "Defer Count");
4171         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
4172                         CTLFLAG_RD, &adapter->stats.mpc,
4173                         "Missed Packets");
4174         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
4175                         CTLFLAG_RD, &adapter->stats.rnbc,
4176                         "Receive No Buffers");
4177         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
4178                         CTLFLAG_RD, &adapter->stats.ruc,
4179                         "Receive Undersize");
4180         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
4181                         CTLFLAG_RD, &adapter->stats.rfc,
4182                         "Fragmented Packets Received ");
4183         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
4184                         CTLFLAG_RD, &adapter->stats.roc,
4185                         "Oversized Packets Received");
4186         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
4187                         CTLFLAG_RD, &adapter->stats.rjc,
4188                         "Recevied Jabber");
4189         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
4190                         CTLFLAG_RD, &adapter->stats.rxerrc,
4191                         "Receive Errors");
4192         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
4193                         CTLFLAG_RD, &adapter->stats.crcerrs,
4194                         "CRC errors");
4195         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
4196                         CTLFLAG_RD, &adapter->stats.algnerrc,
4197                         "Alignment Errors");
4198         /* On 82575 these are collision counts */
4199         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
4200                         CTLFLAG_RD, &adapter->stats.cexterr,
4201                         "Collision/Carrier extension errors");
4202         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
4203                         CTLFLAG_RD, &adapter->stats.xonrxc,
4204                         "XON Received");
4205         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
4206                         CTLFLAG_RD, &adapter->stats.xontxc,
4207                         "XON Transmitted");
4208         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
4209                         CTLFLAG_RD, &adapter->stats.xoffrxc,
4210                         "XOFF Received");
4211         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
4212                         CTLFLAG_RD, &adapter->stats.xofftxc,
4213                         "XOFF Transmitted");
4214
4215         /* Packet Reception Stats */
4216         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
4217                         CTLFLAG_RD, &adapter->stats.tpr,
4218                         "Total Packets Received ");
4219         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
4220                         CTLFLAG_RD, &adapter->stats.gprc,
4221                         "Good Packets Received");
4222         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
4223                         CTLFLAG_RD, &adapter->stats.bprc,
4224                         "Broadcast Packets Received");
4225         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
4226                         CTLFLAG_RD, &adapter->stats.mprc,
4227                         "Multicast Packets Received");
4228         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
4229                         CTLFLAG_RD, &adapter->stats.prc64,
4230                         "64 byte frames received ");
4231         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
4232                         CTLFLAG_RD, &adapter->stats.prc127,
4233                         "65-127 byte frames received");
4234         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
4235                         CTLFLAG_RD, &adapter->stats.prc255,
4236                         "128-255 byte frames received");
4237         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
4238                         CTLFLAG_RD, &adapter->stats.prc511,
4239                         "256-511 byte frames received");
4240         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
4241                         CTLFLAG_RD, &adapter->stats.prc1023,
4242                         "512-1023 byte frames received");
4243         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
4244                         CTLFLAG_RD, &adapter->stats.prc1522,
4245                         "1023-1522 byte frames received");
4246         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
4247                         CTLFLAG_RD, &adapter->stats.gorc,
4248                         "Good Octets Received");
4249
4250         /* Packet Transmission Stats */
4251         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
4252                         CTLFLAG_RD, &adapter->stats.gotc,
4253                         "Good Octets Transmitted");
4254         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
4255                         CTLFLAG_RD, &adapter->stats.tpt,
4256                         "Total Packets Transmitted");
4257         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
4258                         CTLFLAG_RD, &adapter->stats.gptc,
4259                         "Good Packets Transmitted");
4260         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
4261                         CTLFLAG_RD, &adapter->stats.bptc,
4262                         "Broadcast Packets Transmitted");
4263         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
4264                         CTLFLAG_RD, &adapter->stats.mptc,
4265                         "Multicast Packets Transmitted");
4266         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
4267                         CTLFLAG_RD, &adapter->stats.ptc64,
4268                         "64 byte frames transmitted ");
4269         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
4270                         CTLFLAG_RD, &adapter->stats.ptc127,
4271                         "65-127 byte frames transmitted");
4272         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
4273                         CTLFLAG_RD, &adapter->stats.ptc255,
4274                         "128-255 byte frames transmitted");
4275         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
4276                         CTLFLAG_RD, &adapter->stats.ptc511,
4277                         "256-511 byte frames transmitted");
4278         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
4279                         CTLFLAG_RD, &adapter->stats.ptc1023,
4280                         "512-1023 byte frames transmitted");
4281         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
4282                         CTLFLAG_RD, &adapter->stats.ptc1522,
4283                         "1024-1522 byte frames transmitted");
4284         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
4285                         CTLFLAG_RD, &adapter->stats.tsctc,
4286                         "TSO Contexts Transmitted");
4287         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
4288                         CTLFLAG_RD, &adapter->stats.tsctfc,
4289                         "TSO Contexts Failed");
4290
4291
4292         /* Interrupt Stats */
4293
4294         int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
4295                                     CTLFLAG_RD, NULL, "Interrupt Statistics");
4296         int_list = SYSCTL_CHILDREN(int_node);
4297
4298         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
4299                         CTLFLAG_RD, &adapter->stats.iac,
4300                         "Interrupt Assertion Count");
4301
4302         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
4303                         CTLFLAG_RD, &adapter->stats.icrxptc,
4304                         "Interrupt Cause Rx Pkt Timer Expire Count");
4305
4306         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
4307                         CTLFLAG_RD, &adapter->stats.icrxatc,
4308                         "Interrupt Cause Rx Abs Timer Expire Count");
4309
4310         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
4311                         CTLFLAG_RD, &adapter->stats.ictxptc,
4312                         "Interrupt Cause Tx Pkt Timer Expire Count");
4313
4314         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
4315                         CTLFLAG_RD, &adapter->stats.ictxatc,
4316                         "Interrupt Cause Tx Abs Timer Expire Count");
4317
4318         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
4319                         CTLFLAG_RD, &adapter->stats.ictxqec,
4320                         "Interrupt Cause Tx Queue Empty Count");
4321
4322         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
4323                         CTLFLAG_RD, &adapter->stats.ictxqmtc,
4324                         "Interrupt Cause Tx Queue Min Thresh Count");
4325
4326         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
4327                         CTLFLAG_RD, &adapter->stats.icrxdmtc,
4328                         "Interrupt Cause Rx Desc Min Thresh Count");
4329
4330         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
4331                         CTLFLAG_RD, &adapter->stats.icrxoc,
4332                         "Interrupt Cause Receiver Overrun Count");
4333 }
4334
4335 /**********************************************************************
4336  *
4337  *  This routine provides a way to dump out the adapter eeprom,
4338  *  often a useful debug/service tool. This only dumps the first
4339  *  32 words, stuff that matters is in that extent.
4340  *
4341  **********************************************************************/
4342 static int
4343 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4344 {
4345         struct adapter *adapter = (struct adapter *)arg1;
4346         int error;
4347         int result;
4348
4349         result = -1;
4350         error = sysctl_handle_int(oidp, &result, 0, req);
4351
4352         if (error || !req->newptr)
4353                 return (error);
4354
4355         /*
4356          * This value will cause a hex dump of the
4357          * first 32 16-bit words of the EEPROM to
4358          * the screen.
4359          */
4360         if (result == 1)
4361                 em_print_nvm_info(adapter);
4362
4363         return (error);
4364 }
4365
4366 static void
4367 em_print_nvm_info(struct adapter *adapter)
4368 {
4369         u16 eeprom_data;
4370         int i, j, row = 0;
4371
4372         /* Its a bit crude, but it gets the job done */
4373         printf("\nInterface EEPROM Dump:\n");
4374         printf("Offset\n0x0000  ");
4375         for (i = 0, j = 0; i < 32; i++, j++) {
4376                 if (j == 8) { /* Make the offset block */
4377                         j = 0; ++row;
4378                         printf("\n0x00%x0  ",row);
4379                 }
4380                 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
4381                 printf("%04x ", eeprom_data);
4382         }
4383         printf("\n");
4384 }
4385
4386 static int
4387 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4388 {
4389         struct em_int_delay_info *info;
4390         struct adapter *adapter;
4391         u32 regval;
4392         int error, usecs, ticks;
4393
4394         info = (struct em_int_delay_info *) arg1;
4395         usecs = info->value;
4396         error = sysctl_handle_int(oidp, &usecs, 0, req);
4397         if (error != 0 || req->newptr == NULL)
4398                 return (error);
4399         if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4400                 return (EINVAL);
4401         info->value = usecs;
4402         ticks = EM_USECS_TO_TICKS(usecs);
4403         if (info->offset == E1000_ITR)  /* units are 256ns here */
4404                 ticks *= 4;
4405
4406         adapter = info->adapter;
4407
4408         regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
4409         regval = (regval & ~0xffff) | (ticks & 0xffff);
4410         /* Handle a few special cases. */
4411         switch (info->offset) {
4412         case E1000_RDTR:
4413                 break;
4414         case E1000_TIDV:
4415                 if (ticks == 0) {
4416                         adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
4417                         /* Don't write 0 into the TIDV register. */
4418                         regval++;
4419                 } else
4420                         adapter->txd_cmd |= E1000_TXD_CMD_IDE;
4421                 break;
4422         }
4423         E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
4424         return (0);
4425 }
4426
4427 static void
4428 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
4429         const char *description, struct em_int_delay_info *info,
4430         int offset, int value)
4431 {
4432         info->adapter = adapter;
4433         info->offset = offset;
4434         info->value = value;
4435         SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev),
4436             SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4437             OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
4438             info, 0, em_sysctl_int_delay, "I", description);
4439 }
4440
4441 /*
4442  * Set flow control using sysctl:
4443  * Flow control values:
4444  *      0 - off
4445  *      1 - rx pause
4446  *      2 - tx pause
4447  *      3 - full
4448  */
4449 static int
4450 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4451 {
4452         int error;
4453         static int input = 3; /* default is full */
4454         struct adapter  *adapter = (struct adapter *) arg1;
4455
4456         error = sysctl_handle_int(oidp, &input, 0, req);
4457
4458         if ((error) || (req->newptr == NULL))
4459                 return (error);
4460
4461         if (input == adapter->fc) /* no change? */
4462                 return (error);
4463
4464         switch (input) {
4465         case e1000_fc_rx_pause:
4466         case e1000_fc_tx_pause:
4467         case e1000_fc_full:
4468         case e1000_fc_none:
4469                 adapter->hw.fc.requested_mode = input;
4470                 adapter->fc = input;
4471                 break;
4472         default:
4473                 /* Do nothing */
4474                 return (error);
4475         }
4476
4477         adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
4478         e1000_force_mac_fc(&adapter->hw);
4479         return (error);
4480 }
4481
4482 /*
4483  * Manage Energy Efficient Ethernet:
4484  * Control values:
4485  *     0/1 - enabled/disabled
4486  */
4487 static int
4488 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4489 {
4490         struct adapter *adapter = (struct adapter *) arg1;
4491         int error, value;
4492
4493         value = adapter->hw.dev_spec.ich8lan.eee_disable;
4494         error = sysctl_handle_int(oidp, &value, 0, req);
4495         if (error || req->newptr == NULL)
4496                 return (error);
4497         adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4498         em_if_init(adapter->ctx);
4499
4500         return (0);
4501 }
4502
4503 static int
4504 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4505 {
4506         struct adapter *adapter;
4507         int error;
4508         int result;
4509
4510         result = -1;
4511         error = sysctl_handle_int(oidp, &result, 0, req);
4512
4513         if (error || !req->newptr)
4514                 return (error);
4515
4516         if (result == 1) {
4517                 adapter = (struct adapter *) arg1;
4518                 em_print_debug_info(adapter);
4519         }
4520
4521         return (error);
4522 }
4523
4524 static int
4525 em_get_rs(SYSCTL_HANDLER_ARGS)
4526 {
4527         struct adapter *adapter = (struct adapter *) arg1;
4528         int error;
4529         int result;
4530
4531         result = 0;
4532         error = sysctl_handle_int(oidp, &result, 0, req);
4533
4534         if (error || !req->newptr || result != 1)
4535                 return (error);
4536         em_dump_rs(adapter);
4537
4538         return (error);
4539 }
4540
4541 static void
4542 em_if_debug(if_ctx_t ctx)
4543 {
4544         em_dump_rs(iflib_get_softc(ctx));
4545 }
4546
4547 /*
4548  * This routine is meant to be fluid, add whatever is
4549  * needed for debugging a problem.  -jfv
4550  */
4551 static void
4552 em_print_debug_info(struct adapter *adapter)
4553 {
4554         device_t dev = iflib_get_dev(adapter->ctx);
4555         struct ifnet *ifp = iflib_get_ifp(adapter->ctx);
4556         struct tx_ring *txr = &adapter->tx_queues->txr;
4557         struct rx_ring *rxr = &adapter->rx_queues->rxr;
4558
4559         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
4560                 printf("Interface is RUNNING ");
4561         else
4562                 printf("Interface is NOT RUNNING\n");
4563
4564         if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
4565                 printf("and INACTIVE\n");
4566         else
4567                 printf("and ACTIVE\n");
4568
4569         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
4570                 device_printf(dev, "TX Queue %d ------\n", i);
4571                 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
4572                         E1000_READ_REG(&adapter->hw, E1000_TDH(i)),
4573                         E1000_READ_REG(&adapter->hw, E1000_TDT(i)));
4574
4575         }
4576         for (int j=0; j < adapter->rx_num_queues; j++, rxr++) {
4577                 device_printf(dev, "RX Queue %d ------\n", j);
4578                 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
4579                         E1000_READ_REG(&adapter->hw, E1000_RDH(j)),
4580                         E1000_READ_REG(&adapter->hw, E1000_RDT(j)));
4581         }
4582 }
4583
4584 /*
4585  * 82574 only:
4586  * Write a new value to the EEPROM increasing the number of MSI-X
4587  * vectors from 3 to 5, for proper multiqueue support.
4588  */
4589 static void
4590 em_enable_vectors_82574(if_ctx_t ctx)
4591 {
4592         struct adapter *adapter = iflib_get_softc(ctx);
4593         struct e1000_hw *hw = &adapter->hw;
4594         device_t dev = iflib_get_dev(ctx);
4595         u16 edata;
4596
4597         e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4598         if (bootverbose)
4599                 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata);
4600         if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
4601                 device_printf(dev, "Writing to eeprom: increasing "
4602                     "reported MSI-X vectors from 3 to 5...\n");
4603                 edata &= ~(EM_NVM_MSIX_N_MASK);
4604                 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
4605                 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4606                 e1000_update_nvm_checksum(hw);
4607                 device_printf(dev, "Writing to eeprom: done\n");
4608         }
4609 }