2 * Copyright (c) 2016 Matt Macy <mmacy@nextbsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <machine/_inttypes.h>
32 #define em_mac_min e1000_82547
33 #define igb_mac_min e1000_82575
35 /*********************************************************************
37 *********************************************************************/
38 char em_driver_version[] = "7.6.1-k";
40 /*********************************************************************
43 * Used by probe to select devices to load on
44 * Last field stores an index into e1000_strings
45 * Last entry must be all 0s
47 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
48 *********************************************************************/
50 static pci_vendor_info_t em_vendor_info_array[] =
52 /* Intel(R) PRO/1000 Network Connection - Legacy em*/
53 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"),
54 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"),
55 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"),
56 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"),
57 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"),
59 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"),
60 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"),
61 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"),
62 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
63 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"),
64 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"),
65 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
67 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"),
69 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"),
70 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
72 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
73 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
74 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
75 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"),
77 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"),
78 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"),
79 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"),
80 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"),
81 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"),
83 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
84 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
85 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
86 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"),
87 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"),
88 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"),
89 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"),
90 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
91 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"),
93 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"),
94 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
95 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"),
97 /* Intel(R) PRO/1000 Network Connection - em */
98 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
99 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
100 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"),
101 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"),
102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"),
103 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
104 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"),
105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"),
106 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
107 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
108 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
109 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"),
110 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"),
111 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"),
112 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"),
113 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"),
114 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"),
115 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"),
116 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"),
117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"),
118 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
119 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
120 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"),
121 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"),
122 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
123 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"),
124 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"),
125 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"),
126 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
127 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
128 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"),
129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"),
130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"),
131 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"),
132 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
133 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"),
134 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"),
135 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"),
136 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"),
137 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"),
138 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"),
139 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"),
140 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"),
141 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"),
142 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"),
143 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"),
144 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"),
145 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"),
146 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"),
147 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"),
148 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"),
149 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"),
150 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"),
151 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"),
152 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"),
153 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"),
154 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"),
155 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"),
156 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"),
157 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"),
158 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"),
159 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"),
160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"),
161 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"),
162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"),
163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"),
164 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"),
165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"),
166 /* required last entry */
170 static pci_vendor_info_t igb_vendor_info_array[] =
172 /* Intel(R) PRO/1000 Network Connection - em */
173 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
174 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
175 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
176 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"),
177 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
178 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
179 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
180 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
181 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"),
182 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
183 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"),
184 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
185 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
186 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
187 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
188 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
189 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"),
190 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
191 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
192 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
193 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"),
194 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"),
195 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
196 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
197 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
198 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
199 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
200 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
201 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"),
202 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"),
203 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
204 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
205 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
206 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
207 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
208 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
209 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
210 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
211 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
212 /* required last entry */
216 /*********************************************************************
217 * Function prototypes
218 *********************************************************************/
219 static void *em_register(device_t dev);
220 static void *igb_register(device_t dev);
221 static int em_if_attach_pre(if_ctx_t ctx);
222 static int em_if_attach_post(if_ctx_t ctx);
223 static int em_if_detach(if_ctx_t ctx);
224 static int em_if_shutdown(if_ctx_t ctx);
225 static int em_if_suspend(if_ctx_t ctx);
226 static int em_if_resume(if_ctx_t ctx);
228 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets);
229 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets);
230 static void em_if_queues_free(if_ctx_t ctx);
232 static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
233 static void em_if_init(if_ctx_t ctx);
234 static void em_if_stop(if_ctx_t ctx);
235 static void em_if_media_status(if_ctx_t, struct ifmediareq *);
236 static int em_if_media_change(if_ctx_t ctx);
237 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu);
238 static void em_if_timer(if_ctx_t ctx, uint16_t qid);
239 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag);
240 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag);
242 static void em_identify_hardware(if_ctx_t ctx);
243 static int em_allocate_pci_resources(if_ctx_t ctx);
244 static void em_free_pci_resources(if_ctx_t ctx);
245 static void em_reset(if_ctx_t ctx);
246 static int em_setup_interface(if_ctx_t ctx);
247 static int em_setup_msix(if_ctx_t ctx);
249 static void em_initialize_transmit_unit(if_ctx_t ctx);
250 static void em_initialize_receive_unit(if_ctx_t ctx);
252 static void em_if_enable_intr(if_ctx_t ctx);
253 static void em_if_disable_intr(if_ctx_t ctx);
254 static int em_if_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
255 static void em_if_multi_set(if_ctx_t ctx);
256 static void em_if_update_admin_status(if_ctx_t ctx);
257 static void em_update_stats_counters(struct adapter *);
258 static void em_add_hw_stats(struct adapter *adapter);
259 static int em_if_set_promisc(if_ctx_t ctx, int flags);
260 static void em_setup_vlan_hw_support(struct adapter *);
261 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
262 static void em_print_nvm_info(struct adapter *);
263 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
264 static void em_print_debug_info(struct adapter *);
265 static int em_is_valid_ether_addr(u8 *);
266 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
267 static void em_add_int_delay_sysctl(struct adapter *, const char *,
268 const char *, struct em_int_delay_info *, int, int);
269 /* Management and WOL Support */
270 static void em_init_manageability(struct adapter *);
271 static void em_release_manageability(struct adapter *);
272 static void em_get_hw_control(struct adapter *);
273 static void em_release_hw_control(struct adapter *);
274 static void em_get_wakeup(if_ctx_t ctx);
275 static void em_enable_wakeup(if_ctx_t ctx);
276 static int em_enable_phy_wakeup(struct adapter *);
277 static void em_disable_aspm(struct adapter *);
279 int em_intr(void *arg);
280 static void em_disable_promisc(if_ctx_t ctx);
283 static int em_if_msix_intr_assign(if_ctx_t, int);
284 static int em_msix_link(void *);
285 static void em_handle_link(void *context);
287 static void em_enable_vectors_82574(if_ctx_t);
289 static void em_set_sysctl_value(struct adapter *, const char *,
290 const char *, int *, int);
291 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS);
292 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS);
293 static void em_if_led_func(if_ctx_t ctx, int onoff);
295 static void em_init_tx_ring(struct em_tx_queue *que);
296 static int em_get_regs(SYSCTL_HANDLER_ARGS);
298 static void lem_smartspeed(struct adapter *adapter);
299 static void igb_configure_queues(struct adapter *adapter);
302 /*********************************************************************
303 * FreeBSD Device Interface Entry Points
304 *********************************************************************/
305 static device_method_t em_methods[] = {
306 /* Device interface */
307 DEVMETHOD(device_register, em_register),
308 DEVMETHOD(device_probe, iflib_device_probe),
309 DEVMETHOD(device_attach, iflib_device_attach),
310 DEVMETHOD(device_detach, iflib_device_detach),
311 DEVMETHOD(device_shutdown, iflib_device_shutdown),
312 DEVMETHOD(device_suspend, iflib_device_suspend),
313 DEVMETHOD(device_resume, iflib_device_resume),
317 static device_method_t igb_methods[] = {
318 /* Device interface */
319 DEVMETHOD(device_register, igb_register),
320 DEVMETHOD(device_probe, iflib_device_probe),
321 DEVMETHOD(device_attach, iflib_device_attach),
322 DEVMETHOD(device_detach, iflib_device_detach),
323 DEVMETHOD(device_shutdown, iflib_device_shutdown),
324 DEVMETHOD(device_suspend, iflib_device_suspend),
325 DEVMETHOD(device_resume, iflib_device_resume),
330 static driver_t em_driver = {
331 "em", em_methods, sizeof(struct adapter),
334 static devclass_t em_devclass;
335 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
337 MODULE_DEPEND(em, pci, 1, 1, 1);
338 MODULE_DEPEND(em, ether, 1, 1, 1);
339 MODULE_DEPEND(em, iflib, 1, 1, 1);
341 static driver_t igb_driver = {
342 "igb", igb_methods, sizeof(struct adapter),
345 static devclass_t igb_devclass;
346 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
348 MODULE_DEPEND(igb, pci, 1, 1, 1);
349 MODULE_DEPEND(igb, ether, 1, 1, 1);
350 MODULE_DEPEND(igb, iflib, 1, 1, 1);
353 static device_method_t em_if_methods[] = {
354 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
355 DEVMETHOD(ifdi_attach_post, em_if_attach_post),
356 DEVMETHOD(ifdi_detach, em_if_detach),
357 DEVMETHOD(ifdi_shutdown, em_if_shutdown),
358 DEVMETHOD(ifdi_suspend, em_if_suspend),
359 DEVMETHOD(ifdi_resume, em_if_resume),
360 DEVMETHOD(ifdi_init, em_if_init),
361 DEVMETHOD(ifdi_stop, em_if_stop),
362 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
363 DEVMETHOD(ifdi_intr_enable, em_if_enable_intr),
364 DEVMETHOD(ifdi_intr_disable, em_if_disable_intr),
365 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
366 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
367 DEVMETHOD(ifdi_queues_free, em_if_queues_free),
368 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
369 DEVMETHOD(ifdi_multi_set, em_if_multi_set),
370 DEVMETHOD(ifdi_media_status, em_if_media_status),
371 DEVMETHOD(ifdi_media_change, em_if_media_change),
372 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
373 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
374 DEVMETHOD(ifdi_timer, em_if_timer),
375 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
376 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
377 DEVMETHOD(ifdi_get_counter, em_if_get_counter),
378 DEVMETHOD(ifdi_led_func, em_if_led_func),
379 DEVMETHOD(ifdi_queue_intr_enable, em_if_queue_intr_enable),
384 * note that if (adapter->msix_mem) is replaced by:
385 * if (adapter->intr_type == IFLIB_INTR_MSIX)
387 static driver_t em_if_driver = {
388 "em_if", em_if_methods, sizeof(struct adapter)
391 /*********************************************************************
392 * Tunable default values.
393 *********************************************************************/
395 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000)
396 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024)
399 #define MAX_INTS_PER_SEC 8000
400 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256))
402 /* Allow common code without TSO */
407 #define TSO_WORKAROUND 4
409 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters");
411 static int em_disable_crc_stripping = 0;
412 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
413 &em_disable_crc_stripping, 0, "Disable CRC Stripping");
415 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
416 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
417 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
418 0, "Default transmit interrupt delay in usecs");
419 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
420 0, "Default receive interrupt delay in usecs");
422 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
423 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
424 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
425 &em_tx_abs_int_delay_dflt, 0,
426 "Default transmit interrupt delay limit in usecs");
427 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
428 &em_rx_abs_int_delay_dflt, 0,
429 "Default receive interrupt delay limit in usecs");
431 static int em_smart_pwr_down = FALSE;
432 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
433 0, "Set to true to leave smart power down enabled on newer adapters");
435 /* Controls whether promiscuous also shows bad packets */
436 static int em_debug_sbp = TRUE;
437 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
438 "Show bad packets in promiscuous mode");
440 /* How many packets rxeof tries to clean at a time */
441 static int em_rx_process_limit = 100;
442 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
443 &em_rx_process_limit, 0,
444 "Maximum number of received packets to process "
445 "at a time, -1 means unlimited");
447 /* Energy efficient ethernet - default to OFF */
448 static int eee_setting = 1;
449 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
450 "Enable Energy Efficient Ethernet");
453 ** Tuneable Interrupt rate
455 static int em_max_interrupt_rate = 8000;
456 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
457 &em_max_interrupt_rate, 0, "Maximum interrupts per second");
461 /* Global used in WOL setup with multiport cards */
462 static int global_quad_port_a = 0;
464 extern struct if_txrx igb_txrx;
465 extern struct if_txrx em_txrx;
466 extern struct if_txrx lem_txrx;
468 static struct if_shared_ctx em_sctx_init = {
469 .isc_magic = IFLIB_MAGIC,
470 .isc_q_align = PAGE_SIZE,
471 .isc_tx_maxsize = EM_TSO_SIZE,
472 .isc_tx_maxsegsize = PAGE_SIZE,
473 .isc_rx_maxsize = MJUM9BYTES,
474 .isc_rx_nsegments = 1,
475 .isc_rx_maxsegsize = MJUM9BYTES,
479 .isc_admin_intrcnt = 1,
480 .isc_vendor_info = em_vendor_info_array,
481 .isc_driver_version = em_driver_version,
482 .isc_driver = &em_if_driver,
483 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP,
485 .isc_nrxd_min = {EM_MIN_RXD},
486 .isc_ntxd_min = {EM_MIN_TXD},
487 .isc_nrxd_max = {EM_MAX_RXD},
488 .isc_ntxd_max = {EM_MAX_TXD},
489 .isc_nrxd_default = {EM_DEFAULT_RXD},
490 .isc_ntxd_default = {EM_DEFAULT_TXD},
493 if_shared_ctx_t em_sctx = &em_sctx_init;
496 static struct if_shared_ctx igb_sctx_init = {
497 .isc_magic = IFLIB_MAGIC,
498 .isc_q_align = PAGE_SIZE,
499 .isc_tx_maxsize = EM_TSO_SIZE,
500 .isc_tx_maxsegsize = PAGE_SIZE,
501 .isc_rx_maxsize = MJUM9BYTES,
502 .isc_rx_nsegments = 1,
503 .isc_rx_maxsegsize = MJUM9BYTES,
507 .isc_admin_intrcnt = 1,
508 .isc_vendor_info = igb_vendor_info_array,
509 .isc_driver_version = em_driver_version,
510 .isc_driver = &em_if_driver,
511 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP,
513 .isc_nrxd_min = {EM_MIN_RXD},
514 .isc_ntxd_min = {EM_MIN_TXD},
515 .isc_nrxd_max = {EM_MAX_RXD},
516 .isc_ntxd_max = {EM_MAX_TXD},
517 .isc_nrxd_default = {EM_DEFAULT_RXD},
518 .isc_ntxd_default = {EM_DEFAULT_TXD},
521 if_shared_ctx_t igb_sctx = &igb_sctx_init;
523 /*****************************************************************
527 ****************************************************************/
528 #define IGB_REGS_LEN 739
530 static int em_get_regs(SYSCTL_HANDLER_ARGS)
532 struct adapter *adapter = (struct adapter *)arg1;
533 struct e1000_hw *hw = &adapter->hw;
536 u32 *regs_buff = (u32 *)malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_NOWAIT);
539 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
541 rc = sysctl_wire_old_buffer(req, 0);
546 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
551 /* General Registers */
552 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
553 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
554 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
555 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
556 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
557 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
558 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
559 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
560 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
561 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
562 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
563 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
564 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
565 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
566 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
567 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
568 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
569 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
570 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
571 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
572 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
573 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
575 sbuf_printf(sb, "General Registers\n");
576 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
577 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
578 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]);
580 sbuf_printf(sb, "Interrupt Registers\n");
581 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
583 sbuf_printf(sb, "RX Registers\n");
584 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
585 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
586 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
587 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
588 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
589 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
590 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
592 sbuf_printf(sb, "TX Registers\n");
593 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
594 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
595 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
596 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
597 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
598 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
599 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
600 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
601 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
602 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
603 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
607 if_softc_ctx_t scctx = adapter->shared;
608 struct rx_ring *rxr = &rx_que->rxr;
609 struct tx_ring *txr = &tx_que->txr;
610 int ntxd = scctx->isc_ntxd[0];
611 int nrxd = scctx->isc_nrxd[0];
614 for (j = 0; j < nrxd; j++) {
615 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
616 u32 length = le32toh(rxr->rx_base[j].wb.upper.length);
617 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
620 for (j = 0; j < min(ntxd, 256); j++) {
621 struct em_txbuffer *buf = &txr->tx_buffers[j];
622 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
624 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n",
625 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
626 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
632 rc = sbuf_finish(sb);
638 em_register(device_t dev)
644 igb_register(device_t dev)
650 em_init_tx_ring(struct em_tx_queue *que)
652 struct adapter *sc = que->adapter;
653 if_softc_ctx_t scctx = sc->shared;
654 struct tx_ring *txr = &que->txr;
655 struct em_txbuffer *tx_buffer;
657 tx_buffer = txr->tx_buffers;
658 for (int i = 0; i < scctx->isc_ntxd[0]; i++, tx_buffer++) {
664 em_set_num_queues(if_ctx_t ctx)
666 struct adapter *adapter = iflib_get_softc(ctx);
669 /* Sanity check based on HW */
670 switch (adapter->hw.mac.type) {
695 IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \
696 IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | \
697 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU;
700 IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \
701 IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM | \
702 IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU | IFCAP_TXCSUM_IPV6 | IFCAP_HWCSUM_IPV6 | IFCAP_JUMBO_MTU;
704 /*********************************************************************
705 * Device initialization routine
707 * The attach entry point is called when the driver is being loaded.
708 * This routine identifies the type of hardware, allocates all resources
709 * and initializes the hardware.
711 * return 0 on success, positive on failure
712 *********************************************************************/
715 em_if_attach_pre(if_ctx_t ctx)
717 struct adapter *adapter;
718 if_softc_ctx_t scctx;
723 INIT_DEBUGOUT("em_if_attach_pre begin");
724 dev = iflib_get_dev(ctx);
725 adapter = iflib_get_softc(ctx);
727 if (resource_disabled("em", device_get_unit(dev))) {
728 device_printf(dev, "Disabled by device hint\n");
733 adapter->dev = adapter->osdep.dev = dev;
734 scctx = adapter->shared = iflib_get_softc_ctx(ctx);
735 adapter->media = iflib_get_media(ctx);
738 adapter->tx_process_limit = scctx->isc_ntxd[0];
741 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
742 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
743 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
744 em_sysctl_nvm_info, "I", "NVM Information");
746 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
747 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
748 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
749 em_sysctl_debug_info, "I", "Debug Information");
751 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
752 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
753 OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
754 em_set_flowcntl, "I", "Flow Control");
756 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
757 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
758 OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0,
759 em_get_regs, "A", "Dump Registers");
761 /* Determine hardware and mac info */
762 em_identify_hardware(ctx);
764 /* Set isc_msix_bar */
765 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR);
766 scctx->isc_tx_nsegments = EM_MAX_SCATTER;
767 scctx->isc_tx_tso_segments_max = scctx->isc_tx_nsegments;
768 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
769 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
770 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
771 device_printf(dev, "attach_pre capping queues at %d\n", scctx->isc_ntxqsets_max);
773 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
776 if (adapter->hw.mac.type >= igb_mac_min) {
779 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
780 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
781 scctx->isc_txrx = &igb_txrx;
782 scctx->isc_capenable = IGB_CAPS;
783 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | CSUM_IP6_TCP \
784 | CSUM_IP6_UDP | CSUM_IP6_TCP;
785 if (adapter->hw.mac.type != e1000_82575)
786 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
789 ** Some new devices, as with ixgbe, now may
790 ** use a different BAR, so we need to keep
791 ** track of which is used.
793 try_second_bar = pci_read_config(dev, scctx->isc_msix_bar, 4);
794 if (try_second_bar == 0)
795 scctx->isc_msix_bar += 4;
797 } else if (adapter->hw.mac.type >= em_mac_min) {
798 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
799 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
800 scctx->isc_txrx = &em_txrx;
801 scctx->isc_capenable = EM_CAPS;
802 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
804 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
805 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
806 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
807 scctx->isc_txrx = &lem_txrx;
808 scctx->isc_capenable = EM_CAPS;
809 if (adapter->hw.mac.type < e1000_82543)
810 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
811 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
812 scctx->isc_msix_bar = 0;
815 /* Setup PCI resources */
816 if (em_allocate_pci_resources(ctx)) {
817 device_printf(dev, "Allocation of PCI resources failed\n");
823 ** For ICH8 and family we need to
824 ** map the flash memory, and this
825 ** must happen after the MAC is
828 if ((hw->mac.type == e1000_ich8lan) ||
829 (hw->mac.type == e1000_ich9lan) ||
830 (hw->mac.type == e1000_ich10lan) ||
831 (hw->mac.type == e1000_pchlan) ||
832 (hw->mac.type == e1000_pch2lan) ||
833 (hw->mac.type == e1000_pch_lpt)) {
834 int rid = EM_BAR_TYPE_FLASH;
835 adapter->flash = bus_alloc_resource_any(dev,
836 SYS_RES_MEMORY, &rid, RF_ACTIVE);
837 if (adapter->flash == NULL) {
838 device_printf(dev, "Mapping of Flash failed\n");
842 /* This is used in the shared code */
843 hw->flash_address = (u8 *)adapter->flash;
844 adapter->osdep.flash_bus_space_tag =
845 rman_get_bustag(adapter->flash);
846 adapter->osdep.flash_bus_space_handle =
847 rman_get_bushandle(adapter->flash);
850 ** In the new SPT device flash is not a
851 ** separate BAR, rather it is also in BAR0,
852 ** so use the same tag and an offset handle for the
853 ** FLASH read/write macros in the shared code.
855 else if (hw->mac.type == e1000_pch_spt) {
856 adapter->osdep.flash_bus_space_tag =
857 adapter->osdep.mem_bus_space_tag;
858 adapter->osdep.flash_bus_space_handle =
859 adapter->osdep.mem_bus_space_handle
860 + E1000_FLASH_BASE_ADDR;
863 /* Do Shared Code initialization */
864 error = e1000_setup_init_funcs(hw, TRUE);
866 device_printf(dev, "Setup of Shared code failed, error %d\n",
873 e1000_get_bus_info(hw);
875 /* Set up some sysctls for the tunable interrupt delays */
876 em_add_int_delay_sysctl(adapter, "rx_int_delay",
877 "receive interrupt delay in usecs", &adapter->rx_int_delay,
878 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
879 em_add_int_delay_sysctl(adapter, "tx_int_delay",
880 "transmit interrupt delay in usecs", &adapter->tx_int_delay,
881 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
882 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
883 "receive interrupt delay limit in usecs",
884 &adapter->rx_abs_int_delay,
885 E1000_REGISTER(hw, E1000_RADV),
886 em_rx_abs_int_delay_dflt);
887 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
888 "transmit interrupt delay limit in usecs",
889 &adapter->tx_abs_int_delay,
890 E1000_REGISTER(hw, E1000_TADV),
891 em_tx_abs_int_delay_dflt);
892 em_add_int_delay_sysctl(adapter, "itr",
893 "interrupt delay limit in usecs/4",
895 E1000_REGISTER(hw, E1000_ITR),
898 /* Sysctl for limiting the amount of work done in the taskqueue */
899 em_set_sysctl_value(adapter, "rx_processing_limit",
900 "max number of rx packets to process", &adapter->rx_process_limit,
901 em_rx_process_limit);
903 hw->mac.autoneg = DO_AUTO_NEG;
904 hw->phy.autoneg_wait_to_complete = FALSE;
905 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
907 if (adapter->hw.mac.type < em_mac_min) {
908 e1000_init_script_state_82541(&adapter->hw, TRUE);
909 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
912 if (hw->phy.media_type == e1000_media_type_copper) {
913 hw->phy.mdix = AUTO_ALL_MODES;
914 hw->phy.disable_polarity_correction = FALSE;
915 hw->phy.ms_type = EM_MASTER_SLAVE;
919 * Set the frame limits assuming
920 * standard ethernet sized frames.
922 adapter->hw.mac.max_frame_size =
923 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
926 * This controls when hardware reports transmit completion
929 hw->mac.report_tx_early = 1;
931 /* Allocate multicast array memory. */
932 adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN *
933 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
934 if (adapter->mta == NULL) {
935 device_printf(dev, "Can not allocate multicast setup array\n");
940 /* Check SOL/IDER usage */
941 if (e1000_check_reset_block(hw))
942 device_printf(dev, "PHY reset is blocked"
943 " due to SOL/IDER session.\n");
945 /* Sysctl for setting Energy Efficient Ethernet */
946 hw->dev_spec.ich8lan.eee_disable = eee_setting;
947 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
948 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
949 OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW,
950 adapter, 0, em_sysctl_eee, "I",
951 "Disable Energy Efficient Ethernet");
954 ** Start from a known state, this is
955 ** important in reading the nvm and
960 /* Make sure we have a good EEPROM before we read from it */
961 if (e1000_validate_nvm_checksum(hw) < 0) {
963 ** Some PCI-E parts fail the first check due to
964 ** the link being in sleep state, call it again,
965 ** if it fails a second time its a real issue.
967 if (e1000_validate_nvm_checksum(hw) < 0) {
969 "The EEPROM Checksum Is Not Valid\n");
975 /* Copy the permanent MAC address out of the EEPROM */
976 if (e1000_read_mac_addr(hw) < 0) {
977 device_printf(dev, "EEPROM read error while reading MAC"
983 if (!em_is_valid_ether_addr(hw->mac.addr)) {
984 device_printf(dev, "Invalid MAC address\n");
989 /* Disable ULP support */
990 e1000_disable_ulp_lpt_lp(hw, TRUE);
993 * Get Wake-on-Lan and Management info for later use
997 iflib_set_mac(ctx, hw->mac.addr);
1002 em_release_hw_control(adapter);
1004 em_free_pci_resources(ctx);
1005 free(adapter->mta, M_DEVBUF);
1011 em_if_attach_post(if_ctx_t ctx)
1013 struct adapter *adapter = iflib_get_softc(ctx);
1014 struct e1000_hw *hw = &adapter->hw;
1017 /* Setup OS specific network interface */
1018 error = em_setup_interface(ctx);
1025 /* Initialize statistics */
1026 em_update_stats_counters(adapter);
1027 hw->mac.get_link_status = 1;
1028 em_if_update_admin_status(ctx);
1029 em_add_hw_stats(adapter);
1031 /* Non-AMT based hardware can now take control from firmware */
1032 if (adapter->has_manage && !adapter->has_amt)
1033 em_get_hw_control(adapter);
1035 INIT_DEBUGOUT("em_if_attach_post: end");
1040 em_release_hw_control(adapter);
1041 em_free_pci_resources(ctx);
1042 em_if_queues_free(ctx);
1043 free(adapter->mta, M_DEVBUF);
1048 /*********************************************************************
1049 * Device removal routine
1051 * The detach entry point is called when the driver is being removed.
1052 * This routine stops the adapter and deallocates all the resources
1053 * that were allocated for driver operation.
1055 * return 0 on success, positive on failure
1056 *********************************************************************/
1059 em_if_detach(if_ctx_t ctx)
1061 struct adapter *adapter = iflib_get_softc(ctx);
1063 INIT_DEBUGOUT("em_detach: begin");
1065 e1000_phy_hw_reset(&adapter->hw);
1067 em_release_manageability(adapter);
1068 em_release_hw_control(adapter);
1069 em_free_pci_resources(ctx);
1074 /*********************************************************************
1076 * Shutdown entry point
1078 **********************************************************************/
1081 em_if_shutdown(if_ctx_t ctx)
1083 return em_if_suspend(ctx);
1087 * Suspend/resume device methods.
1090 em_if_suspend(if_ctx_t ctx)
1092 struct adapter *adapter = iflib_get_softc(ctx);
1094 em_release_manageability(adapter);
1095 em_release_hw_control(adapter);
1096 em_enable_wakeup(ctx);
1101 em_if_resume(if_ctx_t ctx)
1103 struct adapter *adapter = iflib_get_softc(ctx);
1105 if (adapter->hw.mac.type == e1000_pch2lan)
1106 e1000_resume_workarounds_pchlan(&adapter->hw);
1108 em_init_manageability(adapter);
1114 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1117 struct adapter *adapter = iflib_get_softc(ctx);
1118 struct ifnet *ifp = iflib_get_ifp(ctx);
1120 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1122 switch (adapter->hw.mac.type) {
1126 case e1000_ich10lan:
1132 case e1000_80003es2lan: /* 9K Jumbo Frame size */
1133 max_frame_size = 9234;
1136 max_frame_size = 4096;
1138 /* Adapters that do not support jumbo frames */
1140 max_frame_size = ETHER_MAX_LEN;
1143 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1145 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1149 adapter->hw.mac.max_frame_size = if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN;
1153 /*********************************************************************
1156 * This routine is used in two ways. It is used by the stack as
1157 * init entry point in network interface structure. It is also used
1158 * by the driver as a hw/sw initialization routine to get to a
1161 * return 0 on success, positive on failure
1162 **********************************************************************/
1165 em_if_init(if_ctx_t ctx)
1167 struct adapter *adapter = iflib_get_softc(ctx);
1168 struct ifnet *ifp = iflib_get_ifp(ctx);
1170 INIT_DEBUGOUT("em_if_init: begin");
1172 /* Get the latest mac address, User can use a LAA */
1173 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr,
1176 /* Put the address into the Receive Address Array */
1177 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1180 * With the 82571 adapter, RAR[0] may be overwritten
1181 * when the other port is reset, we make a duplicate
1182 * in RAR[14] for that eventuality, this assures
1183 * the interface continues to function.
1185 if (adapter->hw.mac.type == e1000_82571) {
1186 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1187 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1188 E1000_RAR_ENTRIES - 1);
1191 /* Initialize the hardware */
1193 em_if_update_admin_status(ctx);
1195 /* Setup VLAN support, basic and offload if available */
1196 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1198 /* Clear bad data from Rx FIFOs */
1199 if (adapter->hw.mac.type >= igb_mac_min)
1200 e1000_rx_fifo_flush_82575(&adapter->hw);
1202 /* Configure for OS presence */
1203 em_init_manageability(adapter);
1205 /* Prepare transmit descriptors and buffers */
1206 em_initialize_transmit_unit(ctx);
1208 /* Setup Multicast table */
1209 em_if_multi_set(ctx);
1212 ** Figure out the desired mbuf
1213 ** pool for doing jumbos
1215 if (adapter->hw.mac.max_frame_size <= 2048)
1216 adapter->rx_mbuf_sz = MCLBYTES;
1217 else if (adapter->hw.mac.max_frame_size <= 4096)
1218 adapter->rx_mbuf_sz = MJUMPAGESIZE;
1220 adapter->rx_mbuf_sz = MJUM9BYTES;
1222 em_initialize_receive_unit(ctx);
1224 /* Use real VLAN Filter support? */
1225 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1226 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
1227 /* Use real VLAN Filter support */
1228 em_setup_vlan_hw_support(adapter);
1231 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1232 ctrl |= E1000_CTRL_VME;
1233 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1237 /* Don't lose promiscuous settings */
1238 em_if_set_promisc(ctx, IFF_PROMISC);
1239 e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1241 /* MSI/X configuration for 82574 */
1242 if (adapter->hw.mac.type == e1000_82574) {
1243 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1245 tmp |= E1000_CTRL_EXT_PBA_CLR;
1246 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1247 /* Set the IVAR - interrupt vector routing. */
1248 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars);
1249 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1250 igb_configure_queues(adapter);
1252 /* this clears any pending interrupts */
1253 E1000_READ_REG(&adapter->hw, E1000_ICR);
1254 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC);
1256 /* AMT based hardware can now take control from firmware */
1257 if (adapter->has_manage && adapter->has_amt)
1258 em_get_hw_control(adapter);
1260 /* Set Energy Efficient Ethernet */
1261 if (adapter->hw.mac.type >= igb_mac_min &&
1262 adapter->hw.phy.media_type == e1000_media_type_copper) {
1263 if (adapter->hw.mac.type == e1000_i354)
1264 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
1266 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
1270 /*********************************************************************
1272 * Fast Legacy/MSI Combined Interrupt Service routine
1274 *********************************************************************/
1278 struct adapter *adapter = arg;
1279 if_ctx_t ctx = adapter->ctx;
1282 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1284 if (adapter->intr_type != IFLIB_INTR_LEGACY)
1287 if (reg_icr == 0xffffffff)
1288 return FILTER_STRAY;
1290 /* Definitely not our interrupt. */
1292 return FILTER_STRAY;
1295 * Starting with the 82571 chip, bit 31 should be used to
1296 * determine whether the interrupt belongs to us.
1298 if (adapter->hw.mac.type >= e1000_82571 &&
1299 (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1300 return FILTER_STRAY;
1303 /* Link status change */
1304 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1305 adapter->hw.mac.get_link_status = 1;
1306 iflib_admin_intr_deferred(ctx);
1309 if (reg_icr & E1000_ICR_RXO)
1310 adapter->rx_overruns++;
1312 return (FILTER_SCHEDULE_THREAD);
1316 igb_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq)
1318 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims);
1322 em_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq)
1324 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims);
1328 em_if_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1330 struct adapter *adapter = iflib_get_softc(ctx);
1331 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1333 if (adapter->hw.mac.type >= igb_mac_min)
1334 igb_enable_queue(adapter, rxq);
1336 em_enable_queue(adapter, rxq);
1340 /*********************************************************************
1342 * MSIX RX Interrupt Service routine
1344 **********************************************************************/
1346 em_msix_que(void *arg)
1348 struct em_rx_queue *que = arg;
1352 return (FILTER_SCHEDULE_THREAD);
1355 /*********************************************************************
1357 * MSIX Link Fast Interrupt Service routine
1359 **********************************************************************/
1361 em_msix_link(void *arg)
1363 struct adapter *adapter = arg;
1366 ++adapter->link_irq;
1367 MPASS(adapter->hw.back != NULL);
1368 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1370 if (reg_icr & E1000_ICR_RXO)
1371 adapter->rx_overruns++;
1373 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1374 em_handle_link(adapter->ctx);
1376 E1000_WRITE_REG(&adapter->hw, E1000_IMS,
1377 EM_MSIX_LINK | E1000_IMS_LSC);
1378 if (adapter->hw.mac.type >= igb_mac_min)
1379 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1384 ** Because we must read the ICR for this interrupt
1385 ** it may clear other causes using autoclear, for
1386 ** this reason we simply create a soft interrupt
1387 ** for all these vectors.
1389 if (reg_icr && adapter->hw.mac.type < igb_mac_min) {
1390 E1000_WRITE_REG(&adapter->hw,
1391 E1000_ICS, adapter->ims);
1394 return (FILTER_HANDLED);
1398 em_handle_link(void *context)
1400 if_ctx_t ctx = context;
1401 struct adapter *adapter = iflib_get_softc(ctx);
1403 adapter->hw.mac.get_link_status = 1;
1404 iflib_admin_intr_deferred(ctx);
1408 /*********************************************************************
1410 * Media Ioctl callback
1412 * This routine is called whenever the user queries the status of
1413 * the interface using ifconfig.
1415 **********************************************************************/
1417 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1419 struct adapter *adapter = iflib_get_softc(ctx);
1420 u_char fiber_type = IFM_1000_SX;
1422 INIT_DEBUGOUT("em_if_media_status: begin");
1424 iflib_admin_intr_deferred(ctx);
1426 ifmr->ifm_status = IFM_AVALID;
1427 ifmr->ifm_active = IFM_ETHER;
1429 if (!adapter->link_active) {
1433 ifmr->ifm_status |= IFM_ACTIVE;
1435 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
1436 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1437 if (adapter->hw.mac.type == e1000_82545)
1438 fiber_type = IFM_1000_LX;
1439 ifmr->ifm_active |= fiber_type | IFM_FDX;
1441 switch (adapter->link_speed) {
1443 ifmr->ifm_active |= IFM_10_T;
1446 ifmr->ifm_active |= IFM_100_TX;
1449 ifmr->ifm_active |= IFM_1000_T;
1452 if (adapter->link_duplex == FULL_DUPLEX)
1453 ifmr->ifm_active |= IFM_FDX;
1455 ifmr->ifm_active |= IFM_HDX;
1459 /*********************************************************************
1461 * Media Ioctl callback
1463 * This routine is called when the user changes speed/duplex using
1464 * media/mediopt option with ifconfig.
1466 **********************************************************************/
1468 em_if_media_change(if_ctx_t ctx)
1470 struct adapter *adapter = iflib_get_softc(ctx);
1471 struct ifmedia *ifm = iflib_get_media(ctx);
1473 INIT_DEBUGOUT("em_if_media_change: begin");
1475 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1478 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1480 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1481 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1486 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1487 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1490 adapter->hw.mac.autoneg = FALSE;
1491 adapter->hw.phy.autoneg_advertised = 0;
1492 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1493 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1495 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1498 adapter->hw.mac.autoneg = FALSE;
1499 adapter->hw.phy.autoneg_advertised = 0;
1500 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1501 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1503 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1506 device_printf(adapter->dev, "Unsupported media type\n");
1515 em_if_set_promisc(if_ctx_t ctx, int flags)
1517 struct adapter *adapter = iflib_get_softc(ctx);
1520 em_disable_promisc(ctx);
1522 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1524 if (flags & IFF_PROMISC) {
1525 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1526 /* Turn this on if you want to see bad packets */
1528 reg_rctl |= E1000_RCTL_SBP;
1529 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1530 } else if (flags & IFF_ALLMULTI) {
1531 reg_rctl |= E1000_RCTL_MPE;
1532 reg_rctl &= ~E1000_RCTL_UPE;
1533 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1539 em_disable_promisc(if_ctx_t ctx)
1541 struct adapter *adapter = iflib_get_softc(ctx);
1542 struct ifnet *ifp = iflib_get_ifp(ctx);
1546 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1547 reg_rctl &= (~E1000_RCTL_UPE);
1548 if (if_getflags(ifp) & IFF_ALLMULTI)
1549 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1551 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES);
1552 /* Don't disable if in MAX groups */
1553 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1554 reg_rctl &= (~E1000_RCTL_MPE);
1555 reg_rctl &= (~E1000_RCTL_SBP);
1556 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1560 /*********************************************************************
1563 * This routine is called whenever multicast address list is updated.
1565 **********************************************************************/
1568 em_if_multi_set(if_ctx_t ctx)
1570 struct adapter *adapter = iflib_get_softc(ctx);
1571 struct ifnet *ifp = iflib_get_ifp(ctx);
1573 u8 *mta; /* Multicast array memory */
1576 IOCTL_DEBUGOUT("em_set_multi: begin");
1579 bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1581 if (adapter->hw.mac.type == e1000_82542 &&
1582 adapter->hw.revision_id == E1000_REVISION_2) {
1583 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1584 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1585 e1000_pci_clear_mwi(&adapter->hw);
1586 reg_rctl |= E1000_RCTL_RST;
1587 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1591 if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES);
1593 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1594 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1595 reg_rctl |= E1000_RCTL_MPE;
1596 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1598 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
1600 if (adapter->hw.mac.type == e1000_82542 &&
1601 adapter->hw.revision_id == E1000_REVISION_2) {
1602 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1603 reg_rctl &= ~E1000_RCTL_RST;
1604 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1606 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1607 e1000_pci_set_mwi(&adapter->hw);
1612 /*********************************************************************
1615 * This routine checks for link status and updates statistics.
1617 **********************************************************************/
1620 em_if_timer(if_ctx_t ctx, uint16_t qid)
1622 struct adapter *adapter = iflib_get_softc(ctx);
1623 struct em_rx_queue *que;
1627 em_if_update_admin_status(ctx);
1628 em_update_stats_counters(adapter);
1630 /* Reset LAA into RAR[0] on 82571 */
1631 if ((adapter->hw.mac.type == e1000_82571) &&
1632 e1000_get_laa_state_82571(&adapter->hw))
1633 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1635 if (adapter->hw.mac.type < em_mac_min)
1636 lem_smartspeed(adapter);
1638 /* Mask to use in the irq trigger */
1639 if (adapter->intr_type == IFLIB_INTR_MSIX) {
1640 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++)
1641 trigger |= que->eims;
1643 trigger = E1000_ICS_RXDMT0;
1649 em_if_update_admin_status(if_ctx_t ctx)
1651 struct adapter *adapter = iflib_get_softc(ctx);
1652 struct e1000_hw *hw = &adapter->hw;
1653 struct ifnet *ifp = iflib_get_ifp(ctx);
1654 device_t dev = iflib_get_dev(ctx);
1657 /* Get the cached link value or read phy for real */
1658 switch (hw->phy.media_type) {
1659 case e1000_media_type_copper:
1660 if (hw->mac.get_link_status) {
1661 if (hw->mac.type == e1000_pch_spt)
1663 /* Do the work to read phy */
1664 e1000_check_for_link(hw);
1665 link_check = !hw->mac.get_link_status;
1666 if (link_check) /* ESB2 fix */
1667 e1000_cfg_on_link_up(hw);
1672 case e1000_media_type_fiber:
1673 e1000_check_for_link(hw);
1674 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1677 case e1000_media_type_internal_serdes:
1678 e1000_check_for_link(hw);
1679 link_check = adapter->hw.mac.serdes_has_link;
1682 case e1000_media_type_unknown:
1686 /* Now check for a transition */
1687 if (link_check && (adapter->link_active == 0)) {
1688 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
1689 &adapter->link_duplex);
1690 /* Check if we must disable SPEED_MODE bit on PCI-E */
1691 if ((adapter->link_speed != SPEED_1000) &&
1692 ((hw->mac.type == e1000_82571) ||
1693 (hw->mac.type == e1000_82572))) {
1695 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1696 tarc0 &= ~TARC_SPEED_MODE_BIT;
1697 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1700 device_printf(dev, "Link is up %d Mbps %s\n",
1701 adapter->link_speed,
1702 ((adapter->link_duplex == FULL_DUPLEX) ?
1703 "Full Duplex" : "Half Duplex"));
1704 adapter->link_active = 1;
1705 adapter->smartspeed = 0;
1706 if_setbaudrate(ifp, adapter->link_speed * 1000000);
1707 iflib_link_state_change(ctx, LINK_STATE_UP, ifp->if_baudrate);
1708 printf("Link state changed to up\n");
1709 } else if (!link_check && (adapter->link_active == 1)) {
1710 if_setbaudrate(ifp, 0);
1711 adapter->link_speed = 0;
1712 adapter->link_duplex = 0;
1714 device_printf(dev, "Link is Down\n");
1715 adapter->link_active = 0;
1716 iflib_link_state_change(ctx, LINK_STATE_DOWN, ifp->if_baudrate);
1717 printf("link state changed to down\n");
1720 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC);
1723 /*********************************************************************
1725 * This routine disables all traffic on the adapter by issuing a
1726 * global reset on the MAC and deallocates TX/RX buffers.
1728 * This routine should always be called with BOTH the CORE
1730 **********************************************************************/
1733 em_if_stop(if_ctx_t ctx)
1735 struct adapter *adapter = iflib_get_softc(ctx);
1737 INIT_DEBUGOUT("em_stop: begin");
1739 e1000_reset_hw(&adapter->hw);
1740 if (adapter->hw.mac.type >= e1000_82544)
1741 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0);
1743 e1000_led_off(&adapter->hw);
1744 e1000_cleanup_led(&adapter->hw);
1748 /*********************************************************************
1750 * Determine hardware revision.
1752 **********************************************************************/
1754 em_identify_hardware(if_ctx_t ctx)
1756 device_t dev = iflib_get_dev(ctx);
1757 struct adapter *adapter = iflib_get_softc(ctx);
1759 /* Make sure our PCI config space has the necessary stuff set */
1760 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1762 /* Save off the information about this board */
1763 adapter->hw.vendor_id = pci_get_vendor(dev);
1764 adapter->hw.device_id = pci_get_device(dev);
1765 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1766 adapter->hw.subsystem_vendor_id =
1767 pci_read_config(dev, PCIR_SUBVEND_0, 2);
1768 adapter->hw.subsystem_device_id =
1769 pci_read_config(dev, PCIR_SUBDEV_0, 2);
1771 /* Do Shared Code Init and Setup */
1772 if (e1000_set_mac_type(&adapter->hw)) {
1773 device_printf(dev, "Setup init failure\n");
1779 em_allocate_pci_resources(if_ctx_t ctx)
1781 struct adapter *adapter = iflib_get_softc(ctx);
1782 device_t dev = iflib_get_dev(ctx);
1786 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1788 if (adapter->memory == NULL) {
1789 device_printf(dev, "Unable to allocate bus resource: memory\n");
1792 adapter->osdep.mem_bus_space_tag =
1793 rman_get_bustag(adapter->memory);
1794 adapter->osdep.mem_bus_space_handle =
1795 rman_get_bushandle(adapter->memory);
1796 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle;
1798 /* Only older adapters use IO mapping */
1799 if (adapter->hw.mac.type < em_mac_min &&
1800 adapter->hw.mac.type > e1000_82543) {
1801 /* Figure our where our IO BAR is ? */
1802 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1803 val = pci_read_config(dev, rid, 4);
1804 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1805 adapter->io_rid = rid;
1809 /* check for 64bit BAR */
1810 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1813 if (rid >= PCIR_CIS) {
1814 device_printf(dev, "Unable to locate IO BAR\n");
1817 adapter->ioport = bus_alloc_resource_any(dev,
1818 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE);
1819 if (adapter->ioport == NULL) {
1820 device_printf(dev, "Unable to allocate bus resource: "
1824 adapter->hw.io_base = 0;
1825 adapter->osdep.io_bus_space_tag =
1826 rman_get_bustag(adapter->ioport);
1827 adapter->osdep.io_bus_space_handle =
1828 rman_get_bushandle(adapter->ioport);
1831 adapter->hw.back = &adapter->osdep;
1836 /*********************************************************************
1838 * Setup the MSIX Interrupt handlers
1840 **********************************************************************/
1842 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
1844 struct adapter *adapter = iflib_get_softc(ctx);
1845 struct em_rx_queue *rx_que = adapter->rx_queues;
1846 struct em_tx_queue *tx_que = adapter->tx_queues;
1847 int error, rid, i, vector = 0;
1850 /* First set up ring resources */
1851 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) {
1853 snprintf(buf, sizeof(buf), "rxq%d", i);
1854 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RX, em_msix_que, rx_que, rx_que->me, buf);
1856 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
1857 adapter->rx_num_queues = i + 1;
1861 rx_que->msix = vector;
1864 ** Set the bit to enable interrupt
1865 ** in E1000_IMS -- bits 20 and 21
1866 ** are for RX0 and RX1, note this has
1867 ** NOTHING to do with the MSIX vector
1869 if (adapter->hw.mac.type == e1000_82574) {
1870 rx_que->eims = 1 << (20 + i);
1871 adapter->ims |= rx_que->eims;
1872 adapter->ivars |= (8 | rx_que->msix) << (i * 4);
1873 } else if (adapter->hw.mac.type == e1000_82575)
1874 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
1876 rx_que->eims = 1 << vector;
1879 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
1881 snprintf(buf, sizeof(buf), "txq%d", i);
1882 tx_que = &adapter->tx_queues[i];
1883 iflib_softirq_alloc_generic(ctx, rid, IFLIB_INTR_TX, tx_que, tx_que->me, buf);
1885 tx_que->msix = vector;
1888 ** Set the bit to enable interrupt
1889 ** in E1000_IMS -- bits 22 and 23
1890 ** are for TX0 and TX1, note this has
1891 ** NOTHING to do with the MSIX vector
1893 if (adapter->hw.mac.type < igb_mac_min) {
1894 tx_que->eims = 1 << (22 + i);
1895 adapter->ims |= tx_que->eims;
1896 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
1897 } if (adapter->hw.mac.type == e1000_82575)
1898 tx_que->eims = E1000_EICR_TX_QUEUE0 << (i % adapter->tx_num_queues);
1900 tx_que->eims = 1 << (i % adapter->tx_num_queues);
1903 /* Link interrupt */
1905 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq");
1908 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
1911 adapter->linkvec = vector;
1912 if (adapter->hw.mac.type < igb_mac_min) {
1913 adapter->ivars |= (8 | vector) << 16;
1914 adapter->ivars |= 0x80000000;
1918 iflib_irq_free(ctx, &adapter->irq);
1919 rx_que = adapter->rx_queues;
1920 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++)
1921 iflib_irq_free(ctx, &rx_que->que_irq);
1926 igb_configure_queues(struct adapter *adapter)
1928 struct e1000_hw *hw = &adapter->hw;
1929 struct em_rx_queue *rx_que;
1930 struct em_tx_queue *tx_que;
1931 u32 tmp, ivar = 0, newitr = 0;
1933 /* First turn on RSS capability */
1934 if (adapter->hw.mac.type != e1000_82575)
1935 E1000_WRITE_REG(hw, E1000_GPIE,
1936 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
1937 E1000_GPIE_PBA | E1000_GPIE_NSICR);
1940 switch (adapter->hw.mac.type) {
1947 case e1000_vfadapt_i350:
1949 for (int i = 0; i < adapter->rx_num_queues; i++) {
1951 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
1952 rx_que = &adapter->rx_queues[i];
1955 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
1958 ivar |= rx_que->msix | E1000_IVAR_VALID;
1960 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
1963 for (int i = 0; i < adapter->tx_num_queues; i++) {
1965 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
1966 tx_que = &adapter->tx_queues[i];
1969 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
1972 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
1974 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
1975 adapter->que_mask |= tx_que->eims;
1978 /* And for the link interrupt */
1979 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
1980 adapter->link_mask = 1 << adapter->linkvec;
1981 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
1985 for (int i = 0; i < adapter->rx_num_queues; i++) {
1986 u32 index = i & 0x7; /* Each IVAR has two entries */
1987 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
1988 rx_que = &adapter->rx_queues[i];
1991 ivar |= rx_que->msix | E1000_IVAR_VALID;
1994 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
1996 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
1997 adapter->que_mask |= rx_que->eims;
2000 for (int i = 0; i < adapter->tx_num_queues; i++) {
2001 u32 index = i & 0x7; /* Each IVAR has two entries */
2002 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2003 tx_que = &adapter->tx_queues[i];
2006 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2009 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2011 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2012 adapter->que_mask |= tx_que->eims;
2015 /* And for the link interrupt */
2016 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2017 adapter->link_mask = 1 << adapter->linkvec;
2018 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2022 /* enable MSI-X support*/
2023 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2024 tmp |= E1000_CTRL_EXT_PBA_CLR;
2025 /* Auto-Mask interrupts upon ICR read. */
2026 tmp |= E1000_CTRL_EXT_EIAME;
2027 tmp |= E1000_CTRL_EXT_IRCA;
2028 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2031 for (int i = 0; i < adapter->rx_num_queues; i++) {
2032 rx_que = &adapter->rx_queues[i];
2033 tmp = E1000_EICR_RX_QUEUE0 << i;
2034 tmp |= E1000_EICR_TX_QUEUE0 << i;
2036 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2038 adapter->que_mask |= rx_que->eims;
2042 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec),
2044 adapter->link_mask |= E1000_EIMS_OTHER;
2049 /* Set the starting interrupt rate */
2050 if (em_max_interrupt_rate > 0)
2051 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2053 if (hw->mac.type == e1000_82575)
2054 newitr |= newitr << 16;
2056 newitr |= E1000_EITR_CNT_IGNR;
2058 for (int i = 0; i < adapter->rx_num_queues; i++) {
2059 rx_que = &adapter->rx_queues[i];
2060 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2067 em_free_pci_resources(if_ctx_t ctx)
2069 struct adapter *adapter = iflib_get_softc(ctx);
2070 struct em_rx_queue *que = adapter->rx_queues;
2071 device_t dev = iflib_get_dev(ctx);
2073 /* Release all msix queue resources */
2074 if (adapter->intr_type == IFLIB_INTR_MSIX)
2075 iflib_irq_free(ctx, &adapter->irq);
2077 for (int i = 0; i < adapter->rx_num_queues; i++, que++) {
2078 iflib_irq_free(ctx, &que->que_irq);
2082 /* First release all the interrupt resources */
2083 if (adapter->memory != NULL) {
2084 bus_release_resource(dev, SYS_RES_MEMORY,
2085 PCIR_BAR(0), adapter->memory);
2086 adapter->memory = NULL;
2089 if (adapter->flash != NULL) {
2090 bus_release_resource(dev, SYS_RES_MEMORY,
2091 EM_FLASH, adapter->flash);
2092 adapter->flash = NULL;
2094 if (adapter->ioport != NULL)
2095 bus_release_resource(dev, SYS_RES_IOPORT,
2096 adapter->io_rid, adapter->ioport);
2099 /* Setup MSI or MSI/X */
2101 em_setup_msix(if_ctx_t ctx)
2103 struct adapter *adapter = iflib_get_softc(ctx);
2105 if (adapter->hw.mac.type == e1000_82574) {
2106 em_enable_vectors_82574(ctx);
2111 /*********************************************************************
2113 * Initialize the hardware to a configuration
2114 * as specified by the adapter structure.
2116 **********************************************************************/
2119 lem_smartspeed(struct adapter *adapter)
2123 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) ||
2124 adapter->hw.mac.autoneg == 0 ||
2125 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2128 if (adapter->smartspeed == 0) {
2129 /* If Master/Slave config fault is asserted twice,
2130 * we assume back-to-back */
2131 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2132 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2134 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2135 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2136 e1000_read_phy_reg(&adapter->hw,
2137 PHY_1000T_CTRL, &phy_tmp);
2138 if(phy_tmp & CR_1000T_MS_ENABLE) {
2139 phy_tmp &= ~CR_1000T_MS_ENABLE;
2140 e1000_write_phy_reg(&adapter->hw,
2141 PHY_1000T_CTRL, phy_tmp);
2142 adapter->smartspeed++;
2143 if(adapter->hw.mac.autoneg &&
2144 !e1000_copper_link_autoneg(&adapter->hw) &&
2145 !e1000_read_phy_reg(&adapter->hw,
2146 PHY_CONTROL, &phy_tmp)) {
2147 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2148 MII_CR_RESTART_AUTO_NEG);
2149 e1000_write_phy_reg(&adapter->hw,
2150 PHY_CONTROL, phy_tmp);
2155 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2156 /* If still no link, perhaps using 2/3 pair cable */
2157 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2158 phy_tmp |= CR_1000T_MS_ENABLE;
2159 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2160 if(adapter->hw.mac.autoneg &&
2161 !e1000_copper_link_autoneg(&adapter->hw) &&
2162 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2163 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2164 MII_CR_RESTART_AUTO_NEG);
2165 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2168 /* Restart process after EM_SMARTSPEED_MAX iterations */
2169 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2170 adapter->smartspeed = 0;
2175 em_reset(if_ctx_t ctx)
2177 device_t dev = iflib_get_dev(ctx);
2178 struct adapter *adapter = iflib_get_softc(ctx);
2179 struct ifnet *ifp = iflib_get_ifp(ctx);
2180 struct e1000_hw *hw = &adapter->hw;
2184 INIT_DEBUGOUT("em_reset: begin");
2186 /* Set up smart power down as default off on newer adapters. */
2187 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2188 hw->mac.type == e1000_82572)) {
2191 /* Speed up time to link by disabling smart power down. */
2192 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2193 phy_tmp &= ~IGP02E1000_PM_SPD;
2194 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2198 * Packet Buffer Allocation (PBA)
2199 * Writing PBA sets the receive portion of the buffer
2200 * the remainder is used for the transmit buffer.
2202 switch (hw->mac.type) {
2203 /* Total Packet Buffer on these is 48K */
2206 case e1000_80003es2lan:
2207 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2209 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
2210 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2214 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2220 case e1000_ich10lan:
2221 /* Boost Receive side for jumbo frames */
2222 if (adapter->hw.mac.max_frame_size > 4096)
2223 pba = E1000_PBA_14K;
2225 pba = E1000_PBA_10K;
2231 pba = E1000_PBA_26K;
2234 if (adapter->hw.mac.max_frame_size > 8192)
2235 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2237 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2239 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
2242 * These parameters control the automatic generation (Tx) and
2243 * response (Rx) to Ethernet PAUSE frames.
2244 * - High water mark should allow for at least two frames to be
2245 * received after sending an XOFF.
2246 * - Low water mark works best when it is very near the high water mark.
2247 * This allows the receiver to restart by sending XON when it has
2248 * drained a bit. Here we use an arbitrary value of 1500 which will
2249 * restart after one full frame is pulled from the buffer. There
2250 * could be several smaller frames in the buffer and if so they will
2251 * not trigger the XON until their total number reduces the buffer
2253 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2255 rx_buffer_size = ((E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10 );
2256 hw->fc.high_water = rx_buffer_size -
2257 roundup2(adapter->hw.mac.max_frame_size, 1024);
2258 hw->fc.low_water = hw->fc.high_water - 1500;
2260 if (adapter->fc) /* locally set flow control value? */
2261 hw->fc.requested_mode = adapter->fc;
2263 hw->fc.requested_mode = e1000_fc_full;
2265 if (hw->mac.type == e1000_80003es2lan)
2266 hw->fc.pause_time = 0xFFFF;
2268 hw->fc.pause_time = EM_FC_PAUSE_TIME;
2270 hw->fc.send_xon = TRUE;
2272 /* Device specific overrides/settings */
2273 switch (hw->mac.type) {
2275 /* Workaround: no TX flow ctrl for PCH */
2276 hw->fc.requested_mode = e1000_fc_rx_pause;
2277 hw->fc.pause_time = 0xFFFF; /* override */
2278 if (if_getmtu(ifp) > ETHERMTU) {
2279 hw->fc.high_water = 0x3500;
2280 hw->fc.low_water = 0x1500;
2282 hw->fc.high_water = 0x5000;
2283 hw->fc.low_water = 0x3000;
2285 hw->fc.refresh_time = 0x1000;
2290 hw->fc.high_water = 0x5C20;
2291 hw->fc.low_water = 0x5048;
2292 hw->fc.pause_time = 0x0650;
2293 hw->fc.refresh_time = 0x0400;
2294 /* Jumbos need adjusted PBA */
2295 if (if_getmtu(ifp) > ETHERMTU)
2296 E1000_WRITE_REG(hw, E1000_PBA, 12);
2298 E1000_WRITE_REG(hw, E1000_PBA, 26);
2301 case e1000_ich10lan:
2302 if (if_getmtu(ifp) > ETHERMTU) {
2303 hw->fc.high_water = 0x2800;
2304 hw->fc.low_water = hw->fc.high_water - 8;
2307 /* else fall thru */
2309 if (hw->mac.type == e1000_80003es2lan)
2310 hw->fc.pause_time = 0xFFFF;
2314 /* Issue a global reset */
2316 E1000_WRITE_REG(hw, E1000_WUFC, 0);
2317 em_disable_aspm(adapter);
2319 if (e1000_init_hw(hw) < 0) {
2320 device_printf(dev, "Hardware Initialization Failed\n");
2324 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2325 e1000_get_phy_info(hw);
2326 e1000_check_for_link(hw);
2329 #define RSSKEYLEN 10
2331 em_initialize_rss_mapping(struct adapter *adapter)
2333 uint8_t rss_key[4 * RSSKEYLEN];
2335 struct e1000_hw *hw = &adapter->hw;
2341 arc4rand(rss_key, sizeof(rss_key), 0);
2342 for (i = 0; i < RSSKEYLEN; ++i) {
2345 rssrk = EM_RSSRK_VAL(rss_key, i);
2346 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2350 * Configure RSS redirect table in following fashion:
2351 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2353 for (i = 0; i < sizeof(reta); ++i) {
2356 q = (i % adapter->rx_num_queues) << 7;
2357 reta |= q << (8 * i);
2360 for (i = 0; i < 32; ++i)
2361 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2363 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2364 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2365 E1000_MRQC_RSS_FIELD_IPV4 |
2366 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2367 E1000_MRQC_RSS_FIELD_IPV6_EX |
2368 E1000_MRQC_RSS_FIELD_IPV6);
2373 igb_initialize_rss_mapping(struct adapter *adapter)
2375 struct e1000_hw *hw = &adapter->hw;
2379 u32 rss_key[10], mrqc, shift = 0;
2382 if (adapter->hw.mac.type == e1000_82575)
2386 * The redirection table controls which destination
2387 * queue each bucket redirects traffic to.
2388 * Each DWORD represents four queues, with the LSB
2389 * being the first queue in the DWORD.
2391 * This just allocates buckets to queues using round-robin
2394 * NOTE: It Just Happens to line up with the default
2395 * RSS allocation method.
2398 /* Warning FM follows */
2400 for (i = 0; i < 128; i++) {
2402 queue_id = rss_get_indirection_to_bucket(i);
2404 * If we have more queues than buckets, we'll
2405 * end up mapping buckets to a subset of the
2408 * If we have more buckets than queues, we'll
2409 * end up instead assigning multiple buckets
2412 * Both are suboptimal, but we need to handle
2413 * the case so we don't go out of bounds
2414 * indexing arrays and such.
2416 queue_id = queue_id % adapter->rx_num_queues;
2418 queue_id = (i % adapter->rx_num_queues);
2420 /* Adjust if required */
2421 queue_id = queue_id << shift;
2424 * The low 8 bits are for hash value (n+0);
2425 * The next 8 bits are for hash value (n+1), etc.
2428 reta = reta | ( ((uint32_t) queue_id) << 24);
2430 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2435 /* Now fill in hash table */
2438 * MRQC: Multiple Receive Queues Command
2439 * Set queuing to RSS control, number depends on the device.
2441 mrqc = E1000_MRQC_ENABLE_RSS_8Q;
2444 /* XXX ew typecasting */
2445 rss_getkey((uint8_t *) &rss_key);
2447 arc4rand(&rss_key, sizeof(rss_key), 0);
2449 for (i = 0; i < 10; i++)
2450 E1000_WRITE_REG_ARRAY(hw,
2451 E1000_RSSRK(0), i, rss_key[i]);
2454 * Configure the RSS fields to hash upon.
2456 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2457 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2458 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2459 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2460 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2461 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2462 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2463 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2465 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2468 /*********************************************************************
2470 * Setup networking device structure and register an interface.
2472 **********************************************************************/
2474 em_setup_interface(if_ctx_t ctx)
2476 struct ifnet *ifp = iflib_get_ifp(ctx);
2477 struct adapter *adapter = iflib_get_softc(ctx);
2478 if_softc_ctx_t scctx = adapter->shared;
2481 INIT_DEBUGOUT("em_setup_interface: begin");
2483 /* TSO parameters */
2484 if_sethwtsomax(ifp, IP_MAXPACKET);
2485 /* Take m_pullup(9)'s in em_xmit() w/ TSO into acount. */
2486 if_sethwtsomaxsegcount(ifp, EM_MAX_SCATTER - 5);
2487 if_sethwtsomaxsegsize(ifp, EM_TSO_SEG_SIZE);
2490 if (adapter->tx_num_queues == 1) {
2491 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
2492 if_setsendqready(ifp);
2495 cap = IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4;
2496 cap |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU;
2499 * Tell the upper layer(s) we
2500 * support full VLAN capability
2502 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
2503 if_setcapabilitiesbit(ifp, cap, 0);
2506 ** Don't turn this on by default, if vlans are
2507 ** created on another pseudo device (eg. lagg)
2508 ** then vlan events are not passed thru, breaking
2509 ** operation, but with HW FILTER off it works. If
2510 ** using vlans directly on the em driver you can
2511 ** enable this and get full hardware tag filtering.
2513 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWFILTER,0);
2515 /* Enable only WOL MAGIC by default */
2517 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC,
2518 IFCAP_WOL_MCAST| IFCAP_WOL_UCAST);
2520 if_setcapenablebit(ifp, 0, IFCAP_WOL_MAGIC |
2521 IFCAP_WOL_MCAST| IFCAP_WOL_UCAST);
2525 * Specify the media types supported by this adapter and register
2526 * callbacks to update media and link information
2528 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
2529 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
2530 u_char fiber_type = IFM_1000_SX; /* default type */
2532 if (adapter->hw.mac.type == e1000_82545)
2533 fiber_type = IFM_1000_LX;
2534 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
2535 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2537 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2538 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2539 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2540 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2541 if (adapter->hw.phy.type != e1000_phy_ife) {
2542 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2543 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2546 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2547 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO);
2552 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
2554 struct adapter *adapter = iflib_get_softc(ctx);
2555 if_softc_ctx_t scctx = adapter->shared;
2556 int error = E1000_SUCCESS;
2557 struct em_tx_queue *que;
2560 MPASS(adapter->tx_num_queues > 0);
2561 MPASS(adapter->tx_num_queues == ntxqsets);
2563 /* First allocate the top level queue structs */
2564 if (!(adapter->tx_queues =
2565 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
2566 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2567 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2571 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) {
2572 /* Set up some basics */
2573 struct tx_ring *txr = &que->txr;
2574 txr->adapter = que->adapter = adapter;
2576 que->me = txr->me = i;
2578 /* Allocate transmit buffer memory */
2579 if (!(txr->tx_buffers = (struct em_txbuffer *) malloc(sizeof(struct em_txbuffer) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2580 device_printf(iflib_get_dev(ctx), "failed to allocate tx_buffer memory\n");
2585 /* get the virtual and physical address of the hardware queues */
2586 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
2587 txr->tx_paddr = paddrs[i*ntxqs];
2591 device_printf(iflib_get_dev(ctx), "allocated for %d tx_queues\n", adapter->tx_num_queues);
2594 em_if_queues_free(ctx);
2599 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
2601 struct adapter *adapter = iflib_get_softc(ctx);
2602 int error = E1000_SUCCESS;
2603 struct em_rx_queue *que;
2606 MPASS(adapter->rx_num_queues > 0);
2607 MPASS(adapter->rx_num_queues == nrxqsets);
2609 /* First allocate the top level queue structs */
2610 if (!(adapter->rx_queues =
2611 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
2612 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2613 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2618 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) {
2619 /* Set up some basics */
2620 struct rx_ring *rxr = &que->rxr;
2621 rxr->adapter = que->adapter = adapter;
2623 que->me = rxr->me = i;
2625 /* get the virtual and physical address of the hardware queues */
2626 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
2627 rxr->rx_paddr = paddrs[i*nrxqs];
2630 device_printf(iflib_get_dev(ctx), "allocated for %d rx_queues\n", adapter->rx_num_queues);
2634 em_if_queues_free(ctx);
2639 em_if_queues_free(if_ctx_t ctx)
2641 struct adapter *adapter = iflib_get_softc(ctx);
2642 struct em_tx_queue *tx_que = adapter->tx_queues;
2643 struct em_rx_queue *rx_que = adapter->rx_queues;
2645 if (tx_que != NULL) {
2646 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
2647 struct tx_ring *txr = &tx_que->txr;
2648 if (txr->tx_buffers == NULL)
2651 free(txr->tx_buffers, M_DEVBUF);
2652 txr->tx_buffers = NULL;
2654 free(adapter->tx_queues, M_DEVBUF);
2655 adapter->tx_queues = NULL;
2658 if (rx_que != NULL) {
2659 free(adapter->rx_queues, M_DEVBUF);
2660 adapter->rx_queues = NULL;
2663 em_release_hw_control(adapter);
2665 if (adapter->mta != NULL) {
2666 free(adapter->mta, M_DEVBUF);
2670 /*********************************************************************
2672 * Enable transmit unit.
2674 **********************************************************************/
2676 em_initialize_transmit_unit(if_ctx_t ctx)
2678 struct adapter *adapter = iflib_get_softc(ctx);
2679 if_softc_ctx_t scctx = adapter->shared;
2680 struct em_tx_queue *que;
2681 struct tx_ring *txr;
2682 struct e1000_hw *hw = &adapter->hw;
2683 u32 tctl, txdctl = 0, tarc, tipg = 0;
2685 INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
2687 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
2691 que = &adapter->tx_queues[i];
2693 bus_addr = txr->tx_paddr;
2695 /*Enable all queues */
2696 em_init_tx_ring(que);
2698 /* Clear checksum offload context. */
2699 offp = (caddr_t)&txr->csum_flags;
2700 endp = (caddr_t)(txr + 1);
2701 bzero(offp, endp - offp);
2703 /* Base and Len of TX Ring */
2704 E1000_WRITE_REG(hw, E1000_TDLEN(i),
2705 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
2706 E1000_WRITE_REG(hw, E1000_TDBAH(i),
2707 (u32)(bus_addr >> 32));
2708 E1000_WRITE_REG(hw, E1000_TDBAL(i),
2710 /* Init the HEAD/TAIL indices */
2711 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
2712 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
2714 HW_DEBUGOUT2("Base = %x, Length = %x\n",
2715 E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)),
2716 E1000_READ_REG(&adapter->hw, E1000_TDLEN(i)));
2718 txdctl = 0; /* clear txdctl */
2719 txdctl |= 0x1f; /* PTHRESH */
2720 txdctl |= 1 << 8; /* HTHRESH */
2721 txdctl |= 1 << 16;/* WTHRESH */
2722 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
2723 txdctl |= E1000_TXDCTL_GRAN;
2724 txdctl |= 1 << 25; /* LWTHRESH */
2726 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
2729 /* Set the default values for the Tx Inter Packet Gap timer */
2730 switch (adapter->hw.mac.type) {
2731 case e1000_80003es2lan:
2732 tipg = DEFAULT_82543_TIPG_IPGR1;
2733 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2734 E1000_TIPG_IPGR2_SHIFT;
2737 tipg = DEFAULT_82542_TIPG_IPGT;
2738 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2739 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2742 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
2743 (adapter->hw.phy.media_type ==
2744 e1000_media_type_internal_serdes))
2745 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2747 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2748 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2749 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2752 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
2753 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value);
2755 if(adapter->hw.mac.type >= e1000_82540)
2756 E1000_WRITE_REG(&adapter->hw, E1000_TADV,
2757 adapter->tx_abs_int_delay.value);
2759 if ((adapter->hw.mac.type == e1000_82571) ||
2760 (adapter->hw.mac.type == e1000_82572)) {
2761 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2762 tarc |= TARC_SPEED_MODE_BIT;
2763 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2764 } else if (adapter->hw.mac.type == e1000_80003es2lan) {
2765 /* errata: program both queues to unweighted RR */
2766 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2768 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2769 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
2771 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
2772 } else if (adapter->hw.mac.type == e1000_82574) {
2773 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2774 tarc |= TARC_ERRATA_BIT;
2775 if ( adapter->tx_num_queues > 1) {
2776 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
2777 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2778 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
2780 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2783 if (adapter->tx_int_delay.value > 0)
2784 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2786 /* Program the Transmit Control Register */
2787 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
2788 tctl &= ~E1000_TCTL_CT;
2789 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2790 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
2792 if (adapter->hw.mac.type >= e1000_82571)
2793 tctl |= E1000_TCTL_MULR;
2795 /* This write will effectively turn on the transmit unit. */
2796 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
2798 if (hw->mac.type == e1000_pch_spt) {
2800 reg = E1000_READ_REG(hw, E1000_IOSFPC);
2801 reg |= E1000_RCTL_RDMTS_HEX;
2802 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
2803 reg = E1000_READ_REG(hw, E1000_TARC(0));
2804 reg |= E1000_TARC0_CB_MULTIQ_3_REQ;
2805 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
2809 /*********************************************************************
2811 * Enable receive unit.
2813 **********************************************************************/
2816 em_initialize_receive_unit(if_ctx_t ctx)
2818 struct adapter *adapter = iflib_get_softc(ctx);
2819 if_softc_ctx_t scctx = adapter->shared;
2820 struct ifnet *ifp = iflib_get_ifp(ctx);
2821 struct e1000_hw *hw = &adapter->hw;
2822 struct em_rx_queue *que;
2824 u32 rctl, rxcsum, rfctl;
2826 INIT_DEBUGOUT("em_initialize_receive_units: begin");
2829 * Make sure receives are disabled while setting
2830 * up the descriptor ring
2832 rctl = E1000_READ_REG(hw, E1000_RCTL);
2833 /* Do not disable if ever enabled on this hardware */
2834 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
2835 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2837 /* Setup the Receive Control Register */
2838 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2839 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
2840 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
2841 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2843 /* Do not store bad packets */
2844 rctl &= ~E1000_RCTL_SBP;
2846 /* Enable Long Packet receive */
2847 if (if_getmtu(ifp) > ETHERMTU)
2848 rctl |= E1000_RCTL_LPE;
2850 rctl &= ~E1000_RCTL_LPE;
2853 if (!em_disable_crc_stripping)
2854 rctl |= E1000_RCTL_SECRC;
2856 if (adapter->hw.mac.type >= e1000_82540) {
2857 E1000_WRITE_REG(&adapter->hw, E1000_RADV,
2858 adapter->rx_abs_int_delay.value);
2861 * Set the interrupt throttling rate. Value is calculated
2862 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
2864 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
2866 E1000_WRITE_REG(&adapter->hw, E1000_RDTR,
2867 adapter->rx_int_delay.value);
2869 /* Use extended rx descriptor formats */
2870 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2871 rfctl |= E1000_RFCTL_EXTEN;
2873 ** When using MSIX interrupts we need to throttle
2874 ** using the EITR register (82574 only)
2876 if (hw->mac.type == e1000_82574) {
2877 for (int i = 0; i < 4; i++)
2878 E1000_WRITE_REG(hw, E1000_EITR_82574(i),
2880 /* Disable accelerated acknowledge */
2881 rfctl |= E1000_RFCTL_ACK_DIS;
2883 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2885 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2886 if (if_getcapenable(ifp) & IFCAP_RXCSUM &&
2887 adapter->hw.mac.type >= e1000_82543) {
2888 if (adapter->tx_num_queues > 1) {
2889 if (adapter->hw.mac.type >= igb_mac_min) {
2890 rxcsum |= E1000_RXCSUM_PCSD;
2891 if (hw->mac.type != e1000_82575)
2892 rxcsum |= E1000_RXCSUM_CRCOFL;
2894 rxcsum |= E1000_RXCSUM_TUOFL |
2895 E1000_RXCSUM_IPOFL |
2898 if (adapter->hw.mac.type >= igb_mac_min)
2899 rxcsum |= E1000_RXCSUM_IPPCSE;
2901 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
2902 if (adapter->hw.mac.type > e1000_82575)
2903 rxcsum |= E1000_RXCSUM_CRCOFL;
2906 rxcsum &= ~E1000_RXCSUM_TUOFL;
2908 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2910 if (adapter->rx_num_queues > 1) {
2911 if (adapter->hw.mac.type >= igb_mac_min)
2912 igb_initialize_rss_mapping(adapter);
2914 em_initialize_rss_mapping(adapter);
2918 ** XXX TEMPORARY WORKAROUND: on some systems with 82573
2919 ** long latencies are observed, like Lenovo X60. This
2920 ** change eliminates the problem, but since having positive
2921 ** values in RDTR is a known source of problems on other
2922 ** platforms another solution is being sought.
2924 if (hw->mac.type == e1000_82573)
2925 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
2927 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
2928 struct rx_ring *rxr = &que->rxr;
2929 /* Setup the Base and Length of the Rx Descriptor Ring */
2930 u64 bus_addr = rxr->rx_paddr;
2932 u32 rdt = adapter->rx_num_queues -1; /* default */
2935 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2936 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
2937 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
2938 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
2939 /* Setup the Head and Tail Descriptor Pointers */
2940 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
2941 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
2945 * Set PTHRESH for improved jumbo performance
2946 * According to 10.2.5.11 of Intel 82574 Datasheet,
2947 * RXDCTL(1) is written whenever RXDCTL(0) is written.
2948 * Only write to RXDCTL(1) if there is a need for different
2952 if (((adapter->hw.mac.type == e1000_ich9lan) ||
2953 (adapter->hw.mac.type == e1000_pch2lan) ||
2954 (adapter->hw.mac.type == e1000_ich10lan)) &&
2955 (if_getmtu(ifp) > ETHERMTU)) {
2956 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
2957 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
2958 } else if (adapter->hw.mac.type == e1000_82574) {
2959 for (int i = 0; i < adapter->rx_num_queues; i++) {
2960 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2961 rxdctl |= 0x20; /* PTHRESH */
2962 rxdctl |= 4 << 8; /* HTHRESH */
2963 rxdctl |= 4 << 16;/* WTHRESH */
2964 rxdctl |= 1 << 24; /* Switch to granularity */
2965 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2967 } else if (adapter->hw.mac.type >= igb_mac_min) {
2968 u32 psize, srrctl = 0;
2970 if (ifp->if_mtu > ETHERMTU) {
2971 rctl |= E1000_RCTL_LPE;
2973 /* Set maximum packet len */
2974 psize = scctx->isc_max_frame_size;
2975 if (psize <= 4096) {
2976 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2977 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2978 } else if (psize > 4096) {
2979 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2980 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2983 /* are we on a vlan? */
2984 if (ifp->if_vlantrunk != NULL)
2985 psize += VLAN_TAG_SIZE;
2986 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2988 rctl &= ~E1000_RCTL_LPE;
2989 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2990 rctl |= E1000_RCTL_SZ_2048;
2994 * If TX flow control is disabled and there's >1 queue defined,
2997 * This drops frames rather than hanging the RX MAC for all queues.
2999 if ((adapter->rx_num_queues > 1) &&
3000 (adapter->fc == e1000_fc_none ||
3001 adapter->fc == e1000_fc_rx_pause)) {
3002 srrctl |= E1000_SRRCTL_DROP_EN;
3004 /* Setup the Base and Length of the Rx Descriptor Rings */
3005 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3006 struct rx_ring *rxr = &que->rxr;
3007 u64 bus_addr = rxr->rx_paddr;
3011 /* Configure for header split? -- ignore for now */
3012 rxr->hdr_split = igb_header_split;
3014 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3018 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3019 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3020 E1000_WRITE_REG(hw, E1000_RDBAH(i),
3021 (uint32_t)(bus_addr >> 32));
3022 E1000_WRITE_REG(hw, E1000_RDBAL(i),
3023 (uint32_t)bus_addr);
3024 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3025 /* Enable this Queue */
3026 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3027 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3028 rxdctl &= 0xFFF00000;
3029 rxdctl |= IGB_RX_PTHRESH;
3030 rxdctl |= IGB_RX_HTHRESH << 8;
3031 rxdctl |= IGB_RX_WTHRESH << 16;
3032 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3035 if (adapter->hw.mac.type >= e1000_pch2lan) {
3036 if (if_getmtu(ifp) > ETHERMTU)
3037 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
3039 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
3042 /* Make sure VLAN Filters are off */
3043 rctl &= ~E1000_RCTL_VFE;
3045 if (adapter->rx_mbuf_sz == MCLBYTES)
3046 rctl |= E1000_RCTL_SZ_2048;
3047 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE)
3048 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3049 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE)
3050 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3052 /* ensure we clear use DTYPE of 00 here */
3053 rctl &= ~0x00000C00;
3054 /* Write out the settings */
3055 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3061 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3063 struct adapter *adapter = iflib_get_softc(ctx);
3066 index = (vtag >> 5) & 0x7F;
3068 adapter->shadow_vfta[index] |= (1 << bit);
3069 ++adapter->num_vlans;
3073 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3075 struct adapter *adapter = iflib_get_softc(ctx);
3078 index = (vtag >> 5) & 0x7F;
3080 adapter->shadow_vfta[index] &= ~(1 << bit);
3081 --adapter->num_vlans;
3085 em_setup_vlan_hw_support(struct adapter *adapter)
3087 struct e1000_hw *hw = &adapter->hw;
3091 ** We get here thru init_locked, meaning
3092 ** a soft reset, this has already cleared
3093 ** the VFTA and other state, so if there
3094 ** have been no vlan's registered do nothing.
3096 if (adapter->num_vlans == 0)
3100 ** A soft reset zero's out the VFTA, so
3101 ** we need to repopulate it now.
3103 for (int i = 0; i < EM_VFTA_SIZE; i++)
3104 if (adapter->shadow_vfta[i] != 0)
3105 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
3106 i, adapter->shadow_vfta[i]);
3108 reg = E1000_READ_REG(hw, E1000_CTRL);
3109 reg |= E1000_CTRL_VME;
3110 E1000_WRITE_REG(hw, E1000_CTRL, reg);
3112 /* Enable the Filter Table */
3113 reg = E1000_READ_REG(hw, E1000_RCTL);
3114 reg &= ~E1000_RCTL_CFIEN;
3115 reg |= E1000_RCTL_VFE;
3116 E1000_WRITE_REG(hw, E1000_RCTL, reg);
3120 em_if_enable_intr(if_ctx_t ctx)
3122 struct adapter *adapter = iflib_get_softc(ctx);
3123 struct e1000_hw *hw = &adapter->hw;
3124 u32 ims_mask = IMS_ENABLE_MASK;
3126 if (hw->mac.type == e1000_82574) {
3127 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK);
3128 ims_mask |= adapter->ims;
3129 } if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min) {
3130 u32 mask = (adapter->que_mask | adapter->link_mask);
3132 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask);
3133 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask);
3134 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask);
3135 ims_mask = E1000_IMS_LSC;
3138 E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3142 em_if_disable_intr(if_ctx_t ctx)
3144 struct adapter *adapter = iflib_get_softc(ctx);
3145 struct e1000_hw *hw = &adapter->hw;
3147 if (adapter->intr_type == IFLIB_INTR_MSIX) {
3148 if (hw->mac.type >= igb_mac_min)
3149 E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0);
3150 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0);
3152 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
3156 * Bit of a misnomer, what this really means is
3157 * to enable OS management of the system... aka
3158 * to disable special hardware management features
3161 em_init_manageability(struct adapter *adapter)
3163 /* A shared code workaround */
3164 #define E1000_82542_MANC2H E1000_MANC2H
3165 if (adapter->has_manage) {
3166 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3167 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3169 /* disable hardware interception of ARP */
3170 manc &= ~(E1000_MANC_ARP_EN);
3172 /* enable receiving management packets to the host */
3173 manc |= E1000_MANC_EN_MNG2HOST;
3174 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3175 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3176 manc2h |= E1000_MNG2HOST_PORT_623;
3177 manc2h |= E1000_MNG2HOST_PORT_664;
3178 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3179 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3184 * Give control back to hardware management
3185 * controller if there is one.
3188 em_release_manageability(struct adapter *adapter)
3190 if (adapter->has_manage) {
3191 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3193 /* re-enable hardware interception of ARP */
3194 manc |= E1000_MANC_ARP_EN;
3195 manc &= ~E1000_MANC_EN_MNG2HOST;
3197 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3202 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3203 * For ASF and Pass Through versions of f/w this means
3204 * that the driver is loaded. For AMT version type f/w
3205 * this means that the network i/f is open.
3208 em_get_hw_control(struct adapter *adapter)
3212 if (adapter->hw.mac.type == e1000_82573) {
3213 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3214 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3215 swsm | E1000_SWSM_DRV_LOAD);
3219 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3220 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3221 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3226 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3227 * For ASF and Pass Through versions of f/w this means that
3228 * the driver is no longer loaded. For AMT versions of the
3229 * f/w this means that the network i/f is closed.
3232 em_release_hw_control(struct adapter *adapter)
3236 if (!adapter->has_manage)
3239 if (adapter->hw.mac.type == e1000_82573) {
3240 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3241 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3242 swsm & ~E1000_SWSM_DRV_LOAD);
3246 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3247 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3248 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3253 em_is_valid_ether_addr(u8 *addr)
3255 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3257 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3265 ** Parse the interface capabilities with regard
3266 ** to both system management and wake-on-lan for
3270 em_get_wakeup(if_ctx_t ctx)
3272 struct adapter *adapter = iflib_get_softc(ctx);
3273 device_t dev = iflib_get_dev(ctx);
3274 u16 eeprom_data = 0, device_id, apme_mask;
3276 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
3277 apme_mask = EM_EEPROM_APME;
3279 switch (adapter->hw.mac.type) {
3284 e1000_read_nvm(&adapter->hw,
3285 NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3286 apme_mask = EM_82544_APME;
3289 case e1000_82546_rev_3:
3290 if (adapter->hw.bus.func == 1) {
3291 e1000_read_nvm(&adapter->hw,
3292 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3295 e1000_read_nvm(&adapter->hw,
3296 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3300 adapter->has_amt = TRUE;
3304 case e1000_80003es2lan:
3305 if (adapter->hw.bus.func == 1) {
3306 e1000_read_nvm(&adapter->hw,
3307 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3310 e1000_read_nvm(&adapter->hw,
3311 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3315 case e1000_ich10lan:
3320 case e1000_82575: /* listing all igb devices */
3328 case e1000_vfadapt_i350:
3329 apme_mask = E1000_WUC_APME;
3330 adapter->has_amt = TRUE;
3331 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
3334 e1000_read_nvm(&adapter->hw,
3335 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3338 if (eeprom_data & apme_mask)
3339 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
3341 * We have the eeprom settings, now apply the special cases
3342 * where the eeprom may be wrong or the board won't support
3343 * wake on lan on a particular port
3345 device_id = pci_get_device(dev);
3346 switch (device_id) {
3347 case E1000_DEV_ID_82546GB_PCIE:
3350 case E1000_DEV_ID_82546EB_FIBER:
3351 case E1000_DEV_ID_82546GB_FIBER:
3352 /* Wake events only supported on port A for dual fiber
3353 * regardless of eeprom setting */
3354 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3355 E1000_STATUS_FUNC_1)
3358 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
3359 /* if quad port adapter, disable WoL on all but port A */
3360 if (global_quad_port_a != 0)
3362 /* Reset for multiple quad port adapters */
3363 if (++global_quad_port_a == 4)
3364 global_quad_port_a = 0;
3366 case E1000_DEV_ID_82571EB_FIBER:
3367 /* Wake events only supported on port A for dual fiber
3368 * regardless of eeprom setting */
3369 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3370 E1000_STATUS_FUNC_1)
3373 case E1000_DEV_ID_82571EB_QUAD_COPPER:
3374 case E1000_DEV_ID_82571EB_QUAD_FIBER:
3375 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
3376 /* if quad port adapter, disable WoL on all but port A */
3377 if (global_quad_port_a != 0)
3379 /* Reset for multiple quad port adapters */
3380 if (++global_quad_port_a == 4)
3381 global_quad_port_a = 0;
3389 * Enable PCI Wake On Lan capability
3392 em_enable_wakeup(if_ctx_t ctx)
3394 struct adapter *adapter = iflib_get_softc(ctx);
3395 device_t dev = iflib_get_dev(ctx);
3396 if_t ifp = iflib_get_ifp(ctx);
3397 u32 pmc, ctrl, ctrl_ext, rctl, wuc;
3400 if ((pci_find_cap(dev, PCIY_PMG, &pmc) != 0))
3403 /* Advertise the wakeup capability */
3404 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
3405 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
3406 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
3407 wuc = E1000_READ_REG(&adapter->hw, E1000_WUC);
3408 wuc |= (E1000_WUC_PME_EN | E1000_WUC_APME);
3409 E1000_WRITE_REG(&adapter->hw, E1000_WUC, wuc);
3411 if ((adapter->hw.mac.type == e1000_ich8lan) ||
3412 (adapter->hw.mac.type == e1000_pchlan) ||
3413 (adapter->hw.mac.type == e1000_ich9lan) ||
3414 (adapter->hw.mac.type == e1000_ich10lan))
3415 e1000_suspend_workarounds_ich8lan(&adapter->hw);
3417 /* Keep the laser running on Fiber adapters */
3418 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3419 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
3420 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3421 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
3422 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext);
3426 ** Determine type of Wakeup: note that wol
3427 ** is set with all bits on by default.
3429 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
3430 adapter->wol &= ~E1000_WUFC_MAG;
3432 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
3433 adapter->wol &= ~E1000_WUFC_EX;
3435 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
3436 adapter->wol &= ~E1000_WUFC_MC;
3438 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3439 rctl |= E1000_RCTL_MPE;
3440 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3443 if ( adapter->hw.mac.type >= e1000_pchlan) {
3444 if (em_enable_phy_wakeup(adapter))
3447 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
3448 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
3451 if (adapter->hw.phy.type == e1000_phy_igp_3)
3452 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
3455 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
3456 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3457 if (if_getcapenable(ifp) & IFCAP_WOL)
3458 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3459 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
3465 ** WOL in the newer chipset interfaces (pchlan)
3466 ** require thing to be copied into the phy
3469 em_enable_phy_wakeup(struct adapter *adapter)
3471 struct e1000_hw *hw = &adapter->hw;
3475 /* copy MAC RARs to PHY RARs */
3476 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
3478 /* copy MAC MTA to PHY MTA */
3479 for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
3480 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
3481 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
3482 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
3483 (u16)((mreg >> 16) & 0xFFFF));
3486 /* configure PHY Rx Control register */
3487 e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg);
3488 mreg = E1000_READ_REG(hw, E1000_RCTL);
3489 if (mreg & E1000_RCTL_UPE)
3490 preg |= BM_RCTL_UPE;
3491 if (mreg & E1000_RCTL_MPE)
3492 preg |= BM_RCTL_MPE;
3493 preg &= ~(BM_RCTL_MO_MASK);
3494 if (mreg & E1000_RCTL_MO_3)
3495 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
3496 << BM_RCTL_MO_SHIFT);
3497 if (mreg & E1000_RCTL_BAM)
3498 preg |= BM_RCTL_BAM;
3499 if (mreg & E1000_RCTL_PMCF)
3500 preg |= BM_RCTL_PMCF;
3501 mreg = E1000_READ_REG(hw, E1000_CTRL);
3502 if (mreg & E1000_CTRL_RFCE)
3503 preg |= BM_RCTL_RFCE;
3504 e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg);
3506 /* enable PHY wakeup in MAC register */
3507 E1000_WRITE_REG(hw, E1000_WUC,
3508 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
3509 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol);
3511 /* configure and enable PHY wakeup in PHY registers */
3512 e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol);
3513 e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
3515 /* activate PHY wakeup */
3516 ret = hw->phy.ops.acquire(hw);
3518 printf("Could not acquire PHY\n");
3521 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3522 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3523 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
3525 printf("Could not read PHY page 769\n");
3528 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
3529 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
3531 printf("Could not set PHY Host Wakeup bit\n");
3533 hw->phy.ops.release(hw);
3539 em_if_led_func(if_ctx_t ctx, int onoff)
3541 struct adapter *adapter = iflib_get_softc(ctx);
3544 e1000_setup_led(&adapter->hw);
3545 e1000_led_on(&adapter->hw);
3547 e1000_led_off(&adapter->hw);
3548 e1000_cleanup_led(&adapter->hw);
3553 ** Disable the L0S and L1 LINK states
3556 em_disable_aspm(struct adapter *adapter)
3559 u16 link_cap,link_ctrl;
3560 device_t dev = adapter->dev;
3562 switch (adapter->hw.mac.type) {
3570 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
3572 reg = base + PCIER_LINK_CAP;
3573 link_cap = pci_read_config(dev, reg, 2);
3574 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
3576 reg = base + PCIER_LINK_CTL;
3577 link_ctrl = pci_read_config(dev, reg, 2);
3578 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
3579 pci_write_config(dev, reg, link_ctrl, 2);
3583 /**********************************************************************
3585 * Update the board statistics counters.
3587 **********************************************************************/
3589 em_update_stats_counters(struct adapter *adapter)
3592 if(adapter->hw.phy.media_type == e1000_media_type_copper ||
3593 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3594 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
3595 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
3597 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
3598 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
3599 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
3600 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
3602 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
3603 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
3604 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
3605 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
3606 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
3607 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
3608 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
3609 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
3610 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
3611 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
3612 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
3613 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
3614 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
3615 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
3616 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
3617 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
3618 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
3619 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
3620 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
3621 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
3623 /* For the 64-bit byte counters the low dword must be read first. */
3624 /* Both registers clear on the read of the high dword */
3626 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) +
3627 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32);
3628 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) +
3629 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32);
3631 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
3632 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
3633 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
3634 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
3635 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
3637 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
3638 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
3640 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
3641 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
3642 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
3643 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
3644 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
3645 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
3646 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
3647 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
3648 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
3649 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
3651 /* Interrupt Counts */
3653 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC);
3654 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC);
3655 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC);
3656 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC);
3657 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC);
3658 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC);
3659 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC);
3660 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC);
3661 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC);
3663 if (adapter->hw.mac.type >= e1000_82543) {
3664 adapter->stats.algnerrc +=
3665 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
3666 adapter->stats.rxerrc +=
3667 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
3668 adapter->stats.tncrs +=
3669 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
3670 adapter->stats.cexterr +=
3671 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
3672 adapter->stats.tsctc +=
3673 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
3674 adapter->stats.tsctfc +=
3675 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
3680 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
3682 struct adapter *adapter = iflib_get_softc(ctx);
3683 struct ifnet *ifp = iflib_get_ifp(ctx);
3686 case IFCOUNTER_COLLISIONS:
3687 return (adapter->stats.colc);
3688 case IFCOUNTER_IERRORS:
3689 return (adapter->dropped_pkts + adapter->stats.rxerrc +
3690 adapter->stats.crcerrs + adapter->stats.algnerrc +
3691 adapter->stats.ruc + adapter->stats.roc +
3692 adapter->stats.mpc + adapter->stats.cexterr);
3693 case IFCOUNTER_OERRORS:
3694 return (adapter->stats.ecol + adapter->stats.latecol +
3695 adapter->watchdog_events);
3697 return (if_get_counter_default(ifp, cnt));
3701 /* Export a single 32-bit register via a read-only sysctl. */
3703 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
3705 struct adapter *adapter;
3708 adapter = oidp->oid_arg1;
3709 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2);
3710 return (sysctl_handle_int(oidp, &val, 0, req));
3714 * Add sysctl variables, one per statistic, to the system.
3717 em_add_hw_stats(struct adapter *adapter)
3719 device_t dev = iflib_get_dev(adapter->ctx);
3720 struct em_tx_queue *tx_que = adapter->tx_queues;
3721 struct em_rx_queue *rx_que = adapter->rx_queues;
3723 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
3724 struct sysctl_oid *tree = device_get_sysctl_tree(dev);
3725 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
3726 struct e1000_hw_stats *stats = &adapter->stats;
3728 struct sysctl_oid *stat_node, *queue_node, *int_node;
3729 struct sysctl_oid_list *stat_list, *queue_list, *int_list;
3731 #define QUEUE_NAME_LEN 32
3732 char namebuf[QUEUE_NAME_LEN];
3734 /* Driver Statistics */
3735 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
3736 CTLFLAG_RD, &adapter->dropped_pkts,
3737 "Driver dropped packets");
3738 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
3739 CTLFLAG_RD, &adapter->link_irq,
3740 "Link MSIX IRQ Handled");
3741 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "mbuf_defrag_fail",
3742 CTLFLAG_RD, &adapter->mbuf_defrag_failed,
3743 "Defragmenting mbuf chain failed");
3744 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "tx_dma_fail",
3745 CTLFLAG_RD, &adapter->no_tx_dma_setup,
3746 "Driver tx dma failure in xmit");
3747 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
3748 CTLFLAG_RD, &adapter->rx_overruns,
3750 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
3751 CTLFLAG_RD, &adapter->watchdog_events,
3752 "Watchdog timeouts");
3754 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
3755 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL,
3756 em_sysctl_reg_handler, "IU",
3757 "Device Control Register");
3758 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
3759 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL,
3760 em_sysctl_reg_handler, "IU",
3761 "Receiver Control Register");
3762 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
3763 CTLFLAG_RD, &adapter->hw.fc.high_water, 0,
3764 "Flow Control High Watermark");
3765 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
3766 CTLFLAG_RD, &adapter->hw.fc.low_water, 0,
3767 "Flow Control Low Watermark");
3769 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
3770 struct tx_ring *txr = &tx_que->txr;
3771 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
3772 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
3773 CTLFLAG_RD, NULL, "TX Queue Name");
3774 queue_list = SYSCTL_CHILDREN(queue_node);
3776 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
3777 CTLTYPE_UINT | CTLFLAG_RD, adapter,
3779 em_sysctl_reg_handler, "IU",
3780 "Transmit Descriptor Head");
3781 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
3782 CTLTYPE_UINT | CTLFLAG_RD, adapter,
3784 em_sysctl_reg_handler, "IU",
3785 "Transmit Descriptor Tail");
3786 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
3787 CTLFLAG_RD, &txr->tx_irq,
3788 "Queue MSI-X Transmit Interrupts");
3789 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "no_desc_avail",
3790 CTLFLAG_RD, &txr->no_desc_avail,
3791 "Queue No Descriptor Available");
3794 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) {
3795 struct rx_ring *rxr = &rx_que->rxr;
3796 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
3797 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
3798 CTLFLAG_RD, NULL, "RX Queue Name");
3799 queue_list = SYSCTL_CHILDREN(queue_node);
3801 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
3802 CTLTYPE_UINT | CTLFLAG_RD, adapter,
3804 em_sysctl_reg_handler, "IU",
3805 "Receive Descriptor Head");
3806 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
3807 CTLTYPE_UINT | CTLFLAG_RD, adapter,
3809 em_sysctl_reg_handler, "IU",
3810 "Receive Descriptor Tail");
3811 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
3812 CTLFLAG_RD, &rxr->rx_irq,
3813 "Queue MSI-X Receive Interrupts");
3816 /* MAC stats get their own sub node */
3818 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
3819 CTLFLAG_RD, NULL, "Statistics");
3820 stat_list = SYSCTL_CHILDREN(stat_node);
3822 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
3823 CTLFLAG_RD, &stats->ecol,
3824 "Excessive collisions");
3825 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
3826 CTLFLAG_RD, &stats->scc,
3827 "Single collisions");
3828 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
3829 CTLFLAG_RD, &stats->mcc,
3830 "Multiple collisions");
3831 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
3832 CTLFLAG_RD, &stats->latecol,
3834 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
3835 CTLFLAG_RD, &stats->colc,
3837 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
3838 CTLFLAG_RD, &adapter->stats.symerrs,
3840 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
3841 CTLFLAG_RD, &adapter->stats.sec,
3843 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
3844 CTLFLAG_RD, &adapter->stats.dc,
3846 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
3847 CTLFLAG_RD, &adapter->stats.mpc,
3849 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
3850 CTLFLAG_RD, &adapter->stats.rnbc,
3851 "Receive No Buffers");
3852 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
3853 CTLFLAG_RD, &adapter->stats.ruc,
3854 "Receive Undersize");
3855 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
3856 CTLFLAG_RD, &adapter->stats.rfc,
3857 "Fragmented Packets Received ");
3858 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
3859 CTLFLAG_RD, &adapter->stats.roc,
3860 "Oversized Packets Received");
3861 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
3862 CTLFLAG_RD, &adapter->stats.rjc,
3864 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
3865 CTLFLAG_RD, &adapter->stats.rxerrc,
3867 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
3868 CTLFLAG_RD, &adapter->stats.crcerrs,
3870 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
3871 CTLFLAG_RD, &adapter->stats.algnerrc,
3872 "Alignment Errors");
3873 /* On 82575 these are collision counts */
3874 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
3875 CTLFLAG_RD, &adapter->stats.cexterr,
3876 "Collision/Carrier extension errors");
3877 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
3878 CTLFLAG_RD, &adapter->stats.xonrxc,
3880 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
3881 CTLFLAG_RD, &adapter->stats.xontxc,
3883 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
3884 CTLFLAG_RD, &adapter->stats.xoffrxc,
3886 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
3887 CTLFLAG_RD, &adapter->stats.xofftxc,
3888 "XOFF Transmitted");
3890 /* Packet Reception Stats */
3891 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
3892 CTLFLAG_RD, &adapter->stats.tpr,
3893 "Total Packets Received ");
3894 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
3895 CTLFLAG_RD, &adapter->stats.gprc,
3896 "Good Packets Received");
3897 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
3898 CTLFLAG_RD, &adapter->stats.bprc,
3899 "Broadcast Packets Received");
3900 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
3901 CTLFLAG_RD, &adapter->stats.mprc,
3902 "Multicast Packets Received");
3903 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
3904 CTLFLAG_RD, &adapter->stats.prc64,
3905 "64 byte frames received ");
3906 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
3907 CTLFLAG_RD, &adapter->stats.prc127,
3908 "65-127 byte frames received");
3909 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
3910 CTLFLAG_RD, &adapter->stats.prc255,
3911 "128-255 byte frames received");
3912 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
3913 CTLFLAG_RD, &adapter->stats.prc511,
3914 "256-511 byte frames received");
3915 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
3916 CTLFLAG_RD, &adapter->stats.prc1023,
3917 "512-1023 byte frames received");
3918 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
3919 CTLFLAG_RD, &adapter->stats.prc1522,
3920 "1023-1522 byte frames received");
3921 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
3922 CTLFLAG_RD, &adapter->stats.gorc,
3923 "Good Octets Received");
3925 /* Packet Transmission Stats */
3926 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
3927 CTLFLAG_RD, &adapter->stats.gotc,
3928 "Good Octets Transmitted");
3929 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
3930 CTLFLAG_RD, &adapter->stats.tpt,
3931 "Total Packets Transmitted");
3932 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
3933 CTLFLAG_RD, &adapter->stats.gptc,
3934 "Good Packets Transmitted");
3935 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
3936 CTLFLAG_RD, &adapter->stats.bptc,
3937 "Broadcast Packets Transmitted");
3938 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
3939 CTLFLAG_RD, &adapter->stats.mptc,
3940 "Multicast Packets Transmitted");
3941 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
3942 CTLFLAG_RD, &adapter->stats.ptc64,
3943 "64 byte frames transmitted ");
3944 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
3945 CTLFLAG_RD, &adapter->stats.ptc127,
3946 "65-127 byte frames transmitted");
3947 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
3948 CTLFLAG_RD, &adapter->stats.ptc255,
3949 "128-255 byte frames transmitted");
3950 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
3951 CTLFLAG_RD, &adapter->stats.ptc511,
3952 "256-511 byte frames transmitted");
3953 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
3954 CTLFLAG_RD, &adapter->stats.ptc1023,
3955 "512-1023 byte frames transmitted");
3956 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
3957 CTLFLAG_RD, &adapter->stats.ptc1522,
3958 "1024-1522 byte frames transmitted");
3959 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
3960 CTLFLAG_RD, &adapter->stats.tsctc,
3961 "TSO Contexts Transmitted");
3962 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
3963 CTLFLAG_RD, &adapter->stats.tsctfc,
3964 "TSO Contexts Failed");
3967 /* Interrupt Stats */
3969 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
3970 CTLFLAG_RD, NULL, "Interrupt Statistics");
3971 int_list = SYSCTL_CHILDREN(int_node);
3973 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
3974 CTLFLAG_RD, &adapter->stats.iac,
3975 "Interrupt Assertion Count");
3977 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
3978 CTLFLAG_RD, &adapter->stats.icrxptc,
3979 "Interrupt Cause Rx Pkt Timer Expire Count");
3981 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
3982 CTLFLAG_RD, &adapter->stats.icrxatc,
3983 "Interrupt Cause Rx Abs Timer Expire Count");
3985 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
3986 CTLFLAG_RD, &adapter->stats.ictxptc,
3987 "Interrupt Cause Tx Pkt Timer Expire Count");
3989 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
3990 CTLFLAG_RD, &adapter->stats.ictxatc,
3991 "Interrupt Cause Tx Abs Timer Expire Count");
3993 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
3994 CTLFLAG_RD, &adapter->stats.ictxqec,
3995 "Interrupt Cause Tx Queue Empty Count");
3997 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
3998 CTLFLAG_RD, &adapter->stats.ictxqmtc,
3999 "Interrupt Cause Tx Queue Min Thresh Count");
4001 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
4002 CTLFLAG_RD, &adapter->stats.icrxdmtc,
4003 "Interrupt Cause Rx Desc Min Thresh Count");
4005 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
4006 CTLFLAG_RD, &adapter->stats.icrxoc,
4007 "Interrupt Cause Receiver Overrun Count");
4010 /**********************************************************************
4012 * This routine provides a way to dump out the adapter eeprom,
4013 * often a useful debug/service tool. This only dumps the first
4014 * 32 words, stuff that matters is in that extent.
4016 **********************************************************************/
4018 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4020 struct adapter *adapter = (struct adapter *)arg1;
4025 error = sysctl_handle_int(oidp, &result, 0, req);
4027 if (error || !req->newptr)
4031 * This value will cause a hex dump of the
4032 * first 32 16-bit words of the EEPROM to
4036 em_print_nvm_info(adapter);
4042 em_print_nvm_info(struct adapter *adapter)
4047 /* Its a bit crude, but it gets the job done */
4048 printf("\nInterface EEPROM Dump:\n");
4049 printf("Offset\n0x0000 ");
4050 for (i = 0, j = 0; i < 32; i++, j++) {
4051 if (j == 8) { /* Make the offset block */
4053 printf("\n0x00%x0 ",row);
4055 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
4056 printf("%04x ", eeprom_data);
4062 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4064 struct em_int_delay_info *info;
4065 struct adapter *adapter;
4067 int error, usecs, ticks;
4069 info = (struct em_int_delay_info *)arg1;
4070 usecs = info->value;
4071 error = sysctl_handle_int(oidp, &usecs, 0, req);
4072 if (error != 0 || req->newptr == NULL)
4074 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4076 info->value = usecs;
4077 ticks = EM_USECS_TO_TICKS(usecs);
4078 if (info->offset == E1000_ITR) /* units are 256ns here */
4081 adapter = info->adapter;
4083 regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
4084 regval = (regval & ~0xffff) | (ticks & 0xffff);
4085 /* Handle a few special cases. */
4086 switch (info->offset) {
4091 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
4092 /* Don't write 0 into the TIDV register. */
4095 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
4098 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
4103 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
4104 const char *description, struct em_int_delay_info *info,
4105 int offset, int value)
4107 info->adapter = adapter;
4108 info->offset = offset;
4109 info->value = value;
4110 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev),
4111 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4112 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
4113 info, 0, em_sysctl_int_delay, "I", description);
4117 em_set_sysctl_value(struct adapter *adapter, const char *name,
4118 const char *description, int *limit, int value)
4121 SYSCTL_ADD_INT(device_get_sysctl_ctx(adapter->dev),
4122 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4123 OID_AUTO, name, CTLFLAG_RW, limit, value, description);
4128 ** Set flow control using sysctl:
4129 ** Flow control values:
4136 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4139 static int input = 3; /* default is full */
4140 struct adapter *adapter = (struct adapter *) arg1;
4142 error = sysctl_handle_int(oidp, &input, 0, req);
4144 if ((error) || (req->newptr == NULL))
4147 if (input == adapter->fc) /* no change? */
4151 case e1000_fc_rx_pause:
4152 case e1000_fc_tx_pause:
4155 adapter->hw.fc.requested_mode = input;
4156 adapter->fc = input;
4163 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
4164 e1000_force_mac_fc(&adapter->hw);
4169 ** Manage Energy Efficient Ethernet:
4171 ** 0/1 - enabled/disabled
4174 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4176 struct adapter *adapter = (struct adapter *) arg1;
4179 value = adapter->hw.dev_spec.ich8lan.eee_disable;
4180 error = sysctl_handle_int(oidp, &value, 0, req);
4181 if (error || req->newptr == NULL)
4183 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4184 em_if_init(adapter->ctx);
4190 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4192 struct adapter *adapter;
4197 error = sysctl_handle_int(oidp, &result, 0, req);
4199 if (error || !req->newptr)
4203 adapter = (struct adapter *)arg1;
4204 em_print_debug_info(adapter);
4211 ** This routine is meant to be fluid, add whatever is
4212 ** needed for debugging a problem. -jfv
4215 em_print_debug_info(struct adapter *adapter)
4217 device_t dev = adapter->dev;
4218 struct tx_ring *txr = &adapter->tx_queues->txr;
4219 struct rx_ring *rxr = &adapter->rx_queues->rxr;
4221 if (if_getdrvflags(adapter->ifp) & IFF_DRV_RUNNING)
4222 printf("Interface is RUNNING ");
4224 printf("Interface is NOT RUNNING\n");
4226 if (if_getdrvflags(adapter->ifp) & IFF_DRV_OACTIVE)
4227 printf("and INACTIVE\n");
4229 printf("and ACTIVE\n");
4231 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
4232 device_printf(dev, "TX Queue %d ------\n", i);
4233 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
4234 E1000_READ_REG(&adapter->hw, E1000_TDH(i)),
4235 E1000_READ_REG(&adapter->hw, E1000_TDT(i)));
4238 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) {
4239 device_printf(dev, "RX Queue %d ------\n", j);
4240 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
4241 E1000_READ_REG(&adapter->hw, E1000_RDH(j)),
4242 E1000_READ_REG(&adapter->hw, E1000_RDT(j)));
4249 * Write a new value to the EEPROM increasing the number of MSIX
4250 * vectors from 3 to 5, for proper multiqueue support.
4253 em_enable_vectors_82574(if_ctx_t ctx)
4255 struct adapter *adapter = iflib_get_softc(ctx);
4256 struct e1000_hw *hw = &adapter->hw;
4257 device_t dev = iflib_get_dev(ctx);
4260 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4261 printf("Current cap: %#06x\n", edata);
4262 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
4263 device_printf(dev, "Writing to eeprom: increasing "
4264 "reported MSIX vectors from 3 to 5...\n");
4265 edata &= ~(EM_NVM_MSIX_N_MASK);
4266 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
4267 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4268 e1000_update_nvm_checksum(hw);
4269 device_printf(dev, "Writing to eeprom: done\n");
4275 DB_COMMAND(em_reset_dev, em_ddb_reset_dev)
4280 dc = devclass_find("em");
4281 max_em = devclass_get_maxunit(dc);
4283 for (int index = 0; index < (max_em - 1); index++) {
4285 dev = devclass_get_device(dc, index);
4286 if (device_get_driver(dev) == &em_driver) {
4287 struct adapter *adapter = device_get_softc(dev);
4288 em_if_init(adapter->ctx);
4292 DB_COMMAND(em_dump_queue, em_ddb_dump_queue)
4297 dc = devclass_find("em");
4298 max_em = devclass_get_maxunit(dc);
4300 for (int index = 0; index < (max_em - 1); index++) {
4302 dev = devclass_get_device(dc, index);
4303 if (device_get_driver(dev) == &em_driver)
4304 em_print_debug_info(device_get_softc(dev));