sys/dev/e1000/if_em.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /* $FreeBSD$ */
  30 #include "if_em.h"
  31 #include <sys/sbuf.h>
  32 #include <machine/_inttypes.h>
  33
  34 #define em_mac_min e1000_82571
  35 #define igb_mac_min e1000_82575
  36
  37 /*********************************************************************
  38  *  Driver version:
  39  *********************************************************************/
  40 char em_driver_version[] = "7.6.1-k";
  41
  42 /*********************************************************************
  43  *  PCI Device ID Table
  44  *
  45  *  Used by probe to select devices to load on
  46  *  Last field stores an index into e1000_strings
  47  *  Last entry must be all 0s
  48  *
  49  *  { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
  50  *********************************************************************/
  51
  52 static pci_vendor_info_t em_vendor_info_array[] =
  53 {
  54         /* Intel(R) - lem-class legacy devices */
  55         PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"),
  56         PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"),
  57         PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"),
  58         PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"),
  59         PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"),
  60
  61         PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"),
  62         PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"),
  63         PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"),
  64         PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"),
  65         PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"),
  66         PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"),
  67         PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"),
  68
  69         PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"),
  70
  71         PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"),
  72         PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"),
  73
  74         PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"),
  75         PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"),
  76         PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"),
  77         PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"),
  78
  79         PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"),
  80         PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"),
  81         PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"),
  82         PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"),
  83         PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"),
  84
  85         PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"),
  86         PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"),
  87         PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"),
  88         PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"),
  89         PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"),
  90         PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"),
  91         PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"),
  92         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
  93         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
  94
  95         PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"),
  96         PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"),
  97         PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"),
  98
  99         /* Intel(R) - em-class devices */
 100         PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"),
 101         PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"),
 102         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"),
 103         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"),
 104         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"),
 105         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
 106         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
 107         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"),
 108         PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"),
 109         PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"),
 110         PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"),
 111         PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"),
 112         PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"),
 113         PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"),
 114         PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"),
 115         PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"),
 116         PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"),
 117         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"),
 118         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"),
 119         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"),
 120         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"),
 121         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"),
 122         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"),
 123         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"),
 124         PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"),
 125         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"),
 126         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"),
 127         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"),
 128         PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"),
 129         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"),
 130         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"),
 131         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"),
 132         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"),
 133         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"),
 134         PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"),
 135         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"),
 136         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"),
 137         PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"),
 138         PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"),
 139         PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"),
 140         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"),
 141         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"),
 142         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"),
 143         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"),
 144         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"),
 145         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"),
 146         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"),
 147         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"),
 148         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"),
 149         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"),
 150         PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"),
 151         PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"),
 152         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"),
 153         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"),
 154         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"),
 155         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"),
 156         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"),
 157         PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"),
 158         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"),
 159         PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"),
 160         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"),
 161         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"),
 162         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"),
 163         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"),
 164         PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"),
 165         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"),
 166         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"),
 167         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"),
 168         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"),
 169         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"),
 170         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"),
 171         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"),
 172         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"),
 173         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"),
 174         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"),
 175         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"),
 176         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"),
 177         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"),
 178         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"),
 179         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"),
 180         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"),
 181         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"),
 182         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"),
 183         PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"),
 184         PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"),
 185         PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"),
 186         PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"),
 187         PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"),
 188         PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"),
 189         PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"),
 190         PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"),
 191         PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"),
 192         PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"),
 193         PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"),
 194         PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"),
 195         PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"),
 196         PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"),
 197         /* required last entry */
 198         PVID_END
 199 };
 200
 201 static pci_vendor_info_t igb_vendor_info_array[] =
 202 {
 203         /* Intel(R) - igb-class devices */
 204         PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"),
 205         PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"),
 206         PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"),
 207         PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"),
 208         PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"),
 209         PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"),
 210         PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"),
 211         PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"),
 212         PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"),
 213         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"),
 214         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"),
 215         PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"),
 216         PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"),
 217         PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"),
 218         PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"),
 219         PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"),
 220         PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"),
 221         PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"),
 222         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"),
 223         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"),
 224         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"),
 225         PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"),
 226         PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"),
 227         PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"),
 228         PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"),
 229         PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"),
 230         PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"),
 231         PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"),
 232         PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"),
 233         PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"),
 234         PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"),
 235         PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"),
 236         PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"),
 237         PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"),
 238         PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"),
 239         PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"),
 240         PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"),
 241         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"),
 242         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"),
 243         PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"),
 244         /* required last entry */
 245         PVID_END
 246 };
 247
 248 /*********************************************************************
 249  *  Function prototypes
 250  *********************************************************************/
 251 static void     *em_register(device_t dev);
 252 static void     *igb_register(device_t dev);
 253 static int      em_if_attach_pre(if_ctx_t ctx);
 254 static int      em_if_attach_post(if_ctx_t ctx);
 255 static int      em_if_detach(if_ctx_t ctx);
 256 static int      em_if_shutdown(if_ctx_t ctx);
 257 static int      em_if_suspend(if_ctx_t ctx);
 258 static int      em_if_resume(if_ctx_t ctx);
 259
 260 static int      em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets);
 261 static int      em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets);
 262 static void     em_if_queues_free(if_ctx_t ctx);
 263
 264 static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
 265 static void     em_if_init(if_ctx_t ctx);
 266 static void     em_if_stop(if_ctx_t ctx);
 267 static void     em_if_media_status(if_ctx_t, struct ifmediareq *);
 268 static int      em_if_media_change(if_ctx_t ctx);
 269 static int      em_if_mtu_set(if_ctx_t ctx, uint32_t mtu);
 270 static void     em_if_timer(if_ctx_t ctx, uint16_t qid);
 271 static void     em_if_vlan_register(if_ctx_t ctx, u16 vtag);
 272 static void     em_if_vlan_unregister(if_ctx_t ctx, u16 vtag);
 273 static void     em_if_watchdog_reset(if_ctx_t ctx);
 274 static bool     em_if_needs_restart(if_ctx_t ctx, enum iflib_restart_event event);
 275
 276 static void     em_identify_hardware(if_ctx_t ctx);
 277 static int      em_allocate_pci_resources(if_ctx_t ctx);
 278 static void     em_free_pci_resources(if_ctx_t ctx);
 279 static void     em_reset(if_ctx_t ctx);
 280 static int      em_setup_interface(if_ctx_t ctx);
 281 static int      em_setup_msix(if_ctx_t ctx);
 282
 283 static void     em_initialize_transmit_unit(if_ctx_t ctx);
 284 static void     em_initialize_receive_unit(if_ctx_t ctx);
 285
 286 static void     em_if_intr_enable(if_ctx_t ctx);
 287 static void     em_if_intr_disable(if_ctx_t ctx);
 288 static void     igb_if_intr_enable(if_ctx_t ctx);
 289 static void     igb_if_intr_disable(if_ctx_t ctx);
 290 static int      em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 291 static int      em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
 292 static int      igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 293 static int      igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
 294 static void     em_if_multi_set(if_ctx_t ctx);
 295 static void     em_if_update_admin_status(if_ctx_t ctx);
 296 static void     em_if_debug(if_ctx_t ctx);
 297 static void     em_update_stats_counters(struct e1000_softc *);
 298 static void     em_add_hw_stats(struct e1000_softc *);
 299 static int      em_if_set_promisc(if_ctx_t ctx, int flags);
 300 static bool     em_if_vlan_filter_capable(struct e1000_softc *);
 301 static bool     em_if_vlan_filter_used(struct e1000_softc *);
 302 static void     em_if_vlan_filter_enable(struct e1000_softc *);
 303 static void     em_if_vlan_filter_disable(struct e1000_softc *);
 304 static void     em_if_vlan_filter_write(struct e1000_softc *);
 305 static void     em_setup_vlan_hw_support(struct e1000_softc *);
 306 static int      em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
 307 static void     em_print_nvm_info(struct e1000_softc *);
 308 static int      em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 309 static int      em_get_rs(SYSCTL_HANDLER_ARGS);
 310 static void     em_print_debug_info(struct e1000_softc *);
 311 static int      em_is_valid_ether_addr(u8 *);
 312 static int      em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
 313 static void     em_add_int_delay_sysctl(struct e1000_softc *, const char *,
 314                     const char *, struct em_int_delay_info *, int, int);
 315 /* Management and WOL Support */
 316 static void     em_init_manageability(struct e1000_softc *);
 317 static void     em_release_manageability(struct e1000_softc *);
 318 static void     em_get_hw_control(struct e1000_softc *);
 319 static void     em_release_hw_control(struct e1000_softc *);
 320 static void     em_get_wakeup(if_ctx_t ctx);
 321 static void     em_enable_wakeup(if_ctx_t ctx);
 322 static int      em_enable_phy_wakeup(struct e1000_softc *);
 323 static void     em_disable_aspm(struct e1000_softc *);
 324
 325 int             em_intr(void *arg);
 326
 327 /* MSI-X handlers */
 328 static int      em_if_msix_intr_assign(if_ctx_t, int);
 329 static int      em_msix_link(void *);
 330 static void     em_handle_link(void *context);
 331
 332 static void     em_enable_vectors_82574(if_ctx_t);
 333
 334 static int      em_set_flowcntl(SYSCTL_HANDLER_ARGS);
 335 static int      em_sysctl_eee(SYSCTL_HANDLER_ARGS);
 336 static void     em_if_led_func(if_ctx_t ctx, int onoff);
 337
 338 static int      em_get_regs(SYSCTL_HANDLER_ARGS);
 339
 340 static void     lem_smartspeed(struct e1000_softc *);
 341 static void     igb_configure_queues(struct e1000_softc *);
 342
 343
 344 /*********************************************************************
 345  *  FreeBSD Device Interface Entry Points
 346  *********************************************************************/
 347 static device_method_t em_methods[] = {
 348         /* Device interface */
 349         DEVMETHOD(device_register, em_register),
 350         DEVMETHOD(device_probe, iflib_device_probe),
 351         DEVMETHOD(device_attach, iflib_device_attach),
 352         DEVMETHOD(device_detach, iflib_device_detach),
 353         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 354         DEVMETHOD(device_suspend, iflib_device_suspend),
 355         DEVMETHOD(device_resume, iflib_device_resume),
 356         DEVMETHOD_END
 357 };
 358
 359 static device_method_t igb_methods[] = {
 360         /* Device interface */
 361         DEVMETHOD(device_register, igb_register),
 362         DEVMETHOD(device_probe, iflib_device_probe),
 363         DEVMETHOD(device_attach, iflib_device_attach),
 364         DEVMETHOD(device_detach, iflib_device_detach),
 365         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 366         DEVMETHOD(device_suspend, iflib_device_suspend),
 367         DEVMETHOD(device_resume, iflib_device_resume),
 368         DEVMETHOD_END
 369 };
 370
 371
 372 static driver_t em_driver = {
 373         "em", em_methods, sizeof(struct e1000_softc),
 374 };
 375
 376 static devclass_t em_devclass;
 377 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
 378
 379 MODULE_DEPEND(em, pci, 1, 1, 1);
 380 MODULE_DEPEND(em, ether, 1, 1, 1);
 381 MODULE_DEPEND(em, iflib, 1, 1, 1);
 382
 383 IFLIB_PNP_INFO(pci, em, em_vendor_info_array);
 384
 385 static driver_t igb_driver = {
 386         "igb", igb_methods, sizeof(struct e1000_softc),
 387 };
 388
 389 static devclass_t igb_devclass;
 390 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
 391
 392 MODULE_DEPEND(igb, pci, 1, 1, 1);
 393 MODULE_DEPEND(igb, ether, 1, 1, 1);
 394 MODULE_DEPEND(igb, iflib, 1, 1, 1);
 395
 396 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array);
 397
 398 static device_method_t em_if_methods[] = {
 399         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 400         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 401         DEVMETHOD(ifdi_detach, em_if_detach),
 402         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 403         DEVMETHOD(ifdi_suspend, em_if_suspend),
 404         DEVMETHOD(ifdi_resume, em_if_resume),
 405         DEVMETHOD(ifdi_init, em_if_init),
 406         DEVMETHOD(ifdi_stop, em_if_stop),
 407         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 408         DEVMETHOD(ifdi_intr_enable, em_if_intr_enable),
 409         DEVMETHOD(ifdi_intr_disable, em_if_intr_disable),
 410         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 411         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 412         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 413         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 414         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 415         DEVMETHOD(ifdi_media_status, em_if_media_status),
 416         DEVMETHOD(ifdi_media_change, em_if_media_change),
 417         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 418         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 419         DEVMETHOD(ifdi_timer, em_if_timer),
 420         DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
 421         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 422         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 423         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 424         DEVMETHOD(ifdi_led_func, em_if_led_func),
 425         DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable),
 426         DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable),
 427         DEVMETHOD(ifdi_debug, em_if_debug),
 428         DEVMETHOD(ifdi_needs_restart, em_if_needs_restart),
 429         DEVMETHOD_END
 430 };
 431
 432 static driver_t em_if_driver = {
 433         "em_if", em_if_methods, sizeof(struct e1000_softc)
 434 };
 435
 436 static device_method_t igb_if_methods[] = {
 437         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 438         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 439         DEVMETHOD(ifdi_detach, em_if_detach),
 440         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 441         DEVMETHOD(ifdi_suspend, em_if_suspend),
 442         DEVMETHOD(ifdi_resume, em_if_resume),
 443         DEVMETHOD(ifdi_init, em_if_init),
 444         DEVMETHOD(ifdi_stop, em_if_stop),
 445         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 446         DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable),
 447         DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable),
 448         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 449         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 450         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 451         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 452         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 453         DEVMETHOD(ifdi_media_status, em_if_media_status),
 454         DEVMETHOD(ifdi_media_change, em_if_media_change),
 455         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 456         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 457         DEVMETHOD(ifdi_timer, em_if_timer),
 458         DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
 459         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 460         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 461         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 462         DEVMETHOD(ifdi_led_func, em_if_led_func),
 463         DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable),
 464         DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable),
 465         DEVMETHOD(ifdi_debug, em_if_debug),
 466         DEVMETHOD(ifdi_needs_restart, em_if_needs_restart),
 467         DEVMETHOD_END
 468 };
 469
 470 static driver_t igb_if_driver = {
 471         "igb_if", igb_if_methods, sizeof(struct e1000_softc)
 472 };
 473
 474 /*********************************************************************
 475  *  Tunable default values.
 476  *********************************************************************/
 477
 478 #define EM_TICKS_TO_USECS(ticks)        ((1024 * (ticks) + 500) / 1000)
 479 #define EM_USECS_TO_TICKS(usecs)        ((1000 * (usecs) + 512) / 1024)
 480
 481 #define MAX_INTS_PER_SEC        8000
 482 #define DEFAULT_ITR             (1000000000/(MAX_INTS_PER_SEC * 256))
 483
 484 /* Allow common code without TSO */
 485 #ifndef CSUM_TSO
 486 #define CSUM_TSO        0
 487 #endif
 488
 489 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
 490     "EM driver parameters");
 491
 492 static int em_disable_crc_stripping = 0;
 493 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
 494     &em_disable_crc_stripping, 0, "Disable CRC Stripping");
 495
 496 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
 497 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
 498 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
 499     0, "Default transmit interrupt delay in usecs");
 500 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
 501     0, "Default receive interrupt delay in usecs");
 502
 503 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
 504 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
 505 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
 506     &em_tx_abs_int_delay_dflt, 0,
 507     "Default transmit interrupt delay limit in usecs");
 508 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
 509     &em_rx_abs_int_delay_dflt, 0,
 510     "Default receive interrupt delay limit in usecs");
 511
 512 static int em_smart_pwr_down = false;
 513 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
 514     0, "Set to true to leave smart power down enabled on newer adapters");
 515
 516 /* Controls whether promiscuous also shows bad packets */
 517 static int em_debug_sbp = false;
 518 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
 519     "Show bad packets in promiscuous mode");
 520
 521 /* How many packets rxeof tries to clean at a time */
 522 static int em_rx_process_limit = 100;
 523 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
 524     &em_rx_process_limit, 0,
 525     "Maximum number of received packets to process "
 526     "at a time, -1 means unlimited");
 527
 528 /* Energy efficient ethernet - default to OFF */
 529 static int eee_setting = 1;
 530 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
 531     "Enable Energy Efficient Ethernet");
 532
 533 /*
 534 ** Tuneable Interrupt rate
 535 */
 536 static int em_max_interrupt_rate = 8000;
 537 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
 538     &em_max_interrupt_rate, 0, "Maximum interrupts per second");
 539
 540
 541
 542 /* Global used in WOL setup with multiport cards */
 543 static int global_quad_port_a = 0;
 544
 545 extern struct if_txrx igb_txrx;
 546 extern struct if_txrx em_txrx;
 547 extern struct if_txrx lem_txrx;
 548
 549 static struct if_shared_ctx em_sctx_init = {
 550         .isc_magic = IFLIB_MAGIC,
 551         .isc_q_align = PAGE_SIZE,
 552         .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 553         .isc_tx_maxsegsize = PAGE_SIZE,
 554         .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 555         .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
 556         .isc_rx_maxsize = MJUM9BYTES,
 557         .isc_rx_nsegments = 1,
 558         .isc_rx_maxsegsize = MJUM9BYTES,
 559         .isc_nfl = 1,
 560         .isc_nrxqs = 1,
 561         .isc_ntxqs = 1,
 562         .isc_admin_intrcnt = 1,
 563         .isc_vendor_info = em_vendor_info_array,
 564         .isc_driver_version = em_driver_version,
 565         .isc_driver = &em_if_driver,
 566         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 567
 568         .isc_nrxd_min = {EM_MIN_RXD},
 569         .isc_ntxd_min = {EM_MIN_TXD},
 570         .isc_nrxd_max = {EM_MAX_RXD},
 571         .isc_ntxd_max = {EM_MAX_TXD},
 572         .isc_nrxd_default = {EM_DEFAULT_RXD},
 573         .isc_ntxd_default = {EM_DEFAULT_TXD},
 574 };
 575
 576 static struct if_shared_ctx igb_sctx_init = {
 577         .isc_magic = IFLIB_MAGIC,
 578         .isc_q_align = PAGE_SIZE,
 579         .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 580         .isc_tx_maxsegsize = PAGE_SIZE,
 581         .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 582         .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
 583         .isc_rx_maxsize = MJUM9BYTES,
 584         .isc_rx_nsegments = 1,
 585         .isc_rx_maxsegsize = MJUM9BYTES,
 586         .isc_nfl = 1,
 587         .isc_nrxqs = 1,
 588         .isc_ntxqs = 1,
 589         .isc_admin_intrcnt = 1,
 590         .isc_vendor_info = igb_vendor_info_array,
 591         .isc_driver_version = em_driver_version,
 592         .isc_driver = &igb_if_driver,
 593         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 594
 595         .isc_nrxd_min = {EM_MIN_RXD},
 596         .isc_ntxd_min = {EM_MIN_TXD},
 597         .isc_nrxd_max = {IGB_MAX_RXD},
 598         .isc_ntxd_max = {IGB_MAX_TXD},
 599         .isc_nrxd_default = {EM_DEFAULT_RXD},
 600         .isc_ntxd_default = {EM_DEFAULT_TXD},
 601 };
 602
 603 /*****************************************************************
 604  *
 605  * Dump Registers
 606  *
 607  ****************************************************************/
 608 #define IGB_REGS_LEN 739
 609
 610 static int em_get_regs(SYSCTL_HANDLER_ARGS)
 611 {
 612         struct e1000_softc *sc = (struct e1000_softc *)arg1;
 613         struct e1000_hw *hw = &sc->hw;
 614         struct sbuf *sb;
 615         u32 *regs_buff;
 616         int rc;
 617
 618         regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK);
 619         memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
 620
 621         rc = sysctl_wire_old_buffer(req, 0);
 622         MPASS(rc == 0);
 623         if (rc != 0) {
 624                 free(regs_buff, M_DEVBUF);
 625                 return (rc);
 626         }
 627
 628         sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
 629         MPASS(sb != NULL);
 630         if (sb == NULL) {
 631                 free(regs_buff, M_DEVBUF);
 632                 return (ENOMEM);
 633         }
 634
 635         /* General Registers */
 636         regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
 637         regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
 638         regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
 639         regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
 640         regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
 641         regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
 642         regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
 643         regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
 644         regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
 645         regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
 646         regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
 647         regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
 648         regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
 649         regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
 650         regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
 651         regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
 652         regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
 653         regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
 654         regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
 655         regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
 656         regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
 657         regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
 658
 659         sbuf_printf(sb, "General Registers\n");
 660         sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
 661         sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
 662         sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]);
 663
 664         sbuf_printf(sb, "Interrupt Registers\n");
 665         sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
 666
 667         sbuf_printf(sb, "RX Registers\n");
 668         sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
 669         sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
 670         sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
 671         sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
 672         sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
 673         sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
 674         sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
 675
 676         sbuf_printf(sb, "TX Registers\n");
 677         sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
 678         sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
 679         sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
 680         sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
 681         sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
 682         sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
 683         sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
 684         sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
 685         sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
 686         sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
 687         sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
 688
 689         free(regs_buff, M_DEVBUF);
 690
 691 #ifdef DUMP_DESCS
 692         {
 693                 if_softc_ctx_t scctx = sc->shared;
 694                 struct rx_ring *rxr = &rx_que->rxr;
 695                 struct tx_ring *txr = &tx_que->txr;
 696                 int ntxd = scctx->isc_ntxd[0];
 697                 int nrxd = scctx->isc_nrxd[0];
 698                 int j;
 699
 700         for (j = 0; j < nrxd; j++) {
 701                 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
 702                 u32 length =  le32toh(rxr->rx_base[j].wb.upper.length);
 703                 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 "  Error:%d  Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
 704         }
 705
 706         for (j = 0; j < min(ntxd, 256); j++) {
 707                 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
 708
 709                 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x  eop: %d DD=%d\n",
 710                             j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
 711                             buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
 712
 713         }
 714         }
 715 #endif
 716
 717         rc = sbuf_finish(sb);
 718         sbuf_delete(sb);
 719         return(rc);
 720 }
 721
 722 static void *
 723 em_register(device_t dev)
 724 {
 725         return (&em_sctx_init);
 726 }
 727
 728 static void *
 729 igb_register(device_t dev)
 730 {
 731         return (&igb_sctx_init);
 732 }
 733
 734 static int
 735 em_set_num_queues(if_ctx_t ctx)
 736 {
 737         struct e1000_softc *sc = iflib_get_softc(ctx);
 738         int maxqueues;
 739
 740         /* Sanity check based on HW */
 741         switch (sc->hw.mac.type) {
 742         case e1000_82576:
 743         case e1000_82580:
 744         case e1000_i350:
 745         case e1000_i354:
 746                 maxqueues = 8;
 747                 break;
 748         case e1000_i210:
 749         case e1000_82575:
 750                 maxqueues = 4;
 751                 break;
 752         case e1000_i211:
 753         case e1000_82574:
 754                 maxqueues = 2;
 755                 break;
 756         default:
 757                 maxqueues = 1;
 758                 break;
 759         }
 760
 761         return (maxqueues);
 762 }
 763
 764 #define LEM_CAPS                                                        \
 765     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 766     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER
 767
 768 #define EM_CAPS                                                         \
 769     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 770     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 |  \
 771     IFCAP_LRO | IFCAP_VLAN_HWTSO
 772
 773 #define IGB_CAPS                                                        \
 774     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 775     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 |  \
 776     IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\
 777     IFCAP_TSO6
 778
 779 /*********************************************************************
 780  *  Device initialization routine
 781  *
 782  *  The attach entry point is called when the driver is being loaded.
 783  *  This routine identifies the type of hardware, allocates all resources
 784  *  and initializes the hardware.
 785  *
 786  *  return 0 on success, positive on failure
 787  *********************************************************************/
 788 static int
 789 em_if_attach_pre(if_ctx_t ctx)
 790 {
 791         struct e1000_softc *sc;
 792         if_softc_ctx_t scctx;
 793         device_t dev;
 794         struct e1000_hw *hw;
 795         int error = 0;
 796
 797         INIT_DEBUGOUT("em_if_attach_pre: begin");
 798         dev = iflib_get_dev(ctx);
 799         sc = iflib_get_softc(ctx);
 800
 801         sc->ctx = sc->osdep.ctx = ctx;
 802         sc->dev = sc->osdep.dev = dev;
 803         scctx = sc->shared = iflib_get_softc_ctx(ctx);
 804         sc->media = iflib_get_media(ctx);
 805         hw = &sc->hw;
 806
 807         sc->tx_process_limit = scctx->isc_ntxd[0];
 808
 809         /* SYSCTL stuff */
 810         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 811             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 812             OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
 813             sc, 0, em_sysctl_nvm_info, "I", "NVM Information");
 814
 815         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 816             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 817             OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
 818             sc, 0, em_sysctl_debug_info, "I", "Debug Information");
 819
 820         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 821             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 822             OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
 823             sc, 0, em_set_flowcntl, "I", "Flow Control");
 824
 825         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 826             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 827             OID_AUTO, "reg_dump",
 828             CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
 829             em_get_regs, "A", "Dump Registers");
 830
 831         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 832             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 833             OID_AUTO, "rs_dump",
 834             CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
 835             em_get_rs, "I", "Dump RS indexes");
 836
 837         /* Determine hardware and mac info */
 838         em_identify_hardware(ctx);
 839
 840         scctx->isc_tx_nsegments = EM_MAX_SCATTER;
 841         scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
 842         if (bootverbose)
 843                 device_printf(dev, "attach_pre capping queues at %d\n",
 844                     scctx->isc_ntxqsets_max);
 845
 846         if (hw->mac.type >= igb_mac_min) {
 847                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
 848                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
 849                 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
 850                 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
 851                 scctx->isc_txrx = &igb_txrx;
 852                 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
 853                 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 854                 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 855                 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS;
 856                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO |
 857                      CSUM_IP6_TCP | CSUM_IP6_UDP;
 858                 if (hw->mac.type != e1000_82575)
 859                         scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
 860                 /*
 861                 ** Some new devices, as with ixgbe, now may
 862                 ** use a different BAR, so we need to keep
 863                 ** track of which is used.
 864                 */
 865                 scctx->isc_msix_bar = pci_msix_table_bar(dev);
 866         } else if (hw->mac.type >= em_mac_min) {
 867                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 868                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
 869                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 870                 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
 871                 scctx->isc_txrx = &em_txrx;
 872                 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
 873                 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 874                 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 875                 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS;
 876                 /*
 877                  * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO}
 878                  * by default as we don't have workarounds for all associated
 879                  * silicon errata.  E. g., with several MACs such as 82573E,
 880                  * TSO only works at Gigabit speed and otherwise can cause the
 881                  * hardware to hang (which also would be next to impossible to
 882                  * work around given that already queued TSO-using descriptors
 883                  * would need to be flushed and vlan(4) reconfigured at runtime
 884                  * in case of a link speed change).  Moreover, MACs like 82579
 885                  * still can hang at Gigabit even with all publicly documented
 886                  * TSO workarounds implemented.  Generally, the penality of
 887                  * these workarounds is rather high and may involve copying
 888                  * mbuf data around so advantages of TSO lapse.  Still, TSO may
 889                  * work for a few MACs of this class - at least when sticking
 890                  * with Gigabit - in which case users may enable TSO manually.
 891                  */
 892                 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
 893                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 894                 /*
 895                  * We support MSI-X with 82574 only, but indicate to iflib(4)
 896                  * that it shall give MSI at least a try with other devices.
 897                  */
 898                 if (hw->mac.type == e1000_82574) {
 899                         scctx->isc_msix_bar = pci_msix_table_bar(dev);;
 900                 } else {
 901                         scctx->isc_msix_bar = -1;
 902                         scctx->isc_disable_msix = 1;
 903                 }
 904         } else {
 905                 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 906                 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
 907                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 908                 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
 909                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP;
 910                 scctx->isc_txrx = &lem_txrx;
 911                 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS;
 912                 if (hw->mac.type < e1000_82543)
 913                         scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
 914                 /* 82541ER doesn't do HW tagging */
 915                 if (hw->device_id == E1000_DEV_ID_82541ER || hw->device_id == E1000_DEV_ID_82541ER_LOM)
 916                         scctx->isc_capenable &= ~IFCAP_VLAN_HWTAGGING;
 917                 /* INTx only */
 918                 scctx->isc_msix_bar = 0;
 919         }
 920
 921         /* Setup PCI resources */
 922         if (em_allocate_pci_resources(ctx)) {
 923                 device_printf(dev, "Allocation of PCI resources failed\n");
 924                 error = ENXIO;
 925                 goto err_pci;
 926         }
 927
 928         /*
 929         ** For ICH8 and family we need to
 930         ** map the flash memory, and this
 931         ** must happen after the MAC is
 932         ** identified
 933         */
 934         if ((hw->mac.type == e1000_ich8lan) ||
 935             (hw->mac.type == e1000_ich9lan) ||
 936             (hw->mac.type == e1000_ich10lan) ||
 937             (hw->mac.type == e1000_pchlan) ||
 938             (hw->mac.type == e1000_pch2lan) ||
 939             (hw->mac.type == e1000_pch_lpt)) {
 940                 int rid = EM_BAR_TYPE_FLASH;
 941                 sc->flash = bus_alloc_resource_any(dev,
 942                     SYS_RES_MEMORY, &rid, RF_ACTIVE);
 943                 if (sc->flash == NULL) {
 944                         device_printf(dev, "Mapping of Flash failed\n");
 945                         error = ENXIO;
 946                         goto err_pci;
 947                 }
 948                 /* This is used in the shared code */
 949                 hw->flash_address = (u8 *)sc->flash;
 950                 sc->osdep.flash_bus_space_tag =
 951                     rman_get_bustag(sc->flash);
 952                 sc->osdep.flash_bus_space_handle =
 953                     rman_get_bushandle(sc->flash);
 954         }
 955         /*
 956         ** In the new SPT device flash is not  a
 957         ** separate BAR, rather it is also in BAR0,
 958         ** so use the same tag and an offset handle for the
 959         ** FLASH read/write macros in the shared code.
 960         */
 961         else if (hw->mac.type >= e1000_pch_spt) {
 962                 sc->osdep.flash_bus_space_tag =
 963                     sc->osdep.mem_bus_space_tag;
 964                 sc->osdep.flash_bus_space_handle =
 965                     sc->osdep.mem_bus_space_handle
 966                     + E1000_FLASH_BASE_ADDR;
 967         }
 968
 969         /* Do Shared Code initialization */
 970         error = e1000_setup_init_funcs(hw, true);
 971         if (error) {
 972                 device_printf(dev, "Setup of Shared code failed, error %d\n",
 973                     error);
 974                 error = ENXIO;
 975                 goto err_pci;
 976         }
 977
 978         em_setup_msix(ctx);
 979         e1000_get_bus_info(hw);
 980
 981         /* Set up some sysctls for the tunable interrupt delays */
 982         em_add_int_delay_sysctl(sc, "rx_int_delay",
 983             "receive interrupt delay in usecs", &sc->rx_int_delay,
 984             E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
 985         em_add_int_delay_sysctl(sc, "tx_int_delay",
 986             "transmit interrupt delay in usecs", &sc->tx_int_delay,
 987             E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
 988         em_add_int_delay_sysctl(sc, "rx_abs_int_delay",
 989             "receive interrupt delay limit in usecs",
 990             &sc->rx_abs_int_delay,
 991             E1000_REGISTER(hw, E1000_RADV),
 992             em_rx_abs_int_delay_dflt);
 993         em_add_int_delay_sysctl(sc, "tx_abs_int_delay",
 994             "transmit interrupt delay limit in usecs",
 995             &sc->tx_abs_int_delay,
 996             E1000_REGISTER(hw, E1000_TADV),
 997             em_tx_abs_int_delay_dflt);
 998         em_add_int_delay_sysctl(sc, "itr",
 999             "interrupt delay limit in usecs/4",
1000             &sc->tx_itr,
1001             E1000_REGISTER(hw, E1000_ITR),
1002             DEFAULT_ITR);
1003
1004         hw->mac.autoneg = DO_AUTO_NEG;
1005         hw->phy.autoneg_wait_to_complete = false;
1006         hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1007
1008         if (hw->mac.type < em_mac_min) {
1009                 e1000_init_script_state_82541(hw, true);
1010                 e1000_set_tbi_compatibility_82543(hw, true);
1011         }
1012         /* Copper options */
1013         if (hw->phy.media_type == e1000_media_type_copper) {
1014                 hw->phy.mdix = AUTO_ALL_MODES;
1015                 hw->phy.disable_polarity_correction = false;
1016                 hw->phy.ms_type = EM_MASTER_SLAVE;
1017         }
1018
1019         /*
1020          * Set the frame limits assuming
1021          * standard ethernet sized frames.
1022          */
1023         scctx->isc_max_frame_size = hw->mac.max_frame_size =
1024             ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
1025
1026         /*
1027          * This controls when hardware reports transmit completion
1028          * status.
1029          */
1030         hw->mac.report_tx_early = 1;
1031
1032         /* Allocate multicast array memory. */
1033         sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN *
1034             MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
1035         if (sc->mta == NULL) {
1036                 device_printf(dev, "Can not allocate multicast setup array\n");
1037                 error = ENOMEM;
1038                 goto err_late;
1039         }
1040
1041         /* Check SOL/IDER usage */
1042         if (e1000_check_reset_block(hw))
1043                 device_printf(dev, "PHY reset is blocked"
1044                               " due to SOL/IDER session.\n");
1045
1046         /* Sysctl for setting Energy Efficient Ethernet */
1047         hw->dev_spec.ich8lan.eee_disable = eee_setting;
1048         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1049             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1050             OID_AUTO, "eee_control",
1051             CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
1052             sc, 0, em_sysctl_eee, "I",
1053             "Disable Energy Efficient Ethernet");
1054
1055         /*
1056         ** Start from a known state, this is
1057         ** important in reading the nvm and
1058         ** mac from that.
1059         */
1060         e1000_reset_hw(hw);
1061
1062         /* Make sure we have a good EEPROM before we read from it */
1063         if (e1000_validate_nvm_checksum(hw) < 0) {
1064                 /*
1065                 ** Some PCI-E parts fail the first check due to
1066                 ** the link being in sleep state, call it again,
1067                 ** if it fails a second time its a real issue.
1068                 */
1069                 if (e1000_validate_nvm_checksum(hw) < 0) {
1070                         device_printf(dev,
1071                             "The EEPROM Checksum Is Not Valid\n");
1072                         error = EIO;
1073                         goto err_late;
1074                 }
1075         }
1076
1077         /* Copy the permanent MAC address out of the EEPROM */
1078         if (e1000_read_mac_addr(hw) < 0) {
1079                 device_printf(dev, "EEPROM read error while reading MAC"
1080                               " address\n");
1081                 error = EIO;
1082                 goto err_late;
1083         }
1084
1085         if (!em_is_valid_ether_addr(hw->mac.addr)) {
1086                 if (sc->vf_ifp) {
1087                         ether_gen_addr(iflib_get_ifp(ctx),
1088                             (struct ether_addr *)hw->mac.addr);
1089                 } else {
1090                         device_printf(dev, "Invalid MAC address\n");
1091                         error = EIO;
1092                         goto err_late;
1093                 }
1094         }
1095
1096         /* Disable ULP support */
1097         e1000_disable_ulp_lpt_lp(hw, true);
1098
1099         /*
1100          * Get Wake-on-Lan and Management info for later use
1101          */
1102         em_get_wakeup(ctx);
1103
1104         /* Enable only WOL MAGIC by default */
1105         scctx->isc_capenable &= ~IFCAP_WOL;
1106         if (sc->wol != 0)
1107                 scctx->isc_capenable |= IFCAP_WOL_MAGIC;
1108
1109         iflib_set_mac(ctx, hw->mac.addr);
1110
1111         return (0);
1112
1113 err_late:
1114         em_release_hw_control(sc);
1115 err_pci:
1116         em_free_pci_resources(ctx);
1117         free(sc->mta, M_DEVBUF);
1118
1119         return (error);
1120 }
1121
1122 static int
1123 em_if_attach_post(if_ctx_t ctx)
1124 {
1125         struct e1000_softc *sc = iflib_get_softc(ctx);
1126         struct e1000_hw *hw = &sc->hw;
1127         int error = 0;
1128
1129         /* Setup OS specific network interface */
1130         error = em_setup_interface(ctx);
1131         if (error != 0) {
1132                 device_printf(sc->dev, "Interface setup failed: %d\n", error);
1133                 goto err_late;
1134         }
1135
1136         em_reset(ctx);
1137
1138         /* Initialize statistics */
1139         em_update_stats_counters(sc);
1140         hw->mac.get_link_status = 1;
1141         em_if_update_admin_status(ctx);
1142         em_add_hw_stats(sc);
1143
1144         /* Non-AMT based hardware can now take control from firmware */
1145         if (sc->has_manage && !sc->has_amt)
1146                 em_get_hw_control(sc);
1147
1148         INIT_DEBUGOUT("em_if_attach_post: end");
1149
1150         return (0);
1151
1152 err_late:
1153         /* upon attach_post() error, iflib calls _if_detach() to free resources. */
1154         return (error);
1155 }
1156
1157 /*********************************************************************
1158  *  Device removal routine
1159  *
1160  *  The detach entry point is called when the driver is being removed.
1161  *  This routine stops the adapter and deallocates all the resources
1162  *  that were allocated for driver operation.
1163  *
1164  *  return 0 on success, positive on failure
1165  *********************************************************************/
1166 static int
1167 em_if_detach(if_ctx_t ctx)
1168 {
1169         struct e1000_softc      *sc = iflib_get_softc(ctx);
1170
1171         INIT_DEBUGOUT("em_if_detach: begin");
1172
1173         e1000_phy_hw_reset(&sc->hw);
1174
1175         em_release_manageability(sc);
1176         em_release_hw_control(sc);
1177         em_free_pci_resources(ctx);
1178         free(sc->mta, M_DEVBUF);
1179         sc->mta = NULL;
1180
1181         return (0);
1182 }
1183
1184 /*********************************************************************
1185  *
1186  *  Shutdown entry point
1187  *
1188  **********************************************************************/
1189
1190 static int
1191 em_if_shutdown(if_ctx_t ctx)
1192 {
1193         return em_if_suspend(ctx);
1194 }
1195
1196 /*
1197  * Suspend/resume device methods.
1198  */
1199 static int
1200 em_if_suspend(if_ctx_t ctx)
1201 {
1202         struct e1000_softc *sc = iflib_get_softc(ctx);
1203
1204         em_release_manageability(sc);
1205         em_release_hw_control(sc);
1206         em_enable_wakeup(ctx);
1207         return (0);
1208 }
1209
1210 static int
1211 em_if_resume(if_ctx_t ctx)
1212 {
1213         struct e1000_softc *sc = iflib_get_softc(ctx);
1214
1215         if (sc->hw.mac.type == e1000_pch2lan)
1216                 e1000_resume_workarounds_pchlan(&sc->hw);
1217         em_if_init(ctx);
1218         em_init_manageability(sc);
1219
1220         return(0);
1221 }
1222
1223 static int
1224 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1225 {
1226         int max_frame_size;
1227         struct e1000_softc *sc = iflib_get_softc(ctx);
1228         if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1229
1230         IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1231
1232         switch (sc->hw.mac.type) {
1233         case e1000_82571:
1234         case e1000_82572:
1235         case e1000_ich9lan:
1236         case e1000_ich10lan:
1237         case e1000_pch2lan:
1238         case e1000_pch_lpt:
1239         case e1000_pch_spt:
1240         case e1000_pch_cnp:
1241         case e1000_pch_tgp:
1242         case e1000_pch_adp:
1243         case e1000_pch_mtp:
1244         case e1000_82574:
1245         case e1000_82583:
1246         case e1000_80003es2lan:
1247                 /* 9K Jumbo Frame size */
1248                 max_frame_size = 9234;
1249                 break;
1250         case e1000_pchlan:
1251                 max_frame_size = 4096;
1252                 break;
1253         case e1000_82542:
1254         case e1000_ich8lan:
1255                 /* Adapters that do not support jumbo frames */
1256                 max_frame_size = ETHER_MAX_LEN;
1257                 break;
1258         default:
1259                 if (sc->hw.mac.type >= igb_mac_min)
1260                         max_frame_size = 9234;
1261                 else /* lem */
1262                         max_frame_size = MAX_JUMBO_FRAME_SIZE;
1263         }
1264         if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1265                 return (EINVAL);
1266         }
1267
1268         scctx->isc_max_frame_size = sc->hw.mac.max_frame_size =
1269             mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1270         return (0);
1271 }
1272
1273 /*********************************************************************
1274  *  Init entry point
1275  *
1276  *  This routine is used in two ways. It is used by the stack as
1277  *  init entry point in network interface structure. It is also used
1278  *  by the driver as a hw/sw initialization routine to get to a
1279  *  consistent state.
1280  *
1281  **********************************************************************/
1282 static void
1283 em_if_init(if_ctx_t ctx)
1284 {
1285         struct e1000_softc *sc = iflib_get_softc(ctx);
1286         if_softc_ctx_t scctx = sc->shared;
1287         struct ifnet *ifp = iflib_get_ifp(ctx);
1288         struct em_tx_queue *tx_que;
1289         int i;
1290
1291         INIT_DEBUGOUT("em_if_init: begin");
1292
1293         /* Get the latest mac address, User can use a LAA */
1294         bcopy(if_getlladdr(ifp), sc->hw.mac.addr,
1295             ETHER_ADDR_LEN);
1296
1297         /* Put the address into the Receive Address Array */
1298         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1299
1300         /*
1301          * With the 82571 adapter, RAR[0] may be overwritten
1302          * when the other port is reset, we make a duplicate
1303          * in RAR[14] for that eventuality, this assures
1304          * the interface continues to function.
1305          */
1306         if (sc->hw.mac.type == e1000_82571) {
1307                 e1000_set_laa_state_82571(&sc->hw, true);
1308                 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1309                     E1000_RAR_ENTRIES - 1);
1310         }
1311
1312
1313         /* Initialize the hardware */
1314         em_reset(ctx);
1315         em_if_update_admin_status(ctx);
1316
1317         for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; i++, tx_que++) {
1318                 struct tx_ring *txr = &tx_que->txr;
1319
1320                 txr->tx_rs_cidx = txr->tx_rs_pidx;
1321
1322                 /* Initialize the last processed descriptor to be the end of
1323                  * the ring, rather than the start, so that we avoid an
1324                  * off-by-one error when calculating how many descriptors are
1325                  * done in the credits_update function.
1326                  */
1327                 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
1328         }
1329
1330         /* Setup VLAN support, basic and offload if available */
1331         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1332
1333         /* Clear bad data from Rx FIFOs */
1334         if (sc->hw.mac.type >= igb_mac_min)
1335                 e1000_rx_fifo_flush_base(&sc->hw);
1336
1337         /* Configure for OS presence */
1338         em_init_manageability(sc);
1339
1340         /* Prepare transmit descriptors and buffers */
1341         em_initialize_transmit_unit(ctx);
1342
1343         /* Setup Multicast table */
1344         em_if_multi_set(ctx);
1345
1346         sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx);
1347         em_initialize_receive_unit(ctx);
1348
1349         /* Set up VLAN support and filter */
1350         em_setup_vlan_hw_support(sc);
1351
1352         /* Don't lose promiscuous settings */
1353         em_if_set_promisc(ctx, if_getflags(ifp));
1354         e1000_clear_hw_cntrs_base_generic(&sc->hw);
1355
1356         /* MSI-X configuration for 82574 */
1357         if (sc->hw.mac.type == e1000_82574) {
1358                 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1359
1360                 tmp |= E1000_CTRL_EXT_PBA_CLR;
1361                 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1362                 /* Set the IVAR - interrupt vector routing. */
1363                 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars);
1364         } else if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1365                 igb_configure_queues(sc);
1366
1367         /* this clears any pending interrupts */
1368         E1000_READ_REG(&sc->hw, E1000_ICR);
1369         E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
1370
1371         /* AMT based hardware can now take control from firmware */
1372         if (sc->has_manage && sc->has_amt)
1373                 em_get_hw_control(sc);
1374
1375         /* Set Energy Efficient Ethernet */
1376         if (sc->hw.mac.type >= igb_mac_min &&
1377             sc->hw.phy.media_type == e1000_media_type_copper) {
1378                 if (sc->hw.mac.type == e1000_i354)
1379                         e1000_set_eee_i354(&sc->hw, true, true);
1380                 else
1381                         e1000_set_eee_i350(&sc->hw, true, true);
1382         }
1383 }
1384
1385 /*********************************************************************
1386  *
1387  *  Fast Legacy/MSI Combined Interrupt Service routine
1388  *
1389  *********************************************************************/
1390 int
1391 em_intr(void *arg)
1392 {
1393         struct e1000_softc *sc = arg;
1394         if_ctx_t ctx = sc->ctx;
1395         u32 reg_icr;
1396
1397         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1398
1399         /* Hot eject? */
1400         if (reg_icr == 0xffffffff)
1401                 return FILTER_STRAY;
1402
1403         /* Definitely not our interrupt. */
1404         if (reg_icr == 0x0)
1405                 return FILTER_STRAY;
1406
1407         /*
1408          * Starting with the 82571 chip, bit 31 should be used to
1409          * determine whether the interrupt belongs to us.
1410          */
1411         if (sc->hw.mac.type >= e1000_82571 &&
1412             (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1413                 return FILTER_STRAY;
1414
1415         /*
1416          * Only MSI-X interrupts have one-shot behavior by taking advantage
1417          * of the EIAC register.  Thus, explicitly disable interrupts.  This
1418          * also works around the MSI message reordering errata on certain
1419          * systems.
1420          */
1421         IFDI_INTR_DISABLE(ctx);
1422
1423         /* Link status change */
1424         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))
1425                 em_handle_link(ctx);
1426
1427         if (reg_icr & E1000_ICR_RXO)
1428                 sc->rx_overruns++;
1429
1430         return (FILTER_SCHEDULE_THREAD);
1431 }
1432
1433 static int
1434 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1435 {
1436         struct e1000_softc *sc = iflib_get_softc(ctx);
1437         struct em_rx_queue *rxq = &sc->rx_queues[rxqid];
1438
1439         E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims);
1440         return (0);
1441 }
1442
1443 static int
1444 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1445 {
1446         struct e1000_softc *sc = iflib_get_softc(ctx);
1447         struct em_tx_queue *txq = &sc->tx_queues[txqid];
1448
1449         E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims);
1450         return (0);
1451 }
1452
1453 static int
1454 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1455 {
1456         struct e1000_softc *sc = iflib_get_softc(ctx);
1457         struct em_rx_queue *rxq = &sc->rx_queues[rxqid];
1458
1459         E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims);
1460         return (0);
1461 }
1462
1463 static int
1464 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1465 {
1466         struct e1000_softc *sc = iflib_get_softc(ctx);
1467         struct em_tx_queue *txq = &sc->tx_queues[txqid];
1468
1469         E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims);
1470         return (0);
1471 }
1472
1473 /*********************************************************************
1474  *
1475  *  MSI-X RX Interrupt Service routine
1476  *
1477  **********************************************************************/
1478 static int
1479 em_msix_que(void *arg)
1480 {
1481         struct em_rx_queue *que = arg;
1482
1483         ++que->irqs;
1484
1485         return (FILTER_SCHEDULE_THREAD);
1486 }
1487
1488 /*********************************************************************
1489  *
1490  *  MSI-X Link Fast Interrupt Service routine
1491  *
1492  **********************************************************************/
1493 static int
1494 em_msix_link(void *arg)
1495 {
1496         struct e1000_softc *sc = arg;
1497         u32 reg_icr;
1498
1499         ++sc->link_irq;
1500         MPASS(sc->hw.back != NULL);
1501         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1502
1503         if (reg_icr & E1000_ICR_RXO)
1504                 sc->rx_overruns++;
1505
1506         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))
1507                 em_handle_link(sc->ctx);
1508
1509         /* Re-arm unconditionally */
1510         if (sc->hw.mac.type >= igb_mac_min) {
1511                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
1512                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask);
1513         } else if (sc->hw.mac.type == e1000_82574) {
1514                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC |
1515                     E1000_IMS_OTHER);
1516                 /*
1517                  * Because we must read the ICR for this interrupt it may
1518                  * clear other causes using autoclear, for this reason we
1519                  * simply create a soft interrupt for all these vectors.
1520                  */
1521                 if (reg_icr)
1522                         E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims);
1523         } else
1524                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
1525
1526         return (FILTER_HANDLED);
1527 }
1528
1529 static void
1530 em_handle_link(void *context)
1531 {
1532         if_ctx_t ctx = context;
1533         struct e1000_softc *sc = iflib_get_softc(ctx);
1534
1535         sc->hw.mac.get_link_status = 1;
1536         iflib_admin_intr_deferred(ctx);
1537 }
1538
1539 /*********************************************************************
1540  *
1541  *  Media Ioctl callback
1542  *
1543  *  This routine is called whenever the user queries the status of
1544  *  the interface using ifconfig.
1545  *
1546  **********************************************************************/
1547 static void
1548 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1549 {
1550         struct e1000_softc *sc = iflib_get_softc(ctx);
1551         u_char fiber_type = IFM_1000_SX;
1552
1553         INIT_DEBUGOUT("em_if_media_status: begin");
1554
1555         iflib_admin_intr_deferred(ctx);
1556
1557         ifmr->ifm_status = IFM_AVALID;
1558         ifmr->ifm_active = IFM_ETHER;
1559
1560         if (!sc->link_active) {
1561                 return;
1562         }
1563
1564         ifmr->ifm_status |= IFM_ACTIVE;
1565
1566         if ((sc->hw.phy.media_type == e1000_media_type_fiber) ||
1567             (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1568                 if (sc->hw.mac.type == e1000_82545)
1569                         fiber_type = IFM_1000_LX;
1570                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1571         } else {
1572                 switch (sc->link_speed) {
1573                 case 10:
1574                         ifmr->ifm_active |= IFM_10_T;
1575                         break;
1576                 case 100:
1577                         ifmr->ifm_active |= IFM_100_TX;
1578                         break;
1579                 case 1000:
1580                         ifmr->ifm_active |= IFM_1000_T;
1581                         break;
1582                 }
1583                 if (sc->link_duplex == FULL_DUPLEX)
1584                         ifmr->ifm_active |= IFM_FDX;
1585                 else
1586                         ifmr->ifm_active |= IFM_HDX;
1587         }
1588 }
1589
1590 /*********************************************************************
1591  *
1592  *  Media Ioctl callback
1593  *
1594  *  This routine is called when the user changes speed/duplex using
1595  *  media/mediopt option with ifconfig.
1596  *
1597  **********************************************************************/
1598 static int
1599 em_if_media_change(if_ctx_t ctx)
1600 {
1601         struct e1000_softc *sc = iflib_get_softc(ctx);
1602         struct ifmedia *ifm = iflib_get_media(ctx);
1603
1604         INIT_DEBUGOUT("em_if_media_change: begin");
1605
1606         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1607                 return (EINVAL);
1608
1609         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1610         case IFM_AUTO:
1611                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1612                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1613                 break;
1614         case IFM_1000_LX:
1615         case IFM_1000_SX:
1616         case IFM_1000_T:
1617                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1618                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1619                 break;
1620         case IFM_100_TX:
1621                 sc->hw.mac.autoneg = false;
1622                 sc->hw.phy.autoneg_advertised = 0;
1623                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1624                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1625                 else
1626                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1627                 break;
1628         case IFM_10_T:
1629                 sc->hw.mac.autoneg = false;
1630                 sc->hw.phy.autoneg_advertised = 0;
1631                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1632                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1633                 else
1634                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1635                 break;
1636         default:
1637                 device_printf(sc->dev, "Unsupported media type\n");
1638         }
1639
1640         em_if_init(ctx);
1641
1642         return (0);
1643 }
1644
1645 static int
1646 em_if_set_promisc(if_ctx_t ctx, int flags)
1647 {
1648         struct e1000_softc *sc = iflib_get_softc(ctx);
1649         struct ifnet *ifp = iflib_get_ifp(ctx);
1650         u32 reg_rctl;
1651         int mcnt = 0;
1652
1653         reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1654         reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE);
1655         if (flags & IFF_ALLMULTI)
1656                 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1657         else
1658                 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES);
1659
1660         if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1661                 reg_rctl &= (~E1000_RCTL_MPE);
1662         E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1663
1664         if (flags & IFF_PROMISC) {
1665                 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1666                 em_if_vlan_filter_disable(sc);
1667                 /* Turn this on if you want to see bad packets */
1668                 if (em_debug_sbp)
1669                         reg_rctl |= E1000_RCTL_SBP;
1670                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1671         } else {
1672                 if (flags & IFF_ALLMULTI) {
1673                         reg_rctl |= E1000_RCTL_MPE;
1674                         reg_rctl &= ~E1000_RCTL_UPE;
1675                         E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1676                 }
1677                 if (em_if_vlan_filter_used(sc))
1678                         em_if_vlan_filter_enable(sc);
1679         }
1680         return (0);
1681 }
1682
1683 static u_int
1684 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx)
1685 {
1686         u8 *mta = arg;
1687
1688         if (idx == MAX_NUM_MULTICAST_ADDRESSES)
1689                 return (0);
1690
1691         bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1692
1693         return (1);
1694 }
1695
1696 /*********************************************************************
1697  *  Multicast Update
1698  *
1699  *  This routine is called whenever multicast address list is updated.
1700  *
1701  **********************************************************************/
1702 static void
1703 em_if_multi_set(if_ctx_t ctx)
1704 {
1705         struct e1000_softc *sc = iflib_get_softc(ctx);
1706         struct ifnet *ifp = iflib_get_ifp(ctx);
1707         u8  *mta; /* Multicast array memory */
1708         u32 reg_rctl = 0;
1709         int mcnt = 0;
1710
1711         IOCTL_DEBUGOUT("em_set_multi: begin");
1712
1713         mta = sc->mta;
1714         bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1715
1716         if (sc->hw.mac.type == e1000_82542 &&
1717             sc->hw.revision_id == E1000_REVISION_2) {
1718                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1719                 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1720                         e1000_pci_clear_mwi(&sc->hw);
1721                 reg_rctl |= E1000_RCTL_RST;
1722                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1723                 msec_delay(5);
1724         }
1725
1726         mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta);
1727
1728         reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1729
1730         if (if_getflags(ifp) & IFF_PROMISC)
1731                 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1732         else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES ||
1733             if_getflags(ifp) & IFF_ALLMULTI) {
1734                 reg_rctl |= E1000_RCTL_MPE;
1735                 reg_rctl &= ~E1000_RCTL_UPE;
1736         } else
1737                 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
1738
1739         E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1740
1741         if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1742                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1743
1744         if (sc->hw.mac.type == e1000_82542 &&
1745             sc->hw.revision_id == E1000_REVISION_2) {
1746                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1747                 reg_rctl &= ~E1000_RCTL_RST;
1748                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1749                 msec_delay(5);
1750                 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1751                         e1000_pci_set_mwi(&sc->hw);
1752         }
1753 }
1754
1755 /*********************************************************************
1756  *  Timer routine
1757  *
1758  *  This routine schedules em_if_update_admin_status() to check for
1759  *  link status and to gather statistics as well as to perform some
1760  *  controller-specific hardware patting.
1761  *
1762  **********************************************************************/
1763 static void
1764 em_if_timer(if_ctx_t ctx, uint16_t qid)
1765 {
1766
1767         if (qid != 0)
1768                 return;
1769
1770         iflib_admin_intr_deferred(ctx);
1771 }
1772
1773 static void
1774 em_if_update_admin_status(if_ctx_t ctx)
1775 {
1776         struct e1000_softc *sc = iflib_get_softc(ctx);
1777         struct e1000_hw *hw = &sc->hw;
1778         device_t dev = iflib_get_dev(ctx);
1779         u32 link_check, thstat, ctrl;
1780
1781         link_check = thstat = ctrl = 0;
1782         /* Get the cached link value or read phy for real */
1783         switch (hw->phy.media_type) {
1784         case e1000_media_type_copper:
1785                 if (hw->mac.get_link_status) {
1786                         if (hw->mac.type == e1000_pch_spt)
1787                                 msec_delay(50);
1788                         /* Do the work to read phy */
1789                         e1000_check_for_link(hw);
1790                         link_check = !hw->mac.get_link_status;
1791                         if (link_check) /* ESB2 fix */
1792                                 e1000_cfg_on_link_up(hw);
1793                 } else {
1794                         link_check = true;
1795                 }
1796                 break;
1797         case e1000_media_type_fiber:
1798                 e1000_check_for_link(hw);
1799                 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1800                             E1000_STATUS_LU);
1801                 break;
1802         case e1000_media_type_internal_serdes:
1803                 e1000_check_for_link(hw);
1804                 link_check = hw->mac.serdes_has_link;
1805                 break;
1806         /* VF device is type_unknown */
1807         case e1000_media_type_unknown:
1808                 e1000_check_for_link(hw);
1809                 link_check = !hw->mac.get_link_status;
1810                 /* FALLTHROUGH */
1811         default:
1812                 break;
1813         }
1814
1815         /* Check for thermal downshift or shutdown */
1816         if (hw->mac.type == e1000_i350) {
1817                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1818                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1819         }
1820
1821         /* Now check for a transition */
1822         if (link_check && (sc->link_active == 0)) {
1823                 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1824                     &sc->link_duplex);
1825                 /* Check if we must disable SPEED_MODE bit on PCI-E */
1826                 if ((sc->link_speed != SPEED_1000) &&
1827                     ((hw->mac.type == e1000_82571) ||
1828                     (hw->mac.type == e1000_82572))) {
1829                         int tarc0;
1830                         tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1831                         tarc0 &= ~TARC_SPEED_MODE_BIT;
1832                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1833                 }
1834                 if (bootverbose)
1835                         device_printf(dev, "Link is up %d Mbps %s\n",
1836                             sc->link_speed,
1837                             ((sc->link_duplex == FULL_DUPLEX) ?
1838                             "Full Duplex" : "Half Duplex"));
1839                 sc->link_active = 1;
1840                 sc->smartspeed = 0;
1841                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) ==
1842                     E1000_CTRL_EXT_LINK_MODE_GMII &&
1843                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1844                         device_printf(dev, "Link: thermal downshift\n");
1845                 /* Delay Link Up for Phy update */
1846                 if (((hw->mac.type == e1000_i210) ||
1847                     (hw->mac.type == e1000_i211)) &&
1848                     (hw->phy.id == I210_I_PHY_ID))
1849                         msec_delay(I210_LINK_DELAY);
1850                 /* Reset if the media type changed. */
1851                 if (hw->dev_spec._82575.media_changed &&
1852                     hw->mac.type >= igb_mac_min) {
1853                         hw->dev_spec._82575.media_changed = false;
1854                         sc->flags |= IGB_MEDIA_RESET;
1855                         em_reset(ctx);
1856                 }
1857                 iflib_link_state_change(ctx, LINK_STATE_UP,
1858                     IF_Mbps(sc->link_speed));
1859         } else if (!link_check && (sc->link_active == 1)) {
1860                 sc->link_speed = 0;
1861                 sc->link_duplex = 0;
1862                 sc->link_active = 0;
1863                 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
1864         }
1865         em_update_stats_counters(sc);
1866
1867         /* Reset LAA into RAR[0] on 82571 */
1868         if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw))
1869                 e1000_rar_set(hw, hw->mac.addr, 0);
1870
1871         if (hw->mac.type < em_mac_min)
1872                 lem_smartspeed(sc);
1873 }
1874
1875 static void
1876 em_if_watchdog_reset(if_ctx_t ctx)
1877 {
1878         struct e1000_softc *sc = iflib_get_softc(ctx);
1879
1880         /*
1881          * Just count the event; iflib(4) will already trigger a
1882          * sufficient reset of the controller.
1883          */
1884         sc->watchdog_events++;
1885 }
1886
1887 /*********************************************************************
1888  *
1889  *  This routine disables all traffic on the adapter by issuing a
1890  *  global reset on the MAC.
1891  *
1892  **********************************************************************/
1893 static void
1894 em_if_stop(if_ctx_t ctx)
1895 {
1896         struct e1000_softc *sc = iflib_get_softc(ctx);
1897
1898         INIT_DEBUGOUT("em_if_stop: begin");
1899
1900         e1000_reset_hw(&sc->hw);
1901         if (sc->hw.mac.type >= e1000_82544)
1902                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0);
1903
1904         e1000_led_off(&sc->hw);
1905         e1000_cleanup_led(&sc->hw);
1906 }
1907
1908 /*********************************************************************
1909  *
1910  *  Determine hardware revision.
1911  *
1912  **********************************************************************/
1913 static void
1914 em_identify_hardware(if_ctx_t ctx)
1915 {
1916         device_t dev = iflib_get_dev(ctx);
1917         struct e1000_softc *sc = iflib_get_softc(ctx);
1918
1919         /* Make sure our PCI config space has the necessary stuff set */
1920         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1921
1922         /* Save off the information about this board */
1923         sc->hw.vendor_id = pci_get_vendor(dev);
1924         sc->hw.device_id = pci_get_device(dev);
1925         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1926         sc->hw.subsystem_vendor_id =
1927             pci_read_config(dev, PCIR_SUBVEND_0, 2);
1928         sc->hw.subsystem_device_id =
1929             pci_read_config(dev, PCIR_SUBDEV_0, 2);
1930
1931         /* Do Shared Code Init and Setup */
1932         if (e1000_set_mac_type(&sc->hw)) {
1933                 device_printf(dev, "Setup init failure\n");
1934                 return;
1935         }
1936
1937         /* Are we a VF device? */
1938         if ((sc->hw.mac.type == e1000_vfadapt) ||
1939             (sc->hw.mac.type == e1000_vfadapt_i350))
1940                 sc->vf_ifp = 1;
1941         else
1942                 sc->vf_ifp = 0;
1943 }
1944
1945 static int
1946 em_allocate_pci_resources(if_ctx_t ctx)
1947 {
1948         struct e1000_softc *sc = iflib_get_softc(ctx);
1949         device_t dev = iflib_get_dev(ctx);
1950         int rid, val;
1951
1952         rid = PCIR_BAR(0);
1953         sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1954             &rid, RF_ACTIVE);
1955         if (sc->memory == NULL) {
1956                 device_printf(dev, "Unable to allocate bus resource: memory\n");
1957                 return (ENXIO);
1958         }
1959         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
1960         sc->osdep.mem_bus_space_handle =
1961             rman_get_bushandle(sc->memory);
1962         sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle;
1963
1964         /* Only older adapters use IO mapping */
1965         if (sc->hw.mac.type < em_mac_min &&
1966             sc->hw.mac.type > e1000_82543) {
1967                 /* Figure our where our IO BAR is ? */
1968                 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1969                         val = pci_read_config(dev, rid, 4);
1970                         if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1971                                 break;
1972                         }
1973                         rid += 4;
1974                         /* check for 64bit BAR */
1975                         if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1976                                 rid += 4;
1977                 }
1978                 if (rid >= PCIR_CIS) {
1979                         device_printf(dev, "Unable to locate IO BAR\n");
1980                         return (ENXIO);
1981                 }
1982                 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
1983                     &rid, RF_ACTIVE);
1984                 if (sc->ioport == NULL) {
1985                         device_printf(dev, "Unable to allocate bus resource: "
1986                             "ioport\n");
1987                         return (ENXIO);
1988                 }
1989                 sc->hw.io_base = 0;
1990                 sc->osdep.io_bus_space_tag =
1991                     rman_get_bustag(sc->ioport);
1992                 sc->osdep.io_bus_space_handle =
1993                     rman_get_bushandle(sc->ioport);
1994         }
1995
1996         sc->hw.back = &sc->osdep;
1997
1998         return (0);
1999 }
2000
2001 /*********************************************************************
2002  *
2003  *  Set up the MSI-X Interrupt handlers
2004  *
2005  **********************************************************************/
2006 static int
2007 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
2008 {
2009         struct e1000_softc *sc = iflib_get_softc(ctx);
2010         struct em_rx_queue *rx_que = sc->rx_queues;
2011         struct em_tx_queue *tx_que = sc->tx_queues;
2012         int error, rid, i, vector = 0, rx_vectors;
2013         char buf[16];
2014
2015         /* First set up ring resources */
2016         for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) {
2017                 rid = vector + 1;
2018                 snprintf(buf, sizeof(buf), "rxq%d", i);
2019                 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
2020                 if (error) {
2021                         device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
2022                         sc->rx_num_queues = i + 1;
2023                         goto fail;
2024                 }
2025
2026                 rx_que->msix =  vector;
2027
2028                 /*
2029                  * Set the bit to enable interrupt
2030                  * in E1000_IMS -- bits 20 and 21
2031                  * are for RX0 and RX1, note this has
2032                  * NOTHING to do with the MSI-X vector
2033                  */
2034                 if (sc->hw.mac.type == e1000_82574) {
2035                         rx_que->eims = 1 << (20 + i);
2036                         sc->ims |= rx_que->eims;
2037                         sc->ivars |= (8 | rx_que->msix) << (i * 4);
2038                 } else if (sc->hw.mac.type == e1000_82575)
2039                         rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
2040                 else
2041                         rx_que->eims = 1 << vector;
2042         }
2043         rx_vectors = vector;
2044
2045         vector = 0;
2046         for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) {
2047                 snprintf(buf, sizeof(buf), "txq%d", i);
2048                 tx_que = &sc->tx_queues[i];
2049                 iflib_softirq_alloc_generic(ctx,
2050                     &sc->rx_queues[i % sc->rx_num_queues].que_irq,
2051                     IFLIB_INTR_TX, tx_que, tx_que->me, buf);
2052
2053                 tx_que->msix = (vector % sc->rx_num_queues);
2054
2055                 /*
2056                  * Set the bit to enable interrupt
2057                  * in E1000_IMS -- bits 22 and 23
2058                  * are for TX0 and TX1, note this has
2059                  * NOTHING to do with the MSI-X vector
2060                  */
2061                 if (sc->hw.mac.type == e1000_82574) {
2062                         tx_que->eims = 1 << (22 + i);
2063                         sc->ims |= tx_que->eims;
2064                         sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
2065                 } else if (sc->hw.mac.type == e1000_82575) {
2066                         tx_que->eims = E1000_EICR_TX_QUEUE0 << i;
2067                 } else {
2068                         tx_que->eims = 1 << i;
2069                 }
2070         }
2071
2072         /* Link interrupt */
2073         rid = rx_vectors + 1;
2074         error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, sc, 0, "aq");
2075
2076         if (error) {
2077                 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
2078                 goto fail;
2079         }
2080         sc->linkvec = rx_vectors;
2081         if (sc->hw.mac.type < igb_mac_min) {
2082                 sc->ivars |=  (8 | rx_vectors) << 16;
2083                 sc->ivars |= 0x80000000;
2084                 /* Enable the "Other" interrupt type for link status change */
2085                 sc->ims |= E1000_IMS_OTHER;
2086         }
2087
2088         return (0);
2089 fail:
2090         iflib_irq_free(ctx, &sc->irq);
2091         rx_que = sc->rx_queues;
2092         for (int i = 0; i < sc->rx_num_queues; i++, rx_que++)
2093                 iflib_irq_free(ctx, &rx_que->que_irq);
2094         return (error);
2095 }
2096
2097 static void
2098 igb_configure_queues(struct e1000_softc *sc)
2099 {
2100         struct e1000_hw *hw = &sc->hw;
2101         struct em_rx_queue *rx_que;
2102         struct em_tx_queue *tx_que;
2103         u32 tmp, ivar = 0, newitr = 0;
2104
2105         /* First turn on RSS capability */
2106         if (hw->mac.type != e1000_82575)
2107                 E1000_WRITE_REG(hw, E1000_GPIE,
2108                     E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
2109                     E1000_GPIE_PBA | E1000_GPIE_NSICR);
2110
2111         /* Turn on MSI-X */
2112         switch (hw->mac.type) {
2113         case e1000_82580:
2114         case e1000_i350:
2115         case e1000_i354:
2116         case e1000_i210:
2117         case e1000_i211:
2118         case e1000_vfadapt:
2119         case e1000_vfadapt_i350:
2120                 /* RX entries */
2121                 for (int i = 0; i < sc->rx_num_queues; i++) {
2122                         u32 index = i >> 1;
2123                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2124                         rx_que = &sc->rx_queues[i];
2125                         if (i & 1) {
2126                                 ivar &= 0xFF00FFFF;
2127                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2128                         } else {
2129                                 ivar &= 0xFFFFFF00;
2130                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2131                         }
2132                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2133                 }
2134                 /* TX entries */
2135                 for (int i = 0; i < sc->tx_num_queues; i++) {
2136                         u32 index = i >> 1;
2137                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2138                         tx_que = &sc->tx_queues[i];
2139                         if (i & 1) {
2140                                 ivar &= 0x00FFFFFF;
2141                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2142                         } else {
2143                                 ivar &= 0xFFFF00FF;
2144                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2145                         }
2146                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2147                         sc->que_mask |= tx_que->eims;
2148                 }
2149
2150                 /* And for the link interrupt */
2151                 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8;
2152                 sc->link_mask = 1 << sc->linkvec;
2153                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2154                 break;
2155         case e1000_82576:
2156                 /* RX entries */
2157                 for (int i = 0; i < sc->rx_num_queues; i++) {
2158                         u32 index = i & 0x7; /* Each IVAR has two entries */
2159                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2160                         rx_que = &sc->rx_queues[i];
2161                         if (i < 8) {
2162                                 ivar &= 0xFFFFFF00;
2163                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2164                         } else {
2165                                 ivar &= 0xFF00FFFF;
2166                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2167                         }
2168                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2169                         sc->que_mask |= rx_que->eims;
2170                 }
2171                 /* TX entries */
2172                 for (int i = 0; i < sc->tx_num_queues; i++) {
2173                         u32 index = i & 0x7; /* Each IVAR has two entries */
2174                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2175                         tx_que = &sc->tx_queues[i];
2176                         if (i < 8) {
2177                                 ivar &= 0xFFFF00FF;
2178                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2179                         } else {
2180                                 ivar &= 0x00FFFFFF;
2181                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2182                         }
2183                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2184                         sc->que_mask |= tx_que->eims;
2185                 }
2186
2187                 /* And for the link interrupt */
2188                 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8;
2189                 sc->link_mask = 1 << sc->linkvec;
2190                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2191                 break;
2192
2193         case e1000_82575:
2194                 /* enable MSI-X support*/
2195                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2196                 tmp |= E1000_CTRL_EXT_PBA_CLR;
2197                 /* Auto-Mask interrupts upon ICR read. */
2198                 tmp |= E1000_CTRL_EXT_EIAME;
2199                 tmp |= E1000_CTRL_EXT_IRCA;
2200                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2201
2202                 /* Queues */
2203                 for (int i = 0; i < sc->rx_num_queues; i++) {
2204                         rx_que = &sc->rx_queues[i];
2205                         tmp = E1000_EICR_RX_QUEUE0 << i;
2206                         tmp |= E1000_EICR_TX_QUEUE0 << i;
2207                         rx_que->eims = tmp;
2208                         E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2209                             i, rx_que->eims);
2210                         sc->que_mask |= rx_que->eims;
2211                 }
2212
2213                 /* Link */
2214                 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec),
2215                     E1000_EIMS_OTHER);
2216                 sc->link_mask |= E1000_EIMS_OTHER;
2217         default:
2218                 break;
2219         }
2220
2221         /* Set the starting interrupt rate */
2222         if (em_max_interrupt_rate > 0)
2223                 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2224
2225         if (hw->mac.type == e1000_82575)
2226                 newitr |= newitr << 16;
2227         else
2228                 newitr |= E1000_EITR_CNT_IGNR;
2229
2230         for (int i = 0; i < sc->rx_num_queues; i++) {
2231                 rx_que = &sc->rx_queues[i];
2232                 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2233         }
2234
2235         return;
2236 }
2237
2238 static void
2239 em_free_pci_resources(if_ctx_t ctx)
2240 {
2241         struct e1000_softc *sc = iflib_get_softc(ctx);
2242         struct em_rx_queue *que = sc->rx_queues;
2243         device_t dev = iflib_get_dev(ctx);
2244
2245         /* Release all MSI-X queue resources */
2246         if (sc->intr_type == IFLIB_INTR_MSIX)
2247                 iflib_irq_free(ctx, &sc->irq);
2248
2249         if (que != NULL) {
2250                 for (int i = 0; i < sc->rx_num_queues; i++, que++) {
2251                         iflib_irq_free(ctx, &que->que_irq);
2252                 }
2253         }
2254
2255         if (sc->memory != NULL) {
2256                 bus_release_resource(dev, SYS_RES_MEMORY,
2257                     rman_get_rid(sc->memory), sc->memory);
2258                 sc->memory = NULL;
2259         }
2260
2261         if (sc->flash != NULL) {
2262                 bus_release_resource(dev, SYS_RES_MEMORY,
2263                     rman_get_rid(sc->flash), sc->flash);
2264                 sc->flash = NULL;
2265         }
2266
2267         if (sc->ioport != NULL) {
2268                 bus_release_resource(dev, SYS_RES_IOPORT,
2269                     rman_get_rid(sc->ioport), sc->ioport);
2270                 sc->ioport = NULL;
2271         }
2272 }
2273
2274 /* Set up MSI or MSI-X */
2275 static int
2276 em_setup_msix(if_ctx_t ctx)
2277 {
2278         struct e1000_softc *sc = iflib_get_softc(ctx);
2279
2280         if (sc->hw.mac.type == e1000_82574) {
2281                 em_enable_vectors_82574(ctx);
2282         }
2283         return (0);
2284 }
2285
2286 /*********************************************************************
2287  *
2288  *  Workaround for SmartSpeed on 82541 and 82547 controllers
2289  *
2290  **********************************************************************/
2291 static void
2292 lem_smartspeed(struct e1000_softc *sc)
2293 {
2294         u16 phy_tmp;
2295
2296         if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) ||
2297             sc->hw.mac.autoneg == 0 ||
2298             (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2299                 return;
2300
2301         if (sc->smartspeed == 0) {
2302                 /* If Master/Slave config fault is asserted twice,
2303                  * we assume back-to-back */
2304                 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2305                 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2306                         return;
2307                 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2308                 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2309                         e1000_read_phy_reg(&sc->hw,
2310                             PHY_1000T_CTRL, &phy_tmp);
2311                         if(phy_tmp & CR_1000T_MS_ENABLE) {
2312                                 phy_tmp &= ~CR_1000T_MS_ENABLE;
2313                                 e1000_write_phy_reg(&sc->hw,
2314                                     PHY_1000T_CTRL, phy_tmp);
2315                                 sc->smartspeed++;
2316                                 if(sc->hw.mac.autoneg &&
2317                                    !e1000_copper_link_autoneg(&sc->hw) &&
2318                                    !e1000_read_phy_reg(&sc->hw,
2319                                     PHY_CONTROL, &phy_tmp)) {
2320                                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2321                                                     MII_CR_RESTART_AUTO_NEG);
2322                                         e1000_write_phy_reg(&sc->hw,
2323                                             PHY_CONTROL, phy_tmp);
2324                                 }
2325                         }
2326                 }
2327                 return;
2328         } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2329                 /* If still no link, perhaps using 2/3 pair cable */
2330                 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
2331                 phy_tmp |= CR_1000T_MS_ENABLE;
2332                 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
2333                 if(sc->hw.mac.autoneg &&
2334                    !e1000_copper_link_autoneg(&sc->hw) &&
2335                    !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
2336                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2337                                     MII_CR_RESTART_AUTO_NEG);
2338                         e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
2339                 }
2340         }
2341         /* Restart process after EM_SMARTSPEED_MAX iterations */
2342         if(sc->smartspeed++ == EM_SMARTSPEED_MAX)
2343                 sc->smartspeed = 0;
2344 }
2345
2346 /*********************************************************************
2347  *
2348  *  Initialize the DMA Coalescing feature
2349  *
2350  **********************************************************************/
2351 static void
2352 igb_init_dmac(struct e1000_softc *sc, u32 pba)
2353 {
2354         device_t        dev = sc->dev;
2355         struct e1000_hw *hw = &sc->hw;
2356         u32             dmac, reg = ~E1000_DMACR_DMAC_EN;
2357         u16             hwm;
2358         u16             max_frame_size;
2359
2360         if (hw->mac.type == e1000_i211)
2361                 return;
2362
2363         max_frame_size = sc->shared->isc_max_frame_size;
2364         if (hw->mac.type > e1000_82580) {
2365
2366                 if (sc->dmac == 0) { /* Disabling it */
2367                         E1000_WRITE_REG(hw, E1000_DMACR, reg);
2368                         return;
2369                 } else
2370                         device_printf(dev, "DMA Coalescing enabled\n");
2371
2372                 /* Set starting threshold */
2373                 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
2374
2375                 hwm = 64 * pba - max_frame_size / 16;
2376                 if (hwm < 64 * (pba - 6))
2377                         hwm = 64 * (pba - 6);
2378                 reg = E1000_READ_REG(hw, E1000_FCRTC);
2379                 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
2380                 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
2381                     & E1000_FCRTC_RTH_COAL_MASK);
2382                 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
2383
2384
2385                 dmac = pba - max_frame_size / 512;
2386                 if (dmac < pba - 10)
2387                         dmac = pba - 10;
2388                 reg = E1000_READ_REG(hw, E1000_DMACR);
2389                 reg &= ~E1000_DMACR_DMACTHR_MASK;
2390                 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT)
2391                     & E1000_DMACR_DMACTHR_MASK);
2392
2393                 /* transition to L0x or L1 if available..*/
2394                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
2395
2396                 /* Check if status is 2.5Gb backplane connection
2397                 * before configuration of watchdog timer, which is
2398                 * in msec values in 12.8usec intervals
2399                 * watchdog timer= msec values in 32usec intervals
2400                 * for non 2.5Gb connection
2401                 */
2402                 if (hw->mac.type == e1000_i354) {
2403                         int status = E1000_READ_REG(hw, E1000_STATUS);
2404                         if ((status & E1000_STATUS_2P5_SKU) &&
2405                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2406                                 reg |= ((sc->dmac * 5) >> 6);
2407                         else
2408                                 reg |= (sc->dmac >> 5);
2409                 } else {
2410                         reg |= (sc->dmac >> 5);
2411                 }
2412
2413                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2414
2415                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
2416
2417                 /* Set the interval before transition */
2418                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
2419                 if (hw->mac.type == e1000_i350)
2420                         reg |= IGB_DMCTLX_DCFLUSH_DIS;
2421                 /*
2422                 ** in 2.5Gb connection, TTLX unit is 0.4 usec
2423                 ** which is 0x4*2 = 0xA. But delay is still 4 usec
2424                 */
2425                 if (hw->mac.type == e1000_i354) {
2426                         int status = E1000_READ_REG(hw, E1000_STATUS);
2427                         if ((status & E1000_STATUS_2P5_SKU) &&
2428                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2429                                 reg |= 0xA;
2430                         else
2431                                 reg |= 0x4;
2432                 } else {
2433                         reg |= 0x4;
2434                 }
2435
2436                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
2437
2438                 /* free space in tx packet buffer to wake from DMA coal */
2439                 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE -
2440                     (2 * max_frame_size)) >> 6);
2441
2442                 /* make low power state decision controlled by DMA coal */
2443                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2444                 reg &= ~E1000_PCIEMISC_LX_DECISION;
2445                 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
2446
2447         } else if (hw->mac.type == e1000_82580) {
2448                 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2449                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
2450                     reg & ~E1000_PCIEMISC_LX_DECISION);
2451                 E1000_WRITE_REG(hw, E1000_DMACR, 0);
2452         }
2453 }
2454
2455 /*********************************************************************
2456  *
2457  *  Initialize the hardware to a configuration as specified by the
2458  *  sc structure.
2459  *
2460  **********************************************************************/
2461 static void
2462 em_reset(if_ctx_t ctx)
2463 {
2464         device_t dev = iflib_get_dev(ctx);
2465         struct e1000_softc *sc = iflib_get_softc(ctx);
2466         struct ifnet *ifp = iflib_get_ifp(ctx);
2467         struct e1000_hw *hw = &sc->hw;
2468         u16 rx_buffer_size;
2469         u32 pba;
2470
2471         INIT_DEBUGOUT("em_reset: begin");
2472         /* Let the firmware know the OS is in control */
2473         em_get_hw_control(sc);
2474
2475         /* Set up smart power down as default off on newer adapters. */
2476         if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2477             hw->mac.type == e1000_82572)) {
2478                 u16 phy_tmp = 0;
2479
2480                 /* Speed up time to link by disabling smart power down. */
2481                 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2482                 phy_tmp &= ~IGP02E1000_PM_SPD;
2483                 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2484         }
2485
2486         /*
2487          * Packet Buffer Allocation (PBA)
2488          * Writing PBA sets the receive portion of the buffer
2489          * the remainder is used for the transmit buffer.
2490          */
2491         switch (hw->mac.type) {
2492         /* 82547: Total Packet Buffer is 40K */
2493         case e1000_82547:
2494         case e1000_82547_rev_2:
2495                 if (hw->mac.max_frame_size > 8192)
2496                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
2497                 else
2498                         pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
2499                 break;
2500         /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */
2501         case e1000_82571:
2502         case e1000_82572:
2503         case e1000_80003es2lan:
2504                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2505                 break;
2506         /* 82573: Total Packet Buffer is 32K */
2507         case e1000_82573:
2508                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2509                 break;
2510         case e1000_82574:
2511         case e1000_82583:
2512                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2513                 break;
2514         case e1000_ich8lan:
2515                 pba = E1000_PBA_8K;
2516                 break;
2517         case e1000_ich9lan:
2518         case e1000_ich10lan:
2519                 /* Boost Receive side for jumbo frames */
2520                 if (hw->mac.max_frame_size > 4096)
2521                         pba = E1000_PBA_14K;
2522                 else
2523                         pba = E1000_PBA_10K;
2524                 break;
2525         case e1000_pchlan:
2526         case e1000_pch2lan:
2527         case e1000_pch_lpt:
2528         case e1000_pch_spt:
2529         case e1000_pch_cnp:
2530         case e1000_pch_tgp:
2531         case e1000_pch_adp:
2532         case e1000_pch_mtp:
2533                 pba = E1000_PBA_26K;
2534                 break;
2535         case e1000_82575:
2536                 pba = E1000_PBA_32K;
2537                 break;
2538         case e1000_82576:
2539         case e1000_vfadapt:
2540                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2541                 pba &= E1000_RXPBS_SIZE_MASK_82576;
2542                 break;
2543         case e1000_82580:
2544         case e1000_i350:
2545         case e1000_i354:
2546         case e1000_vfadapt_i350:
2547                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2548                 pba = e1000_rxpbs_adjust_82580(pba);
2549                 break;
2550         case e1000_i210:
2551         case e1000_i211:
2552                 pba = E1000_PBA_34K;
2553                 break;
2554         default:
2555                 /* Remaining devices assumed to have a Packet Buffer of 64K. */
2556                 if (hw->mac.max_frame_size > 8192)
2557                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2558                 else
2559                         pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2560         }
2561
2562         /* Special needs in case of Jumbo frames */
2563         if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) {
2564                 u32 tx_space, min_tx, min_rx;
2565                 pba = E1000_READ_REG(hw, E1000_PBA);
2566                 tx_space = pba >> 16;
2567                 pba &= 0xffff;
2568                 min_tx = (hw->mac.max_frame_size +
2569                     sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
2570                 min_tx = roundup2(min_tx, 1024);
2571                 min_tx >>= 10;
2572                 min_rx = hw->mac.max_frame_size;
2573                 min_rx = roundup2(min_rx, 1024);
2574                 min_rx >>= 10;
2575                 if (tx_space < min_tx &&
2576                     ((min_tx - tx_space) < pba)) {
2577                         pba = pba - (min_tx - tx_space);
2578                         /*
2579                          * if short on rx space, rx wins
2580                          * and must trump tx adjustment
2581                          */
2582                         if (pba < min_rx)
2583                                 pba = min_rx;
2584                 }
2585                 E1000_WRITE_REG(hw, E1000_PBA, pba);
2586         }
2587
2588         if (hw->mac.type < igb_mac_min)
2589                 E1000_WRITE_REG(hw, E1000_PBA, pba);
2590
2591         INIT_DEBUGOUT1("em_reset: pba=%dK",pba);
2592
2593         /*
2594          * These parameters control the automatic generation (Tx) and
2595          * response (Rx) to Ethernet PAUSE frames.
2596          * - High water mark should allow for at least two frames to be
2597          *   received after sending an XOFF.
2598          * - Low water mark works best when it is very near the high water mark.
2599          *   This allows the receiver to restart by sending XON when it has
2600          *   drained a bit. Here we use an arbitrary value of 1500 which will
2601          *   restart after one full frame is pulled from the buffer. There
2602          *   could be several smaller frames in the buffer and if so they will
2603          *   not trigger the XON until their total number reduces the buffer
2604          *   by 1500.
2605          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2606          */
2607         rx_buffer_size = (pba & 0xffff) << 10;
2608         hw->fc.high_water = rx_buffer_size -
2609             roundup2(hw->mac.max_frame_size, 1024);
2610         hw->fc.low_water = hw->fc.high_water - 1500;
2611
2612         if (sc->fc) /* locally set flow control value? */
2613                 hw->fc.requested_mode = sc->fc;
2614         else
2615                 hw->fc.requested_mode = e1000_fc_full;
2616
2617         if (hw->mac.type == e1000_80003es2lan)
2618                 hw->fc.pause_time = 0xFFFF;
2619         else
2620                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
2621
2622         hw->fc.send_xon = true;
2623
2624         /* Device specific overrides/settings */
2625         switch (hw->mac.type) {
2626         case e1000_pchlan:
2627                 /* Workaround: no TX flow ctrl for PCH */
2628                 hw->fc.requested_mode = e1000_fc_rx_pause;
2629                 hw->fc.pause_time = 0xFFFF; /* override */
2630                 if (if_getmtu(ifp) > ETHERMTU) {
2631                         hw->fc.high_water = 0x3500;
2632                         hw->fc.low_water = 0x1500;
2633                 } else {
2634                         hw->fc.high_water = 0x5000;
2635                         hw->fc.low_water = 0x3000;
2636                 }
2637                 hw->fc.refresh_time = 0x1000;
2638                 break;
2639         case e1000_pch2lan:
2640         case e1000_pch_lpt:
2641         case e1000_pch_spt:
2642         case e1000_pch_cnp:
2643         case e1000_pch_tgp:
2644         case e1000_pch_adp:
2645         case e1000_pch_mtp:
2646                 hw->fc.high_water = 0x5C20;
2647                 hw->fc.low_water = 0x5048;
2648                 hw->fc.pause_time = 0x0650;
2649                 hw->fc.refresh_time = 0x0400;
2650                 /* Jumbos need adjusted PBA */
2651                 if (if_getmtu(ifp) > ETHERMTU)
2652                         E1000_WRITE_REG(hw, E1000_PBA, 12);
2653                 else
2654                         E1000_WRITE_REG(hw, E1000_PBA, 26);
2655                 break;
2656         case e1000_82575:
2657         case e1000_82576:
2658                 /* 8-byte granularity */
2659                 hw->fc.low_water = hw->fc.high_water - 8;
2660                 break;
2661         case e1000_82580:
2662         case e1000_i350:
2663         case e1000_i354:
2664         case e1000_i210:
2665         case e1000_i211:
2666         case e1000_vfadapt:
2667         case e1000_vfadapt_i350:
2668                 /* 16-byte granularity */
2669                 hw->fc.low_water = hw->fc.high_water - 16;
2670                 break;
2671         case e1000_ich9lan:
2672         case e1000_ich10lan:
2673                 if (if_getmtu(ifp) > ETHERMTU) {
2674                         hw->fc.high_water = 0x2800;
2675                         hw->fc.low_water = hw->fc.high_water - 8;
2676                         break;
2677                 }
2678                 /* FALLTHROUGH */
2679         default:
2680                 if (hw->mac.type == e1000_80003es2lan)
2681                         hw->fc.pause_time = 0xFFFF;
2682                 break;
2683         }
2684
2685         /* Issue a global reset */
2686         e1000_reset_hw(hw);
2687         if (hw->mac.type >= igb_mac_min) {
2688                 E1000_WRITE_REG(hw, E1000_WUC, 0);
2689         } else {
2690                 E1000_WRITE_REG(hw, E1000_WUFC, 0);
2691                 em_disable_aspm(sc);
2692         }
2693         if (sc->flags & IGB_MEDIA_RESET) {
2694                 e1000_setup_init_funcs(hw, true);
2695                 e1000_get_bus_info(hw);
2696                 sc->flags &= ~IGB_MEDIA_RESET;
2697         }
2698         /* and a re-init */
2699         if (e1000_init_hw(hw) < 0) {
2700                 device_printf(dev, "Hardware Initialization Failed\n");
2701                 return;
2702         }
2703         if (hw->mac.type >= igb_mac_min)
2704                 igb_init_dmac(sc, pba);
2705
2706         E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2707         e1000_get_phy_info(hw);
2708         e1000_check_for_link(hw);
2709 }
2710
2711 /*
2712  * Initialise the RSS mapping for NICs that support multiple transmit/
2713  * receive rings.
2714  */
2715
2716 #define RSSKEYLEN 10
2717 static void
2718 em_initialize_rss_mapping(struct e1000_softc *sc)
2719 {
2720         uint8_t  rss_key[4 * RSSKEYLEN];
2721         uint32_t reta = 0;
2722         struct e1000_hw *hw = &sc->hw;
2723         int i;
2724
2725         /*
2726          * Configure RSS key
2727          */
2728         arc4rand(rss_key, sizeof(rss_key), 0);
2729         for (i = 0; i < RSSKEYLEN; ++i) {
2730                 uint32_t rssrk = 0;
2731
2732                 rssrk = EM_RSSRK_VAL(rss_key, i);
2733                 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2734         }
2735
2736         /*
2737          * Configure RSS redirect table in following fashion:
2738          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2739          */
2740         for (i = 0; i < sizeof(reta); ++i) {
2741                 uint32_t q;
2742
2743                 q = (i % sc->rx_num_queues) << 7;
2744                 reta |= q << (8 * i);
2745         }
2746
2747         for (i = 0; i < 32; ++i)
2748                 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2749
2750         E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2751                         E1000_MRQC_RSS_FIELD_IPV4_TCP |
2752                         E1000_MRQC_RSS_FIELD_IPV4 |
2753                         E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2754                         E1000_MRQC_RSS_FIELD_IPV6_EX |
2755                         E1000_MRQC_RSS_FIELD_IPV6);
2756 }
2757
2758 static void
2759 igb_initialize_rss_mapping(struct e1000_softc *sc)
2760 {
2761         struct e1000_hw *hw = &sc->hw;
2762         int i;
2763         int queue_id;
2764         u32 reta;
2765         u32 rss_key[10], mrqc, shift = 0;
2766
2767         /* XXX? */
2768         if (hw->mac.type == e1000_82575)
2769                 shift = 6;
2770
2771         /*
2772          * The redirection table controls which destination
2773          * queue each bucket redirects traffic to.
2774          * Each DWORD represents four queues, with the LSB
2775          * being the first queue in the DWORD.
2776          *
2777          * This just allocates buckets to queues using round-robin
2778          * allocation.
2779          *
2780          * NOTE: It Just Happens to line up with the default
2781          * RSS allocation method.
2782          */
2783
2784         /* Warning FM follows */
2785         reta = 0;
2786         for (i = 0; i < 128; i++) {
2787 #ifdef RSS
2788                 queue_id = rss_get_indirection_to_bucket(i);
2789                 /*
2790                  * If we have more queues than buckets, we'll
2791                  * end up mapping buckets to a subset of the
2792                  * queues.
2793                  *
2794                  * If we have more buckets than queues, we'll
2795                  * end up instead assigning multiple buckets
2796                  * to queues.
2797                  *
2798                  * Both are suboptimal, but we need to handle
2799                  * the case so we don't go out of bounds
2800                  * indexing arrays and such.
2801                  */
2802                 queue_id = queue_id % sc->rx_num_queues;
2803 #else
2804                 queue_id = (i % sc->rx_num_queues);
2805 #endif
2806                 /* Adjust if required */
2807                 queue_id = queue_id << shift;
2808
2809                 /*
2810                  * The low 8 bits are for hash value (n+0);
2811                  * The next 8 bits are for hash value (n+1), etc.
2812                  */
2813                 reta = reta >> 8;
2814                 reta = reta | ( ((uint32_t) queue_id) << 24);
2815                 if ((i & 3) == 3) {
2816                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2817                         reta = 0;
2818                 }
2819         }
2820
2821         /* Now fill in hash table */
2822
2823         /*
2824          * MRQC: Multiple Receive Queues Command
2825          * Set queuing to RSS control, number depends on the device.
2826          */
2827         mrqc = E1000_MRQC_ENABLE_RSS_MQ;
2828
2829 #ifdef RSS
2830         /* XXX ew typecasting */
2831         rss_getkey((uint8_t *) &rss_key);
2832 #else
2833         arc4rand(&rss_key, sizeof(rss_key), 0);
2834 #endif
2835         for (i = 0; i < 10; i++)
2836                 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]);
2837
2838         /*
2839          * Configure the RSS fields to hash upon.
2840          */
2841         mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2842             E1000_MRQC_RSS_FIELD_IPV4_TCP);
2843         mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2844             E1000_MRQC_RSS_FIELD_IPV6_TCP);
2845         mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2846             E1000_MRQC_RSS_FIELD_IPV6_UDP);
2847         mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2848             E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2849
2850         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2851 }
2852
2853 /*********************************************************************
2854  *
2855  *  Setup networking device structure and register interface media.
2856  *
2857  **********************************************************************/
2858 static int
2859 em_setup_interface(if_ctx_t ctx)
2860 {
2861         struct ifnet *ifp = iflib_get_ifp(ctx);
2862         struct e1000_softc *sc = iflib_get_softc(ctx);
2863         if_softc_ctx_t scctx = sc->shared;
2864
2865         INIT_DEBUGOUT("em_setup_interface: begin");
2866
2867         /* Single Queue */
2868         if (sc->tx_num_queues == 1) {
2869                 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
2870                 if_setsendqready(ifp);
2871         }
2872
2873         /*
2874          * Specify the media types supported by this adapter and register
2875          * callbacks to update media and link information
2876          */
2877         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2878             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
2879                 u_char fiber_type = IFM_1000_SX;        /* default type */
2880
2881                 if (sc->hw.mac.type == e1000_82545)
2882                         fiber_type = IFM_1000_LX;
2883                 ifmedia_add(sc->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
2884                 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL);
2885         } else {
2886                 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
2887                 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2888                 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2889                 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2890                 if (sc->hw.phy.type != e1000_phy_ife) {
2891                         ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2892                         ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2893                 }
2894         }
2895         ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2896         ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO);
2897         return (0);
2898 }
2899
2900 static int
2901 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
2902 {
2903         struct e1000_softc *sc = iflib_get_softc(ctx);
2904         if_softc_ctx_t scctx = sc->shared;
2905         int error = E1000_SUCCESS;
2906         struct em_tx_queue *que;
2907         int i, j;
2908
2909         MPASS(sc->tx_num_queues > 0);
2910         MPASS(sc->tx_num_queues == ntxqsets);
2911
2912         /* First allocate the top level queue structs */
2913         if (!(sc->tx_queues =
2914             (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
2915             sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2916                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2917                 return(ENOMEM);
2918         }
2919
2920         for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) {
2921                 /* Set up some basics */
2922
2923                 struct tx_ring *txr = &que->txr;
2924                 txr->sc = que->sc = sc;
2925                 que->me = txr->me =  i;
2926
2927                 /* Allocate report status array */
2928                 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2929                         device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n");
2930                         error = ENOMEM;
2931                         goto fail;
2932                 }
2933                 for (j = 0; j < scctx->isc_ntxd[0]; j++)
2934                         txr->tx_rsq[j] = QIDX_INVALID;
2935                 /* get the virtual and physical address of the hardware queues */
2936                 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
2937                 txr->tx_paddr = paddrs[i*ntxqs];
2938         }
2939
2940         if (bootverbose)
2941                 device_printf(iflib_get_dev(ctx),
2942                     "allocated for %d tx_queues\n", sc->tx_num_queues);
2943         return (0);
2944 fail:
2945         em_if_queues_free(ctx);
2946         return (error);
2947 }
2948
2949 static int
2950 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
2951 {
2952         struct e1000_softc *sc = iflib_get_softc(ctx);
2953         int error = E1000_SUCCESS;
2954         struct em_rx_queue *que;
2955         int i;
2956
2957         MPASS(sc->rx_num_queues > 0);
2958         MPASS(sc->rx_num_queues == nrxqsets);
2959
2960         /* First allocate the top level queue structs */
2961         if (!(sc->rx_queues =
2962             (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
2963             sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2964                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2965                 error = ENOMEM;
2966                 goto fail;
2967         }
2968
2969         for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) {
2970                 /* Set up some basics */
2971                 struct rx_ring *rxr = &que->rxr;
2972                 rxr->sc = que->sc = sc;
2973                 rxr->que = que;
2974                 que->me = rxr->me =  i;
2975
2976                 /* get the virtual and physical address of the hardware queues */
2977                 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
2978                 rxr->rx_paddr = paddrs[i*nrxqs];
2979         }
2980
2981         if (bootverbose)
2982                 device_printf(iflib_get_dev(ctx),
2983                     "allocated for %d rx_queues\n", sc->rx_num_queues);
2984
2985         return (0);
2986 fail:
2987         em_if_queues_free(ctx);
2988         return (error);
2989 }
2990
2991 static void
2992 em_if_queues_free(if_ctx_t ctx)
2993 {
2994         struct e1000_softc *sc = iflib_get_softc(ctx);
2995         struct em_tx_queue *tx_que = sc->tx_queues;
2996         struct em_rx_queue *rx_que = sc->rx_queues;
2997
2998         if (tx_que != NULL) {
2999                 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) {
3000                         struct tx_ring *txr = &tx_que->txr;
3001                         if (txr->tx_rsq == NULL)
3002                                 break;
3003
3004                         free(txr->tx_rsq, M_DEVBUF);
3005                         txr->tx_rsq = NULL;
3006                 }
3007                 free(sc->tx_queues, M_DEVBUF);
3008                 sc->tx_queues = NULL;
3009         }
3010
3011         if (rx_que != NULL) {
3012                 free(sc->rx_queues, M_DEVBUF);
3013                 sc->rx_queues = NULL;
3014         }
3015 }
3016
3017 /*********************************************************************
3018  *
3019  *  Enable transmit unit.
3020  *
3021  **********************************************************************/
3022 static void
3023 em_initialize_transmit_unit(if_ctx_t ctx)
3024 {
3025         struct e1000_softc *sc = iflib_get_softc(ctx);
3026         if_softc_ctx_t scctx = sc->shared;
3027         struct em_tx_queue *que;
3028         struct tx_ring  *txr;
3029         struct e1000_hw *hw = &sc->hw;
3030         u32 tctl, txdctl = 0, tarc, tipg = 0;
3031
3032         INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
3033
3034         for (int i = 0; i < sc->tx_num_queues; i++, txr++) {
3035                 u64 bus_addr;
3036                 caddr_t offp, endp;
3037
3038                 que = &sc->tx_queues[i];
3039                 txr = &que->txr;
3040                 bus_addr = txr->tx_paddr;
3041
3042                 /* Clear checksum offload context. */
3043                 offp = (caddr_t)&txr->csum_flags;
3044                 endp = (caddr_t)(txr + 1);
3045                 bzero(offp, endp - offp);
3046
3047                 /* Base and Len of TX Ring */
3048                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
3049                     scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
3050                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
3051                     (u32)(bus_addr >> 32));
3052                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
3053                     (u32)bus_addr);
3054                 /* Init the HEAD/TAIL indices */
3055                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
3056                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
3057
3058                 HW_DEBUGOUT2("Base = %x, Length = %x\n",
3059                     E1000_READ_REG(hw, E1000_TDBAL(i)),
3060                     E1000_READ_REG(hw, E1000_TDLEN(i)));
3061
3062                 txdctl = 0; /* clear txdctl */
3063                 txdctl |= 0x1f; /* PTHRESH */
3064                 txdctl |= 1 << 8; /* HTHRESH */
3065                 txdctl |= 1 << 16;/* WTHRESH */
3066                 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
3067                 txdctl |= E1000_TXDCTL_GRAN;
3068                 txdctl |= 1 << 25; /* LWTHRESH */
3069
3070                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
3071         }
3072
3073         /* Set the default values for the Tx Inter Packet Gap timer */
3074         switch (hw->mac.type) {
3075         case e1000_80003es2lan:
3076                 tipg = DEFAULT_82543_TIPG_IPGR1;
3077                 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
3078                     E1000_TIPG_IPGR2_SHIFT;
3079                 break;
3080         case e1000_82542:
3081                 tipg = DEFAULT_82542_TIPG_IPGT;
3082                 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3083                 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3084                 break;
3085         default:
3086                 if (hw->phy.media_type == e1000_media_type_fiber ||
3087                     hw->phy.media_type == e1000_media_type_internal_serdes)
3088                         tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
3089                 else
3090                         tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
3091                 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3092                 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3093         }
3094
3095         E1000_WRITE_REG(hw, E1000_TIPG, tipg);
3096         E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value);
3097
3098         if(hw->mac.type >= e1000_82540)
3099                 E1000_WRITE_REG(hw, E1000_TADV,
3100                     sc->tx_abs_int_delay.value);
3101
3102         if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) {
3103                 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3104                 tarc |= TARC_SPEED_MODE_BIT;
3105                 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3106         } else if (hw->mac.type == e1000_80003es2lan) {
3107                 /* errata: program both queues to unweighted RR */
3108                 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3109                 tarc |= 1;
3110                 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3111                 tarc = E1000_READ_REG(hw, E1000_TARC(1));
3112                 tarc |= 1;
3113                 E1000_WRITE_REG(hw, E1000_TARC(1), tarc);
3114         } else if (hw->mac.type == e1000_82574) {
3115                 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3116                 tarc |= TARC_ERRATA_BIT;
3117                 if ( sc->tx_num_queues > 1) {
3118                         tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
3119                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3120                         E1000_WRITE_REG(hw, E1000_TARC(1), tarc);
3121                 } else
3122                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3123         }
3124
3125         if (sc->tx_int_delay.value > 0)
3126                 sc->txd_cmd |= E1000_TXD_CMD_IDE;
3127
3128         /* Program the Transmit Control Register */
3129         tctl = E1000_READ_REG(hw, E1000_TCTL);
3130         tctl &= ~E1000_TCTL_CT;
3131         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
3132                    (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
3133
3134         if (hw->mac.type >= e1000_82571)
3135                 tctl |= E1000_TCTL_MULR;
3136
3137         /* This write will effectively turn on the transmit unit. */
3138         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
3139
3140         /* SPT and KBL errata workarounds */
3141         if (hw->mac.type == e1000_pch_spt) {
3142                 u32 reg;
3143                 reg = E1000_READ_REG(hw, E1000_IOSFPC);
3144                 reg |= E1000_RCTL_RDMTS_HEX;
3145                 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
3146                 /* i218-i219 Specification Update 1.5.4.5 */
3147                 reg = E1000_READ_REG(hw, E1000_TARC(0));
3148                 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3149                 reg |= E1000_TARC0_CB_MULTIQ_2_REQ;
3150                 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3151         }
3152 }
3153
3154 /*********************************************************************
3155  *
3156  *  Enable receive unit.
3157  *
3158  **********************************************************************/
3159 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1)
3160
3161 static void
3162 em_initialize_receive_unit(if_ctx_t ctx)
3163 {
3164         struct e1000_softc *sc = iflib_get_softc(ctx);
3165         if_softc_ctx_t scctx = sc->shared;
3166         struct ifnet *ifp = iflib_get_ifp(ctx);
3167         struct e1000_hw *hw = &sc->hw;
3168         struct em_rx_queue *que;
3169         int i;
3170         uint32_t rctl, rxcsum;
3171
3172         INIT_DEBUGOUT("em_initialize_receive_units: begin");
3173
3174         /*
3175          * Make sure receives are disabled while setting
3176          * up the descriptor ring
3177          */
3178         rctl = E1000_READ_REG(hw, E1000_RCTL);
3179         /* Do not disable if ever enabled on this hardware */
3180         if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
3181                 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3182
3183         /* Setup the Receive Control Register */
3184         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3185         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3186             E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3187             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3188
3189         /* Do not store bad packets */
3190         rctl &= ~E1000_RCTL_SBP;
3191
3192         /* Enable Long Packet receive */
3193         if (if_getmtu(ifp) > ETHERMTU)
3194                 rctl |= E1000_RCTL_LPE;
3195         else
3196                 rctl &= ~E1000_RCTL_LPE;
3197
3198         /* Strip the CRC */
3199         if (!em_disable_crc_stripping)
3200                 rctl |= E1000_RCTL_SECRC;
3201
3202         if (hw->mac.type >= e1000_82540) {
3203                 E1000_WRITE_REG(hw, E1000_RADV,
3204                     sc->rx_abs_int_delay.value);
3205
3206                 /*
3207                  * Set the interrupt throttling rate. Value is calculated
3208                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
3209                  */
3210                 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
3211         }
3212         E1000_WRITE_REG(hw, E1000_RDTR, sc->rx_int_delay.value);
3213
3214         if (hw->mac.type >= em_mac_min) {
3215                 uint32_t rfctl;
3216                 /* Use extended rx descriptor formats */
3217                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3218                 rfctl |= E1000_RFCTL_EXTEN;
3219
3220                 /*
3221                  * When using MSI-X interrupts we need to throttle
3222                  * using the EITR register (82574 only)
3223                  */
3224                 if (hw->mac.type == e1000_82574) {
3225                         for (int i = 0; i < 4; i++)
3226                                 E1000_WRITE_REG(hw, E1000_EITR_82574(i),
3227                                     DEFAULT_ITR);
3228                         /* Disable accelerated acknowledge */
3229                         rfctl |= E1000_RFCTL_ACK_DIS;
3230                 }
3231                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3232         }
3233
3234         /* Set up L3 and L4 csum Rx descriptor offloads */
3235         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
3236         if (scctx->isc_capenable & IFCAP_RXCSUM) {
3237                 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
3238                 if (hw->mac.type > e1000_82575)
3239                         rxcsum |= E1000_RXCSUM_CRCOFL;
3240                 else if (hw->mac.type < em_mac_min &&
3241                     scctx->isc_capenable & IFCAP_HWCSUM_IPV6)
3242                         rxcsum |= E1000_RXCSUM_IPV6OFL;
3243         } else {
3244                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
3245                 if (hw->mac.type > e1000_82575)
3246                         rxcsum &= ~E1000_RXCSUM_CRCOFL;
3247                 else if (hw->mac.type < em_mac_min)
3248                         rxcsum &= ~E1000_RXCSUM_IPV6OFL;
3249         }
3250
3251         if (sc->rx_num_queues > 1) {
3252                 /* RSS hash needed in the Rx descriptor */
3253                 rxcsum |= E1000_RXCSUM_PCSD;
3254
3255                 if (hw->mac.type >= igb_mac_min)
3256                         igb_initialize_rss_mapping(sc);
3257                 else
3258                         em_initialize_rss_mapping(sc);
3259         }
3260         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
3261
3262         /*
3263          * XXX TEMPORARY WORKAROUND: on some systems with 82573
3264          * long latencies are observed, like Lenovo X60. This
3265          * change eliminates the problem, but since having positive
3266          * values in RDTR is a known source of problems on other
3267          * platforms another solution is being sought.
3268          */
3269         if (hw->mac.type == e1000_82573)
3270                 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
3271
3272         for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) {
3273                 struct rx_ring *rxr = &que->rxr;
3274                 /* Setup the Base and Length of the Rx Descriptor Ring */
3275                 u64 bus_addr = rxr->rx_paddr;
3276 #if 0
3277                 u32 rdt = sc->rx_num_queues -1;  /* default */
3278 #endif
3279
3280                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3281                     scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
3282                 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
3283                 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
3284                 /* Setup the Head and Tail Descriptor Pointers */
3285                 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
3286                 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
3287         }
3288
3289         /*
3290          * Set PTHRESH for improved jumbo performance
3291          * According to 10.2.5.11 of Intel 82574 Datasheet,
3292          * RXDCTL(1) is written whenever RXDCTL(0) is written.
3293          * Only write to RXDCTL(1) if there is a need for different
3294          * settings.
3295          */
3296         if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan ||
3297             hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) {
3298                 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
3299                 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
3300         } else if (hw->mac.type == e1000_82574) {
3301                 for (int i = 0; i < sc->rx_num_queues; i++) {
3302                         u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3303                         rxdctl |= 0x20; /* PTHRESH */
3304                         rxdctl |= 4 << 8; /* HTHRESH */
3305                         rxdctl |= 4 << 16;/* WTHRESH */
3306                         rxdctl |= 1 << 24; /* Switch to granularity */
3307                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3308                 }
3309         } else if (hw->mac.type >= igb_mac_min) {
3310                 u32 psize, srrctl = 0;
3311
3312                 if (if_getmtu(ifp) > ETHERMTU) {
3313                         psize = scctx->isc_max_frame_size;
3314                         /* are we on a vlan? */
3315                         if (ifp->if_vlantrunk != NULL)
3316                                 psize += VLAN_TAG_SIZE;
3317
3318                         if (sc->vf_ifp)
3319                                 e1000_rlpml_set_vf(hw, psize);
3320                         else
3321                                 E1000_WRITE_REG(hw, E1000_RLPML, psize);
3322                 }
3323
3324                 /* Set maximum packet buffer len */
3325                 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >>
3326                     E1000_SRRCTL_BSIZEPKT_SHIFT;
3327
3328                 /*
3329                  * If TX flow control is disabled and there's >1 queue defined,
3330                  * enable DROP.
3331                  *
3332                  * This drops frames rather than hanging the RX MAC for all queues.
3333                  */
3334                 if ((sc->rx_num_queues > 1) &&
3335                     (sc->fc == e1000_fc_none ||
3336                      sc->fc == e1000_fc_rx_pause)) {
3337                         srrctl |= E1000_SRRCTL_DROP_EN;
3338                 }
3339                         /* Setup the Base and Length of the Rx Descriptor Rings */
3340                 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) {
3341                         struct rx_ring *rxr = &que->rxr;
3342                         u64 bus_addr = rxr->rx_paddr;
3343                         u32 rxdctl;
3344
3345 #ifdef notyet
3346                         /* Configure for header split? -- ignore for now */
3347                         rxr->hdr_split = igb_header_split;
3348 #else
3349                         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3350 #endif
3351
3352                         E1000_WRITE_REG(hw, E1000_RDLEN(i),
3353                                         scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3354                         E1000_WRITE_REG(hw, E1000_RDBAH(i),
3355                                         (uint32_t)(bus_addr >> 32));
3356                         E1000_WRITE_REG(hw, E1000_RDBAL(i),
3357                                         (uint32_t)bus_addr);
3358                         E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3359                         /* Enable this Queue */
3360                         rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3361                         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3362                         rxdctl &= 0xFFF00000;
3363                         rxdctl |= IGB_RX_PTHRESH;
3364                         rxdctl |= IGB_RX_HTHRESH << 8;
3365                         rxdctl |= IGB_RX_WTHRESH << 16;
3366                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3367                 }
3368         } else if (hw->mac.type >= e1000_pch2lan) {
3369                 if (if_getmtu(ifp) > ETHERMTU)
3370                         e1000_lv_jumbo_workaround_ich8lan(hw, true);
3371                 else
3372                         e1000_lv_jumbo_workaround_ich8lan(hw, false);
3373         }
3374
3375         /* Make sure VLAN Filters are off */
3376         rctl &= ~E1000_RCTL_VFE;
3377
3378         /* Set up packet buffer size, overridden by per queue srrctl on igb */
3379         if (hw->mac.type < igb_mac_min) {
3380                 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096)
3381                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3382                 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192)
3383                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3384                 else if (sc->rx_mbuf_sz > 8192)
3385                         rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX;
3386                 else {
3387                         rctl |= E1000_RCTL_SZ_2048;
3388                         rctl &= ~E1000_RCTL_BSEX;
3389                 }
3390         } else
3391                 rctl |= E1000_RCTL_SZ_2048;
3392
3393         /*
3394          * rctl bits 11:10 are as follows
3395          * lem: reserved
3396          * em: DTYPE
3397          * igb: reserved
3398          * and should be 00 on all of the above
3399          */
3400         rctl &= ~0x00000C00;
3401
3402         /* Write out the settings */
3403         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3404
3405         return;
3406 }
3407
3408 static void
3409 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3410 {
3411         struct e1000_softc *sc = iflib_get_softc(ctx);
3412         u32 index, bit;
3413
3414         index = (vtag >> 5) & 0x7F;
3415         bit = vtag & 0x1F;
3416         sc->shadow_vfta[index] |= (1 << bit);
3417         ++sc->num_vlans;
3418         em_if_vlan_filter_write(sc);
3419 }
3420
3421 static void
3422 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3423 {
3424         struct e1000_softc *sc = iflib_get_softc(ctx);
3425         u32 index, bit;
3426
3427         index = (vtag >> 5) & 0x7F;
3428         bit = vtag & 0x1F;
3429         sc->shadow_vfta[index] &= ~(1 << bit);
3430         --sc->num_vlans;
3431         em_if_vlan_filter_write(sc);
3432 }
3433
3434 static bool
3435 em_if_vlan_filter_capable(struct e1000_softc *sc)
3436 {
3437         if_softc_ctx_t scctx = sc->shared;
3438
3439         if ((scctx->isc_capenable & IFCAP_VLAN_HWFILTER) &&
3440             !em_disable_crc_stripping)
3441                 return (true);
3442
3443         return (false);
3444 }
3445
3446 static bool
3447 em_if_vlan_filter_used(struct e1000_softc *sc)
3448 {
3449         if (!em_if_vlan_filter_capable(sc))
3450                 return (false);
3451
3452         for (int i = 0; i < EM_VFTA_SIZE; i++)
3453                 if (sc->shadow_vfta[i] != 0)
3454                         return (true);
3455
3456         return (false);
3457 }
3458
3459 static void
3460 em_if_vlan_filter_enable(struct e1000_softc *sc)
3461 {
3462         struct e1000_hw *hw = &sc->hw;
3463         u32 reg;
3464
3465         reg = E1000_READ_REG(hw, E1000_RCTL);
3466         reg &= ~E1000_RCTL_CFIEN;
3467         reg |= E1000_RCTL_VFE;
3468         E1000_WRITE_REG(hw, E1000_RCTL, reg);
3469 }
3470
3471 static void
3472 em_if_vlan_filter_disable(struct e1000_softc *sc)
3473 {
3474         struct e1000_hw *hw = &sc->hw;
3475         u32 reg;
3476
3477         reg = E1000_READ_REG(hw, E1000_RCTL);
3478         reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
3479         E1000_WRITE_REG(hw, E1000_RCTL, reg);
3480 }
3481
3482 static void
3483 em_if_vlan_filter_write(struct e1000_softc *sc)
3484 {
3485         struct e1000_hw *hw = &sc->hw;
3486
3487         if (sc->vf_ifp)
3488                 return;
3489
3490         /* Disable interrupts for lem-class devices during the filter change */
3491         if (hw->mac.type < em_mac_min)
3492                 em_if_intr_disable(sc->ctx);
3493
3494         for (int i = 0; i < EM_VFTA_SIZE; i++)
3495                 if (sc->shadow_vfta[i] != 0) {
3496                         /* XXXKB: incomplete VF support, we return early above */
3497                         if (sc->vf_ifp)
3498                                 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], true);
3499                         else
3500                                 e1000_write_vfta(hw, i, sc->shadow_vfta[i]);
3501                 }
3502
3503         /* Re-enable interrupts for lem-class devices */
3504         if (hw->mac.type < em_mac_min)
3505                 em_if_intr_enable(sc->ctx);
3506 }
3507
3508 static void
3509 em_setup_vlan_hw_support(struct e1000_softc *sc)
3510 {
3511         if_softc_ctx_t scctx = sc->shared;
3512         struct e1000_hw *hw = &sc->hw;
3513         u32 reg;
3514
3515         /* XXXKB: Return early if we are a VF until VF decap and filter management
3516          * is ready and tested.
3517          */
3518         if (sc->vf_ifp)
3519                 return;
3520
3521         if (scctx->isc_capenable & IFCAP_VLAN_HWTAGGING &&
3522             !em_disable_crc_stripping) {
3523                 reg = E1000_READ_REG(hw, E1000_CTRL);
3524                 reg |= E1000_CTRL_VME;
3525                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
3526         } else {
3527                 reg = E1000_READ_REG(hw, E1000_CTRL);
3528                 reg &= ~E1000_CTRL_VME;
3529                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
3530         }
3531
3532         /* If we aren't doing HW filtering, we're done */
3533         if (!em_if_vlan_filter_capable(sc))  {
3534                 em_if_vlan_filter_disable(sc);
3535                 return;
3536         }
3537
3538         /*
3539          * A soft reset zero's out the VFTA, so
3540          * we need to repopulate it now.
3541          */
3542         em_if_vlan_filter_write(sc);
3543
3544         /* Enable the Filter Table */
3545         em_if_vlan_filter_enable(sc);
3546 }
3547
3548 static void
3549 em_if_intr_enable(if_ctx_t ctx)
3550 {
3551         struct e1000_softc *sc = iflib_get_softc(ctx);
3552         struct e1000_hw *hw = &sc->hw;
3553         u32 ims_mask = IMS_ENABLE_MASK;
3554
3555         if (sc->intr_type == IFLIB_INTR_MSIX) {
3556                 E1000_WRITE_REG(hw, EM_EIAC, sc->ims);
3557                 ims_mask |= sc->ims;
3558         }
3559         E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3560         E1000_WRITE_FLUSH(hw);
3561 }
3562
3563 static void
3564 em_if_intr_disable(if_ctx_t ctx)
3565 {
3566         struct e1000_softc *sc = iflib_get_softc(ctx);
3567         struct e1000_hw *hw = &sc->hw;
3568
3569         if (sc->intr_type == IFLIB_INTR_MSIX)
3570                 E1000_WRITE_REG(hw, EM_EIAC, 0);
3571         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3572         E1000_WRITE_FLUSH(hw);
3573 }
3574
3575 static void
3576 igb_if_intr_enable(if_ctx_t ctx)
3577 {
3578         struct e1000_softc *sc = iflib_get_softc(ctx);
3579         struct e1000_hw *hw = &sc->hw;
3580         u32 mask;
3581
3582         if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) {
3583                 mask = (sc->que_mask | sc->link_mask);
3584                 E1000_WRITE_REG(hw, E1000_EIAC, mask);
3585                 E1000_WRITE_REG(hw, E1000_EIAM, mask);
3586                 E1000_WRITE_REG(hw, E1000_EIMS, mask);
3587                 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
3588         } else
3589                 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
3590         E1000_WRITE_FLUSH(hw);
3591 }
3592
3593 static void
3594 igb_if_intr_disable(if_ctx_t ctx)
3595 {
3596         struct e1000_softc *sc = iflib_get_softc(ctx);
3597         struct e1000_hw *hw = &sc->hw;
3598
3599         if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) {
3600                 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff);
3601                 E1000_WRITE_REG(hw, E1000_EIAC, 0);
3602         }
3603         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3604         E1000_WRITE_FLUSH(hw);
3605 }
3606
3607 /*
3608  * Bit of a misnomer, what this really means is
3609  * to enable OS management of the system... aka
3610  * to disable special hardware management features
3611  */
3612 static void
3613 em_init_manageability(struct e1000_softc *sc)
3614 {
3615         /* A shared code workaround */
3616 #define E1000_82542_MANC2H E1000_MANC2H
3617         if (sc->has_manage) {
3618                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3619                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3620
3621                 /* disable hardware interception of ARP */
3622                 manc &= ~(E1000_MANC_ARP_EN);
3623
3624                 /* enable receiving management packets to the host */
3625                 manc |= E1000_MANC_EN_MNG2HOST;
3626 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3627 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3628                 manc2h |= E1000_MNG2HOST_PORT_623;
3629                 manc2h |= E1000_MNG2HOST_PORT_664;
3630                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3631                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3632         }
3633 }
3634
3635 /*
3636  * Give control back to hardware management
3637  * controller if there is one.
3638  */
3639 static void
3640 em_release_manageability(struct e1000_softc *sc)
3641 {
3642         if (sc->has_manage) {
3643                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3644
3645                 /* re-enable hardware interception of ARP */
3646                 manc |= E1000_MANC_ARP_EN;
3647                 manc &= ~E1000_MANC_EN_MNG2HOST;
3648
3649                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3650         }
3651 }
3652
3653 /*
3654  * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3655  * For ASF and Pass Through versions of f/w this means
3656  * that the driver is loaded. For AMT version type f/w
3657  * this means that the network i/f is open.
3658  */
3659 static void
3660 em_get_hw_control(struct e1000_softc *sc)
3661 {
3662         u32 ctrl_ext, swsm;
3663
3664         if (sc->vf_ifp)
3665                 return;
3666
3667         if (sc->hw.mac.type == e1000_82573) {
3668                 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3669                 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3670                     swsm | E1000_SWSM_DRV_LOAD);
3671                 return;
3672         }
3673         /* else */
3674         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3675         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3676             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3677 }
3678
3679 /*
3680  * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3681  * For ASF and Pass Through versions of f/w this means that
3682  * the driver is no longer loaded. For AMT versions of the
3683  * f/w this means that the network i/f is closed.
3684  */
3685 static void
3686 em_release_hw_control(struct e1000_softc *sc)
3687 {
3688         u32 ctrl_ext, swsm;
3689
3690         if (!sc->has_manage)
3691                 return;
3692
3693         if (sc->hw.mac.type == e1000_82573) {
3694                 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3695                 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3696                     swsm & ~E1000_SWSM_DRV_LOAD);
3697                 return;
3698         }
3699         /* else */
3700         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3701         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3702             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3703         return;
3704 }
3705
3706 static int
3707 em_is_valid_ether_addr(u8 *addr)
3708 {
3709         char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3710
3711         if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3712                 return (false);
3713         }
3714
3715         return (true);
3716 }
3717
3718 /*
3719 ** Parse the interface capabilities with regard
3720 ** to both system management and wake-on-lan for
3721 ** later use.
3722 */
3723 static void
3724 em_get_wakeup(if_ctx_t ctx)
3725 {
3726         struct e1000_softc *sc = iflib_get_softc(ctx);
3727         device_t dev = iflib_get_dev(ctx);
3728         u16 eeprom_data = 0, device_id, apme_mask;
3729
3730         sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
3731         apme_mask = EM_EEPROM_APME;
3732
3733         switch (sc->hw.mac.type) {
3734         case e1000_82542:
3735         case e1000_82543:
3736                 break;
3737         case e1000_82544:
3738                 e1000_read_nvm(&sc->hw,
3739                     NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3740                 apme_mask = EM_82544_APME;
3741                 break;
3742         case e1000_82546:
3743         case e1000_82546_rev_3:
3744                 if (sc->hw.bus.func == 1) {
3745                         e1000_read_nvm(&sc->hw,
3746                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3747                         break;
3748                 } else
3749                         e1000_read_nvm(&sc->hw,
3750                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3751                 break;
3752         case e1000_82573:
3753         case e1000_82583:
3754                 sc->has_amt = true;
3755                 /* FALLTHROUGH */
3756         case e1000_82571:
3757         case e1000_82572:
3758         case e1000_80003es2lan:
3759                 if (sc->hw.bus.func == 1) {
3760                         e1000_read_nvm(&sc->hw,
3761                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3762                         break;
3763                 } else
3764                         e1000_read_nvm(&sc->hw,
3765                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3766                 break;
3767         case e1000_ich8lan:
3768         case e1000_ich9lan:
3769         case e1000_ich10lan:
3770         case e1000_pchlan:
3771         case e1000_pch2lan:
3772         case e1000_pch_lpt:
3773         case e1000_pch_spt:
3774         case e1000_82575:       /* listing all igb devices */
3775         case e1000_82576:
3776         case e1000_82580:
3777         case e1000_i350:
3778         case e1000_i354:
3779         case e1000_i210:
3780         case e1000_i211:
3781         case e1000_vfadapt:
3782         case e1000_vfadapt_i350:
3783                 apme_mask = E1000_WUC_APME;
3784                 sc->has_amt = true;
3785                 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC);
3786                 break;
3787         default:
3788                 e1000_read_nvm(&sc->hw,
3789                     NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3790                 break;
3791         }
3792         if (eeprom_data & apme_mask)
3793                 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
3794         /*
3795          * We have the eeprom settings, now apply the special cases
3796          * where the eeprom may be wrong or the board won't support
3797          * wake on lan on a particular port
3798          */
3799         device_id = pci_get_device(dev);
3800         switch (device_id) {
3801         case E1000_DEV_ID_82546GB_PCIE:
3802                 sc->wol = 0;
3803                 break;
3804         case E1000_DEV_ID_82546EB_FIBER:
3805         case E1000_DEV_ID_82546GB_FIBER:
3806                 /* Wake events only supported on port A for dual fiber
3807                  * regardless of eeprom setting */
3808                 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
3809                     E1000_STATUS_FUNC_1)
3810                         sc->wol = 0;
3811                 break;
3812         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
3813                 /* if quad port adapter, disable WoL on all but port A */
3814                 if (global_quad_port_a != 0)
3815                         sc->wol = 0;
3816                 /* Reset for multiple quad port adapters */
3817                 if (++global_quad_port_a == 4)
3818                         global_quad_port_a = 0;
3819                 break;
3820         case E1000_DEV_ID_82571EB_FIBER:
3821                 /* Wake events only supported on port A for dual fiber
3822                  * regardless of eeprom setting */
3823                 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
3824                     E1000_STATUS_FUNC_1)
3825                         sc->wol = 0;
3826                 break;
3827         case E1000_DEV_ID_82571EB_QUAD_COPPER:
3828         case E1000_DEV_ID_82571EB_QUAD_FIBER:
3829         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
3830                 /* if quad port adapter, disable WoL on all but port A */
3831                 if (global_quad_port_a != 0)
3832                         sc->wol = 0;
3833                 /* Reset for multiple quad port adapters */
3834                 if (++global_quad_port_a == 4)
3835                         global_quad_port_a = 0;
3836                 break;
3837         }
3838         return;
3839 }
3840
3841
3842 /*
3843  * Enable PCI Wake On Lan capability
3844  */
3845 static void
3846 em_enable_wakeup(if_ctx_t ctx)
3847 {
3848         struct e1000_softc *sc = iflib_get_softc(ctx);
3849         device_t dev = iflib_get_dev(ctx);
3850         if_t ifp = iflib_get_ifp(ctx);
3851         int error = 0;
3852         u32 pmc, ctrl, ctrl_ext, rctl;
3853         u16 status;
3854
3855         if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
3856                 return;
3857
3858         /*
3859          * Determine type of Wakeup: note that wol
3860          * is set with all bits on by default.
3861          */
3862         if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
3863                 sc->wol &= ~E1000_WUFC_MAG;
3864
3865         if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
3866                 sc->wol &= ~E1000_WUFC_EX;
3867
3868         if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
3869                 sc->wol &= ~E1000_WUFC_MC;
3870         else {
3871                 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
3872                 rctl |= E1000_RCTL_MPE;
3873                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
3874         }
3875
3876         if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC)))
3877                 goto pme;
3878
3879         /* Advertise the wakeup capability */
3880         ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
3881         ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
3882         E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
3883
3884         /* Keep the laser running on Fiber adapters */
3885         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
3886             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
3887                 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3888                 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
3889                 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext);
3890         }
3891
3892         if ((sc->hw.mac.type == e1000_ich8lan) ||
3893             (sc->hw.mac.type == e1000_pchlan) ||
3894             (sc->hw.mac.type == e1000_ich9lan) ||
3895             (sc->hw.mac.type == e1000_ich10lan))
3896                 e1000_suspend_workarounds_ich8lan(&sc->hw);
3897
3898         if ( sc->hw.mac.type >= e1000_pchlan) {
3899                 error = em_enable_phy_wakeup(sc);
3900                 if (error)
3901                         goto pme;
3902         } else {
3903                 /* Enable wakeup by the MAC */
3904                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
3905                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
3906         }
3907
3908         if (sc->hw.phy.type == e1000_phy_igp_3)
3909                 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw);
3910
3911 pme:
3912         status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
3913         status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3914         if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
3915                 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3916         pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
3917
3918         return;
3919 }
3920
3921 /*
3922  * WOL in the newer chipset interfaces (pchlan)
3923  * require thing to be copied into the phy
3924  */
3925 static int
3926 em_enable_phy_wakeup(struct e1000_softc *sc)
3927 {
3928         struct e1000_hw *hw = &sc->hw;
3929         u32 mreg, ret = 0;
3930         u16 preg;
3931
3932         /* copy MAC RARs to PHY RARs */
3933         e1000_copy_rx_addrs_to_phy_ich8lan(hw);
3934
3935         /* copy MAC MTA to PHY MTA */
3936         for (int i = 0; i < hw->mac.mta_reg_count; i++) {
3937                 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
3938                 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
3939                 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
3940                     (u16)((mreg >> 16) & 0xFFFF));
3941         }
3942
3943         /* configure PHY Rx Control register */
3944         e1000_read_phy_reg(hw, BM_RCTL, &preg);
3945         mreg = E1000_READ_REG(hw, E1000_RCTL);
3946         if (mreg & E1000_RCTL_UPE)
3947                 preg |= BM_RCTL_UPE;
3948         if (mreg & E1000_RCTL_MPE)
3949                 preg |= BM_RCTL_MPE;
3950         preg &= ~(BM_RCTL_MO_MASK);
3951         if (mreg & E1000_RCTL_MO_3)
3952                 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
3953                                 << BM_RCTL_MO_SHIFT);
3954         if (mreg & E1000_RCTL_BAM)
3955                 preg |= BM_RCTL_BAM;
3956         if (mreg & E1000_RCTL_PMCF)
3957                 preg |= BM_RCTL_PMCF;
3958         mreg = E1000_READ_REG(hw, E1000_CTRL);
3959         if (mreg & E1000_CTRL_RFCE)
3960                 preg |= BM_RCTL_RFCE;
3961         e1000_write_phy_reg(hw, BM_RCTL, preg);
3962
3963         /* enable PHY wakeup in MAC register */
3964         E1000_WRITE_REG(hw, E1000_WUC,
3965             E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
3966         E1000_WRITE_REG(hw, E1000_WUFC, sc->wol);
3967
3968         /* configure and enable PHY wakeup in PHY registers */
3969         e1000_write_phy_reg(hw, BM_WUFC, sc->wol);
3970         e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN);
3971
3972         /* activate PHY wakeup */
3973         ret = hw->phy.ops.acquire(hw);
3974         if (ret) {
3975                 printf("Could not acquire PHY\n");
3976                 return ret;
3977         }
3978         e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3979                                  (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3980         ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
3981         if (ret) {
3982                 printf("Could not read PHY page 769\n");
3983                 goto out;
3984         }
3985         preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
3986         ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
3987         if (ret)
3988                 printf("Could not set PHY Host Wakeup bit\n");
3989 out:
3990         hw->phy.ops.release(hw);
3991
3992         return ret;
3993 }
3994
3995 static void
3996 em_if_led_func(if_ctx_t ctx, int onoff)
3997 {
3998         struct e1000_softc *sc = iflib_get_softc(ctx);
3999
4000         if (onoff) {
4001                 e1000_setup_led(&sc->hw);
4002                 e1000_led_on(&sc->hw);
4003         } else {
4004                 e1000_led_off(&sc->hw);
4005                 e1000_cleanup_led(&sc->hw);
4006         }
4007 }
4008
4009 /*
4010  * Disable the L0S and L1 LINK states
4011  */
4012 static void
4013 em_disable_aspm(struct e1000_softc *sc)
4014 {
4015         int base, reg;
4016         u16 link_cap,link_ctrl;
4017         device_t dev = sc->dev;
4018
4019         switch (sc->hw.mac.type) {
4020         case e1000_82573:
4021         case e1000_82574:
4022         case e1000_82583:
4023                 break;
4024         default:
4025                 return;
4026         }
4027         if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
4028                 return;
4029         reg = base + PCIER_LINK_CAP;
4030         link_cap = pci_read_config(dev, reg, 2);
4031         if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
4032                 return;
4033         reg = base + PCIER_LINK_CTL;
4034         link_ctrl = pci_read_config(dev, reg, 2);
4035         link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
4036         pci_write_config(dev, reg, link_ctrl, 2);
4037         return;
4038 }
4039
4040 /**********************************************************************
4041  *
4042  *  Update the board statistics counters.
4043  *
4044  **********************************************************************/
4045 static void
4046 em_update_stats_counters(struct e1000_softc *sc)
4047 {
4048         u64 prev_xoffrxc = sc->stats.xoffrxc;
4049
4050         if(sc->hw.phy.media_type == e1000_media_type_copper ||
4051            (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
4052                 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
4053                 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
4054         }
4055         sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
4056         sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
4057         sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
4058         sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
4059
4060         sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
4061         sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
4062         sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
4063         sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
4064         sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
4065         sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
4066         sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
4067         sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
4068         /*
4069          ** For watchdog management we need to know if we have been
4070          ** paused during the last interval, so capture that here.
4071         */
4072         if (sc->stats.xoffrxc != prev_xoffrxc)
4073                 sc->shared->isc_pause_frames = 1;
4074         sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
4075         sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
4076         sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
4077         sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
4078         sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
4079         sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
4080         sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
4081         sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
4082         sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
4083         sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
4084         sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
4085         sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
4086
4087         /* For the 64-bit byte counters the low dword must be read first. */
4088         /* Both registers clear on the read of the high dword */
4089
4090         sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) +
4091             ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32);
4092         sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) +
4093             ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32);
4094
4095         sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
4096         sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
4097         sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
4098         sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
4099         sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
4100
4101         sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
4102         sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
4103
4104         sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
4105         sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
4106         sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
4107         sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
4108         sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
4109         sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
4110         sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
4111         sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
4112         sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
4113         sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
4114
4115         /* Interrupt Counts */
4116
4117         sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC);
4118         sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC);
4119         sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC);
4120         sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC);
4121         sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC);
4122         sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC);
4123         sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC);
4124         sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC);
4125         sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC);
4126
4127         if (sc->hw.mac.type >= e1000_82543) {
4128                 sc->stats.algnerrc +=
4129                 E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
4130                 sc->stats.rxerrc +=
4131                 E1000_READ_REG(&sc->hw, E1000_RXERRC);
4132                 sc->stats.tncrs +=
4133                 E1000_READ_REG(&sc->hw, E1000_TNCRS);
4134                 sc->stats.cexterr +=
4135                 E1000_READ_REG(&sc->hw, E1000_CEXTERR);
4136                 sc->stats.tsctc +=
4137                 E1000_READ_REG(&sc->hw, E1000_TSCTC);
4138                 sc->stats.tsctfc +=
4139                 E1000_READ_REG(&sc->hw, E1000_TSCTFC);
4140         }
4141 }
4142
4143 static uint64_t
4144 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
4145 {
4146         struct e1000_softc *sc = iflib_get_softc(ctx);
4147         struct ifnet *ifp = iflib_get_ifp(ctx);
4148
4149         switch (cnt) {
4150         case IFCOUNTER_COLLISIONS:
4151                 return (sc->stats.colc);
4152         case IFCOUNTER_IERRORS:
4153                 return (sc->dropped_pkts + sc->stats.rxerrc +
4154                     sc->stats.crcerrs + sc->stats.algnerrc +
4155                     sc->stats.ruc + sc->stats.roc +
4156                     sc->stats.mpc + sc->stats.cexterr);
4157         case IFCOUNTER_OERRORS:
4158                 return (sc->stats.ecol + sc->stats.latecol +
4159                     sc->watchdog_events);
4160         default:
4161                 return (if_get_counter_default(ifp, cnt));
4162         }
4163 }
4164
4165 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized
4166  * @ctx: iflib context
4167  * @event: event code to check
4168  *
4169  * Defaults to returning true for unknown events.
4170  *
4171  * @returns true if iflib needs to reinit the interface
4172  */
4173 static bool
4174 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
4175 {
4176         switch (event) {
4177         case IFLIB_RESTART_VLAN_CONFIG:
4178                 return (false);
4179         default:
4180                 return (true);
4181         }
4182 }
4183
4184 /* Export a single 32-bit register via a read-only sysctl. */
4185 static int
4186 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
4187 {
4188         struct e1000_softc *sc;
4189         u_int val;
4190
4191         sc = oidp->oid_arg1;
4192         val = E1000_READ_REG(&sc->hw, oidp->oid_arg2);
4193         return (sysctl_handle_int(oidp, &val, 0, req));
4194 }
4195
4196 /*
4197  * Add sysctl variables, one per statistic, to the system.
4198  */
4199 static void
4200 em_add_hw_stats(struct e1000_softc *sc)
4201 {
4202         device_t dev = iflib_get_dev(sc->ctx);
4203         struct em_tx_queue *tx_que = sc->tx_queues;
4204         struct em_rx_queue *rx_que = sc->rx_queues;
4205
4206         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
4207         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
4208         struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
4209         struct e1000_hw_stats *stats = &sc->stats;
4210
4211         struct sysctl_oid *stat_node, *queue_node, *int_node;
4212         struct sysctl_oid_list *stat_list, *queue_list, *int_list;
4213
4214 #define QUEUE_NAME_LEN 32
4215         char namebuf[QUEUE_NAME_LEN];
4216
4217         /* Driver Statistics */
4218         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
4219                         CTLFLAG_RD, &sc->dropped_pkts,
4220                         "Driver dropped packets");
4221         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
4222                         CTLFLAG_RD, &sc->link_irq,
4223                         "Link MSI-X IRQ Handled");
4224         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
4225                         CTLFLAG_RD, &sc->rx_overruns,
4226                         "RX overruns");
4227         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
4228                         CTLFLAG_RD, &sc->watchdog_events,
4229                         "Watchdog timeouts");
4230         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
4231             CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
4232             sc, E1000_CTRL, em_sysctl_reg_handler, "IU",
4233             "Device Control Register");
4234         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
4235             CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
4236             sc, E1000_RCTL, em_sysctl_reg_handler, "IU",
4237             "Receiver Control Register");
4238         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
4239                         CTLFLAG_RD, &sc->hw.fc.high_water, 0,
4240                         "Flow Control High Watermark");
4241         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
4242                         CTLFLAG_RD, &sc->hw.fc.low_water, 0,
4243                         "Flow Control Low Watermark");
4244
4245         for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) {
4246                 struct tx_ring *txr = &tx_que->txr;
4247                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
4248                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4249                     CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name");
4250                 queue_list = SYSCTL_CHILDREN(queue_node);
4251
4252                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
4253                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
4254                     E1000_TDH(txr->me), em_sysctl_reg_handler, "IU",
4255                     "Transmit Descriptor Head");
4256                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
4257                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
4258                     E1000_TDT(txr->me), em_sysctl_reg_handler, "IU",
4259                     "Transmit Descriptor Tail");
4260                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
4261                                 CTLFLAG_RD, &txr->tx_irq,
4262                                 "Queue MSI-X Transmit Interrupts");
4263         }
4264
4265         for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) {
4266                 struct rx_ring *rxr = &rx_que->rxr;
4267                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
4268                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4269                     CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name");
4270                 queue_list = SYSCTL_CHILDREN(queue_node);
4271
4272                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
4273                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
4274                     E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU",
4275                     "Receive Descriptor Head");
4276                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
4277                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
4278                     E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU",
4279                     "Receive Descriptor Tail");
4280                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
4281                                 CTLFLAG_RD, &rxr->rx_irq,
4282                                 "Queue MSI-X Receive Interrupts");
4283         }
4284
4285         /* MAC stats get their own sub node */
4286
4287         stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
4288             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics");
4289         stat_list = SYSCTL_CHILDREN(stat_node);
4290
4291         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
4292                         CTLFLAG_RD, &stats->ecol,
4293                         "Excessive collisions");
4294         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
4295                         CTLFLAG_RD, &stats->scc,
4296                         "Single collisions");
4297         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
4298                         CTLFLAG_RD, &stats->mcc,
4299                         "Multiple collisions");
4300         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
4301                         CTLFLAG_RD, &stats->latecol,
4302                         "Late collisions");
4303         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
4304                         CTLFLAG_RD, &stats->colc,
4305                         "Collision Count");
4306         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
4307                         CTLFLAG_RD, &sc->stats.symerrs,
4308                         "Symbol Errors");
4309         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
4310                         CTLFLAG_RD, &sc->stats.sec,
4311                         "Sequence Errors");
4312         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
4313                         CTLFLAG_RD, &sc->stats.dc,
4314                         "Defer Count");
4315         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
4316                         CTLFLAG_RD, &sc->stats.mpc,
4317                         "Missed Packets");
4318         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
4319                         CTLFLAG_RD, &sc->stats.rnbc,
4320                         "Receive No Buffers");
4321         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
4322                         CTLFLAG_RD, &sc->stats.ruc,
4323                         "Receive Undersize");
4324         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
4325                         CTLFLAG_RD, &sc->stats.rfc,
4326                         "Fragmented Packets Received ");
4327         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
4328                         CTLFLAG_RD, &sc->stats.roc,
4329                         "Oversized Packets Received");
4330         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
4331                         CTLFLAG_RD, &sc->stats.rjc,
4332                         "Recevied Jabber");
4333         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
4334                         CTLFLAG_RD, &sc->stats.rxerrc,
4335                         "Receive Errors");
4336         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
4337                         CTLFLAG_RD, &sc->stats.crcerrs,
4338                         "CRC errors");
4339         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
4340                         CTLFLAG_RD, &sc->stats.algnerrc,
4341                         "Alignment Errors");
4342         /* On 82575 these are collision counts */
4343         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
4344                         CTLFLAG_RD, &sc->stats.cexterr,
4345                         "Collision/Carrier extension errors");
4346         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
4347                         CTLFLAG_RD, &sc->stats.xonrxc,
4348                         "XON Received");
4349         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
4350                         CTLFLAG_RD, &sc->stats.xontxc,
4351                         "XON Transmitted");
4352         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
4353                         CTLFLAG_RD, &sc->stats.xoffrxc,
4354                         "XOFF Received");
4355         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
4356                         CTLFLAG_RD, &sc->stats.xofftxc,
4357                         "XOFF Transmitted");
4358
4359         /* Packet Reception Stats */
4360         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
4361                         CTLFLAG_RD, &sc->stats.tpr,
4362                         "Total Packets Received ");
4363         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
4364                         CTLFLAG_RD, &sc->stats.gprc,
4365                         "Good Packets Received");
4366         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
4367                         CTLFLAG_RD, &sc->stats.bprc,
4368                         "Broadcast Packets Received");
4369         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
4370                         CTLFLAG_RD, &sc->stats.mprc,
4371                         "Multicast Packets Received");
4372         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
4373                         CTLFLAG_RD, &sc->stats.prc64,
4374                         "64 byte frames received ");
4375         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
4376                         CTLFLAG_RD, &sc->stats.prc127,
4377                         "65-127 byte frames received");
4378         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
4379                         CTLFLAG_RD, &sc->stats.prc255,
4380                         "128-255 byte frames received");
4381         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
4382                         CTLFLAG_RD, &sc->stats.prc511,
4383                         "256-511 byte frames received");
4384         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
4385                         CTLFLAG_RD, &sc->stats.prc1023,
4386                         "512-1023 byte frames received");
4387         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
4388                         CTLFLAG_RD, &sc->stats.prc1522,
4389                         "1023-1522 byte frames received");
4390         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
4391                         CTLFLAG_RD, &sc->stats.gorc,
4392                         "Good Octets Received");
4393
4394         /* Packet Transmission Stats */
4395         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
4396                         CTLFLAG_RD, &sc->stats.gotc,
4397                         "Good Octets Transmitted");
4398         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
4399                         CTLFLAG_RD, &sc->stats.tpt,
4400                         "Total Packets Transmitted");
4401         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
4402                         CTLFLAG_RD, &sc->stats.gptc,
4403                         "Good Packets Transmitted");
4404         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
4405                         CTLFLAG_RD, &sc->stats.bptc,
4406                         "Broadcast Packets Transmitted");
4407         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
4408                         CTLFLAG_RD, &sc->stats.mptc,
4409                         "Multicast Packets Transmitted");
4410         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
4411                         CTLFLAG_RD, &sc->stats.ptc64,
4412                         "64 byte frames transmitted ");
4413         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
4414                         CTLFLAG_RD, &sc->stats.ptc127,
4415                         "65-127 byte frames transmitted");
4416         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
4417                         CTLFLAG_RD, &sc->stats.ptc255,
4418                         "128-255 byte frames transmitted");
4419         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
4420                         CTLFLAG_RD, &sc->stats.ptc511,
4421                         "256-511 byte frames transmitted");
4422         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
4423                         CTLFLAG_RD, &sc->stats.ptc1023,
4424                         "512-1023 byte frames transmitted");
4425         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
4426                         CTLFLAG_RD, &sc->stats.ptc1522,
4427                         "1024-1522 byte frames transmitted");
4428         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
4429                         CTLFLAG_RD, &sc->stats.tsctc,
4430                         "TSO Contexts Transmitted");
4431         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
4432                         CTLFLAG_RD, &sc->stats.tsctfc,
4433                         "TSO Contexts Failed");
4434
4435
4436         /* Interrupt Stats */
4437
4438         int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
4439             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics");
4440         int_list = SYSCTL_CHILDREN(int_node);
4441
4442         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
4443                         CTLFLAG_RD, &sc->stats.iac,
4444                         "Interrupt Assertion Count");
4445
4446         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
4447                         CTLFLAG_RD, &sc->stats.icrxptc,
4448                         "Interrupt Cause Rx Pkt Timer Expire Count");
4449
4450         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
4451                         CTLFLAG_RD, &sc->stats.icrxatc,
4452                         "Interrupt Cause Rx Abs Timer Expire Count");
4453
4454         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
4455                         CTLFLAG_RD, &sc->stats.ictxptc,
4456                         "Interrupt Cause Tx Pkt Timer Expire Count");
4457
4458         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
4459                         CTLFLAG_RD, &sc->stats.ictxatc,
4460                         "Interrupt Cause Tx Abs Timer Expire Count");
4461
4462         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
4463                         CTLFLAG_RD, &sc->stats.ictxqec,
4464                         "Interrupt Cause Tx Queue Empty Count");
4465
4466         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
4467                         CTLFLAG_RD, &sc->stats.ictxqmtc,
4468                         "Interrupt Cause Tx Queue Min Thresh Count");
4469
4470         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
4471                         CTLFLAG_RD, &sc->stats.icrxdmtc,
4472                         "Interrupt Cause Rx Desc Min Thresh Count");
4473
4474         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
4475                         CTLFLAG_RD, &sc->stats.icrxoc,
4476                         "Interrupt Cause Receiver Overrun Count");
4477 }
4478
4479 /**********************************************************************
4480  *
4481  *  This routine provides a way to dump out the adapter eeprom,
4482  *  often a useful debug/service tool. This only dumps the first
4483  *  32 words, stuff that matters is in that extent.
4484  *
4485  **********************************************************************/
4486 static int
4487 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4488 {
4489         struct e1000_softc *sc = (struct e1000_softc *)arg1;
4490         int error;
4491         int result;
4492
4493         result = -1;
4494         error = sysctl_handle_int(oidp, &result, 0, req);
4495
4496         if (error || !req->newptr)
4497                 return (error);
4498
4499         /*
4500          * This value will cause a hex dump of the
4501          * first 32 16-bit words of the EEPROM to
4502          * the screen.
4503          */
4504         if (result == 1)
4505                 em_print_nvm_info(sc);
4506
4507         return (error);
4508 }
4509
4510 static void
4511 em_print_nvm_info(struct e1000_softc *sc)
4512 {
4513         u16 eeprom_data;
4514         int i, j, row = 0;
4515
4516         /* Its a bit crude, but it gets the job done */
4517         printf("\nInterface EEPROM Dump:\n");
4518         printf("Offset\n0x0000  ");
4519         for (i = 0, j = 0; i < 32; i++, j++) {
4520                 if (j == 8) { /* Make the offset block */
4521                         j = 0; ++row;
4522                         printf("\n0x00%x0  ",row);
4523                 }
4524                 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
4525                 printf("%04x ", eeprom_data);
4526         }
4527         printf("\n");
4528 }
4529
4530 static int
4531 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4532 {
4533         struct em_int_delay_info *info;
4534         struct e1000_softc *sc;
4535         u32 regval;
4536         int error, usecs, ticks;
4537
4538         info = (struct em_int_delay_info *) arg1;
4539         usecs = info->value;
4540         error = sysctl_handle_int(oidp, &usecs, 0, req);
4541         if (error != 0 || req->newptr == NULL)
4542                 return (error);
4543         if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4544                 return (EINVAL);
4545         info->value = usecs;
4546         ticks = EM_USECS_TO_TICKS(usecs);
4547         if (info->offset == E1000_ITR)  /* units are 256ns here */
4548                 ticks *= 4;
4549
4550         sc = info->sc;
4551
4552         regval = E1000_READ_OFFSET(&sc->hw, info->offset);
4553         regval = (regval & ~0xffff) | (ticks & 0xffff);
4554         /* Handle a few special cases. */
4555         switch (info->offset) {
4556         case E1000_RDTR:
4557                 break;
4558         case E1000_TIDV:
4559                 if (ticks == 0) {
4560                         sc->txd_cmd &= ~E1000_TXD_CMD_IDE;
4561                         /* Don't write 0 into the TIDV register. */
4562                         regval++;
4563                 } else
4564                         sc->txd_cmd |= E1000_TXD_CMD_IDE;
4565                 break;
4566         }
4567         E1000_WRITE_OFFSET(&sc->hw, info->offset, regval);
4568         return (0);
4569 }
4570
4571 static void
4572 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name,
4573         const char *description, struct em_int_delay_info *info,
4574         int offset, int value)
4575 {
4576         info->sc = sc;
4577         info->offset = offset;
4578         info->value = value;
4579         SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
4580             SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
4581             OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
4582             info, 0, em_sysctl_int_delay, "I", description);
4583 }
4584
4585 /*
4586  * Set flow control using sysctl:
4587  * Flow control values:
4588  *      0 - off
4589  *      1 - rx pause
4590  *      2 - tx pause
4591  *      3 - full
4592  */
4593 static int
4594 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4595 {
4596         int error;
4597         static int input = 3; /* default is full */
4598         struct e1000_softc      *sc = (struct e1000_softc *) arg1;
4599
4600         error = sysctl_handle_int(oidp, &input, 0, req);
4601
4602         if ((error) || (req->newptr == NULL))
4603                 return (error);
4604
4605         if (input == sc->fc) /* no change? */
4606                 return (error);
4607
4608         switch (input) {
4609         case e1000_fc_rx_pause:
4610         case e1000_fc_tx_pause:
4611         case e1000_fc_full:
4612         case e1000_fc_none:
4613                 sc->hw.fc.requested_mode = input;
4614                 sc->fc = input;
4615                 break;
4616         default:
4617                 /* Do nothing */
4618                 return (error);
4619         }
4620
4621         sc->hw.fc.current_mode = sc->hw.fc.requested_mode;
4622         e1000_force_mac_fc(&sc->hw);
4623         return (error);
4624 }
4625
4626 /*
4627  * Manage Energy Efficient Ethernet:
4628  * Control values:
4629  *     0/1 - enabled/disabled
4630  */
4631 static int
4632 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4633 {
4634         struct e1000_softc *sc = (struct e1000_softc *) arg1;
4635         int error, value;
4636
4637         value = sc->hw.dev_spec.ich8lan.eee_disable;
4638         error = sysctl_handle_int(oidp, &value, 0, req);
4639         if (error || req->newptr == NULL)
4640                 return (error);
4641         sc->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4642         em_if_init(sc->ctx);
4643
4644         return (0);
4645 }
4646
4647 static int
4648 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4649 {
4650         struct e1000_softc *sc;
4651         int error;
4652         int result;
4653
4654         result = -1;
4655         error = sysctl_handle_int(oidp, &result, 0, req);
4656
4657         if (error || !req->newptr)
4658                 return (error);
4659
4660         if (result == 1) {
4661                 sc = (struct e1000_softc *) arg1;
4662                 em_print_debug_info(sc);
4663         }
4664
4665         return (error);
4666 }
4667
4668 static int
4669 em_get_rs(SYSCTL_HANDLER_ARGS)
4670 {
4671         struct e1000_softc *sc = (struct e1000_softc *) arg1;
4672         int error;
4673         int result;
4674
4675         result = 0;
4676         error = sysctl_handle_int(oidp, &result, 0, req);
4677
4678         if (error || !req->newptr || result != 1)
4679                 return (error);
4680         em_dump_rs(sc);
4681
4682         return (error);
4683 }
4684
4685 static void
4686 em_if_debug(if_ctx_t ctx)
4687 {
4688         em_dump_rs(iflib_get_softc(ctx));
4689 }
4690
4691 /*
4692  * This routine is meant to be fluid, add whatever is
4693  * needed for debugging a problem.  -jfv
4694  */
4695 static void
4696 em_print_debug_info(struct e1000_softc *sc)
4697 {
4698         device_t dev = iflib_get_dev(sc->ctx);
4699         struct ifnet *ifp = iflib_get_ifp(sc->ctx);
4700         struct tx_ring *txr = &sc->tx_queues->txr;
4701         struct rx_ring *rxr = &sc->rx_queues->rxr;
4702
4703         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
4704                 printf("Interface is RUNNING ");
4705         else
4706                 printf("Interface is NOT RUNNING\n");
4707
4708         if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
4709                 printf("and INACTIVE\n");
4710         else
4711                 printf("and ACTIVE\n");
4712
4713         for (int i = 0; i < sc->tx_num_queues; i++, txr++) {
4714                 device_printf(dev, "TX Queue %d ------\n", i);
4715                 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
4716                         E1000_READ_REG(&sc->hw, E1000_TDH(i)),
4717                         E1000_READ_REG(&sc->hw, E1000_TDT(i)));
4718
4719         }
4720         for (int j=0; j < sc->rx_num_queues; j++, rxr++) {
4721                 device_printf(dev, "RX Queue %d ------\n", j);
4722                 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
4723                         E1000_READ_REG(&sc->hw, E1000_RDH(j)),
4724                         E1000_READ_REG(&sc->hw, E1000_RDT(j)));
4725         }
4726 }
4727
4728 /*
4729  * 82574 only:
4730  * Write a new value to the EEPROM increasing the number of MSI-X
4731  * vectors from 3 to 5, for proper multiqueue support.
4732  */
4733 static void
4734 em_enable_vectors_82574(if_ctx_t ctx)
4735 {
4736         struct e1000_softc *sc = iflib_get_softc(ctx);
4737         struct e1000_hw *hw = &sc->hw;
4738         device_t dev = iflib_get_dev(ctx);
4739         u16 edata;
4740
4741         e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4742         if (bootverbose)
4743                 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata);
4744         if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
4745                 device_printf(dev, "Writing to eeprom: increasing "
4746                     "reported MSI-X vectors from 3 to 5...\n");
4747                 edata &= ~(EM_NVM_MSIX_N_MASK);
4748                 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
4749                 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4750                 e1000_update_nvm_checksum(hw);
4751                 device_printf(dev, "Writing to eeprom: done\n");
4752         }
4753 }