sys/dev/e1000/if_em.c

   1 /*-
   2  * Copyright (c) 2016 Matt Macy <mmacy@nextbsd.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 /* $FreeBSD$ */
  28 #include "if_em.h"
  29 #include <sys/sbuf.h>
  30 #include <machine/_inttypes.h>
  31
  32 #define em_mac_min e1000_82547
  33 #define igb_mac_min e1000_82575
  34
  35 /*********************************************************************
  36  *  Driver version:
  37  *********************************************************************/
  38 char em_driver_version[] = "7.6.1-k";
  39
  40 /*********************************************************************
  41  *  PCI Device ID Table
  42  *
  43  *  Used by probe to select devices to load on
  44  *  Last field stores an index into e1000_strings
  45  *  Last entry must be all 0s
  46  *
  47  *  { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
  48  *********************************************************************/
  49
  50 static pci_vendor_info_t em_vendor_info_array[] =
  51 {
  52         /* Intel(R) PRO/1000 Network Connection - Legacy em*/
  53         PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"),
  54         PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"),
  55         PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"),
  56         PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"),
  57         PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"),
  58
  59         PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"),
  60         PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"),
  61         PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"),
  62         PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  63         PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"),
  64         PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"),
  65         PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  66
  67         PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"),
  68
  69         PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"),
  70         PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
  71
  72         PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
  73         PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
  74         PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
  75         PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"),
  76
  77         PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"),
  78         PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"),
  79         PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"),
  80         PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"),
  81         PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"),
  82
  83         PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  84         PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
  85         PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
  86         PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  87         PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"),
  88         PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"),
  89         PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"),
  90         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
  91         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"),
  92
  93         PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"),
  94         PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  95         PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"),
  96
  97         /* Intel(R) PRO/1000 Network Connection - em */
  98         PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  99         PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
 100         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"),
 101         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"),
 102         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"),
 103         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 104         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"),
 105         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"),
 106         PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 107         PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"),
 108         PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
 109         PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
 110         PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"),
 111         PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"),
 112         PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"),
 113         PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"),
 114         PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"),
 115         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"),
 116         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"),
 117         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"),
 118         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"),
 119         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
 120         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 121         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"),
 122         PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"),
 123         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
 124         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"),
 125         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"),
 126         PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"),
 127         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
 128         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 129         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"),
 130         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"),
 131         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"),
 132         PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"),
 133         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
 134         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"),
 135         PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"),
 136         PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"),
 137         PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"),
 138         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"),
 139         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"),
 140         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"),
 141         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"),
 142         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"),
 143         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"),
 144         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"),
 145         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"),
 146         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"),
 147         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"),
 148         PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"),
 149         PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"),
 150         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"),
 151         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"),
 152         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"),
 153         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"),
 154         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"),
 155         PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"),
 156         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"),
 157         PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"),
 158         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"),
 159         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"),
 160         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"),
 161         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"),
 162         PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"),
 163         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"),
 164         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"),
 165         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"),
 166         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"),
 167         /* required last entry */
 168         PVID_END
 169 };
 170
 171 static pci_vendor_info_t igb_vendor_info_array[] =
 172 {
 173         /* Intel(R) PRO/1000 Network Connection - igb */
 174         PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 175         PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 176         PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 177         PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 178         PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 179         PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 180         PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 181         PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 182         PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 183         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 184         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 185         PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 186         PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 187         PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 188         PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 189         PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 190         PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 191         PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 192         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 193         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 194         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 195         PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 196         PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 197         PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 198         PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 199         PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 200         PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 201         PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 202         PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 203         PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 204         PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 205         PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 206         PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 207         PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 208         PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 209         PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 210         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 211         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 212         PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 213         /* required last entry */
 214         PVID_END
 215 };
 216
 217 /*********************************************************************
 218  *  Function prototypes
 219  *********************************************************************/
 220 static void     *em_register(device_t dev);
 221 static void     *igb_register(device_t dev);
 222 static int      em_if_attach_pre(if_ctx_t ctx);
 223 static int      em_if_attach_post(if_ctx_t ctx);
 224 static int      em_if_detach(if_ctx_t ctx);
 225 static int      em_if_shutdown(if_ctx_t ctx);
 226 static int      em_if_suspend(if_ctx_t ctx);
 227 static int      em_if_resume(if_ctx_t ctx);
 228
 229 static int      em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets);
 230 static int      em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets);
 231 static void     em_if_queues_free(if_ctx_t ctx);
 232
 233 static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
 234 static void     em_if_init(if_ctx_t ctx);
 235 static void     em_if_stop(if_ctx_t ctx);
 236 static void     em_if_media_status(if_ctx_t, struct ifmediareq *);
 237 static int      em_if_media_change(if_ctx_t ctx);
 238 static int      em_if_mtu_set(if_ctx_t ctx, uint32_t mtu);
 239 static void     em_if_timer(if_ctx_t ctx, uint16_t qid);
 240 static void     em_if_vlan_register(if_ctx_t ctx, u16 vtag);
 241 static void     em_if_vlan_unregister(if_ctx_t ctx, u16 vtag);
 242
 243 static void     em_identify_hardware(if_ctx_t ctx);
 244 static int      em_allocate_pci_resources(if_ctx_t ctx);
 245 static void     em_free_pci_resources(if_ctx_t ctx);
 246 static void     em_reset(if_ctx_t ctx);
 247 static int      em_setup_interface(if_ctx_t ctx);
 248 static int      em_setup_msix(if_ctx_t ctx);
 249
 250 static void     em_initialize_transmit_unit(if_ctx_t ctx);
 251 static void     em_initialize_receive_unit(if_ctx_t ctx);
 252
 253 static void     em_if_enable_intr(if_ctx_t ctx);
 254 static void     em_if_disable_intr(if_ctx_t ctx);
 255 static int      em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 256 static int      em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
 257 static void     em_if_multi_set(if_ctx_t ctx);
 258 static void     em_if_update_admin_status(if_ctx_t ctx);
 259 static void     em_if_debug(if_ctx_t ctx);
 260 static void     em_update_stats_counters(struct adapter *);
 261 static void     em_add_hw_stats(struct adapter *adapter);
 262 static int      em_if_set_promisc(if_ctx_t ctx, int flags);
 263 static void     em_setup_vlan_hw_support(struct adapter *);
 264 static int      em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
 265 static void     em_print_nvm_info(struct adapter *);
 266 static int      em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 267 static int      em_get_rs(SYSCTL_HANDLER_ARGS);
 268 static void     em_print_debug_info(struct adapter *);
 269 static int      em_is_valid_ether_addr(u8 *);
 270 static int      em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
 271 static void     em_add_int_delay_sysctl(struct adapter *, const char *,
 272                     const char *, struct em_int_delay_info *, int, int);
 273 /* Management and WOL Support */
 274 static void     em_init_manageability(struct adapter *);
 275 static void     em_release_manageability(struct adapter *);
 276 static void     em_get_hw_control(struct adapter *);
 277 static void     em_release_hw_control(struct adapter *);
 278 static void     em_get_wakeup(if_ctx_t ctx);
 279 static void     em_enable_wakeup(if_ctx_t ctx);
 280 static int      em_enable_phy_wakeup(struct adapter *);
 281 static void     em_disable_aspm(struct adapter *);
 282
 283 int             em_intr(void *arg);
 284 static void     em_disable_promisc(if_ctx_t ctx);
 285
 286 /* MSIX handlers */
 287 static int      em_if_msix_intr_assign(if_ctx_t, int);
 288 static int      em_msix_link(void *);
 289 static void     em_handle_link(void *context);
 290
 291 static void     em_enable_vectors_82574(if_ctx_t);
 292
 293 static int      em_set_flowcntl(SYSCTL_HANDLER_ARGS);
 294 static int      em_sysctl_eee(SYSCTL_HANDLER_ARGS);
 295 static void     em_if_led_func(if_ctx_t ctx, int onoff);
 296
 297 static int      em_get_regs(SYSCTL_HANDLER_ARGS);
 298
 299 static void     lem_smartspeed(struct adapter *adapter);
 300 static void     igb_configure_queues(struct adapter *adapter);
 301
 302
 303 /*********************************************************************
 304  *  FreeBSD Device Interface Entry Points
 305  *********************************************************************/
 306 static device_method_t em_methods[] = {
 307         /* Device interface */
 308         DEVMETHOD(device_register, em_register),
 309         DEVMETHOD(device_probe, iflib_device_probe),
 310         DEVMETHOD(device_attach, iflib_device_attach),
 311         DEVMETHOD(device_detach, iflib_device_detach),
 312         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 313         DEVMETHOD(device_suspend, iflib_device_suspend),
 314         DEVMETHOD(device_resume, iflib_device_resume),
 315         DEVMETHOD_END
 316 };
 317
 318 static device_method_t igb_methods[] = {
 319         /* Device interface */
 320         DEVMETHOD(device_register, igb_register),
 321         DEVMETHOD(device_probe, iflib_device_probe),
 322         DEVMETHOD(device_attach, iflib_device_attach),
 323         DEVMETHOD(device_detach, iflib_device_detach),
 324         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 325         DEVMETHOD(device_suspend, iflib_device_suspend),
 326         DEVMETHOD(device_resume, iflib_device_resume),
 327         DEVMETHOD_END
 328 };
 329
 330
 331 static driver_t em_driver = {
 332         "em", em_methods, sizeof(struct adapter),
 333 };
 334
 335 static devclass_t em_devclass;
 336 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
 337
 338 MODULE_DEPEND(em, pci, 1, 1, 1);
 339 MODULE_DEPEND(em, ether, 1, 1, 1);
 340 MODULE_DEPEND(em, iflib, 1, 1, 1);
 341
 342 static driver_t igb_driver = {
 343         "igb", igb_methods, sizeof(struct adapter),
 344 };
 345
 346 static devclass_t igb_devclass;
 347 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
 348
 349 MODULE_DEPEND(igb, pci, 1, 1, 1);
 350 MODULE_DEPEND(igb, ether, 1, 1, 1);
 351 MODULE_DEPEND(igb, iflib, 1, 1, 1);
 352
 353
 354 static device_method_t em_if_methods[] = {
 355         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 356         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 357         DEVMETHOD(ifdi_detach, em_if_detach),
 358         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 359         DEVMETHOD(ifdi_suspend, em_if_suspend),
 360         DEVMETHOD(ifdi_resume, em_if_resume),
 361         DEVMETHOD(ifdi_init, em_if_init),
 362         DEVMETHOD(ifdi_stop, em_if_stop),
 363         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 364         DEVMETHOD(ifdi_intr_enable, em_if_enable_intr),
 365         DEVMETHOD(ifdi_intr_disable, em_if_disable_intr),
 366         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 367         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 368         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 369         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 370         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 371         DEVMETHOD(ifdi_media_status, em_if_media_status),
 372         DEVMETHOD(ifdi_media_change, em_if_media_change),
 373         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 374         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 375         DEVMETHOD(ifdi_timer, em_if_timer),
 376         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 377         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 378         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 379         DEVMETHOD(ifdi_led_func, em_if_led_func),
 380         DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable),
 381         DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable),
 382         DEVMETHOD(ifdi_debug, em_if_debug),
 383         DEVMETHOD_END
 384 };
 385
 386 /*
 387  * note that if (adapter->msix_mem) is replaced by:
 388  * if (adapter->intr_type == IFLIB_INTR_MSIX)
 389  */
 390 static driver_t em_if_driver = {
 391         "em_if", em_if_methods, sizeof(struct adapter)
 392 };
 393
 394 /*********************************************************************
 395  *  Tunable default values.
 396  *********************************************************************/
 397
 398 #define EM_TICKS_TO_USECS(ticks)        ((1024 * (ticks) + 500) / 1000)
 399 #define EM_USECS_TO_TICKS(usecs)        ((1000 * (usecs) + 512) / 1024)
 400 #define M_TSO_LEN                       66
 401
 402 #define MAX_INTS_PER_SEC        8000
 403 #define DEFAULT_ITR             (1000000000/(MAX_INTS_PER_SEC * 256))
 404
 405 /* Allow common code without TSO */
 406 #ifndef CSUM_TSO
 407 #define CSUM_TSO        0
 408 #endif
 409
 410 #define TSO_WORKAROUND  4
 411
 412 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters");
 413
 414 static int em_disable_crc_stripping = 0;
 415 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
 416     &em_disable_crc_stripping, 0, "Disable CRC Stripping");
 417
 418 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
 419 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
 420 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
 421     0, "Default transmit interrupt delay in usecs");
 422 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
 423     0, "Default receive interrupt delay in usecs");
 424
 425 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
 426 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
 427 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
 428     &em_tx_abs_int_delay_dflt, 0,
 429     "Default transmit interrupt delay limit in usecs");
 430 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
 431     &em_rx_abs_int_delay_dflt, 0,
 432     "Default receive interrupt delay limit in usecs");
 433
 434 static int em_smart_pwr_down = FALSE;
 435 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
 436     0, "Set to true to leave smart power down enabled on newer adapters");
 437
 438 /* Controls whether promiscuous also shows bad packets */
 439 static int em_debug_sbp = TRUE;
 440 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
 441     "Show bad packets in promiscuous mode");
 442
 443 /* How many packets rxeof tries to clean at a time */
 444 static int em_rx_process_limit = 100;
 445 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
 446     &em_rx_process_limit, 0,
 447     "Maximum number of received packets to process "
 448     "at a time, -1 means unlimited");
 449
 450 /* Energy efficient ethernet - default to OFF */
 451 static int eee_setting = 1;
 452 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
 453     "Enable Energy Efficient Ethernet");
 454
 455 /*
 456 ** Tuneable Interrupt rate
 457 */
 458 static int em_max_interrupt_rate = 8000;
 459 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
 460     &em_max_interrupt_rate, 0, "Maximum interrupts per second");
 461
 462
 463
 464 /* Global used in WOL setup with multiport cards */
 465 static int global_quad_port_a = 0;
 466
 467 extern struct if_txrx igb_txrx;
 468 extern struct if_txrx em_txrx;
 469 extern struct if_txrx lem_txrx;
 470
 471 static struct if_shared_ctx em_sctx_init = {
 472         .isc_magic = IFLIB_MAGIC,
 473         .isc_q_align = PAGE_SIZE,
 474         .isc_tx_maxsize = EM_TSO_SIZE,
 475         .isc_tx_maxsegsize = PAGE_SIZE,
 476         .isc_rx_maxsize = MJUM9BYTES,
 477         .isc_rx_nsegments = 1,
 478         .isc_rx_maxsegsize = MJUM9BYTES,
 479         .isc_nfl = 1,
 480         .isc_nrxqs = 1,
 481         .isc_ntxqs = 1,
 482         .isc_admin_intrcnt = 1,
 483         .isc_vendor_info = em_vendor_info_array,
 484         .isc_driver_version = em_driver_version,
 485         .isc_driver = &em_if_driver,
 486         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP,
 487
 488         .isc_nrxd_min = {EM_MIN_RXD},
 489         .isc_ntxd_min = {EM_MIN_TXD},
 490         .isc_nrxd_max = {EM_MAX_RXD},
 491         .isc_ntxd_max = {EM_MAX_TXD},
 492         .isc_nrxd_default = {EM_DEFAULT_RXD},
 493         .isc_ntxd_default = {EM_DEFAULT_TXD},
 494 };
 495
 496 if_shared_ctx_t em_sctx = &em_sctx_init;
 497
 498
 499 static struct if_shared_ctx igb_sctx_init = {
 500         .isc_magic = IFLIB_MAGIC,
 501         .isc_q_align = PAGE_SIZE,
 502         .isc_tx_maxsize = EM_TSO_SIZE,
 503         .isc_tx_maxsegsize = PAGE_SIZE,
 504         .isc_rx_maxsize = MJUM9BYTES,
 505         .isc_rx_nsegments = 1,
 506         .isc_rx_maxsegsize = MJUM9BYTES,
 507         .isc_nfl = 1,
 508         .isc_nrxqs = 1,
 509         .isc_ntxqs = 1,
 510         .isc_admin_intrcnt = 1,
 511         .isc_vendor_info = igb_vendor_info_array,
 512         .isc_driver_version = em_driver_version,
 513         .isc_driver = &em_if_driver,
 514         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP,
 515
 516         .isc_nrxd_min = {EM_MIN_RXD},
 517         .isc_ntxd_min = {EM_MIN_TXD},
 518         .isc_nrxd_max = {IGB_MAX_RXD},
 519         .isc_ntxd_max = {IGB_MAX_TXD},
 520         .isc_nrxd_default = {EM_DEFAULT_RXD},
 521         .isc_ntxd_default = {EM_DEFAULT_TXD},
 522 };
 523
 524 if_shared_ctx_t igb_sctx = &igb_sctx_init;
 525
 526 /*****************************************************************
 527  *
 528  * Dump Registers
 529  *
 530  ****************************************************************/
 531 #define IGB_REGS_LEN 739
 532
 533 static int em_get_regs(SYSCTL_HANDLER_ARGS)
 534 {
 535         struct adapter *adapter = (struct adapter *)arg1;
 536         struct e1000_hw *hw = &adapter->hw;
 537         struct sbuf *sb;
 538         u32 *regs_buff;
 539         int rc;
 540
 541         regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK);
 542         memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
 543
 544         rc = sysctl_wire_old_buffer(req, 0);
 545         MPASS(rc == 0);
 546         if (rc != 0) {
 547                 free(regs_buff, M_DEVBUF);
 548                 return (rc);
 549         }
 550
 551         sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
 552         MPASS(sb != NULL);
 553         if (sb == NULL) {
 554                 free(regs_buff, M_DEVBUF);
 555                 return (ENOMEM);
 556         }
 557
 558         /* General Registers */
 559         regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
 560         regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
 561         regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
 562         regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
 563         regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
 564         regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
 565         regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
 566         regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
 567         regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
 568         regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
 569         regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
 570         regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
 571         regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
 572         regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
 573         regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
 574         regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
 575         regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
 576         regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
 577         regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
 578         regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
 579         regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
 580         regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
 581
 582         sbuf_printf(sb, "General Registers\n");
 583         sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
 584         sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
 585         sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]);
 586
 587         sbuf_printf(sb, "Interrupt Registers\n");
 588         sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
 589
 590         sbuf_printf(sb, "RX Registers\n");
 591         sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
 592         sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
 593         sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
 594         sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
 595         sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
 596         sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
 597         sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
 598
 599         sbuf_printf(sb, "TX Registers\n");
 600         sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
 601         sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
 602         sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
 603         sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
 604         sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
 605         sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
 606         sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
 607         sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
 608         sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
 609         sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
 610         sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
 611
 612         free(regs_buff, M_DEVBUF);
 613
 614 #ifdef DUMP_DESCS
 615         {
 616                 if_softc_ctx_t scctx = adapter->shared;
 617                 struct rx_ring *rxr = &rx_que->rxr;
 618                 struct tx_ring *txr = &tx_que->txr;
 619                 int ntxd = scctx->isc_ntxd[0];
 620                 int nrxd = scctx->isc_nrxd[0];
 621                 int j;
 622
 623         for (j = 0; j < nrxd; j++) {
 624                 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
 625                 u32 length =  le32toh(rxr->rx_base[j].wb.upper.length);
 626                 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 "  Error:%d  Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
 627         }
 628
 629         for (j = 0; j < min(ntxd, 256); j++) {
 630                 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
 631
 632                 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x  eop: %d DD=%d\n",
 633                             j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
 634                             buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
 635
 636         }
 637         }
 638 #endif
 639
 640         rc = sbuf_finish(sb);
 641         sbuf_delete(sb);
 642         return(rc);
 643 }
 644
 645 static void *
 646 em_register(device_t dev)
 647 {
 648         return (em_sctx);
 649 }
 650
 651 static void *
 652 igb_register(device_t dev)
 653 {
 654         return (igb_sctx);
 655 }
 656
 657 static int
 658 em_set_num_queues(if_ctx_t ctx)
 659 {
 660         struct adapter *adapter = iflib_get_softc(ctx);
 661         int maxqueues;
 662
 663         /* Sanity check based on HW */
 664         switch (adapter->hw.mac.type) {
 665         case e1000_82576:
 666         case e1000_82580:
 667         case e1000_i350:
 668         case e1000_i354:
 669                 maxqueues = 8;
 670                 break;
 671         case e1000_i210:
 672         case e1000_82575:
 673                 maxqueues = 4;
 674                 break;
 675         case e1000_i211:
 676         case e1000_82574:
 677                 maxqueues = 2;
 678                 break;
 679         default:
 680                 maxqueues = 1;
 681                 break;
 682         }
 683
 684         return (maxqueues);
 685 }
 686
 687
 688 #define EM_CAPS \
 689         IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \
 690         IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | \
 691         IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU;
 692
 693 #define IGB_CAPS \
 694         IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \
 695         IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM | \
 696         IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU | IFCAP_TXCSUM_IPV6 | IFCAP_HWCSUM_IPV6 | IFCAP_JUMBO_MTU;
 697
 698 /*********************************************************************
 699  *  Device initialization routine
 700  *
 701  *  The attach entry point is called when the driver is being loaded.
 702  *  This routine identifies the type of hardware, allocates all resources
 703  *  and initializes the hardware.
 704  *
 705  *  return 0 on success, positive on failure
 706  *********************************************************************/
 707
 708 static int
 709 em_if_attach_pre(if_ctx_t ctx)
 710 {
 711         struct adapter *adapter;
 712         if_softc_ctx_t scctx;
 713         device_t dev;
 714         struct e1000_hw *hw;
 715         int error = 0;
 716
 717         INIT_DEBUGOUT("em_if_attach_pre begin");
 718         dev = iflib_get_dev(ctx);
 719         adapter = iflib_get_softc(ctx);
 720
 721         if (resource_disabled("em", device_get_unit(dev))) {
 722                 device_printf(dev, "Disabled by device hint\n");
 723                 return (ENXIO);
 724         }
 725
 726         adapter->ctx = ctx;
 727         adapter->dev = adapter->osdep.dev = dev;
 728         scctx = adapter->shared = iflib_get_softc_ctx(ctx);
 729         adapter->media = iflib_get_media(ctx);
 730         hw = &adapter->hw;
 731
 732         adapter->tx_process_limit = scctx->isc_ntxd[0];
 733
 734         /* SYSCTL stuff */
 735         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 736             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 737             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 738             em_sysctl_nvm_info, "I", "NVM Information");
 739
 740         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 741             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 742             OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 743             em_sysctl_debug_info, "I", "Debug Information");
 744
 745         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 746             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 747             OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 748             em_set_flowcntl, "I", "Flow Control");
 749
 750         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 751             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 752             OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0,
 753             em_get_regs, "A", "Dump Registers");
 754
 755         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 756             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 757             OID_AUTO, "rs_dump", CTLTYPE_INT | CTLFLAG_RW, adapter, 0,
 758             em_get_rs, "I", "Dump RS indexes");
 759
 760         /* Determine hardware and mac info */
 761         em_identify_hardware(ctx);
 762
 763         /* Set isc_msix_bar */
 764         scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR);
 765         scctx->isc_tx_nsegments = EM_MAX_SCATTER;
 766         scctx->isc_tx_tso_segments_max = scctx->isc_tx_nsegments;
 767         scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 768         scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 769         scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
 770         device_printf(dev, "attach_pre capping queues at %d\n", scctx->isc_ntxqsets_max);
 771
 772         scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 773
 774
 775         if (adapter->hw.mac.type >= igb_mac_min) {
 776                 int try_second_bar;
 777
 778                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
 779                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
 780                 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
 781                 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
 782                 scctx->isc_txrx = &igb_txrx;
 783                 scctx->isc_capenable = IGB_CAPS;
 784                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | CSUM_IP6_TCP \
 785                         | CSUM_IP6_UDP | CSUM_IP6_TCP;
 786                 if (adapter->hw.mac.type != e1000_82575)
 787                         scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
 788
 789                 /*
 790                 ** Some new devices, as with ixgbe, now may
 791                 ** use a different BAR, so we need to keep
 792                 ** track of which is used.
 793                 */
 794                 try_second_bar = pci_read_config(dev, scctx->isc_msix_bar, 4);
 795                 if (try_second_bar == 0)
 796                         scctx->isc_msix_bar += 4;
 797
 798         } else if (adapter->hw.mac.type >= em_mac_min) {
 799                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 800                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
 801                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 802                 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
 803                 scctx->isc_txrx = &em_txrx;
 804                 scctx->isc_capenable = EM_CAPS;
 805                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 806         } else {
 807                 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 808                 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
 809                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 810                 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
 811                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 812                 scctx->isc_txrx = &lem_txrx;
 813                 scctx->isc_capenable = EM_CAPS;
 814                 if (adapter->hw.mac.type < e1000_82543)
 815                         scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
 816                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 817                 scctx->isc_msix_bar = 0;
 818         }
 819
 820         /* Setup PCI resources */
 821         if (em_allocate_pci_resources(ctx)) {
 822                 device_printf(dev, "Allocation of PCI resources failed\n");
 823                 error = ENXIO;
 824                 goto err_pci;
 825         }
 826
 827         /*
 828         ** For ICH8 and family we need to
 829         ** map the flash memory, and this
 830         ** must happen after the MAC is
 831         ** identified
 832         */
 833         if ((hw->mac.type == e1000_ich8lan) ||
 834             (hw->mac.type == e1000_ich9lan) ||
 835             (hw->mac.type == e1000_ich10lan) ||
 836             (hw->mac.type == e1000_pchlan) ||
 837             (hw->mac.type == e1000_pch2lan) ||
 838             (hw->mac.type == e1000_pch_lpt)) {
 839                 int rid = EM_BAR_TYPE_FLASH;
 840                 adapter->flash = bus_alloc_resource_any(dev,
 841                     SYS_RES_MEMORY, &rid, RF_ACTIVE);
 842                 if (adapter->flash == NULL) {
 843                         device_printf(dev, "Mapping of Flash failed\n");
 844                         error = ENXIO;
 845                         goto err_pci;
 846                 }
 847                 /* This is used in the shared code */
 848                 hw->flash_address = (u8 *)adapter->flash;
 849                 adapter->osdep.flash_bus_space_tag =
 850                     rman_get_bustag(adapter->flash);
 851                 adapter->osdep.flash_bus_space_handle =
 852                     rman_get_bushandle(adapter->flash);
 853         }
 854         /*
 855         ** In the new SPT device flash is not  a
 856         ** separate BAR, rather it is also in BAR0,
 857         ** so use the same tag and an offset handle for the
 858         ** FLASH read/write macros in the shared code.
 859         */
 860         else if (hw->mac.type == e1000_pch_spt) {
 861                 adapter->osdep.flash_bus_space_tag =
 862                     adapter->osdep.mem_bus_space_tag;
 863                 adapter->osdep.flash_bus_space_handle =
 864                     adapter->osdep.mem_bus_space_handle
 865                     + E1000_FLASH_BASE_ADDR;
 866         }
 867
 868         /* Do Shared Code initialization */
 869         error = e1000_setup_init_funcs(hw, TRUE);
 870         if (error) {
 871                 device_printf(dev, "Setup of Shared code failed, error %d\n",
 872                     error);
 873                 error = ENXIO;
 874                 goto err_pci;
 875         }
 876
 877         em_setup_msix(ctx);
 878         e1000_get_bus_info(hw);
 879
 880         /* Set up some sysctls for the tunable interrupt delays */
 881         em_add_int_delay_sysctl(adapter, "rx_int_delay",
 882             "receive interrupt delay in usecs", &adapter->rx_int_delay,
 883             E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
 884         em_add_int_delay_sysctl(adapter, "tx_int_delay",
 885             "transmit interrupt delay in usecs", &adapter->tx_int_delay,
 886             E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
 887         em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
 888             "receive interrupt delay limit in usecs",
 889             &adapter->rx_abs_int_delay,
 890             E1000_REGISTER(hw, E1000_RADV),
 891             em_rx_abs_int_delay_dflt);
 892         em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
 893             "transmit interrupt delay limit in usecs",
 894             &adapter->tx_abs_int_delay,
 895             E1000_REGISTER(hw, E1000_TADV),
 896             em_tx_abs_int_delay_dflt);
 897         em_add_int_delay_sysctl(adapter, "itr",
 898             "interrupt delay limit in usecs/4",
 899             &adapter->tx_itr,
 900             E1000_REGISTER(hw, E1000_ITR),
 901             DEFAULT_ITR);
 902
 903         hw->mac.autoneg = DO_AUTO_NEG;
 904         hw->phy.autoneg_wait_to_complete = FALSE;
 905         hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 906
 907         if (adapter->hw.mac.type < em_mac_min) {
 908                 e1000_init_script_state_82541(&adapter->hw, TRUE);
 909                 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
 910         }
 911         /* Copper options */
 912         if (hw->phy.media_type == e1000_media_type_copper) {
 913                 hw->phy.mdix = AUTO_ALL_MODES;
 914                 hw->phy.disable_polarity_correction = FALSE;
 915                 hw->phy.ms_type = EM_MASTER_SLAVE;
 916         }
 917
 918         /*
 919          * Set the frame limits assuming
 920          * standard ethernet sized frames.
 921          */
 922         scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
 923             ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
 924
 925         /*
 926          * This controls when hardware reports transmit completion
 927          * status.
 928          */
 929         hw->mac.report_tx_early = 1;
 930
 931         /* Allocate multicast array memory. */
 932         adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN *
 933             MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
 934         if (adapter->mta == NULL) {
 935                 device_printf(dev, "Can not allocate multicast setup array\n");
 936                 error = ENOMEM;
 937                 goto err_late;
 938         }
 939
 940         /* Check SOL/IDER usage */
 941         if (e1000_check_reset_block(hw))
 942                 device_printf(dev, "PHY reset is blocked"
 943                               " due to SOL/IDER session.\n");
 944
 945         /* Sysctl for setting Energy Efficient Ethernet */
 946         hw->dev_spec.ich8lan.eee_disable = eee_setting;
 947         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 948             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 949             OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW,
 950             adapter, 0, em_sysctl_eee, "I",
 951             "Disable Energy Efficient Ethernet");
 952
 953         /*
 954         ** Start from a known state, this is
 955         ** important in reading the nvm and
 956         ** mac from that.
 957         */
 958         e1000_reset_hw(hw);
 959
 960         /* Make sure we have a good EEPROM before we read from it */
 961         if (e1000_validate_nvm_checksum(hw) < 0) {
 962                 /*
 963                 ** Some PCI-E parts fail the first check due to
 964                 ** the link being in sleep state, call it again,
 965                 ** if it fails a second time its a real issue.
 966                 */
 967                 if (e1000_validate_nvm_checksum(hw) < 0) {
 968                         device_printf(dev,
 969                             "The EEPROM Checksum Is Not Valid\n");
 970                         error = EIO;
 971                         goto err_late;
 972                 }
 973         }
 974
 975         /* Copy the permanent MAC address out of the EEPROM */
 976         if (e1000_read_mac_addr(hw) < 0) {
 977                 device_printf(dev, "EEPROM read error while reading MAC"
 978                               " address\n");
 979                 error = EIO;
 980                 goto err_late;
 981         }
 982
 983         if (!em_is_valid_ether_addr(hw->mac.addr)) {
 984                 device_printf(dev, "Invalid MAC address\n");
 985                 error = EIO;
 986                 goto err_late;
 987         }
 988
 989         /* Disable ULP support */
 990         e1000_disable_ulp_lpt_lp(hw, TRUE);
 991
 992         /*
 993          * Get Wake-on-Lan and Management info for later use
 994          */
 995         em_get_wakeup(ctx);
 996
 997         iflib_set_mac(ctx, hw->mac.addr);
 998
 999         return (0);
1000
1001 err_late:
1002         em_release_hw_control(adapter);
1003 err_pci:
1004         em_free_pci_resources(ctx);
1005         free(adapter->mta, M_DEVBUF);
1006
1007         return (error);
1008 }
1009
1010 static int
1011 em_if_attach_post(if_ctx_t ctx)
1012 {
1013         struct adapter *adapter = iflib_get_softc(ctx);
1014         struct e1000_hw *hw = &adapter->hw;
1015         int error = 0;
1016
1017         /* Setup OS specific network interface */
1018         error = em_setup_interface(ctx);
1019         if (error != 0) {
1020                 goto err_late;
1021         }
1022
1023         em_reset(ctx);
1024
1025         /* Initialize statistics */
1026         em_update_stats_counters(adapter);
1027         hw->mac.get_link_status = 1;
1028         em_if_update_admin_status(ctx);
1029         em_add_hw_stats(adapter);
1030
1031         /* Non-AMT based hardware can now take control from firmware */
1032         if (adapter->has_manage && !adapter->has_amt)
1033                 em_get_hw_control(adapter);
1034
1035         INIT_DEBUGOUT("em_if_attach_post: end");
1036
1037         return (error);
1038
1039 err_late:
1040         em_release_hw_control(adapter);
1041         em_free_pci_resources(ctx);
1042         em_if_queues_free(ctx);
1043         free(adapter->mta, M_DEVBUF);
1044
1045         return (error);
1046 }
1047
1048 /*********************************************************************
1049  *  Device removal routine
1050  *
1051  *  The detach entry point is called when the driver is being removed.
1052  *  This routine stops the adapter and deallocates all the resources
1053  *  that were allocated for driver operation.
1054  *
1055  *  return 0 on success, positive on failure
1056  *********************************************************************/
1057
1058 static int
1059 em_if_detach(if_ctx_t ctx)
1060 {
1061         struct adapter  *adapter = iflib_get_softc(ctx);
1062
1063         INIT_DEBUGOUT("em_detach: begin");
1064
1065         e1000_phy_hw_reset(&adapter->hw);
1066
1067         em_release_manageability(adapter);
1068         em_release_hw_control(adapter);
1069         em_free_pci_resources(ctx);
1070
1071         return (0);
1072 }
1073
1074 /*********************************************************************
1075  *
1076  *  Shutdown entry point
1077  *
1078  **********************************************************************/
1079
1080 static int
1081 em_if_shutdown(if_ctx_t ctx)
1082 {
1083         return em_if_suspend(ctx);
1084 }
1085
1086 /*
1087  * Suspend/resume device methods.
1088  */
1089 static int
1090 em_if_suspend(if_ctx_t ctx)
1091 {
1092         struct adapter *adapter = iflib_get_softc(ctx);
1093
1094         em_release_manageability(adapter);
1095         em_release_hw_control(adapter);
1096         em_enable_wakeup(ctx);
1097         return (0);
1098 }
1099
1100 static int
1101 em_if_resume(if_ctx_t ctx)
1102 {
1103         struct adapter *adapter = iflib_get_softc(ctx);
1104
1105         if (adapter->hw.mac.type == e1000_pch2lan)
1106                 e1000_resume_workarounds_pchlan(&adapter->hw);
1107         em_if_init(ctx);
1108         em_init_manageability(adapter);
1109
1110         return(0);
1111 }
1112
1113 static int
1114 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1115 {
1116         int max_frame_size;
1117         struct adapter *adapter = iflib_get_softc(ctx);
1118         if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1119
1120          IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1121
1122         switch (adapter->hw.mac.type) {
1123         case e1000_82571:
1124         case e1000_82572:
1125         case e1000_ich9lan:
1126         case e1000_ich10lan:
1127         case e1000_pch2lan:
1128         case e1000_pch_lpt:
1129         case e1000_pch_spt:
1130         case e1000_82574:
1131         case e1000_82583:
1132         case e1000_80003es2lan:
1133                 /* 9K Jumbo Frame size */
1134                 max_frame_size = 9234;
1135                 break;
1136         case e1000_pchlan:
1137                 max_frame_size = 4096;
1138                 break;
1139         case e1000_82542:
1140         case e1000_ich8lan:
1141                 /* Adapters that do not support jumbo frames */
1142                 max_frame_size = ETHER_MAX_LEN;
1143                 break;
1144         default:
1145                 if (adapter->hw.mac.type >= igb_mac_min)
1146                         max_frame_size = 9234;
1147                 else /* lem */
1148                         max_frame_size = MAX_JUMBO_FRAME_SIZE;
1149         }
1150         if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1151                 return (EINVAL);
1152         }
1153
1154         scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
1155             mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1156         return (0);
1157 }
1158
1159 /*********************************************************************
1160  *  Init entry point
1161  *
1162  *  This routine is used in two ways. It is used by the stack as
1163  *  init entry point in network interface structure. It is also used
1164  *  by the driver as a hw/sw initialization routine to get to a
1165  *  consistent state.
1166  *
1167  *  return 0 on success, positive on failure
1168  **********************************************************************/
1169
1170 static void
1171 em_if_init(if_ctx_t ctx)
1172 {
1173         struct adapter *adapter = iflib_get_softc(ctx);
1174         struct ifnet *ifp = iflib_get_ifp(ctx);
1175         struct em_tx_queue *tx_que;
1176         int i;
1177         INIT_DEBUGOUT("em_if_init: begin");
1178
1179         /* Get the latest mac address, User can use a LAA */
1180         bcopy(if_getlladdr(ifp), adapter->hw.mac.addr,
1181             ETHER_ADDR_LEN);
1182
1183         /* Put the address into the Receive Address Array */
1184         e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1185
1186         /*
1187          * With the 82571 adapter, RAR[0] may be overwritten
1188          * when the other port is reset, we make a duplicate
1189          * in RAR[14] for that eventuality, this assures
1190          * the interface continues to function.
1191          */
1192         if (adapter->hw.mac.type == e1000_82571) {
1193                 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1194                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1195                     E1000_RAR_ENTRIES - 1);
1196         }
1197
1198
1199         /* Initialize the hardware */
1200         em_reset(ctx);
1201         em_if_update_admin_status(ctx);
1202
1203         for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) {
1204                 struct tx_ring *txr = &tx_que->txr;
1205
1206                 txr->tx_rs_cidx = txr->tx_rs_pidx = txr->tx_cidx_processed = 0;
1207         }
1208
1209         /* Setup VLAN support, basic and offload if available */
1210         E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1211
1212         /* Clear bad data from Rx FIFOs */
1213         if (adapter->hw.mac.type >= igb_mac_min)
1214                 e1000_rx_fifo_flush_82575(&adapter->hw);
1215
1216         /* Configure for OS presence */
1217         em_init_manageability(adapter);
1218
1219         /* Prepare transmit descriptors and buffers */
1220         em_initialize_transmit_unit(ctx);
1221
1222         /* Setup Multicast table */
1223         em_if_multi_set(ctx);
1224
1225         /*
1226          * Figure out the desired mbuf
1227          * pool for doing jumbos
1228          */
1229         if (adapter->hw.mac.max_frame_size <= 2048)
1230                 adapter->rx_mbuf_sz = MCLBYTES;
1231 #ifndef CONTIGMALLOC_WORKS
1232         else
1233                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
1234 #else
1235         else if (adapter->hw.mac.max_frame_size <= 4096)
1236                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
1237         else
1238                 adapter->rx_mbuf_sz = MJUM9BYTES;
1239 #endif
1240         em_initialize_receive_unit(ctx);
1241
1242         /* Use real VLAN Filter support? */
1243         if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1244                 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
1245                         /* Use real VLAN Filter support */
1246                         em_setup_vlan_hw_support(adapter);
1247                 else {
1248                         u32 ctrl;
1249                         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1250                         ctrl |= E1000_CTRL_VME;
1251                         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1252                 }
1253         }
1254
1255         /* Don't lose promiscuous settings */
1256         em_if_set_promisc(ctx, IFF_PROMISC);
1257         e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1258
1259         /* MSI/X configuration for 82574 */
1260         if (adapter->hw.mac.type == e1000_82574) {
1261                 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1262
1263                 tmp |= E1000_CTRL_EXT_PBA_CLR;
1264                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1265                 /* Set the IVAR - interrupt vector routing. */
1266                 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars);
1267         } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1268                 igb_configure_queues(adapter);
1269
1270         /* this clears any pending interrupts */
1271         E1000_READ_REG(&adapter->hw, E1000_ICR);
1272         E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC);
1273
1274         /* AMT based hardware can now take control from firmware */
1275         if (adapter->has_manage && adapter->has_amt)
1276                 em_get_hw_control(adapter);
1277
1278         /* Set Energy Efficient Ethernet */
1279         if (adapter->hw.mac.type >= igb_mac_min &&
1280             adapter->hw.phy.media_type == e1000_media_type_copper) {
1281                 if (adapter->hw.mac.type == e1000_i354)
1282                         e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
1283                 else
1284                         e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
1285         }
1286 }
1287
1288 /*********************************************************************
1289  *
1290  *  Fast Legacy/MSI Combined Interrupt Service routine
1291  *
1292  *********************************************************************/
1293 int
1294 em_intr(void *arg)
1295 {
1296         struct adapter *adapter = arg;
1297         if_ctx_t ctx = adapter->ctx;
1298         u32 reg_icr;
1299
1300         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1301
1302         if (adapter->intr_type != IFLIB_INTR_LEGACY)
1303                 goto skip_stray;
1304         /* Hot eject? */
1305         if (reg_icr == 0xffffffff)
1306                 return FILTER_STRAY;
1307
1308         /* Definitely not our interrupt. */
1309         if (reg_icr == 0x0)
1310                 return FILTER_STRAY;
1311
1312         /*
1313          * Starting with the 82571 chip, bit 31 should be used to
1314          * determine whether the interrupt belongs to us.
1315          */
1316         if (adapter->hw.mac.type >= e1000_82571 &&
1317             (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1318                 return FILTER_STRAY;
1319
1320 skip_stray:
1321         /* Link status change */
1322         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1323                 adapter->hw.mac.get_link_status = 1;
1324                 iflib_admin_intr_deferred(ctx);
1325         }
1326
1327         if (reg_icr & E1000_ICR_RXO)
1328                 adapter->rx_overruns++;
1329
1330         return (FILTER_SCHEDULE_THREAD);
1331 }
1332
1333 static void
1334 igb_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq)
1335 {
1336         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims);
1337 }
1338
1339 static void
1340 em_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq)
1341 {
1342         E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims);
1343 }
1344
1345 static void
1346 igb_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq)
1347 {
1348         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims);
1349 }
1350
1351 static void
1352 em_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq)
1353 {
1354         E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims);
1355 }
1356
1357 static int
1358 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1359 {
1360         struct adapter *adapter = iflib_get_softc(ctx);
1361         struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1362
1363         if (adapter->hw.mac.type >= igb_mac_min)
1364                 igb_rx_enable_queue(adapter, rxq);
1365         else
1366                 em_rx_enable_queue(adapter, rxq);
1367         return (0);
1368 }
1369
1370 static int
1371 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1372 {
1373         struct adapter *adapter = iflib_get_softc(ctx);
1374         struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1375
1376         if (adapter->hw.mac.type >= igb_mac_min)
1377                 igb_tx_enable_queue(adapter, txq);
1378         else
1379                 em_tx_enable_queue(adapter, txq);
1380         return (0);
1381 }
1382
1383 /*********************************************************************
1384  *
1385  *  MSIX RX Interrupt Service routine
1386  *
1387  **********************************************************************/
1388 static int
1389 em_msix_que(void *arg)
1390 {
1391         struct em_rx_queue *que = arg;
1392
1393         ++que->irqs;
1394
1395         return (FILTER_SCHEDULE_THREAD);
1396 }
1397
1398 /*********************************************************************
1399  *
1400  *  MSIX Link Fast Interrupt Service routine
1401  *
1402  **********************************************************************/
1403 static int
1404 em_msix_link(void *arg)
1405 {
1406         struct adapter *adapter = arg;
1407         u32 reg_icr;
1408
1409         ++adapter->link_irq;
1410         MPASS(adapter->hw.back != NULL);
1411         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1412
1413         if (reg_icr & E1000_ICR_RXO)
1414                 adapter->rx_overruns++;
1415
1416         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1417                 em_handle_link(adapter->ctx);
1418         } else {
1419                 E1000_WRITE_REG(&adapter->hw, E1000_IMS,
1420                                 EM_MSIX_LINK | E1000_IMS_LSC);
1421                 if (adapter->hw.mac.type >= igb_mac_min)
1422                         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1423         }
1424
1425         /*
1426          * Because we must read the ICR for this interrupt
1427          * it may clear other causes using autoclear, for
1428          * this reason we simply create a soft interrupt
1429          * for all these vectors.
1430          */
1431         if (reg_icr && adapter->hw.mac.type < igb_mac_min) {
1432                 E1000_WRITE_REG(&adapter->hw,
1433                         E1000_ICS, adapter->ims);
1434         }
1435
1436         return (FILTER_HANDLED);
1437 }
1438
1439 static void
1440 em_handle_link(void *context)
1441 {
1442         if_ctx_t ctx = context;
1443         struct adapter *adapter = iflib_get_softc(ctx);
1444
1445         adapter->hw.mac.get_link_status = 1;
1446         iflib_admin_intr_deferred(ctx);
1447 }
1448
1449
1450 /*********************************************************************
1451  *
1452  *  Media Ioctl callback
1453  *
1454  *  This routine is called whenever the user queries the status of
1455  *  the interface using ifconfig.
1456  *
1457  **********************************************************************/
1458 static void
1459 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1460 {
1461         struct adapter *adapter = iflib_get_softc(ctx);
1462         u_char fiber_type = IFM_1000_SX;
1463
1464         INIT_DEBUGOUT("em_if_media_status: begin");
1465
1466         iflib_admin_intr_deferred(ctx);
1467
1468         ifmr->ifm_status = IFM_AVALID;
1469         ifmr->ifm_active = IFM_ETHER;
1470
1471         if (!adapter->link_active) {
1472                 return;
1473         }
1474
1475         ifmr->ifm_status |= IFM_ACTIVE;
1476
1477         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
1478             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1479                 if (adapter->hw.mac.type == e1000_82545)
1480                         fiber_type = IFM_1000_LX;
1481                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1482         } else {
1483                 switch (adapter->link_speed) {
1484                 case 10:
1485                         ifmr->ifm_active |= IFM_10_T;
1486                         break;
1487                 case 100:
1488                         ifmr->ifm_active |= IFM_100_TX;
1489                         break;
1490                 case 1000:
1491                         ifmr->ifm_active |= IFM_1000_T;
1492                         break;
1493                 }
1494                 if (adapter->link_duplex == FULL_DUPLEX)
1495                         ifmr->ifm_active |= IFM_FDX;
1496                 else
1497                         ifmr->ifm_active |= IFM_HDX;
1498         }
1499 }
1500
1501 /*********************************************************************
1502  *
1503  *  Media Ioctl callback
1504  *
1505  *  This routine is called when the user changes speed/duplex using
1506  *  media/mediopt option with ifconfig.
1507  *
1508  **********************************************************************/
1509 static int
1510 em_if_media_change(if_ctx_t ctx)
1511 {
1512         struct adapter *adapter = iflib_get_softc(ctx);
1513         struct ifmedia *ifm = iflib_get_media(ctx);
1514
1515         INIT_DEBUGOUT("em_if_media_change: begin");
1516
1517         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1518                 return (EINVAL);
1519
1520         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1521         case IFM_AUTO:
1522                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1523                 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1524                 break;
1525         case IFM_1000_LX:
1526         case IFM_1000_SX:
1527         case IFM_1000_T:
1528                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1529                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1530                 break;
1531         case IFM_100_TX:
1532                 adapter->hw.mac.autoneg = FALSE;
1533                 adapter->hw.phy.autoneg_advertised = 0;
1534                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1535                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1536                 else
1537                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1538                 break;
1539         case IFM_10_T:
1540                 adapter->hw.mac.autoneg = FALSE;
1541                 adapter->hw.phy.autoneg_advertised = 0;
1542                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1543                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1544                 else
1545                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1546                 break;
1547         default:
1548                 device_printf(adapter->dev, "Unsupported media type\n");
1549         }
1550
1551         em_if_init(ctx);
1552
1553         return (0);
1554 }
1555
1556 static int
1557 em_if_set_promisc(if_ctx_t ctx, int flags)
1558 {
1559         struct adapter *adapter = iflib_get_softc(ctx);
1560         u32 reg_rctl;
1561
1562         em_disable_promisc(ctx);
1563
1564         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1565
1566         if (flags & IFF_PROMISC) {
1567                 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1568                 /* Turn this on if you want to see bad packets */
1569                 if (em_debug_sbp)
1570                         reg_rctl |= E1000_RCTL_SBP;
1571                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1572         } else if (flags & IFF_ALLMULTI) {
1573                 reg_rctl |= E1000_RCTL_MPE;
1574                 reg_rctl &= ~E1000_RCTL_UPE;
1575                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1576         }
1577         return (0);
1578 }
1579
1580 static void
1581 em_disable_promisc(if_ctx_t ctx)
1582 {
1583         struct adapter *adapter = iflib_get_softc(ctx);
1584         struct ifnet *ifp = iflib_get_ifp(ctx);
1585         u32 reg_rctl;
1586         int mcnt = 0;
1587
1588         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1589         reg_rctl &= (~E1000_RCTL_UPE);
1590         if (if_getflags(ifp) & IFF_ALLMULTI)
1591                 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1592         else
1593                 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES);
1594         /* Don't disable if in MAX groups */
1595         if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1596                 reg_rctl &=  (~E1000_RCTL_MPE);
1597         reg_rctl &=  (~E1000_RCTL_SBP);
1598         E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1599 }
1600
1601
1602 /*********************************************************************
1603  *  Multicast Update
1604  *
1605  *  This routine is called whenever multicast address list is updated.
1606  *
1607  **********************************************************************/
1608
1609 static void
1610 em_if_multi_set(if_ctx_t ctx)
1611 {
1612         struct adapter *adapter = iflib_get_softc(ctx);
1613         struct ifnet *ifp = iflib_get_ifp(ctx);
1614         u32 reg_rctl = 0;
1615         u8  *mta; /* Multicast array memory */
1616         int mcnt = 0;
1617
1618         IOCTL_DEBUGOUT("em_set_multi: begin");
1619
1620         mta = adapter->mta;
1621         bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1622
1623         if (adapter->hw.mac.type == e1000_82542 &&
1624             adapter->hw.revision_id == E1000_REVISION_2) {
1625                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1626                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1627                         e1000_pci_clear_mwi(&adapter->hw);
1628                 reg_rctl |= E1000_RCTL_RST;
1629                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1630                 msec_delay(5);
1631         }
1632
1633         if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES);
1634
1635         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1636                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1637                 reg_rctl |= E1000_RCTL_MPE;
1638                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1639         } else
1640                 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
1641
1642         if (adapter->hw.mac.type == e1000_82542 &&
1643             adapter->hw.revision_id == E1000_REVISION_2) {
1644                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1645                 reg_rctl &= ~E1000_RCTL_RST;
1646                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1647                 msec_delay(5);
1648                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1649                         e1000_pci_set_mwi(&adapter->hw);
1650         }
1651 }
1652
1653
1654 /*********************************************************************
1655  *  Timer routine
1656  *
1657  *  This routine checks for link status and updates statistics.
1658  *
1659  **********************************************************************/
1660
1661 static void
1662 em_if_timer(if_ctx_t ctx, uint16_t qid)
1663 {
1664         struct adapter *adapter = iflib_get_softc(ctx);
1665         struct em_rx_queue *que;
1666         int i;
1667         int trigger = 0;
1668
1669         if (qid != 0)
1670                 return;
1671
1672         iflib_admin_intr_deferred(ctx);
1673         /* Reset LAA into RAR[0] on 82571 */
1674         if ((adapter->hw.mac.type == e1000_82571) &&
1675             e1000_get_laa_state_82571(&adapter->hw))
1676                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1677
1678         if (adapter->hw.mac.type < em_mac_min)
1679                 lem_smartspeed(adapter);
1680
1681         /* Mask to use in the irq trigger */
1682         if (adapter->intr_type == IFLIB_INTR_MSIX) {
1683                 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++)
1684                         trigger |= que->eims;
1685         } else {
1686                 trigger = E1000_ICS_RXDMT0;
1687         }
1688 }
1689
1690
1691 static void
1692 em_if_update_admin_status(if_ctx_t ctx)
1693 {
1694         struct adapter *adapter = iflib_get_softc(ctx);
1695         struct e1000_hw *hw = &adapter->hw;
1696         struct ifnet *ifp = iflib_get_ifp(ctx);
1697         device_t dev = iflib_get_dev(ctx);
1698         u32 link_check, thstat, ctrl;
1699
1700         link_check = thstat = ctrl = 0;
1701         /* Get the cached link value or read phy for real */
1702         switch (hw->phy.media_type) {
1703         case e1000_media_type_copper:
1704                 if (hw->mac.get_link_status) {
1705                         if (hw->mac.type == e1000_pch_spt)
1706                                 msec_delay(50);
1707                         /* Do the work to read phy */
1708                         e1000_check_for_link(hw);
1709                         link_check = !hw->mac.get_link_status;
1710                         if (link_check) /* ESB2 fix */
1711                                 e1000_cfg_on_link_up(hw);
1712                 } else {
1713                         link_check = TRUE;
1714                 }
1715                 break;
1716         case e1000_media_type_fiber:
1717                 e1000_check_for_link(hw);
1718                 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1719                             E1000_STATUS_LU);
1720                 break;
1721         case e1000_media_type_internal_serdes:
1722                 e1000_check_for_link(hw);
1723                 link_check = adapter->hw.mac.serdes_has_link;
1724                 break;
1725         /* VF device is type_unknown */
1726         case e1000_media_type_unknown:
1727                 e1000_check_for_link(hw);
1728                 link_check = !hw->mac.get_link_status;
1729                 /* FALLTHROUGH */
1730         default:
1731                 break;
1732         }
1733
1734         /* Check for thermal downshift or shutdown */
1735         if (hw->mac.type == e1000_i350) {
1736                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1737                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1738         }
1739
1740         /* Now check for a transition */
1741         if (link_check && (adapter->link_active == 0)) {
1742                 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
1743                     &adapter->link_duplex);
1744                 /* Check if we must disable SPEED_MODE bit on PCI-E */
1745                 if ((adapter->link_speed != SPEED_1000) &&
1746                     ((hw->mac.type == e1000_82571) ||
1747                     (hw->mac.type == e1000_82572))) {
1748                         int tarc0;
1749                         tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1750                         tarc0 &= ~TARC_SPEED_MODE_BIT;
1751                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1752                 }
1753                 if (bootverbose)
1754                         device_printf(dev, "Link is up %d Mbps %s\n",
1755                             adapter->link_speed,
1756                             ((adapter->link_duplex == FULL_DUPLEX) ?
1757                             "Full Duplex" : "Half Duplex"));
1758                 adapter->link_active = 1;
1759                 adapter->smartspeed = 0;
1760                 if_setbaudrate(ifp, adapter->link_speed * 1000000);
1761                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1762                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1763                         device_printf(dev, "Link: thermal downshift\n");
1764                 /* Delay Link Up for Phy update */
1765                 if (((hw->mac.type == e1000_i210) ||
1766                     (hw->mac.type == e1000_i211)) &&
1767                     (hw->phy.id == I210_I_PHY_ID))
1768                         msec_delay(I210_LINK_DELAY);
1769                 /* Reset if the media type changed. */
1770                 if ((hw->dev_spec._82575.media_changed) &&
1771                         (adapter->hw.mac.type >= igb_mac_min)) {
1772                         hw->dev_spec._82575.media_changed = false;
1773                         adapter->flags |= IGB_MEDIA_RESET;
1774                         em_reset(ctx);
1775                 }
1776                 iflib_link_state_change(ctx, LINK_STATE_UP, ifp->if_baudrate);
1777                 printf("Link state changed to up\n");
1778         } else if (!link_check && (adapter->link_active == 1)) {
1779                 if_setbaudrate(ifp, 0);
1780                 adapter->link_speed = 0;
1781                 adapter->link_duplex = 0;
1782                 if (bootverbose)
1783                         device_printf(dev, "Link is Down\n");
1784                 adapter->link_active = 0;
1785                 iflib_link_state_change(ctx, LINK_STATE_DOWN, ifp->if_baudrate);
1786                 printf("link state changed to down\n");
1787         }
1788         em_update_stats_counters(adapter);
1789
1790         E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC);
1791 }
1792
1793 /*********************************************************************
1794  *
1795  *  This routine disables all traffic on the adapter by issuing a
1796  *  global reset on the MAC and deallocates TX/RX buffers.
1797  *
1798  *  This routine should always be called with BOTH the CORE
1799  *  and TX locks.
1800  **********************************************************************/
1801
1802 static void
1803 em_if_stop(if_ctx_t ctx)
1804 {
1805         struct adapter *adapter = iflib_get_softc(ctx);
1806
1807         INIT_DEBUGOUT("em_stop: begin");
1808
1809         e1000_reset_hw(&adapter->hw);
1810         if (adapter->hw.mac.type >= e1000_82544)
1811                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0);
1812
1813         e1000_led_off(&adapter->hw);
1814         e1000_cleanup_led(&adapter->hw);
1815 }
1816
1817
1818 /*********************************************************************
1819  *
1820  *  Determine hardware revision.
1821  *
1822  **********************************************************************/
1823 static void
1824 em_identify_hardware(if_ctx_t ctx)
1825 {
1826         device_t dev = iflib_get_dev(ctx);
1827         struct adapter *adapter = iflib_get_softc(ctx);
1828
1829         /* Make sure our PCI config space has the necessary stuff set */
1830         adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1831
1832         /* Save off the information about this board */
1833         adapter->hw.vendor_id = pci_get_vendor(dev);
1834         adapter->hw.device_id = pci_get_device(dev);
1835         adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1836         adapter->hw.subsystem_vendor_id =
1837             pci_read_config(dev, PCIR_SUBVEND_0, 2);
1838         adapter->hw.subsystem_device_id =
1839             pci_read_config(dev, PCIR_SUBDEV_0, 2);
1840
1841         /* Do Shared Code Init and Setup */
1842         if (e1000_set_mac_type(&adapter->hw)) {
1843                 device_printf(dev, "Setup init failure\n");
1844                 return;
1845         }
1846 }
1847
1848 static int
1849 em_allocate_pci_resources(if_ctx_t ctx)
1850 {
1851         struct adapter *adapter = iflib_get_softc(ctx);
1852         device_t dev = iflib_get_dev(ctx);
1853         int rid, val;
1854
1855         rid = PCIR_BAR(0);
1856         adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1857             &rid, RF_ACTIVE);
1858         if (adapter->memory == NULL) {
1859                 device_printf(dev, "Unable to allocate bus resource: memory\n");
1860                 return (ENXIO);
1861         }
1862         adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory);
1863         adapter->osdep.mem_bus_space_handle =
1864             rman_get_bushandle(adapter->memory);
1865         adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle;
1866
1867         /* Only older adapters use IO mapping */
1868         if (adapter->hw.mac.type < em_mac_min &&
1869             adapter->hw.mac.type > e1000_82543) {
1870                 /* Figure our where our IO BAR is ? */
1871                 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1872                         val = pci_read_config(dev, rid, 4);
1873                         if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1874                                 adapter->io_rid = rid;
1875                                 break;
1876                         }
1877                         rid += 4;
1878                         /* check for 64bit BAR */
1879                         if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1880                                 rid += 4;
1881                 }
1882                 if (rid >= PCIR_CIS) {
1883                         device_printf(dev, "Unable to locate IO BAR\n");
1884                         return (ENXIO);
1885                 }
1886                 adapter->ioport = bus_alloc_resource_any(dev,
1887                     SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE);
1888                 if (adapter->ioport == NULL) {
1889                         device_printf(dev, "Unable to allocate bus resource: "
1890                             "ioport\n");
1891                         return (ENXIO);
1892                 }
1893                 adapter->hw.io_base = 0;
1894                 adapter->osdep.io_bus_space_tag =
1895                     rman_get_bustag(adapter->ioport);
1896                 adapter->osdep.io_bus_space_handle =
1897                     rman_get_bushandle(adapter->ioport);
1898         }
1899
1900         adapter->hw.back = &adapter->osdep;
1901
1902         return (0);
1903 }
1904
1905 /*********************************************************************
1906  *
1907  *  Setup the MSIX Interrupt handlers
1908  *
1909  **********************************************************************/
1910 static int
1911 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
1912 {
1913         struct adapter *adapter = iflib_get_softc(ctx);
1914         struct em_rx_queue *rx_que = adapter->rx_queues;
1915         struct em_tx_queue *tx_que = adapter->tx_queues;
1916         int error, rid, i, vector = 0, rx_vectors;
1917         char buf[16];
1918
1919         /* First set up ring resources */
1920         for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) {
1921                 rid = vector + 1;
1922                 snprintf(buf, sizeof(buf), "rxq%d", i);
1923                 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
1924                 if (error) {
1925                         device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
1926                         adapter->rx_num_queues = i + 1;
1927                         goto fail;
1928                 }
1929
1930                 rx_que->msix =  vector;
1931
1932                 /*
1933                  * Set the bit to enable interrupt
1934                  * in E1000_IMS -- bits 20 and 21
1935                  * are for RX0 and RX1, note this has
1936                  * NOTHING to do with the MSIX vector
1937                  */
1938                 if (adapter->hw.mac.type == e1000_82574) {
1939                         rx_que->eims = 1 << (20 + i);
1940                         adapter->ims |= rx_que->eims;
1941                         adapter->ivars |= (8 | rx_que->msix) << (i * 4);
1942                 } else if (adapter->hw.mac.type == e1000_82575)
1943                         rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
1944                 else
1945                         rx_que->eims = 1 << vector;
1946         }
1947         rx_vectors = vector;
1948
1949         vector = 0;
1950         for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) {
1951                 rid = vector + 1;
1952                 snprintf(buf, sizeof(buf), "txq%d", i);
1953                 tx_que = &adapter->tx_queues[i];
1954                 iflib_softirq_alloc_generic(ctx, rid, IFLIB_INTR_TX, tx_que, tx_que->me, buf);
1955
1956                 tx_que->msix = (vector % adapter->tx_num_queues);
1957
1958                 /*
1959                  * Set the bit to enable interrupt
1960                  * in E1000_IMS -- bits 22 and 23
1961                  * are for TX0 and TX1, note this has
1962                  * NOTHING to do with the MSIX vector
1963                  */
1964                 if (adapter->hw.mac.type == e1000_82574) {
1965                         tx_que->eims = 1 << (22 + i);
1966                         adapter->ims |= tx_que->eims;
1967                         adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
1968                 } else if (adapter->hw.mac.type == e1000_82575) {
1969                         tx_que->eims = E1000_EICR_TX_QUEUE0 << (i %  adapter->tx_num_queues);
1970                 } else {
1971                         tx_que->eims = 1 << (i %  adapter->tx_num_queues);
1972                 }
1973         }
1974
1975         /* Link interrupt */
1976         rid = rx_vectors + 1;
1977         error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq");
1978
1979         if (error) {
1980                 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
1981                 goto fail;
1982         }
1983         adapter->linkvec = rx_vectors;
1984         if (adapter->hw.mac.type < igb_mac_min) {
1985                 adapter->ivars |=  (8 | rx_vectors) << 16;
1986                 adapter->ivars |= 0x80000000;
1987         }
1988         return (0);
1989 fail:
1990         iflib_irq_free(ctx, &adapter->irq);
1991         rx_que = adapter->rx_queues;
1992         for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++)
1993                 iflib_irq_free(ctx, &rx_que->que_irq);
1994         return (error);
1995 }
1996
1997 static void
1998 igb_configure_queues(struct adapter *adapter)
1999 {
2000         struct e1000_hw *hw = &adapter->hw;
2001         struct em_rx_queue *rx_que;
2002         struct em_tx_queue *tx_que;
2003         u32 tmp, ivar = 0, newitr = 0;
2004
2005         /* First turn on RSS capability */
2006         if (adapter->hw.mac.type != e1000_82575)
2007                 E1000_WRITE_REG(hw, E1000_GPIE,
2008                     E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
2009                     E1000_GPIE_PBA | E1000_GPIE_NSICR);
2010
2011         /* Turn on MSIX */
2012         switch (adapter->hw.mac.type) {
2013         case e1000_82580:
2014         case e1000_i350:
2015         case e1000_i354:
2016         case e1000_i210:
2017         case e1000_i211:
2018         case e1000_vfadapt:
2019         case e1000_vfadapt_i350:
2020                 /* RX entries */
2021                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2022                         u32 index = i >> 1;
2023                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2024                         rx_que = &adapter->rx_queues[i];
2025                         if (i & 1) {
2026                                 ivar &= 0xFF00FFFF;
2027                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2028                         } else {
2029                                 ivar &= 0xFFFFFF00;
2030                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2031                         }
2032                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2033                 }
2034                 /* TX entries */
2035                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2036                         u32 index = i >> 1;
2037                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2038                         tx_que = &adapter->tx_queues[i];
2039                         if (i & 1) {
2040                                 ivar &= 0x00FFFFFF;
2041                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2042                         } else {
2043                                 ivar &= 0xFFFF00FF;
2044                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2045                         }
2046                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2047                         adapter->que_mask |= tx_que->eims;
2048                 }
2049
2050                 /* And for the link interrupt */
2051                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2052                 adapter->link_mask = 1 << adapter->linkvec;
2053                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2054                 break;
2055         case e1000_82576:
2056                 /* RX entries */
2057                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2058                         u32 index = i & 0x7; /* Each IVAR has two entries */
2059                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2060                         rx_que = &adapter->rx_queues[i];
2061                         if (i < 8) {
2062                                 ivar &= 0xFFFFFF00;
2063                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2064                         } else {
2065                                 ivar &= 0xFF00FFFF;
2066                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2067                         }
2068                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2069                         adapter->que_mask |= rx_que->eims;
2070                 }
2071                 /* TX entries */
2072                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2073                         u32 index = i & 0x7; /* Each IVAR has two entries */
2074                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2075                         tx_que = &adapter->tx_queues[i];
2076                         if (i < 8) {
2077                                 ivar &= 0xFFFF00FF;
2078                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2079                         } else {
2080                                 ivar &= 0x00FFFFFF;
2081                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2082                         }
2083                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2084                         adapter->que_mask |= tx_que->eims;
2085                 }
2086
2087                 /* And for the link interrupt */
2088                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2089                 adapter->link_mask = 1 << adapter->linkvec;
2090                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2091                 break;
2092
2093         case e1000_82575:
2094                 /* enable MSI-X support*/
2095                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2096                 tmp |= E1000_CTRL_EXT_PBA_CLR;
2097                 /* Auto-Mask interrupts upon ICR read. */
2098                 tmp |= E1000_CTRL_EXT_EIAME;
2099                 tmp |= E1000_CTRL_EXT_IRCA;
2100                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2101
2102                 /* Queues */
2103                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2104                         rx_que = &adapter->rx_queues[i];
2105                         tmp = E1000_EICR_RX_QUEUE0 << i;
2106                         tmp |= E1000_EICR_TX_QUEUE0 << i;
2107                         rx_que->eims = tmp;
2108                         E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2109                             i, rx_que->eims);
2110                         adapter->que_mask |= rx_que->eims;
2111                 }
2112
2113                 /* Link */
2114                 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec),
2115                     E1000_EIMS_OTHER);
2116                 adapter->link_mask |= E1000_EIMS_OTHER;
2117         default:
2118                 break;
2119         }
2120
2121         /* Set the starting interrupt rate */
2122         if (em_max_interrupt_rate > 0)
2123                 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2124
2125         if (hw->mac.type == e1000_82575)
2126                 newitr |= newitr << 16;
2127         else
2128                 newitr |= E1000_EITR_CNT_IGNR;
2129
2130         for (int i = 0; i < adapter->rx_num_queues; i++) {
2131                 rx_que = &adapter->rx_queues[i];
2132                 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2133         }
2134
2135         return;
2136 }
2137
2138 static void
2139 em_free_pci_resources(if_ctx_t ctx)
2140 {
2141         struct adapter *adapter = iflib_get_softc(ctx);
2142         struct em_rx_queue *que = adapter->rx_queues;
2143         device_t dev = iflib_get_dev(ctx);
2144
2145         /* Release all msix queue resources */
2146         if (adapter->intr_type == IFLIB_INTR_MSIX)
2147                 iflib_irq_free(ctx, &adapter->irq);
2148
2149         for (int i = 0; i < adapter->rx_num_queues; i++, que++) {
2150                 iflib_irq_free(ctx, &que->que_irq);
2151         }
2152
2153         /* First release all the interrupt resources */
2154         if (adapter->memory != NULL) {
2155                 bus_release_resource(dev, SYS_RES_MEMORY,
2156                                      PCIR_BAR(0), adapter->memory);
2157                 adapter->memory = NULL;
2158         }
2159
2160         if (adapter->flash != NULL) {
2161                 bus_release_resource(dev, SYS_RES_MEMORY,
2162                                      EM_FLASH, adapter->flash);
2163                 adapter->flash = NULL;
2164         }
2165         if (adapter->ioport != NULL)
2166                 bus_release_resource(dev, SYS_RES_IOPORT,
2167                     adapter->io_rid, adapter->ioport);
2168 }
2169
2170 /* Setup MSI or MSI/X */
2171 static int
2172 em_setup_msix(if_ctx_t ctx)
2173 {
2174         struct adapter *adapter = iflib_get_softc(ctx);
2175
2176         if (adapter->hw.mac.type == e1000_82574) {
2177                 em_enable_vectors_82574(ctx);
2178         }
2179         return (0);
2180 }
2181
2182 /*********************************************************************
2183  *
2184  *  Initialize the hardware to a configuration
2185  *  as specified by the adapter structure.
2186  *
2187  **********************************************************************/
2188
2189 static void
2190 lem_smartspeed(struct adapter *adapter)
2191 {
2192         u16 phy_tmp;
2193
2194         if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) ||
2195             adapter->hw.mac.autoneg == 0 ||
2196             (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2197                 return;
2198
2199         if (adapter->smartspeed == 0) {
2200                 /* If Master/Slave config fault is asserted twice,
2201                  * we assume back-to-back */
2202                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2203                 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2204                         return;
2205                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2206                 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2207                         e1000_read_phy_reg(&adapter->hw,
2208                             PHY_1000T_CTRL, &phy_tmp);
2209                         if(phy_tmp & CR_1000T_MS_ENABLE) {
2210                                 phy_tmp &= ~CR_1000T_MS_ENABLE;
2211                                 e1000_write_phy_reg(&adapter->hw,
2212                                     PHY_1000T_CTRL, phy_tmp);
2213                                 adapter->smartspeed++;
2214                                 if(adapter->hw.mac.autoneg &&
2215                                    !e1000_copper_link_autoneg(&adapter->hw) &&
2216                                    !e1000_read_phy_reg(&adapter->hw,
2217                                     PHY_CONTROL, &phy_tmp)) {
2218                                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2219                                                     MII_CR_RESTART_AUTO_NEG);
2220                                         e1000_write_phy_reg(&adapter->hw,
2221                                             PHY_CONTROL, phy_tmp);
2222                                 }
2223                         }
2224                 }
2225                 return;
2226         } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2227                 /* If still no link, perhaps using 2/3 pair cable */
2228                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2229                 phy_tmp |= CR_1000T_MS_ENABLE;
2230                 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2231                 if(adapter->hw.mac.autoneg &&
2232                    !e1000_copper_link_autoneg(&adapter->hw) &&
2233                    !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2234                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2235                                     MII_CR_RESTART_AUTO_NEG);
2236                         e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2237                 }
2238         }
2239         /* Restart process after EM_SMARTSPEED_MAX iterations */
2240         if(adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2241                 adapter->smartspeed = 0;
2242 }
2243
2244 /*********************************************************************
2245  *
2246  *  Initialize the DMA Coalescing feature
2247  *
2248  **********************************************************************/
2249 static void
2250 igb_init_dmac(struct adapter *adapter, u32 pba)
2251 {
2252         device_t        dev = adapter->dev;
2253         struct e1000_hw *hw = &adapter->hw;
2254         u32             dmac, reg = ~E1000_DMACR_DMAC_EN;
2255         u16             hwm;
2256         u16             max_frame_size;
2257
2258         if (hw->mac.type == e1000_i211)
2259                 return;
2260
2261         max_frame_size = adapter->shared->isc_max_frame_size;
2262         if (hw->mac.type > e1000_82580) {
2263
2264                 if (adapter->dmac == 0) { /* Disabling it */
2265                         E1000_WRITE_REG(hw, E1000_DMACR, reg);
2266                         return;
2267                 } else
2268                         device_printf(dev, "DMA Coalescing enabled\n");
2269
2270                 /* Set starting threshold */
2271                 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
2272
2273                 hwm = 64 * pba - max_frame_size / 16;
2274                 if (hwm < 64 * (pba - 6))
2275                         hwm = 64 * (pba - 6);
2276                 reg = E1000_READ_REG(hw, E1000_FCRTC);
2277                 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
2278                 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
2279                     & E1000_FCRTC_RTH_COAL_MASK);
2280                 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
2281
2282
2283                 dmac = pba - max_frame_size / 512;
2284                 if (dmac < pba - 10)
2285                         dmac = pba - 10;
2286                 reg = E1000_READ_REG(hw, E1000_DMACR);
2287                 reg &= ~E1000_DMACR_DMACTHR_MASK;
2288                 reg = ((dmac << E1000_DMACR_DMACTHR_SHIFT)
2289                     & E1000_DMACR_DMACTHR_MASK);
2290
2291                 /* transition to L0x or L1 if available..*/
2292                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
2293
2294                 /* Check if status is 2.5Gb backplane connection
2295                 * before configuration of watchdog timer, which is
2296                 * in msec values in 12.8usec intervals
2297                 * watchdog timer= msec values in 32usec intervals
2298                 * for non 2.5Gb connection
2299                 */
2300                 if (hw->mac.type == e1000_i354) {
2301                         int status = E1000_READ_REG(hw, E1000_STATUS);
2302                         if ((status & E1000_STATUS_2P5_SKU) &&
2303                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2304                                 reg |= ((adapter->dmac * 5) >> 6);
2305                         else
2306                                 reg |= (adapter->dmac >> 5);
2307                 } else {
2308                         reg |= (adapter->dmac >> 5);
2309                 }
2310
2311                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2312
2313                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
2314
2315                 /* Set the interval before transition */
2316                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
2317                 if (hw->mac.type == e1000_i350)
2318                         reg |= IGB_DMCTLX_DCFLUSH_DIS;
2319                 /*
2320                 ** in 2.5Gb connection, TTLX unit is 0.4 usec
2321                 ** which is 0x4*2 = 0xA. But delay is still 4 usec
2322                 */
2323                 if (hw->mac.type == e1000_i354) {
2324                         int status = E1000_READ_REG(hw, E1000_STATUS);
2325                         if ((status & E1000_STATUS_2P5_SKU) &&
2326                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2327                                 reg |= 0xA;
2328                         else
2329                                 reg |= 0x4;
2330                 } else {
2331                         reg |= 0x4;
2332                 }
2333
2334                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
2335
2336                 /* free space in tx packet buffer to wake from DMA coal */
2337                 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE -
2338                     (2 * max_frame_size)) >> 6);
2339
2340                 /* make low power state decision controlled by DMA coal */
2341                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2342                 reg &= ~E1000_PCIEMISC_LX_DECISION;
2343                 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
2344
2345         } else if (hw->mac.type == e1000_82580) {
2346                 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2347                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
2348                     reg & ~E1000_PCIEMISC_LX_DECISION);
2349                 E1000_WRITE_REG(hw, E1000_DMACR, 0);
2350         }
2351 }
2352
2353 static void
2354 em_reset(if_ctx_t ctx)
2355 {
2356         device_t dev = iflib_get_dev(ctx);
2357         struct adapter *adapter = iflib_get_softc(ctx);
2358         struct ifnet *ifp = iflib_get_ifp(ctx);
2359         struct e1000_hw *hw = &adapter->hw;
2360         u16 rx_buffer_size;
2361         u32 pba;
2362
2363         INIT_DEBUGOUT("em_reset: begin");
2364         /* Let the firmware know the OS is in control */
2365         em_get_hw_control(adapter);
2366
2367         /* Set up smart power down as default off on newer adapters. */
2368         if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2369             hw->mac.type == e1000_82572)) {
2370                 u16 phy_tmp = 0;
2371
2372                 /* Speed up time to link by disabling smart power down. */
2373                 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2374                 phy_tmp &= ~IGP02E1000_PM_SPD;
2375                 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2376         }
2377
2378         /*
2379          * Packet Buffer Allocation (PBA)
2380          * Writing PBA sets the receive portion of the buffer
2381          * the remainder is used for the transmit buffer.
2382          */
2383         switch (hw->mac.type) {
2384         /* Total Packet Buffer on these is 48K */
2385         case e1000_82571:
2386         case e1000_82572:
2387         case e1000_80003es2lan:
2388                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2389                 break;
2390         case e1000_82573: /* 82573: Total Packet Buffer is 32K */
2391                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2392                 break;
2393         case e1000_82574:
2394         case e1000_82583:
2395                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2396                 break;
2397         case e1000_ich8lan:
2398                 pba = E1000_PBA_8K;
2399                 break;
2400         case e1000_ich9lan:
2401         case e1000_ich10lan:
2402                 /* Boost Receive side for jumbo frames */
2403                 if (adapter->hw.mac.max_frame_size > 4096)
2404                         pba = E1000_PBA_14K;
2405                 else
2406                         pba = E1000_PBA_10K;
2407                 break;
2408         case e1000_pchlan:
2409         case e1000_pch2lan:
2410         case e1000_pch_lpt:
2411         case e1000_pch_spt:
2412                 pba = E1000_PBA_26K;
2413                 break;
2414         case e1000_82575:
2415                 pba = E1000_PBA_32K;
2416                 break;
2417         case e1000_82576:
2418         case e1000_vfadapt:
2419                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2420                 pba &= E1000_RXPBS_SIZE_MASK_82576;
2421                 break;
2422         case e1000_82580:
2423         case e1000_i350:
2424         case e1000_i354:
2425         case e1000_vfadapt_i350:
2426                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2427                 pba = e1000_rxpbs_adjust_82580(pba);
2428                 break;
2429         case e1000_i210:
2430         case e1000_i211:
2431                 pba = E1000_PBA_34K;
2432                 break;
2433         default:
2434                 if (adapter->hw.mac.max_frame_size > 8192)
2435                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2436                 else
2437                         pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2438         }
2439
2440         /* Special needs in case of Jumbo frames */
2441         if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) {
2442                 u32 tx_space, min_tx, min_rx;
2443                 pba = E1000_READ_REG(hw, E1000_PBA);
2444                 tx_space = pba >> 16;
2445                 pba &= 0xffff;
2446                 min_tx = (adapter->hw.mac.max_frame_size +
2447                     sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
2448                 min_tx = roundup2(min_tx, 1024);
2449                 min_tx >>= 10;
2450                 min_rx = adapter->hw.mac.max_frame_size;
2451                 min_rx = roundup2(min_rx, 1024);
2452                 min_rx >>= 10;
2453                 if (tx_space < min_tx &&
2454                     ((min_tx - tx_space) < pba)) {
2455                         pba = pba - (min_tx - tx_space);
2456                         /*
2457                          * if short on rx space, rx wins
2458                          * and must trump tx adjustment
2459                          */
2460                         if (pba < min_rx)
2461                                 pba = min_rx;
2462                 }
2463                 E1000_WRITE_REG(hw, E1000_PBA, pba);
2464         }
2465
2466         if (hw->mac.type < igb_mac_min)
2467                 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
2468
2469         INIT_DEBUGOUT1("em_reset: pba=%dK",pba);
2470
2471         /*
2472          * These parameters control the automatic generation (Tx) and
2473          * response (Rx) to Ethernet PAUSE frames.
2474          * - High water mark should allow for at least two frames to be
2475          *   received after sending an XOFF.
2476          * - Low water mark works best when it is very near the high water mark.
2477          *   This allows the receiver to restart by sending XON when it has
2478          *   drained a bit. Here we use an arbitrary value of 1500 which will
2479          *   restart after one full frame is pulled from the buffer. There
2480          *   could be several smaller frames in the buffer and if so they will
2481          *   not trigger the XON until their total number reduces the buffer
2482          *   by 1500.
2483          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2484          */
2485         rx_buffer_size = (pba & 0xffff) << 10;
2486         hw->fc.high_water = rx_buffer_size -
2487             roundup2(adapter->hw.mac.max_frame_size, 1024);
2488         hw->fc.low_water = hw->fc.high_water - 1500;
2489
2490         if (adapter->fc) /* locally set flow control value? */
2491                 hw->fc.requested_mode = adapter->fc;
2492         else
2493                 hw->fc.requested_mode = e1000_fc_full;
2494
2495         if (hw->mac.type == e1000_80003es2lan)
2496                 hw->fc.pause_time = 0xFFFF;
2497         else
2498                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
2499
2500         hw->fc.send_xon = TRUE;
2501
2502         /* Device specific overrides/settings */
2503         switch (hw->mac.type) {
2504         case e1000_pchlan:
2505                 /* Workaround: no TX flow ctrl for PCH */
2506                 hw->fc.requested_mode = e1000_fc_rx_pause;
2507                 hw->fc.pause_time = 0xFFFF; /* override */
2508                 if (if_getmtu(ifp) > ETHERMTU) {
2509                         hw->fc.high_water = 0x3500;
2510                         hw->fc.low_water = 0x1500;
2511                 } else {
2512                         hw->fc.high_water = 0x5000;
2513                         hw->fc.low_water = 0x3000;
2514                 }
2515                 hw->fc.refresh_time = 0x1000;
2516                 break;
2517         case e1000_pch2lan:
2518         case e1000_pch_lpt:
2519         case e1000_pch_spt:
2520                 hw->fc.high_water = 0x5C20;
2521                 hw->fc.low_water = 0x5048;
2522                 hw->fc.pause_time = 0x0650;
2523                 hw->fc.refresh_time = 0x0400;
2524                 /* Jumbos need adjusted PBA */
2525                 if (if_getmtu(ifp) > ETHERMTU)
2526                         E1000_WRITE_REG(hw, E1000_PBA, 12);
2527                 else
2528                         E1000_WRITE_REG(hw, E1000_PBA, 26);
2529                 break;
2530         case e1000_82575:
2531         case e1000_82576:
2532                 /* 8-byte granularity */
2533                 hw->fc.low_water = hw->fc.high_water - 8;
2534                 break;
2535         case e1000_82580:
2536         case e1000_i350:
2537         case e1000_i354:
2538         case e1000_i210:
2539         case e1000_i211:
2540         case e1000_vfadapt:
2541         case e1000_vfadapt_i350:
2542                 /* 16-byte granularity */
2543                 hw->fc.low_water = hw->fc.high_water - 16;
2544                 break;
2545         case e1000_ich9lan:
2546         case e1000_ich10lan:
2547                 if (if_getmtu(ifp) > ETHERMTU) {
2548                         hw->fc.high_water = 0x2800;
2549                         hw->fc.low_water = hw->fc.high_water - 8;
2550                         break;
2551                 }
2552                 /* FALLTHROUGH */
2553         default:
2554                 if (hw->mac.type == e1000_80003es2lan)
2555                         hw->fc.pause_time = 0xFFFF;
2556                 break;
2557         }
2558
2559         /* Issue a global reset */
2560         e1000_reset_hw(hw);
2561         if (adapter->hw.mac.type >= igb_mac_min) {
2562                 E1000_WRITE_REG(hw, E1000_WUC, 0);
2563         } else {
2564                 E1000_WRITE_REG(hw, E1000_WUFC, 0);
2565                 em_disable_aspm(adapter);
2566         }
2567         if (adapter->flags & IGB_MEDIA_RESET) {
2568                 e1000_setup_init_funcs(hw, TRUE);
2569                 e1000_get_bus_info(hw);
2570                 adapter->flags &= ~IGB_MEDIA_RESET;
2571         }
2572         /* and a re-init */
2573         if (e1000_init_hw(hw) < 0) {
2574                 device_printf(dev, "Hardware Initialization Failed\n");
2575                 return;
2576         }
2577         if (adapter->hw.mac.type >= igb_mac_min)
2578                 igb_init_dmac(adapter, pba);
2579
2580         E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2581         e1000_get_phy_info(hw);
2582         e1000_check_for_link(hw);
2583 }
2584
2585 #define RSSKEYLEN 10
2586 static void
2587 em_initialize_rss_mapping(struct adapter *adapter)
2588 {
2589         uint8_t  rss_key[4 * RSSKEYLEN];
2590         uint32_t reta = 0;
2591         struct e1000_hw *hw = &adapter->hw;
2592         int i;
2593
2594         /*
2595          * Configure RSS key
2596          */
2597         arc4rand(rss_key, sizeof(rss_key), 0);
2598         for (i = 0; i < RSSKEYLEN; ++i) {
2599                 uint32_t rssrk = 0;
2600
2601                 rssrk = EM_RSSRK_VAL(rss_key, i);
2602                 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2603         }
2604
2605         /*
2606          * Configure RSS redirect table in following fashion:
2607          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2608          */
2609         for (i = 0; i < sizeof(reta); ++i) {
2610                 uint32_t q;
2611
2612                 q = (i % adapter->rx_num_queues) << 7;
2613                 reta |= q << (8 * i);
2614         }
2615
2616         for (i = 0; i < 32; ++i)
2617                 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2618
2619         E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2620                         E1000_MRQC_RSS_FIELD_IPV4_TCP |
2621                         E1000_MRQC_RSS_FIELD_IPV4 |
2622                         E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2623                         E1000_MRQC_RSS_FIELD_IPV6_EX |
2624                         E1000_MRQC_RSS_FIELD_IPV6);
2625
2626 }
2627
2628 static void
2629 igb_initialize_rss_mapping(struct adapter *adapter)
2630 {
2631         struct e1000_hw *hw = &adapter->hw;
2632         int i;
2633         int queue_id;
2634         u32 reta;
2635         u32 rss_key[10], mrqc, shift = 0;
2636
2637         /* XXX? */
2638         if (adapter->hw.mac.type == e1000_82575)
2639                 shift = 6;
2640
2641         /*
2642          * The redirection table controls which destination
2643          * queue each bucket redirects traffic to.
2644          * Each DWORD represents four queues, with the LSB
2645          * being the first queue in the DWORD.
2646          *
2647          * This just allocates buckets to queues using round-robin
2648          * allocation.
2649          *
2650          * NOTE: It Just Happens to line up with the default
2651          * RSS allocation method.
2652          */
2653
2654         /* Warning FM follows */
2655         reta = 0;
2656         for (i = 0; i < 128; i++) {
2657 #ifdef RSS
2658                 queue_id = rss_get_indirection_to_bucket(i);
2659                 /*
2660                  * If we have more queues than buckets, we'll
2661                  * end up mapping buckets to a subset of the
2662                  * queues.
2663                  *
2664                  * If we have more buckets than queues, we'll
2665                  * end up instead assigning multiple buckets
2666                  * to queues.
2667                  *
2668                  * Both are suboptimal, but we need to handle
2669                  * the case so we don't go out of bounds
2670                  * indexing arrays and such.
2671                  */
2672                 queue_id = queue_id % adapter->rx_num_queues;
2673 #else
2674                 queue_id = (i % adapter->rx_num_queues);
2675 #endif
2676                 /* Adjust if required */
2677                 queue_id = queue_id << shift;
2678
2679                 /*
2680                  * The low 8 bits are for hash value (n+0);
2681                  * The next 8 bits are for hash value (n+1), etc.
2682                  */
2683                 reta = reta >> 8;
2684                 reta = reta | ( ((uint32_t) queue_id) << 24);
2685                 if ((i & 3) == 3) {
2686                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2687                         reta = 0;
2688                 }
2689         }
2690
2691         /* Now fill in hash table */
2692
2693         /*
2694          * MRQC: Multiple Receive Queues Command
2695          * Set queuing to RSS control, number depends on the device.
2696          */
2697         mrqc = E1000_MRQC_ENABLE_RSS_8Q;
2698
2699 #ifdef RSS
2700         /* XXX ew typecasting */
2701         rss_getkey((uint8_t *) &rss_key);
2702 #else
2703         arc4rand(&rss_key, sizeof(rss_key), 0);
2704 #endif
2705         for (i = 0; i < 10; i++)
2706                 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]);
2707
2708         /*
2709          * Configure the RSS fields to hash upon.
2710          */
2711         mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2712             E1000_MRQC_RSS_FIELD_IPV4_TCP);
2713         mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2714             E1000_MRQC_RSS_FIELD_IPV6_TCP);
2715         mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2716             E1000_MRQC_RSS_FIELD_IPV6_UDP);
2717         mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2718             E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2719
2720         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2721 }
2722
2723 /*********************************************************************
2724  *
2725  *  Setup networking device structure and register an interface.
2726  *
2727  **********************************************************************/
2728 static int
2729 em_setup_interface(if_ctx_t ctx)
2730 {
2731         struct ifnet *ifp = iflib_get_ifp(ctx);
2732         struct adapter *adapter = iflib_get_softc(ctx);
2733         if_softc_ctx_t scctx = adapter->shared;
2734         uint64_t cap = 0;
2735
2736         INIT_DEBUGOUT("em_setup_interface: begin");
2737
2738         /* TSO parameters */
2739         if_sethwtsomax(ifp, IP_MAXPACKET);
2740         /* Take m_pullup(9)'s in em_xmit() w/ TSO into acount. */
2741         if_sethwtsomaxsegcount(ifp, EM_MAX_SCATTER - 5);
2742         if_sethwtsomaxsegsize(ifp, EM_TSO_SEG_SIZE);
2743
2744         /* Single Queue */
2745         if (adapter->tx_num_queues == 1) {
2746                 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
2747                 if_setsendqready(ifp);
2748         }
2749
2750         cap = IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4;
2751         cap |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU;
2752
2753         /*
2754          * Tell the upper layer(s) we
2755          * support full VLAN capability
2756          */
2757         if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
2758         if_setcapabilitiesbit(ifp, cap, 0);
2759
2760         /*
2761          * Don't turn this on by default, if vlans are
2762          * created on another pseudo device (eg. lagg)
2763          * then vlan events are not passed thru, breaking
2764          * operation, but with HW FILTER off it works. If
2765          * using vlans directly on the em driver you can
2766          * enable this and get full hardware tag filtering.
2767          */
2768         if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWFILTER,0);
2769
2770         /* Enable only WOL MAGIC by default */
2771         if (adapter->wol) {
2772                 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC,
2773                             IFCAP_WOL_MCAST| IFCAP_WOL_UCAST);
2774         } else {
2775                 if_setcapenablebit(ifp, 0, IFCAP_WOL_MAGIC |
2776                              IFCAP_WOL_MCAST| IFCAP_WOL_UCAST);
2777         }
2778
2779         /*
2780          * Specify the media types supported by this adapter and register
2781          * callbacks to update media and link information
2782          */
2783         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
2784             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
2785                 u_char fiber_type = IFM_1000_SX;        /* default type */
2786
2787                 if (adapter->hw.mac.type == e1000_82545)
2788                         fiber_type = IFM_1000_LX;
2789                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
2790                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2791         } else {
2792                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2793                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2794                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2795                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2796                 if (adapter->hw.phy.type != e1000_phy_ife) {
2797                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2798                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2799                 }
2800         }
2801         ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2802         ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO);
2803         return (0);
2804 }
2805
2806 static int
2807 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
2808 {
2809         struct adapter *adapter = iflib_get_softc(ctx);
2810         if_softc_ctx_t scctx = adapter->shared;
2811         int error = E1000_SUCCESS;
2812         struct em_tx_queue *que;
2813         int i, j;
2814
2815         MPASS(adapter->tx_num_queues > 0);
2816         MPASS(adapter->tx_num_queues == ntxqsets);
2817
2818         /* First allocate the top level queue structs */
2819         if (!(adapter->tx_queues =
2820             (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
2821             adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2822                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2823                 return(ENOMEM);
2824         }
2825
2826         for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) {
2827                 /* Set up some basics */
2828
2829                 struct tx_ring *txr = &que->txr;
2830                 txr->adapter = que->adapter = adapter;
2831                 que->me = txr->me =  i;
2832
2833                 /* Allocate report status array */
2834                 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2835                         device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n");
2836                         error = ENOMEM;
2837                         goto fail;
2838                 }
2839                 for (j = 0; j < scctx->isc_ntxd[0]; j++)
2840                         txr->tx_rsq[j] = QIDX_INVALID;
2841                 /* get the virtual and physical address of the hardware queues */
2842                 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
2843                 txr->tx_paddr = paddrs[i*ntxqs];
2844         }
2845
2846         device_printf(iflib_get_dev(ctx), "allocated for %d tx_queues\n", adapter->tx_num_queues);
2847         return (0);
2848 fail:
2849         em_if_queues_free(ctx);
2850         return (error);
2851 }
2852
2853 static int
2854 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
2855 {
2856         struct adapter *adapter = iflib_get_softc(ctx);
2857         int error = E1000_SUCCESS;
2858         struct em_rx_queue *que;
2859         int i;
2860
2861         MPASS(adapter->rx_num_queues > 0);
2862         MPASS(adapter->rx_num_queues == nrxqsets);
2863
2864         /* First allocate the top level queue structs */
2865         if (!(adapter->rx_queues =
2866             (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
2867             adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2868                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2869                 error = ENOMEM;
2870                 goto fail;
2871         }
2872
2873         for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) {
2874                 /* Set up some basics */
2875                 struct rx_ring *rxr = &que->rxr;
2876                 rxr->adapter = que->adapter = adapter;
2877                 rxr->que = que;
2878                 que->me = rxr->me =  i;
2879
2880                 /* get the virtual and physical address of the hardware queues */
2881                 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
2882                 rxr->rx_paddr = paddrs[i*nrxqs];
2883         }
2884
2885         device_printf(iflib_get_dev(ctx), "allocated for %d rx_queues\n", adapter->rx_num_queues);
2886
2887         return (0);
2888 fail:
2889         em_if_queues_free(ctx);
2890         return (error);
2891 }
2892
2893 static void
2894 em_if_queues_free(if_ctx_t ctx)
2895 {
2896         struct adapter *adapter = iflib_get_softc(ctx);
2897         struct em_tx_queue *tx_que = adapter->tx_queues;
2898         struct em_rx_queue *rx_que = adapter->rx_queues;
2899
2900         if (tx_que != NULL) {
2901                 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
2902                         struct tx_ring *txr = &tx_que->txr;
2903                         if (txr->tx_rsq == NULL)
2904                                 break;
2905
2906                         free(txr->tx_rsq, M_DEVBUF);
2907                         txr->tx_rsq = NULL;
2908                 }
2909                 free(adapter->tx_queues, M_DEVBUF);
2910                 adapter->tx_queues = NULL;
2911         }
2912
2913         if (rx_que != NULL) {
2914                 free(adapter->rx_queues, M_DEVBUF);
2915                 adapter->rx_queues = NULL;
2916         }
2917
2918         em_release_hw_control(adapter);
2919
2920         if (adapter->mta != NULL) {
2921                 free(adapter->mta, M_DEVBUF);
2922         }
2923 }
2924
2925 /*********************************************************************
2926  *
2927  *  Enable transmit unit.
2928  *
2929  **********************************************************************/
2930 static void
2931 em_initialize_transmit_unit(if_ctx_t ctx)
2932 {
2933         struct adapter *adapter = iflib_get_softc(ctx);
2934         if_softc_ctx_t scctx = adapter->shared;
2935         struct em_tx_queue *que;
2936         struct tx_ring  *txr;
2937         struct e1000_hw *hw = &adapter->hw;
2938         u32 tctl, txdctl = 0, tarc, tipg = 0;
2939
2940         INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
2941
2942         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
2943                 u64 bus_addr;
2944                 caddr_t offp, endp;
2945
2946                 que = &adapter->tx_queues[i];
2947                 txr = &que->txr;
2948                 bus_addr = txr->tx_paddr;
2949
2950                 /* Clear checksum offload context. */
2951                 offp = (caddr_t)&txr->csum_flags;
2952                 endp = (caddr_t)(txr + 1);
2953                 bzero(offp, endp - offp);
2954
2955                 /* Base and Len of TX Ring */
2956                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
2957                     scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
2958                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
2959                     (u32)(bus_addr >> 32));
2960                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
2961                     (u32)bus_addr);
2962                 /* Init the HEAD/TAIL indices */
2963                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
2964                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
2965
2966                 HW_DEBUGOUT2("Base = %x, Length = %x\n",
2967                     E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)),
2968                     E1000_READ_REG(&adapter->hw, E1000_TDLEN(i)));
2969
2970                 txdctl = 0; /* clear txdctl */
2971                 txdctl |= 0x1f; /* PTHRESH */
2972                 txdctl |= 1 << 8; /* HTHRESH */
2973                 txdctl |= 1 << 16;/* WTHRESH */
2974                 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
2975                 txdctl |= E1000_TXDCTL_GRAN;
2976                 txdctl |= 1 << 25; /* LWTHRESH */
2977
2978                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
2979         }
2980
2981         /* Set the default values for the Tx Inter Packet Gap timer */
2982         switch (adapter->hw.mac.type) {
2983         case e1000_80003es2lan:
2984                 tipg = DEFAULT_82543_TIPG_IPGR1;
2985                 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2986                     E1000_TIPG_IPGR2_SHIFT;
2987                 break;
2988         case e1000_82542:
2989                 tipg = DEFAULT_82542_TIPG_IPGT;
2990                 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2991                 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2992                 break;
2993         default:
2994                 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
2995                     (adapter->hw.phy.media_type ==
2996                     e1000_media_type_internal_serdes))
2997                         tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2998                 else
2999                         tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
3000                 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3001                 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3002         }
3003
3004         E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
3005         E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value);
3006
3007         if(adapter->hw.mac.type >= e1000_82540)
3008                 E1000_WRITE_REG(&adapter->hw, E1000_TADV,
3009                     adapter->tx_abs_int_delay.value);
3010
3011         if ((adapter->hw.mac.type == e1000_82571) ||
3012             (adapter->hw.mac.type == e1000_82572)) {
3013                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3014                 tarc |= TARC_SPEED_MODE_BIT;
3015                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3016         } else if (adapter->hw.mac.type == e1000_80003es2lan) {
3017                 /* errata: program both queues to unweighted RR */
3018                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3019                 tarc |= 1;
3020                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3021                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
3022                 tarc |= 1;
3023                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
3024         } else if (adapter->hw.mac.type == e1000_82574) {
3025                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3026                 tarc |= TARC_ERRATA_BIT;
3027                 if ( adapter->tx_num_queues > 1) {
3028                         tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
3029                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3030                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
3031                 } else
3032                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3033         }
3034
3035         if (adapter->tx_int_delay.value > 0)
3036                 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3037
3038         /* Program the Transmit Control Register */
3039         tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
3040         tctl &= ~E1000_TCTL_CT;
3041         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
3042                    (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
3043
3044         if (adapter->hw.mac.type >= e1000_82571)
3045                 tctl |= E1000_TCTL_MULR;
3046
3047         /* This write will effectively turn on the transmit unit. */
3048         E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
3049
3050         if (hw->mac.type == e1000_pch_spt) {
3051                 u32 reg;
3052                 reg = E1000_READ_REG(hw, E1000_IOSFPC);
3053                 reg |= E1000_RCTL_RDMTS_HEX;
3054                 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
3055                 reg = E1000_READ_REG(hw, E1000_TARC(0));
3056                 reg |= E1000_TARC0_CB_MULTIQ_3_REQ;
3057                 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3058         }
3059 }
3060
3061 /*********************************************************************
3062  *
3063  *  Enable receive unit.
3064  *
3065  **********************************************************************/
3066
3067 static void
3068 em_initialize_receive_unit(if_ctx_t ctx)
3069 {
3070         struct adapter *adapter = iflib_get_softc(ctx);
3071         if_softc_ctx_t scctx = adapter->shared;
3072         struct ifnet *ifp = iflib_get_ifp(ctx);
3073         struct e1000_hw *hw = &adapter->hw;
3074         struct em_rx_queue *que;
3075         int i;
3076         u32 rctl, rxcsum, rfctl;
3077
3078         INIT_DEBUGOUT("em_initialize_receive_units: begin");
3079
3080         /*
3081          * Make sure receives are disabled while setting
3082          * up the descriptor ring
3083          */
3084         rctl = E1000_READ_REG(hw, E1000_RCTL);
3085         /* Do not disable if ever enabled on this hardware */
3086         if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
3087                 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3088
3089         /* Setup the Receive Control Register */
3090         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3091         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3092             E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3093             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3094
3095         /* Do not store bad packets */
3096         rctl &= ~E1000_RCTL_SBP;
3097
3098         /* Enable Long Packet receive */
3099         if (if_getmtu(ifp) > ETHERMTU)
3100                 rctl |= E1000_RCTL_LPE;
3101         else
3102                 rctl &= ~E1000_RCTL_LPE;
3103
3104         /* Strip the CRC */
3105         if (!em_disable_crc_stripping)
3106                 rctl |= E1000_RCTL_SECRC;
3107
3108         if (adapter->hw.mac.type >= e1000_82540) {
3109                 E1000_WRITE_REG(&adapter->hw, E1000_RADV,
3110                             adapter->rx_abs_int_delay.value);
3111
3112                 /*
3113                  * Set the interrupt throttling rate. Value is calculated
3114                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
3115                  */
3116                 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
3117         }
3118         E1000_WRITE_REG(&adapter->hw, E1000_RDTR,
3119             adapter->rx_int_delay.value);
3120
3121         /* Use extended rx descriptor formats */
3122         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3123         rfctl |= E1000_RFCTL_EXTEN;
3124         /*
3125          * When using MSIX interrupts we need to throttle
3126          * using the EITR register (82574 only)
3127          */
3128         if (hw->mac.type == e1000_82574) {
3129                 for (int i = 0; i < 4; i++)
3130                         E1000_WRITE_REG(hw, E1000_EITR_82574(i),
3131                             DEFAULT_ITR);
3132                 /* Disable accelerated acknowledge */
3133                 rfctl |= E1000_RFCTL_ACK_DIS;
3134         }
3135         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3136
3137         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
3138         if (if_getcapenable(ifp) & IFCAP_RXCSUM &&
3139             adapter->hw.mac.type >= e1000_82543) {
3140                 if (adapter->tx_num_queues > 1) {
3141                         if (adapter->hw.mac.type >= igb_mac_min) {
3142                                 rxcsum |= E1000_RXCSUM_PCSD;
3143                                 if (hw->mac.type != e1000_82575)
3144                                         rxcsum |= E1000_RXCSUM_CRCOFL;
3145                         } else
3146                                 rxcsum |= E1000_RXCSUM_TUOFL |
3147                                         E1000_RXCSUM_IPOFL |
3148                                         E1000_RXCSUM_PCSD;
3149                 } else {
3150                         if (adapter->hw.mac.type >= igb_mac_min)
3151                                 rxcsum |= E1000_RXCSUM_IPPCSE;
3152                         else
3153                                 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
3154                         if (adapter->hw.mac.type > e1000_82575)
3155                                 rxcsum |= E1000_RXCSUM_CRCOFL;
3156                 }
3157         } else
3158                 rxcsum &= ~E1000_RXCSUM_TUOFL;
3159
3160         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
3161
3162         if (adapter->rx_num_queues > 1) {
3163                 if (adapter->hw.mac.type >= igb_mac_min)
3164                         igb_initialize_rss_mapping(adapter);
3165                 else
3166                         em_initialize_rss_mapping(adapter);
3167         }
3168
3169         /*
3170          * XXX TEMPORARY WORKAROUND: on some systems with 82573
3171          * long latencies are observed, like Lenovo X60. This
3172          * change eliminates the problem, but since having positive
3173          * values in RDTR is a known source of problems on other
3174          * platforms another solution is being sought.
3175          */
3176         if (hw->mac.type == e1000_82573)
3177                 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
3178
3179         for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3180                 struct rx_ring *rxr = &que->rxr;
3181                 /* Setup the Base and Length of the Rx Descriptor Ring */
3182                 u64 bus_addr = rxr->rx_paddr;
3183 #if 0
3184                 u32 rdt = adapter->rx_num_queues -1;  /* default */
3185 #endif
3186
3187                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3188                     scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
3189                 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
3190                 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
3191                 /* Setup the Head and Tail Descriptor Pointers */
3192                 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
3193                 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
3194         }
3195
3196         /*
3197          * Set PTHRESH for improved jumbo performance
3198          * According to 10.2.5.11 of Intel 82574 Datasheet,
3199          * RXDCTL(1) is written whenever RXDCTL(0) is written.
3200          * Only write to RXDCTL(1) if there is a need for different
3201          * settings.
3202          */
3203
3204         if (((adapter->hw.mac.type == e1000_ich9lan) ||
3205             (adapter->hw.mac.type == e1000_pch2lan) ||
3206             (adapter->hw.mac.type == e1000_ich10lan)) &&
3207             (if_getmtu(ifp) > ETHERMTU)) {
3208                 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
3209                 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
3210         } else if (adapter->hw.mac.type == e1000_82574) {
3211                 for (int i = 0; i < adapter->rx_num_queues; i++) {
3212                         u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3213                         rxdctl |= 0x20; /* PTHRESH */
3214                         rxdctl |= 4 << 8; /* HTHRESH */
3215                         rxdctl |= 4 << 16;/* WTHRESH */
3216                         rxdctl |= 1 << 24; /* Switch to granularity */
3217                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3218                 }
3219         } else if (adapter->hw.mac.type >= igb_mac_min) {
3220                 u32 psize, srrctl = 0;
3221
3222                 if (if_getmtu(ifp) > ETHERMTU) {
3223                         /* Set maximum packet len */
3224                         if (adapter->rx_mbuf_sz <= 4096) {
3225                                 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3226                                 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3227                         } else if (adapter->rx_mbuf_sz > 4096) {
3228                                 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3229                                 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3230                         }
3231                         psize = scctx->isc_max_frame_size;
3232                         /* are we on a vlan? */
3233                         if (ifp->if_vlantrunk != NULL)
3234                                 psize += VLAN_TAG_SIZE;
3235                         E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
3236                 } else {
3237                         srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3238                         rctl |= E1000_RCTL_SZ_2048;
3239                 }
3240
3241                 /*
3242                  * If TX flow control is disabled and there's >1 queue defined,
3243                  * enable DROP.
3244                  *
3245                  * This drops frames rather than hanging the RX MAC for all queues.
3246                  */
3247                 if ((adapter->rx_num_queues > 1) &&
3248                     (adapter->fc == e1000_fc_none ||
3249                      adapter->fc == e1000_fc_rx_pause)) {
3250                         srrctl |= E1000_SRRCTL_DROP_EN;
3251                 }
3252                         /* Setup the Base and Length of the Rx Descriptor Rings */
3253                 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3254                         struct rx_ring *rxr = &que->rxr;
3255                         u64 bus_addr = rxr->rx_paddr;
3256                         u32 rxdctl;
3257
3258 #ifdef notyet
3259                         /* Configure for header split? -- ignore for now */
3260                         rxr->hdr_split = igb_header_split;
3261 #else
3262                         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3263 #endif
3264
3265                         E1000_WRITE_REG(hw, E1000_RDLEN(i),
3266                                         scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3267                         E1000_WRITE_REG(hw, E1000_RDBAH(i),
3268                                         (uint32_t)(bus_addr >> 32));
3269                         E1000_WRITE_REG(hw, E1000_RDBAL(i),
3270                                         (uint32_t)bus_addr);
3271                         E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3272                         /* Enable this Queue */
3273                         rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3274                         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3275                         rxdctl &= 0xFFF00000;
3276                         rxdctl |= IGB_RX_PTHRESH;
3277                         rxdctl |= IGB_RX_HTHRESH << 8;
3278                         rxdctl |= IGB_RX_WTHRESH << 16;
3279                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3280                 }
3281         } else if (adapter->hw.mac.type >= e1000_pch2lan) {
3282                 if (if_getmtu(ifp) > ETHERMTU)
3283                         e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
3284                 else
3285                         e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
3286         }
3287
3288         /* Make sure VLAN Filters are off */
3289         rctl &= ~E1000_RCTL_VFE;
3290
3291         if (adapter->hw.mac.type < igb_mac_min) {
3292                 if (adapter->rx_mbuf_sz == MCLBYTES)
3293                         rctl |= E1000_RCTL_SZ_2048;
3294                 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE)
3295                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3296                 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE)
3297                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3298
3299                 /* ensure we clear use DTYPE of 00 here */
3300                 rctl &= ~0x00000C00;
3301         }
3302
3303         /* Write out the settings */
3304         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3305
3306         return;
3307 }
3308
3309 static void
3310 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3311 {
3312         struct adapter *adapter = iflib_get_softc(ctx);
3313         u32 index, bit;
3314
3315         index = (vtag >> 5) & 0x7F;
3316         bit = vtag & 0x1F;
3317         adapter->shadow_vfta[index] |= (1 << bit);
3318         ++adapter->num_vlans;
3319 }
3320
3321 static void
3322 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3323 {
3324         struct adapter *adapter = iflib_get_softc(ctx);
3325         u32 index, bit;
3326
3327         index = (vtag >> 5) & 0x7F;
3328         bit = vtag & 0x1F;
3329         adapter->shadow_vfta[index] &= ~(1 << bit);
3330         --adapter->num_vlans;
3331 }
3332
3333 static void
3334 em_setup_vlan_hw_support(struct adapter *adapter)
3335 {
3336         struct e1000_hw *hw = &adapter->hw;
3337         u32 reg;
3338
3339         /*
3340          * We get here thru init_locked, meaning
3341          * a soft reset, this has already cleared
3342          * the VFTA and other state, so if there
3343          * have been no vlan's registered do nothing.
3344          */
3345         if (adapter->num_vlans == 0)
3346                 return;
3347
3348         /*
3349          * A soft reset zero's out the VFTA, so
3350          * we need to repopulate it now.
3351          */
3352         for (int i = 0; i < EM_VFTA_SIZE; i++)
3353                 if (adapter->shadow_vfta[i] != 0)
3354                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
3355                             i, adapter->shadow_vfta[i]);
3356
3357         reg = E1000_READ_REG(hw, E1000_CTRL);
3358         reg |= E1000_CTRL_VME;
3359         E1000_WRITE_REG(hw, E1000_CTRL, reg);
3360
3361         /* Enable the Filter Table */
3362         reg = E1000_READ_REG(hw, E1000_RCTL);
3363         reg &= ~E1000_RCTL_CFIEN;
3364         reg |= E1000_RCTL_VFE;
3365         E1000_WRITE_REG(hw, E1000_RCTL, reg);
3366 }
3367
3368 static void
3369 em_if_enable_intr(if_ctx_t ctx)
3370 {
3371         struct adapter *adapter = iflib_get_softc(ctx);
3372         struct e1000_hw *hw = &adapter->hw;
3373         u32 ims_mask = IMS_ENABLE_MASK;
3374
3375         if (hw->mac.type == e1000_82574) {
3376                 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK);
3377                 ims_mask |= adapter->ims;
3378         } else if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min)  {
3379                 u32 mask = (adapter->que_mask | adapter->link_mask);
3380
3381                 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask);
3382                 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask);
3383                 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask);
3384                 ims_mask = E1000_IMS_LSC;
3385         }
3386
3387         E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3388 }
3389
3390 static void
3391 em_if_disable_intr(if_ctx_t ctx)
3392 {
3393         struct adapter *adapter = iflib_get_softc(ctx);
3394         struct e1000_hw *hw = &adapter->hw;
3395
3396         if (adapter->intr_type == IFLIB_INTR_MSIX) {
3397                 if (hw->mac.type >= igb_mac_min)
3398                         E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0);
3399                 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0);
3400         }
3401         E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
3402 }
3403
3404 /*
3405  * Bit of a misnomer, what this really means is
3406  * to enable OS management of the system... aka
3407  * to disable special hardware management features
3408  */
3409 static void
3410 em_init_manageability(struct adapter *adapter)
3411 {
3412         /* A shared code workaround */
3413 #define E1000_82542_MANC2H E1000_MANC2H
3414         if (adapter->has_manage) {
3415                 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3416                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3417
3418                 /* disable hardware interception of ARP */
3419                 manc &= ~(E1000_MANC_ARP_EN);
3420
3421                 /* enable receiving management packets to the host */
3422                 manc |= E1000_MANC_EN_MNG2HOST;
3423 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3424 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3425                 manc2h |= E1000_MNG2HOST_PORT_623;
3426                 manc2h |= E1000_MNG2HOST_PORT_664;
3427                 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3428                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3429         }
3430 }
3431
3432 /*
3433  * Give control back to hardware management
3434  * controller if there is one.
3435  */
3436 static void
3437 em_release_manageability(struct adapter *adapter)
3438 {
3439         if (adapter->has_manage) {
3440                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3441
3442                 /* re-enable hardware interception of ARP */
3443                 manc |= E1000_MANC_ARP_EN;
3444                 manc &= ~E1000_MANC_EN_MNG2HOST;
3445
3446                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3447         }
3448 }
3449
3450 /*
3451  * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3452  * For ASF and Pass Through versions of f/w this means
3453  * that the driver is loaded. For AMT version type f/w
3454  * this means that the network i/f is open.
3455  */
3456 static void
3457 em_get_hw_control(struct adapter *adapter)
3458 {
3459         u32 ctrl_ext, swsm;
3460
3461         if (adapter->vf_ifp)
3462                 return;
3463
3464         if (adapter->hw.mac.type == e1000_82573) {
3465                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3466                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3467                     swsm | E1000_SWSM_DRV_LOAD);
3468                 return;
3469         }
3470         /* else */
3471         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3472         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3473             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3474 }
3475
3476 /*
3477  * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3478  * For ASF and Pass Through versions of f/w this means that
3479  * the driver is no longer loaded. For AMT versions of the
3480  * f/w this means that the network i/f is closed.
3481  */
3482 static void
3483 em_release_hw_control(struct adapter *adapter)
3484 {
3485         u32 ctrl_ext, swsm;
3486
3487         if (!adapter->has_manage)
3488                 return;
3489
3490         if (adapter->hw.mac.type == e1000_82573) {
3491                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3492                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3493                     swsm & ~E1000_SWSM_DRV_LOAD);
3494                 return;
3495         }
3496         /* else */
3497         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3498         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3499             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3500         return;
3501 }
3502
3503 static int
3504 em_is_valid_ether_addr(u8 *addr)
3505 {
3506         char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3507
3508         if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3509                 return (FALSE);
3510         }
3511
3512         return (TRUE);
3513 }
3514
3515 /*
3516 ** Parse the interface capabilities with regard
3517 ** to both system management and wake-on-lan for
3518 ** later use.
3519 */
3520 static void
3521 em_get_wakeup(if_ctx_t ctx)
3522 {
3523         struct adapter *adapter = iflib_get_softc(ctx);
3524         device_t dev = iflib_get_dev(ctx);
3525         u16 eeprom_data = 0, device_id, apme_mask;
3526
3527         adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
3528         apme_mask = EM_EEPROM_APME;
3529
3530         switch (adapter->hw.mac.type) {
3531         case e1000_82542:
3532         case e1000_82543:
3533                 break;
3534         case e1000_82544:
3535                 e1000_read_nvm(&adapter->hw,
3536                     NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3537                 apme_mask = EM_82544_APME;
3538                 break;
3539         case e1000_82546:
3540         case e1000_82546_rev_3:
3541                 if (adapter->hw.bus.func == 1) {
3542                         e1000_read_nvm(&adapter->hw,
3543                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3544                         break;
3545                 } else
3546                         e1000_read_nvm(&adapter->hw,
3547                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3548                 break;
3549         case e1000_82573:
3550         case e1000_82583:
3551                 adapter->has_amt = TRUE;
3552                 /* FALLTHROUGH */
3553         case e1000_82571:
3554         case e1000_82572:
3555         case e1000_80003es2lan:
3556                 if (adapter->hw.bus.func == 1) {
3557                         e1000_read_nvm(&adapter->hw,
3558                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3559                         break;
3560                 } else
3561                         e1000_read_nvm(&adapter->hw,
3562                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3563                 break;
3564         case e1000_ich8lan:
3565         case e1000_ich9lan:
3566         case e1000_ich10lan:
3567         case e1000_pchlan:
3568         case e1000_pch2lan:
3569         case e1000_pch_lpt:
3570         case e1000_pch_spt:
3571         case e1000_82575:       /* listing all igb devices */
3572         case e1000_82576:
3573         case e1000_82580:
3574         case e1000_i350:
3575         case e1000_i354:
3576         case e1000_i210:
3577         case e1000_i211:
3578         case e1000_vfadapt:
3579         case e1000_vfadapt_i350:
3580                 apme_mask = E1000_WUC_APME;
3581                 adapter->has_amt = TRUE;
3582                 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
3583                 break;
3584         default:
3585                 e1000_read_nvm(&adapter->hw,
3586                     NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3587                 break;
3588         }
3589         if (eeprom_data & apme_mask)
3590                 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
3591         /*
3592          * We have the eeprom settings, now apply the special cases
3593          * where the eeprom may be wrong or the board won't support
3594          * wake on lan on a particular port
3595          */
3596         device_id = pci_get_device(dev);
3597         switch (device_id) {
3598         case E1000_DEV_ID_82546GB_PCIE:
3599                 adapter->wol = 0;
3600                 break;
3601         case E1000_DEV_ID_82546EB_FIBER:
3602         case E1000_DEV_ID_82546GB_FIBER:
3603                 /* Wake events only supported on port A for dual fiber
3604                  * regardless of eeprom setting */
3605                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3606                     E1000_STATUS_FUNC_1)
3607                         adapter->wol = 0;
3608                 break;
3609         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
3610                 /* if quad port adapter, disable WoL on all but port A */
3611                 if (global_quad_port_a != 0)
3612                         adapter->wol = 0;
3613                 /* Reset for multiple quad port adapters */
3614                 if (++global_quad_port_a == 4)
3615                         global_quad_port_a = 0;
3616                 break;
3617         case E1000_DEV_ID_82571EB_FIBER:
3618                 /* Wake events only supported on port A for dual fiber
3619                  * regardless of eeprom setting */
3620                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3621                     E1000_STATUS_FUNC_1)
3622                         adapter->wol = 0;
3623                 break;
3624         case E1000_DEV_ID_82571EB_QUAD_COPPER:
3625         case E1000_DEV_ID_82571EB_QUAD_FIBER:
3626         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
3627                 /* if quad port adapter, disable WoL on all but port A */
3628                 if (global_quad_port_a != 0)
3629                         adapter->wol = 0;
3630                 /* Reset for multiple quad port adapters */
3631                 if (++global_quad_port_a == 4)
3632                         global_quad_port_a = 0;
3633                 break;
3634         }
3635         return;
3636 }
3637
3638
3639 /*
3640  * Enable PCI Wake On Lan capability
3641  */
3642 static void
3643 em_enable_wakeup(if_ctx_t ctx)
3644 {
3645         struct adapter *adapter = iflib_get_softc(ctx);
3646         device_t dev = iflib_get_dev(ctx);
3647         if_t ifp = iflib_get_ifp(ctx);
3648         int error = 0;
3649         u32 pmc, ctrl, ctrl_ext, rctl;
3650         u16 status;
3651
3652         if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
3653                 return;
3654
3655         /*
3656          * Determine type of Wakeup: note that wol
3657          * is set with all bits on by default.
3658          */
3659         if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
3660                 adapter->wol &= ~E1000_WUFC_MAG;
3661
3662         if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
3663                 adapter->wol &= ~E1000_WUFC_EX;
3664
3665         if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
3666                 adapter->wol &= ~E1000_WUFC_MC;
3667         else {
3668                 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3669                 rctl |= E1000_RCTL_MPE;
3670                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3671         }
3672
3673         if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC)))
3674                 goto pme;
3675
3676         /* Advertise the wakeup capability */
3677         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
3678         ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
3679         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
3680
3681         /* Keep the laser running on Fiber adapters */
3682         if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3683             adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
3684                 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3685                 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
3686                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext);
3687         }
3688
3689         if ((adapter->hw.mac.type == e1000_ich8lan) ||
3690             (adapter->hw.mac.type == e1000_pchlan) ||
3691             (adapter->hw.mac.type == e1000_ich9lan) ||
3692             (adapter->hw.mac.type == e1000_ich10lan))
3693                 e1000_suspend_workarounds_ich8lan(&adapter->hw);
3694
3695         if ( adapter->hw.mac.type >= e1000_pchlan) {
3696                 error = em_enable_phy_wakeup(adapter);
3697                 if (error)
3698                         goto pme;
3699         } else {
3700                 /* Enable wakeup by the MAC */
3701                 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
3702                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
3703         }
3704
3705         if (adapter->hw.phy.type == e1000_phy_igp_3)
3706                 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
3707
3708 pme:
3709         status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
3710         status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3711         if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
3712                 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3713         pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
3714
3715         return;
3716 }
3717
3718 /*
3719  * WOL in the newer chipset interfaces (pchlan)
3720  * require thing to be copied into the phy
3721  */
3722 static int
3723 em_enable_phy_wakeup(struct adapter *adapter)
3724 {
3725         struct e1000_hw *hw = &adapter->hw;
3726         u32 mreg, ret = 0;
3727         u16 preg;
3728
3729         /* copy MAC RARs to PHY RARs */
3730         e1000_copy_rx_addrs_to_phy_ich8lan(hw);
3731
3732         /* copy MAC MTA to PHY MTA */
3733         for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
3734                 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
3735                 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
3736                 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
3737                     (u16)((mreg >> 16) & 0xFFFF));
3738         }
3739
3740         /* configure PHY Rx Control register */
3741         e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg);
3742         mreg = E1000_READ_REG(hw, E1000_RCTL);
3743         if (mreg & E1000_RCTL_UPE)
3744                 preg |= BM_RCTL_UPE;
3745         if (mreg & E1000_RCTL_MPE)
3746                 preg |= BM_RCTL_MPE;
3747         preg &= ~(BM_RCTL_MO_MASK);
3748         if (mreg & E1000_RCTL_MO_3)
3749                 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
3750                                 << BM_RCTL_MO_SHIFT);
3751         if (mreg & E1000_RCTL_BAM)
3752                 preg |= BM_RCTL_BAM;
3753         if (mreg & E1000_RCTL_PMCF)
3754                 preg |= BM_RCTL_PMCF;
3755         mreg = E1000_READ_REG(hw, E1000_CTRL);
3756         if (mreg & E1000_CTRL_RFCE)
3757                 preg |= BM_RCTL_RFCE;
3758         e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg);
3759
3760         /* enable PHY wakeup in MAC register */
3761         E1000_WRITE_REG(hw, E1000_WUC,
3762             E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
3763         E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol);
3764
3765         /* configure and enable PHY wakeup in PHY registers */
3766         e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol);
3767         e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
3768
3769         /* activate PHY wakeup */
3770         ret = hw->phy.ops.acquire(hw);
3771         if (ret) {
3772                 printf("Could not acquire PHY\n");
3773                 return ret;
3774         }
3775         e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3776                                  (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3777         ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
3778         if (ret) {
3779                 printf("Could not read PHY page 769\n");
3780                 goto out;
3781         }
3782         preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
3783         ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
3784         if (ret)
3785                 printf("Could not set PHY Host Wakeup bit\n");
3786 out:
3787         hw->phy.ops.release(hw);
3788
3789         return ret;
3790 }
3791
3792 static void
3793 em_if_led_func(if_ctx_t ctx, int onoff)
3794 {
3795         struct adapter *adapter = iflib_get_softc(ctx);
3796
3797         if (onoff) {
3798                 e1000_setup_led(&adapter->hw);
3799                 e1000_led_on(&adapter->hw);
3800         } else {
3801                 e1000_led_off(&adapter->hw);
3802                 e1000_cleanup_led(&adapter->hw);
3803         }
3804 }
3805
3806 /*
3807  * Disable the L0S and L1 LINK states
3808  */
3809 static void
3810 em_disable_aspm(struct adapter *adapter)
3811 {
3812         int base, reg;
3813         u16 link_cap,link_ctrl;
3814         device_t dev = adapter->dev;
3815
3816         switch (adapter->hw.mac.type) {
3817         case e1000_82573:
3818         case e1000_82574:
3819         case e1000_82583:
3820                 break;
3821         default:
3822                 return;
3823         }
3824         if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
3825                 return;
3826         reg = base + PCIER_LINK_CAP;
3827         link_cap = pci_read_config(dev, reg, 2);
3828         if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
3829                 return;
3830         reg = base + PCIER_LINK_CTL;
3831         link_ctrl = pci_read_config(dev, reg, 2);
3832         link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
3833         pci_write_config(dev, reg, link_ctrl, 2);
3834         return;
3835 }
3836
3837 /**********************************************************************
3838  *
3839  *  Update the board statistics counters.
3840  *
3841  **********************************************************************/
3842 static void
3843 em_update_stats_counters(struct adapter *adapter)
3844 {
3845
3846         if(adapter->hw.phy.media_type == e1000_media_type_copper ||
3847            (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3848                 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
3849                 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
3850         }
3851         adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
3852         adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
3853         adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
3854         adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
3855
3856         adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
3857         adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
3858         adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
3859         adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
3860         adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
3861         adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
3862         adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
3863         adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
3864         /*
3865          ** For watchdog management we need to know if we have been
3866          ** paused during the last interval, so capture that here.
3867         */
3868         adapter->shared->isc_pause_frames = adapter->stats.xoffrxc;
3869         adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
3870         adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
3871         adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
3872         adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
3873         adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
3874         adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
3875         adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
3876         adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
3877         adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
3878         adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
3879         adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
3880         adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
3881
3882         /* For the 64-bit byte counters the low dword must be read first. */
3883         /* Both registers clear on the read of the high dword */
3884
3885         adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) +
3886             ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32);
3887         adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) +
3888             ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32);
3889
3890         adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
3891         adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
3892         adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
3893         adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
3894         adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
3895
3896         adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
3897         adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
3898
3899         adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
3900         adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
3901         adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
3902         adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
3903         adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
3904         adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
3905         adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
3906         adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
3907         adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
3908         adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
3909
3910         /* Interrupt Counts */
3911
3912         adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC);
3913         adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC);
3914         adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC);
3915         adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC);
3916         adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC);
3917         adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC);
3918         adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC);
3919         adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC);
3920         adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC);
3921
3922         if (adapter->hw.mac.type >= e1000_82543) {
3923                 adapter->stats.algnerrc +=
3924                 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
3925                 adapter->stats.rxerrc +=
3926                 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
3927                 adapter->stats.tncrs +=
3928                 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
3929                 adapter->stats.cexterr +=
3930                 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
3931                 adapter->stats.tsctc +=
3932                 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
3933                 adapter->stats.tsctfc +=
3934                 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
3935         }
3936 }
3937
3938 static uint64_t
3939 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
3940 {
3941         struct adapter *adapter = iflib_get_softc(ctx);
3942         struct ifnet *ifp = iflib_get_ifp(ctx);
3943
3944         switch (cnt) {
3945         case IFCOUNTER_COLLISIONS:
3946                 return (adapter->stats.colc);
3947         case IFCOUNTER_IERRORS:
3948                 return (adapter->dropped_pkts + adapter->stats.rxerrc +
3949                     adapter->stats.crcerrs + adapter->stats.algnerrc +
3950                     adapter->stats.ruc + adapter->stats.roc +
3951                     adapter->stats.mpc + adapter->stats.cexterr);
3952         case IFCOUNTER_OERRORS:
3953                 return (adapter->stats.ecol + adapter->stats.latecol +
3954                     adapter->watchdog_events);
3955         default:
3956                 return (if_get_counter_default(ifp, cnt));
3957         }
3958 }
3959
3960 /* Export a single 32-bit register via a read-only sysctl. */
3961 static int
3962 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
3963 {
3964         struct adapter *adapter;
3965         u_int val;
3966
3967         adapter = oidp->oid_arg1;
3968         val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2);
3969         return (sysctl_handle_int(oidp, &val, 0, req));
3970 }
3971
3972 /*
3973  * Add sysctl variables, one per statistic, to the system.
3974  */
3975 static void
3976 em_add_hw_stats(struct adapter *adapter)
3977 {
3978         device_t dev = iflib_get_dev(adapter->ctx);
3979         struct em_tx_queue *tx_que = adapter->tx_queues;
3980         struct em_rx_queue *rx_que = adapter->rx_queues;
3981
3982         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
3983         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
3984         struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
3985         struct e1000_hw_stats *stats = &adapter->stats;
3986
3987         struct sysctl_oid *stat_node, *queue_node, *int_node;
3988         struct sysctl_oid_list *stat_list, *queue_list, *int_list;
3989
3990 #define QUEUE_NAME_LEN 32
3991         char namebuf[QUEUE_NAME_LEN];
3992
3993         /* Driver Statistics */
3994         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
3995                         CTLFLAG_RD, &adapter->dropped_pkts,
3996                         "Driver dropped packets");
3997         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
3998                         CTLFLAG_RD, &adapter->link_irq,
3999                         "Link MSIX IRQ Handled");
4000         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "mbuf_defrag_fail",
4001                          CTLFLAG_RD, &adapter->mbuf_defrag_failed,
4002                          "Defragmenting mbuf chain failed");
4003         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "tx_dma_fail",
4004                         CTLFLAG_RD, &adapter->no_tx_dma_setup,
4005                         "Driver tx dma failure in xmit");
4006         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
4007                         CTLFLAG_RD, &adapter->rx_overruns,
4008                         "RX overruns");
4009         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
4010                         CTLFLAG_RD, &adapter->watchdog_events,
4011                         "Watchdog timeouts");
4012         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
4013                         CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL,
4014                         em_sysctl_reg_handler, "IU",
4015                         "Device Control Register");
4016         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
4017                         CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL,
4018                         em_sysctl_reg_handler, "IU",
4019                         "Receiver Control Register");
4020         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
4021                         CTLFLAG_RD, &adapter->hw.fc.high_water, 0,
4022                         "Flow Control High Watermark");
4023         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
4024                         CTLFLAG_RD, &adapter->hw.fc.low_water, 0,
4025                         "Flow Control Low Watermark");
4026
4027         for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
4028                 struct tx_ring *txr = &tx_que->txr;
4029                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
4030                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4031                                             CTLFLAG_RD, NULL, "TX Queue Name");
4032                 queue_list = SYSCTL_CHILDREN(queue_node);
4033
4034                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
4035                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4036                                 E1000_TDH(txr->me),
4037                                 em_sysctl_reg_handler, "IU",
4038                                 "Transmit Descriptor Head");
4039                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
4040                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4041                                 E1000_TDT(txr->me),
4042                                 em_sysctl_reg_handler, "IU",
4043                                 "Transmit Descriptor Tail");
4044                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
4045                                 CTLFLAG_RD, &txr->tx_irq,
4046                                 "Queue MSI-X Transmit Interrupts");
4047         }
4048
4049         for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) {
4050                 struct rx_ring *rxr = &rx_que->rxr;
4051                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
4052                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4053                                             CTLFLAG_RD, NULL, "RX Queue Name");
4054                 queue_list = SYSCTL_CHILDREN(queue_node);
4055
4056                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
4057                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4058                                 E1000_RDH(rxr->me),
4059                                 em_sysctl_reg_handler, "IU",
4060                                 "Receive Descriptor Head");
4061                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
4062                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4063                                 E1000_RDT(rxr->me),
4064                                 em_sysctl_reg_handler, "IU",
4065                                 "Receive Descriptor Tail");
4066                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
4067                                 CTLFLAG_RD, &rxr->rx_irq,
4068                                 "Queue MSI-X Receive Interrupts");
4069         }
4070
4071         /* MAC stats get their own sub node */
4072
4073         stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
4074                                     CTLFLAG_RD, NULL, "Statistics");
4075         stat_list = SYSCTL_CHILDREN(stat_node);
4076
4077         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
4078                         CTLFLAG_RD, &stats->ecol,
4079                         "Excessive collisions");
4080         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
4081                         CTLFLAG_RD, &stats->scc,
4082                         "Single collisions");
4083         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
4084                         CTLFLAG_RD, &stats->mcc,
4085                         "Multiple collisions");
4086         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
4087                         CTLFLAG_RD, &stats->latecol,
4088                         "Late collisions");
4089         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
4090                         CTLFLAG_RD, &stats->colc,
4091                         "Collision Count");
4092         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
4093                         CTLFLAG_RD, &adapter->stats.symerrs,
4094                         "Symbol Errors");
4095         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
4096                         CTLFLAG_RD, &adapter->stats.sec,
4097                         "Sequence Errors");
4098         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
4099                         CTLFLAG_RD, &adapter->stats.dc,
4100                         "Defer Count");
4101         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
4102                         CTLFLAG_RD, &adapter->stats.mpc,
4103                         "Missed Packets");
4104         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
4105                         CTLFLAG_RD, &adapter->stats.rnbc,
4106                         "Receive No Buffers");
4107         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
4108                         CTLFLAG_RD, &adapter->stats.ruc,
4109                         "Receive Undersize");
4110         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
4111                         CTLFLAG_RD, &adapter->stats.rfc,
4112                         "Fragmented Packets Received ");
4113         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
4114                         CTLFLAG_RD, &adapter->stats.roc,
4115                         "Oversized Packets Received");
4116         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
4117                         CTLFLAG_RD, &adapter->stats.rjc,
4118                         "Recevied Jabber");
4119         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
4120                         CTLFLAG_RD, &adapter->stats.rxerrc,
4121                         "Receive Errors");
4122         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
4123                         CTLFLAG_RD, &adapter->stats.crcerrs,
4124                         "CRC errors");
4125         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
4126                         CTLFLAG_RD, &adapter->stats.algnerrc,
4127                         "Alignment Errors");
4128         /* On 82575 these are collision counts */
4129         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
4130                         CTLFLAG_RD, &adapter->stats.cexterr,
4131                         "Collision/Carrier extension errors");
4132         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
4133                         CTLFLAG_RD, &adapter->stats.xonrxc,
4134                         "XON Received");
4135         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
4136                         CTLFLAG_RD, &adapter->stats.xontxc,
4137                         "XON Transmitted");
4138         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
4139                         CTLFLAG_RD, &adapter->stats.xoffrxc,
4140                         "XOFF Received");
4141         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
4142                         CTLFLAG_RD, &adapter->stats.xofftxc,
4143                         "XOFF Transmitted");
4144
4145         /* Packet Reception Stats */
4146         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
4147                         CTLFLAG_RD, &adapter->stats.tpr,
4148                         "Total Packets Received ");
4149         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
4150                         CTLFLAG_RD, &adapter->stats.gprc,
4151                         "Good Packets Received");
4152         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
4153                         CTLFLAG_RD, &adapter->stats.bprc,
4154                         "Broadcast Packets Received");
4155         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
4156                         CTLFLAG_RD, &adapter->stats.mprc,
4157                         "Multicast Packets Received");
4158         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
4159                         CTLFLAG_RD, &adapter->stats.prc64,
4160                         "64 byte frames received ");
4161         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
4162                         CTLFLAG_RD, &adapter->stats.prc127,
4163                         "65-127 byte frames received");
4164         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
4165                         CTLFLAG_RD, &adapter->stats.prc255,
4166                         "128-255 byte frames received");
4167         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
4168                         CTLFLAG_RD, &adapter->stats.prc511,
4169                         "256-511 byte frames received");
4170         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
4171                         CTLFLAG_RD, &adapter->stats.prc1023,
4172                         "512-1023 byte frames received");
4173         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
4174                         CTLFLAG_RD, &adapter->stats.prc1522,
4175                         "1023-1522 byte frames received");
4176         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
4177                         CTLFLAG_RD, &adapter->stats.gorc,
4178                         "Good Octets Received");
4179
4180         /* Packet Transmission Stats */
4181         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
4182                         CTLFLAG_RD, &adapter->stats.gotc,
4183                         "Good Octets Transmitted");
4184         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
4185                         CTLFLAG_RD, &adapter->stats.tpt,
4186                         "Total Packets Transmitted");
4187         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
4188                         CTLFLAG_RD, &adapter->stats.gptc,
4189                         "Good Packets Transmitted");
4190         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
4191                         CTLFLAG_RD, &adapter->stats.bptc,
4192                         "Broadcast Packets Transmitted");
4193         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
4194                         CTLFLAG_RD, &adapter->stats.mptc,
4195                         "Multicast Packets Transmitted");
4196         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
4197                         CTLFLAG_RD, &adapter->stats.ptc64,
4198                         "64 byte frames transmitted ");
4199         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
4200                         CTLFLAG_RD, &adapter->stats.ptc127,
4201                         "65-127 byte frames transmitted");
4202         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
4203                         CTLFLAG_RD, &adapter->stats.ptc255,
4204                         "128-255 byte frames transmitted");
4205         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
4206                         CTLFLAG_RD, &adapter->stats.ptc511,
4207                         "256-511 byte frames transmitted");
4208         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
4209                         CTLFLAG_RD, &adapter->stats.ptc1023,
4210                         "512-1023 byte frames transmitted");
4211         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
4212                         CTLFLAG_RD, &adapter->stats.ptc1522,
4213                         "1024-1522 byte frames transmitted");
4214         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
4215                         CTLFLAG_RD, &adapter->stats.tsctc,
4216                         "TSO Contexts Transmitted");
4217         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
4218                         CTLFLAG_RD, &adapter->stats.tsctfc,
4219                         "TSO Contexts Failed");
4220
4221
4222         /* Interrupt Stats */
4223
4224         int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
4225                                     CTLFLAG_RD, NULL, "Interrupt Statistics");
4226         int_list = SYSCTL_CHILDREN(int_node);
4227
4228         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
4229                         CTLFLAG_RD, &adapter->stats.iac,
4230                         "Interrupt Assertion Count");
4231
4232         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
4233                         CTLFLAG_RD, &adapter->stats.icrxptc,
4234                         "Interrupt Cause Rx Pkt Timer Expire Count");
4235
4236         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
4237                         CTLFLAG_RD, &adapter->stats.icrxatc,
4238                         "Interrupt Cause Rx Abs Timer Expire Count");
4239
4240         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
4241                         CTLFLAG_RD, &adapter->stats.ictxptc,
4242                         "Interrupt Cause Tx Pkt Timer Expire Count");
4243
4244         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
4245                         CTLFLAG_RD, &adapter->stats.ictxatc,
4246                         "Interrupt Cause Tx Abs Timer Expire Count");
4247
4248         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
4249                         CTLFLAG_RD, &adapter->stats.ictxqec,
4250                         "Interrupt Cause Tx Queue Empty Count");
4251
4252         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
4253                         CTLFLAG_RD, &adapter->stats.ictxqmtc,
4254                         "Interrupt Cause Tx Queue Min Thresh Count");
4255
4256         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
4257                         CTLFLAG_RD, &adapter->stats.icrxdmtc,
4258                         "Interrupt Cause Rx Desc Min Thresh Count");
4259
4260         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
4261                         CTLFLAG_RD, &adapter->stats.icrxoc,
4262                         "Interrupt Cause Receiver Overrun Count");
4263 }
4264
4265 /**********************************************************************
4266  *
4267  *  This routine provides a way to dump out the adapter eeprom,
4268  *  often a useful debug/service tool. This only dumps the first
4269  *  32 words, stuff that matters is in that extent.
4270  *
4271  **********************************************************************/
4272 static int
4273 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4274 {
4275         struct adapter *adapter = (struct adapter *)arg1;
4276         int error;
4277         int result;
4278
4279         result = -1;
4280         error = sysctl_handle_int(oidp, &result, 0, req);
4281
4282         if (error || !req->newptr)
4283                 return (error);
4284
4285         /*
4286          * This value will cause a hex dump of the
4287          * first 32 16-bit words of the EEPROM to
4288          * the screen.
4289          */
4290         if (result == 1)
4291                 em_print_nvm_info(adapter);
4292
4293         return (error);
4294 }
4295
4296 static void
4297 em_print_nvm_info(struct adapter *adapter)
4298 {
4299         u16 eeprom_data;
4300         int i, j, row = 0;
4301
4302         /* Its a bit crude, but it gets the job done */
4303         printf("\nInterface EEPROM Dump:\n");
4304         printf("Offset\n0x0000  ");
4305         for (i = 0, j = 0; i < 32; i++, j++) {
4306                 if (j == 8) { /* Make the offset block */
4307                         j = 0; ++row;
4308                         printf("\n0x00%x0  ",row);
4309                 }
4310                 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
4311                 printf("%04x ", eeprom_data);
4312         }
4313         printf("\n");
4314 }
4315
4316 static int
4317 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4318 {
4319         struct em_int_delay_info *info;
4320         struct adapter *adapter;
4321         u32 regval;
4322         int error, usecs, ticks;
4323
4324         info = (struct em_int_delay_info *) arg1;
4325         usecs = info->value;
4326         error = sysctl_handle_int(oidp, &usecs, 0, req);
4327         if (error != 0 || req->newptr == NULL)
4328                 return (error);
4329         if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4330                 return (EINVAL);
4331         info->value = usecs;
4332         ticks = EM_USECS_TO_TICKS(usecs);
4333         if (info->offset == E1000_ITR)  /* units are 256ns here */
4334                 ticks *= 4;
4335
4336         adapter = info->adapter;
4337
4338         regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
4339         regval = (regval & ~0xffff) | (ticks & 0xffff);
4340         /* Handle a few special cases. */
4341         switch (info->offset) {
4342         case E1000_RDTR:
4343                 break;
4344         case E1000_TIDV:
4345                 if (ticks == 0) {
4346                         adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
4347                         /* Don't write 0 into the TIDV register. */
4348                         regval++;
4349                 } else
4350                         adapter->txd_cmd |= E1000_TXD_CMD_IDE;
4351                 break;
4352         }
4353         E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
4354         return (0);
4355 }
4356
4357 static void
4358 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
4359         const char *description, struct em_int_delay_info *info,
4360         int offset, int value)
4361 {
4362         info->adapter = adapter;
4363         info->offset = offset;
4364         info->value = value;
4365         SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev),
4366             SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4367             OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
4368             info, 0, em_sysctl_int_delay, "I", description);
4369 }
4370
4371 /*
4372  * Set flow control using sysctl:
4373  * Flow control values:
4374  *      0 - off
4375  *      1 - rx pause
4376  *      2 - tx pause
4377  *      3 - full
4378  */
4379 static int
4380 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4381 {
4382         int error;
4383         static int input = 3; /* default is full */
4384         struct adapter  *adapter = (struct adapter *) arg1;
4385
4386         error = sysctl_handle_int(oidp, &input, 0, req);
4387
4388         if ((error) || (req->newptr == NULL))
4389                 return (error);
4390
4391         if (input == adapter->fc) /* no change? */
4392                 return (error);
4393
4394         switch (input) {
4395         case e1000_fc_rx_pause:
4396         case e1000_fc_tx_pause:
4397         case e1000_fc_full:
4398         case e1000_fc_none:
4399                 adapter->hw.fc.requested_mode = input;
4400                 adapter->fc = input;
4401                 break;
4402         default:
4403                 /* Do nothing */
4404                 return (error);
4405         }
4406
4407         adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
4408         e1000_force_mac_fc(&adapter->hw);
4409         return (error);
4410 }
4411
4412 /*
4413  * Manage Energy Efficient Ethernet:
4414  * Control values:
4415  *     0/1 - enabled/disabled
4416  */
4417 static int
4418 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4419 {
4420         struct adapter *adapter = (struct adapter *) arg1;
4421         int error, value;
4422
4423         value = adapter->hw.dev_spec.ich8lan.eee_disable;
4424         error = sysctl_handle_int(oidp, &value, 0, req);
4425         if (error || req->newptr == NULL)
4426                 return (error);
4427         adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4428         em_if_init(adapter->ctx);
4429
4430         return (0);
4431 }
4432
4433 static int
4434 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4435 {
4436         struct adapter *adapter;
4437         int error;
4438         int result;
4439
4440         result = -1;
4441         error = sysctl_handle_int(oidp, &result, 0, req);
4442
4443         if (error || !req->newptr)
4444                 return (error);
4445
4446         if (result == 1) {
4447                 adapter = (struct adapter *) arg1;
4448                 em_print_debug_info(adapter);
4449         }
4450
4451         return (error);
4452 }
4453
4454 static int
4455 em_get_rs(SYSCTL_HANDLER_ARGS)
4456 {
4457         struct adapter *adapter = (struct adapter *) arg1;
4458         int error;
4459         int result;
4460
4461         result = 0;
4462         error = sysctl_handle_int(oidp, &result, 0, req);
4463
4464         if (error || !req->newptr || result != 1)
4465                 return (error);
4466         em_dump_rs(adapter);
4467
4468         return (error);
4469 }
4470
4471 static void
4472 em_if_debug(if_ctx_t ctx)
4473 {
4474         em_dump_rs(iflib_get_softc(ctx));
4475 }
4476
4477 /*
4478  * This routine is meant to be fluid, add whatever is
4479  * needed for debugging a problem.  -jfv
4480  */
4481 static void
4482 em_print_debug_info(struct adapter *adapter)
4483 {
4484         device_t dev = iflib_get_dev(adapter->ctx);
4485         struct ifnet *ifp = iflib_get_ifp(adapter->ctx);
4486         struct tx_ring *txr = &adapter->tx_queues->txr;
4487         struct rx_ring *rxr = &adapter->rx_queues->rxr;
4488
4489         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
4490                 printf("Interface is RUNNING ");
4491         else
4492                 printf("Interface is NOT RUNNING\n");
4493
4494         if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
4495                 printf("and INACTIVE\n");
4496         else
4497                 printf("and ACTIVE\n");
4498
4499         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
4500                 device_printf(dev, "TX Queue %d ------\n", i);
4501                 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
4502                         E1000_READ_REG(&adapter->hw, E1000_TDH(i)),
4503                         E1000_READ_REG(&adapter->hw, E1000_TDT(i)));
4504
4505         }
4506         for (int j=0; j < adapter->rx_num_queues; j++, rxr++) {
4507                 device_printf(dev, "RX Queue %d ------\n", j);
4508                 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
4509                         E1000_READ_REG(&adapter->hw, E1000_RDH(j)),
4510                         E1000_READ_REG(&adapter->hw, E1000_RDT(j)));
4511         }
4512 }
4513
4514 /*
4515  * 82574 only:
4516  * Write a new value to the EEPROM increasing the number of MSIX
4517  * vectors from 3 to 5, for proper multiqueue support.
4518  */
4519 static void
4520 em_enable_vectors_82574(if_ctx_t ctx)
4521 {
4522         struct adapter *adapter = iflib_get_softc(ctx);
4523         struct e1000_hw *hw = &adapter->hw;
4524         device_t dev = iflib_get_dev(ctx);
4525         u16 edata;
4526
4527         e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4528         printf("Current cap: %#06x\n", edata);
4529         if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
4530                 device_printf(dev, "Writing to eeprom: increasing "
4531                     "reported MSIX vectors from 3 to 5...\n");
4532                 edata &= ~(EM_NVM_MSIX_N_MASK);
4533                 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
4534                 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4535                 e1000_update_nvm_checksum(hw);
4536                 device_printf(dev, "Writing to eeprom: done\n");
4537         }
4538 }