sys/dev/e1000/if_em.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /* $FreeBSD$ */
  30 #include "if_em.h"
  31 #include <sys/sbuf.h>
  32 #include <machine/_inttypes.h>
  33
  34 #define em_mac_min e1000_82547
  35 #define igb_mac_min e1000_82575
  36
  37 /*********************************************************************
  38  *  Driver version:
  39  *********************************************************************/
  40 char em_driver_version[] = "7.6.1-k";
  41
  42 /*********************************************************************
  43  *  PCI Device ID Table
  44  *
  45  *  Used by probe to select devices to load on
  46  *  Last field stores an index into e1000_strings
  47  *  Last entry must be all 0s
  48  *
  49  *  { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
  50  *********************************************************************/
  51
  52 static pci_vendor_info_t em_vendor_info_array[] =
  53 {
  54         /* Intel(R) PRO/1000 Network Connection - Legacy em*/
  55         PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"),
  56         PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"),
  57         PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"),
  58         PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"),
  59         PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"),
  60
  61         PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"),
  62         PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"),
  63         PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"),
  64         PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  65         PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"),
  66         PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"),
  67         PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  68
  69         PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"),
  70
  71         PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"),
  72         PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
  73
  74         PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
  75         PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
  76         PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
  77         PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"),
  78
  79         PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"),
  80         PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"),
  81         PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"),
  82         PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"),
  83         PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"),
  84
  85         PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  86         PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
  87         PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
  88         PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  89         PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"),
  90         PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"),
  91         PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"),
  92         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
  93         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"),
  94
  95         PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"),
  96         PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  97         PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"),
  98
  99         /* Intel(R) PRO/1000 Network Connection - em */
 100         PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
 101         PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
 102         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"),
 103         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"),
 104         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"),
 105         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 106         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"),
 107         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"),
 108         PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 109         PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"),
 110         PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
 111         PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
 112         PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"),
 113         PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"),
 114         PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"),
 115         PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"),
 116         PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"),
 117         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"),
 118         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"),
 119         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"),
 120         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"),
 121         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
 122         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 123         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"),
 124         PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"),
 125         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
 126         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"),
 127         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"),
 128         PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"),
 129         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
 130         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 131         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"),
 132         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"),
 133         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"),
 134         PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"),
 135         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
 136         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"),
 137         PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"),
 138         PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"),
 139         PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"),
 140         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"),
 141         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"),
 142         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"),
 143         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"),
 144         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"),
 145         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"),
 146         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"),
 147         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"),
 148         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"),
 149         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"),
 150         PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"),
 151         PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"),
 152         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"),
 153         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"),
 154         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"),
 155         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"),
 156         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"),
 157         PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"),
 158         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"),
 159         PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"),
 160         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"),
 161         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"),
 162         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"),
 163         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"),
 164         PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"),
 165         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"),
 166         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"),
 167         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"),
 168         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"),
 169         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) PRO/1000 Network Connection"),
 170         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) PRO/1000 Network Connection"),
 171         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) PRO/1000 Network Connection"),
 172         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) PRO/1000 Network Connection"),
 173         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) PRO/1000 Network Connection"),
 174         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) PRO/1000 Network Connection"),
 175         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) PRO/1000 Network Connection"),
 176         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) PRO/1000 Network Connection"),
 177         /* required last entry */
 178         PVID_END
 179 };
 180
 181 static pci_vendor_info_t igb_vendor_info_array[] =
 182 {
 183         /* Intel(R) PRO/1000 Network Connection - igb */
 184         PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 185         PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 186         PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 187         PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 188         PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 189         PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 190         PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 191         PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 192         PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 193         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 194         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 195         PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 196         PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 197         PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 198         PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 199         PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 200         PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 201         PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 202         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 203         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 204         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 205         PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 206         PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 207         PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 208         PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 209         PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 210         PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 211         PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 212         PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 213         PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 214         PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 215         PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 216         PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 217         PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 218         PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 219         PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 220         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 221         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 222         PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 223         /* required last entry */
 224         PVID_END
 225 };
 226
 227 /*********************************************************************
 228  *  Function prototypes
 229  *********************************************************************/
 230 static void     *em_register(device_t dev);
 231 static void     *igb_register(device_t dev);
 232 static int      em_if_attach_pre(if_ctx_t ctx);
 233 static int      em_if_attach_post(if_ctx_t ctx);
 234 static int      em_if_detach(if_ctx_t ctx);
 235 static int      em_if_shutdown(if_ctx_t ctx);
 236 static int      em_if_suspend(if_ctx_t ctx);
 237 static int      em_if_resume(if_ctx_t ctx);
 238
 239 static int      em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets);
 240 static int      em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets);
 241 static void     em_if_queues_free(if_ctx_t ctx);
 242
 243 static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
 244 static void     em_if_init(if_ctx_t ctx);
 245 static void     em_if_stop(if_ctx_t ctx);
 246 static void     em_if_media_status(if_ctx_t, struct ifmediareq *);
 247 static int      em_if_media_change(if_ctx_t ctx);
 248 static int      em_if_mtu_set(if_ctx_t ctx, uint32_t mtu);
 249 static void     em_if_timer(if_ctx_t ctx, uint16_t qid);
 250 static void     em_if_vlan_register(if_ctx_t ctx, u16 vtag);
 251 static void     em_if_vlan_unregister(if_ctx_t ctx, u16 vtag);
 252
 253 static void     em_identify_hardware(if_ctx_t ctx);
 254 static int      em_allocate_pci_resources(if_ctx_t ctx);
 255 static void     em_free_pci_resources(if_ctx_t ctx);
 256 static void     em_reset(if_ctx_t ctx);
 257 static int      em_setup_interface(if_ctx_t ctx);
 258 static int      em_setup_msix(if_ctx_t ctx);
 259
 260 static void     em_initialize_transmit_unit(if_ctx_t ctx);
 261 static void     em_initialize_receive_unit(if_ctx_t ctx);
 262
 263 static void     em_if_enable_intr(if_ctx_t ctx);
 264 static void     em_if_disable_intr(if_ctx_t ctx);
 265 static int      em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 266 static int      em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
 267 static void     em_if_multi_set(if_ctx_t ctx);
 268 static void     em_if_update_admin_status(if_ctx_t ctx);
 269 static void     em_if_debug(if_ctx_t ctx);
 270 static void     em_update_stats_counters(struct adapter *);
 271 static void     em_add_hw_stats(struct adapter *adapter);
 272 static int      em_if_set_promisc(if_ctx_t ctx, int flags);
 273 static void     em_setup_vlan_hw_support(struct adapter *);
 274 static int      em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
 275 static void     em_print_nvm_info(struct adapter *);
 276 static int      em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 277 static int      em_get_rs(SYSCTL_HANDLER_ARGS);
 278 static void     em_print_debug_info(struct adapter *);
 279 static int      em_is_valid_ether_addr(u8 *);
 280 static int      em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
 281 static void     em_add_int_delay_sysctl(struct adapter *, const char *,
 282                     const char *, struct em_int_delay_info *, int, int);
 283 /* Management and WOL Support */
 284 static void     em_init_manageability(struct adapter *);
 285 static void     em_release_manageability(struct adapter *);
 286 static void     em_get_hw_control(struct adapter *);
 287 static void     em_release_hw_control(struct adapter *);
 288 static void     em_get_wakeup(if_ctx_t ctx);
 289 static void     em_enable_wakeup(if_ctx_t ctx);
 290 static int      em_enable_phy_wakeup(struct adapter *);
 291 static void     em_disable_aspm(struct adapter *);
 292
 293 int             em_intr(void *arg);
 294 static void     em_disable_promisc(if_ctx_t ctx);
 295
 296 /* MSIX handlers */
 297 static int      em_if_msix_intr_assign(if_ctx_t, int);
 298 static int      em_msix_link(void *);
 299 static void     em_handle_link(void *context);
 300
 301 static void     em_enable_vectors_82574(if_ctx_t);
 302
 303 static int      em_set_flowcntl(SYSCTL_HANDLER_ARGS);
 304 static int      em_sysctl_eee(SYSCTL_HANDLER_ARGS);
 305 static void     em_if_led_func(if_ctx_t ctx, int onoff);
 306
 307 static int      em_get_regs(SYSCTL_HANDLER_ARGS);
 308
 309 static void     lem_smartspeed(struct adapter *adapter);
 310 static void     igb_configure_queues(struct adapter *adapter);
 311
 312
 313 /*********************************************************************
 314  *  FreeBSD Device Interface Entry Points
 315  *********************************************************************/
 316 static device_method_t em_methods[] = {
 317         /* Device interface */
 318         DEVMETHOD(device_register, em_register),
 319         DEVMETHOD(device_probe, iflib_device_probe),
 320         DEVMETHOD(device_attach, iflib_device_attach),
 321         DEVMETHOD(device_detach, iflib_device_detach),
 322         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 323         DEVMETHOD(device_suspend, iflib_device_suspend),
 324         DEVMETHOD(device_resume, iflib_device_resume),
 325         DEVMETHOD_END
 326 };
 327
 328 static device_method_t igb_methods[] = {
 329         /* Device interface */
 330         DEVMETHOD(device_register, igb_register),
 331         DEVMETHOD(device_probe, iflib_device_probe),
 332         DEVMETHOD(device_attach, iflib_device_attach),
 333         DEVMETHOD(device_detach, iflib_device_detach),
 334         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 335         DEVMETHOD(device_suspend, iflib_device_suspend),
 336         DEVMETHOD(device_resume, iflib_device_resume),
 337         DEVMETHOD_END
 338 };
 339
 340
 341 static driver_t em_driver = {
 342         "em", em_methods, sizeof(struct adapter),
 343 };
 344
 345 static devclass_t em_devclass;
 346 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
 347
 348 MODULE_DEPEND(em, pci, 1, 1, 1);
 349 MODULE_DEPEND(em, ether, 1, 1, 1);
 350 MODULE_DEPEND(em, iflib, 1, 1, 1);
 351
 352 IFLIB_PNP_INFO(pci, em, em_vendor_info_array);
 353
 354 static driver_t igb_driver = {
 355         "igb", igb_methods, sizeof(struct adapter),
 356 };
 357
 358 static devclass_t igb_devclass;
 359 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
 360
 361 MODULE_DEPEND(igb, pci, 1, 1, 1);
 362 MODULE_DEPEND(igb, ether, 1, 1, 1);
 363 MODULE_DEPEND(igb, iflib, 1, 1, 1);
 364
 365 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array);
 366
 367 static device_method_t em_if_methods[] = {
 368         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 369         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 370         DEVMETHOD(ifdi_detach, em_if_detach),
 371         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 372         DEVMETHOD(ifdi_suspend, em_if_suspend),
 373         DEVMETHOD(ifdi_resume, em_if_resume),
 374         DEVMETHOD(ifdi_init, em_if_init),
 375         DEVMETHOD(ifdi_stop, em_if_stop),
 376         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 377         DEVMETHOD(ifdi_intr_enable, em_if_enable_intr),
 378         DEVMETHOD(ifdi_intr_disable, em_if_disable_intr),
 379         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 380         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 381         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 382         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 383         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 384         DEVMETHOD(ifdi_media_status, em_if_media_status),
 385         DEVMETHOD(ifdi_media_change, em_if_media_change),
 386         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 387         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 388         DEVMETHOD(ifdi_timer, em_if_timer),
 389         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 390         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 391         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 392         DEVMETHOD(ifdi_led_func, em_if_led_func),
 393         DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable),
 394         DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable),
 395         DEVMETHOD(ifdi_debug, em_if_debug),
 396         DEVMETHOD_END
 397 };
 398
 399 /*
 400  * note that if (adapter->msix_mem) is replaced by:
 401  * if (adapter->intr_type == IFLIB_INTR_MSIX)
 402  */
 403 static driver_t em_if_driver = {
 404         "em_if", em_if_methods, sizeof(struct adapter)
 405 };
 406
 407 /*********************************************************************
 408  *  Tunable default values.
 409  *********************************************************************/
 410
 411 #define EM_TICKS_TO_USECS(ticks)        ((1024 * (ticks) + 500) / 1000)
 412 #define EM_USECS_TO_TICKS(usecs)        ((1000 * (usecs) + 512) / 1024)
 413 #define M_TSO_LEN                       66
 414
 415 #define MAX_INTS_PER_SEC        8000
 416 #define DEFAULT_ITR             (1000000000/(MAX_INTS_PER_SEC * 256))
 417
 418 /* Allow common code without TSO */
 419 #ifndef CSUM_TSO
 420 #define CSUM_TSO        0
 421 #endif
 422
 423 #define TSO_WORKAROUND  4
 424
 425 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters");
 426
 427 static int em_disable_crc_stripping = 0;
 428 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
 429     &em_disable_crc_stripping, 0, "Disable CRC Stripping");
 430
 431 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
 432 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
 433 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
 434     0, "Default transmit interrupt delay in usecs");
 435 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
 436     0, "Default receive interrupt delay in usecs");
 437
 438 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
 439 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
 440 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
 441     &em_tx_abs_int_delay_dflt, 0,
 442     "Default transmit interrupt delay limit in usecs");
 443 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
 444     &em_rx_abs_int_delay_dflt, 0,
 445     "Default receive interrupt delay limit in usecs");
 446
 447 static int em_smart_pwr_down = FALSE;
 448 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
 449     0, "Set to true to leave smart power down enabled on newer adapters");
 450
 451 /* Controls whether promiscuous also shows bad packets */
 452 static int em_debug_sbp = TRUE;
 453 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
 454     "Show bad packets in promiscuous mode");
 455
 456 /* How many packets rxeof tries to clean at a time */
 457 static int em_rx_process_limit = 100;
 458 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
 459     &em_rx_process_limit, 0,
 460     "Maximum number of received packets to process "
 461     "at a time, -1 means unlimited");
 462
 463 /* Energy efficient ethernet - default to OFF */
 464 static int eee_setting = 1;
 465 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
 466     "Enable Energy Efficient Ethernet");
 467
 468 /*
 469 ** Tuneable Interrupt rate
 470 */
 471 static int em_max_interrupt_rate = 8000;
 472 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
 473     &em_max_interrupt_rate, 0, "Maximum interrupts per second");
 474
 475
 476
 477 /* Global used in WOL setup with multiport cards */
 478 static int global_quad_port_a = 0;
 479
 480 extern struct if_txrx igb_txrx;
 481 extern struct if_txrx em_txrx;
 482 extern struct if_txrx lem_txrx;
 483
 484 static struct if_shared_ctx em_sctx_init = {
 485         .isc_magic = IFLIB_MAGIC,
 486         .isc_q_align = PAGE_SIZE,
 487         .isc_tx_maxsize = EM_TSO_SIZE,
 488         .isc_tx_maxsegsize = PAGE_SIZE,
 489         .isc_rx_maxsize = MJUM9BYTES,
 490         .isc_rx_nsegments = 1,
 491         .isc_rx_maxsegsize = MJUM9BYTES,
 492         .isc_nfl = 1,
 493         .isc_nrxqs = 1,
 494         .isc_ntxqs = 1,
 495         .isc_admin_intrcnt = 1,
 496         .isc_vendor_info = em_vendor_info_array,
 497         .isc_driver_version = em_driver_version,
 498         .isc_driver = &em_if_driver,
 499         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 500
 501         .isc_nrxd_min = {EM_MIN_RXD},
 502         .isc_ntxd_min = {EM_MIN_TXD},
 503         .isc_nrxd_max = {EM_MAX_RXD},
 504         .isc_ntxd_max = {EM_MAX_TXD},
 505         .isc_nrxd_default = {EM_DEFAULT_RXD},
 506         .isc_ntxd_default = {EM_DEFAULT_TXD},
 507 };
 508
 509 if_shared_ctx_t em_sctx = &em_sctx_init;
 510
 511
 512 static struct if_shared_ctx igb_sctx_init = {
 513         .isc_magic = IFLIB_MAGIC,
 514         .isc_q_align = PAGE_SIZE,
 515         .isc_tx_maxsize = EM_TSO_SIZE,
 516         .isc_tx_maxsegsize = PAGE_SIZE,
 517         .isc_rx_maxsize = MJUM9BYTES,
 518         .isc_rx_nsegments = 1,
 519         .isc_rx_maxsegsize = MJUM9BYTES,
 520         .isc_nfl = 1,
 521         .isc_nrxqs = 1,
 522         .isc_ntxqs = 1,
 523         .isc_admin_intrcnt = 1,
 524         .isc_vendor_info = igb_vendor_info_array,
 525         .isc_driver_version = em_driver_version,
 526         .isc_driver = &em_if_driver,
 527         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 528
 529         .isc_nrxd_min = {EM_MIN_RXD},
 530         .isc_ntxd_min = {EM_MIN_TXD},
 531         .isc_nrxd_max = {IGB_MAX_RXD},
 532         .isc_ntxd_max = {IGB_MAX_TXD},
 533         .isc_nrxd_default = {EM_DEFAULT_RXD},
 534         .isc_ntxd_default = {EM_DEFAULT_TXD},
 535 };
 536
 537 if_shared_ctx_t igb_sctx = &igb_sctx_init;
 538
 539 /*****************************************************************
 540  *
 541  * Dump Registers
 542  *
 543  ****************************************************************/
 544 #define IGB_REGS_LEN 739
 545
 546 static int em_get_regs(SYSCTL_HANDLER_ARGS)
 547 {
 548         struct adapter *adapter = (struct adapter *)arg1;
 549         struct e1000_hw *hw = &adapter->hw;
 550         struct sbuf *sb;
 551         u32 *regs_buff;
 552         int rc;
 553
 554         regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK);
 555         memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
 556
 557         rc = sysctl_wire_old_buffer(req, 0);
 558         MPASS(rc == 0);
 559         if (rc != 0) {
 560                 free(regs_buff, M_DEVBUF);
 561                 return (rc);
 562         }
 563
 564         sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
 565         MPASS(sb != NULL);
 566         if (sb == NULL) {
 567                 free(regs_buff, M_DEVBUF);
 568                 return (ENOMEM);
 569         }
 570
 571         /* General Registers */
 572         regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
 573         regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
 574         regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
 575         regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
 576         regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
 577         regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
 578         regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
 579         regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
 580         regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
 581         regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
 582         regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
 583         regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
 584         regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
 585         regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
 586         regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
 587         regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
 588         regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
 589         regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
 590         regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
 591         regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
 592         regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
 593         regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
 594
 595         sbuf_printf(sb, "General Registers\n");
 596         sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
 597         sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
 598         sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]);
 599
 600         sbuf_printf(sb, "Interrupt Registers\n");
 601         sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
 602
 603         sbuf_printf(sb, "RX Registers\n");
 604         sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
 605         sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
 606         sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
 607         sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
 608         sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
 609         sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
 610         sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
 611
 612         sbuf_printf(sb, "TX Registers\n");
 613         sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
 614         sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
 615         sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
 616         sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
 617         sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
 618         sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
 619         sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
 620         sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
 621         sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
 622         sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
 623         sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
 624
 625         free(regs_buff, M_DEVBUF);
 626
 627 #ifdef DUMP_DESCS
 628         {
 629                 if_softc_ctx_t scctx = adapter->shared;
 630                 struct rx_ring *rxr = &rx_que->rxr;
 631                 struct tx_ring *txr = &tx_que->txr;
 632                 int ntxd = scctx->isc_ntxd[0];
 633                 int nrxd = scctx->isc_nrxd[0];
 634                 int j;
 635
 636         for (j = 0; j < nrxd; j++) {
 637                 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
 638                 u32 length =  le32toh(rxr->rx_base[j].wb.upper.length);
 639                 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 "  Error:%d  Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
 640         }
 641
 642         for (j = 0; j < min(ntxd, 256); j++) {
 643                 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
 644
 645                 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x  eop: %d DD=%d\n",
 646                             j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
 647                             buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
 648
 649         }
 650         }
 651 #endif
 652
 653         rc = sbuf_finish(sb);
 654         sbuf_delete(sb);
 655         return(rc);
 656 }
 657
 658 static void *
 659 em_register(device_t dev)
 660 {
 661         return (em_sctx);
 662 }
 663
 664 static void *
 665 igb_register(device_t dev)
 666 {
 667         return (igb_sctx);
 668 }
 669
 670 static int
 671 em_set_num_queues(if_ctx_t ctx)
 672 {
 673         struct adapter *adapter = iflib_get_softc(ctx);
 674         int maxqueues;
 675
 676         /* Sanity check based on HW */
 677         switch (adapter->hw.mac.type) {
 678         case e1000_82576:
 679         case e1000_82580:
 680         case e1000_i350:
 681         case e1000_i354:
 682                 maxqueues = 8;
 683                 break;
 684         case e1000_i210:
 685         case e1000_82575:
 686                 maxqueues = 4;
 687                 break;
 688         case e1000_i211:
 689         case e1000_82574:
 690                 maxqueues = 2;
 691                 break;
 692         default:
 693                 maxqueues = 1;
 694                 break;
 695         }
 696
 697         return (maxqueues);
 698 }
 699
 700
 701 #define EM_CAPS \
 702         IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \
 703         IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | \
 704         IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU;
 705
 706 #define IGB_CAPS \
 707         IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \
 708         IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM | \
 709         IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU | IFCAP_TXCSUM_IPV6 | IFCAP_HWCSUM_IPV6 | IFCAP_JUMBO_MTU;
 710
 711 /*********************************************************************
 712  *  Device initialization routine
 713  *
 714  *  The attach entry point is called when the driver is being loaded.
 715  *  This routine identifies the type of hardware, allocates all resources
 716  *  and initializes the hardware.
 717  *
 718  *  return 0 on success, positive on failure
 719  *********************************************************************/
 720
 721 static int
 722 em_if_attach_pre(if_ctx_t ctx)
 723 {
 724         struct adapter *adapter;
 725         if_softc_ctx_t scctx;
 726         device_t dev;
 727         struct e1000_hw *hw;
 728         int error = 0;
 729
 730         INIT_DEBUGOUT("em_if_attach_pre begin");
 731         dev = iflib_get_dev(ctx);
 732         adapter = iflib_get_softc(ctx);
 733
 734         if (resource_disabled("em", device_get_unit(dev))) {
 735                 device_printf(dev, "Disabled by device hint\n");
 736                 return (ENXIO);
 737         }
 738
 739         adapter->ctx = adapter->osdep.ctx = ctx;
 740         adapter->dev = adapter->osdep.dev = dev;
 741         scctx = adapter->shared = iflib_get_softc_ctx(ctx);
 742         adapter->media = iflib_get_media(ctx);
 743         hw = &adapter->hw;
 744
 745         adapter->tx_process_limit = scctx->isc_ntxd[0];
 746
 747         /* SYSCTL stuff */
 748         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 749             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 750             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 751             em_sysctl_nvm_info, "I", "NVM Information");
 752
 753         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 754             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 755             OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 756             em_sysctl_debug_info, "I", "Debug Information");
 757
 758         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 759             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 760             OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 761             em_set_flowcntl, "I", "Flow Control");
 762
 763         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 764             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 765             OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0,
 766             em_get_regs, "A", "Dump Registers");
 767
 768         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 769             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 770             OID_AUTO, "rs_dump", CTLTYPE_INT | CTLFLAG_RW, adapter, 0,
 771             em_get_rs, "I", "Dump RS indexes");
 772
 773         /* Determine hardware and mac info */
 774         em_identify_hardware(ctx);
 775
 776         /* Set isc_msix_bar */
 777         scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR);
 778         scctx->isc_tx_nsegments = EM_MAX_SCATTER;
 779         scctx->isc_tx_tso_segments_max = scctx->isc_tx_nsegments;
 780         scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 781         scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 782         scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
 783         device_printf(dev, "attach_pre capping queues at %d\n", scctx->isc_ntxqsets_max);
 784
 785         scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 786
 787
 788         if (adapter->hw.mac.type >= igb_mac_min) {
 789                 int try_second_bar;
 790
 791                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
 792                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
 793                 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
 794                 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
 795                 scctx->isc_txrx = &igb_txrx;
 796                 scctx->isc_capenable = IGB_CAPS;
 797                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | CSUM_IP6_TCP \
 798                         | CSUM_IP6_UDP | CSUM_IP6_TCP;
 799                 if (adapter->hw.mac.type != e1000_82575)
 800                         scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
 801
 802                 /*
 803                 ** Some new devices, as with ixgbe, now may
 804                 ** use a different BAR, so we need to keep
 805                 ** track of which is used.
 806                 */
 807                 try_second_bar = pci_read_config(dev, scctx->isc_msix_bar, 4);
 808                 if (try_second_bar == 0)
 809                         scctx->isc_msix_bar += 4;
 810
 811         } else if (adapter->hw.mac.type >= em_mac_min) {
 812                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 813                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
 814                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 815                 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
 816                 scctx->isc_txrx = &em_txrx;
 817                 scctx->isc_capenable = EM_CAPS;
 818                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 819         } else {
 820                 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 821                 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
 822                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 823                 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
 824                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 825                 scctx->isc_txrx = &lem_txrx;
 826                 scctx->isc_capenable = EM_CAPS;
 827                 if (adapter->hw.mac.type < e1000_82543)
 828                         scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
 829                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 830                 scctx->isc_msix_bar = 0;
 831         }
 832
 833         /* Setup PCI resources */
 834         if (em_allocate_pci_resources(ctx)) {
 835                 device_printf(dev, "Allocation of PCI resources failed\n");
 836                 error = ENXIO;
 837                 goto err_pci;
 838         }
 839
 840         /*
 841         ** For ICH8 and family we need to
 842         ** map the flash memory, and this
 843         ** must happen after the MAC is
 844         ** identified
 845         */
 846         if ((hw->mac.type == e1000_ich8lan) ||
 847             (hw->mac.type == e1000_ich9lan) ||
 848             (hw->mac.type == e1000_ich10lan) ||
 849             (hw->mac.type == e1000_pchlan) ||
 850             (hw->mac.type == e1000_pch2lan) ||
 851             (hw->mac.type == e1000_pch_lpt)) {
 852                 int rid = EM_BAR_TYPE_FLASH;
 853                 adapter->flash = bus_alloc_resource_any(dev,
 854                     SYS_RES_MEMORY, &rid, RF_ACTIVE);
 855                 if (adapter->flash == NULL) {
 856                         device_printf(dev, "Mapping of Flash failed\n");
 857                         error = ENXIO;
 858                         goto err_pci;
 859                 }
 860                 /* This is used in the shared code */
 861                 hw->flash_address = (u8 *)adapter->flash;
 862                 adapter->osdep.flash_bus_space_tag =
 863                     rman_get_bustag(adapter->flash);
 864                 adapter->osdep.flash_bus_space_handle =
 865                     rman_get_bushandle(adapter->flash);
 866         }
 867         /*
 868         ** In the new SPT device flash is not  a
 869         ** separate BAR, rather it is also in BAR0,
 870         ** so use the same tag and an offset handle for the
 871         ** FLASH read/write macros in the shared code.
 872         */
 873         else if (hw->mac.type >= e1000_pch_spt) {
 874                 adapter->osdep.flash_bus_space_tag =
 875                     adapter->osdep.mem_bus_space_tag;
 876                 adapter->osdep.flash_bus_space_handle =
 877                     adapter->osdep.mem_bus_space_handle
 878                     + E1000_FLASH_BASE_ADDR;
 879         }
 880
 881         /* Do Shared Code initialization */
 882         error = e1000_setup_init_funcs(hw, TRUE);
 883         if (error) {
 884                 device_printf(dev, "Setup of Shared code failed, error %d\n",
 885                     error);
 886                 error = ENXIO;
 887                 goto err_pci;
 888         }
 889
 890         em_setup_msix(ctx);
 891         e1000_get_bus_info(hw);
 892
 893         /* Set up some sysctls for the tunable interrupt delays */
 894         em_add_int_delay_sysctl(adapter, "rx_int_delay",
 895             "receive interrupt delay in usecs", &adapter->rx_int_delay,
 896             E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
 897         em_add_int_delay_sysctl(adapter, "tx_int_delay",
 898             "transmit interrupt delay in usecs", &adapter->tx_int_delay,
 899             E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
 900         em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
 901             "receive interrupt delay limit in usecs",
 902             &adapter->rx_abs_int_delay,
 903             E1000_REGISTER(hw, E1000_RADV),
 904             em_rx_abs_int_delay_dflt);
 905         em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
 906             "transmit interrupt delay limit in usecs",
 907             &adapter->tx_abs_int_delay,
 908             E1000_REGISTER(hw, E1000_TADV),
 909             em_tx_abs_int_delay_dflt);
 910         em_add_int_delay_sysctl(adapter, "itr",
 911             "interrupt delay limit in usecs/4",
 912             &adapter->tx_itr,
 913             E1000_REGISTER(hw, E1000_ITR),
 914             DEFAULT_ITR);
 915
 916         hw->mac.autoneg = DO_AUTO_NEG;
 917         hw->phy.autoneg_wait_to_complete = FALSE;
 918         hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 919
 920         if (adapter->hw.mac.type < em_mac_min) {
 921                 e1000_init_script_state_82541(&adapter->hw, TRUE);
 922                 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
 923         }
 924         /* Copper options */
 925         if (hw->phy.media_type == e1000_media_type_copper) {
 926                 hw->phy.mdix = AUTO_ALL_MODES;
 927                 hw->phy.disable_polarity_correction = FALSE;
 928                 hw->phy.ms_type = EM_MASTER_SLAVE;
 929         }
 930
 931         /*
 932          * Set the frame limits assuming
 933          * standard ethernet sized frames.
 934          */
 935         scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
 936             ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
 937
 938         /*
 939          * This controls when hardware reports transmit completion
 940          * status.
 941          */
 942         hw->mac.report_tx_early = 1;
 943
 944         /* Allocate multicast array memory. */
 945         adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN *
 946             MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
 947         if (adapter->mta == NULL) {
 948                 device_printf(dev, "Can not allocate multicast setup array\n");
 949                 error = ENOMEM;
 950                 goto err_late;
 951         }
 952
 953         /* Check SOL/IDER usage */
 954         if (e1000_check_reset_block(hw))
 955                 device_printf(dev, "PHY reset is blocked"
 956                               " due to SOL/IDER session.\n");
 957
 958         /* Sysctl for setting Energy Efficient Ethernet */
 959         hw->dev_spec.ich8lan.eee_disable = eee_setting;
 960         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 961             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 962             OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW,
 963             adapter, 0, em_sysctl_eee, "I",
 964             "Disable Energy Efficient Ethernet");
 965
 966         /*
 967         ** Start from a known state, this is
 968         ** important in reading the nvm and
 969         ** mac from that.
 970         */
 971         e1000_reset_hw(hw);
 972
 973         /* Make sure we have a good EEPROM before we read from it */
 974         if (e1000_validate_nvm_checksum(hw) < 0) {
 975                 /*
 976                 ** Some PCI-E parts fail the first check due to
 977                 ** the link being in sleep state, call it again,
 978                 ** if it fails a second time its a real issue.
 979                 */
 980                 if (e1000_validate_nvm_checksum(hw) < 0) {
 981                         device_printf(dev,
 982                             "The EEPROM Checksum Is Not Valid\n");
 983                         error = EIO;
 984                         goto err_late;
 985                 }
 986         }
 987
 988         /* Copy the permanent MAC address out of the EEPROM */
 989         if (e1000_read_mac_addr(hw) < 0) {
 990                 device_printf(dev, "EEPROM read error while reading MAC"
 991                               " address\n");
 992                 error = EIO;
 993                 goto err_late;
 994         }
 995
 996         if (!em_is_valid_ether_addr(hw->mac.addr)) {
 997                 device_printf(dev, "Invalid MAC address\n");
 998                 error = EIO;
 999                 goto err_late;
1000         }
1001
1002         /* Disable ULP support */
1003         e1000_disable_ulp_lpt_lp(hw, TRUE);
1004
1005         /*
1006          * Get Wake-on-Lan and Management info for later use
1007          */
1008         em_get_wakeup(ctx);
1009
1010         iflib_set_mac(ctx, hw->mac.addr);
1011
1012         return (0);
1013
1014 err_late:
1015         em_release_hw_control(adapter);
1016 err_pci:
1017         em_free_pci_resources(ctx);
1018         free(adapter->mta, M_DEVBUF);
1019
1020         return (error);
1021 }
1022
1023 static int
1024 em_if_attach_post(if_ctx_t ctx)
1025 {
1026         struct adapter *adapter = iflib_get_softc(ctx);
1027         struct e1000_hw *hw = &adapter->hw;
1028         int error = 0;
1029
1030         /* Setup OS specific network interface */
1031         error = em_setup_interface(ctx);
1032         if (error != 0) {
1033                 goto err_late;
1034         }
1035
1036         em_reset(ctx);
1037
1038         /* Initialize statistics */
1039         em_update_stats_counters(adapter);
1040         hw->mac.get_link_status = 1;
1041         em_if_update_admin_status(ctx);
1042         em_add_hw_stats(adapter);
1043
1044         /* Non-AMT based hardware can now take control from firmware */
1045         if (adapter->has_manage && !adapter->has_amt)
1046                 em_get_hw_control(adapter);
1047
1048         INIT_DEBUGOUT("em_if_attach_post: end");
1049
1050         return (error);
1051
1052 err_late:
1053         em_release_hw_control(adapter);
1054         em_free_pci_resources(ctx);
1055         em_if_queues_free(ctx);
1056         free(adapter->mta, M_DEVBUF);
1057
1058         return (error);
1059 }
1060
1061 /*********************************************************************
1062  *  Device removal routine
1063  *
1064  *  The detach entry point is called when the driver is being removed.
1065  *  This routine stops the adapter and deallocates all the resources
1066  *  that were allocated for driver operation.
1067  *
1068  *  return 0 on success, positive on failure
1069  *********************************************************************/
1070
1071 static int
1072 em_if_detach(if_ctx_t ctx)
1073 {
1074         struct adapter  *adapter = iflib_get_softc(ctx);
1075
1076         INIT_DEBUGOUT("em_detach: begin");
1077
1078         e1000_phy_hw_reset(&adapter->hw);
1079
1080         em_release_manageability(adapter);
1081         em_release_hw_control(adapter);
1082         em_free_pci_resources(ctx);
1083
1084         return (0);
1085 }
1086
1087 /*********************************************************************
1088  *
1089  *  Shutdown entry point
1090  *
1091  **********************************************************************/
1092
1093 static int
1094 em_if_shutdown(if_ctx_t ctx)
1095 {
1096         return em_if_suspend(ctx);
1097 }
1098
1099 /*
1100  * Suspend/resume device methods.
1101  */
1102 static int
1103 em_if_suspend(if_ctx_t ctx)
1104 {
1105         struct adapter *adapter = iflib_get_softc(ctx);
1106
1107         em_release_manageability(adapter);
1108         em_release_hw_control(adapter);
1109         em_enable_wakeup(ctx);
1110         return (0);
1111 }
1112
1113 static int
1114 em_if_resume(if_ctx_t ctx)
1115 {
1116         struct adapter *adapter = iflib_get_softc(ctx);
1117
1118         if (adapter->hw.mac.type == e1000_pch2lan)
1119                 e1000_resume_workarounds_pchlan(&adapter->hw);
1120         em_if_init(ctx);
1121         em_init_manageability(adapter);
1122
1123         return(0);
1124 }
1125
1126 static int
1127 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1128 {
1129         int max_frame_size;
1130         struct adapter *adapter = iflib_get_softc(ctx);
1131         if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1132
1133          IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1134
1135         switch (adapter->hw.mac.type) {
1136         case e1000_82571:
1137         case e1000_82572:
1138         case e1000_ich9lan:
1139         case e1000_ich10lan:
1140         case e1000_pch2lan:
1141         case e1000_pch_lpt:
1142         case e1000_pch_spt:
1143         case e1000_pch_cnp:
1144         case e1000_82574:
1145         case e1000_82583:
1146         case e1000_80003es2lan:
1147                 /* 9K Jumbo Frame size */
1148                 max_frame_size = 9234;
1149                 break;
1150         case e1000_pchlan:
1151                 max_frame_size = 4096;
1152                 break;
1153         case e1000_82542:
1154         case e1000_ich8lan:
1155                 /* Adapters that do not support jumbo frames */
1156                 max_frame_size = ETHER_MAX_LEN;
1157                 break;
1158         default:
1159                 if (adapter->hw.mac.type >= igb_mac_min)
1160                         max_frame_size = 9234;
1161                 else /* lem */
1162                         max_frame_size = MAX_JUMBO_FRAME_SIZE;
1163         }
1164         if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1165                 return (EINVAL);
1166         }
1167
1168         scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
1169             mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1170         return (0);
1171 }
1172
1173 /*********************************************************************
1174  *  Init entry point
1175  *
1176  *  This routine is used in two ways. It is used by the stack as
1177  *  init entry point in network interface structure. It is also used
1178  *  by the driver as a hw/sw initialization routine to get to a
1179  *  consistent state.
1180  *
1181  *  return 0 on success, positive on failure
1182  **********************************************************************/
1183
1184 static void
1185 em_if_init(if_ctx_t ctx)
1186 {
1187         struct adapter *adapter = iflib_get_softc(ctx);
1188         struct ifnet *ifp = iflib_get_ifp(ctx);
1189         struct em_tx_queue *tx_que;
1190         int i;
1191         INIT_DEBUGOUT("em_if_init: begin");
1192
1193         /* Get the latest mac address, User can use a LAA */
1194         bcopy(if_getlladdr(ifp), adapter->hw.mac.addr,
1195             ETHER_ADDR_LEN);
1196
1197         /* Put the address into the Receive Address Array */
1198         e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1199
1200         /*
1201          * With the 82571 adapter, RAR[0] may be overwritten
1202          * when the other port is reset, we make a duplicate
1203          * in RAR[14] for that eventuality, this assures
1204          * the interface continues to function.
1205          */
1206         if (adapter->hw.mac.type == e1000_82571) {
1207                 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1208                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1209                     E1000_RAR_ENTRIES - 1);
1210         }
1211
1212
1213         /* Initialize the hardware */
1214         em_reset(ctx);
1215         em_if_update_admin_status(ctx);
1216
1217         for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) {
1218                 struct tx_ring *txr = &tx_que->txr;
1219
1220                 txr->tx_rs_cidx = txr->tx_rs_pidx = txr->tx_cidx_processed = 0;
1221         }
1222
1223         /* Setup VLAN support, basic and offload if available */
1224         E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1225
1226         /* Clear bad data from Rx FIFOs */
1227         if (adapter->hw.mac.type >= igb_mac_min)
1228                 e1000_rx_fifo_flush_82575(&adapter->hw);
1229
1230         /* Configure for OS presence */
1231         em_init_manageability(adapter);
1232
1233         /* Prepare transmit descriptors and buffers */
1234         em_initialize_transmit_unit(ctx);
1235
1236         /* Setup Multicast table */
1237         em_if_multi_set(ctx);
1238
1239         /*
1240          * Figure out the desired mbuf
1241          * pool for doing jumbos
1242          */
1243         if (adapter->hw.mac.max_frame_size <= 2048)
1244                 adapter->rx_mbuf_sz = MCLBYTES;
1245 #ifndef CONTIGMALLOC_WORKS
1246         else
1247                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
1248 #else
1249         else if (adapter->hw.mac.max_frame_size <= 4096)
1250                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
1251         else
1252                 adapter->rx_mbuf_sz = MJUM9BYTES;
1253 #endif
1254         em_initialize_receive_unit(ctx);
1255
1256         /* Use real VLAN Filter support? */
1257         if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1258                 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
1259                         /* Use real VLAN Filter support */
1260                         em_setup_vlan_hw_support(adapter);
1261                 else {
1262                         u32 ctrl;
1263                         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1264                         ctrl |= E1000_CTRL_VME;
1265                         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1266                 }
1267         }
1268
1269         /* Don't lose promiscuous settings */
1270         em_if_set_promisc(ctx, IFF_PROMISC);
1271         e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1272
1273         /* MSI/X configuration for 82574 */
1274         if (adapter->hw.mac.type == e1000_82574) {
1275                 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1276
1277                 tmp |= E1000_CTRL_EXT_PBA_CLR;
1278                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1279                 /* Set the IVAR - interrupt vector routing. */
1280                 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars);
1281         } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1282                 igb_configure_queues(adapter);
1283
1284         /* this clears any pending interrupts */
1285         E1000_READ_REG(&adapter->hw, E1000_ICR);
1286         E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC);
1287
1288         /* AMT based hardware can now take control from firmware */
1289         if (adapter->has_manage && adapter->has_amt)
1290                 em_get_hw_control(adapter);
1291
1292         /* Set Energy Efficient Ethernet */
1293         if (adapter->hw.mac.type >= igb_mac_min &&
1294             adapter->hw.phy.media_type == e1000_media_type_copper) {
1295                 if (adapter->hw.mac.type == e1000_i354)
1296                         e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
1297                 else
1298                         e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
1299         }
1300 }
1301
1302 /*********************************************************************
1303  *
1304  *  Fast Legacy/MSI Combined Interrupt Service routine
1305  *
1306  *********************************************************************/
1307 int
1308 em_intr(void *arg)
1309 {
1310         struct adapter *adapter = arg;
1311         if_ctx_t ctx = adapter->ctx;
1312         u32 reg_icr;
1313
1314         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1315
1316         if (adapter->intr_type != IFLIB_INTR_LEGACY)
1317                 goto skip_stray;
1318         /* Hot eject? */
1319         if (reg_icr == 0xffffffff)
1320                 return FILTER_STRAY;
1321
1322         /* Definitely not our interrupt. */
1323         if (reg_icr == 0x0)
1324                 return FILTER_STRAY;
1325
1326         /*
1327          * Starting with the 82571 chip, bit 31 should be used to
1328          * determine whether the interrupt belongs to us.
1329          */
1330         if (adapter->hw.mac.type >= e1000_82571 &&
1331             (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1332                 return FILTER_STRAY;
1333
1334 skip_stray:
1335         /* Link status change */
1336         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1337                 adapter->hw.mac.get_link_status = 1;
1338                 iflib_admin_intr_deferred(ctx);
1339         }
1340
1341         if (reg_icr & E1000_ICR_RXO)
1342                 adapter->rx_overruns++;
1343
1344         return (FILTER_SCHEDULE_THREAD);
1345 }
1346
1347 static void
1348 igb_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq)
1349 {
1350         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims);
1351 }
1352
1353 static void
1354 em_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq)
1355 {
1356         E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims);
1357 }
1358
1359 static void
1360 igb_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq)
1361 {
1362         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims);
1363 }
1364
1365 static void
1366 em_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq)
1367 {
1368         E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims);
1369 }
1370
1371 static int
1372 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1373 {
1374         struct adapter *adapter = iflib_get_softc(ctx);
1375         struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1376
1377         if (adapter->hw.mac.type >= igb_mac_min)
1378                 igb_rx_enable_queue(adapter, rxq);
1379         else
1380                 em_rx_enable_queue(adapter, rxq);
1381         return (0);
1382 }
1383
1384 static int
1385 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1386 {
1387         struct adapter *adapter = iflib_get_softc(ctx);
1388         struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1389
1390         if (adapter->hw.mac.type >= igb_mac_min)
1391                 igb_tx_enable_queue(adapter, txq);
1392         else
1393                 em_tx_enable_queue(adapter, txq);
1394         return (0);
1395 }
1396
1397 /*********************************************************************
1398  *
1399  *  MSIX RX Interrupt Service routine
1400  *
1401  **********************************************************************/
1402 static int
1403 em_msix_que(void *arg)
1404 {
1405         struct em_rx_queue *que = arg;
1406
1407         ++que->irqs;
1408
1409         return (FILTER_SCHEDULE_THREAD);
1410 }
1411
1412 /*********************************************************************
1413  *
1414  *  MSIX Link Fast Interrupt Service routine
1415  *
1416  **********************************************************************/
1417 static int
1418 em_msix_link(void *arg)
1419 {
1420         struct adapter *adapter = arg;
1421         u32 reg_icr;
1422
1423         ++adapter->link_irq;
1424         MPASS(adapter->hw.back != NULL);
1425         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1426
1427         if (reg_icr & E1000_ICR_RXO)
1428                 adapter->rx_overruns++;
1429
1430         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1431                 em_handle_link(adapter->ctx);
1432         } else {
1433                 E1000_WRITE_REG(&adapter->hw, E1000_IMS,
1434                                 EM_MSIX_LINK | E1000_IMS_LSC);
1435                 if (adapter->hw.mac.type >= igb_mac_min)
1436                         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1437         }
1438
1439         /*
1440          * Because we must read the ICR for this interrupt
1441          * it may clear other causes using autoclear, for
1442          * this reason we simply create a soft interrupt
1443          * for all these vectors.
1444          */
1445         if (reg_icr && adapter->hw.mac.type < igb_mac_min) {
1446                 E1000_WRITE_REG(&adapter->hw,
1447                         E1000_ICS, adapter->ims);
1448         }
1449
1450         return (FILTER_HANDLED);
1451 }
1452
1453 static void
1454 em_handle_link(void *context)
1455 {
1456         if_ctx_t ctx = context;
1457         struct adapter *adapter = iflib_get_softc(ctx);
1458
1459         adapter->hw.mac.get_link_status = 1;
1460         iflib_admin_intr_deferred(ctx);
1461 }
1462
1463
1464 /*********************************************************************
1465  *
1466  *  Media Ioctl callback
1467  *
1468  *  This routine is called whenever the user queries the status of
1469  *  the interface using ifconfig.
1470  *
1471  **********************************************************************/
1472 static void
1473 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1474 {
1475         struct adapter *adapter = iflib_get_softc(ctx);
1476         u_char fiber_type = IFM_1000_SX;
1477
1478         INIT_DEBUGOUT("em_if_media_status: begin");
1479
1480         iflib_admin_intr_deferred(ctx);
1481
1482         ifmr->ifm_status = IFM_AVALID;
1483         ifmr->ifm_active = IFM_ETHER;
1484
1485         if (!adapter->link_active) {
1486                 return;
1487         }
1488
1489         ifmr->ifm_status |= IFM_ACTIVE;
1490
1491         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
1492             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1493                 if (adapter->hw.mac.type == e1000_82545)
1494                         fiber_type = IFM_1000_LX;
1495                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1496         } else {
1497                 switch (adapter->link_speed) {
1498                 case 10:
1499                         ifmr->ifm_active |= IFM_10_T;
1500                         break;
1501                 case 100:
1502                         ifmr->ifm_active |= IFM_100_TX;
1503                         break;
1504                 case 1000:
1505                         ifmr->ifm_active |= IFM_1000_T;
1506                         break;
1507                 }
1508                 if (adapter->link_duplex == FULL_DUPLEX)
1509                         ifmr->ifm_active |= IFM_FDX;
1510                 else
1511                         ifmr->ifm_active |= IFM_HDX;
1512         }
1513 }
1514
1515 /*********************************************************************
1516  *
1517  *  Media Ioctl callback
1518  *
1519  *  This routine is called when the user changes speed/duplex using
1520  *  media/mediopt option with ifconfig.
1521  *
1522  **********************************************************************/
1523 static int
1524 em_if_media_change(if_ctx_t ctx)
1525 {
1526         struct adapter *adapter = iflib_get_softc(ctx);
1527         struct ifmedia *ifm = iflib_get_media(ctx);
1528
1529         INIT_DEBUGOUT("em_if_media_change: begin");
1530
1531         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1532                 return (EINVAL);
1533
1534         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1535         case IFM_AUTO:
1536                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1537                 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1538                 break;
1539         case IFM_1000_LX:
1540         case IFM_1000_SX:
1541         case IFM_1000_T:
1542                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1543                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1544                 break;
1545         case IFM_100_TX:
1546                 adapter->hw.mac.autoneg = FALSE;
1547                 adapter->hw.phy.autoneg_advertised = 0;
1548                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1549                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1550                 else
1551                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1552                 break;
1553         case IFM_10_T:
1554                 adapter->hw.mac.autoneg = FALSE;
1555                 adapter->hw.phy.autoneg_advertised = 0;
1556                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1557                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1558                 else
1559                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1560                 break;
1561         default:
1562                 device_printf(adapter->dev, "Unsupported media type\n");
1563         }
1564
1565         em_if_init(ctx);
1566
1567         return (0);
1568 }
1569
1570 static int
1571 em_if_set_promisc(if_ctx_t ctx, int flags)
1572 {
1573         struct adapter *adapter = iflib_get_softc(ctx);
1574         u32 reg_rctl;
1575
1576         em_disable_promisc(ctx);
1577
1578         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1579
1580         if (flags & IFF_PROMISC) {
1581                 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1582                 /* Turn this on if you want to see bad packets */
1583                 if (em_debug_sbp)
1584                         reg_rctl |= E1000_RCTL_SBP;
1585                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1586         } else if (flags & IFF_ALLMULTI) {
1587                 reg_rctl |= E1000_RCTL_MPE;
1588                 reg_rctl &= ~E1000_RCTL_UPE;
1589                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1590         }
1591         return (0);
1592 }
1593
1594 static void
1595 em_disable_promisc(if_ctx_t ctx)
1596 {
1597         struct adapter *adapter = iflib_get_softc(ctx);
1598         struct ifnet *ifp = iflib_get_ifp(ctx);
1599         u32 reg_rctl;
1600         int mcnt = 0;
1601
1602         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1603         reg_rctl &= (~E1000_RCTL_UPE);
1604         if (if_getflags(ifp) & IFF_ALLMULTI)
1605                 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1606         else
1607                 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES);
1608         /* Don't disable if in MAX groups */
1609         if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1610                 reg_rctl &=  (~E1000_RCTL_MPE);
1611         reg_rctl &=  (~E1000_RCTL_SBP);
1612         E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1613 }
1614
1615
1616 /*********************************************************************
1617  *  Multicast Update
1618  *
1619  *  This routine is called whenever multicast address list is updated.
1620  *
1621  **********************************************************************/
1622
1623 static void
1624 em_if_multi_set(if_ctx_t ctx)
1625 {
1626         struct adapter *adapter = iflib_get_softc(ctx);
1627         struct ifnet *ifp = iflib_get_ifp(ctx);
1628         u32 reg_rctl = 0;
1629         u8  *mta; /* Multicast array memory */
1630         int mcnt = 0;
1631
1632         IOCTL_DEBUGOUT("em_set_multi: begin");
1633
1634         mta = adapter->mta;
1635         bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1636
1637         if (adapter->hw.mac.type == e1000_82542 &&
1638             adapter->hw.revision_id == E1000_REVISION_2) {
1639                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1640                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1641                         e1000_pci_clear_mwi(&adapter->hw);
1642                 reg_rctl |= E1000_RCTL_RST;
1643                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1644                 msec_delay(5);
1645         }
1646
1647         if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES);
1648
1649         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1650                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1651                 reg_rctl |= E1000_RCTL_MPE;
1652                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1653         } else
1654                 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
1655
1656         if (adapter->hw.mac.type == e1000_82542 &&
1657             adapter->hw.revision_id == E1000_REVISION_2) {
1658                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1659                 reg_rctl &= ~E1000_RCTL_RST;
1660                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1661                 msec_delay(5);
1662                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1663                         e1000_pci_set_mwi(&adapter->hw);
1664         }
1665 }
1666
1667
1668 /*********************************************************************
1669  *  Timer routine
1670  *
1671  *  This routine checks for link status and updates statistics.
1672  *
1673  **********************************************************************/
1674
1675 static void
1676 em_if_timer(if_ctx_t ctx, uint16_t qid)
1677 {
1678         struct adapter *adapter = iflib_get_softc(ctx);
1679         struct em_rx_queue *que;
1680         int i;
1681         int trigger = 0;
1682
1683         if (qid != 0)
1684                 return;
1685
1686         iflib_admin_intr_deferred(ctx);
1687
1688         /* Mask to use in the irq trigger */
1689         if (adapter->intr_type == IFLIB_INTR_MSIX) {
1690                 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++)
1691                         trigger |= que->eims;
1692         } else {
1693                 trigger = E1000_ICS_RXDMT0;
1694         }
1695 }
1696
1697
1698 static void
1699 em_if_update_admin_status(if_ctx_t ctx)
1700 {
1701         struct adapter *adapter = iflib_get_softc(ctx);
1702         struct e1000_hw *hw = &adapter->hw;
1703         struct ifnet *ifp = iflib_get_ifp(ctx);
1704         device_t dev = iflib_get_dev(ctx);
1705         u32 link_check, thstat, ctrl;
1706
1707         link_check = thstat = ctrl = 0;
1708         /* Get the cached link value or read phy for real */
1709         switch (hw->phy.media_type) {
1710         case e1000_media_type_copper:
1711                 if (hw->mac.get_link_status) {
1712                         if (hw->mac.type == e1000_pch_spt)
1713                                 msec_delay(50);
1714                         /* Do the work to read phy */
1715                         e1000_check_for_link(hw);
1716                         link_check = !hw->mac.get_link_status;
1717                         if (link_check) /* ESB2 fix */
1718                                 e1000_cfg_on_link_up(hw);
1719                 } else {
1720                         link_check = TRUE;
1721                 }
1722                 break;
1723         case e1000_media_type_fiber:
1724                 e1000_check_for_link(hw);
1725                 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1726                             E1000_STATUS_LU);
1727                 break;
1728         case e1000_media_type_internal_serdes:
1729                 e1000_check_for_link(hw);
1730                 link_check = adapter->hw.mac.serdes_has_link;
1731                 break;
1732         /* VF device is type_unknown */
1733         case e1000_media_type_unknown:
1734                 e1000_check_for_link(hw);
1735                 link_check = !hw->mac.get_link_status;
1736                 /* FALLTHROUGH */
1737         default:
1738                 break;
1739         }
1740
1741         /* Check for thermal downshift or shutdown */
1742         if (hw->mac.type == e1000_i350) {
1743                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1744                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1745         }
1746
1747         /* Now check for a transition */
1748         if (link_check && (adapter->link_active == 0)) {
1749                 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
1750                     &adapter->link_duplex);
1751                 /* Check if we must disable SPEED_MODE bit on PCI-E */
1752                 if ((adapter->link_speed != SPEED_1000) &&
1753                     ((hw->mac.type == e1000_82571) ||
1754                     (hw->mac.type == e1000_82572))) {
1755                         int tarc0;
1756                         tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1757                         tarc0 &= ~TARC_SPEED_MODE_BIT;
1758                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1759                 }
1760                 if (bootverbose)
1761                         device_printf(dev, "Link is up %d Mbps %s\n",
1762                             adapter->link_speed,
1763                             ((adapter->link_duplex == FULL_DUPLEX) ?
1764                             "Full Duplex" : "Half Duplex"));
1765                 adapter->link_active = 1;
1766                 adapter->smartspeed = 0;
1767                 if_setbaudrate(ifp, adapter->link_speed * 1000000);
1768                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1769                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1770                         device_printf(dev, "Link: thermal downshift\n");
1771                 /* Delay Link Up for Phy update */
1772                 if (((hw->mac.type == e1000_i210) ||
1773                     (hw->mac.type == e1000_i211)) &&
1774                     (hw->phy.id == I210_I_PHY_ID))
1775                         msec_delay(I210_LINK_DELAY);
1776                 /* Reset if the media type changed. */
1777                 if ((hw->dev_spec._82575.media_changed) &&
1778                         (adapter->hw.mac.type >= igb_mac_min)) {
1779                         hw->dev_spec._82575.media_changed = false;
1780                         adapter->flags |= IGB_MEDIA_RESET;
1781                         em_reset(ctx);
1782                 }
1783                 iflib_link_state_change(ctx, LINK_STATE_UP, ifp->if_baudrate);
1784                 printf("Link state changed to up\n");
1785         } else if (!link_check && (adapter->link_active == 1)) {
1786                 if_setbaudrate(ifp, 0);
1787                 adapter->link_speed = 0;
1788                 adapter->link_duplex = 0;
1789                 if (bootverbose)
1790                         device_printf(dev, "Link is Down\n");
1791                 adapter->link_active = 0;
1792                 iflib_link_state_change(ctx, LINK_STATE_DOWN, ifp->if_baudrate);
1793                 printf("link state changed to down\n");
1794         }
1795         em_update_stats_counters(adapter);
1796
1797         /* Reset LAA into RAR[0] on 82571 */
1798         if ((adapter->hw.mac.type == e1000_82571) &&
1799             e1000_get_laa_state_82571(&adapter->hw))
1800                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1801
1802         if (adapter->hw.mac.type < em_mac_min)
1803                 lem_smartspeed(adapter);
1804
1805         E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC);
1806 }
1807
1808 /*********************************************************************
1809  *
1810  *  This routine disables all traffic on the adapter by issuing a
1811  *  global reset on the MAC and deallocates TX/RX buffers.
1812  *
1813  *  This routine should always be called with BOTH the CORE
1814  *  and TX locks.
1815  **********************************************************************/
1816
1817 static void
1818 em_if_stop(if_ctx_t ctx)
1819 {
1820         struct adapter *adapter = iflib_get_softc(ctx);
1821
1822         INIT_DEBUGOUT("em_stop: begin");
1823
1824         e1000_reset_hw(&adapter->hw);
1825         if (adapter->hw.mac.type >= e1000_82544)
1826                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0);
1827
1828         e1000_led_off(&adapter->hw);
1829         e1000_cleanup_led(&adapter->hw);
1830 }
1831
1832
1833 /*********************************************************************
1834  *
1835  *  Determine hardware revision.
1836  *
1837  **********************************************************************/
1838 static void
1839 em_identify_hardware(if_ctx_t ctx)
1840 {
1841         device_t dev = iflib_get_dev(ctx);
1842         struct adapter *adapter = iflib_get_softc(ctx);
1843
1844         /* Make sure our PCI config space has the necessary stuff set */
1845         adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1846
1847         /* Save off the information about this board */
1848         adapter->hw.vendor_id = pci_get_vendor(dev);
1849         adapter->hw.device_id = pci_get_device(dev);
1850         adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1851         adapter->hw.subsystem_vendor_id =
1852             pci_read_config(dev, PCIR_SUBVEND_0, 2);
1853         adapter->hw.subsystem_device_id =
1854             pci_read_config(dev, PCIR_SUBDEV_0, 2);
1855
1856         /* Do Shared Code Init and Setup */
1857         if (e1000_set_mac_type(&adapter->hw)) {
1858                 device_printf(dev, "Setup init failure\n");
1859                 return;
1860         }
1861 }
1862
1863 static int
1864 em_allocate_pci_resources(if_ctx_t ctx)
1865 {
1866         struct adapter *adapter = iflib_get_softc(ctx);
1867         device_t dev = iflib_get_dev(ctx);
1868         int rid, val;
1869
1870         rid = PCIR_BAR(0);
1871         adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1872             &rid, RF_ACTIVE);
1873         if (adapter->memory == NULL) {
1874                 device_printf(dev, "Unable to allocate bus resource: memory\n");
1875                 return (ENXIO);
1876         }
1877         adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory);
1878         adapter->osdep.mem_bus_space_handle =
1879             rman_get_bushandle(adapter->memory);
1880         adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle;
1881
1882         /* Only older adapters use IO mapping */
1883         if (adapter->hw.mac.type < em_mac_min &&
1884             adapter->hw.mac.type > e1000_82543) {
1885                 /* Figure our where our IO BAR is ? */
1886                 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1887                         val = pci_read_config(dev, rid, 4);
1888                         if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1889                                 adapter->io_rid = rid;
1890                                 break;
1891                         }
1892                         rid += 4;
1893                         /* check for 64bit BAR */
1894                         if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1895                                 rid += 4;
1896                 }
1897                 if (rid >= PCIR_CIS) {
1898                         device_printf(dev, "Unable to locate IO BAR\n");
1899                         return (ENXIO);
1900                 }
1901                 adapter->ioport = bus_alloc_resource_any(dev,
1902                     SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE);
1903                 if (adapter->ioport == NULL) {
1904                         device_printf(dev, "Unable to allocate bus resource: "
1905                             "ioport\n");
1906                         return (ENXIO);
1907                 }
1908                 adapter->hw.io_base = 0;
1909                 adapter->osdep.io_bus_space_tag =
1910                     rman_get_bustag(adapter->ioport);
1911                 adapter->osdep.io_bus_space_handle =
1912                     rman_get_bushandle(adapter->ioport);
1913         }
1914
1915         adapter->hw.back = &adapter->osdep;
1916
1917         return (0);
1918 }
1919
1920 /*********************************************************************
1921  *
1922  *  Setup the MSIX Interrupt handlers
1923  *
1924  **********************************************************************/
1925 static int
1926 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
1927 {
1928         struct adapter *adapter = iflib_get_softc(ctx);
1929         struct em_rx_queue *rx_que = adapter->rx_queues;
1930         struct em_tx_queue *tx_que = adapter->tx_queues;
1931         int error, rid, i, vector = 0, rx_vectors;
1932         char buf[16];
1933
1934         /* First set up ring resources */
1935         for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) {
1936                 rid = vector + 1;
1937                 snprintf(buf, sizeof(buf), "rxq%d", i);
1938                 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
1939                 if (error) {
1940                         device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
1941                         adapter->rx_num_queues = i + 1;
1942                         goto fail;
1943                 }
1944
1945                 rx_que->msix =  vector;
1946
1947                 /*
1948                  * Set the bit to enable interrupt
1949                  * in E1000_IMS -- bits 20 and 21
1950                  * are for RX0 and RX1, note this has
1951                  * NOTHING to do with the MSIX vector
1952                  */
1953                 if (adapter->hw.mac.type == e1000_82574) {
1954                         rx_que->eims = 1 << (20 + i);
1955                         adapter->ims |= rx_que->eims;
1956                         adapter->ivars |= (8 | rx_que->msix) << (i * 4);
1957                 } else if (adapter->hw.mac.type == e1000_82575)
1958                         rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
1959                 else
1960                         rx_que->eims = 1 << vector;
1961         }
1962         rx_vectors = vector;
1963
1964         vector = 0;
1965         for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) {
1966                 rid = vector + 1;
1967                 snprintf(buf, sizeof(buf), "txq%d", i);
1968                 tx_que = &adapter->tx_queues[i];
1969                 iflib_softirq_alloc_generic(ctx,
1970                     &adapter->rx_queues[i % adapter->rx_num_queues].que_irq,
1971                     IFLIB_INTR_TX, tx_que, tx_que->me, buf);
1972
1973                 tx_que->msix = (vector % adapter->tx_num_queues);
1974
1975                 /*
1976                  * Set the bit to enable interrupt
1977                  * in E1000_IMS -- bits 22 and 23
1978                  * are for TX0 and TX1, note this has
1979                  * NOTHING to do with the MSIX vector
1980                  */
1981                 if (adapter->hw.mac.type == e1000_82574) {
1982                         tx_que->eims = 1 << (22 + i);
1983                         adapter->ims |= tx_que->eims;
1984                         adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
1985                 } else if (adapter->hw.mac.type == e1000_82575) {
1986                         tx_que->eims = E1000_EICR_TX_QUEUE0 << (i %  adapter->tx_num_queues);
1987                 } else {
1988                         tx_que->eims = 1 << (i %  adapter->tx_num_queues);
1989                 }
1990         }
1991
1992         /* Link interrupt */
1993         rid = rx_vectors + 1;
1994         error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq");
1995
1996         if (error) {
1997                 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
1998                 goto fail;
1999         }
2000         adapter->linkvec = rx_vectors;
2001         if (adapter->hw.mac.type < igb_mac_min) {
2002                 adapter->ivars |=  (8 | rx_vectors) << 16;
2003                 adapter->ivars |= 0x80000000;
2004         }
2005         return (0);
2006 fail:
2007         iflib_irq_free(ctx, &adapter->irq);
2008         rx_que = adapter->rx_queues;
2009         for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++)
2010                 iflib_irq_free(ctx, &rx_que->que_irq);
2011         return (error);
2012 }
2013
2014 static void
2015 igb_configure_queues(struct adapter *adapter)
2016 {
2017         struct e1000_hw *hw = &adapter->hw;
2018         struct em_rx_queue *rx_que;
2019         struct em_tx_queue *tx_que;
2020         u32 tmp, ivar = 0, newitr = 0;
2021
2022         /* First turn on RSS capability */
2023         if (adapter->hw.mac.type != e1000_82575)
2024                 E1000_WRITE_REG(hw, E1000_GPIE,
2025                     E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
2026                     E1000_GPIE_PBA | E1000_GPIE_NSICR);
2027
2028         /* Turn on MSIX */
2029         switch (adapter->hw.mac.type) {
2030         case e1000_82580:
2031         case e1000_i350:
2032         case e1000_i354:
2033         case e1000_i210:
2034         case e1000_i211:
2035         case e1000_vfadapt:
2036         case e1000_vfadapt_i350:
2037                 /* RX entries */
2038                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2039                         u32 index = i >> 1;
2040                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2041                         rx_que = &adapter->rx_queues[i];
2042                         if (i & 1) {
2043                                 ivar &= 0xFF00FFFF;
2044                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2045                         } else {
2046                                 ivar &= 0xFFFFFF00;
2047                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2048                         }
2049                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2050                 }
2051                 /* TX entries */
2052                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2053                         u32 index = i >> 1;
2054                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2055                         tx_que = &adapter->tx_queues[i];
2056                         if (i & 1) {
2057                                 ivar &= 0x00FFFFFF;
2058                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2059                         } else {
2060                                 ivar &= 0xFFFF00FF;
2061                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2062                         }
2063                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2064                         adapter->que_mask |= tx_que->eims;
2065                 }
2066
2067                 /* And for the link interrupt */
2068                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2069                 adapter->link_mask = 1 << adapter->linkvec;
2070                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2071                 break;
2072         case e1000_82576:
2073                 /* RX entries */
2074                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2075                         u32 index = i & 0x7; /* Each IVAR has two entries */
2076                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2077                         rx_que = &adapter->rx_queues[i];
2078                         if (i < 8) {
2079                                 ivar &= 0xFFFFFF00;
2080                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2081                         } else {
2082                                 ivar &= 0xFF00FFFF;
2083                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2084                         }
2085                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2086                         adapter->que_mask |= rx_que->eims;
2087                 }
2088                 /* TX entries */
2089                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2090                         u32 index = i & 0x7; /* Each IVAR has two entries */
2091                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2092                         tx_que = &adapter->tx_queues[i];
2093                         if (i < 8) {
2094                                 ivar &= 0xFFFF00FF;
2095                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2096                         } else {
2097                                 ivar &= 0x00FFFFFF;
2098                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2099                         }
2100                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2101                         adapter->que_mask |= tx_que->eims;
2102                 }
2103
2104                 /* And for the link interrupt */
2105                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2106                 adapter->link_mask = 1 << adapter->linkvec;
2107                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2108                 break;
2109
2110         case e1000_82575:
2111                 /* enable MSI-X support*/
2112                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2113                 tmp |= E1000_CTRL_EXT_PBA_CLR;
2114                 /* Auto-Mask interrupts upon ICR read. */
2115                 tmp |= E1000_CTRL_EXT_EIAME;
2116                 tmp |= E1000_CTRL_EXT_IRCA;
2117                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2118
2119                 /* Queues */
2120                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2121                         rx_que = &adapter->rx_queues[i];
2122                         tmp = E1000_EICR_RX_QUEUE0 << i;
2123                         tmp |= E1000_EICR_TX_QUEUE0 << i;
2124                         rx_que->eims = tmp;
2125                         E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2126                             i, rx_que->eims);
2127                         adapter->que_mask |= rx_que->eims;
2128                 }
2129
2130                 /* Link */
2131                 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec),
2132                     E1000_EIMS_OTHER);
2133                 adapter->link_mask |= E1000_EIMS_OTHER;
2134         default:
2135                 break;
2136         }
2137
2138         /* Set the starting interrupt rate */
2139         if (em_max_interrupt_rate > 0)
2140                 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2141
2142         if (hw->mac.type == e1000_82575)
2143                 newitr |= newitr << 16;
2144         else
2145                 newitr |= E1000_EITR_CNT_IGNR;
2146
2147         for (int i = 0; i < adapter->rx_num_queues; i++) {
2148                 rx_que = &adapter->rx_queues[i];
2149                 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2150         }
2151
2152         return;
2153 }
2154
2155 static void
2156 em_free_pci_resources(if_ctx_t ctx)
2157 {
2158         struct adapter *adapter = iflib_get_softc(ctx);
2159         struct em_rx_queue *que = adapter->rx_queues;
2160         device_t dev = iflib_get_dev(ctx);
2161
2162         /* Release all msix queue resources */
2163         if (adapter->intr_type == IFLIB_INTR_MSIX)
2164                 iflib_irq_free(ctx, &adapter->irq);
2165
2166         for (int i = 0; i < adapter->rx_num_queues; i++, que++) {
2167                 iflib_irq_free(ctx, &que->que_irq);
2168         }
2169
2170         /* First release all the interrupt resources */
2171         if (adapter->memory != NULL) {
2172                 bus_release_resource(dev, SYS_RES_MEMORY,
2173                                      PCIR_BAR(0), adapter->memory);
2174                 adapter->memory = NULL;
2175         }
2176
2177         if (adapter->flash != NULL) {
2178                 bus_release_resource(dev, SYS_RES_MEMORY,
2179                                      EM_FLASH, adapter->flash);
2180                 adapter->flash = NULL;
2181         }
2182         if (adapter->ioport != NULL)
2183                 bus_release_resource(dev, SYS_RES_IOPORT,
2184                     adapter->io_rid, adapter->ioport);
2185 }
2186
2187 /* Setup MSI or MSI/X */
2188 static int
2189 em_setup_msix(if_ctx_t ctx)
2190 {
2191         struct adapter *adapter = iflib_get_softc(ctx);
2192
2193         if (adapter->hw.mac.type == e1000_82574) {
2194                 em_enable_vectors_82574(ctx);
2195         }
2196         return (0);
2197 }
2198
2199 /*********************************************************************
2200  *
2201  *  Initialize the hardware to a configuration
2202  *  as specified by the adapter structure.
2203  *
2204  **********************************************************************/
2205
2206 static void
2207 lem_smartspeed(struct adapter *adapter)
2208 {
2209         u16 phy_tmp;
2210
2211         if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) ||
2212             adapter->hw.mac.autoneg == 0 ||
2213             (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2214                 return;
2215
2216         if (adapter->smartspeed == 0) {
2217                 /* If Master/Slave config fault is asserted twice,
2218                  * we assume back-to-back */
2219                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2220                 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2221                         return;
2222                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2223                 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2224                         e1000_read_phy_reg(&adapter->hw,
2225                             PHY_1000T_CTRL, &phy_tmp);
2226                         if(phy_tmp & CR_1000T_MS_ENABLE) {
2227                                 phy_tmp &= ~CR_1000T_MS_ENABLE;
2228                                 e1000_write_phy_reg(&adapter->hw,
2229                                     PHY_1000T_CTRL, phy_tmp);
2230                                 adapter->smartspeed++;
2231                                 if(adapter->hw.mac.autoneg &&
2232                                    !e1000_copper_link_autoneg(&adapter->hw) &&
2233                                    !e1000_read_phy_reg(&adapter->hw,
2234                                     PHY_CONTROL, &phy_tmp)) {
2235                                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2236                                                     MII_CR_RESTART_AUTO_NEG);
2237                                         e1000_write_phy_reg(&adapter->hw,
2238                                             PHY_CONTROL, phy_tmp);
2239                                 }
2240                         }
2241                 }
2242                 return;
2243         } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2244                 /* If still no link, perhaps using 2/3 pair cable */
2245                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2246                 phy_tmp |= CR_1000T_MS_ENABLE;
2247                 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2248                 if(adapter->hw.mac.autoneg &&
2249                    !e1000_copper_link_autoneg(&adapter->hw) &&
2250                    !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2251                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2252                                     MII_CR_RESTART_AUTO_NEG);
2253                         e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2254                 }
2255         }
2256         /* Restart process after EM_SMARTSPEED_MAX iterations */
2257         if(adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2258                 adapter->smartspeed = 0;
2259 }
2260
2261 /*********************************************************************
2262  *
2263  *  Initialize the DMA Coalescing feature
2264  *
2265  **********************************************************************/
2266 static void
2267 igb_init_dmac(struct adapter *adapter, u32 pba)
2268 {
2269         device_t        dev = adapter->dev;
2270         struct e1000_hw *hw = &adapter->hw;
2271         u32             dmac, reg = ~E1000_DMACR_DMAC_EN;
2272         u16             hwm;
2273         u16             max_frame_size;
2274
2275         if (hw->mac.type == e1000_i211)
2276                 return;
2277
2278         max_frame_size = adapter->shared->isc_max_frame_size;
2279         if (hw->mac.type > e1000_82580) {
2280
2281                 if (adapter->dmac == 0) { /* Disabling it */
2282                         E1000_WRITE_REG(hw, E1000_DMACR, reg);
2283                         return;
2284                 } else
2285                         device_printf(dev, "DMA Coalescing enabled\n");
2286
2287                 /* Set starting threshold */
2288                 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
2289
2290                 hwm = 64 * pba - max_frame_size / 16;
2291                 if (hwm < 64 * (pba - 6))
2292                         hwm = 64 * (pba - 6);
2293                 reg = E1000_READ_REG(hw, E1000_FCRTC);
2294                 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
2295                 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
2296                     & E1000_FCRTC_RTH_COAL_MASK);
2297                 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
2298
2299
2300                 dmac = pba - max_frame_size / 512;
2301                 if (dmac < pba - 10)
2302                         dmac = pba - 10;
2303                 reg = E1000_READ_REG(hw, E1000_DMACR);
2304                 reg &= ~E1000_DMACR_DMACTHR_MASK;
2305                 reg = ((dmac << E1000_DMACR_DMACTHR_SHIFT)
2306                     & E1000_DMACR_DMACTHR_MASK);
2307
2308                 /* transition to L0x or L1 if available..*/
2309                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
2310
2311                 /* Check if status is 2.5Gb backplane connection
2312                 * before configuration of watchdog timer, which is
2313                 * in msec values in 12.8usec intervals
2314                 * watchdog timer= msec values in 32usec intervals
2315                 * for non 2.5Gb connection
2316                 */
2317                 if (hw->mac.type == e1000_i354) {
2318                         int status = E1000_READ_REG(hw, E1000_STATUS);
2319                         if ((status & E1000_STATUS_2P5_SKU) &&
2320                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2321                                 reg |= ((adapter->dmac * 5) >> 6);
2322                         else
2323                                 reg |= (adapter->dmac >> 5);
2324                 } else {
2325                         reg |= (adapter->dmac >> 5);
2326                 }
2327
2328                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2329
2330                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
2331
2332                 /* Set the interval before transition */
2333                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
2334                 if (hw->mac.type == e1000_i350)
2335                         reg |= IGB_DMCTLX_DCFLUSH_DIS;
2336                 /*
2337                 ** in 2.5Gb connection, TTLX unit is 0.4 usec
2338                 ** which is 0x4*2 = 0xA. But delay is still 4 usec
2339                 */
2340                 if (hw->mac.type == e1000_i354) {
2341                         int status = E1000_READ_REG(hw, E1000_STATUS);
2342                         if ((status & E1000_STATUS_2P5_SKU) &&
2343                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2344                                 reg |= 0xA;
2345                         else
2346                                 reg |= 0x4;
2347                 } else {
2348                         reg |= 0x4;
2349                 }
2350
2351                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
2352
2353                 /* free space in tx packet buffer to wake from DMA coal */
2354                 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE -
2355                     (2 * max_frame_size)) >> 6);
2356
2357                 /* make low power state decision controlled by DMA coal */
2358                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2359                 reg &= ~E1000_PCIEMISC_LX_DECISION;
2360                 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
2361
2362         } else if (hw->mac.type == e1000_82580) {
2363                 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2364                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
2365                     reg & ~E1000_PCIEMISC_LX_DECISION);
2366                 E1000_WRITE_REG(hw, E1000_DMACR, 0);
2367         }
2368 }
2369
2370 static void
2371 em_reset(if_ctx_t ctx)
2372 {
2373         device_t dev = iflib_get_dev(ctx);
2374         struct adapter *adapter = iflib_get_softc(ctx);
2375         struct ifnet *ifp = iflib_get_ifp(ctx);
2376         struct e1000_hw *hw = &adapter->hw;
2377         u16 rx_buffer_size;
2378         u32 pba;
2379
2380         INIT_DEBUGOUT("em_reset: begin");
2381         /* Let the firmware know the OS is in control */
2382         em_get_hw_control(adapter);
2383
2384         /* Set up smart power down as default off on newer adapters. */
2385         if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2386             hw->mac.type == e1000_82572)) {
2387                 u16 phy_tmp = 0;
2388
2389                 /* Speed up time to link by disabling smart power down. */
2390                 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2391                 phy_tmp &= ~IGP02E1000_PM_SPD;
2392                 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2393         }
2394
2395         /*
2396          * Packet Buffer Allocation (PBA)
2397          * Writing PBA sets the receive portion of the buffer
2398          * the remainder is used for the transmit buffer.
2399          */
2400         switch (hw->mac.type) {
2401         /* Total Packet Buffer on these is 48K */
2402         case e1000_82571:
2403         case e1000_82572:
2404         case e1000_80003es2lan:
2405                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2406                 break;
2407         case e1000_82573: /* 82573: Total Packet Buffer is 32K */
2408                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2409                 break;
2410         case e1000_82574:
2411         case e1000_82583:
2412                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2413                 break;
2414         case e1000_ich8lan:
2415                 pba = E1000_PBA_8K;
2416                 break;
2417         case e1000_ich9lan:
2418         case e1000_ich10lan:
2419                 /* Boost Receive side for jumbo frames */
2420                 if (adapter->hw.mac.max_frame_size > 4096)
2421                         pba = E1000_PBA_14K;
2422                 else
2423                         pba = E1000_PBA_10K;
2424                 break;
2425         case e1000_pchlan:
2426         case e1000_pch2lan:
2427         case e1000_pch_lpt:
2428         case e1000_pch_spt:
2429         case e1000_pch_cnp:
2430                 pba = E1000_PBA_26K;
2431                 break;
2432         case e1000_82575:
2433                 pba = E1000_PBA_32K;
2434                 break;
2435         case e1000_82576:
2436         case e1000_vfadapt:
2437                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2438                 pba &= E1000_RXPBS_SIZE_MASK_82576;
2439                 break;
2440         case e1000_82580:
2441         case e1000_i350:
2442         case e1000_i354:
2443         case e1000_vfadapt_i350:
2444                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2445                 pba = e1000_rxpbs_adjust_82580(pba);
2446                 break;
2447         case e1000_i210:
2448         case e1000_i211:
2449                 pba = E1000_PBA_34K;
2450                 break;
2451         default:
2452                 if (adapter->hw.mac.max_frame_size > 8192)
2453                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2454                 else
2455                         pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2456         }
2457
2458         /* Special needs in case of Jumbo frames */
2459         if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) {
2460                 u32 tx_space, min_tx, min_rx;
2461                 pba = E1000_READ_REG(hw, E1000_PBA);
2462                 tx_space = pba >> 16;
2463                 pba &= 0xffff;
2464                 min_tx = (adapter->hw.mac.max_frame_size +
2465                     sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
2466                 min_tx = roundup2(min_tx, 1024);
2467                 min_tx >>= 10;
2468                 min_rx = adapter->hw.mac.max_frame_size;
2469                 min_rx = roundup2(min_rx, 1024);
2470                 min_rx >>= 10;
2471                 if (tx_space < min_tx &&
2472                     ((min_tx - tx_space) < pba)) {
2473                         pba = pba - (min_tx - tx_space);
2474                         /*
2475                          * if short on rx space, rx wins
2476                          * and must trump tx adjustment
2477                          */
2478                         if (pba < min_rx)
2479                                 pba = min_rx;
2480                 }
2481                 E1000_WRITE_REG(hw, E1000_PBA, pba);
2482         }
2483
2484         if (hw->mac.type < igb_mac_min)
2485                 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
2486
2487         INIT_DEBUGOUT1("em_reset: pba=%dK",pba);
2488
2489         /*
2490          * These parameters control the automatic generation (Tx) and
2491          * response (Rx) to Ethernet PAUSE frames.
2492          * - High water mark should allow for at least two frames to be
2493          *   received after sending an XOFF.
2494          * - Low water mark works best when it is very near the high water mark.
2495          *   This allows the receiver to restart by sending XON when it has
2496          *   drained a bit. Here we use an arbitrary value of 1500 which will
2497          *   restart after one full frame is pulled from the buffer. There
2498          *   could be several smaller frames in the buffer and if so they will
2499          *   not trigger the XON until their total number reduces the buffer
2500          *   by 1500.
2501          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2502          */
2503         rx_buffer_size = (pba & 0xffff) << 10;
2504         hw->fc.high_water = rx_buffer_size -
2505             roundup2(adapter->hw.mac.max_frame_size, 1024);
2506         hw->fc.low_water = hw->fc.high_water - 1500;
2507
2508         if (adapter->fc) /* locally set flow control value? */
2509                 hw->fc.requested_mode = adapter->fc;
2510         else
2511                 hw->fc.requested_mode = e1000_fc_full;
2512
2513         if (hw->mac.type == e1000_80003es2lan)
2514                 hw->fc.pause_time = 0xFFFF;
2515         else
2516                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
2517
2518         hw->fc.send_xon = TRUE;
2519
2520         /* Device specific overrides/settings */
2521         switch (hw->mac.type) {
2522         case e1000_pchlan:
2523                 /* Workaround: no TX flow ctrl for PCH */
2524                 hw->fc.requested_mode = e1000_fc_rx_pause;
2525                 hw->fc.pause_time = 0xFFFF; /* override */
2526                 if (if_getmtu(ifp) > ETHERMTU) {
2527                         hw->fc.high_water = 0x3500;
2528                         hw->fc.low_water = 0x1500;
2529                 } else {
2530                         hw->fc.high_water = 0x5000;
2531                         hw->fc.low_water = 0x3000;
2532                 }
2533                 hw->fc.refresh_time = 0x1000;
2534                 break;
2535         case e1000_pch2lan:
2536         case e1000_pch_lpt:
2537         case e1000_pch_spt:
2538         case e1000_pch_cnp:
2539                 hw->fc.high_water = 0x5C20;
2540                 hw->fc.low_water = 0x5048;
2541                 hw->fc.pause_time = 0x0650;
2542                 hw->fc.refresh_time = 0x0400;
2543                 /* Jumbos need adjusted PBA */
2544                 if (if_getmtu(ifp) > ETHERMTU)
2545                         E1000_WRITE_REG(hw, E1000_PBA, 12);
2546                 else
2547                         E1000_WRITE_REG(hw, E1000_PBA, 26);
2548                 break;
2549         case e1000_82575:
2550         case e1000_82576:
2551                 /* 8-byte granularity */
2552                 hw->fc.low_water = hw->fc.high_water - 8;
2553                 break;
2554         case e1000_82580:
2555         case e1000_i350:
2556         case e1000_i354:
2557         case e1000_i210:
2558         case e1000_i211:
2559         case e1000_vfadapt:
2560         case e1000_vfadapt_i350:
2561                 /* 16-byte granularity */
2562                 hw->fc.low_water = hw->fc.high_water - 16;
2563                 break;
2564         case e1000_ich9lan:
2565         case e1000_ich10lan:
2566                 if (if_getmtu(ifp) > ETHERMTU) {
2567                         hw->fc.high_water = 0x2800;
2568                         hw->fc.low_water = hw->fc.high_water - 8;
2569                         break;
2570                 }
2571                 /* FALLTHROUGH */
2572         default:
2573                 if (hw->mac.type == e1000_80003es2lan)
2574                         hw->fc.pause_time = 0xFFFF;
2575                 break;
2576         }
2577
2578         /* Issue a global reset */
2579         e1000_reset_hw(hw);
2580         if (adapter->hw.mac.type >= igb_mac_min) {
2581                 E1000_WRITE_REG(hw, E1000_WUC, 0);
2582         } else {
2583                 E1000_WRITE_REG(hw, E1000_WUFC, 0);
2584                 em_disable_aspm(adapter);
2585         }
2586         if (adapter->flags & IGB_MEDIA_RESET) {
2587                 e1000_setup_init_funcs(hw, TRUE);
2588                 e1000_get_bus_info(hw);
2589                 adapter->flags &= ~IGB_MEDIA_RESET;
2590         }
2591         /* and a re-init */
2592         if (e1000_init_hw(hw) < 0) {
2593                 device_printf(dev, "Hardware Initialization Failed\n");
2594                 return;
2595         }
2596         if (adapter->hw.mac.type >= igb_mac_min)
2597                 igb_init_dmac(adapter, pba);
2598
2599         E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2600         e1000_get_phy_info(hw);
2601         e1000_check_for_link(hw);
2602 }
2603
2604 #define RSSKEYLEN 10
2605 static void
2606 em_initialize_rss_mapping(struct adapter *adapter)
2607 {
2608         uint8_t  rss_key[4 * RSSKEYLEN];
2609         uint32_t reta = 0;
2610         struct e1000_hw *hw = &adapter->hw;
2611         int i;
2612
2613         /*
2614          * Configure RSS key
2615          */
2616         arc4rand(rss_key, sizeof(rss_key), 0);
2617         for (i = 0; i < RSSKEYLEN; ++i) {
2618                 uint32_t rssrk = 0;
2619
2620                 rssrk = EM_RSSRK_VAL(rss_key, i);
2621                 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2622         }
2623
2624         /*
2625          * Configure RSS redirect table in following fashion:
2626          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2627          */
2628         for (i = 0; i < sizeof(reta); ++i) {
2629                 uint32_t q;
2630
2631                 q = (i % adapter->rx_num_queues) << 7;
2632                 reta |= q << (8 * i);
2633         }
2634
2635         for (i = 0; i < 32; ++i)
2636                 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2637
2638         E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2639                         E1000_MRQC_RSS_FIELD_IPV4_TCP |
2640                         E1000_MRQC_RSS_FIELD_IPV4 |
2641                         E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2642                         E1000_MRQC_RSS_FIELD_IPV6_EX |
2643                         E1000_MRQC_RSS_FIELD_IPV6);
2644
2645 }
2646
2647 static void
2648 igb_initialize_rss_mapping(struct adapter *adapter)
2649 {
2650         struct e1000_hw *hw = &adapter->hw;
2651         int i;
2652         int queue_id;
2653         u32 reta;
2654         u32 rss_key[10], mrqc, shift = 0;
2655
2656         /* XXX? */
2657         if (adapter->hw.mac.type == e1000_82575)
2658                 shift = 6;
2659
2660         /*
2661          * The redirection table controls which destination
2662          * queue each bucket redirects traffic to.
2663          * Each DWORD represents four queues, with the LSB
2664          * being the first queue in the DWORD.
2665          *
2666          * This just allocates buckets to queues using round-robin
2667          * allocation.
2668          *
2669          * NOTE: It Just Happens to line up with the default
2670          * RSS allocation method.
2671          */
2672
2673         /* Warning FM follows */
2674         reta = 0;
2675         for (i = 0; i < 128; i++) {
2676 #ifdef RSS
2677                 queue_id = rss_get_indirection_to_bucket(i);
2678                 /*
2679                  * If we have more queues than buckets, we'll
2680                  * end up mapping buckets to a subset of the
2681                  * queues.
2682                  *
2683                  * If we have more buckets than queues, we'll
2684                  * end up instead assigning multiple buckets
2685                  * to queues.
2686                  *
2687                  * Both are suboptimal, but we need to handle
2688                  * the case so we don't go out of bounds
2689                  * indexing arrays and such.
2690                  */
2691                 queue_id = queue_id % adapter->rx_num_queues;
2692 #else
2693                 queue_id = (i % adapter->rx_num_queues);
2694 #endif
2695                 /* Adjust if required */
2696                 queue_id = queue_id << shift;
2697
2698                 /*
2699                  * The low 8 bits are for hash value (n+0);
2700                  * The next 8 bits are for hash value (n+1), etc.
2701                  */
2702                 reta = reta >> 8;
2703                 reta = reta | ( ((uint32_t) queue_id) << 24);
2704                 if ((i & 3) == 3) {
2705                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2706                         reta = 0;
2707                 }
2708         }
2709
2710         /* Now fill in hash table */
2711
2712         /*
2713          * MRQC: Multiple Receive Queues Command
2714          * Set queuing to RSS control, number depends on the device.
2715          */
2716         mrqc = E1000_MRQC_ENABLE_RSS_8Q;
2717
2718 #ifdef RSS
2719         /* XXX ew typecasting */
2720         rss_getkey((uint8_t *) &rss_key);
2721 #else
2722         arc4rand(&rss_key, sizeof(rss_key), 0);
2723 #endif
2724         for (i = 0; i < 10; i++)
2725                 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]);
2726
2727         /*
2728          * Configure the RSS fields to hash upon.
2729          */
2730         mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2731             E1000_MRQC_RSS_FIELD_IPV4_TCP);
2732         mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2733             E1000_MRQC_RSS_FIELD_IPV6_TCP);
2734         mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2735             E1000_MRQC_RSS_FIELD_IPV6_UDP);
2736         mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2737             E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2738
2739         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2740 }
2741
2742 /*********************************************************************
2743  *
2744  *  Setup networking device structure and register an interface.
2745  *
2746  **********************************************************************/
2747 static int
2748 em_setup_interface(if_ctx_t ctx)
2749 {
2750         struct ifnet *ifp = iflib_get_ifp(ctx);
2751         struct adapter *adapter = iflib_get_softc(ctx);
2752         if_softc_ctx_t scctx = adapter->shared;
2753         uint64_t cap = 0;
2754
2755         INIT_DEBUGOUT("em_setup_interface: begin");
2756
2757         /* TSO parameters */
2758         if_sethwtsomax(ifp, IP_MAXPACKET);
2759         /* Take m_pullup(9)'s in em_xmit() w/ TSO into acount. */
2760         if_sethwtsomaxsegcount(ifp, EM_MAX_SCATTER - 5);
2761         if_sethwtsomaxsegsize(ifp, EM_TSO_SEG_SIZE);
2762
2763         /* Single Queue */
2764         if (adapter->tx_num_queues == 1) {
2765                 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
2766                 if_setsendqready(ifp);
2767         }
2768
2769         cap = IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4;
2770         cap |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU;
2771
2772         /*
2773          * Tell the upper layer(s) we
2774          * support full VLAN capability
2775          */
2776         if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
2777         if_setcapabilitiesbit(ifp, cap, 0);
2778
2779         /*
2780          * Don't turn this on by default, if vlans are
2781          * created on another pseudo device (eg. lagg)
2782          * then vlan events are not passed thru, breaking
2783          * operation, but with HW FILTER off it works. If
2784          * using vlans directly on the em driver you can
2785          * enable this and get full hardware tag filtering.
2786          */
2787         if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWFILTER,0);
2788
2789         /* Enable only WOL MAGIC by default */
2790         if (adapter->wol) {
2791                 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC,
2792                             IFCAP_WOL_MCAST| IFCAP_WOL_UCAST);
2793         } else {
2794                 if_setcapenablebit(ifp, 0, IFCAP_WOL_MAGIC |
2795                              IFCAP_WOL_MCAST| IFCAP_WOL_UCAST);
2796         }
2797
2798         /*
2799          * Specify the media types supported by this adapter and register
2800          * callbacks to update media and link information
2801          */
2802         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
2803             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
2804                 u_char fiber_type = IFM_1000_SX;        /* default type */
2805
2806                 if (adapter->hw.mac.type == e1000_82545)
2807                         fiber_type = IFM_1000_LX;
2808                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
2809                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2810         } else {
2811                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2812                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2813                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2814                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2815                 if (adapter->hw.phy.type != e1000_phy_ife) {
2816                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2817                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2818                 }
2819         }
2820         ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2821         ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO);
2822         return (0);
2823 }
2824
2825 static int
2826 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
2827 {
2828         struct adapter *adapter = iflib_get_softc(ctx);
2829         if_softc_ctx_t scctx = adapter->shared;
2830         int error = E1000_SUCCESS;
2831         struct em_tx_queue *que;
2832         int i, j;
2833
2834         MPASS(adapter->tx_num_queues > 0);
2835         MPASS(adapter->tx_num_queues == ntxqsets);
2836
2837         /* First allocate the top level queue structs */
2838         if (!(adapter->tx_queues =
2839             (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
2840             adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2841                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2842                 return(ENOMEM);
2843         }
2844
2845         for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) {
2846                 /* Set up some basics */
2847
2848                 struct tx_ring *txr = &que->txr;
2849                 txr->adapter = que->adapter = adapter;
2850                 que->me = txr->me =  i;
2851
2852                 /* Allocate report status array */
2853                 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2854                         device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n");
2855                         error = ENOMEM;
2856                         goto fail;
2857                 }
2858                 for (j = 0; j < scctx->isc_ntxd[0]; j++)
2859                         txr->tx_rsq[j] = QIDX_INVALID;
2860                 /* get the virtual and physical address of the hardware queues */
2861                 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
2862                 txr->tx_paddr = paddrs[i*ntxqs];
2863         }
2864
2865         device_printf(iflib_get_dev(ctx), "allocated for %d tx_queues\n", adapter->tx_num_queues);
2866         return (0);
2867 fail:
2868         em_if_queues_free(ctx);
2869         return (error);
2870 }
2871
2872 static int
2873 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
2874 {
2875         struct adapter *adapter = iflib_get_softc(ctx);
2876         int error = E1000_SUCCESS;
2877         struct em_rx_queue *que;
2878         int i;
2879
2880         MPASS(adapter->rx_num_queues > 0);
2881         MPASS(adapter->rx_num_queues == nrxqsets);
2882
2883         /* First allocate the top level queue structs */
2884         if (!(adapter->rx_queues =
2885             (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
2886             adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2887                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2888                 error = ENOMEM;
2889                 goto fail;
2890         }
2891
2892         for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) {
2893                 /* Set up some basics */
2894                 struct rx_ring *rxr = &que->rxr;
2895                 rxr->adapter = que->adapter = adapter;
2896                 rxr->que = que;
2897                 que->me = rxr->me =  i;
2898
2899                 /* get the virtual and physical address of the hardware queues */
2900                 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
2901                 rxr->rx_paddr = paddrs[i*nrxqs];
2902         }
2903
2904         device_printf(iflib_get_dev(ctx), "allocated for %d rx_queues\n", adapter->rx_num_queues);
2905
2906         return (0);
2907 fail:
2908         em_if_queues_free(ctx);
2909         return (error);
2910 }
2911
2912 static void
2913 em_if_queues_free(if_ctx_t ctx)
2914 {
2915         struct adapter *adapter = iflib_get_softc(ctx);
2916         struct em_tx_queue *tx_que = adapter->tx_queues;
2917         struct em_rx_queue *rx_que = adapter->rx_queues;
2918
2919         if (tx_que != NULL) {
2920                 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
2921                         struct tx_ring *txr = &tx_que->txr;
2922                         if (txr->tx_rsq == NULL)
2923                                 break;
2924
2925                         free(txr->tx_rsq, M_DEVBUF);
2926                         txr->tx_rsq = NULL;
2927                 }
2928                 free(adapter->tx_queues, M_DEVBUF);
2929                 adapter->tx_queues = NULL;
2930         }
2931
2932         if (rx_que != NULL) {
2933                 free(adapter->rx_queues, M_DEVBUF);
2934                 adapter->rx_queues = NULL;
2935         }
2936
2937         em_release_hw_control(adapter);
2938
2939         if (adapter->mta != NULL) {
2940                 free(adapter->mta, M_DEVBUF);
2941         }
2942 }
2943
2944 /*********************************************************************
2945  *
2946  *  Enable transmit unit.
2947  *
2948  **********************************************************************/
2949 static void
2950 em_initialize_transmit_unit(if_ctx_t ctx)
2951 {
2952         struct adapter *adapter = iflib_get_softc(ctx);
2953         if_softc_ctx_t scctx = adapter->shared;
2954         struct em_tx_queue *que;
2955         struct tx_ring  *txr;
2956         struct e1000_hw *hw = &adapter->hw;
2957         u32 tctl, txdctl = 0, tarc, tipg = 0;
2958
2959         INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
2960
2961         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
2962                 u64 bus_addr;
2963                 caddr_t offp, endp;
2964
2965                 que = &adapter->tx_queues[i];
2966                 txr = &que->txr;
2967                 bus_addr = txr->tx_paddr;
2968
2969                 /* Clear checksum offload context. */
2970                 offp = (caddr_t)&txr->csum_flags;
2971                 endp = (caddr_t)(txr + 1);
2972                 bzero(offp, endp - offp);
2973
2974                 /* Base and Len of TX Ring */
2975                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
2976                     scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
2977                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
2978                     (u32)(bus_addr >> 32));
2979                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
2980                     (u32)bus_addr);
2981                 /* Init the HEAD/TAIL indices */
2982                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
2983                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
2984
2985                 HW_DEBUGOUT2("Base = %x, Length = %x\n",
2986                     E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)),
2987                     E1000_READ_REG(&adapter->hw, E1000_TDLEN(i)));
2988
2989                 txdctl = 0; /* clear txdctl */
2990                 txdctl |= 0x1f; /* PTHRESH */
2991                 txdctl |= 1 << 8; /* HTHRESH */
2992                 txdctl |= 1 << 16;/* WTHRESH */
2993                 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
2994                 txdctl |= E1000_TXDCTL_GRAN;
2995                 txdctl |= 1 << 25; /* LWTHRESH */
2996
2997                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
2998         }
2999
3000         /* Set the default values for the Tx Inter Packet Gap timer */
3001         switch (adapter->hw.mac.type) {
3002         case e1000_80003es2lan:
3003                 tipg = DEFAULT_82543_TIPG_IPGR1;
3004                 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
3005                     E1000_TIPG_IPGR2_SHIFT;
3006                 break;
3007         case e1000_82542:
3008                 tipg = DEFAULT_82542_TIPG_IPGT;
3009                 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3010                 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3011                 break;
3012         default:
3013                 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
3014                     (adapter->hw.phy.media_type ==
3015                     e1000_media_type_internal_serdes))
3016                         tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
3017                 else
3018                         tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
3019                 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3020                 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3021         }
3022
3023         E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
3024         E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value);
3025
3026         if(adapter->hw.mac.type >= e1000_82540)
3027                 E1000_WRITE_REG(&adapter->hw, E1000_TADV,
3028                     adapter->tx_abs_int_delay.value);
3029
3030         if ((adapter->hw.mac.type == e1000_82571) ||
3031             (adapter->hw.mac.type == e1000_82572)) {
3032                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3033                 tarc |= TARC_SPEED_MODE_BIT;
3034                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3035         } else if (adapter->hw.mac.type == e1000_80003es2lan) {
3036                 /* errata: program both queues to unweighted RR */
3037                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3038                 tarc |= 1;
3039                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3040                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
3041                 tarc |= 1;
3042                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
3043         } else if (adapter->hw.mac.type == e1000_82574) {
3044                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3045                 tarc |= TARC_ERRATA_BIT;
3046                 if ( adapter->tx_num_queues > 1) {
3047                         tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
3048                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3049                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
3050                 } else
3051                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3052         }
3053
3054         if (adapter->tx_int_delay.value > 0)
3055                 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3056
3057         /* Program the Transmit Control Register */
3058         tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
3059         tctl &= ~E1000_TCTL_CT;
3060         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
3061                    (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
3062
3063         if (adapter->hw.mac.type >= e1000_82571)
3064                 tctl |= E1000_TCTL_MULR;
3065
3066         /* This write will effectively turn on the transmit unit. */
3067         E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
3068
3069         /* SPT and KBL errata workarounds */
3070         if (hw->mac.type == e1000_pch_spt) {
3071                 u32 reg;
3072                 reg = E1000_READ_REG(hw, E1000_IOSFPC);
3073                 reg |= E1000_RCTL_RDMTS_HEX;
3074                 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
3075                 /* i218-i219 Specification Update 1.5.4.5 */
3076                 reg = E1000_READ_REG(hw, E1000_TARC(0));
3077                 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3078                 reg |= E1000_TARC0_CB_MULTIQ_2_REQ;
3079                 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3080         }
3081 }
3082
3083 /*********************************************************************
3084  *
3085  *  Enable receive unit.
3086  *
3087  **********************************************************************/
3088
3089 static void
3090 em_initialize_receive_unit(if_ctx_t ctx)
3091 {
3092         struct adapter *adapter = iflib_get_softc(ctx);
3093         if_softc_ctx_t scctx = adapter->shared;
3094         struct ifnet *ifp = iflib_get_ifp(ctx);
3095         struct e1000_hw *hw = &adapter->hw;
3096         struct em_rx_queue *que;
3097         int i;
3098         u32 rctl, rxcsum, rfctl;
3099
3100         INIT_DEBUGOUT("em_initialize_receive_units: begin");
3101
3102         /*
3103          * Make sure receives are disabled while setting
3104          * up the descriptor ring
3105          */
3106         rctl = E1000_READ_REG(hw, E1000_RCTL);
3107         /* Do not disable if ever enabled on this hardware */
3108         if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
3109                 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3110
3111         /* Setup the Receive Control Register */
3112         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3113         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3114             E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3115             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3116
3117         /* Do not store bad packets */
3118         rctl &= ~E1000_RCTL_SBP;
3119
3120         /* Enable Long Packet receive */
3121         if (if_getmtu(ifp) > ETHERMTU)
3122                 rctl |= E1000_RCTL_LPE;
3123         else
3124                 rctl &= ~E1000_RCTL_LPE;
3125
3126         /* Strip the CRC */
3127         if (!em_disable_crc_stripping)
3128                 rctl |= E1000_RCTL_SECRC;
3129
3130         if (adapter->hw.mac.type >= e1000_82540) {
3131                 E1000_WRITE_REG(&adapter->hw, E1000_RADV,
3132                             adapter->rx_abs_int_delay.value);
3133
3134                 /*
3135                  * Set the interrupt throttling rate. Value is calculated
3136                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
3137                  */
3138                 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
3139         }
3140         E1000_WRITE_REG(&adapter->hw, E1000_RDTR,
3141             adapter->rx_int_delay.value);
3142
3143         /* Use extended rx descriptor formats */
3144         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3145         rfctl |= E1000_RFCTL_EXTEN;
3146         /*
3147          * When using MSIX interrupts we need to throttle
3148          * using the EITR register (82574 only)
3149          */
3150         if (hw->mac.type == e1000_82574) {
3151                 for (int i = 0; i < 4; i++)
3152                         E1000_WRITE_REG(hw, E1000_EITR_82574(i),
3153                             DEFAULT_ITR);
3154                 /* Disable accelerated acknowledge */
3155                 rfctl |= E1000_RFCTL_ACK_DIS;
3156         }
3157         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3158
3159         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
3160         if (if_getcapenable(ifp) & IFCAP_RXCSUM &&
3161             adapter->hw.mac.type >= e1000_82543) {
3162                 if (adapter->tx_num_queues > 1) {
3163                         if (adapter->hw.mac.type >= igb_mac_min) {
3164                                 rxcsum |= E1000_RXCSUM_PCSD;
3165                                 if (hw->mac.type != e1000_82575)
3166                                         rxcsum |= E1000_RXCSUM_CRCOFL;
3167                         } else
3168                                 rxcsum |= E1000_RXCSUM_TUOFL |
3169                                         E1000_RXCSUM_IPOFL |
3170                                         E1000_RXCSUM_PCSD;
3171                 } else {
3172                         if (adapter->hw.mac.type >= igb_mac_min)
3173                                 rxcsum |= E1000_RXCSUM_IPPCSE;
3174                         else
3175                                 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
3176                         if (adapter->hw.mac.type > e1000_82575)
3177                                 rxcsum |= E1000_RXCSUM_CRCOFL;
3178                 }
3179         } else
3180                 rxcsum &= ~E1000_RXCSUM_TUOFL;
3181
3182         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
3183
3184         if (adapter->rx_num_queues > 1) {
3185                 if (adapter->hw.mac.type >= igb_mac_min)
3186                         igb_initialize_rss_mapping(adapter);
3187                 else
3188                         em_initialize_rss_mapping(adapter);
3189         }
3190
3191         /*
3192          * XXX TEMPORARY WORKAROUND: on some systems with 82573
3193          * long latencies are observed, like Lenovo X60. This
3194          * change eliminates the problem, but since having positive
3195          * values in RDTR is a known source of problems on other
3196          * platforms another solution is being sought.
3197          */
3198         if (hw->mac.type == e1000_82573)
3199                 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
3200
3201         for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3202                 struct rx_ring *rxr = &que->rxr;
3203                 /* Setup the Base and Length of the Rx Descriptor Ring */
3204                 u64 bus_addr = rxr->rx_paddr;
3205 #if 0
3206                 u32 rdt = adapter->rx_num_queues -1;  /* default */
3207 #endif
3208
3209                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3210                     scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
3211                 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
3212                 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
3213                 /* Setup the Head and Tail Descriptor Pointers */
3214                 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
3215                 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
3216         }
3217
3218         /*
3219          * Set PTHRESH for improved jumbo performance
3220          * According to 10.2.5.11 of Intel 82574 Datasheet,
3221          * RXDCTL(1) is written whenever RXDCTL(0) is written.
3222          * Only write to RXDCTL(1) if there is a need for different
3223          * settings.
3224          */
3225
3226         if (((adapter->hw.mac.type == e1000_ich9lan) ||
3227             (adapter->hw.mac.type == e1000_pch2lan) ||
3228             (adapter->hw.mac.type == e1000_ich10lan)) &&
3229             (if_getmtu(ifp) > ETHERMTU)) {
3230                 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
3231                 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
3232         } else if (adapter->hw.mac.type == e1000_82574) {
3233                 for (int i = 0; i < adapter->rx_num_queues; i++) {
3234                         u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3235                         rxdctl |= 0x20; /* PTHRESH */
3236                         rxdctl |= 4 << 8; /* HTHRESH */
3237                         rxdctl |= 4 << 16;/* WTHRESH */
3238                         rxdctl |= 1 << 24; /* Switch to granularity */
3239                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3240                 }
3241         } else if (adapter->hw.mac.type >= igb_mac_min) {
3242                 u32 psize, srrctl = 0;
3243
3244                 if (if_getmtu(ifp) > ETHERMTU) {
3245                         /* Set maximum packet len */
3246                         if (adapter->rx_mbuf_sz <= 4096) {
3247                                 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3248                                 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3249                         } else if (adapter->rx_mbuf_sz > 4096) {
3250                                 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3251                                 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3252                         }
3253                         psize = scctx->isc_max_frame_size;
3254                         /* are we on a vlan? */
3255                         if (ifp->if_vlantrunk != NULL)
3256                                 psize += VLAN_TAG_SIZE;
3257                         E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
3258                 } else {
3259                         srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3260                         rctl |= E1000_RCTL_SZ_2048;
3261                 }
3262
3263                 /*
3264                  * If TX flow control is disabled and there's >1 queue defined,
3265                  * enable DROP.
3266                  *
3267                  * This drops frames rather than hanging the RX MAC for all queues.
3268                  */
3269                 if ((adapter->rx_num_queues > 1) &&
3270                     (adapter->fc == e1000_fc_none ||
3271                      adapter->fc == e1000_fc_rx_pause)) {
3272                         srrctl |= E1000_SRRCTL_DROP_EN;
3273                 }
3274                         /* Setup the Base and Length of the Rx Descriptor Rings */
3275                 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3276                         struct rx_ring *rxr = &que->rxr;
3277                         u64 bus_addr = rxr->rx_paddr;
3278                         u32 rxdctl;
3279
3280 #ifdef notyet
3281                         /* Configure for header split? -- ignore for now */
3282                         rxr->hdr_split = igb_header_split;
3283 #else
3284                         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3285 #endif
3286
3287                         E1000_WRITE_REG(hw, E1000_RDLEN(i),
3288                                         scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3289                         E1000_WRITE_REG(hw, E1000_RDBAH(i),
3290                                         (uint32_t)(bus_addr >> 32));
3291                         E1000_WRITE_REG(hw, E1000_RDBAL(i),
3292                                         (uint32_t)bus_addr);
3293                         E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3294                         /* Enable this Queue */
3295                         rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3296                         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3297                         rxdctl &= 0xFFF00000;
3298                         rxdctl |= IGB_RX_PTHRESH;
3299                         rxdctl |= IGB_RX_HTHRESH << 8;
3300                         rxdctl |= IGB_RX_WTHRESH << 16;
3301                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3302                 }
3303         } else if (adapter->hw.mac.type >= e1000_pch2lan) {
3304                 if (if_getmtu(ifp) > ETHERMTU)
3305                         e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
3306                 else
3307                         e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
3308         }
3309
3310         /* Make sure VLAN Filters are off */
3311         rctl &= ~E1000_RCTL_VFE;
3312
3313         if (adapter->hw.mac.type < igb_mac_min) {
3314                 if (adapter->rx_mbuf_sz == MCLBYTES)
3315                         rctl |= E1000_RCTL_SZ_2048;
3316                 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE)
3317                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3318                 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE)
3319                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3320
3321                 /* ensure we clear use DTYPE of 00 here */
3322                 rctl &= ~0x00000C00;
3323         }
3324
3325         /* Write out the settings */
3326         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3327
3328         return;
3329 }
3330
3331 static void
3332 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3333 {
3334         struct adapter *adapter = iflib_get_softc(ctx);
3335         u32 index, bit;
3336
3337         index = (vtag >> 5) & 0x7F;
3338         bit = vtag & 0x1F;
3339         adapter->shadow_vfta[index] |= (1 << bit);
3340         ++adapter->num_vlans;
3341 }
3342
3343 static void
3344 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3345 {
3346         struct adapter *adapter = iflib_get_softc(ctx);
3347         u32 index, bit;
3348
3349         index = (vtag >> 5) & 0x7F;
3350         bit = vtag & 0x1F;
3351         adapter->shadow_vfta[index] &= ~(1 << bit);
3352         --adapter->num_vlans;
3353 }
3354
3355 static void
3356 em_setup_vlan_hw_support(struct adapter *adapter)
3357 {
3358         struct e1000_hw *hw = &adapter->hw;
3359         u32 reg;
3360
3361         /*
3362          * We get here thru init_locked, meaning
3363          * a soft reset, this has already cleared
3364          * the VFTA and other state, so if there
3365          * have been no vlan's registered do nothing.
3366          */
3367         if (adapter->num_vlans == 0)
3368                 return;
3369
3370         /*
3371          * A soft reset zero's out the VFTA, so
3372          * we need to repopulate it now.
3373          */
3374         for (int i = 0; i < EM_VFTA_SIZE; i++)
3375                 if (adapter->shadow_vfta[i] != 0)
3376                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
3377                             i, adapter->shadow_vfta[i]);
3378
3379         reg = E1000_READ_REG(hw, E1000_CTRL);
3380         reg |= E1000_CTRL_VME;
3381         E1000_WRITE_REG(hw, E1000_CTRL, reg);
3382
3383         /* Enable the Filter Table */
3384         reg = E1000_READ_REG(hw, E1000_RCTL);
3385         reg &= ~E1000_RCTL_CFIEN;
3386         reg |= E1000_RCTL_VFE;
3387         E1000_WRITE_REG(hw, E1000_RCTL, reg);
3388 }
3389
3390 static void
3391 em_if_enable_intr(if_ctx_t ctx)
3392 {
3393         struct adapter *adapter = iflib_get_softc(ctx);
3394         struct e1000_hw *hw = &adapter->hw;
3395         u32 ims_mask = IMS_ENABLE_MASK;
3396
3397         if (hw->mac.type == e1000_82574) {
3398                 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK);
3399                 ims_mask |= adapter->ims;
3400         } else if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min)  {
3401                 u32 mask = (adapter->que_mask | adapter->link_mask);
3402
3403                 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask);
3404                 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask);
3405                 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask);
3406                 ims_mask = E1000_IMS_LSC;
3407         }
3408
3409         E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3410 }
3411
3412 static void
3413 em_if_disable_intr(if_ctx_t ctx)
3414 {
3415         struct adapter *adapter = iflib_get_softc(ctx);
3416         struct e1000_hw *hw = &adapter->hw;
3417
3418         if (adapter->intr_type == IFLIB_INTR_MSIX) {
3419                 if (hw->mac.type >= igb_mac_min)
3420                         E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0);
3421                 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0);
3422         }
3423         E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
3424 }
3425
3426 /*
3427  * Bit of a misnomer, what this really means is
3428  * to enable OS management of the system... aka
3429  * to disable special hardware management features
3430  */
3431 static void
3432 em_init_manageability(struct adapter *adapter)
3433 {
3434         /* A shared code workaround */
3435 #define E1000_82542_MANC2H E1000_MANC2H
3436         if (adapter->has_manage) {
3437                 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3438                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3439
3440                 /* disable hardware interception of ARP */
3441                 manc &= ~(E1000_MANC_ARP_EN);
3442
3443                 /* enable receiving management packets to the host */
3444                 manc |= E1000_MANC_EN_MNG2HOST;
3445 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3446 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3447                 manc2h |= E1000_MNG2HOST_PORT_623;
3448                 manc2h |= E1000_MNG2HOST_PORT_664;
3449                 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3450                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3451         }
3452 }
3453
3454 /*
3455  * Give control back to hardware management
3456  * controller if there is one.
3457  */
3458 static void
3459 em_release_manageability(struct adapter *adapter)
3460 {
3461         if (adapter->has_manage) {
3462                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3463
3464                 /* re-enable hardware interception of ARP */
3465                 manc |= E1000_MANC_ARP_EN;
3466                 manc &= ~E1000_MANC_EN_MNG2HOST;
3467
3468                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3469         }
3470 }
3471
3472 /*
3473  * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3474  * For ASF and Pass Through versions of f/w this means
3475  * that the driver is loaded. For AMT version type f/w
3476  * this means that the network i/f is open.
3477  */
3478 static void
3479 em_get_hw_control(struct adapter *adapter)
3480 {
3481         u32 ctrl_ext, swsm;
3482
3483         if (adapter->vf_ifp)
3484                 return;
3485
3486         if (adapter->hw.mac.type == e1000_82573) {
3487                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3488                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3489                     swsm | E1000_SWSM_DRV_LOAD);
3490                 return;
3491         }
3492         /* else */
3493         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3494         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3495             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3496 }
3497
3498 /*
3499  * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3500  * For ASF and Pass Through versions of f/w this means that
3501  * the driver is no longer loaded. For AMT versions of the
3502  * f/w this means that the network i/f is closed.
3503  */
3504 static void
3505 em_release_hw_control(struct adapter *adapter)
3506 {
3507         u32 ctrl_ext, swsm;
3508
3509         if (!adapter->has_manage)
3510                 return;
3511
3512         if (adapter->hw.mac.type == e1000_82573) {
3513                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3514                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3515                     swsm & ~E1000_SWSM_DRV_LOAD);
3516                 return;
3517         }
3518         /* else */
3519         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3520         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3521             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3522         return;
3523 }
3524
3525 static int
3526 em_is_valid_ether_addr(u8 *addr)
3527 {
3528         char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3529
3530         if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3531                 return (FALSE);
3532         }
3533
3534         return (TRUE);
3535 }
3536
3537 /*
3538 ** Parse the interface capabilities with regard
3539 ** to both system management and wake-on-lan for
3540 ** later use.
3541 */
3542 static void
3543 em_get_wakeup(if_ctx_t ctx)
3544 {
3545         struct adapter *adapter = iflib_get_softc(ctx);
3546         device_t dev = iflib_get_dev(ctx);
3547         u16 eeprom_data = 0, device_id, apme_mask;
3548
3549         adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
3550         apme_mask = EM_EEPROM_APME;
3551
3552         switch (adapter->hw.mac.type) {
3553         case e1000_82542:
3554         case e1000_82543:
3555                 break;
3556         case e1000_82544:
3557                 e1000_read_nvm(&adapter->hw,
3558                     NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3559                 apme_mask = EM_82544_APME;
3560                 break;
3561         case e1000_82546:
3562         case e1000_82546_rev_3:
3563                 if (adapter->hw.bus.func == 1) {
3564                         e1000_read_nvm(&adapter->hw,
3565                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3566                         break;
3567                 } else
3568                         e1000_read_nvm(&adapter->hw,
3569                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3570                 break;
3571         case e1000_82573:
3572         case e1000_82583:
3573                 adapter->has_amt = TRUE;
3574                 /* FALLTHROUGH */
3575         case e1000_82571:
3576         case e1000_82572:
3577         case e1000_80003es2lan:
3578                 if (adapter->hw.bus.func == 1) {
3579                         e1000_read_nvm(&adapter->hw,
3580                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3581                         break;
3582                 } else
3583                         e1000_read_nvm(&adapter->hw,
3584                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3585                 break;
3586         case e1000_ich8lan:
3587         case e1000_ich9lan:
3588         case e1000_ich10lan:
3589         case e1000_pchlan:
3590         case e1000_pch2lan:
3591         case e1000_pch_lpt:
3592         case e1000_pch_spt:
3593         case e1000_82575:       /* listing all igb devices */
3594         case e1000_82576:
3595         case e1000_82580:
3596         case e1000_i350:
3597         case e1000_i354:
3598         case e1000_i210:
3599         case e1000_i211:
3600         case e1000_vfadapt:
3601         case e1000_vfadapt_i350:
3602                 apme_mask = E1000_WUC_APME;
3603                 adapter->has_amt = TRUE;
3604                 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
3605                 break;
3606         default:
3607                 e1000_read_nvm(&adapter->hw,
3608                     NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3609                 break;
3610         }
3611         if (eeprom_data & apme_mask)
3612                 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
3613         /*
3614          * We have the eeprom settings, now apply the special cases
3615          * where the eeprom may be wrong or the board won't support
3616          * wake on lan on a particular port
3617          */
3618         device_id = pci_get_device(dev);
3619         switch (device_id) {
3620         case E1000_DEV_ID_82546GB_PCIE:
3621                 adapter->wol = 0;
3622                 break;
3623         case E1000_DEV_ID_82546EB_FIBER:
3624         case E1000_DEV_ID_82546GB_FIBER:
3625                 /* Wake events only supported on port A for dual fiber
3626                  * regardless of eeprom setting */
3627                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3628                     E1000_STATUS_FUNC_1)
3629                         adapter->wol = 0;
3630                 break;
3631         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
3632                 /* if quad port adapter, disable WoL on all but port A */
3633                 if (global_quad_port_a != 0)
3634                         adapter->wol = 0;
3635                 /* Reset for multiple quad port adapters */
3636                 if (++global_quad_port_a == 4)
3637                         global_quad_port_a = 0;
3638                 break;
3639         case E1000_DEV_ID_82571EB_FIBER:
3640                 /* Wake events only supported on port A for dual fiber
3641                  * regardless of eeprom setting */
3642                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3643                     E1000_STATUS_FUNC_1)
3644                         adapter->wol = 0;
3645                 break;
3646         case E1000_DEV_ID_82571EB_QUAD_COPPER:
3647         case E1000_DEV_ID_82571EB_QUAD_FIBER:
3648         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
3649                 /* if quad port adapter, disable WoL on all but port A */
3650                 if (global_quad_port_a != 0)
3651                         adapter->wol = 0;
3652                 /* Reset for multiple quad port adapters */
3653                 if (++global_quad_port_a == 4)
3654                         global_quad_port_a = 0;
3655                 break;
3656         }
3657         return;
3658 }
3659
3660
3661 /*
3662  * Enable PCI Wake On Lan capability
3663  */
3664 static void
3665 em_enable_wakeup(if_ctx_t ctx)
3666 {
3667         struct adapter *adapter = iflib_get_softc(ctx);
3668         device_t dev = iflib_get_dev(ctx);
3669         if_t ifp = iflib_get_ifp(ctx);
3670         int error = 0;
3671         u32 pmc, ctrl, ctrl_ext, rctl;
3672         u16 status;
3673
3674         if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
3675                 return;
3676
3677         /*
3678          * Determine type of Wakeup: note that wol
3679          * is set with all bits on by default.
3680          */
3681         if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
3682                 adapter->wol &= ~E1000_WUFC_MAG;
3683
3684         if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
3685                 adapter->wol &= ~E1000_WUFC_EX;
3686
3687         if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
3688                 adapter->wol &= ~E1000_WUFC_MC;
3689         else {
3690                 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3691                 rctl |= E1000_RCTL_MPE;
3692                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3693         }
3694
3695         if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC)))
3696                 goto pme;
3697
3698         /* Advertise the wakeup capability */
3699         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
3700         ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
3701         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
3702
3703         /* Keep the laser running on Fiber adapters */
3704         if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3705             adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
3706                 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3707                 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
3708                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext);
3709         }
3710
3711         if ((adapter->hw.mac.type == e1000_ich8lan) ||
3712             (adapter->hw.mac.type == e1000_pchlan) ||
3713             (adapter->hw.mac.type == e1000_ich9lan) ||
3714             (adapter->hw.mac.type == e1000_ich10lan))
3715                 e1000_suspend_workarounds_ich8lan(&adapter->hw);
3716
3717         if ( adapter->hw.mac.type >= e1000_pchlan) {
3718                 error = em_enable_phy_wakeup(adapter);
3719                 if (error)
3720                         goto pme;
3721         } else {
3722                 /* Enable wakeup by the MAC */
3723                 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
3724                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
3725         }
3726
3727         if (adapter->hw.phy.type == e1000_phy_igp_3)
3728                 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
3729
3730 pme:
3731         status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
3732         status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3733         if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
3734                 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3735         pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
3736
3737         return;
3738 }
3739
3740 /*
3741  * WOL in the newer chipset interfaces (pchlan)
3742  * require thing to be copied into the phy
3743  */
3744 static int
3745 em_enable_phy_wakeup(struct adapter *adapter)
3746 {
3747         struct e1000_hw *hw = &adapter->hw;
3748         u32 mreg, ret = 0;
3749         u16 preg;
3750
3751         /* copy MAC RARs to PHY RARs */
3752         e1000_copy_rx_addrs_to_phy_ich8lan(hw);
3753
3754         /* copy MAC MTA to PHY MTA */
3755         for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
3756                 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
3757                 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
3758                 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
3759                     (u16)((mreg >> 16) & 0xFFFF));
3760         }
3761
3762         /* configure PHY Rx Control register */
3763         e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg);
3764         mreg = E1000_READ_REG(hw, E1000_RCTL);
3765         if (mreg & E1000_RCTL_UPE)
3766                 preg |= BM_RCTL_UPE;
3767         if (mreg & E1000_RCTL_MPE)
3768                 preg |= BM_RCTL_MPE;
3769         preg &= ~(BM_RCTL_MO_MASK);
3770         if (mreg & E1000_RCTL_MO_3)
3771                 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
3772                                 << BM_RCTL_MO_SHIFT);
3773         if (mreg & E1000_RCTL_BAM)
3774                 preg |= BM_RCTL_BAM;
3775         if (mreg & E1000_RCTL_PMCF)
3776                 preg |= BM_RCTL_PMCF;
3777         mreg = E1000_READ_REG(hw, E1000_CTRL);
3778         if (mreg & E1000_CTRL_RFCE)
3779                 preg |= BM_RCTL_RFCE;
3780         e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg);
3781
3782         /* enable PHY wakeup in MAC register */
3783         E1000_WRITE_REG(hw, E1000_WUC,
3784             E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
3785         E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol);
3786
3787         /* configure and enable PHY wakeup in PHY registers */
3788         e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol);
3789         e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
3790
3791         /* activate PHY wakeup */
3792         ret = hw->phy.ops.acquire(hw);
3793         if (ret) {
3794                 printf("Could not acquire PHY\n");
3795                 return ret;
3796         }
3797         e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3798                                  (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3799         ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
3800         if (ret) {
3801                 printf("Could not read PHY page 769\n");
3802                 goto out;
3803         }
3804         preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
3805         ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
3806         if (ret)
3807                 printf("Could not set PHY Host Wakeup bit\n");
3808 out:
3809         hw->phy.ops.release(hw);
3810
3811         return ret;
3812 }
3813
3814 static void
3815 em_if_led_func(if_ctx_t ctx, int onoff)
3816 {
3817         struct adapter *adapter = iflib_get_softc(ctx);
3818
3819         if (onoff) {
3820                 e1000_setup_led(&adapter->hw);
3821                 e1000_led_on(&adapter->hw);
3822         } else {
3823                 e1000_led_off(&adapter->hw);
3824                 e1000_cleanup_led(&adapter->hw);
3825         }
3826 }
3827
3828 /*
3829  * Disable the L0S and L1 LINK states
3830  */
3831 static void
3832 em_disable_aspm(struct adapter *adapter)
3833 {
3834         int base, reg;
3835         u16 link_cap,link_ctrl;
3836         device_t dev = adapter->dev;
3837
3838         switch (adapter->hw.mac.type) {
3839         case e1000_82573:
3840         case e1000_82574:
3841         case e1000_82583:
3842                 break;
3843         default:
3844                 return;
3845         }
3846         if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
3847                 return;
3848         reg = base + PCIER_LINK_CAP;
3849         link_cap = pci_read_config(dev, reg, 2);
3850         if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
3851                 return;
3852         reg = base + PCIER_LINK_CTL;
3853         link_ctrl = pci_read_config(dev, reg, 2);
3854         link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
3855         pci_write_config(dev, reg, link_ctrl, 2);
3856         return;
3857 }
3858
3859 /**********************************************************************
3860  *
3861  *  Update the board statistics counters.
3862  *
3863  **********************************************************************/
3864 static void
3865 em_update_stats_counters(struct adapter *adapter)
3866 {
3867
3868         if(adapter->hw.phy.media_type == e1000_media_type_copper ||
3869            (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3870                 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
3871                 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
3872         }
3873         adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
3874         adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
3875         adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
3876         adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
3877
3878         adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
3879         adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
3880         adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
3881         adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
3882         adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
3883         adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
3884         adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
3885         adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
3886         /*
3887          ** For watchdog management we need to know if we have been
3888          ** paused during the last interval, so capture that here.
3889         */
3890         adapter->shared->isc_pause_frames = adapter->stats.xoffrxc;
3891         adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
3892         adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
3893         adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
3894         adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
3895         adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
3896         adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
3897         adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
3898         adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
3899         adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
3900         adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
3901         adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
3902         adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
3903
3904         /* For the 64-bit byte counters the low dword must be read first. */
3905         /* Both registers clear on the read of the high dword */
3906
3907         adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) +
3908             ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32);
3909         adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) +
3910             ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32);
3911
3912         adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
3913         adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
3914         adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
3915         adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
3916         adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
3917
3918         adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
3919         adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
3920
3921         adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
3922         adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
3923         adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
3924         adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
3925         adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
3926         adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
3927         adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
3928         adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
3929         adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
3930         adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
3931
3932         /* Interrupt Counts */
3933
3934         adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC);
3935         adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC);
3936         adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC);
3937         adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC);
3938         adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC);
3939         adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC);
3940         adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC);
3941         adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC);
3942         adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC);
3943
3944         if (adapter->hw.mac.type >= e1000_82543) {
3945                 adapter->stats.algnerrc +=
3946                 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
3947                 adapter->stats.rxerrc +=
3948                 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
3949                 adapter->stats.tncrs +=
3950                 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
3951                 adapter->stats.cexterr +=
3952                 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
3953                 adapter->stats.tsctc +=
3954                 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
3955                 adapter->stats.tsctfc +=
3956                 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
3957         }
3958 }
3959
3960 static uint64_t
3961 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
3962 {
3963         struct adapter *adapter = iflib_get_softc(ctx);
3964         struct ifnet *ifp = iflib_get_ifp(ctx);
3965
3966         switch (cnt) {
3967         case IFCOUNTER_COLLISIONS:
3968                 return (adapter->stats.colc);
3969         case IFCOUNTER_IERRORS:
3970                 return (adapter->dropped_pkts + adapter->stats.rxerrc +
3971                     adapter->stats.crcerrs + adapter->stats.algnerrc +
3972                     adapter->stats.ruc + adapter->stats.roc +
3973                     adapter->stats.mpc + adapter->stats.cexterr);
3974         case IFCOUNTER_OERRORS:
3975                 return (adapter->stats.ecol + adapter->stats.latecol +
3976                     adapter->watchdog_events);
3977         default:
3978                 return (if_get_counter_default(ifp, cnt));
3979         }
3980 }
3981
3982 /* Export a single 32-bit register via a read-only sysctl. */
3983 static int
3984 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
3985 {
3986         struct adapter *adapter;
3987         u_int val;
3988
3989         adapter = oidp->oid_arg1;
3990         val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2);
3991         return (sysctl_handle_int(oidp, &val, 0, req));
3992 }
3993
3994 /*
3995  * Add sysctl variables, one per statistic, to the system.
3996  */
3997 static void
3998 em_add_hw_stats(struct adapter *adapter)
3999 {
4000         device_t dev = iflib_get_dev(adapter->ctx);
4001         struct em_tx_queue *tx_que = adapter->tx_queues;
4002         struct em_rx_queue *rx_que = adapter->rx_queues;
4003
4004         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
4005         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
4006         struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
4007         struct e1000_hw_stats *stats = &adapter->stats;
4008
4009         struct sysctl_oid *stat_node, *queue_node, *int_node;
4010         struct sysctl_oid_list *stat_list, *queue_list, *int_list;
4011
4012 #define QUEUE_NAME_LEN 32
4013         char namebuf[QUEUE_NAME_LEN];
4014
4015         /* Driver Statistics */
4016         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
4017                         CTLFLAG_RD, &adapter->dropped_pkts,
4018                         "Driver dropped packets");
4019         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
4020                         CTLFLAG_RD, &adapter->link_irq,
4021                         "Link MSIX IRQ Handled");
4022         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "mbuf_defrag_fail",
4023                          CTLFLAG_RD, &adapter->mbuf_defrag_failed,
4024                          "Defragmenting mbuf chain failed");
4025         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "tx_dma_fail",
4026                         CTLFLAG_RD, &adapter->no_tx_dma_setup,
4027                         "Driver tx dma failure in xmit");
4028         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
4029                         CTLFLAG_RD, &adapter->rx_overruns,
4030                         "RX overruns");
4031         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
4032                         CTLFLAG_RD, &adapter->watchdog_events,
4033                         "Watchdog timeouts");
4034         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
4035                         CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL,
4036                         em_sysctl_reg_handler, "IU",
4037                         "Device Control Register");
4038         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
4039                         CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL,
4040                         em_sysctl_reg_handler, "IU",
4041                         "Receiver Control Register");
4042         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
4043                         CTLFLAG_RD, &adapter->hw.fc.high_water, 0,
4044                         "Flow Control High Watermark");
4045         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
4046                         CTLFLAG_RD, &adapter->hw.fc.low_water, 0,
4047                         "Flow Control Low Watermark");
4048
4049         for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
4050                 struct tx_ring *txr = &tx_que->txr;
4051                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
4052                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4053                                             CTLFLAG_RD, NULL, "TX Queue Name");
4054                 queue_list = SYSCTL_CHILDREN(queue_node);
4055
4056                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
4057                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4058                                 E1000_TDH(txr->me),
4059                                 em_sysctl_reg_handler, "IU",
4060                                 "Transmit Descriptor Head");
4061                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
4062                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4063                                 E1000_TDT(txr->me),
4064                                 em_sysctl_reg_handler, "IU",
4065                                 "Transmit Descriptor Tail");
4066                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
4067                                 CTLFLAG_RD, &txr->tx_irq,
4068                                 "Queue MSI-X Transmit Interrupts");
4069         }
4070
4071         for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) {
4072                 struct rx_ring *rxr = &rx_que->rxr;
4073                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
4074                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4075                                             CTLFLAG_RD, NULL, "RX Queue Name");
4076                 queue_list = SYSCTL_CHILDREN(queue_node);
4077
4078                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
4079                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4080                                 E1000_RDH(rxr->me),
4081                                 em_sysctl_reg_handler, "IU",
4082                                 "Receive Descriptor Head");
4083                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
4084                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4085                                 E1000_RDT(rxr->me),
4086                                 em_sysctl_reg_handler, "IU",
4087                                 "Receive Descriptor Tail");
4088                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
4089                                 CTLFLAG_RD, &rxr->rx_irq,
4090                                 "Queue MSI-X Receive Interrupts");
4091         }
4092
4093         /* MAC stats get their own sub node */
4094
4095         stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
4096                                     CTLFLAG_RD, NULL, "Statistics");
4097         stat_list = SYSCTL_CHILDREN(stat_node);
4098
4099         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
4100                         CTLFLAG_RD, &stats->ecol,
4101                         "Excessive collisions");
4102         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
4103                         CTLFLAG_RD, &stats->scc,
4104                         "Single collisions");
4105         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
4106                         CTLFLAG_RD, &stats->mcc,
4107                         "Multiple collisions");
4108         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
4109                         CTLFLAG_RD, &stats->latecol,
4110                         "Late collisions");
4111         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
4112                         CTLFLAG_RD, &stats->colc,
4113                         "Collision Count");
4114         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
4115                         CTLFLAG_RD, &adapter->stats.symerrs,
4116                         "Symbol Errors");
4117         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
4118                         CTLFLAG_RD, &adapter->stats.sec,
4119                         "Sequence Errors");
4120         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
4121                         CTLFLAG_RD, &adapter->stats.dc,
4122                         "Defer Count");
4123         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
4124                         CTLFLAG_RD, &adapter->stats.mpc,
4125                         "Missed Packets");
4126         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
4127                         CTLFLAG_RD, &adapter->stats.rnbc,
4128                         "Receive No Buffers");
4129         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
4130                         CTLFLAG_RD, &adapter->stats.ruc,
4131                         "Receive Undersize");
4132         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
4133                         CTLFLAG_RD, &adapter->stats.rfc,
4134                         "Fragmented Packets Received ");
4135         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
4136                         CTLFLAG_RD, &adapter->stats.roc,
4137                         "Oversized Packets Received");
4138         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
4139                         CTLFLAG_RD, &adapter->stats.rjc,
4140                         "Recevied Jabber");
4141         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
4142                         CTLFLAG_RD, &adapter->stats.rxerrc,
4143                         "Receive Errors");
4144         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
4145                         CTLFLAG_RD, &adapter->stats.crcerrs,
4146                         "CRC errors");
4147         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
4148                         CTLFLAG_RD, &adapter->stats.algnerrc,
4149                         "Alignment Errors");
4150         /* On 82575 these are collision counts */
4151         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
4152                         CTLFLAG_RD, &adapter->stats.cexterr,
4153                         "Collision/Carrier extension errors");
4154         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
4155                         CTLFLAG_RD, &adapter->stats.xonrxc,
4156                         "XON Received");
4157         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
4158                         CTLFLAG_RD, &adapter->stats.xontxc,
4159                         "XON Transmitted");
4160         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
4161                         CTLFLAG_RD, &adapter->stats.xoffrxc,
4162                         "XOFF Received");
4163         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
4164                         CTLFLAG_RD, &adapter->stats.xofftxc,
4165                         "XOFF Transmitted");
4166
4167         /* Packet Reception Stats */
4168         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
4169                         CTLFLAG_RD, &adapter->stats.tpr,
4170                         "Total Packets Received ");
4171         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
4172                         CTLFLAG_RD, &adapter->stats.gprc,
4173                         "Good Packets Received");
4174         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
4175                         CTLFLAG_RD, &adapter->stats.bprc,
4176                         "Broadcast Packets Received");
4177         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
4178                         CTLFLAG_RD, &adapter->stats.mprc,
4179                         "Multicast Packets Received");
4180         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
4181                         CTLFLAG_RD, &adapter->stats.prc64,
4182                         "64 byte frames received ");
4183         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
4184                         CTLFLAG_RD, &adapter->stats.prc127,
4185                         "65-127 byte frames received");
4186         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
4187                         CTLFLAG_RD, &adapter->stats.prc255,
4188                         "128-255 byte frames received");
4189         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
4190                         CTLFLAG_RD, &adapter->stats.prc511,
4191                         "256-511 byte frames received");
4192         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
4193                         CTLFLAG_RD, &adapter->stats.prc1023,
4194                         "512-1023 byte frames received");
4195         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
4196                         CTLFLAG_RD, &adapter->stats.prc1522,
4197                         "1023-1522 byte frames received");
4198         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
4199                         CTLFLAG_RD, &adapter->stats.gorc,
4200                         "Good Octets Received");
4201
4202         /* Packet Transmission Stats */
4203         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
4204                         CTLFLAG_RD, &adapter->stats.gotc,
4205                         "Good Octets Transmitted");
4206         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
4207                         CTLFLAG_RD, &adapter->stats.tpt,
4208                         "Total Packets Transmitted");
4209         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
4210                         CTLFLAG_RD, &adapter->stats.gptc,
4211                         "Good Packets Transmitted");
4212         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
4213                         CTLFLAG_RD, &adapter->stats.bptc,
4214                         "Broadcast Packets Transmitted");
4215         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
4216                         CTLFLAG_RD, &adapter->stats.mptc,
4217                         "Multicast Packets Transmitted");
4218         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
4219                         CTLFLAG_RD, &adapter->stats.ptc64,
4220                         "64 byte frames transmitted ");
4221         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
4222                         CTLFLAG_RD, &adapter->stats.ptc127,
4223                         "65-127 byte frames transmitted");
4224         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
4225                         CTLFLAG_RD, &adapter->stats.ptc255,
4226                         "128-255 byte frames transmitted");
4227         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
4228                         CTLFLAG_RD, &adapter->stats.ptc511,
4229                         "256-511 byte frames transmitted");
4230         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
4231                         CTLFLAG_RD, &adapter->stats.ptc1023,
4232                         "512-1023 byte frames transmitted");
4233         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
4234                         CTLFLAG_RD, &adapter->stats.ptc1522,
4235                         "1024-1522 byte frames transmitted");
4236         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
4237                         CTLFLAG_RD, &adapter->stats.tsctc,
4238                         "TSO Contexts Transmitted");
4239         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
4240                         CTLFLAG_RD, &adapter->stats.tsctfc,
4241                         "TSO Contexts Failed");
4242
4243
4244         /* Interrupt Stats */
4245
4246         int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
4247                                     CTLFLAG_RD, NULL, "Interrupt Statistics");
4248         int_list = SYSCTL_CHILDREN(int_node);
4249
4250         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
4251                         CTLFLAG_RD, &adapter->stats.iac,
4252                         "Interrupt Assertion Count");
4253
4254         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
4255                         CTLFLAG_RD, &adapter->stats.icrxptc,
4256                         "Interrupt Cause Rx Pkt Timer Expire Count");
4257
4258         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
4259                         CTLFLAG_RD, &adapter->stats.icrxatc,
4260                         "Interrupt Cause Rx Abs Timer Expire Count");
4261
4262         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
4263                         CTLFLAG_RD, &adapter->stats.ictxptc,
4264                         "Interrupt Cause Tx Pkt Timer Expire Count");
4265
4266         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
4267                         CTLFLAG_RD, &adapter->stats.ictxatc,
4268                         "Interrupt Cause Tx Abs Timer Expire Count");
4269
4270         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
4271                         CTLFLAG_RD, &adapter->stats.ictxqec,
4272                         "Interrupt Cause Tx Queue Empty Count");
4273
4274         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
4275                         CTLFLAG_RD, &adapter->stats.ictxqmtc,
4276                         "Interrupt Cause Tx Queue Min Thresh Count");
4277
4278         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
4279                         CTLFLAG_RD, &adapter->stats.icrxdmtc,
4280                         "Interrupt Cause Rx Desc Min Thresh Count");
4281
4282         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
4283                         CTLFLAG_RD, &adapter->stats.icrxoc,
4284                         "Interrupt Cause Receiver Overrun Count");
4285 }
4286
4287 /**********************************************************************
4288  *
4289  *  This routine provides a way to dump out the adapter eeprom,
4290  *  often a useful debug/service tool. This only dumps the first
4291  *  32 words, stuff that matters is in that extent.
4292  *
4293  **********************************************************************/
4294 static int
4295 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4296 {
4297         struct adapter *adapter = (struct adapter *)arg1;
4298         int error;
4299         int result;
4300
4301         result = -1;
4302         error = sysctl_handle_int(oidp, &result, 0, req);
4303
4304         if (error || !req->newptr)
4305                 return (error);
4306
4307         /*
4308          * This value will cause a hex dump of the
4309          * first 32 16-bit words of the EEPROM to
4310          * the screen.
4311          */
4312         if (result == 1)
4313                 em_print_nvm_info(adapter);
4314
4315         return (error);
4316 }
4317
4318 static void
4319 em_print_nvm_info(struct adapter *adapter)
4320 {
4321         u16 eeprom_data;
4322         int i, j, row = 0;
4323
4324         /* Its a bit crude, but it gets the job done */
4325         printf("\nInterface EEPROM Dump:\n");
4326         printf("Offset\n0x0000  ");
4327         for (i = 0, j = 0; i < 32; i++, j++) {
4328                 if (j == 8) { /* Make the offset block */
4329                         j = 0; ++row;
4330                         printf("\n0x00%x0  ",row);
4331                 }
4332                 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
4333                 printf("%04x ", eeprom_data);
4334         }
4335         printf("\n");
4336 }
4337
4338 static int
4339 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4340 {
4341         struct em_int_delay_info *info;
4342         struct adapter *adapter;
4343         u32 regval;
4344         int error, usecs, ticks;
4345
4346         info = (struct em_int_delay_info *) arg1;
4347         usecs = info->value;
4348         error = sysctl_handle_int(oidp, &usecs, 0, req);
4349         if (error != 0 || req->newptr == NULL)
4350                 return (error);
4351         if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4352                 return (EINVAL);
4353         info->value = usecs;
4354         ticks = EM_USECS_TO_TICKS(usecs);
4355         if (info->offset == E1000_ITR)  /* units are 256ns here */
4356                 ticks *= 4;
4357
4358         adapter = info->adapter;
4359
4360         regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
4361         regval = (regval & ~0xffff) | (ticks & 0xffff);
4362         /* Handle a few special cases. */
4363         switch (info->offset) {
4364         case E1000_RDTR:
4365                 break;
4366         case E1000_TIDV:
4367                 if (ticks == 0) {
4368                         adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
4369                         /* Don't write 0 into the TIDV register. */
4370                         regval++;
4371                 } else
4372                         adapter->txd_cmd |= E1000_TXD_CMD_IDE;
4373                 break;
4374         }
4375         E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
4376         return (0);
4377 }
4378
4379 static void
4380 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
4381         const char *description, struct em_int_delay_info *info,
4382         int offset, int value)
4383 {
4384         info->adapter = adapter;
4385         info->offset = offset;
4386         info->value = value;
4387         SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev),
4388             SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4389             OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
4390             info, 0, em_sysctl_int_delay, "I", description);
4391 }
4392
4393 /*
4394  * Set flow control using sysctl:
4395  * Flow control values:
4396  *      0 - off
4397  *      1 - rx pause
4398  *      2 - tx pause
4399  *      3 - full
4400  */
4401 static int
4402 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4403 {
4404         int error;
4405         static int input = 3; /* default is full */
4406         struct adapter  *adapter = (struct adapter *) arg1;
4407
4408         error = sysctl_handle_int(oidp, &input, 0, req);
4409
4410         if ((error) || (req->newptr == NULL))
4411                 return (error);
4412
4413         if (input == adapter->fc) /* no change? */
4414                 return (error);
4415
4416         switch (input) {
4417         case e1000_fc_rx_pause:
4418         case e1000_fc_tx_pause:
4419         case e1000_fc_full:
4420         case e1000_fc_none:
4421                 adapter->hw.fc.requested_mode = input;
4422                 adapter->fc = input;
4423                 break;
4424         default:
4425                 /* Do nothing */
4426                 return (error);
4427         }
4428
4429         adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
4430         e1000_force_mac_fc(&adapter->hw);
4431         return (error);
4432 }
4433
4434 /*
4435  * Manage Energy Efficient Ethernet:
4436  * Control values:
4437  *     0/1 - enabled/disabled
4438  */
4439 static int
4440 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4441 {
4442         struct adapter *adapter = (struct adapter *) arg1;
4443         int error, value;
4444
4445         value = adapter->hw.dev_spec.ich8lan.eee_disable;
4446         error = sysctl_handle_int(oidp, &value, 0, req);
4447         if (error || req->newptr == NULL)
4448                 return (error);
4449         adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4450         em_if_init(adapter->ctx);
4451
4452         return (0);
4453 }
4454
4455 static int
4456 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4457 {
4458         struct adapter *adapter;
4459         int error;
4460         int result;
4461
4462         result = -1;
4463         error = sysctl_handle_int(oidp, &result, 0, req);
4464
4465         if (error || !req->newptr)
4466                 return (error);
4467
4468         if (result == 1) {
4469                 adapter = (struct adapter *) arg1;
4470                 em_print_debug_info(adapter);
4471         }
4472
4473         return (error);
4474 }
4475
4476 static int
4477 em_get_rs(SYSCTL_HANDLER_ARGS)
4478 {
4479         struct adapter *adapter = (struct adapter *) arg1;
4480         int error;
4481         int result;
4482
4483         result = 0;
4484         error = sysctl_handle_int(oidp, &result, 0, req);
4485
4486         if (error || !req->newptr || result != 1)
4487                 return (error);
4488         em_dump_rs(adapter);
4489
4490         return (error);
4491 }
4492
4493 static void
4494 em_if_debug(if_ctx_t ctx)
4495 {
4496         em_dump_rs(iflib_get_softc(ctx));
4497 }
4498
4499 /*
4500  * This routine is meant to be fluid, add whatever is
4501  * needed for debugging a problem.  -jfv
4502  */
4503 static void
4504 em_print_debug_info(struct adapter *adapter)
4505 {
4506         device_t dev = iflib_get_dev(adapter->ctx);
4507         struct ifnet *ifp = iflib_get_ifp(adapter->ctx);
4508         struct tx_ring *txr = &adapter->tx_queues->txr;
4509         struct rx_ring *rxr = &adapter->rx_queues->rxr;
4510
4511         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
4512                 printf("Interface is RUNNING ");
4513         else
4514                 printf("Interface is NOT RUNNING\n");
4515
4516         if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
4517                 printf("and INACTIVE\n");
4518         else
4519                 printf("and ACTIVE\n");
4520
4521         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
4522                 device_printf(dev, "TX Queue %d ------\n", i);
4523                 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
4524                         E1000_READ_REG(&adapter->hw, E1000_TDH(i)),
4525                         E1000_READ_REG(&adapter->hw, E1000_TDT(i)));
4526
4527         }
4528         for (int j=0; j < adapter->rx_num_queues; j++, rxr++) {
4529                 device_printf(dev, "RX Queue %d ------\n", j);
4530                 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
4531                         E1000_READ_REG(&adapter->hw, E1000_RDH(j)),
4532                         E1000_READ_REG(&adapter->hw, E1000_RDT(j)));
4533         }
4534 }
4535
4536 /*
4537  * 82574 only:
4538  * Write a new value to the EEPROM increasing the number of MSIX
4539  * vectors from 3 to 5, for proper multiqueue support.
4540  */
4541 static void
4542 em_enable_vectors_82574(if_ctx_t ctx)
4543 {
4544         struct adapter *adapter = iflib_get_softc(ctx);
4545         struct e1000_hw *hw = &adapter->hw;
4546         device_t dev = iflib_get_dev(ctx);
4547         u16 edata;
4548
4549         e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4550         printf("Current cap: %#06x\n", edata);
4551         if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
4552                 device_printf(dev, "Writing to eeprom: increasing "
4553                     "reported MSIX vectors from 3 to 5...\n");
4554                 edata &= ~(EM_NVM_MSIX_N_MASK);
4555                 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
4556                 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4557                 e1000_update_nvm_checksum(hw);
4558                 device_printf(dev, "Writing to eeprom: done\n");
4559         }
4560 }