sys/dev/e1000/if_em.c

   1 /*-
   2  * Copyright (c) 2016 Matt Macy <mmacy@nextbsd.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 /* $FreeBSD$ */
  28 #include "if_em.h"
  29 #include <sys/sbuf.h>
  30 #include <machine/_inttypes.h>
  31
  32 #define em_mac_min e1000_82547
  33 #define igb_mac_min e1000_82575
  34
  35 /*********************************************************************
  36  *  Driver version:
  37  *********************************************************************/
  38 char em_driver_version[] = "7.6.1-k";
  39
  40 /*********************************************************************
  41  *  PCI Device ID Table
  42  *
  43  *  Used by probe to select devices to load on
  44  *  Last field stores an index into e1000_strings
  45  *  Last entry must be all 0s
  46  *
  47  *  { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
  48  *********************************************************************/
  49
  50 static pci_vendor_info_t em_vendor_info_array[] =
  51 {
  52         /* Intel(R) PRO/1000 Network Connection - Legacy em*/
  53         PVID(0x8086, E1000_DEV_ID_82540EM,  "Intel(R) PRO/1000 Network Connection"),
  54         PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"),
  55         PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"),
  56         PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"),
  57         PVID(0x8086, E1000_DEV_ID_82540EP_LP,  "Intel(R) PRO/1000 Network Connection"),
  58
  59         PVID(0x8086, E1000_DEV_ID_82541EI,  "Intel(R) PRO/1000 Network Connection"),
  60         PVID(0x8086, E1000_DEV_ID_82541ER,  "Intel(R) PRO/1000 Network Connection"),
  61         PVID(0x8086, E1000_DEV_ID_82541ER_LOM,  "Intel(R) PRO/1000 Network Connection"),
  62         PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE,   "Intel(R) PRO/1000 Network Connection"),
  63         PVID(0x8086, E1000_DEV_ID_82541GI,   "Intel(R) PRO/1000 Network Connection"),
  64         PVID(0x8086, E1000_DEV_ID_82541GI_LF,   "Intel(R) PRO/1000 Network Connection"),
  65         PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE,  "Intel(R) PRO/1000 Network Connection"),
  66
  67         PVID(0x8086, E1000_DEV_ID_82542,  "Intel(R) PRO/1000 Network Connection"),
  68
  69         PVID(0x8086, E1000_DEV_ID_82543GC_FIBER,  "Intel(R) PRO/1000 Network Connection"),
  70         PVID(0x8086, E1000_DEV_ID_82543GC_COPPER,  "Intel(R) PRO/1000 Network Connection"),
  71
  72         PVID(0x8086, E1000_DEV_ID_82544EI_COPPER,  "Intel(R) PRO/1000 Network Connection"),
  73         PVID(0x8086, E1000_DEV_ID_82544EI_FIBER,  "Intel(R) PRO/1000 Network Connection"),
  74         PVID(0x8086, E1000_DEV_ID_82544GC_COPPER,  "Intel(R) PRO/1000 Network Connection"),
  75         PVID(0x8086, E1000_DEV_ID_82544GC_LOM,  "Intel(R) PRO/1000 Network Connection"),
  76
  77         PVID(0x8086, E1000_DEV_ID_82545EM_COPPER,  "Intel(R) PRO/1000 Network Connection"),
  78         PVID(0x8086, E1000_DEV_ID_82545EM_FIBER,  "Intel(R) PRO/1000 Network Connection"),
  79         PVID(0x8086, E1000_DEV_ID_82545GM_COPPER,  "Intel(R) PRO/1000 Network Connection"),
  80         PVID(0x8086, E1000_DEV_ID_82545GM_FIBER,  "Intel(R) PRO/1000 Network Connection"),
  81         PVID(0x8086, E1000_DEV_ID_82545GM_SERDES,  "Intel(R) PRO/1000 Network Connection"),
  82
  83         PVID(0x8086, E1000_DEV_ID_82546EB_COPPER,  "Intel(R) PRO/1000 Network Connection"),
  84         PVID(0x8086, E1000_DEV_ID_82546EB_FIBER,  "Intel(R) PRO/1000 Network Connection"),
  85         PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER,  "Intel(R) PRO/1000 Network Connection"),
  86         PVID(0x8086, E1000_DEV_ID_82546GB_COPPER,  "Intel(R) PRO/1000 Network Connection"),
  87         PVID(0x8086, E1000_DEV_ID_82546GB_FIBER,  "Intel(R) PRO/1000 Network Connection"),
  88         PVID(0x8086, E1000_DEV_ID_82546GB_SERDES,  "Intel(R) PRO/1000 Network Connection"),
  89         PVID(0x8086, E1000_DEV_ID_82546GB_PCIE,  "Intel(R) PRO/1000 Network Connection"),
  90         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER,  "Intel(R) PRO/1000 Network Connection"),
  91         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3,  "Intel(R) PRO/1000 Network Connection"),
  92
  93         PVID(0x8086, E1000_DEV_ID_82547EI,  "Intel(R) PRO/1000 Network Connection"),
  94         PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE,  "Intel(R) PRO/1000 Network Connection"),
  95         PVID(0x8086, E1000_DEV_ID_82547GI,  "Intel(R) PRO/1000 Network Connection"),
  96
  97         /* Intel(R) PRO/1000 Network Connection - em */
  98         PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  99         PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
 100         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"),
 101         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"),
 102         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"),
 103         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 104         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"),
 105         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"),
 106         PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 107         PVID(0x8086, E1000_DEV_ID_82572EI_COPPER,       "Intel(R) PRO/1000 Network Connection"),
 108         PVID(0x8086, E1000_DEV_ID_82572EI_FIBER,        "Intel(R) PRO/1000 Network Connection"),
 109         PVID(0x8086, E1000_DEV_ID_82572EI_SERDES,       "Intel(R) PRO/1000 Network Connection"),
 110         PVID(0x8086, E1000_DEV_ID_82573E,               "Intel(R) PRO/1000 Network Connection"),
 111         PVID(0x8086, E1000_DEV_ID_82573E_IAMT,  "Intel(R) PRO/1000 Network Connection"),
 112         PVID(0x8086, E1000_DEV_ID_82573L,               "Intel(R) PRO/1000 Network Connection"),
 113         PVID(0x8086, E1000_DEV_ID_82583V,               "Intel(R) PRO/1000 Network Connection"),
 114         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"),
 115         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"),
 116         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"),
 117         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"),
 118         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT,       "Intel(R) PRO/1000 Network Connection"),
 119         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 120         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C,   "Intel(R) PRO/1000 Network Connection"),
 121         PVID(0x8086, E1000_DEV_ID_ICH8_IFE,     "Intel(R) PRO/1000 Network Connection"),
 122         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT,  "Intel(R) PRO/1000 Network Connection"),
 123         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G,   "Intel(R) PRO/1000 Network Connection"),
 124         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M,   "Intel(R) PRO/1000 Network Connection"),
 125         PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3,        "Intel(R) PRO/1000 Network Connection"),
 126         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT,       "Intel(R) PRO/1000 Network Connection"),
 127         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 128         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C,   "Intel(R) PRO/1000 Network Connection"),
 129         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M,   "Intel(R) PRO/1000 Network Connection"),
 130         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"),
 131         PVID(0x8086, E1000_DEV_ID_ICH9_IFE,     "Intel(R) PRO/1000 Network Connection"),
 132         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT,  "Intel(R) PRO/1000 Network Connection"),
 133         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G,   "Intel(R) PRO/1000 Network Connection"),
 134         PVID(0x8086, E1000_DEV_ID_ICH9_BM,              "Intel(R) PRO/1000 Network Connection"),
 135         PVID(0x8086, E1000_DEV_ID_82574L,               "Intel(R) PRO/1000 Network Connection"),
 136         PVID(0x8086, E1000_DEV_ID_82574LA,              "Intel(R) PRO/1000 Network Connection"),
 137         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM,        "Intel(R) PRO/1000 Network Connection"),
 138         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF,        "Intel(R) PRO/1000 Network Connection"),
 139         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"),
 140         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM,        "Intel(R) PRO/1000 Network Connection"),
 141         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF,        "Intel(R) PRO/1000 Network Connection"),
 142         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"),
 143         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM,  "Intel(R) PRO/1000 Network Connection"),
 144         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC,  "Intel(R) PRO/1000 Network Connection"),
 145         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM,  "Intel(R) PRO/1000 Network Connection"),
 146         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC,  "Intel(R) PRO/1000 Network Connection"),
 147         PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM,   "Intel(R) PRO/1000 Network Connection"),
 148         PVID(0x8086, E1000_DEV_ID_PCH2_LV_V,    "Intel(R) PRO/1000 Network Connection"),
 149         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM,      "Intel(R) PRO/1000 Network Connection"),
 150         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V,       "Intel(R) PRO/1000 Network Connection"),
 151         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"),
 152         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"),
 153         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"),
 154         PVID(0x8086, E1000_DEV_ID_PCH_I218_V2,  "Intel(R) PRO/1000 Network Connection"),
 155         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"),
 156         PVID(0x8086, E1000_DEV_ID_PCH_I218_V3,  "Intel(R) PRO/1000 Network Connection"),
 157         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"),
 158         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V,  "Intel(R) PRO/1000 Network Connection"),
 159         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"),
 160         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"),
 161         PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"),
 162         /* required last entry */
 163         PVID_END
 164 };
 165
 166 static pci_vendor_info_t igb_vendor_info_array[] =
 167 {
 168         /* Intel(R) PRO/1000 Network Connection - em */
 169         PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 170         PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 171         PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 172         PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 173         PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 174         PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 175         PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 176         PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 177         PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 178         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 179         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 180         PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 181         PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 182         PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 183         PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 184         PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 185         PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 186         PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 187         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 188         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 189         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 190         PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 191         PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 192         PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 193         PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 194         PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 195         PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 196         PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 197         PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 198         PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 199         PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 200         PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 201         PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 202         PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 203         PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 204         PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 205         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 206         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 207         PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 208         /* required last entry */
 209         PVID_END
 210 };
 211
 212 /*********************************************************************
 213  *  Function prototypes
 214  *********************************************************************/
 215 static void     *em_register(device_t dev);
 216 static void     *igb_register(device_t dev);
 217 static int      em_if_attach_pre(if_ctx_t ctx);
 218 static int      em_if_attach_post(if_ctx_t ctx);
 219 static int      em_if_detach(if_ctx_t ctx);
 220 static int      em_if_shutdown(if_ctx_t ctx);
 221 static int      em_if_suspend(if_ctx_t ctx);
 222 static int      em_if_resume(if_ctx_t ctx);
 223
 224 static int      em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets);
 225 static int      em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets);
 226 static void     em_if_queues_free(if_ctx_t ctx);
 227
 228 static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
 229 static void     em_if_init(if_ctx_t ctx);
 230 static void     em_if_stop(if_ctx_t ctx);
 231 static void     em_if_media_status(if_ctx_t, struct ifmediareq *);
 232 static int      em_if_media_change(if_ctx_t ctx);
 233 static int      em_if_mtu_set(if_ctx_t ctx, uint32_t mtu);
 234 static void     em_if_timer(if_ctx_t ctx, uint16_t qid);
 235 static void     em_if_vlan_register(if_ctx_t ctx, u16 vtag);
 236 static void     em_if_vlan_unregister(if_ctx_t ctx, u16 vtag);
 237
 238 static void     em_identify_hardware(if_ctx_t ctx);
 239 static int      em_allocate_pci_resources(if_ctx_t ctx);
 240 static void     em_free_pci_resources(if_ctx_t ctx);
 241 static void     em_reset(if_ctx_t ctx);
 242 static int      em_setup_interface(if_ctx_t ctx);
 243 static int      em_setup_msix(if_ctx_t ctx);
 244
 245 static void     em_initialize_transmit_unit(if_ctx_t ctx);
 246 static void     em_initialize_receive_unit(if_ctx_t ctx);
 247
 248 static void     em_if_enable_intr(if_ctx_t ctx);
 249 static void     em_if_disable_intr(if_ctx_t ctx);
 250 static int      em_if_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 251 static void     em_if_multi_set(if_ctx_t ctx);
 252 static void     em_if_update_admin_status(if_ctx_t ctx);
 253 static void     em_update_stats_counters(struct adapter *);
 254 static void     em_add_hw_stats(struct adapter *adapter);
 255 static int      em_if_set_promisc(if_ctx_t ctx, int flags);
 256 static void     em_setup_vlan_hw_support(struct adapter *);
 257 static int      em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
 258 static void     em_print_nvm_info(struct adapter *);
 259 static int      em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 260 static void     em_print_debug_info(struct adapter *);
 261 static int      em_is_valid_ether_addr(u8 *);
 262 static int      em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
 263 static void     em_add_int_delay_sysctl(struct adapter *, const char *,
 264                     const char *, struct em_int_delay_info *, int, int);
 265 /* Management and WOL Support */
 266 static void     em_init_manageability(struct adapter *);
 267 static void     em_release_manageability(struct adapter *);
 268 static void     em_get_hw_control(struct adapter *);
 269 static void     em_release_hw_control(struct adapter *);
 270 static void     em_get_wakeup(if_ctx_t ctx);
 271 static void     em_enable_wakeup(if_ctx_t ctx);
 272 static int      em_enable_phy_wakeup(struct adapter *);
 273 static void     em_disable_aspm(struct adapter *);
 274
 275 int             em_intr(void *arg);
 276 static void     em_disable_promisc(if_ctx_t ctx);
 277
 278 /* MSIX handlers */
 279 static int      em_if_msix_intr_assign(if_ctx_t, int);
 280 static int      em_msix_link(void *);
 281 static void     em_handle_link(void *context);
 282
 283 static void     em_enable_vectors_82574(if_ctx_t);
 284
 285 static void     em_set_sysctl_value(struct adapter *, const char *,
 286                     const char *, int *, int);
 287 static int      em_set_flowcntl(SYSCTL_HANDLER_ARGS);
 288 static int      em_sysctl_eee(SYSCTL_HANDLER_ARGS);
 289 static void     em_if_led_func(if_ctx_t ctx, int onoff);
 290
 291 static void     em_init_tx_ring(struct em_tx_queue *que);
 292 static int      em_get_regs(SYSCTL_HANDLER_ARGS);
 293
 294 static void     lem_smartspeed(struct adapter *adapter);
 295 static void     igb_configure_queues(struct adapter *adapter);
 296
 297
 298 /*********************************************************************
 299  *  FreeBSD Device Interface Entry Points
 300  *********************************************************************/
 301 static device_method_t em_methods[] = {
 302         /* Device interface */
 303   DEVMETHOD(device_register, em_register),
 304   DEVMETHOD(device_probe, iflib_device_probe),
 305   DEVMETHOD(device_attach, iflib_device_attach),
 306   DEVMETHOD(device_detach, iflib_device_detach),
 307   DEVMETHOD(device_shutdown, iflib_device_shutdown),
 308   DEVMETHOD(device_suspend, iflib_device_suspend),
 309   DEVMETHOD(device_resume, iflib_device_resume),
 310   DEVMETHOD_END
 311 };
 312
 313 static device_method_t igb_methods[] = {
 314         /* Device interface */
 315   DEVMETHOD(device_register, igb_register),
 316   DEVMETHOD(device_probe, iflib_device_probe),
 317   DEVMETHOD(device_attach, iflib_device_attach),
 318   DEVMETHOD(device_detach, iflib_device_detach),
 319   DEVMETHOD(device_shutdown, iflib_device_shutdown),
 320   DEVMETHOD(device_suspend, iflib_device_suspend),
 321   DEVMETHOD(device_resume, iflib_device_resume),
 322   DEVMETHOD_END
 323 };
 324
 325
 326 static driver_t em_driver = {
 327         "em", em_methods, sizeof(struct adapter),
 328 };
 329
 330 static devclass_t em_devclass;
 331 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
 332
 333 MODULE_DEPEND(em, pci, 1, 1, 1);
 334 MODULE_DEPEND(em, ether, 1, 1, 1);
 335 MODULE_DEPEND(em, iflib, 1, 1, 1);
 336
 337 static driver_t igb_driver = {
 338         "igb", igb_methods, sizeof(struct adapter),
 339 };
 340
 341 static devclass_t igb_devclass;
 342 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
 343
 344 MODULE_DEPEND(igb, pci, 1, 1, 1);
 345 MODULE_DEPEND(igb, ether, 1, 1, 1);
 346 MODULE_DEPEND(igb, iflib, 1, 1, 1);
 347
 348
 349 static device_method_t em_if_methods[] = {
 350         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 351         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 352         DEVMETHOD(ifdi_detach, em_if_detach),
 353         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 354         DEVMETHOD(ifdi_suspend, em_if_suspend),
 355         DEVMETHOD(ifdi_resume, em_if_resume),
 356         DEVMETHOD(ifdi_init, em_if_init),
 357         DEVMETHOD(ifdi_stop, em_if_stop),
 358         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 359         DEVMETHOD(ifdi_intr_enable, em_if_enable_intr),
 360         DEVMETHOD(ifdi_intr_disable, em_if_disable_intr),
 361         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 362         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 363         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 364         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 365         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 366         DEVMETHOD(ifdi_media_status, em_if_media_status),
 367         DEVMETHOD(ifdi_media_change, em_if_media_change),
 368         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 369         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 370         DEVMETHOD(ifdi_timer, em_if_timer),
 371         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 372         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 373         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 374         DEVMETHOD(ifdi_led_func, em_if_led_func),
 375         DEVMETHOD(ifdi_queue_intr_enable, em_if_queue_intr_enable),
 376         DEVMETHOD_END
 377 };
 378
 379   /*
 380  * note that if (adapter->msix_mem) is replaced by:
 381  * if (adapter->intr_type == IFLIB_INTR_MSIX)
 382  */
 383 static driver_t em_if_driver = {
 384   "em_if", em_if_methods, sizeof(struct adapter)
 385 };
 386
 387 /*********************************************************************
 388  *  Tunable default values.
 389  *********************************************************************/
 390
 391 #define EM_TICKS_TO_USECS(ticks)        ((1024 * (ticks) + 500) / 1000)
 392 #define EM_USECS_TO_TICKS(usecs)        ((1000 * (usecs) + 512) / 1024)
 393 #define M_TSO_LEN                       66
 394
 395 #define MAX_INTS_PER_SEC        8000
 396 #define DEFAULT_ITR             (1000000000/(MAX_INTS_PER_SEC * 256))
 397
 398 /* Allow common code without TSO */
 399 #ifndef CSUM_TSO
 400 #define CSUM_TSO        0
 401 #endif
 402
 403 #define TSO_WORKAROUND  4
 404
 405 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters");
 406
 407 static int em_disable_crc_stripping = 0;
 408 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
 409     &em_disable_crc_stripping, 0, "Disable CRC Stripping");
 410
 411 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
 412 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
 413 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
 414     0, "Default transmit interrupt delay in usecs");
 415 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
 416     0, "Default receive interrupt delay in usecs");
 417
 418 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
 419 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
 420 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
 421     &em_tx_abs_int_delay_dflt, 0,
 422     "Default transmit interrupt delay limit in usecs");
 423 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
 424     &em_rx_abs_int_delay_dflt, 0,
 425     "Default receive interrupt delay limit in usecs");
 426
 427 static int em_smart_pwr_down = FALSE;
 428 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
 429     0, "Set to true to leave smart power down enabled on newer adapters");
 430
 431 /* Controls whether promiscuous also shows bad packets */
 432 static int em_debug_sbp = TRUE;
 433 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
 434     "Show bad packets in promiscuous mode");
 435
 436 /* How many packets rxeof tries to clean at a time */
 437 static int em_rx_process_limit = 100;
 438 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
 439     &em_rx_process_limit, 0,
 440     "Maximum number of received packets to process "
 441     "at a time, -1 means unlimited");
 442
 443 /* Energy efficient ethernet - default to OFF */
 444 static int eee_setting = 1;
 445 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
 446     "Enable Energy Efficient Ethernet");
 447
 448 /*
 449 ** Tuneable Interrupt rate
 450 */
 451 static int em_max_interrupt_rate = 8000;
 452 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
 453     &em_max_interrupt_rate, 0, "Maximum interrupts per second");
 454
 455
 456
 457 /* Global used in WOL setup with multiport cards */
 458 static int global_quad_port_a = 0;
 459
 460 extern struct if_txrx igb_txrx;
 461 extern struct if_txrx em_txrx;
 462 extern struct if_txrx lem_txrx;
 463
 464 static struct if_shared_ctx em_sctx_init = {
 465         .isc_magic = IFLIB_MAGIC,
 466         .isc_q_align = PAGE_SIZE,
 467         .isc_tx_maxsize = EM_TSO_SIZE,
 468         .isc_tx_maxsegsize = PAGE_SIZE,
 469         .isc_rx_maxsize = MJUM9BYTES,
 470         .isc_rx_nsegments = 1,
 471         .isc_rx_maxsegsize = MJUM9BYTES,
 472         .isc_nfl = 1,
 473         .isc_nrxqs = 1,
 474         .isc_ntxqs = 1,
 475         .isc_admin_intrcnt = 1,
 476         .isc_vendor_info = em_vendor_info_array,
 477         .isc_driver_version = em_driver_version,
 478         .isc_driver = &em_if_driver,
 479         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP,
 480
 481         .isc_nrxd_min = {EM_MIN_RXD},
 482         .isc_ntxd_min = {EM_MIN_TXD},
 483         .isc_nrxd_max = {EM_MAX_RXD},
 484         .isc_ntxd_max = {EM_MAX_TXD},
 485         .isc_nrxd_default = {EM_DEFAULT_RXD},
 486         .isc_ntxd_default = {EM_DEFAULT_TXD},
 487 };
 488
 489 if_shared_ctx_t em_sctx = &em_sctx_init;
 490
 491
 492 static struct if_shared_ctx igb_sctx_init = {
 493         .isc_magic = IFLIB_MAGIC,
 494         .isc_q_align = PAGE_SIZE,
 495         .isc_tx_maxsize = EM_TSO_SIZE,
 496         .isc_tx_maxsegsize = PAGE_SIZE,
 497         .isc_rx_maxsize = MJUM9BYTES,
 498         .isc_rx_nsegments = 1,
 499         .isc_rx_maxsegsize = MJUM9BYTES,
 500         .isc_nfl = 1,
 501         .isc_nrxqs = 1,
 502         .isc_ntxqs = 1,
 503         .isc_admin_intrcnt = 1,
 504         .isc_vendor_info = igb_vendor_info_array,
 505         .isc_driver_version = em_driver_version,
 506         .isc_driver = &em_if_driver,
 507         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP,
 508
 509         .isc_nrxd_min = {EM_MIN_RXD},
 510         .isc_ntxd_min = {EM_MIN_TXD},
 511         .isc_nrxd_max = {EM_MAX_RXD},
 512         .isc_ntxd_max = {EM_MAX_TXD},
 513         .isc_nrxd_default = {EM_DEFAULT_RXD},
 514         .isc_ntxd_default = {EM_DEFAULT_TXD},
 515 };
 516
 517 if_shared_ctx_t igb_sctx = &igb_sctx_init;
 518
 519 /*****************************************************************
 520  *
 521  * Dump Registers
 522  *
 523  ****************************************************************/
 524 #define IGB_REGS_LEN 739
 525
 526 static int em_get_regs(SYSCTL_HANDLER_ARGS)
 527 {
 528         struct adapter *adapter = (struct adapter *)arg1;
 529         struct e1000_hw *hw = &adapter->hw;
 530
 531         struct sbuf *sb;
 532         u32 *regs_buff = (u32 *)malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_NOWAIT);
 533         int rc;
 534
 535         memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
 536
 537         rc = sysctl_wire_old_buffer(req, 0);
 538         MPASS(rc == 0);
 539         if (rc != 0)
 540           return (rc);
 541
 542         sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
 543         MPASS(sb != NULL);
 544         if (sb == NULL)
 545                 return (ENOMEM);
 546
 547         /* General Registers */
 548         regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
 549         regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
 550         regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
 551         regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
 552         regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
 553         regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
 554         regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
 555         regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
 556         regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
 557         regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
 558         regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
 559         regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
 560         regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
 561         regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
 562         regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
 563         regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
 564         regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
 565         regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
 566         regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
 567         regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
 568         regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
 569         regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
 570
 571         sbuf_printf(sb, "General Registers\n");
 572         sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
 573         sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
 574         sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]);
 575
 576         sbuf_printf(sb, "Interrupt Registers\n");
 577         sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
 578
 579         sbuf_printf(sb, "RX Registers\n");
 580         sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
 581         sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
 582         sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
 583         sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
 584         sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
 585         sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
 586         sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
 587
 588         sbuf_printf(sb, "TX Registers\n");
 589         sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
 590         sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
 591         sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
 592         sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
 593         sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
 594         sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
 595         sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
 596         sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
 597         sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
 598         sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
 599         sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
 600
 601 #ifdef DUMP_DESCS
 602         {
 603                 if_softc_ctx_t scctx = adapter->shared;
 604                 struct rx_ring *rxr = &rx_que->rxr;
 605                 struct tx_ring *txr = &tx_que->txr;
 606                 int ntxd = scctx->isc_ntxd[0];
 607                 int nrxd = scctx->isc_nrxd[0];
 608                 int j;
 609
 610         for (j = 0; j < nrxd; j++) {
 611                 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
 612                 u32 length =  le32toh(rxr->rx_base[j].wb.upper.length);
 613                 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 "  Error:%d  Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
 614         }
 615
 616         for (j = 0; j < min(ntxd, 256); j++) {
 617                 struct em_txbuffer *buf = &txr->tx_buffers[j];
 618                 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
 619
 620                 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x  eop: %d DD=%d\n",
 621                             j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
 622                             buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
 623
 624         }
 625         }
 626 #endif
 627
 628         rc = sbuf_finish(sb);
 629         sbuf_delete(sb);
 630         return(rc);
 631 }
 632
 633 static void *
 634 em_register(device_t dev)
 635 {
 636         return (em_sctx);
 637 }
 638
 639 static void *
 640 igb_register(device_t dev)
 641 {
 642         return (igb_sctx);
 643 }
 644
 645 static void
 646 em_init_tx_ring(struct em_tx_queue *que)
 647 {
 648         struct adapter *sc = que->adapter;
 649         if_softc_ctx_t scctx = sc->shared;
 650         struct tx_ring *txr = &que->txr;
 651         struct em_txbuffer *tx_buffer;
 652
 653         tx_buffer = txr->tx_buffers;
 654         for (int i = 0; i < scctx->isc_ntxd[0]; i++, tx_buffer++) {
 655                 tx_buffer->eop = -1;
 656         }
 657 }
 658
 659 static int
 660 em_set_num_queues(if_ctx_t ctx)
 661 {
 662         struct adapter *adapter = iflib_get_softc(ctx);
 663         int maxqueues;
 664
 665         /* Sanity check based on HW */
 666         switch (adapter->hw.mac.type) {
 667                 case e1000_82576:
 668                 case e1000_82580:
 669                 case e1000_i350:
 670                 case e1000_i354:
 671                         maxqueues = 8;
 672                         break;
 673                 case e1000_i210:
 674                 case e1000_82575:
 675                         maxqueues = 4;
 676                         break;
 677                 case e1000_i211:
 678                 case e1000_82574:
 679                         maxqueues = 2;
 680                         break;
 681                 default:
 682                         maxqueues = 1;
 683                         break;
 684         }
 685
 686         return (maxqueues);
 687 }
 688
 689
 690 #define EM_CAPS                                                         \
 691         IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \
 692         IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | \
 693         IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU;
 694
 695 #define IGB_CAPS                                                        \
 696         IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \
 697         IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM | \
 698         IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU | IFCAP_TXCSUM_IPV6 | IFCAP_HWCSUM_IPV6 | IFCAP_JUMBO_MTU;
 699
 700 /*********************************************************************
 701  *  Device initialization routine
 702  *
 703  *  The attach entry point is called when the driver is being loaded.
 704  *  This routine identifies the type of hardware, allocates all resources
 705  *  and initializes the hardware.
 706  *
 707  *  return 0 on success, positive on failure
 708  *********************************************************************/
 709
 710 static int
 711 em_if_attach_pre(if_ctx_t ctx)
 712 {
 713         struct adapter  *adapter;
 714         if_softc_ctx_t scctx;
 715         device_t        dev;
 716         struct e1000_hw *hw;
 717         int             error = 0;
 718
 719         INIT_DEBUGOUT("em_if_attach_pre begin");
 720         dev = iflib_get_dev(ctx);
 721         adapter = iflib_get_softc(ctx);
 722
 723         if (resource_disabled("em", device_get_unit(dev))) {
 724                 device_printf(dev, "Disabled by device hint\n");
 725                 return (ENXIO);
 726         }
 727
 728         adapter->ctx = ctx;
 729         adapter->dev = adapter->osdep.dev = dev;
 730         scctx = adapter->shared = iflib_get_softc_ctx(ctx);
 731         adapter->media = iflib_get_media(ctx);
 732         hw = &adapter->hw;
 733
 734         adapter->tx_process_limit = scctx->isc_ntxd[0];
 735
 736         /* SYSCTL stuff */
 737         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 738             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 739             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 740             em_sysctl_nvm_info, "I", "NVM Information");
 741
 742         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 743             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 744             OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 745             em_sysctl_debug_info, "I", "Debug Information");
 746
 747         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 748             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 749             OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 750             em_set_flowcntl, "I", "Flow Control");
 751
 752         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 753             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 754             OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0,
 755             em_get_regs, "A", "Dump Registers");
 756
 757         /* Determine hardware and mac info */
 758         em_identify_hardware(ctx);
 759
 760         /* Set isc_msix_bar */
 761         scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR);
 762         scctx->isc_tx_nsegments = EM_MAX_SCATTER;
 763         scctx->isc_tx_tso_segments_max = scctx->isc_tx_nsegments;
 764         scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 765         scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 766         scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
 767         device_printf(dev, "attach_pre capping queues at %d\n", scctx->isc_ntxqsets_max);
 768
 769         scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 770
 771
 772         if (adapter->hw.mac.type >= igb_mac_min) {
 773                 int try_second_bar;
 774
 775                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
 776                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
 777                 scctx->isc_txrx = &igb_txrx;
 778                 scctx->isc_capenable = IGB_CAPS;
 779                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | CSUM_IP6_TCP \
 780                         | CSUM_IP6_UDP | CSUM_IP6_TCP;
 781                 if (adapter->hw.mac.type != e1000_82575)
 782                         scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
 783
 784                 /*
 785                 ** Some new devices, as with ixgbe, now may
 786                 ** use a different BAR, so we need to keep
 787                 ** track of which is used.
 788                 */
 789                 try_second_bar = pci_read_config(dev, scctx->isc_msix_bar, 4);
 790                 if (try_second_bar == 0)
 791                         scctx->isc_msix_bar += 4;
 792
 793         } else if (adapter->hw.mac.type >= em_mac_min) {
 794                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 795                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
 796                 scctx->isc_txrx = &em_txrx;
 797                 scctx->isc_capenable = EM_CAPS;
 798                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 799         } else {
 800                 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 801                 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
 802                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 803                 scctx->isc_txrx = &lem_txrx;
 804                 scctx->isc_capenable = EM_CAPS;
 805                 if (adapter->hw.mac.type < e1000_82543)
 806                         scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
 807                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 808                 scctx->isc_msix_bar = 0;
 809         }
 810
 811         /* Setup PCI resources */
 812         if (em_allocate_pci_resources(ctx)) {
 813                 device_printf(dev, "Allocation of PCI resources failed\n");
 814                 error = ENXIO;
 815                 goto err_pci;
 816         }
 817
 818         /*
 819         ** For ICH8 and family we need to
 820         ** map the flash memory, and this
 821         ** must happen after the MAC is
 822         ** identified
 823         */
 824         if ((hw->mac.type == e1000_ich8lan) ||
 825             (hw->mac.type == e1000_ich9lan) ||
 826             (hw->mac.type == e1000_ich10lan) ||
 827             (hw->mac.type == e1000_pchlan) ||
 828             (hw->mac.type == e1000_pch2lan) ||
 829             (hw->mac.type == e1000_pch_lpt)) {
 830                 int rid = EM_BAR_TYPE_FLASH;
 831                 adapter->flash = bus_alloc_resource_any(dev,
 832                     SYS_RES_MEMORY, &rid, RF_ACTIVE);
 833                 if (adapter->flash == NULL) {
 834                         device_printf(dev, "Mapping of Flash failed\n");
 835                         error = ENXIO;
 836                         goto err_pci;
 837                 }
 838                 /* This is used in the shared code */
 839                 hw->flash_address = (u8 *)adapter->flash;
 840                 adapter->osdep.flash_bus_space_tag =
 841                     rman_get_bustag(adapter->flash);
 842                 adapter->osdep.flash_bus_space_handle =
 843                     rman_get_bushandle(adapter->flash);
 844         }
 845         /*
 846         ** In the new SPT device flash is not  a
 847         ** separate BAR, rather it is also in BAR0,
 848         ** so use the same tag and an offset handle for the
 849         ** FLASH read/write macros in the shared code.
 850         */
 851         else if (hw->mac.type == e1000_pch_spt) {
 852                 adapter->osdep.flash_bus_space_tag =
 853                     adapter->osdep.mem_bus_space_tag;
 854                 adapter->osdep.flash_bus_space_handle =
 855                     adapter->osdep.mem_bus_space_handle
 856                     + E1000_FLASH_BASE_ADDR;
 857         }
 858
 859         /* Do Shared Code initialization */
 860         error = e1000_setup_init_funcs(hw, TRUE);
 861         if (error) {
 862                 device_printf(dev, "Setup of Shared code failed, error %d\n",
 863                     error);
 864                 error = ENXIO;
 865                 goto err_pci;
 866         }
 867
 868         em_setup_msix(ctx);
 869         e1000_get_bus_info(hw);
 870
 871         /* Set up some sysctls for the tunable interrupt delays */
 872         em_add_int_delay_sysctl(adapter, "rx_int_delay",
 873             "receive interrupt delay in usecs", &adapter->rx_int_delay,
 874             E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
 875         em_add_int_delay_sysctl(adapter, "tx_int_delay",
 876             "transmit interrupt delay in usecs", &adapter->tx_int_delay,
 877             E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
 878         em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
 879             "receive interrupt delay limit in usecs",
 880             &adapter->rx_abs_int_delay,
 881             E1000_REGISTER(hw, E1000_RADV),
 882             em_rx_abs_int_delay_dflt);
 883         em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
 884             "transmit interrupt delay limit in usecs",
 885             &adapter->tx_abs_int_delay,
 886             E1000_REGISTER(hw, E1000_TADV),
 887             em_tx_abs_int_delay_dflt);
 888         em_add_int_delay_sysctl(adapter, "itr",
 889             "interrupt delay limit in usecs/4",
 890             &adapter->tx_itr,
 891             E1000_REGISTER(hw, E1000_ITR),
 892             DEFAULT_ITR);
 893
 894         /* Sysctl for limiting the amount of work done in the taskqueue */
 895         em_set_sysctl_value(adapter, "rx_processing_limit",
 896             "max number of rx packets to process", &adapter->rx_process_limit,
 897             em_rx_process_limit);
 898
 899         hw->mac.autoneg = DO_AUTO_NEG;
 900         hw->phy.autoneg_wait_to_complete = FALSE;
 901         hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 902
 903         if (adapter->hw.mac.type < em_mac_min) {
 904                 e1000_init_script_state_82541(&adapter->hw, TRUE);
 905                 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
 906         }
 907         /* Copper options */
 908         if (hw->phy.media_type == e1000_media_type_copper) {
 909                 hw->phy.mdix = AUTO_ALL_MODES;
 910                 hw->phy.disable_polarity_correction = FALSE;
 911                 hw->phy.ms_type = EM_MASTER_SLAVE;
 912         }
 913
 914         /*
 915          * Set the frame limits assuming
 916          * standard ethernet sized frames.
 917          */
 918         adapter->hw.mac.max_frame_size =
 919             ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
 920
 921         /*
 922          * This controls when hardware reports transmit completion
 923          * status.
 924          */
 925         hw->mac.report_tx_early = 1;
 926
 927         /* Allocate multicast array memory. */
 928         adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN *
 929             MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
 930         if (adapter->mta == NULL) {
 931                 device_printf(dev, "Can not allocate multicast setup array\n");
 932                 error = ENOMEM;
 933                 goto err_late;
 934         }
 935
 936         /* Check SOL/IDER usage */
 937         if (e1000_check_reset_block(hw))
 938                 device_printf(dev, "PHY reset is blocked"
 939                     " due to SOL/IDER session.\n");
 940
 941         /* Sysctl for setting Energy Efficient Ethernet */
 942         hw->dev_spec.ich8lan.eee_disable = eee_setting;
 943         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 944             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 945             OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW,
 946             adapter, 0, em_sysctl_eee, "I",
 947             "Disable Energy Efficient Ethernet");
 948
 949         /*
 950         ** Start from a known state, this is
 951         ** important in reading the nvm and
 952         ** mac from that.
 953         */
 954         e1000_reset_hw(hw);
 955
 956         /* Make sure we have a good EEPROM before we read from it */
 957         if (e1000_validate_nvm_checksum(hw) < 0) {
 958                 /*
 959                 ** Some PCI-E parts fail the first check due to
 960                 ** the link being in sleep state, call it again,
 961                 ** if it fails a second time its a real issue.
 962                 */
 963                 if (e1000_validate_nvm_checksum(hw) < 0) {
 964                         device_printf(dev,
 965                             "The EEPROM Checksum Is Not Valid\n");
 966                         error = EIO;
 967                         goto err_late;
 968                 }
 969         }
 970
 971         /* Copy the permanent MAC address out of the EEPROM */
 972         if (e1000_read_mac_addr(hw) < 0) {
 973                 device_printf(dev, "EEPROM read error while reading MAC"
 974                     " address\n");
 975                 error = EIO;
 976                 goto err_late;
 977         }
 978
 979         if (!em_is_valid_ether_addr(hw->mac.addr)) {
 980                 device_printf(dev, "Invalid MAC address\n");
 981                 error = EIO;
 982                 goto err_late;
 983         }
 984
 985         /* Disable ULP support */
 986         e1000_disable_ulp_lpt_lp(hw, TRUE);
 987
 988         /*
 989          * Get Wake-on-Lan and Management info for later use
 990          */
 991         em_get_wakeup(ctx);
 992
 993         iflib_set_mac(ctx, hw->mac.addr);
 994
 995         return (0);
 996
 997 err_late:
 998         em_release_hw_control(adapter);
 999 err_pci:
1000         em_free_pci_resources(ctx);
1001         free(adapter->mta, M_DEVBUF);
1002
1003         return (error);
1004 }
1005
1006 static int
1007 em_if_attach_post(if_ctx_t ctx)
1008 {
1009         struct adapter *adapter = iflib_get_softc(ctx);
1010         struct e1000_hw *hw = &adapter->hw;
1011         int error = 0;
1012
1013         /* Setup OS specific network interface */
1014         error = em_setup_interface(ctx);
1015         if (error != 0) {
1016                 goto err_late;
1017         }
1018
1019         em_reset(ctx);
1020
1021         /* Initialize statistics */
1022         em_update_stats_counters(adapter);
1023         hw->mac.get_link_status = 1;
1024         em_if_update_admin_status(ctx);
1025         em_add_hw_stats(adapter);
1026
1027         /* Non-AMT based hardware can now take control from firmware */
1028         if (adapter->has_manage && !adapter->has_amt)
1029                 em_get_hw_control(adapter);
1030
1031         INIT_DEBUGOUT("em_if_attach_post: end");
1032
1033         return (error);
1034
1035 err_late:
1036         em_release_hw_control(adapter);
1037         em_free_pci_resources(ctx);
1038         em_if_queues_free(ctx);
1039         free(adapter->mta, M_DEVBUF);
1040
1041         return (error);
1042 }
1043
1044 /*********************************************************************
1045  *  Device removal routine
1046  *
1047  *  The detach entry point is called when the driver is being removed.
1048  *  This routine stops the adapter and deallocates all the resources
1049  *  that were allocated for driver operation.
1050  *
1051  *  return 0 on success, positive on failure
1052  *********************************************************************/
1053
1054 static int
1055 em_if_detach(if_ctx_t ctx)
1056 {
1057         struct adapter  *adapter = iflib_get_softc(ctx);
1058
1059         INIT_DEBUGOUT("em_detach: begin");
1060
1061         e1000_phy_hw_reset(&adapter->hw);
1062
1063         em_release_manageability(adapter);
1064         em_release_hw_control(adapter);
1065         em_free_pci_resources(ctx);
1066
1067         return (0);
1068 }
1069
1070 /*********************************************************************
1071  *
1072  *  Shutdown entry point
1073  *
1074  **********************************************************************/
1075
1076 static int
1077 em_if_shutdown(if_ctx_t ctx)
1078 {
1079         return em_if_suspend(ctx);
1080 }
1081
1082 /*
1083  * Suspend/resume device methods.
1084  */
1085 static int
1086 em_if_suspend(if_ctx_t ctx)
1087 {
1088         struct adapter *adapter = iflib_get_softc(ctx);
1089
1090         em_release_manageability(adapter);
1091         em_release_hw_control(adapter);
1092         em_enable_wakeup(ctx);
1093         return (0);
1094 }
1095
1096 static int
1097 em_if_resume(if_ctx_t ctx)
1098 {
1099         struct adapter *adapter = iflib_get_softc(ctx);
1100
1101         if (adapter->hw.mac.type == e1000_pch2lan)
1102                 e1000_resume_workarounds_pchlan(&adapter->hw);
1103         em_if_init(ctx);
1104         em_init_manageability(adapter);
1105
1106         return(0);
1107 }
1108
1109 static int
1110 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1111 {
1112   int max_frame_size;
1113   struct adapter *adapter = iflib_get_softc(ctx);
1114   struct ifnet *ifp = iflib_get_ifp(ctx);
1115
1116   IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1117
1118   switch (adapter->hw.mac.type) {
1119   case e1000_82571:
1120   case e1000_82572:
1121   case e1000_ich9lan:
1122   case e1000_ich10lan:
1123   case e1000_pch2lan:
1124   case e1000_pch_lpt:
1125   case e1000_pch_spt:
1126   case e1000_82574:
1127   case e1000_82583:
1128   case e1000_80003es2lan:       /* 9K Jumbo Frame size */
1129           max_frame_size = 9234;
1130           break;
1131   case e1000_pchlan:
1132           max_frame_size = 4096;
1133           break;
1134           /* Adapters that do not support jumbo frames */
1135   case e1000_ich8lan:
1136           max_frame_size = ETHER_MAX_LEN;
1137           break;
1138   default:
1139           max_frame_size = MAX_JUMBO_FRAME_SIZE;
1140   }
1141   if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1142           return (EINVAL);
1143   }
1144
1145   adapter->hw.mac.max_frame_size = if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN;
1146   return (0);
1147 }
1148
1149 /*********************************************************************
1150  *  Init entry point
1151  *
1152  *  This routine is used in two ways. It is used by the stack as
1153  *  init entry point in network interface structure. It is also used
1154  *  by the driver as a hw/sw initialization routine to get to a
1155  *  consistent state.
1156  *
1157  *  return 0 on success, positive on failure
1158  **********************************************************************/
1159
1160 static void
1161 em_if_init(if_ctx_t ctx)
1162 {
1163         struct adapter *adapter = iflib_get_softc(ctx);
1164         struct ifnet *ifp = iflib_get_ifp(ctx);
1165
1166         INIT_DEBUGOUT("em_if_init: begin");
1167
1168         /* Get the latest mac address, User can use a LAA */
1169         bcopy(if_getlladdr(ifp), adapter->hw.mac.addr,
1170               ETHER_ADDR_LEN);
1171
1172         /* Put the address into the Receive Address Array */
1173         e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1174
1175         /*
1176          * With the 82571 adapter, RAR[0] may be overwritten
1177          * when the other port is reset, we make a duplicate
1178          * in RAR[14] for that eventuality, this assures
1179          * the interface continues to function.
1180          */
1181         if (adapter->hw.mac.type == e1000_82571) {
1182                 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1183                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1184                     E1000_RAR_ENTRIES - 1);
1185         }
1186
1187         /* Initialize the hardware */
1188         em_reset(ctx);
1189         em_if_update_admin_status(ctx);
1190
1191         /* Setup VLAN support, basic and offload if available */
1192         E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1193
1194         /* Clear bad data from Rx FIFOs */
1195         if (adapter->hw.mac.type >= igb_mac_min)
1196                 e1000_rx_fifo_flush_82575(&adapter->hw);
1197
1198         /* Configure for OS presence */
1199         em_init_manageability(adapter);
1200
1201         /* Prepare transmit descriptors and buffers */
1202         em_initialize_transmit_unit(ctx);
1203
1204         /* Setup Multicast table */
1205         em_if_multi_set(ctx);
1206
1207         /*
1208         ** Figure out the desired mbuf
1209         ** pool for doing jumbos
1210         */
1211         if (adapter->hw.mac.max_frame_size <= 2048)
1212                 adapter->rx_mbuf_sz = MCLBYTES;
1213         else if (adapter->hw.mac.max_frame_size <= 4096)
1214                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
1215         else
1216                 adapter->rx_mbuf_sz = MJUM9BYTES;
1217
1218         em_initialize_receive_unit(ctx);
1219
1220         /* Use real VLAN Filter support? */
1221         if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1222                 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
1223                         /* Use real VLAN Filter support */
1224                         em_setup_vlan_hw_support(adapter);
1225                 else {
1226                         u32 ctrl;
1227                         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1228                         ctrl |= E1000_CTRL_VME;
1229                         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1230                 }
1231         }
1232
1233         /* Don't lose promiscuous settings */
1234         em_if_set_promisc(ctx, IFF_PROMISC);
1235         e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1236
1237         /* MSI/X configuration for 82574 */
1238         if (adapter->hw.mac.type == e1000_82574) {
1239                 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1240
1241                 tmp |= E1000_CTRL_EXT_PBA_CLR;
1242                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1243                 /* Set the IVAR - interrupt vector routing. */
1244                 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars);
1245         } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1246                 igb_configure_queues(adapter);
1247
1248         /* this clears any pending interrupts */
1249         E1000_READ_REG(&adapter->hw, E1000_ICR);
1250         E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC);
1251
1252         /* AMT based hardware can now take control from firmware */
1253         if (adapter->has_manage && adapter->has_amt)
1254                 em_get_hw_control(adapter);
1255
1256         /* Set Energy Efficient Ethernet */
1257         if (adapter->hw.mac.type >= igb_mac_min &&
1258             adapter->hw.phy.media_type == e1000_media_type_copper) {
1259                 if (adapter->hw.mac.type == e1000_i354)
1260                         e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
1261                 else
1262                         e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
1263         }
1264 }
1265
1266 /*********************************************************************
1267  *
1268  *  Fast Legacy/MSI Combined Interrupt Service routine
1269  *
1270  *********************************************************************/
1271 int
1272 em_intr(void *arg)
1273 {
1274         struct adapter  *adapter = arg;
1275         if_ctx_t ctx = adapter->ctx;
1276         u32             reg_icr;
1277
1278         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1279
1280         if (adapter->intr_type != IFLIB_INTR_LEGACY)
1281                 goto skip_stray;
1282         /* Hot eject?  */
1283         if (reg_icr == 0xffffffff)
1284                 return FILTER_STRAY;
1285
1286         /* Definitely not our interrupt.  */
1287         if (reg_icr == 0x0)
1288                 return FILTER_STRAY;
1289
1290         /*
1291          * Starting with the 82571 chip, bit 31 should be used to
1292          * determine whether the interrupt belongs to us.
1293          */
1294         if (adapter->hw.mac.type >= e1000_82571 &&
1295             (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1296                 return FILTER_STRAY;
1297
1298 skip_stray:
1299         /* Link status change */
1300         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1301                 adapter->hw.mac.get_link_status = 1;
1302                 iflib_admin_intr_deferred(ctx);
1303         }
1304
1305         if (reg_icr & E1000_ICR_RXO)
1306                 adapter->rx_overruns++;
1307
1308         return (FILTER_SCHEDULE_THREAD);
1309 }
1310
1311 static void
1312 igb_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq)
1313 {
1314         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims);
1315 }
1316
1317 static void
1318 em_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq)
1319 {
1320         E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims);
1321 }
1322
1323 static int
1324 em_if_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1325 {
1326         struct adapter  *adapter = iflib_get_softc(ctx);
1327         struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1328
1329         if (adapter->hw.mac.type >= igb_mac_min)
1330                 igb_enable_queue(adapter, rxq);
1331         else
1332                 em_enable_queue(adapter, rxq);
1333         return (0);
1334 }
1335
1336 /*********************************************************************
1337  *
1338  *  MSIX RX Interrupt Service routine
1339  *
1340  **********************************************************************/
1341 static int
1342 em_msix_que(void *arg)
1343 {
1344         struct em_rx_queue *que = arg;
1345
1346         ++que->irqs;
1347
1348         return (FILTER_SCHEDULE_THREAD);
1349 }
1350
1351 /*********************************************************************
1352  *
1353  *  MSIX Link Fast Interrupt Service routine
1354  *
1355  **********************************************************************/
1356 static int
1357 em_msix_link(void *arg)
1358 {
1359         struct adapter  *adapter = arg;
1360         u32             reg_icr;
1361
1362         ++adapter->link_irq;
1363         MPASS(adapter->hw.back != NULL);
1364         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1365
1366         if (reg_icr & E1000_ICR_RXO)
1367                 adapter->rx_overruns++;
1368
1369         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1370                 em_handle_link(adapter->ctx);
1371         } else {
1372                 E1000_WRITE_REG(&adapter->hw, E1000_IMS,
1373                                 EM_MSIX_LINK | E1000_IMS_LSC);
1374                 if (adapter->hw.mac.type >= igb_mac_min)
1375                         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1376
1377         }
1378
1379         /*
1380         ** Because we must read the ICR for this interrupt
1381         ** it may clear other causes using autoclear, for
1382         ** this reason we simply create a soft interrupt
1383         ** for all these vectors.
1384         */
1385         if (reg_icr && adapter->hw.mac.type < igb_mac_min) {
1386                 E1000_WRITE_REG(&adapter->hw,
1387                         E1000_ICS, adapter->ims);
1388         }
1389
1390         return (FILTER_HANDLED);
1391 }
1392
1393 static void
1394 em_handle_link(void *context)
1395 {
1396         if_ctx_t ctx = context;
1397         struct adapter  *adapter = iflib_get_softc(ctx);
1398
1399         adapter->hw.mac.get_link_status = 1;
1400         iflib_admin_intr_deferred(ctx);
1401 }
1402
1403
1404 /*********************************************************************
1405  *
1406  *  Media Ioctl callback
1407  *
1408  *  This routine is called whenever the user queries the status of
1409  *  the interface using ifconfig.
1410  *
1411  **********************************************************************/
1412 static void
1413 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1414 {
1415   struct adapter *adapter = iflib_get_softc(ctx);
1416   u_char fiber_type = IFM_1000_SX;
1417
1418   INIT_DEBUGOUT("em_if_media_status: begin");
1419
1420         iflib_admin_intr_deferred(ctx);
1421
1422         ifmr->ifm_status = IFM_AVALID;
1423         ifmr->ifm_active = IFM_ETHER;
1424
1425         if (!adapter->link_active) {
1426                 return;
1427         }
1428
1429         ifmr->ifm_status |= IFM_ACTIVE;
1430
1431         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
1432             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1433                 if (adapter->hw.mac.type == e1000_82545)
1434                         fiber_type = IFM_1000_LX;
1435                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1436         } else {
1437                 switch (adapter->link_speed) {
1438                 case 10:
1439                         ifmr->ifm_active |= IFM_10_T;
1440                         break;
1441                 case 100:
1442                         ifmr->ifm_active |= IFM_100_TX;
1443                         break;
1444                 case 1000:
1445                         ifmr->ifm_active |= IFM_1000_T;
1446                         break;
1447                 }
1448                 if (adapter->link_duplex == FULL_DUPLEX)
1449                         ifmr->ifm_active |= IFM_FDX;
1450                 else
1451                         ifmr->ifm_active |= IFM_HDX;
1452         }
1453 }
1454
1455 /*********************************************************************
1456  *
1457  *  Media Ioctl callback
1458  *
1459  *  This routine is called when the user changes speed/duplex using
1460  *  media/mediopt option with ifconfig.
1461  *
1462  **********************************************************************/
1463 static int
1464 em_if_media_change(if_ctx_t ctx)
1465 {
1466         struct adapter *adapter = iflib_get_softc(ctx);
1467         struct ifmedia  *ifm = iflib_get_media(ctx);
1468
1469         INIT_DEBUGOUT("em_if_media_change: begin");
1470
1471         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1472                 return (EINVAL);
1473
1474         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1475         case IFM_AUTO:
1476                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1477                 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1478                 break;
1479         case IFM_1000_LX:
1480         case IFM_1000_SX:
1481         case IFM_1000_T:
1482                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1483                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1484                 break;
1485         case IFM_100_TX:
1486                 adapter->hw.mac.autoneg = FALSE;
1487                 adapter->hw.phy.autoneg_advertised = 0;
1488                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1489                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1490                 else
1491                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1492                 break;
1493         case IFM_10_T:
1494                 adapter->hw.mac.autoneg = FALSE;
1495                 adapter->hw.phy.autoneg_advertised = 0;
1496                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1497                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1498                 else
1499                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1500                 break;
1501         default:
1502                 device_printf(adapter->dev, "Unsupported media type\n");
1503         }
1504
1505         em_if_init(ctx);
1506
1507         return (0);
1508 }
1509
1510 static int
1511 em_if_set_promisc(if_ctx_t ctx, int flags)
1512 {
1513         struct adapter *adapter = iflib_get_softc(ctx);
1514         u32             reg_rctl;
1515
1516         em_disable_promisc(ctx);
1517
1518         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1519
1520         if (flags & IFF_PROMISC) {
1521                 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1522                 /* Turn this on if you want to see bad packets */
1523                 if (em_debug_sbp)
1524                         reg_rctl |= E1000_RCTL_SBP;
1525                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1526         } else if (flags & IFF_ALLMULTI) {
1527                 reg_rctl |= E1000_RCTL_MPE;
1528                 reg_rctl &= ~E1000_RCTL_UPE;
1529                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1530         }
1531         return (0);
1532 }
1533
1534 static void
1535 em_disable_promisc(if_ctx_t ctx)
1536 {
1537         struct adapter *adapter = iflib_get_softc(ctx);
1538         struct ifnet *ifp = iflib_get_ifp(ctx);
1539         u32             reg_rctl;
1540         int             mcnt = 0;
1541
1542         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1543         reg_rctl &=  (~E1000_RCTL_UPE);
1544         if (if_getflags(ifp) & IFF_ALLMULTI)
1545                 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1546         else
1547                 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES);
1548         /* Don't disable if in MAX groups */
1549         if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1550                 reg_rctl &=  (~E1000_RCTL_MPE);
1551         reg_rctl &=  (~E1000_RCTL_SBP);
1552         E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1553 }
1554
1555
1556 /*********************************************************************
1557  *  Multicast Update
1558  *
1559  *  This routine is called whenever multicast address list is updated.
1560  *
1561  **********************************************************************/
1562
1563 static void
1564 em_if_multi_set(if_ctx_t ctx)
1565 {
1566         struct adapter *adapter = iflib_get_softc(ctx);
1567         struct ifnet *ifp = iflib_get_ifp(ctx);
1568         u32 reg_rctl = 0;
1569         u8  *mta; /* Multicast array memory */
1570         int mcnt = 0;
1571
1572         IOCTL_DEBUGOUT("em_set_multi: begin");
1573
1574         mta = adapter->mta;
1575         bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1576
1577         if (adapter->hw.mac.type == e1000_82542 &&
1578             adapter->hw.revision_id == E1000_REVISION_2) {
1579                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1580                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1581                         e1000_pci_clear_mwi(&adapter->hw);
1582                 reg_rctl |= E1000_RCTL_RST;
1583                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1584                 msec_delay(5);
1585         }
1586
1587         if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES);
1588
1589         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1590                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1591                 reg_rctl |= E1000_RCTL_MPE;
1592                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1593         } else
1594                 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
1595
1596         if (adapter->hw.mac.type == e1000_82542 &&
1597             adapter->hw.revision_id == E1000_REVISION_2) {
1598                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1599                 reg_rctl &= ~E1000_RCTL_RST;
1600                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1601                 msec_delay(5);
1602                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1603                         e1000_pci_set_mwi(&adapter->hw);
1604         }
1605 }
1606
1607
1608 /*********************************************************************
1609  *  Timer routine
1610  *
1611  *  This routine checks for link status and updates statistics.
1612  *
1613  **********************************************************************/
1614
1615 static void
1616 em_if_timer(if_ctx_t ctx, uint16_t qid)
1617 {
1618         struct adapter  *adapter = iflib_get_softc(ctx);
1619         struct em_rx_queue *que;
1620         int i;
1621         int trigger = 0;
1622
1623         em_if_update_admin_status(ctx);
1624         em_update_stats_counters(adapter);
1625
1626         /* Reset LAA into RAR[0] on 82571 */
1627         if ((adapter->hw.mac.type == e1000_82571) &&
1628             e1000_get_laa_state_82571(&adapter->hw))
1629                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1630
1631         if (adapter->hw.mac.type < em_mac_min)
1632                 lem_smartspeed(adapter);
1633
1634         /* Mask to use in the irq trigger */
1635         if (adapter->intr_type == IFLIB_INTR_MSIX) {
1636                 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++)
1637                         trigger |= que->eims;
1638         } else {
1639                 trigger = E1000_ICS_RXDMT0;
1640         }
1641 }
1642
1643
1644 static void
1645 em_if_update_admin_status(if_ctx_t ctx)
1646 {
1647         struct adapter *adapter = iflib_get_softc(ctx);
1648         struct e1000_hw *hw = &adapter->hw;
1649         struct ifnet *ifp = iflib_get_ifp(ctx);
1650         device_t dev = iflib_get_dev(ctx);
1651         u32 link_check = 0;
1652
1653         /* Get the cached link value or read phy for real */
1654         switch (hw->phy.media_type) {
1655         case e1000_media_type_copper:
1656                 if (hw->mac.get_link_status) {
1657                         if (hw->mac.type == e1000_pch_spt)
1658                                 msec_delay(50);
1659                         /* Do the work to read phy */
1660                         e1000_check_for_link(hw);
1661                         link_check = !hw->mac.get_link_status;
1662                         if (link_check) /* ESB2 fix */
1663                                 e1000_cfg_on_link_up(hw);
1664                 } else {
1665                         link_check = TRUE;
1666                 }
1667                 break;
1668         case e1000_media_type_fiber:
1669                 e1000_check_for_link(hw);
1670                 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1671                                  E1000_STATUS_LU);
1672                 break;
1673         case e1000_media_type_internal_serdes:
1674                 e1000_check_for_link(hw);
1675                 link_check = adapter->hw.mac.serdes_has_link;
1676                 break;
1677         default:
1678         case e1000_media_type_unknown:
1679                 break;
1680         }
1681
1682         /* Now check for a transition */
1683         if (link_check && (adapter->link_active == 0)) {
1684                 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
1685                     &adapter->link_duplex);
1686                 /* Check if we must disable SPEED_MODE bit on PCI-E */
1687                 if ((adapter->link_speed != SPEED_1000) &&
1688                     ((hw->mac.type == e1000_82571) ||
1689                     (hw->mac.type == e1000_82572))) {
1690                         int tarc0;
1691                         tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1692                         tarc0 &= ~TARC_SPEED_MODE_BIT;
1693                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1694                 }
1695                 if (bootverbose)
1696                         device_printf(dev, "Link is up %d Mbps %s\n",
1697                             adapter->link_speed,
1698                             ((adapter->link_duplex == FULL_DUPLEX) ?
1699                             "Full Duplex" : "Half Duplex"));
1700                 adapter->link_active = 1;
1701                 adapter->smartspeed = 0;
1702                 if_setbaudrate(ifp, adapter->link_speed * 1000000);
1703                 iflib_link_state_change(ctx, LINK_STATE_UP, ifp->if_baudrate);
1704                 printf("Link state changed to up\n");
1705         } else if (!link_check && (adapter->link_active == 1)) {
1706                 if_setbaudrate(ifp, 0);
1707                 adapter->link_speed = 0;
1708                 adapter->link_duplex = 0;
1709                 if (bootverbose)
1710                         device_printf(dev, "Link is Down\n");
1711                 adapter->link_active = 0;
1712                 iflib_link_state_change(ctx, LINK_STATE_DOWN, ifp->if_baudrate);
1713                 printf("link state changed to down\n");
1714         }
1715
1716         E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC);
1717 }
1718
1719 /*********************************************************************
1720  *
1721  *  This routine disables all traffic on the adapter by issuing a
1722  *  global reset on the MAC and deallocates TX/RX buffers.
1723  *
1724  *  This routine should always be called with BOTH the CORE
1725  *  and TX locks.
1726  **********************************************************************/
1727
1728 static void
1729 em_if_stop(if_ctx_t ctx)
1730 {
1731         struct adapter *adapter = iflib_get_softc(ctx);
1732
1733         INIT_DEBUGOUT("em_stop: begin");
1734
1735         e1000_reset_hw(&adapter->hw);
1736         if (adapter->hw.mac.type >= e1000_82544)
1737                 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0);
1738
1739         e1000_led_off(&adapter->hw);
1740         e1000_cleanup_led(&adapter->hw);
1741 }
1742
1743
1744 /*********************************************************************
1745  *
1746  *  Determine hardware revision.
1747  *
1748  **********************************************************************/
1749 static void
1750 em_identify_hardware(if_ctx_t ctx)
1751 {
1752         device_t dev = iflib_get_dev(ctx);
1753         struct adapter *adapter = iflib_get_softc(ctx);
1754
1755         /* Make sure our PCI config space has the necessary stuff set */
1756         adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1757
1758         /* Save off the information about this board */
1759         adapter->hw.vendor_id = pci_get_vendor(dev);
1760         adapter->hw.device_id = pci_get_device(dev);
1761         adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1762         adapter->hw.subsystem_vendor_id =
1763             pci_read_config(dev, PCIR_SUBVEND_0, 2);
1764         adapter->hw.subsystem_device_id =
1765             pci_read_config(dev, PCIR_SUBDEV_0, 2);
1766
1767         /* Do Shared Code Init and Setup */
1768         if (e1000_set_mac_type(&adapter->hw)) {
1769                 device_printf(dev, "Setup init failure\n");
1770                 return;
1771         }
1772 }
1773
1774 static int
1775 em_allocate_pci_resources(if_ctx_t ctx)
1776 {
1777         struct adapter *adapter = iflib_get_softc(ctx);
1778         device_t        dev = iflib_get_dev(ctx);
1779         int             rid, val;
1780
1781         rid = PCIR_BAR(0);
1782         adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1783             &rid, RF_ACTIVE);
1784         if (adapter->memory == NULL) {
1785                 device_printf(dev, "Unable to allocate bus resource: memory\n");
1786                 return (ENXIO);
1787         }
1788         adapter->osdep.mem_bus_space_tag =
1789             rman_get_bustag(adapter->memory);
1790         adapter->osdep.mem_bus_space_handle =
1791             rman_get_bushandle(adapter->memory);
1792         adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle;
1793
1794         /* Only older adapters use IO mapping */
1795         if (adapter->hw.mac.type < em_mac_min &&
1796             adapter->hw.mac.type > e1000_82543) {
1797                 /* Figure our where our IO BAR is ? */
1798                 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1799                         val = pci_read_config(dev, rid, 4);
1800                         if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1801                                 adapter->io_rid = rid;
1802                                 break;
1803                         }
1804                         rid += 4;
1805                         /* check for 64bit BAR */
1806                         if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1807                                 rid += 4;
1808                 }
1809                 if (rid >= PCIR_CIS) {
1810                         device_printf(dev, "Unable to locate IO BAR\n");
1811                         return (ENXIO);
1812                 }
1813                 adapter->ioport = bus_alloc_resource_any(dev,
1814                     SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE);
1815                 if (adapter->ioport == NULL) {
1816                         device_printf(dev, "Unable to allocate bus resource: "
1817                             "ioport\n");
1818                         return (ENXIO);
1819                 }
1820                 adapter->hw.io_base = 0;
1821                 adapter->osdep.io_bus_space_tag =
1822                     rman_get_bustag(adapter->ioport);
1823                 adapter->osdep.io_bus_space_handle =
1824                     rman_get_bushandle(adapter->ioport);
1825         }
1826
1827         adapter->hw.back = &adapter->osdep;
1828
1829         return (0);
1830 }
1831
1832 /*********************************************************************
1833  *
1834  *  Setup the MSIX Interrupt handlers
1835  *
1836  **********************************************************************/
1837 static int
1838 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
1839 {
1840         struct adapter     *adapter = iflib_get_softc(ctx);
1841         struct em_rx_queue *rx_que = adapter->rx_queues;
1842         struct em_tx_queue *tx_que = adapter->tx_queues;
1843         int                error, rid, i, vector = 0;
1844         char buf[16];
1845
1846         /* First set up ring resources */
1847         for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) {
1848                 rid = vector +1;
1849                 snprintf(buf, sizeof(buf), "rxq%d", i);
1850                 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RX, em_msix_que, rx_que, rx_que->me, buf);
1851                 if (error) {
1852                         device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
1853                         adapter->rx_num_queues = i + 1;
1854                         goto fail;
1855                 }
1856
1857                 rx_que->msix =  vector;
1858
1859                 /*
1860                 ** Set the bit to enable interrupt
1861                 ** in E1000_IMS -- bits 20 and 21
1862                 ** are for RX0 and RX1, note this has
1863                 ** NOTHING to do with the MSIX vector
1864                 */
1865                 if (adapter->hw.mac.type == e1000_82574) {
1866                         rx_que->eims = 1 << (20 + i);
1867                         adapter->ims |= rx_que->eims;
1868                         adapter->ivars |= (8 | rx_que->msix) << (i * 4);
1869                 } else if (adapter->hw.mac.type == e1000_82575)
1870                         rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
1871                 else
1872                         rx_que->eims = 1 << vector;
1873         }
1874
1875         for (i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
1876                 rid = vector + 1;
1877                 snprintf(buf, sizeof(buf), "txq%d", i);
1878                 tx_que = &adapter->tx_queues[i];
1879                 iflib_softirq_alloc_generic(ctx, rid, IFLIB_INTR_TX, tx_que, tx_que->me, buf);
1880
1881                 tx_que->msix = vector;
1882
1883                   /*
1884                 ** Set the bit to enable interrupt
1885                 ** in E1000_IMS -- bits 22 and 23
1886                 ** are for TX0 and TX1, note this has
1887                 ** NOTHING to do with the MSIX vector
1888                 */
1889                 if (adapter->hw.mac.type < igb_mac_min) {
1890                         tx_que->eims = 1 << (22 + i);
1891                         adapter->ims |= tx_que->eims;
1892                         adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
1893                 } if (adapter->hw.mac.type == e1000_82575)
1894                         tx_que->eims = E1000_EICR_TX_QUEUE0 << (i %  adapter->tx_num_queues);
1895                 else
1896                         tx_que->eims = 1 << (i %  adapter->tx_num_queues);
1897         }
1898
1899         /* Link interrupt */
1900         rid = vector + 1;
1901         error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq");
1902
1903         if (error) {
1904                 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
1905                 goto fail;
1906         }
1907         adapter->linkvec = vector;
1908         if (adapter->hw.mac.type < igb_mac_min) {
1909                 adapter->ivars |=  (8 | vector) << 16;
1910                 adapter->ivars |= 0x80000000;
1911         }
1912         return (0);
1913  fail:
1914         iflib_irq_free(ctx, &adapter->irq);
1915         rx_que = adapter->rx_queues;
1916         for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++)
1917                 iflib_irq_free(ctx, &rx_que->que_irq);
1918         return (error);
1919 }
1920
1921 static void
1922 igb_configure_queues(struct adapter *adapter)
1923 {
1924         struct  e1000_hw        *hw = &adapter->hw;
1925         struct  em_rx_queue     *rx_que;
1926         struct  em_tx_queue    *tx_que;
1927         u32                     tmp, ivar = 0, newitr = 0;
1928
1929         /* First turn on RSS capability */
1930         if (adapter->hw.mac.type != e1000_82575)
1931                 E1000_WRITE_REG(hw, E1000_GPIE,
1932                     E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
1933                     E1000_GPIE_PBA | E1000_GPIE_NSICR);
1934
1935         /* Turn on MSIX */
1936         switch (adapter->hw.mac.type) {
1937         case e1000_82580:
1938         case e1000_i350:
1939         case e1000_i354:
1940         case e1000_i210:
1941         case e1000_i211:
1942         case e1000_vfadapt:
1943         case e1000_vfadapt_i350:
1944                 /* RX entries */
1945                 for (int i = 0; i < adapter->rx_num_queues; i++) {
1946                         u32 index = i >> 1;
1947                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
1948                         rx_que = &adapter->rx_queues[i];
1949                         if (i & 1) {
1950                                 ivar &= 0xFF00FFFF;
1951                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
1952                         } else {
1953                                 ivar &= 0xFFFFFF00;
1954                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
1955                         }
1956                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
1957                 }
1958                 /* TX entries */
1959                 for (int i = 0; i < adapter->tx_num_queues; i++) {
1960                         u32 index = i >> 1;
1961                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
1962                         tx_que = &adapter->tx_queues[i];
1963                         if (i & 1) {
1964                                 ivar &= 0x00FFFFFF;
1965                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
1966                         } else {
1967                                 ivar &= 0xFFFF00FF;
1968                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
1969                         }
1970                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
1971                         adapter->que_mask |= tx_que->eims;
1972                 }
1973
1974                 /* And for the link interrupt */
1975                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
1976                 adapter->link_mask = 1 << adapter->linkvec;
1977                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
1978                 break;
1979         case e1000_82576:
1980                 /* RX entries */
1981                 for (int i = 0; i < adapter->rx_num_queues; i++) {
1982                         u32 index = i & 0x7; /* Each IVAR has two entries */
1983                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
1984                         rx_que = &adapter->rx_queues[i];
1985                         if (i < 8) {
1986                                 ivar &= 0xFFFFFF00;
1987                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
1988                         } else {
1989                                 ivar &= 0xFF00FFFF;
1990                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
1991                         }
1992                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
1993                         adapter->que_mask |= rx_que->eims;
1994                 }
1995                 /* TX entries */
1996                 for (int i = 0; i < adapter->tx_num_queues; i++) {
1997                         u32 index = i & 0x7; /* Each IVAR has two entries */
1998                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
1999                         tx_que = &adapter->tx_queues[i];
2000                         if (i < 8) {
2001                                 ivar &= 0xFFFF00FF;
2002                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2003                         } else {
2004                                 ivar &= 0x00FFFFFF;
2005                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2006                         }
2007                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2008                         adapter->que_mask |= tx_que->eims;
2009                 }
2010
2011                 /* And for the link interrupt */
2012                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2013                 adapter->link_mask = 1 << adapter->linkvec;
2014                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2015                 break;
2016
2017         case e1000_82575:
2018                 /* enable MSI-X support*/
2019                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2020                 tmp |= E1000_CTRL_EXT_PBA_CLR;
2021                 /* Auto-Mask interrupts upon ICR read. */
2022                 tmp |= E1000_CTRL_EXT_EIAME;
2023                 tmp |= E1000_CTRL_EXT_IRCA;
2024                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2025
2026                 /* Queues */
2027                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2028                         rx_que = &adapter->rx_queues[i];
2029                         tmp = E1000_EICR_RX_QUEUE0 << i;
2030                         tmp |= E1000_EICR_TX_QUEUE0 << i;
2031                         rx_que->eims = tmp;
2032                         E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2033                             i, rx_que->eims);
2034                         adapter->que_mask |= rx_que->eims;
2035                 }
2036
2037                 /* Link */
2038                 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec),
2039                     E1000_EIMS_OTHER);
2040                 adapter->link_mask |= E1000_EIMS_OTHER;
2041         default:
2042                 break;
2043         }
2044
2045         /* Set the starting interrupt rate */
2046         if (em_max_interrupt_rate > 0)
2047                 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2048
2049         if (hw->mac.type == e1000_82575)
2050                 newitr |= newitr << 16;
2051         else
2052                 newitr |= E1000_EITR_CNT_IGNR;
2053
2054         for (int i = 0; i < adapter->rx_num_queues; i++) {
2055                 rx_que = &adapter->rx_queues[i];
2056                 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2057         }
2058
2059         return;
2060 }
2061
2062 static void
2063 em_free_pci_resources(if_ctx_t ctx)
2064 {
2065         struct adapter *adapter = iflib_get_softc(ctx);
2066         struct          em_rx_queue *que = adapter->rx_queues;
2067         device_t        dev = iflib_get_dev(ctx);
2068
2069         /* Release all msix queue resources */
2070         if (adapter->intr_type == IFLIB_INTR_MSIX)
2071                 iflib_irq_free(ctx, &adapter->irq);
2072
2073         for (int i = 0; i < adapter->rx_num_queues; i++, que++) {
2074                 iflib_irq_free(ctx, &que->que_irq);
2075         }
2076
2077
2078         /* First release all the interrupt resources */
2079         if (adapter->memory != NULL) {
2080                 bus_release_resource(dev, SYS_RES_MEMORY,
2081                                      PCIR_BAR(0), adapter->memory);
2082                 adapter->memory = NULL;
2083         }
2084
2085         if (adapter->flash != NULL) {
2086                 bus_release_resource(dev, SYS_RES_MEMORY,
2087                                      EM_FLASH, adapter->flash);
2088                 adapter->flash = NULL;
2089         }
2090         if (adapter->ioport != NULL)
2091                 bus_release_resource(dev, SYS_RES_IOPORT,
2092                     adapter->io_rid, adapter->ioport);
2093 }
2094
2095 /* Setup MSI or MSI/X */
2096 static int
2097 em_setup_msix(if_ctx_t ctx)
2098 {
2099         struct adapter *adapter = iflib_get_softc(ctx);
2100
2101         if (adapter->hw.mac.type == e1000_82574) {
2102                 em_enable_vectors_82574(ctx);
2103         }
2104         return (0);
2105 }
2106
2107 /*********************************************************************
2108  *
2109  *  Initialize the hardware to a configuration
2110  *  as specified by the adapter structure.
2111  *
2112  **********************************************************************/
2113
2114 static void
2115 lem_smartspeed(struct adapter *adapter)
2116 {
2117         u16 phy_tmp;
2118
2119         if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) ||
2120             adapter->hw.mac.autoneg == 0 ||
2121             (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2122                 return;
2123
2124         if (adapter->smartspeed == 0) {
2125                 /* If Master/Slave config fault is asserted twice,
2126                  * we assume back-to-back */
2127                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2128                 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2129                         return;
2130                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2131                 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2132                         e1000_read_phy_reg(&adapter->hw,
2133                             PHY_1000T_CTRL, &phy_tmp);
2134                         if(phy_tmp & CR_1000T_MS_ENABLE) {
2135                                 phy_tmp &= ~CR_1000T_MS_ENABLE;
2136                                 e1000_write_phy_reg(&adapter->hw,
2137                                     PHY_1000T_CTRL, phy_tmp);
2138                                 adapter->smartspeed++;
2139                                 if(adapter->hw.mac.autoneg &&
2140                                    !e1000_copper_link_autoneg(&adapter->hw) &&
2141                                    !e1000_read_phy_reg(&adapter->hw,
2142                                     PHY_CONTROL, &phy_tmp)) {
2143                                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2144                                                     MII_CR_RESTART_AUTO_NEG);
2145                                         e1000_write_phy_reg(&adapter->hw,
2146                                             PHY_CONTROL, phy_tmp);
2147                                 }
2148                         }
2149                 }
2150                 return;
2151         } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2152                 /* If still no link, perhaps using 2/3 pair cable */
2153                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2154                 phy_tmp |= CR_1000T_MS_ENABLE;
2155                 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2156                 if(adapter->hw.mac.autoneg &&
2157                    !e1000_copper_link_autoneg(&adapter->hw) &&
2158                    !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2159                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2160                                     MII_CR_RESTART_AUTO_NEG);
2161                         e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2162                 }
2163         }
2164         /* Restart process after EM_SMARTSPEED_MAX iterations */
2165         if(adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2166                 adapter->smartspeed = 0;
2167 }
2168
2169
2170 static void
2171 em_reset(if_ctx_t ctx)
2172 {
2173         device_t        dev = iflib_get_dev(ctx);
2174         struct adapter *adapter = iflib_get_softc(ctx);
2175         struct ifnet *ifp = iflib_get_ifp(ctx);
2176         struct e1000_hw *hw = &adapter->hw;
2177         u16             rx_buffer_size;
2178         u32             pba;
2179
2180         INIT_DEBUGOUT("em_reset: begin");
2181
2182         /* Set up smart power down as default off on newer adapters. */
2183         if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2184             hw->mac.type == e1000_82572)) {
2185                 u16 phy_tmp = 0;
2186
2187                 /* Speed up time to link by disabling smart power down. */
2188                 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2189                 phy_tmp &= ~IGP02E1000_PM_SPD;
2190                 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2191         }
2192
2193         /*
2194          * Packet Buffer Allocation (PBA)
2195          * Writing PBA sets the receive portion of the buffer
2196          * the remainder is used for the transmit buffer.
2197          */
2198         switch (hw->mac.type) {
2199         /* Total Packet Buffer on these is 48K */
2200         case e1000_82571:
2201         case e1000_82572:
2202         case e1000_80003es2lan:
2203                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2204                 break;
2205         case e1000_82573: /* 82573: Total Packet Buffer is 32K */
2206                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2207                 break;
2208         case e1000_82574:
2209         case e1000_82583:
2210                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2211                 break;
2212         case e1000_ich8lan:
2213                 pba = E1000_PBA_8K;
2214                 break;
2215         case e1000_ich9lan:
2216         case e1000_ich10lan:
2217                 /* Boost Receive side for jumbo frames */
2218                 if (adapter->hw.mac.max_frame_size > 4096)
2219                         pba = E1000_PBA_14K;
2220                 else
2221                         pba = E1000_PBA_10K;
2222                 break;
2223         case e1000_pchlan:
2224         case e1000_pch2lan:
2225         case e1000_pch_lpt:
2226         case e1000_pch_spt:
2227                 pba = E1000_PBA_26K;
2228                 break;
2229         default:
2230                 if (adapter->hw.mac.max_frame_size > 8192)
2231                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2232                 else
2233                         pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2234         }
2235         E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
2236
2237         /*
2238          * These parameters control the automatic generation (Tx) and
2239          * response (Rx) to Ethernet PAUSE frames.
2240          * - High water mark should allow for at least two frames to be
2241          *   received after sending an XOFF.
2242          * - Low water mark works best when it is very near the high water mark.
2243          *   This allows the receiver to restart by sending XON when it has
2244          *   drained a bit. Here we use an arbitrary value of 1500 which will
2245          *   restart after one full frame is pulled from the buffer. There
2246          *   could be several smaller frames in the buffer and if so they will
2247          *   not trigger the XON until their total number reduces the buffer
2248          *   by 1500.
2249          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2250          */
2251         rx_buffer_size = ((E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10 );
2252         hw->fc.high_water = rx_buffer_size -
2253             roundup2(adapter->hw.mac.max_frame_size, 1024);
2254         hw->fc.low_water = hw->fc.high_water - 1500;
2255
2256         if (adapter->fc) /* locally set flow control value? */
2257                 hw->fc.requested_mode = adapter->fc;
2258         else
2259                 hw->fc.requested_mode = e1000_fc_full;
2260
2261         if (hw->mac.type == e1000_80003es2lan)
2262                 hw->fc.pause_time = 0xFFFF;
2263         else
2264                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
2265
2266         hw->fc.send_xon = TRUE;
2267
2268         /* Device specific overrides/settings */
2269         switch (hw->mac.type) {
2270         case e1000_pchlan:
2271                 /* Workaround: no TX flow ctrl for PCH */
2272                 hw->fc.requested_mode = e1000_fc_rx_pause;
2273                 hw->fc.pause_time = 0xFFFF; /* override */
2274                 if (if_getmtu(ifp) > ETHERMTU) {
2275                         hw->fc.high_water = 0x3500;
2276                         hw->fc.low_water = 0x1500;
2277                 } else {
2278                         hw->fc.high_water = 0x5000;
2279                         hw->fc.low_water = 0x3000;
2280                 }
2281                 hw->fc.refresh_time = 0x1000;
2282                 break;
2283         case e1000_pch2lan:
2284         case e1000_pch_lpt:
2285         case e1000_pch_spt:
2286                 hw->fc.high_water = 0x5C20;
2287                 hw->fc.low_water = 0x5048;
2288                 hw->fc.pause_time = 0x0650;
2289                 hw->fc.refresh_time = 0x0400;
2290                 /* Jumbos need adjusted PBA */
2291                 if (if_getmtu(ifp) > ETHERMTU)
2292                         E1000_WRITE_REG(hw, E1000_PBA, 12);
2293                 else
2294                         E1000_WRITE_REG(hw, E1000_PBA, 26);
2295                 break;
2296         case e1000_ich9lan:
2297         case e1000_ich10lan:
2298                 if (if_getmtu(ifp) > ETHERMTU) {
2299                         hw->fc.high_water = 0x2800;
2300                         hw->fc.low_water = hw->fc.high_water - 8;
2301                         break;
2302                 }
2303                 /* else fall thru */
2304         default:
2305                 if (hw->mac.type == e1000_80003es2lan)
2306                         hw->fc.pause_time = 0xFFFF;
2307                 break;
2308         }
2309
2310         /* Issue a global reset */
2311         e1000_reset_hw(hw);
2312         E1000_WRITE_REG(hw, E1000_WUC, 0);
2313         em_disable_aspm(adapter);
2314         /* and a re-init */
2315         if (e1000_init_hw(hw) < 0) {
2316                 device_printf(dev, "Hardware Initialization Failed\n");
2317                 return;
2318         }
2319
2320         E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2321         e1000_get_phy_info(hw);
2322         e1000_check_for_link(hw);
2323 }
2324
2325 #define RSSKEYLEN 10
2326 static void
2327 em_initialize_rss_mapping(struct adapter *adapter)
2328 {
2329         uint8_t  rss_key[4 * RSSKEYLEN];
2330         uint32_t reta = 0;
2331         struct e1000_hw *hw = &adapter->hw;
2332         int i;
2333
2334         /*
2335          * Configure RSS key
2336          */
2337         arc4rand(rss_key, sizeof(rss_key), 0);
2338         for (i = 0; i < RSSKEYLEN; ++i) {
2339                 uint32_t rssrk = 0;
2340
2341                 rssrk = EM_RSSRK_VAL(rss_key, i);
2342                 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2343         }
2344
2345         /*
2346          * Configure RSS redirect table in following fashion:
2347          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2348          */
2349         for (i = 0; i < sizeof(reta); ++i) {
2350                 uint32_t q;
2351
2352                 q = (i % adapter->rx_num_queues) << 7;
2353                 reta |= q << (8 * i);
2354         }
2355
2356         for (i = 0; i < 32; ++i)
2357                 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2358
2359         E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2360                         E1000_MRQC_RSS_FIELD_IPV4_TCP |
2361                         E1000_MRQC_RSS_FIELD_IPV4 |
2362                         E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2363                         E1000_MRQC_RSS_FIELD_IPV6_EX |
2364                         E1000_MRQC_RSS_FIELD_IPV6);
2365
2366 }
2367
2368 static void
2369 igb_initialize_rss_mapping(struct adapter *adapter)
2370 {
2371         struct e1000_hw *hw = &adapter->hw;
2372         int i;
2373         int queue_id;
2374         u32 reta;
2375         u32 rss_key[10], mrqc, shift = 0;
2376
2377         /* XXX? */
2378         if (adapter->hw.mac.type == e1000_82575)
2379                 shift = 6;
2380
2381         /*
2382          * The redirection table controls which destination
2383          * queue each bucket redirects traffic to.
2384          * Each DWORD represents four queues, with the LSB
2385          * being the first queue in the DWORD.
2386          *
2387          * This just allocates buckets to queues using round-robin
2388          * allocation.
2389          *
2390          * NOTE: It Just Happens to line up with the default
2391          * RSS allocation method.
2392          */
2393
2394         /* Warning FM follows */
2395         reta = 0;
2396         for (i = 0; i < 128; i++) {
2397 #ifdef  RSS
2398                 queue_id = rss_get_indirection_to_bucket(i);
2399                 /*
2400                  * If we have more queues than buckets, we'll
2401                  * end up mapping buckets to a subset of the
2402                  * queues.
2403                  *
2404                  * If we have more buckets than queues, we'll
2405                  * end up instead assigning multiple buckets
2406                  * to queues.
2407                  *
2408                  * Both are suboptimal, but we need to handle
2409                  * the case so we don't go out of bounds
2410                  * indexing arrays and such.
2411                  */
2412                 queue_id = queue_id % adapter->rx_num_queues;
2413 #else
2414                 queue_id = (i % adapter->rx_num_queues);
2415 #endif
2416                 /* Adjust if required */
2417                 queue_id = queue_id << shift;
2418
2419                 /*
2420                  * The low 8 bits are for hash value (n+0);
2421                  * The next 8 bits are for hash value (n+1), etc.
2422                  */
2423                 reta = reta >> 8;
2424                 reta = reta | ( ((uint32_t) queue_id) << 24);
2425                 if ((i & 3) == 3) {
2426                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2427                         reta = 0;
2428                 }
2429         }
2430
2431         /* Now fill in hash table */
2432
2433         /*
2434          * MRQC: Multiple Receive Queues Command
2435          * Set queuing to RSS control, number depends on the device.
2436          */
2437         mrqc = E1000_MRQC_ENABLE_RSS_8Q;
2438
2439 #ifdef  RSS
2440         /* XXX ew typecasting */
2441         rss_getkey((uint8_t *) &rss_key);
2442 #else
2443         arc4rand(&rss_key, sizeof(rss_key), 0);
2444 #endif
2445         for (i = 0; i < 10; i++)
2446                 E1000_WRITE_REG_ARRAY(hw,
2447                     E1000_RSSRK(0), i, rss_key[i]);
2448
2449         /*
2450          * Configure the RSS fields to hash upon.
2451          */
2452         mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2453             E1000_MRQC_RSS_FIELD_IPV4_TCP);
2454         mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2455             E1000_MRQC_RSS_FIELD_IPV6_TCP);
2456         mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2457             E1000_MRQC_RSS_FIELD_IPV6_UDP);
2458         mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2459             E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2460
2461         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2462 }
2463
2464 /*********************************************************************
2465  *
2466  *  Setup networking device structure and register an interface.
2467  *
2468  **********************************************************************/
2469 static int
2470 em_setup_interface(if_ctx_t ctx)
2471 {
2472         struct ifnet *ifp = iflib_get_ifp(ctx);
2473         struct adapter *adapter = iflib_get_softc(ctx);
2474         if_softc_ctx_t scctx = adapter->shared;
2475         uint64_t cap = 0;
2476
2477         INIT_DEBUGOUT("em_setup_interface: begin");
2478
2479         /* TSO parameters */
2480         ifp->if_hw_tsomax = IP_MAXPACKET;
2481         /* Take m_pullup(9)'s in em_xmit() w/ TSO into acount. */
2482         ifp->if_hw_tsomaxsegcount = EM_MAX_SCATTER - 5;
2483         ifp->if_hw_tsomaxsegsize = EM_TSO_SEG_SIZE;
2484
2485         /* Single Queue */
2486         if (adapter->tx_num_queues == 1) {
2487           if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
2488           if_setsendqready(ifp);
2489         }
2490
2491         cap = IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4;
2492         cap |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU;
2493
2494         /*
2495          * Tell the upper layer(s) we
2496          * support full VLAN capability
2497          */
2498         if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
2499         if_setcapabilitiesbit(ifp, cap, 0);
2500
2501         /*
2502         ** Don't turn this on by default, if vlans are
2503         ** created on another pseudo device (eg. lagg)
2504         ** then vlan events are not passed thru, breaking
2505         ** operation, but with HW FILTER off it works. If
2506         ** using vlans directly on the em driver you can
2507         ** enable this and get full hardware tag filtering.
2508         */
2509         if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWFILTER,0);
2510
2511         /* Enable only WOL MAGIC by default */
2512         if (adapter->wol) {
2513                 if_setcapabilitiesbit(ifp, IFCAP_WOL, 0);
2514                 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC, 0);
2515         }
2516
2517         /*
2518          * Specify the media types supported by this adapter and register
2519          * callbacks to update media and link information
2520          */
2521         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
2522             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
2523                 u_char fiber_type = IFM_1000_SX;        /* default type */
2524
2525                 if (adapter->hw.mac.type == e1000_82545)
2526                         fiber_type = IFM_1000_LX;
2527                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
2528                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2529         } else {
2530                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2531                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2532                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2533                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2534                 if (adapter->hw.phy.type != e1000_phy_ife) {
2535                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2536                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2537                 }
2538         }
2539         ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2540         ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO);
2541         return (0);
2542 }
2543
2544 static int
2545 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
2546 {
2547         struct adapter *adapter = iflib_get_softc(ctx);
2548         if_softc_ctx_t scctx = adapter->shared;
2549         int error = E1000_SUCCESS;
2550         struct em_tx_queue *que;
2551         int i;
2552
2553         MPASS(adapter->tx_num_queues > 0);
2554         MPASS(adapter->tx_num_queues == ntxqsets);
2555
2556         /* First allocate the top level queue structs */
2557         if (!(adapter->tx_queues =
2558             (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
2559             adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2560                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2561                 return(ENOMEM);
2562         }
2563
2564         for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) {
2565              /* Set up some basics */
2566              struct tx_ring *txr = &que->txr;
2567              txr->adapter = que->adapter = adapter;
2568              txr->que = que;
2569              que->me = txr->me =  i;
2570
2571              /* Allocate transmit buffer memory */
2572           if (!(txr->tx_buffers = (struct em_txbuffer *) malloc(sizeof(struct em_txbuffer) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2573                device_printf(iflib_get_dev(ctx), "failed to allocate tx_buffer memory\n");
2574                error = ENOMEM;
2575                goto fail;
2576           }
2577
2578           /* get the virtual and physical address of the hardware queues */
2579           txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
2580           txr->tx_paddr = paddrs[i*ntxqs];
2581
2582         }
2583
2584         device_printf(iflib_get_dev(ctx), "allocated for %d tx_queues\n", adapter->tx_num_queues);
2585         return (0);
2586  fail:
2587         em_if_queues_free(ctx);
2588         return (error);
2589 }
2590
2591 static int
2592 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
2593 {
2594         struct adapter *adapter = iflib_get_softc(ctx);
2595         int error = E1000_SUCCESS;
2596         struct em_rx_queue *que;
2597         int i;
2598
2599         MPASS(adapter->rx_num_queues > 0);
2600         MPASS(adapter->rx_num_queues == nrxqsets);
2601
2602         /* First allocate the top level queue structs */
2603         if (!(adapter->rx_queues =
2604             (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
2605             adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2606                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2607                 error = ENOMEM;
2608                 goto fail;
2609         }
2610
2611         for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) {
2612                 /* Set up some basics */
2613                 struct rx_ring *rxr = &que->rxr;
2614                 rxr->adapter = que->adapter = adapter;
2615                 rxr->que = que;
2616                 que->me = rxr->me =  i;
2617
2618                 /* get the virtual and physical address of the hardware queues */
2619                 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
2620                 rxr->rx_paddr = paddrs[i*nrxqs];
2621         }
2622
2623         device_printf(iflib_get_dev(ctx), "allocated for %d rx_queues\n", adapter->rx_num_queues);
2624
2625         return (0);
2626 fail:
2627         em_if_queues_free(ctx);
2628         return (error);
2629 }
2630
2631 static void
2632 em_if_queues_free(if_ctx_t ctx)
2633 {
2634         struct adapter *adapter = iflib_get_softc(ctx);
2635         struct em_tx_queue *tx_que = adapter->tx_queues;
2636         struct em_rx_queue *rx_que = adapter->rx_queues;
2637
2638         if (tx_que != NULL) {
2639           for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
2640                 struct tx_ring *txr = &tx_que->txr;
2641                 if (txr->tx_buffers == NULL)
2642                         break;
2643
2644                 free(txr->tx_buffers, M_DEVBUF);
2645                 txr->tx_buffers = NULL;
2646           }
2647           free(adapter->tx_queues, M_DEVBUF);
2648           adapter->tx_queues = NULL;
2649         }
2650
2651         if (rx_que != NULL) {
2652           free(adapter->rx_queues, M_DEVBUF);
2653           adapter->rx_queues = NULL;
2654         }
2655
2656         em_release_hw_control(adapter);
2657
2658         if (adapter->mta != NULL) {
2659                 free(adapter->mta, M_DEVBUF);
2660         }
2661 }
2662
2663 /*********************************************************************
2664  *
2665  *  Enable transmit unit.
2666  *
2667  **********************************************************************/
2668 static void
2669 em_initialize_transmit_unit(if_ctx_t ctx)
2670 {
2671         struct adapter *adapter = iflib_get_softc(ctx);
2672         if_softc_ctx_t scctx = adapter->shared;
2673         struct em_tx_queue *que;
2674         struct tx_ring  *txr;
2675         struct e1000_hw *hw = &adapter->hw;
2676         u32 tctl, txdctl = 0, tarc, tipg = 0;
2677
2678          INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
2679
2680         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
2681                 u64 bus_addr;
2682                 caddr_t offp, endp;
2683
2684                 que = &adapter->tx_queues[i];
2685                 txr = &que->txr;
2686                 bus_addr = txr->tx_paddr;
2687
2688                 /*Enable all queues */
2689                 em_init_tx_ring(que);
2690
2691                 /* Clear checksum offload context. */
2692                 offp = (caddr_t)&txr->csum_flags;
2693                 endp = (caddr_t)(txr + 1);
2694                 bzero(offp, endp - offp);
2695
2696                 /* Base and Len of TX Ring */
2697                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
2698                     scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
2699                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
2700                     (u32)(bus_addr >> 32));
2701                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
2702                     (u32)bus_addr);
2703                 /* Init the HEAD/TAIL indices */
2704                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
2705                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
2706
2707                 HW_DEBUGOUT2("Base = %x, Length = %x\n",
2708                     E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)),
2709                     E1000_READ_REG(&adapter->hw, E1000_TDLEN(i)));
2710
2711                 txdctl = 0; /* clear txdctl */
2712                 txdctl |= 0x1f; /* PTHRESH */
2713                 txdctl |= 1 << 8; /* HTHRESH */
2714                 txdctl |= 1 << 16;/* WTHRESH */
2715                 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
2716                 txdctl |= E1000_TXDCTL_GRAN;
2717                 txdctl |= 1 << 25; /* LWTHRESH */
2718
2719                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
2720         }
2721
2722         /* Set the default values for the Tx Inter Packet Gap timer */
2723         switch (adapter->hw.mac.type) {
2724         case e1000_80003es2lan:
2725                 tipg = DEFAULT_82543_TIPG_IPGR1;
2726                 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2727                     E1000_TIPG_IPGR2_SHIFT;
2728                 break;
2729         case e1000_82542:
2730                 tipg = DEFAULT_82542_TIPG_IPGT;
2731                 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2732                 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2733                 break;
2734         default:
2735                 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
2736                     (adapter->hw.phy.media_type ==
2737                     e1000_media_type_internal_serdes))
2738                         tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2739                 else
2740                         tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2741                 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2742                 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2743         }
2744
2745         E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
2746         E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value);
2747
2748         if(adapter->hw.mac.type >= e1000_82540)
2749                 E1000_WRITE_REG(&adapter->hw, E1000_TADV,
2750                     adapter->tx_abs_int_delay.value);
2751
2752         if ((adapter->hw.mac.type == e1000_82571) ||
2753             (adapter->hw.mac.type == e1000_82572)) {
2754                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2755                 tarc |= TARC_SPEED_MODE_BIT;
2756                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2757         } else if (adapter->hw.mac.type == e1000_80003es2lan) {
2758                 /* errata: program both queues to unweighted RR */
2759                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2760                 tarc |= 1;
2761                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2762                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
2763                 tarc |= 1;
2764                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
2765         } else if (adapter->hw.mac.type == e1000_82574) {
2766                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2767                 tarc |= TARC_ERRATA_BIT;
2768                 if ( adapter->tx_num_queues > 1) {
2769                         tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
2770                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2771                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
2772                 } else
2773                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2774         }
2775
2776         if (adapter->tx_int_delay.value > 0)
2777                 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2778
2779         /* Program the Transmit Control Register */
2780         tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
2781         tctl &= ~E1000_TCTL_CT;
2782         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2783                    (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
2784
2785         if (adapter->hw.mac.type >= e1000_82571)
2786                 tctl |= E1000_TCTL_MULR;
2787
2788         /* This write will effectively turn on the transmit unit. */
2789         E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
2790
2791         if (hw->mac.type == e1000_pch_spt) {
2792                 u32 reg;
2793                 reg = E1000_READ_REG(hw, E1000_IOSFPC);
2794                 reg |= E1000_RCTL_RDMTS_HEX;
2795                 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
2796                 reg = E1000_READ_REG(hw, E1000_TARC(0));
2797                 reg |= E1000_TARC0_CB_MULTIQ_3_REQ;
2798                 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
2799         }
2800 }
2801
2802 /*********************************************************************
2803  *
2804  *  Enable receive unit.
2805  *
2806  **********************************************************************/
2807
2808 static void
2809 em_initialize_receive_unit(if_ctx_t ctx)
2810 {
2811         struct adapter *adapter = iflib_get_softc(ctx);
2812         if_softc_ctx_t scctx = adapter->shared;
2813         struct ifnet *ifp = iflib_get_ifp(ctx);
2814         struct e1000_hw *hw = &adapter->hw;
2815         struct em_rx_queue *que;
2816         int i;
2817         u32     rctl, rxcsum, rfctl;
2818
2819         INIT_DEBUGOUT("em_initialize_receive_units: begin");
2820
2821         /*
2822          * Make sure receives are disabled while setting
2823          * up the descriptor ring
2824          */
2825         rctl = E1000_READ_REG(hw, E1000_RCTL);
2826         /* Do not disable if ever enabled on this hardware */
2827         if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
2828                 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2829
2830         /* Setup the Receive Control Register */
2831         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2832         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
2833             E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
2834             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2835
2836         /* Do not store bad packets */
2837         rctl &= ~E1000_RCTL_SBP;
2838
2839         /* Enable Long Packet receive */
2840         if (if_getmtu(ifp) > ETHERMTU)
2841                 rctl |= E1000_RCTL_LPE;
2842         else
2843                 rctl &= ~E1000_RCTL_LPE;
2844
2845         /* Strip the CRC */
2846         if (!em_disable_crc_stripping)
2847                 rctl |= E1000_RCTL_SECRC;
2848
2849         if (adapter->hw.mac.type >= e1000_82540) {
2850                 E1000_WRITE_REG(&adapter->hw, E1000_RADV,
2851                                 adapter->rx_abs_int_delay.value);
2852
2853                 /*
2854                  * Set the interrupt throttling rate. Value is calculated
2855                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
2856                  */
2857                 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
2858         }
2859         E1000_WRITE_REG(&adapter->hw, E1000_RDTR,
2860             adapter->rx_int_delay.value);
2861
2862         /* Use extended rx descriptor formats */
2863         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2864         rfctl |= E1000_RFCTL_EXTEN;
2865         /*
2866         ** When using MSIX interrupts we need to throttle
2867         ** using the EITR register (82574 only)
2868         */
2869         if (hw->mac.type == e1000_82574) {
2870                 for (int i = 0; i < 4; i++)
2871                         E1000_WRITE_REG(hw, E1000_EITR_82574(i),
2872                             DEFAULT_ITR);
2873                 /* Disable accelerated acknowledge */
2874                 rfctl |= E1000_RFCTL_ACK_DIS;
2875         }
2876         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2877
2878         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2879         if (if_getcapenable(ifp) & IFCAP_RXCSUM &&
2880             adapter->hw.mac.type >= e1000_82543) {
2881                 if (adapter->tx_num_queues > 1) {
2882                         if (adapter->hw.mac.type >= igb_mac_min) {
2883                                 rxcsum |= E1000_RXCSUM_PCSD;
2884                                 if (hw->mac.type != e1000_82575)
2885                                         rxcsum |= E1000_RXCSUM_CRCOFL;
2886                         } else
2887                                 rxcsum |= E1000_RXCSUM_TUOFL |
2888                                         E1000_RXCSUM_IPOFL |
2889                                         E1000_RXCSUM_PCSD;
2890                 } else {
2891                         if (adapter->hw.mac.type >= igb_mac_min)
2892                                 rxcsum |= E1000_RXCSUM_IPPCSE;
2893                         else
2894                                 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
2895                         if (adapter->hw.mac.type > e1000_82575)
2896                                 rxcsum |= E1000_RXCSUM_CRCOFL;
2897                 }
2898         } else
2899                 rxcsum &= ~E1000_RXCSUM_TUOFL;
2900
2901         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2902
2903         if (adapter->rx_num_queues > 1) {
2904                 if (adapter->hw.mac.type >= igb_mac_min)
2905                         igb_initialize_rss_mapping(adapter);
2906                 else
2907                         em_initialize_rss_mapping(adapter);
2908         }
2909
2910         /*
2911         ** XXX TEMPORARY WORKAROUND: on some systems with 82573
2912         ** long latencies are observed, like Lenovo X60. This
2913         ** change eliminates the problem, but since having positive
2914         ** values in RDTR is a known source of problems on other
2915         ** platforms another solution is being sought.
2916         */
2917         if (hw->mac.type == e1000_82573)
2918                 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
2919
2920         for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
2921                 struct rx_ring *rxr = &que->rxr;
2922                 /* Setup the Base and Length of the Rx Descriptor Ring */
2923                 u64 bus_addr = rxr->rx_paddr;
2924 #if 0
2925                 u32 rdt = adapter->rx_num_queues -1;  /* default */
2926 #endif
2927
2928                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2929                     scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
2930                 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
2931                 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
2932                 /* Setup the Head and Tail Descriptor Pointers */
2933                 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
2934                 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
2935         }
2936
2937         /*
2938          * Set PTHRESH for improved jumbo performance
2939          * According to 10.2.5.11 of Intel 82574 Datasheet,
2940          * RXDCTL(1) is written whenever RXDCTL(0) is written.
2941          * Only write to RXDCTL(1) if there is a need for different
2942          * settings.
2943          */
2944
2945         if (((adapter->hw.mac.type == e1000_ich9lan) ||
2946             (adapter->hw.mac.type == e1000_pch2lan) ||
2947             (adapter->hw.mac.type == e1000_ich10lan)) &&
2948             (if_getmtu(ifp) > ETHERMTU)) {
2949                 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
2950                 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
2951         } else if (adapter->hw.mac.type == e1000_82574) {
2952                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2953                         u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2954                         rxdctl |= 0x20; /* PTHRESH */
2955                         rxdctl |= 4 << 8; /* HTHRESH */
2956                         rxdctl |= 4 << 16;/* WTHRESH */
2957                         rxdctl |= 1 << 24; /* Switch to granularity */
2958                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2959                 }
2960         } else if (adapter->hw.mac.type >= igb_mac_min) {
2961                 u32 psize, srrctl = 0;
2962
2963                 if (ifp->if_mtu > ETHERMTU) {
2964                         rctl |= E1000_RCTL_LPE;
2965
2966                         /* Set maximum packet len */
2967                         psize = scctx->isc_max_frame_size;
2968                         if (psize <= 4096) {
2969                                 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2970                                 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2971                         } else if (psize > 4096) {
2972                                 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2973                                 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2974                         }
2975
2976                         /* are we on a vlan? */
2977                         if (ifp->if_vlantrunk != NULL)
2978                                 psize += VLAN_TAG_SIZE;
2979                         E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2980                 } else {
2981                         rctl &= ~E1000_RCTL_LPE;
2982                         srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2983                         rctl |= E1000_RCTL_SZ_2048;
2984                 }
2985
2986                 /*
2987                  * If TX flow control is disabled and there's >1 queue defined,
2988                  * enable DROP.
2989                  *
2990                  * This drops frames rather than hanging the RX MAC for all queues.
2991                  */
2992                 if ((adapter->rx_num_queues > 1) &&
2993                     (adapter->fc == e1000_fc_none ||
2994                      adapter->fc == e1000_fc_rx_pause)) {
2995                         srrctl |= E1000_SRRCTL_DROP_EN;
2996                 }
2997                         /* Setup the Base and Length of the Rx Descriptor Rings */
2998                 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
2999                         struct rx_ring *rxr = &que->rxr;
3000                         u64 bus_addr = rxr->rx_paddr;
3001                         u32 rxdctl;
3002
3003 #ifdef notyet
3004                         /* Configure for header split? -- ignore for now */
3005                         rxr->hdr_split = igb_header_split;
3006 #else
3007                         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3008 #endif
3009
3010
3011                         E1000_WRITE_REG(hw, E1000_RDLEN(i),
3012                                         scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3013                         E1000_WRITE_REG(hw, E1000_RDBAH(i),
3014                                         (uint32_t)(bus_addr >> 32));
3015                         E1000_WRITE_REG(hw, E1000_RDBAL(i),
3016                                         (uint32_t)bus_addr);
3017                         E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3018                         /* Enable this Queue */
3019                         rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3020                         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3021                         rxdctl &= 0xFFF00000;
3022                         rxdctl |= IGB_RX_PTHRESH;
3023                         rxdctl |= IGB_RX_HTHRESH << 8;
3024                         rxdctl |= IGB_RX_WTHRESH << 16;
3025                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3026                 }
3027         }
3028         if (adapter->hw.mac.type >= e1000_pch2lan) {
3029                 if (if_getmtu(ifp) > ETHERMTU)
3030                         e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
3031                 else
3032                         e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
3033         }
3034
3035         /* Make sure VLAN Filters are off */
3036         rctl &= ~E1000_RCTL_VFE;
3037
3038         if (adapter->rx_mbuf_sz == MCLBYTES)
3039                 rctl |= E1000_RCTL_SZ_2048;
3040         else if (adapter->rx_mbuf_sz == MJUMPAGESIZE)
3041                 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3042         else if (adapter->rx_mbuf_sz > MJUMPAGESIZE)
3043                 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3044
3045         /* ensure we clear use DTYPE of 00 here */
3046         rctl &= ~0x00000C00;
3047         /* Write out the settings */
3048         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3049
3050         return;
3051 }
3052
3053 static void
3054 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3055 {
3056         struct adapter  *adapter = iflib_get_softc(ctx);
3057         u32             index, bit;
3058
3059         index = (vtag >> 5) & 0x7F;
3060         bit = vtag & 0x1F;
3061         adapter->shadow_vfta[index] |= (1 << bit);
3062         ++adapter->num_vlans;
3063 }
3064
3065 static void
3066 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3067 {
3068         struct adapter  *adapter = iflib_get_softc(ctx);
3069         u32             index, bit;
3070
3071         index = (vtag >> 5) & 0x7F;
3072         bit = vtag & 0x1F;
3073         adapter->shadow_vfta[index] &= ~(1 << bit);
3074         --adapter->num_vlans;
3075 }
3076
3077 static void
3078 em_setup_vlan_hw_support(struct adapter *adapter)
3079 {
3080         struct e1000_hw *hw = &adapter->hw;
3081         u32             reg;
3082
3083         /*
3084         ** We get here thru init_locked, meaning
3085         ** a soft reset, this has already cleared
3086         ** the VFTA and other state, so if there
3087         ** have been no vlan's registered do nothing.
3088         */
3089         if (adapter->num_vlans == 0)
3090                 return;
3091
3092         /*
3093         ** A soft reset zero's out the VFTA, so
3094         ** we need to repopulate it now.
3095         */
3096         for (int i = 0; i < EM_VFTA_SIZE; i++)
3097                 if (adapter->shadow_vfta[i] != 0)
3098                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
3099                             i, adapter->shadow_vfta[i]);
3100
3101         reg = E1000_READ_REG(hw, E1000_CTRL);
3102         reg |= E1000_CTRL_VME;
3103         E1000_WRITE_REG(hw, E1000_CTRL, reg);
3104
3105         /* Enable the Filter Table */
3106         reg = E1000_READ_REG(hw, E1000_RCTL);
3107         reg &= ~E1000_RCTL_CFIEN;
3108         reg |= E1000_RCTL_VFE;
3109         E1000_WRITE_REG(hw, E1000_RCTL, reg);
3110 }
3111
3112 static void
3113 em_if_enable_intr(if_ctx_t ctx)
3114 {
3115         struct adapter *adapter = iflib_get_softc(ctx);
3116         struct e1000_hw *hw = &adapter->hw;
3117         u32 ims_mask = IMS_ENABLE_MASK;
3118
3119         if (hw->mac.type == e1000_82574) {
3120                 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK);
3121                 ims_mask |= adapter->ims;
3122         } if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min)  {
3123                 u32 mask = (adapter->que_mask | adapter->link_mask);
3124
3125                 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask);
3126                 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask);
3127                 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask);
3128                 ims_mask = E1000_IMS_LSC;
3129         }
3130
3131         E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3132 }
3133
3134 static void
3135 em_if_disable_intr(if_ctx_t ctx)
3136 {
3137         struct adapter *adapter = iflib_get_softc(ctx);
3138         struct e1000_hw *hw = &adapter->hw;
3139
3140         if (adapter->intr_type == IFLIB_INTR_MSIX) {
3141                 if (hw->mac.type >= igb_mac_min)
3142                         E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0);
3143                 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0);
3144         }
3145         E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
3146 }
3147
3148 /*
3149  * Bit of a misnomer, what this really means is
3150  * to enable OS management of the system... aka
3151  * to disable special hardware management features
3152  */
3153 static void
3154 em_init_manageability(struct adapter *adapter)
3155 {
3156         /* A shared code workaround */
3157 #define E1000_82542_MANC2H E1000_MANC2H
3158         if (adapter->has_manage) {
3159                 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3160                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3161
3162                 /* disable hardware interception of ARP */
3163                 manc &= ~(E1000_MANC_ARP_EN);
3164
3165                 /* enable receiving management packets to the host */
3166                 manc |= E1000_MANC_EN_MNG2HOST;
3167 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3168 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3169                 manc2h |= E1000_MNG2HOST_PORT_623;
3170                 manc2h |= E1000_MNG2HOST_PORT_664;
3171                 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3172                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3173         }
3174 }
3175
3176 /*
3177  * Give control back to hardware management
3178  * controller if there is one.
3179  */
3180 static void
3181 em_release_manageability(struct adapter *adapter)
3182 {
3183         if (adapter->has_manage) {
3184                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3185
3186                 /* re-enable hardware interception of ARP */
3187                 manc |= E1000_MANC_ARP_EN;
3188                 manc &= ~E1000_MANC_EN_MNG2HOST;
3189
3190                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3191         }
3192 }
3193
3194 /*
3195  * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3196  * For ASF and Pass Through versions of f/w this means
3197  * that the driver is loaded. For AMT version type f/w
3198  * this means that the network i/f is open.
3199  */
3200 static void
3201 em_get_hw_control(struct adapter *adapter)
3202 {
3203         u32 ctrl_ext, swsm;
3204
3205         if (adapter->hw.mac.type == e1000_82573) {
3206                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3207                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3208                     swsm | E1000_SWSM_DRV_LOAD);
3209                 return;
3210         }
3211         /* else */
3212         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3213         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3214             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3215         return;
3216 }
3217
3218 /*
3219  * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3220  * For ASF and Pass Through versions of f/w this means that
3221  * the driver is no longer loaded. For AMT versions of the
3222  * f/w this means that the network i/f is closed.
3223  */
3224 static void
3225 em_release_hw_control(struct adapter *adapter)
3226 {
3227         u32 ctrl_ext, swsm;
3228
3229         if (!adapter->has_manage)
3230                 return;
3231
3232         if (adapter->hw.mac.type == e1000_82573) {
3233                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3234                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3235                     swsm & ~E1000_SWSM_DRV_LOAD);
3236                 return;
3237         }
3238         /* else */
3239         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3240         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3241             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3242         return;
3243 }
3244
3245 static int
3246 em_is_valid_ether_addr(u8 *addr)
3247 {
3248         char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3249
3250         if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3251                 return (FALSE);
3252         }
3253
3254         return (TRUE);
3255 }
3256
3257 /*
3258 ** Parse the interface capabilities with regard
3259 ** to both system management and wake-on-lan for
3260 ** later use.
3261 */
3262 static void
3263 em_get_wakeup(if_ctx_t ctx)
3264 {
3265         struct adapter  *adapter = iflib_get_softc(ctx);
3266         device_t dev = iflib_get_dev(ctx);
3267         u16             eeprom_data = 0, device_id, apme_mask;
3268
3269         adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
3270         apme_mask = EM_EEPROM_APME;
3271
3272         switch (adapter->hw.mac.type) {
3273         case e1000_82542:
3274         case e1000_82543:
3275                 break;
3276         case e1000_82544:
3277                 e1000_read_nvm(&adapter->hw,
3278                     NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3279                 apme_mask = EM_82544_APME;
3280                 break;
3281         case e1000_82546:
3282         case e1000_82546_rev_3:
3283                 if (adapter->hw.bus.func == 1) {
3284                         e1000_read_nvm(&adapter->hw,
3285                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3286                         break;
3287                 } else
3288                         e1000_read_nvm(&adapter->hw,
3289                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3290                 break;
3291         case e1000_82573:
3292         case e1000_82583:
3293                 adapter->has_amt = TRUE;
3294                 /* Falls thru */
3295         case e1000_82571:
3296         case e1000_82572:
3297         case e1000_80003es2lan:
3298                 if (adapter->hw.bus.func == 1) {
3299                         e1000_read_nvm(&adapter->hw,
3300                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3301                         break;
3302                 } else
3303                         e1000_read_nvm(&adapter->hw,
3304                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3305                 break;
3306         case e1000_ich8lan:
3307         case e1000_ich9lan:
3308         case e1000_ich10lan:
3309         case e1000_pchlan:
3310         case e1000_pch2lan:
3311         case e1000_pch_lpt:
3312         case e1000_pch_spt:
3313                 apme_mask = E1000_WUC_APME;
3314                 adapter->has_amt = TRUE;
3315                 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
3316                 break;
3317         default:
3318                 e1000_read_nvm(&adapter->hw,
3319                     NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3320                 break;
3321         }
3322         if (eeprom_data & apme_mask)
3323                 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
3324         /*
3325          * We have the eeprom settings, now apply the special cases
3326          * where the eeprom may be wrong or the board won't support
3327          * wake on lan on a particular port
3328          */
3329         device_id = pci_get_device(dev);
3330         switch (device_id) {
3331         case E1000_DEV_ID_82546GB_PCIE:
3332                 adapter->wol = 0;
3333                 break;
3334         case E1000_DEV_ID_82546EB_FIBER:
3335         case E1000_DEV_ID_82546GB_FIBER:
3336                 /* Wake events only supported on port A for dual fiber
3337                  * regardless of eeprom setting */
3338                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3339                     E1000_STATUS_FUNC_1)
3340                         adapter->wol = 0;
3341                 break;
3342         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
3343                 /* if quad port adapter, disable WoL on all but port A */
3344                 if (global_quad_port_a != 0)
3345                         adapter->wol = 0;
3346                 /* Reset for multiple quad port adapters */
3347                 if (++global_quad_port_a == 4)
3348                         global_quad_port_a = 0;
3349                 break;
3350         case E1000_DEV_ID_82571EB_FIBER:
3351                 /* Wake events only supported on port A for dual fiber
3352                  * regardless of eeprom setting */
3353                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3354                     E1000_STATUS_FUNC_1)
3355                         adapter->wol = 0;
3356                 break;
3357         case E1000_DEV_ID_82571EB_QUAD_COPPER:
3358         case E1000_DEV_ID_82571EB_QUAD_FIBER:
3359         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
3360                 /* if quad port adapter, disable WoL on all but port A */
3361                 if (global_quad_port_a != 0)
3362                         adapter->wol = 0;
3363                 /* Reset for multiple quad port adapters */
3364                 if (++global_quad_port_a == 4)
3365                         global_quad_port_a = 0;
3366                 break;
3367         }
3368         return;
3369 }
3370
3371
3372 /*
3373  * Enable PCI Wake On Lan capability
3374  */
3375 static void
3376 em_enable_wakeup(if_ctx_t ctx)
3377 {
3378         struct adapter  *adapter = iflib_get_softc(ctx);
3379         device_t dev = iflib_get_dev(ctx);
3380         if_t ifp = iflib_get_ifp(ctx);
3381         u32             pmc, ctrl, ctrl_ext, rctl, wuc;
3382         u16             status;
3383
3384         if ((pci_find_cap(dev, PCIY_PMG, &pmc) != 0))
3385                 return;
3386
3387         /* Advertise the wakeup capability */
3388         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
3389         ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
3390         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
3391         wuc = E1000_READ_REG(&adapter->hw, E1000_WUC);
3392         wuc |= E1000_WUC_PME_EN ;
3393         E1000_WRITE_REG(&adapter->hw, E1000_WUC, wuc);
3394
3395         if ((adapter->hw.mac.type == e1000_ich8lan) ||
3396             (adapter->hw.mac.type == e1000_pchlan) ||
3397             (adapter->hw.mac.type == e1000_ich9lan) ||
3398             (adapter->hw.mac.type == e1000_ich10lan))
3399                 e1000_suspend_workarounds_ich8lan(&adapter->hw);
3400
3401         /* Keep the laser running on Fiber adapters */
3402         if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3403             adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
3404                 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3405                 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
3406                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext);
3407         }
3408
3409         /*
3410         ** Determine type of Wakeup: note that wol
3411         ** is set with all bits on by default.
3412         */
3413         if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
3414                 adapter->wol &= ~E1000_WUFC_MAG;
3415
3416         if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
3417                 adapter->wol &= ~E1000_WUFC_MC;
3418         else {
3419                 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3420                 rctl |= E1000_RCTL_MPE;
3421                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3422         }
3423
3424         if ((adapter->hw.mac.type == e1000_pchlan) ||
3425             (adapter->hw.mac.type == e1000_pch2lan) ||
3426             (adapter->hw.mac.type == e1000_pch_lpt) ||
3427             (adapter->hw.mac.type == e1000_pch_spt)) {
3428                 if (em_enable_phy_wakeup(adapter))
3429                         return;
3430         } else {
3431                 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
3432                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
3433         }
3434
3435         if (adapter->hw.phy.type == e1000_phy_igp_3)
3436                 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
3437
3438         /* Request PME */
3439         status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
3440         status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3441         if (if_getcapenable(ifp) & IFCAP_WOL)
3442                 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3443         pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
3444
3445         return;
3446 }
3447
3448 /*
3449 ** WOL in the newer chipset interfaces (pchlan)
3450 ** require thing to be copied into the phy
3451 */
3452 static int
3453 em_enable_phy_wakeup(struct adapter *adapter)
3454 {
3455         struct e1000_hw *hw = &adapter->hw;
3456         u32 mreg, ret = 0;
3457         u16 preg;
3458
3459         /* copy MAC RARs to PHY RARs */
3460         e1000_copy_rx_addrs_to_phy_ich8lan(hw);
3461
3462         /* copy MAC MTA to PHY MTA */
3463         for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
3464                 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
3465                 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
3466                 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
3467                     (u16)((mreg >> 16) & 0xFFFF));
3468         }
3469
3470         /* configure PHY Rx Control register */
3471         e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg);
3472         mreg = E1000_READ_REG(hw, E1000_RCTL);
3473         if (mreg & E1000_RCTL_UPE)
3474                 preg |= BM_RCTL_UPE;
3475         if (mreg & E1000_RCTL_MPE)
3476                 preg |= BM_RCTL_MPE;
3477         preg &= ~(BM_RCTL_MO_MASK);
3478         if (mreg & E1000_RCTL_MO_3)
3479                 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
3480                                 << BM_RCTL_MO_SHIFT);
3481         if (mreg & E1000_RCTL_BAM)
3482                 preg |= BM_RCTL_BAM;
3483         if (mreg & E1000_RCTL_PMCF)
3484                 preg |= BM_RCTL_PMCF;
3485         mreg = E1000_READ_REG(hw, E1000_CTRL);
3486         if (mreg & E1000_CTRL_RFCE)
3487                 preg |= BM_RCTL_RFCE;
3488         e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg);
3489
3490         /* enable PHY wakeup in MAC register */
3491         E1000_WRITE_REG(hw, E1000_WUC,
3492             E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
3493         E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol);
3494
3495         /* configure and enable PHY wakeup in PHY registers */
3496         e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol);
3497         e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
3498
3499         /* activate PHY wakeup */
3500         ret = hw->phy.ops.acquire(hw);
3501         if (ret) {
3502                 printf("Could not acquire PHY\n");
3503                 return ret;
3504         }
3505         e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3506                                  (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3507         ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
3508         if (ret) {
3509                 printf("Could not read PHY page 769\n");
3510                 goto out;
3511         }
3512         preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
3513         ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
3514         if (ret)
3515                 printf("Could not set PHY Host Wakeup bit\n");
3516 out:
3517         hw->phy.ops.release(hw);
3518
3519         return ret;
3520 }
3521
3522 static void
3523 em_if_led_func(if_ctx_t ctx, int onoff)
3524 {
3525         struct adapter  *adapter = iflib_get_softc(ctx);
3526
3527         if (onoff) {
3528                 e1000_setup_led(&adapter->hw);
3529                 e1000_led_on(&adapter->hw);
3530         } else {
3531                 e1000_led_off(&adapter->hw);
3532                 e1000_cleanup_led(&adapter->hw);
3533         }
3534 }
3535
3536 /*
3537 ** Disable the L0S and L1 LINK states
3538 */
3539 static void
3540 em_disable_aspm(struct adapter *adapter)
3541 {
3542         int             base, reg;
3543         u16             link_cap,link_ctrl;
3544         device_t        dev = adapter->dev;
3545
3546         switch (adapter->hw.mac.type) {
3547                 case e1000_82573:
3548                 case e1000_82574:
3549                 case e1000_82583:
3550                         break;
3551                 default:
3552                         return;
3553         }
3554         if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
3555                 return;
3556         reg = base + PCIER_LINK_CAP;
3557         link_cap = pci_read_config(dev, reg, 2);
3558         if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
3559                 return;
3560         reg = base + PCIER_LINK_CTL;
3561         link_ctrl = pci_read_config(dev, reg, 2);
3562         link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
3563         pci_write_config(dev, reg, link_ctrl, 2);
3564         return;
3565 }
3566
3567 /**********************************************************************
3568  *
3569  *  Update the board statistics counters.
3570  *
3571  **********************************************************************/
3572 static void
3573 em_update_stats_counters(struct adapter *adapter)
3574 {
3575
3576         if(adapter->hw.phy.media_type == e1000_media_type_copper ||
3577            (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3578                 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
3579                 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
3580         }
3581         adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
3582         adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
3583         adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
3584         adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
3585
3586         adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
3587         adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
3588         adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
3589         adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
3590         adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
3591         adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
3592         adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
3593         adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
3594         adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
3595         adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
3596         adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
3597         adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
3598         adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
3599         adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
3600         adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
3601         adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
3602         adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
3603         adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
3604         adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
3605         adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
3606
3607         /* For the 64-bit byte counters the low dword must be read first. */
3608         /* Both registers clear on the read of the high dword */
3609
3610         adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) +
3611             ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32);
3612         adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) +
3613             ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32);
3614
3615         adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
3616         adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
3617         adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
3618         adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
3619         adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
3620
3621         adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
3622         adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
3623
3624         adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
3625         adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
3626         adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
3627         adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
3628         adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
3629         adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
3630         adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
3631         adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
3632         adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
3633         adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
3634
3635         /* Interrupt Counts */
3636
3637         adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC);
3638         adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC);
3639         adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC);
3640         adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC);
3641         adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC);
3642         adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC);
3643         adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC);
3644         adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC);
3645         adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC);
3646
3647         if (adapter->hw.mac.type >= e1000_82543) {
3648                 adapter->stats.algnerrc +=
3649                 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
3650                 adapter->stats.rxerrc +=
3651                 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
3652                 adapter->stats.tncrs +=
3653                 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
3654                 adapter->stats.cexterr +=
3655                 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
3656                 adapter->stats.tsctc +=
3657                 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
3658                 adapter->stats.tsctfc +=
3659                 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
3660         }
3661 }
3662
3663 static uint64_t
3664 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
3665 {
3666         struct adapter *adapter = iflib_get_softc(ctx);
3667         struct ifnet *ifp = iflib_get_ifp(ctx);
3668
3669         switch (cnt) {
3670         case IFCOUNTER_COLLISIONS:
3671                 return (adapter->stats.colc);
3672         case IFCOUNTER_IERRORS:
3673                 return (adapter->dropped_pkts + adapter->stats.rxerrc +
3674                     adapter->stats.crcerrs + adapter->stats.algnerrc +
3675                     adapter->stats.ruc + adapter->stats.roc +
3676                     adapter->stats.mpc + adapter->stats.cexterr);
3677         case IFCOUNTER_OERRORS:
3678                 return (adapter->stats.ecol + adapter->stats.latecol +
3679                     adapter->watchdog_events);
3680         default:
3681                 return (if_get_counter_default(ifp, cnt));
3682         }
3683 }
3684
3685 /* Export a single 32-bit register via a read-only sysctl. */
3686 static int
3687 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
3688 {
3689         struct adapter *adapter;
3690         u_int val;
3691
3692         adapter = oidp->oid_arg1;
3693         val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2);
3694         return (sysctl_handle_int(oidp, &val, 0, req));
3695 }
3696
3697 /*
3698  * Add sysctl variables, one per statistic, to the system.
3699  */
3700 static void
3701 em_add_hw_stats(struct adapter *adapter)
3702 {
3703         device_t dev = iflib_get_dev(adapter->ctx);
3704         struct em_tx_queue *tx_que = adapter->tx_queues;
3705         struct em_rx_queue *rx_que = adapter->rx_queues;
3706
3707         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
3708         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
3709         struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
3710         struct e1000_hw_stats *stats = &adapter->stats;
3711
3712         struct sysctl_oid *stat_node, *queue_node, *int_node;
3713         struct sysctl_oid_list *stat_list, *queue_list, *int_list;
3714
3715 #define QUEUE_NAME_LEN 32
3716         char namebuf[QUEUE_NAME_LEN];
3717
3718         /* Driver Statistics */
3719         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
3720                         CTLFLAG_RD, &adapter->dropped_pkts,
3721                         "Driver dropped packets");
3722         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
3723                         CTLFLAG_RD, &adapter->link_irq,
3724                         "Link MSIX IRQ Handled");
3725         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "mbuf_defrag_fail",
3726                          CTLFLAG_RD, &adapter->mbuf_defrag_failed,
3727                          "Defragmenting mbuf chain failed");
3728         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "tx_dma_fail",
3729                         CTLFLAG_RD, &adapter->no_tx_dma_setup,
3730                         "Driver tx dma failure in xmit");
3731         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
3732                         CTLFLAG_RD, &adapter->rx_overruns,
3733                         "RX overruns");
3734         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
3735                         CTLFLAG_RD, &adapter->watchdog_events,
3736                         "Watchdog timeouts");
3737
3738         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
3739                         CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL,
3740                         em_sysctl_reg_handler, "IU",
3741                         "Device Control Register");
3742         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
3743                         CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL,
3744                         em_sysctl_reg_handler, "IU",
3745                         "Receiver Control Register");
3746         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
3747                         CTLFLAG_RD, &adapter->hw.fc.high_water, 0,
3748                         "Flow Control High Watermark");
3749         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
3750                         CTLFLAG_RD, &adapter->hw.fc.low_water, 0,
3751                         "Flow Control Low Watermark");
3752
3753         for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
3754                 struct tx_ring *txr = &tx_que->txr;
3755                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
3756                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
3757                                             CTLFLAG_RD, NULL, "TX Queue Name");
3758                 queue_list = SYSCTL_CHILDREN(queue_node);
3759
3760                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
3761                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
3762                                 E1000_TDH(txr->me),
3763                                 em_sysctl_reg_handler, "IU",
3764                                 "Transmit Descriptor Head");
3765                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
3766                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
3767                                 E1000_TDT(txr->me),
3768                                 em_sysctl_reg_handler, "IU",
3769                                 "Transmit Descriptor Tail");
3770                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
3771                                 CTLFLAG_RD, &txr->tx_irq,
3772                                 "Queue MSI-X Transmit Interrupts");
3773                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "no_desc_avail",
3774                                 CTLFLAG_RD, &txr->no_desc_avail,
3775                                 "Queue No Descriptor Available");
3776         }
3777
3778         for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) {
3779                 struct rx_ring *rxr = &rx_que->rxr;
3780                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
3781                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
3782                                             CTLFLAG_RD, NULL, "RX Queue Name");
3783                 queue_list = SYSCTL_CHILDREN(queue_node);
3784
3785                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
3786                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
3787                                 E1000_RDH(rxr->me),
3788                                 em_sysctl_reg_handler, "IU",
3789                                 "Receive Descriptor Head");
3790                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
3791                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
3792                                 E1000_RDT(rxr->me),
3793                                 em_sysctl_reg_handler, "IU",
3794                                 "Receive Descriptor Tail");
3795                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
3796                                 CTLFLAG_RD, &rxr->rx_irq,
3797                                 "Queue MSI-X Receive Interrupts");
3798         }
3799
3800         /* MAC stats get their own sub node */
3801
3802         stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
3803                                     CTLFLAG_RD, NULL, "Statistics");
3804         stat_list = SYSCTL_CHILDREN(stat_node);
3805
3806         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
3807                         CTLFLAG_RD, &stats->ecol,
3808                         "Excessive collisions");
3809         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
3810                         CTLFLAG_RD, &stats->scc,
3811                         "Single collisions");
3812         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
3813                         CTLFLAG_RD, &stats->mcc,
3814                         "Multiple collisions");
3815         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
3816                         CTLFLAG_RD, &stats->latecol,
3817                         "Late collisions");
3818         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
3819                         CTLFLAG_RD, &stats->colc,
3820                         "Collision Count");
3821         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
3822                         CTLFLAG_RD, &adapter->stats.symerrs,
3823                         "Symbol Errors");
3824         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
3825                         CTLFLAG_RD, &adapter->stats.sec,
3826                         "Sequence Errors");
3827         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
3828                         CTLFLAG_RD, &adapter->stats.dc,
3829                         "Defer Count");
3830         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
3831                         CTLFLAG_RD, &adapter->stats.mpc,
3832                         "Missed Packets");
3833         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
3834                         CTLFLAG_RD, &adapter->stats.rnbc,
3835                         "Receive No Buffers");
3836         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
3837                         CTLFLAG_RD, &adapter->stats.ruc,
3838                         "Receive Undersize");
3839         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
3840                         CTLFLAG_RD, &adapter->stats.rfc,
3841                         "Fragmented Packets Received ");
3842         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
3843                         CTLFLAG_RD, &adapter->stats.roc,
3844                         "Oversized Packets Received");
3845         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
3846                         CTLFLAG_RD, &adapter->stats.rjc,
3847                         "Recevied Jabber");
3848         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
3849                         CTLFLAG_RD, &adapter->stats.rxerrc,
3850                         "Receive Errors");
3851         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
3852                         CTLFLAG_RD, &adapter->stats.crcerrs,
3853                         "CRC errors");
3854         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
3855                         CTLFLAG_RD, &adapter->stats.algnerrc,
3856                         "Alignment Errors");
3857         /* On 82575 these are collision counts */
3858         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
3859                         CTLFLAG_RD, &adapter->stats.cexterr,
3860                         "Collision/Carrier extension errors");
3861         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
3862                         CTLFLAG_RD, &adapter->stats.xonrxc,
3863                         "XON Received");
3864         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
3865                         CTLFLAG_RD, &adapter->stats.xontxc,
3866                         "XON Transmitted");
3867         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
3868                         CTLFLAG_RD, &adapter->stats.xoffrxc,
3869                         "XOFF Received");
3870         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
3871                         CTLFLAG_RD, &adapter->stats.xofftxc,
3872                         "XOFF Transmitted");
3873
3874         /* Packet Reception Stats */
3875         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
3876                         CTLFLAG_RD, &adapter->stats.tpr,
3877                         "Total Packets Received ");
3878         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
3879                         CTLFLAG_RD, &adapter->stats.gprc,
3880                         "Good Packets Received");
3881         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
3882                         CTLFLAG_RD, &adapter->stats.bprc,
3883                         "Broadcast Packets Received");
3884         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
3885                         CTLFLAG_RD, &adapter->stats.mprc,
3886                         "Multicast Packets Received");
3887         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
3888                         CTLFLAG_RD, &adapter->stats.prc64,
3889                         "64 byte frames received ");
3890         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
3891                         CTLFLAG_RD, &adapter->stats.prc127,
3892                         "65-127 byte frames received");
3893         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
3894                         CTLFLAG_RD, &adapter->stats.prc255,
3895                         "128-255 byte frames received");
3896         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
3897                         CTLFLAG_RD, &adapter->stats.prc511,
3898                         "256-511 byte frames received");
3899         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
3900                         CTLFLAG_RD, &adapter->stats.prc1023,
3901                         "512-1023 byte frames received");
3902         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
3903                         CTLFLAG_RD, &adapter->stats.prc1522,
3904                         "1023-1522 byte frames received");
3905         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
3906                         CTLFLAG_RD, &adapter->stats.gorc,
3907                         "Good Octets Received");
3908
3909         /* Packet Transmission Stats */
3910         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
3911                         CTLFLAG_RD, &adapter->stats.gotc,
3912                         "Good Octets Transmitted");
3913         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
3914                         CTLFLAG_RD, &adapter->stats.tpt,
3915                         "Total Packets Transmitted");
3916         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
3917                         CTLFLAG_RD, &adapter->stats.gptc,
3918                         "Good Packets Transmitted");
3919         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
3920                         CTLFLAG_RD, &adapter->stats.bptc,
3921                         "Broadcast Packets Transmitted");
3922         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
3923                         CTLFLAG_RD, &adapter->stats.mptc,
3924                         "Multicast Packets Transmitted");
3925         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
3926                         CTLFLAG_RD, &adapter->stats.ptc64,
3927                         "64 byte frames transmitted ");
3928         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
3929                         CTLFLAG_RD, &adapter->stats.ptc127,
3930                         "65-127 byte frames transmitted");
3931         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
3932                         CTLFLAG_RD, &adapter->stats.ptc255,
3933                         "128-255 byte frames transmitted");
3934         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
3935                         CTLFLAG_RD, &adapter->stats.ptc511,
3936                         "256-511 byte frames transmitted");
3937         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
3938                         CTLFLAG_RD, &adapter->stats.ptc1023,
3939                         "512-1023 byte frames transmitted");
3940         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
3941                         CTLFLAG_RD, &adapter->stats.ptc1522,
3942                         "1024-1522 byte frames transmitted");
3943         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
3944                         CTLFLAG_RD, &adapter->stats.tsctc,
3945                         "TSO Contexts Transmitted");
3946         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
3947                         CTLFLAG_RD, &adapter->stats.tsctfc,
3948                         "TSO Contexts Failed");
3949
3950
3951         /* Interrupt Stats */
3952
3953         int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
3954                                     CTLFLAG_RD, NULL, "Interrupt Statistics");
3955         int_list = SYSCTL_CHILDREN(int_node);
3956
3957         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
3958                         CTLFLAG_RD, &adapter->stats.iac,
3959                         "Interrupt Assertion Count");
3960
3961         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
3962                         CTLFLAG_RD, &adapter->stats.icrxptc,
3963                         "Interrupt Cause Rx Pkt Timer Expire Count");
3964
3965         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
3966                         CTLFLAG_RD, &adapter->stats.icrxatc,
3967                         "Interrupt Cause Rx Abs Timer Expire Count");
3968
3969         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
3970                         CTLFLAG_RD, &adapter->stats.ictxptc,
3971                         "Interrupt Cause Tx Pkt Timer Expire Count");
3972
3973         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
3974                         CTLFLAG_RD, &adapter->stats.ictxatc,
3975                         "Interrupt Cause Tx Abs Timer Expire Count");
3976
3977         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
3978                         CTLFLAG_RD, &adapter->stats.ictxqec,
3979                         "Interrupt Cause Tx Queue Empty Count");
3980
3981         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
3982                         CTLFLAG_RD, &adapter->stats.ictxqmtc,
3983                         "Interrupt Cause Tx Queue Min Thresh Count");
3984
3985         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
3986                         CTLFLAG_RD, &adapter->stats.icrxdmtc,
3987                         "Interrupt Cause Rx Desc Min Thresh Count");
3988
3989         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
3990                         CTLFLAG_RD, &adapter->stats.icrxoc,
3991                         "Interrupt Cause Receiver Overrun Count");
3992 }
3993
3994 /**********************************************************************
3995  *
3996  *  This routine provides a way to dump out the adapter eeprom,
3997  *  often a useful debug/service tool. This only dumps the first
3998  *  32 words, stuff that matters is in that extent.
3999  *
4000  **********************************************************************/
4001 static int
4002 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4003 {
4004         struct adapter *adapter = (struct adapter *)arg1;
4005         int error;
4006         int result;
4007
4008         result = -1;
4009         error = sysctl_handle_int(oidp, &result, 0, req);
4010
4011         if (error || !req->newptr)
4012                 return (error);
4013
4014         /*
4015          * This value will cause a hex dump of the
4016          * first 32 16-bit words of the EEPROM to
4017          * the screen.
4018          */
4019         if (result == 1)
4020                 em_print_nvm_info(adapter);
4021
4022         return (error);
4023 }
4024
4025 static void
4026 em_print_nvm_info(struct adapter *adapter)
4027 {
4028         u16     eeprom_data;
4029         int     i, j, row = 0;
4030
4031         /* Its a bit crude, but it gets the job done */
4032         printf("\nInterface EEPROM Dump:\n");
4033         printf("Offset\n0x0000  ");
4034         for (i = 0, j = 0; i < 32; i++, j++) {
4035                 if (j == 8) { /* Make the offset block */
4036                         j = 0; ++row;
4037                         printf("\n0x00%x0  ",row);
4038                 }
4039                 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
4040                 printf("%04x ", eeprom_data);
4041         }
4042         printf("\n");
4043 }
4044
4045 static int
4046 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4047 {
4048         struct em_int_delay_info *info;
4049         struct adapter *adapter;
4050         u32 regval;
4051         int error, usecs, ticks;
4052
4053         info = (struct em_int_delay_info *)arg1;
4054         usecs = info->value;
4055         error = sysctl_handle_int(oidp, &usecs, 0, req);
4056         if (error != 0 || req->newptr == NULL)
4057                 return (error);
4058         if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4059                 return (EINVAL);
4060         info->value = usecs;
4061         ticks = EM_USECS_TO_TICKS(usecs);
4062         if (info->offset == E1000_ITR)  /* units are 256ns here */
4063                 ticks *= 4;
4064
4065         adapter = info->adapter;
4066
4067         regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
4068         regval = (regval & ~0xffff) | (ticks & 0xffff);
4069         /* Handle a few special cases. */
4070         switch (info->offset) {
4071         case E1000_RDTR:
4072                 break;
4073         case E1000_TIDV:
4074                 if (ticks == 0) {
4075                         adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
4076                         /* Don't write 0 into the TIDV register. */
4077                         regval++;
4078                 } else
4079                         adapter->txd_cmd |= E1000_TXD_CMD_IDE;
4080                 break;
4081         }
4082         E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
4083         return (0);
4084 }
4085
4086 static void
4087 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
4088         const char *description, struct em_int_delay_info *info,
4089         int offset, int value)
4090 {
4091         info->adapter = adapter;
4092         info->offset = offset;
4093         info->value = value;
4094         SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev),
4095             SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4096             OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
4097             info, 0, em_sysctl_int_delay, "I", description);
4098 }
4099
4100 static void
4101 em_set_sysctl_value(struct adapter *adapter, const char *name,
4102         const char *description, int *limit, int value)
4103 {
4104         *limit = value;
4105         SYSCTL_ADD_INT(device_get_sysctl_ctx(adapter->dev),
4106             SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4107             OID_AUTO, name, CTLFLAG_RW, limit, value, description);
4108 }
4109
4110
4111 /*
4112 ** Set flow control using sysctl:
4113 ** Flow control values:
4114 **      0 - off
4115 **      1 - rx pause
4116 **      2 - tx pause
4117 **      3 - full
4118 */
4119 static int
4120 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4121 {
4122         int             error;
4123         static int      input = 3; /* default is full */
4124         struct adapter  *adapter = (struct adapter *) arg1;
4125
4126         error = sysctl_handle_int(oidp, &input, 0, req);
4127
4128         if ((error) || (req->newptr == NULL))
4129                 return (error);
4130
4131         if (input == adapter->fc) /* no change? */
4132                 return (error);
4133
4134         switch (input) {
4135                 case e1000_fc_rx_pause:
4136                 case e1000_fc_tx_pause:
4137                 case e1000_fc_full:
4138                 case e1000_fc_none:
4139                         adapter->hw.fc.requested_mode = input;
4140                         adapter->fc = input;
4141                         break;
4142                 default:
4143                         /* Do nothing */
4144                         return (error);
4145         }
4146
4147         adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
4148         e1000_force_mac_fc(&adapter->hw);
4149         return (error);
4150 }
4151
4152 /*
4153 ** Manage Energy Efficient Ethernet:
4154 ** Control values:
4155 **     0/1 - enabled/disabled
4156 */
4157 static int
4158 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4159 {
4160        struct adapter *adapter = (struct adapter *) arg1;
4161        int             error, value;
4162
4163        value = adapter->hw.dev_spec.ich8lan.eee_disable;
4164        error = sysctl_handle_int(oidp, &value, 0, req);
4165        if (error || req->newptr == NULL)
4166                return (error);
4167        adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4168        em_if_init(adapter->ctx);
4169
4170        return (0);
4171 }
4172
4173 static int
4174 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4175 {
4176         struct adapter *adapter;
4177         int error;
4178         int result;
4179
4180         result = -1;
4181         error = sysctl_handle_int(oidp, &result, 0, req);
4182
4183         if (error || !req->newptr)
4184                 return (error);
4185
4186         if (result == 1) {
4187                 adapter = (struct adapter *)arg1;
4188                 em_print_debug_info(adapter);
4189         }
4190
4191         return (error);
4192 }
4193
4194 /*
4195 ** This routine is meant to be fluid, add whatever is
4196 ** needed for debugging a problem.  -jfv
4197 */
4198 static void
4199 em_print_debug_info(struct adapter *adapter)
4200 {
4201         device_t dev = adapter->dev;
4202         struct tx_ring *txr = &adapter->tx_queues->txr;
4203         struct rx_ring *rxr = &adapter->rx_queues->rxr;
4204
4205         if (if_getdrvflags(adapter->ifp) & IFF_DRV_RUNNING)
4206                 printf("Interface is RUNNING ");
4207         else
4208                 printf("Interface is NOT RUNNING\n");
4209
4210         if (if_getdrvflags(adapter->ifp) & IFF_DRV_OACTIVE)
4211                 printf("and INACTIVE\n");
4212         else
4213                 printf("and ACTIVE\n");
4214
4215         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
4216                 device_printf(dev, "TX Queue %d ------\n", i);
4217                 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
4218                         E1000_READ_REG(&adapter->hw, E1000_TDH(i)),
4219                         E1000_READ_REG(&adapter->hw, E1000_TDT(i)));
4220
4221         }
4222         for (int j=0; j < adapter->rx_num_queues; j++, rxr++) {
4223                 device_printf(dev, "RX Queue %d ------\n", j);
4224                 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
4225                         E1000_READ_REG(&adapter->hw, E1000_RDH(j)),
4226                         E1000_READ_REG(&adapter->hw, E1000_RDT(j)));
4227         }
4228 }
4229
4230
4231 /*
4232  * 82574 only:
4233  * Write a new value to the EEPROM increasing the number of MSIX
4234  * vectors from 3 to 5, for proper multiqueue support.
4235  */
4236 static void
4237 em_enable_vectors_82574(if_ctx_t ctx)
4238 {
4239         struct adapter *adapter = iflib_get_softc(ctx);
4240         struct e1000_hw *hw = &adapter->hw;
4241         device_t dev = iflib_get_dev(ctx);
4242         u16 edata;
4243
4244         e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4245         printf("Current cap: %#06x\n", edata);
4246         if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
4247                 device_printf(dev, "Writing to eeprom: increasing "
4248                     "reported MSIX vectors from 3 to 5...\n");
4249                 edata &= ~(EM_NVM_MSIX_N_MASK);
4250                 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
4251                 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4252                 e1000_update_nvm_checksum(hw);
4253                 device_printf(dev, "Writing to eeprom: done\n");
4254         }
4255 }
4256
4257
4258 #ifdef DDB
4259 DB_COMMAND(em_reset_dev, em_ddb_reset_dev)
4260 {
4261         devclass_t      dc;
4262         int max_em;
4263
4264         dc = devclass_find("em");
4265         max_em = devclass_get_maxunit(dc);
4266
4267         for (int index = 0; index < (max_em - 1); index++) {
4268                 device_t dev;
4269                 dev = devclass_get_device(dc, index);
4270                 if (device_get_driver(dev) == &em_driver) {
4271                         struct adapter *adapter = device_get_softc(dev);
4272                         em_if_init(adapter->ctx);
4273                 }
4274         }
4275 }
4276 DB_COMMAND(em_dump_queue, em_ddb_dump_queue)
4277 {
4278         devclass_t      dc;
4279         int max_em;
4280
4281         dc = devclass_find("em");
4282         max_em = devclass_get_maxunit(dc);
4283
4284         for (int index = 0; index < (max_em - 1); index++) {
4285                 device_t dev;
4286                 dev = devclass_get_device(dc, index);
4287                 if (device_get_driver(dev) == &em_driver)
4288                         em_print_debug_info(device_get_softc(dev));
4289         }
4290
4291 }
4292 #endif