sys/dev/e1000/if_em.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /* $FreeBSD$ */
  30 #include "if_em.h"
  31 #include <sys/sbuf.h>
  32 #include <machine/_inttypes.h>
  33
  34 #define em_mac_min e1000_82571
  35 #define igb_mac_min e1000_82575
  36
  37 /*********************************************************************
  38  *  Driver version:
  39  *********************************************************************/
  40 char em_driver_version[] = "7.6.1-k";
  41
  42 /*********************************************************************
  43  *  PCI Device ID Table
  44  *
  45  *  Used by probe to select devices to load on
  46  *  Last field stores an index into e1000_strings
  47  *  Last entry must be all 0s
  48  *
  49  *  { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
  50  *********************************************************************/
  51
  52 static pci_vendor_info_t em_vendor_info_array[] =
  53 {
  54         /* Intel(R) - lem-class legacy devices */
  55         PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"),
  56         PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"),
  57         PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"),
  58         PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"),
  59         PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"),
  60
  61         PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"),
  62         PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"),
  63         PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"),
  64         PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"),
  65         PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"),
  66         PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"),
  67         PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"),
  68
  69         PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"),
  70
  71         PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"),
  72         PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"),
  73
  74         PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"),
  75         PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"),
  76         PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"),
  77         PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"),
  78
  79         PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"),
  80         PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"),
  81         PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"),
  82         PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"),
  83         PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"),
  84
  85         PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"),
  86         PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"),
  87         PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"),
  88         PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"),
  89         PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"),
  90         PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"),
  91         PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"),
  92         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
  93         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
  94
  95         PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"),
  96         PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"),
  97         PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"),
  98
  99         /* Intel(R) - em-class devices */
 100         PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"),
 101         PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"),
 102         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"),
 103         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"),
 104         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"),
 105         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
 106         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
 107         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"),
 108         PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"),
 109         PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"),
 110         PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"),
 111         PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"),
 112         PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"),
 113         PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"),
 114         PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"),
 115         PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"),
 116         PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"),
 117         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"),
 118         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"),
 119         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"),
 120         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"),
 121         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"),
 122         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"),
 123         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"),
 124         PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"),
 125         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"),
 126         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"),
 127         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"),
 128         PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"),
 129         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"),
 130         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"),
 131         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"),
 132         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"),
 133         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"),
 134         PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"),
 135         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"),
 136         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"),
 137         PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"),
 138         PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"),
 139         PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"),
 140         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"),
 141         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"),
 142         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"),
 143         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"),
 144         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"),
 145         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"),
 146         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"),
 147         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"),
 148         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"),
 149         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"),
 150         PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"),
 151         PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"),
 152         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"),
 153         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"),
 154         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"),
 155         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"),
 156         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"),
 157         PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"),
 158         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"),
 159         PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"),
 160         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"),
 161         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"),
 162         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"),
 163         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"),
 164         PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"),
 165         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"),
 166         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"),
 167         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"),
 168         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"),
 169         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"),
 170         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"),
 171         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"),
 172         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"),
 173         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"),
 174         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"),
 175         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"),
 176         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"),
 177         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"),
 178         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"),
 179         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"),
 180         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"),
 181         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"),
 182         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"),
 183         PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"),
 184         PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"),
 185         PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"),
 186         PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"),
 187         PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"),
 188         PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"),
 189         PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"),
 190         PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"),
 191         PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"),
 192         PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"),
 193         PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"),
 194         PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"),
 195         PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"),
 196         PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"),
 197         /* required last entry */
 198         PVID_END
 199 };
 200
 201 static pci_vendor_info_t igb_vendor_info_array[] =
 202 {
 203         /* Intel(R) - igb-class devices */
 204         PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"),
 205         PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"),
 206         PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"),
 207         PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"),
 208         PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"),
 209         PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"),
 210         PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"),
 211         PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"),
 212         PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"),
 213         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"),
 214         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"),
 215         PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"),
 216         PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"),
 217         PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"),
 218         PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"),
 219         PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"),
 220         PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"),
 221         PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"),
 222         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"),
 223         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"),
 224         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"),
 225         PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"),
 226         PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"),
 227         PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"),
 228         PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"),
 229         PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"),
 230         PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"),
 231         PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"),
 232         PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"),
 233         PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"),
 234         PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"),
 235         PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"),
 236         PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"),
 237         PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"),
 238         PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"),
 239         PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"),
 240         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"),
 241         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"),
 242         PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"),
 243         /* required last entry */
 244         PVID_END
 245 };
 246
 247 /*********************************************************************
 248  *  Function prototypes
 249  *********************************************************************/
 250 static void     *em_register(device_t dev);
 251 static void     *igb_register(device_t dev);
 252 static int      em_if_attach_pre(if_ctx_t ctx);
 253 static int      em_if_attach_post(if_ctx_t ctx);
 254 static int      em_if_detach(if_ctx_t ctx);
 255 static int      em_if_shutdown(if_ctx_t ctx);
 256 static int      em_if_suspend(if_ctx_t ctx);
 257 static int      em_if_resume(if_ctx_t ctx);
 258
 259 static int      em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets);
 260 static int      em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets);
 261 static void     em_if_queues_free(if_ctx_t ctx);
 262
 263 static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
 264 static void     em_if_init(if_ctx_t ctx);
 265 static void     em_if_stop(if_ctx_t ctx);
 266 static void     em_if_media_status(if_ctx_t, struct ifmediareq *);
 267 static int      em_if_media_change(if_ctx_t ctx);
 268 static int      em_if_mtu_set(if_ctx_t ctx, uint32_t mtu);
 269 static void     em_if_timer(if_ctx_t ctx, uint16_t qid);
 270 static void     em_if_vlan_register(if_ctx_t ctx, u16 vtag);
 271 static void     em_if_vlan_unregister(if_ctx_t ctx, u16 vtag);
 272 static void     em_if_watchdog_reset(if_ctx_t ctx);
 273 static bool     em_if_needs_restart(if_ctx_t ctx, enum iflib_restart_event event);
 274
 275 static void     em_identify_hardware(if_ctx_t ctx);
 276 static int      em_allocate_pci_resources(if_ctx_t ctx);
 277 static void     em_free_pci_resources(if_ctx_t ctx);
 278 static void     em_reset(if_ctx_t ctx);
 279 static int      em_setup_interface(if_ctx_t ctx);
 280 static int      em_setup_msix(if_ctx_t ctx);
 281
 282 static void     em_initialize_transmit_unit(if_ctx_t ctx);
 283 static void     em_initialize_receive_unit(if_ctx_t ctx);
 284
 285 static void     em_if_intr_enable(if_ctx_t ctx);
 286 static void     em_if_intr_disable(if_ctx_t ctx);
 287 static void     igb_if_intr_enable(if_ctx_t ctx);
 288 static void     igb_if_intr_disable(if_ctx_t ctx);
 289 static int      em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 290 static int      em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
 291 static int      igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 292 static int      igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
 293 static void     em_if_multi_set(if_ctx_t ctx);
 294 static void     em_if_update_admin_status(if_ctx_t ctx);
 295 static void     em_if_debug(if_ctx_t ctx);
 296 static void     em_update_stats_counters(struct adapter *);
 297 static void     em_add_hw_stats(struct adapter *adapter);
 298 static int      em_if_set_promisc(if_ctx_t ctx, int flags);
 299 static bool     em_if_vlan_filter_capable(struct adapter *);
 300 static bool     em_if_vlan_filter_used(struct adapter *);
 301 static void     em_if_vlan_filter_enable(struct adapter *);
 302 static void     em_if_vlan_filter_disable(struct adapter *);
 303 static void     em_if_vlan_filter_write(struct adapter *);
 304 static void     em_setup_vlan_hw_support(struct adapter *);
 305 static int      em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
 306 static void     em_print_nvm_info(struct adapter *);
 307 static int      em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 308 static int      em_get_rs(SYSCTL_HANDLER_ARGS);
 309 static void     em_print_debug_info(struct adapter *);
 310 static int      em_is_valid_ether_addr(u8 *);
 311 static int      em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
 312 static void     em_add_int_delay_sysctl(struct adapter *, const char *,
 313                     const char *, struct em_int_delay_info *, int, int);
 314 /* Management and WOL Support */
 315 static void     em_init_manageability(struct adapter *);
 316 static void     em_release_manageability(struct adapter *);
 317 static void     em_get_hw_control(struct adapter *);
 318 static void     em_release_hw_control(struct adapter *);
 319 static void     em_get_wakeup(if_ctx_t ctx);
 320 static void     em_enable_wakeup(if_ctx_t ctx);
 321 static int      em_enable_phy_wakeup(struct adapter *);
 322 static void     em_disable_aspm(struct adapter *);
 323
 324 int             em_intr(void *arg);
 325
 326 /* MSI-X handlers */
 327 static int      em_if_msix_intr_assign(if_ctx_t, int);
 328 static int      em_msix_link(void *);
 329 static void     em_handle_link(void *context);
 330
 331 static void     em_enable_vectors_82574(if_ctx_t);
 332
 333 static int      em_set_flowcntl(SYSCTL_HANDLER_ARGS);
 334 static int      em_sysctl_eee(SYSCTL_HANDLER_ARGS);
 335 static void     em_if_led_func(if_ctx_t ctx, int onoff);
 336
 337 static int      em_get_regs(SYSCTL_HANDLER_ARGS);
 338
 339 static void     lem_smartspeed(struct adapter *adapter);
 340 static void     igb_configure_queues(struct adapter *adapter);
 341
 342
 343 /*********************************************************************
 344  *  FreeBSD Device Interface Entry Points
 345  *********************************************************************/
 346 static device_method_t em_methods[] = {
 347         /* Device interface */
 348         DEVMETHOD(device_register, em_register),
 349         DEVMETHOD(device_probe, iflib_device_probe),
 350         DEVMETHOD(device_attach, iflib_device_attach),
 351         DEVMETHOD(device_detach, iflib_device_detach),
 352         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 353         DEVMETHOD(device_suspend, iflib_device_suspend),
 354         DEVMETHOD(device_resume, iflib_device_resume),
 355         DEVMETHOD_END
 356 };
 357
 358 static device_method_t igb_methods[] = {
 359         /* Device interface */
 360         DEVMETHOD(device_register, igb_register),
 361         DEVMETHOD(device_probe, iflib_device_probe),
 362         DEVMETHOD(device_attach, iflib_device_attach),
 363         DEVMETHOD(device_detach, iflib_device_detach),
 364         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 365         DEVMETHOD(device_suspend, iflib_device_suspend),
 366         DEVMETHOD(device_resume, iflib_device_resume),
 367         DEVMETHOD_END
 368 };
 369
 370
 371 static driver_t em_driver = {
 372         "em", em_methods, sizeof(struct adapter),
 373 };
 374
 375 static devclass_t em_devclass;
 376 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
 377
 378 MODULE_DEPEND(em, pci, 1, 1, 1);
 379 MODULE_DEPEND(em, ether, 1, 1, 1);
 380 MODULE_DEPEND(em, iflib, 1, 1, 1);
 381
 382 IFLIB_PNP_INFO(pci, em, em_vendor_info_array);
 383
 384 static driver_t igb_driver = {
 385         "igb", igb_methods, sizeof(struct adapter),
 386 };
 387
 388 static devclass_t igb_devclass;
 389 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
 390
 391 MODULE_DEPEND(igb, pci, 1, 1, 1);
 392 MODULE_DEPEND(igb, ether, 1, 1, 1);
 393 MODULE_DEPEND(igb, iflib, 1, 1, 1);
 394
 395 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array);
 396
 397 static device_method_t em_if_methods[] = {
 398         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 399         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 400         DEVMETHOD(ifdi_detach, em_if_detach),
 401         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 402         DEVMETHOD(ifdi_suspend, em_if_suspend),
 403         DEVMETHOD(ifdi_resume, em_if_resume),
 404         DEVMETHOD(ifdi_init, em_if_init),
 405         DEVMETHOD(ifdi_stop, em_if_stop),
 406         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 407         DEVMETHOD(ifdi_intr_enable, em_if_intr_enable),
 408         DEVMETHOD(ifdi_intr_disable, em_if_intr_disable),
 409         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 410         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 411         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 412         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 413         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 414         DEVMETHOD(ifdi_media_status, em_if_media_status),
 415         DEVMETHOD(ifdi_media_change, em_if_media_change),
 416         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 417         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 418         DEVMETHOD(ifdi_timer, em_if_timer),
 419         DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
 420         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 421         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 422         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 423         DEVMETHOD(ifdi_led_func, em_if_led_func),
 424         DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable),
 425         DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable),
 426         DEVMETHOD(ifdi_debug, em_if_debug),
 427         DEVMETHOD(ifdi_needs_restart, em_if_needs_restart),
 428         DEVMETHOD_END
 429 };
 430
 431 static driver_t em_if_driver = {
 432         "em_if", em_if_methods, sizeof(struct adapter)
 433 };
 434
 435 static device_method_t igb_if_methods[] = {
 436         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 437         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 438         DEVMETHOD(ifdi_detach, em_if_detach),
 439         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 440         DEVMETHOD(ifdi_suspend, em_if_suspend),
 441         DEVMETHOD(ifdi_resume, em_if_resume),
 442         DEVMETHOD(ifdi_init, em_if_init),
 443         DEVMETHOD(ifdi_stop, em_if_stop),
 444         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 445         DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable),
 446         DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable),
 447         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 448         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 449         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 450         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 451         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 452         DEVMETHOD(ifdi_media_status, em_if_media_status),
 453         DEVMETHOD(ifdi_media_change, em_if_media_change),
 454         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 455         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 456         DEVMETHOD(ifdi_timer, em_if_timer),
 457         DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
 458         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 459         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 460         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 461         DEVMETHOD(ifdi_led_func, em_if_led_func),
 462         DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable),
 463         DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable),
 464         DEVMETHOD(ifdi_debug, em_if_debug),
 465         DEVMETHOD(ifdi_needs_restart, em_if_needs_restart),
 466         DEVMETHOD_END
 467 };
 468
 469 static driver_t igb_if_driver = {
 470         "igb_if", igb_if_methods, sizeof(struct adapter)
 471 };
 472
 473 /*********************************************************************
 474  *  Tunable default values.
 475  *********************************************************************/
 476
 477 #define EM_TICKS_TO_USECS(ticks)        ((1024 * (ticks) + 500) / 1000)
 478 #define EM_USECS_TO_TICKS(usecs)        ((1000 * (usecs) + 512) / 1024)
 479
 480 #define MAX_INTS_PER_SEC        8000
 481 #define DEFAULT_ITR             (1000000000/(MAX_INTS_PER_SEC * 256))
 482
 483 /* Allow common code without TSO */
 484 #ifndef CSUM_TSO
 485 #define CSUM_TSO        0
 486 #endif
 487
 488 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
 489     "EM driver parameters");
 490
 491 static int em_disable_crc_stripping = 0;
 492 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
 493     &em_disable_crc_stripping, 0, "Disable CRC Stripping");
 494
 495 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
 496 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
 497 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
 498     0, "Default transmit interrupt delay in usecs");
 499 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
 500     0, "Default receive interrupt delay in usecs");
 501
 502 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
 503 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
 504 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
 505     &em_tx_abs_int_delay_dflt, 0,
 506     "Default transmit interrupt delay limit in usecs");
 507 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
 508     &em_rx_abs_int_delay_dflt, 0,
 509     "Default receive interrupt delay limit in usecs");
 510
 511 static int em_smart_pwr_down = FALSE;
 512 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
 513     0, "Set to true to leave smart power down enabled on newer adapters");
 514
 515 /* Controls whether promiscuous also shows bad packets */
 516 static int em_debug_sbp = FALSE;
 517 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
 518     "Show bad packets in promiscuous mode");
 519
 520 /* How many packets rxeof tries to clean at a time */
 521 static int em_rx_process_limit = 100;
 522 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
 523     &em_rx_process_limit, 0,
 524     "Maximum number of received packets to process "
 525     "at a time, -1 means unlimited");
 526
 527 /* Energy efficient ethernet - default to OFF */
 528 static int eee_setting = 1;
 529 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
 530     "Enable Energy Efficient Ethernet");
 531
 532 /*
 533 ** Tuneable Interrupt rate
 534 */
 535 static int em_max_interrupt_rate = 8000;
 536 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
 537     &em_max_interrupt_rate, 0, "Maximum interrupts per second");
 538
 539
 540
 541 /* Global used in WOL setup with multiport cards */
 542 static int global_quad_port_a = 0;
 543
 544 extern struct if_txrx igb_txrx;
 545 extern struct if_txrx em_txrx;
 546 extern struct if_txrx lem_txrx;
 547
 548 static struct if_shared_ctx em_sctx_init = {
 549         .isc_magic = IFLIB_MAGIC,
 550         .isc_q_align = PAGE_SIZE,
 551         .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 552         .isc_tx_maxsegsize = PAGE_SIZE,
 553         .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 554         .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
 555         .isc_rx_maxsize = MJUM9BYTES,
 556         .isc_rx_nsegments = 1,
 557         .isc_rx_maxsegsize = MJUM9BYTES,
 558         .isc_nfl = 1,
 559         .isc_nrxqs = 1,
 560         .isc_ntxqs = 1,
 561         .isc_admin_intrcnt = 1,
 562         .isc_vendor_info = em_vendor_info_array,
 563         .isc_driver_version = em_driver_version,
 564         .isc_driver = &em_if_driver,
 565         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 566
 567         .isc_nrxd_min = {EM_MIN_RXD},
 568         .isc_ntxd_min = {EM_MIN_TXD},
 569         .isc_nrxd_max = {EM_MAX_RXD},
 570         .isc_ntxd_max = {EM_MAX_TXD},
 571         .isc_nrxd_default = {EM_DEFAULT_RXD},
 572         .isc_ntxd_default = {EM_DEFAULT_TXD},
 573 };
 574
 575 static struct if_shared_ctx igb_sctx_init = {
 576         .isc_magic = IFLIB_MAGIC,
 577         .isc_q_align = PAGE_SIZE,
 578         .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 579         .isc_tx_maxsegsize = PAGE_SIZE,
 580         .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 581         .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
 582         .isc_rx_maxsize = MJUM9BYTES,
 583         .isc_rx_nsegments = 1,
 584         .isc_rx_maxsegsize = MJUM9BYTES,
 585         .isc_nfl = 1,
 586         .isc_nrxqs = 1,
 587         .isc_ntxqs = 1,
 588         .isc_admin_intrcnt = 1,
 589         .isc_vendor_info = igb_vendor_info_array,
 590         .isc_driver_version = em_driver_version,
 591         .isc_driver = &igb_if_driver,
 592         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 593
 594         .isc_nrxd_min = {EM_MIN_RXD},
 595         .isc_ntxd_min = {EM_MIN_TXD},
 596         .isc_nrxd_max = {IGB_MAX_RXD},
 597         .isc_ntxd_max = {IGB_MAX_TXD},
 598         .isc_nrxd_default = {EM_DEFAULT_RXD},
 599         .isc_ntxd_default = {EM_DEFAULT_TXD},
 600 };
 601
 602 /*****************************************************************
 603  *
 604  * Dump Registers
 605  *
 606  ****************************************************************/
 607 #define IGB_REGS_LEN 739
 608
 609 static int em_get_regs(SYSCTL_HANDLER_ARGS)
 610 {
 611         struct adapter *adapter = (struct adapter *)arg1;
 612         struct e1000_hw *hw = &adapter->hw;
 613         struct sbuf *sb;
 614         u32 *regs_buff;
 615         int rc;
 616
 617         regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK);
 618         memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
 619
 620         rc = sysctl_wire_old_buffer(req, 0);
 621         MPASS(rc == 0);
 622         if (rc != 0) {
 623                 free(regs_buff, M_DEVBUF);
 624                 return (rc);
 625         }
 626
 627         sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
 628         MPASS(sb != NULL);
 629         if (sb == NULL) {
 630                 free(regs_buff, M_DEVBUF);
 631                 return (ENOMEM);
 632         }
 633
 634         /* General Registers */
 635         regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
 636         regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
 637         regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
 638         regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
 639         regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
 640         regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
 641         regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
 642         regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
 643         regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
 644         regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
 645         regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
 646         regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
 647         regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
 648         regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
 649         regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
 650         regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
 651         regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
 652         regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
 653         regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
 654         regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
 655         regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
 656         regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
 657
 658         sbuf_printf(sb, "General Registers\n");
 659         sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
 660         sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
 661         sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]);
 662
 663         sbuf_printf(sb, "Interrupt Registers\n");
 664         sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
 665
 666         sbuf_printf(sb, "RX Registers\n");
 667         sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
 668         sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
 669         sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
 670         sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
 671         sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
 672         sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
 673         sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
 674
 675         sbuf_printf(sb, "TX Registers\n");
 676         sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
 677         sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
 678         sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
 679         sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
 680         sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
 681         sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
 682         sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
 683         sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
 684         sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
 685         sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
 686         sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
 687
 688         free(regs_buff, M_DEVBUF);
 689
 690 #ifdef DUMP_DESCS
 691         {
 692                 if_softc_ctx_t scctx = adapter->shared;
 693                 struct rx_ring *rxr = &rx_que->rxr;
 694                 struct tx_ring *txr = &tx_que->txr;
 695                 int ntxd = scctx->isc_ntxd[0];
 696                 int nrxd = scctx->isc_nrxd[0];
 697                 int j;
 698
 699         for (j = 0; j < nrxd; j++) {
 700                 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
 701                 u32 length =  le32toh(rxr->rx_base[j].wb.upper.length);
 702                 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 "  Error:%d  Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
 703         }
 704
 705         for (j = 0; j < min(ntxd, 256); j++) {
 706                 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
 707
 708                 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x  eop: %d DD=%d\n",
 709                             j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
 710                             buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
 711
 712         }
 713         }
 714 #endif
 715
 716         rc = sbuf_finish(sb);
 717         sbuf_delete(sb);
 718         return(rc);
 719 }
 720
 721 static void *
 722 em_register(device_t dev)
 723 {
 724         return (&em_sctx_init);
 725 }
 726
 727 static void *
 728 igb_register(device_t dev)
 729 {
 730         return (&igb_sctx_init);
 731 }
 732
 733 static int
 734 em_set_num_queues(if_ctx_t ctx)
 735 {
 736         struct adapter *adapter = iflib_get_softc(ctx);
 737         int maxqueues;
 738
 739         /* Sanity check based on HW */
 740         switch (adapter->hw.mac.type) {
 741         case e1000_82576:
 742         case e1000_82580:
 743         case e1000_i350:
 744         case e1000_i354:
 745                 maxqueues = 8;
 746                 break;
 747         case e1000_i210:
 748         case e1000_82575:
 749                 maxqueues = 4;
 750                 break;
 751         case e1000_i211:
 752         case e1000_82574:
 753                 maxqueues = 2;
 754                 break;
 755         default:
 756                 maxqueues = 1;
 757                 break;
 758         }
 759
 760         return (maxqueues);
 761 }
 762
 763 #define LEM_CAPS                                                        \
 764     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 765     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER
 766
 767 #define EM_CAPS                                                         \
 768     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 769     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 |  \
 770     IFCAP_LRO | IFCAP_VLAN_HWTSO
 771
 772 #define IGB_CAPS                                                        \
 773     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 774     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 |  \
 775     IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\
 776     IFCAP_TSO6
 777
 778 /*********************************************************************
 779  *  Device initialization routine
 780  *
 781  *  The attach entry point is called when the driver is being loaded.
 782  *  This routine identifies the type of hardware, allocates all resources
 783  *  and initializes the hardware.
 784  *
 785  *  return 0 on success, positive on failure
 786  *********************************************************************/
 787 static int
 788 em_if_attach_pre(if_ctx_t ctx)
 789 {
 790         struct adapter *adapter;
 791         if_softc_ctx_t scctx;
 792         device_t dev;
 793         struct e1000_hw *hw;
 794         int error = 0;
 795
 796         INIT_DEBUGOUT("em_if_attach_pre: begin");
 797         dev = iflib_get_dev(ctx);
 798         adapter = iflib_get_softc(ctx);
 799
 800         adapter->ctx = adapter->osdep.ctx = ctx;
 801         adapter->dev = adapter->osdep.dev = dev;
 802         scctx = adapter->shared = iflib_get_softc_ctx(ctx);
 803         adapter->media = iflib_get_media(ctx);
 804         hw = &adapter->hw;
 805
 806         adapter->tx_process_limit = scctx->isc_ntxd[0];
 807
 808         /* SYSCTL stuff */
 809         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 810             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 811             OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
 812             adapter, 0, em_sysctl_nvm_info, "I", "NVM Information");
 813
 814         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 815             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 816             OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
 817             adapter, 0, em_sysctl_debug_info, "I", "Debug Information");
 818
 819         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 820             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 821             OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
 822             adapter, 0, em_set_flowcntl, "I", "Flow Control");
 823
 824         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 825             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 826             OID_AUTO, "reg_dump",
 827             CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 0,
 828             em_get_regs, "A", "Dump Registers");
 829
 830         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 831             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 832             OID_AUTO, "rs_dump",
 833             CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, adapter, 0,
 834             em_get_rs, "I", "Dump RS indexes");
 835
 836         /* Determine hardware and mac info */
 837         em_identify_hardware(ctx);
 838
 839         scctx->isc_tx_nsegments = EM_MAX_SCATTER;
 840         scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
 841         if (bootverbose)
 842                 device_printf(dev, "attach_pre capping queues at %d\n",
 843                     scctx->isc_ntxqsets_max);
 844
 845         if (hw->mac.type >= igb_mac_min) {
 846                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
 847                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
 848                 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
 849                 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
 850                 scctx->isc_txrx = &igb_txrx;
 851                 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
 852                 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 853                 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 854                 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS;
 855                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO |
 856                      CSUM_IP6_TCP | CSUM_IP6_UDP;
 857                 if (hw->mac.type != e1000_82575)
 858                         scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
 859                 /*
 860                 ** Some new devices, as with ixgbe, now may
 861                 ** use a different BAR, so we need to keep
 862                 ** track of which is used.
 863                 */
 864                 scctx->isc_msix_bar = pci_msix_table_bar(dev);
 865         } else if (hw->mac.type >= em_mac_min) {
 866                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 867                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
 868                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 869                 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
 870                 scctx->isc_txrx = &em_txrx;
 871                 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
 872                 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 873                 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 874                 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS;
 875                 /*
 876                  * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO}
 877                  * by default as we don't have workarounds for all associated
 878                  * silicon errata.  E. g., with several MACs such as 82573E,
 879                  * TSO only works at Gigabit speed and otherwise can cause the
 880                  * hardware to hang (which also would be next to impossible to
 881                  * work around given that already queued TSO-using descriptors
 882                  * would need to be flushed and vlan(4) reconfigured at runtime
 883                  * in case of a link speed change).  Moreover, MACs like 82579
 884                  * still can hang at Gigabit even with all publicly documented
 885                  * TSO workarounds implemented.  Generally, the penality of
 886                  * these workarounds is rather high and may involve copying
 887                  * mbuf data around so advantages of TSO lapse.  Still, TSO may
 888                  * work for a few MACs of this class - at least when sticking
 889                  * with Gigabit - in which case users may enable TSO manually.
 890                  */
 891                 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
 892                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 893                 /*
 894                  * We support MSI-X with 82574 only, but indicate to iflib(4)
 895                  * that it shall give MSI at least a try with other devices.
 896                  */
 897                 if (hw->mac.type == e1000_82574) {
 898                         scctx->isc_msix_bar = pci_msix_table_bar(dev);;
 899                 } else {
 900                         scctx->isc_msix_bar = -1;
 901                         scctx->isc_disable_msix = 1;
 902                 }
 903         } else {
 904                 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 905                 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
 906                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 907                 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
 908                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP;
 909                 scctx->isc_txrx = &lem_txrx;
 910                 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS;
 911                 if (hw->mac.type < e1000_82543)
 912                         scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
 913                 /* 82541ER doesn't do HW tagging */
 914                 if (hw->device_id == E1000_DEV_ID_82541ER || hw->device_id == E1000_DEV_ID_82541ER_LOM)
 915                         scctx->isc_capenable &= ~IFCAP_VLAN_HWTAGGING;
 916                 /* INTx only */
 917                 scctx->isc_msix_bar = 0;
 918         }
 919
 920         /* Setup PCI resources */
 921         if (em_allocate_pci_resources(ctx)) {
 922                 device_printf(dev, "Allocation of PCI resources failed\n");
 923                 error = ENXIO;
 924                 goto err_pci;
 925         }
 926
 927         /*
 928         ** For ICH8 and family we need to
 929         ** map the flash memory, and this
 930         ** must happen after the MAC is
 931         ** identified
 932         */
 933         if ((hw->mac.type == e1000_ich8lan) ||
 934             (hw->mac.type == e1000_ich9lan) ||
 935             (hw->mac.type == e1000_ich10lan) ||
 936             (hw->mac.type == e1000_pchlan) ||
 937             (hw->mac.type == e1000_pch2lan) ||
 938             (hw->mac.type == e1000_pch_lpt)) {
 939                 int rid = EM_BAR_TYPE_FLASH;
 940                 adapter->flash = bus_alloc_resource_any(dev,
 941                     SYS_RES_MEMORY, &rid, RF_ACTIVE);
 942                 if (adapter->flash == NULL) {
 943                         device_printf(dev, "Mapping of Flash failed\n");
 944                         error = ENXIO;
 945                         goto err_pci;
 946                 }
 947                 /* This is used in the shared code */
 948                 hw->flash_address = (u8 *)adapter->flash;
 949                 adapter->osdep.flash_bus_space_tag =
 950                     rman_get_bustag(adapter->flash);
 951                 adapter->osdep.flash_bus_space_handle =
 952                     rman_get_bushandle(adapter->flash);
 953         }
 954         /*
 955         ** In the new SPT device flash is not  a
 956         ** separate BAR, rather it is also in BAR0,
 957         ** so use the same tag and an offset handle for the
 958         ** FLASH read/write macros in the shared code.
 959         */
 960         else if (hw->mac.type >= e1000_pch_spt) {
 961                 adapter->osdep.flash_bus_space_tag =
 962                     adapter->osdep.mem_bus_space_tag;
 963                 adapter->osdep.flash_bus_space_handle =
 964                     adapter->osdep.mem_bus_space_handle
 965                     + E1000_FLASH_BASE_ADDR;
 966         }
 967
 968         /* Do Shared Code initialization */
 969         error = e1000_setup_init_funcs(hw, TRUE);
 970         if (error) {
 971                 device_printf(dev, "Setup of Shared code failed, error %d\n",
 972                     error);
 973                 error = ENXIO;
 974                 goto err_pci;
 975         }
 976
 977         em_setup_msix(ctx);
 978         e1000_get_bus_info(hw);
 979
 980         /* Set up some sysctls for the tunable interrupt delays */
 981         em_add_int_delay_sysctl(adapter, "rx_int_delay",
 982             "receive interrupt delay in usecs", &adapter->rx_int_delay,
 983             E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
 984         em_add_int_delay_sysctl(adapter, "tx_int_delay",
 985             "transmit interrupt delay in usecs", &adapter->tx_int_delay,
 986             E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
 987         em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
 988             "receive interrupt delay limit in usecs",
 989             &adapter->rx_abs_int_delay,
 990             E1000_REGISTER(hw, E1000_RADV),
 991             em_rx_abs_int_delay_dflt);
 992         em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
 993             "transmit interrupt delay limit in usecs",
 994             &adapter->tx_abs_int_delay,
 995             E1000_REGISTER(hw, E1000_TADV),
 996             em_tx_abs_int_delay_dflt);
 997         em_add_int_delay_sysctl(adapter, "itr",
 998             "interrupt delay limit in usecs/4",
 999             &adapter->tx_itr,
1000             E1000_REGISTER(hw, E1000_ITR),
1001             DEFAULT_ITR);
1002
1003         hw->mac.autoneg = DO_AUTO_NEG;
1004         hw->phy.autoneg_wait_to_complete = FALSE;
1005         hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1006
1007         if (hw->mac.type < em_mac_min) {
1008                 e1000_init_script_state_82541(hw, TRUE);
1009                 e1000_set_tbi_compatibility_82543(hw, TRUE);
1010         }
1011         /* Copper options */
1012         if (hw->phy.media_type == e1000_media_type_copper) {
1013                 hw->phy.mdix = AUTO_ALL_MODES;
1014                 hw->phy.disable_polarity_correction = FALSE;
1015                 hw->phy.ms_type = EM_MASTER_SLAVE;
1016         }
1017
1018         /*
1019          * Set the frame limits assuming
1020          * standard ethernet sized frames.
1021          */
1022         scctx->isc_max_frame_size = hw->mac.max_frame_size =
1023             ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
1024
1025         /*
1026          * This controls when hardware reports transmit completion
1027          * status.
1028          */
1029         hw->mac.report_tx_early = 1;
1030
1031         /* Allocate multicast array memory. */
1032         adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN *
1033             MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
1034         if (adapter->mta == NULL) {
1035                 device_printf(dev, "Can not allocate multicast setup array\n");
1036                 error = ENOMEM;
1037                 goto err_late;
1038         }
1039
1040         /* Check SOL/IDER usage */
1041         if (e1000_check_reset_block(hw))
1042                 device_printf(dev, "PHY reset is blocked"
1043                               " due to SOL/IDER session.\n");
1044
1045         /* Sysctl for setting Energy Efficient Ethernet */
1046         hw->dev_spec.ich8lan.eee_disable = eee_setting;
1047         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1048             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1049             OID_AUTO, "eee_control",
1050             CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
1051             adapter, 0, em_sysctl_eee, "I",
1052             "Disable Energy Efficient Ethernet");
1053
1054         /*
1055         ** Start from a known state, this is
1056         ** important in reading the nvm and
1057         ** mac from that.
1058         */
1059         e1000_reset_hw(hw);
1060
1061         /* Make sure we have a good EEPROM before we read from it */
1062         if (e1000_validate_nvm_checksum(hw) < 0) {
1063                 /*
1064                 ** Some PCI-E parts fail the first check due to
1065                 ** the link being in sleep state, call it again,
1066                 ** if it fails a second time its a real issue.
1067                 */
1068                 if (e1000_validate_nvm_checksum(hw) < 0) {
1069                         device_printf(dev,
1070                             "The EEPROM Checksum Is Not Valid\n");
1071                         error = EIO;
1072                         goto err_late;
1073                 }
1074         }
1075
1076         /* Copy the permanent MAC address out of the EEPROM */
1077         if (e1000_read_mac_addr(hw) < 0) {
1078                 device_printf(dev, "EEPROM read error while reading MAC"
1079                               " address\n");
1080                 error = EIO;
1081                 goto err_late;
1082         }
1083
1084         if (!em_is_valid_ether_addr(hw->mac.addr)) {
1085                 if (adapter->vf_ifp) {
1086                         ether_gen_addr(iflib_get_ifp(ctx),
1087                             (struct ether_addr *)hw->mac.addr);
1088                 } else {
1089                         device_printf(dev, "Invalid MAC address\n");
1090                         error = EIO;
1091                         goto err_late;
1092                 }
1093         }
1094
1095         /* Disable ULP support */
1096         e1000_disable_ulp_lpt_lp(hw, TRUE);
1097
1098         /*
1099          * Get Wake-on-Lan and Management info for later use
1100          */
1101         em_get_wakeup(ctx);
1102
1103         /* Enable only WOL MAGIC by default */
1104         scctx->isc_capenable &= ~IFCAP_WOL;
1105         if (adapter->wol != 0)
1106                 scctx->isc_capenable |= IFCAP_WOL_MAGIC;
1107
1108         iflib_set_mac(ctx, hw->mac.addr);
1109
1110         return (0);
1111
1112 err_late:
1113         em_release_hw_control(adapter);
1114 err_pci:
1115         em_free_pci_resources(ctx);
1116         free(adapter->mta, M_DEVBUF);
1117
1118         return (error);
1119 }
1120
1121 static int
1122 em_if_attach_post(if_ctx_t ctx)
1123 {
1124         struct adapter *adapter = iflib_get_softc(ctx);
1125         struct e1000_hw *hw = &adapter->hw;
1126         int error = 0;
1127
1128         /* Setup OS specific network interface */
1129         error = em_setup_interface(ctx);
1130         if (error != 0) {
1131                 device_printf(adapter->dev, "Interface setup failed: %d\n", error);
1132                 goto err_late;
1133         }
1134
1135         em_reset(ctx);
1136
1137         /* Initialize statistics */
1138         em_update_stats_counters(adapter);
1139         hw->mac.get_link_status = 1;
1140         em_if_update_admin_status(ctx);
1141         em_add_hw_stats(adapter);
1142
1143         /* Non-AMT based hardware can now take control from firmware */
1144         if (adapter->has_manage && !adapter->has_amt)
1145                 em_get_hw_control(adapter);
1146
1147         INIT_DEBUGOUT("em_if_attach_post: end");
1148
1149         return (0);
1150
1151 err_late:
1152         /* upon attach_post() error, iflib calls _if_detach() to free resources. */
1153         return (error);
1154 }
1155
1156 /*********************************************************************
1157  *  Device removal routine
1158  *
1159  *  The detach entry point is called when the driver is being removed.
1160  *  This routine stops the adapter and deallocates all the resources
1161  *  that were allocated for driver operation.
1162  *
1163  *  return 0 on success, positive on failure
1164  *********************************************************************/
1165 static int
1166 em_if_detach(if_ctx_t ctx)
1167 {
1168         struct adapter  *adapter = iflib_get_softc(ctx);
1169
1170         INIT_DEBUGOUT("em_if_detach: begin");
1171
1172         e1000_phy_hw_reset(&adapter->hw);
1173
1174         em_release_manageability(adapter);
1175         em_release_hw_control(adapter);
1176         em_free_pci_resources(ctx);
1177         free(adapter->mta, M_DEVBUF);
1178         adapter->mta = NULL;
1179
1180         return (0);
1181 }
1182
1183 /*********************************************************************
1184  *
1185  *  Shutdown entry point
1186  *
1187  **********************************************************************/
1188
1189 static int
1190 em_if_shutdown(if_ctx_t ctx)
1191 {
1192         return em_if_suspend(ctx);
1193 }
1194
1195 /*
1196  * Suspend/resume device methods.
1197  */
1198 static int
1199 em_if_suspend(if_ctx_t ctx)
1200 {
1201         struct adapter *adapter = iflib_get_softc(ctx);
1202
1203         em_release_manageability(adapter);
1204         em_release_hw_control(adapter);
1205         em_enable_wakeup(ctx);
1206         return (0);
1207 }
1208
1209 static int
1210 em_if_resume(if_ctx_t ctx)
1211 {
1212         struct adapter *adapter = iflib_get_softc(ctx);
1213
1214         if (adapter->hw.mac.type == e1000_pch2lan)
1215                 e1000_resume_workarounds_pchlan(&adapter->hw);
1216         em_if_init(ctx);
1217         em_init_manageability(adapter);
1218
1219         return(0);
1220 }
1221
1222 static int
1223 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1224 {
1225         int max_frame_size;
1226         struct adapter *adapter = iflib_get_softc(ctx);
1227         if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1228
1229         IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1230
1231         switch (adapter->hw.mac.type) {
1232         case e1000_82571:
1233         case e1000_82572:
1234         case e1000_ich9lan:
1235         case e1000_ich10lan:
1236         case e1000_pch2lan:
1237         case e1000_pch_lpt:
1238         case e1000_pch_spt:
1239         case e1000_pch_cnp:
1240         case e1000_pch_tgp:
1241         case e1000_pch_adp:
1242         case e1000_pch_mtp:
1243         case e1000_82574:
1244         case e1000_82583:
1245         case e1000_80003es2lan:
1246                 /* 9K Jumbo Frame size */
1247                 max_frame_size = 9234;
1248                 break;
1249         case e1000_pchlan:
1250                 max_frame_size = 4096;
1251                 break;
1252         case e1000_82542:
1253         case e1000_ich8lan:
1254                 /* Adapters that do not support jumbo frames */
1255                 max_frame_size = ETHER_MAX_LEN;
1256                 break;
1257         default:
1258                 if (adapter->hw.mac.type >= igb_mac_min)
1259                         max_frame_size = 9234;
1260                 else /* lem */
1261                         max_frame_size = MAX_JUMBO_FRAME_SIZE;
1262         }
1263         if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1264                 return (EINVAL);
1265         }
1266
1267         scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
1268             mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1269         return (0);
1270 }
1271
1272 /*********************************************************************
1273  *  Init entry point
1274  *
1275  *  This routine is used in two ways. It is used by the stack as
1276  *  init entry point in network interface structure. It is also used
1277  *  by the driver as a hw/sw initialization routine to get to a
1278  *  consistent state.
1279  *
1280  **********************************************************************/
1281 static void
1282 em_if_init(if_ctx_t ctx)
1283 {
1284         struct adapter *adapter = iflib_get_softc(ctx);
1285         if_softc_ctx_t scctx = adapter->shared;
1286         struct ifnet *ifp = iflib_get_ifp(ctx);
1287         struct em_tx_queue *tx_que;
1288         int i;
1289
1290         INIT_DEBUGOUT("em_if_init: begin");
1291
1292         /* Get the latest mac address, User can use a LAA */
1293         bcopy(if_getlladdr(ifp), adapter->hw.mac.addr,
1294             ETHER_ADDR_LEN);
1295
1296         /* Put the address into the Receive Address Array */
1297         e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1298
1299         /*
1300          * With the 82571 adapter, RAR[0] may be overwritten
1301          * when the other port is reset, we make a duplicate
1302          * in RAR[14] for that eventuality, this assures
1303          * the interface continues to function.
1304          */
1305         if (adapter->hw.mac.type == e1000_82571) {
1306                 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1307                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1308                     E1000_RAR_ENTRIES - 1);
1309         }
1310
1311
1312         /* Initialize the hardware */
1313         em_reset(ctx);
1314         em_if_update_admin_status(ctx);
1315
1316         for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) {
1317                 struct tx_ring *txr = &tx_que->txr;
1318
1319                 txr->tx_rs_cidx = txr->tx_rs_pidx;
1320
1321                 /* Initialize the last processed descriptor to be the end of
1322                  * the ring, rather than the start, so that we avoid an
1323                  * off-by-one error when calculating how many descriptors are
1324                  * done in the credits_update function.
1325                  */
1326                 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
1327         }
1328
1329         /* Setup VLAN support, basic and offload if available */
1330         E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1331
1332         /* Clear bad data from Rx FIFOs */
1333         if (adapter->hw.mac.type >= igb_mac_min)
1334                 e1000_rx_fifo_flush_82575(&adapter->hw);
1335
1336         /* Configure for OS presence */
1337         em_init_manageability(adapter);
1338
1339         /* Prepare transmit descriptors and buffers */
1340         em_initialize_transmit_unit(ctx);
1341
1342         /* Setup Multicast table */
1343         em_if_multi_set(ctx);
1344
1345         adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx);
1346         em_initialize_receive_unit(ctx);
1347
1348         /* Set up VLAN support and filter */
1349         em_setup_vlan_hw_support(adapter);
1350
1351         /* Don't lose promiscuous settings */
1352         em_if_set_promisc(ctx, if_getflags(ifp));
1353         e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1354
1355         /* MSI-X configuration for 82574 */
1356         if (adapter->hw.mac.type == e1000_82574) {
1357                 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1358
1359                 tmp |= E1000_CTRL_EXT_PBA_CLR;
1360                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1361                 /* Set the IVAR - interrupt vector routing. */
1362                 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars);
1363         } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1364                 igb_configure_queues(adapter);
1365
1366         /* this clears any pending interrupts */
1367         E1000_READ_REG(&adapter->hw, E1000_ICR);
1368         E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC);
1369
1370         /* AMT based hardware can now take control from firmware */
1371         if (adapter->has_manage && adapter->has_amt)
1372                 em_get_hw_control(adapter);
1373
1374         /* Set Energy Efficient Ethernet */
1375         if (adapter->hw.mac.type >= igb_mac_min &&
1376             adapter->hw.phy.media_type == e1000_media_type_copper) {
1377                 if (adapter->hw.mac.type == e1000_i354)
1378                         e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
1379                 else
1380                         e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
1381         }
1382 }
1383
1384 /*********************************************************************
1385  *
1386  *  Fast Legacy/MSI Combined Interrupt Service routine
1387  *
1388  *********************************************************************/
1389 int
1390 em_intr(void *arg)
1391 {
1392         struct adapter *adapter = arg;
1393         if_ctx_t ctx = adapter->ctx;
1394         u32 reg_icr;
1395
1396         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1397
1398         /* Hot eject? */
1399         if (reg_icr == 0xffffffff)
1400                 return FILTER_STRAY;
1401
1402         /* Definitely not our interrupt. */
1403         if (reg_icr == 0x0)
1404                 return FILTER_STRAY;
1405
1406         /*
1407          * Starting with the 82571 chip, bit 31 should be used to
1408          * determine whether the interrupt belongs to us.
1409          */
1410         if (adapter->hw.mac.type >= e1000_82571 &&
1411             (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1412                 return FILTER_STRAY;
1413
1414         /*
1415          * Only MSI-X interrupts have one-shot behavior by taking advantage
1416          * of the EIAC register.  Thus, explicitly disable interrupts.  This
1417          * also works around the MSI message reordering errata on certain
1418          * systems.
1419          */
1420         IFDI_INTR_DISABLE(ctx);
1421
1422         /* Link status change */
1423         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))
1424                 em_handle_link(ctx);
1425
1426         if (reg_icr & E1000_ICR_RXO)
1427                 adapter->rx_overruns++;
1428
1429         return (FILTER_SCHEDULE_THREAD);
1430 }
1431
1432 static int
1433 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1434 {
1435         struct adapter *adapter = iflib_get_softc(ctx);
1436         struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1437
1438         E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims);
1439         return (0);
1440 }
1441
1442 static int
1443 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1444 {
1445         struct adapter *adapter = iflib_get_softc(ctx);
1446         struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1447
1448         E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims);
1449         return (0);
1450 }
1451
1452 static int
1453 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1454 {
1455         struct adapter *adapter = iflib_get_softc(ctx);
1456         struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1457
1458         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims);
1459         return (0);
1460 }
1461
1462 static int
1463 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1464 {
1465         struct adapter *adapter = iflib_get_softc(ctx);
1466         struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1467
1468         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims);
1469         return (0);
1470 }
1471
1472 /*********************************************************************
1473  *
1474  *  MSI-X RX Interrupt Service routine
1475  *
1476  **********************************************************************/
1477 static int
1478 em_msix_que(void *arg)
1479 {
1480         struct em_rx_queue *que = arg;
1481
1482         ++que->irqs;
1483
1484         return (FILTER_SCHEDULE_THREAD);
1485 }
1486
1487 /*********************************************************************
1488  *
1489  *  MSI-X Link Fast Interrupt Service routine
1490  *
1491  **********************************************************************/
1492 static int
1493 em_msix_link(void *arg)
1494 {
1495         struct adapter *adapter = arg;
1496         u32 reg_icr;
1497         bool notlink = false;
1498
1499         ++adapter->link_irq;
1500         MPASS(adapter->hw.back != NULL);
1501         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1502
1503         if (reg_icr & E1000_ICR_RXO)
1504                 adapter->rx_overruns++;
1505
1506         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))
1507                 em_handle_link(adapter->ctx);
1508         else
1509                 notlink = true;
1510
1511         /* Re-arm for other/spurious interrupts */
1512         if (notlink && adapter->hw.mac.type >= igb_mac_min) {
1513                 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC);
1514                 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1515         } else if (adapter->hw.mac.type == e1000_82574) {
1516                 if (notlink)
1517                         E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC |
1518                             E1000_IMS_OTHER);
1519                 /*
1520                  * Because we must read the ICR for this interrupt it may
1521                  * clear other causes using autoclear, for this reason we
1522                  * simply create a soft interrupt for all these vectors.
1523                  */
1524                 if (reg_icr)
1525                         E1000_WRITE_REG(&adapter->hw, E1000_ICS, adapter->ims);
1526         }
1527
1528         return (FILTER_HANDLED);
1529 }
1530
1531 static void
1532 em_handle_link(void *context)
1533 {
1534         if_ctx_t ctx = context;
1535         struct adapter *adapter = iflib_get_softc(ctx);
1536
1537         adapter->hw.mac.get_link_status = 1;
1538         iflib_admin_intr_deferred(ctx);
1539 }
1540
1541 /*********************************************************************
1542  *
1543  *  Media Ioctl callback
1544  *
1545  *  This routine is called whenever the user queries the status of
1546  *  the interface using ifconfig.
1547  *
1548  **********************************************************************/
1549 static void
1550 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1551 {
1552         struct adapter *adapter = iflib_get_softc(ctx);
1553         u_char fiber_type = IFM_1000_SX;
1554
1555         INIT_DEBUGOUT("em_if_media_status: begin");
1556
1557         iflib_admin_intr_deferred(ctx);
1558
1559         ifmr->ifm_status = IFM_AVALID;
1560         ifmr->ifm_active = IFM_ETHER;
1561
1562         if (!adapter->link_active) {
1563                 return;
1564         }
1565
1566         ifmr->ifm_status |= IFM_ACTIVE;
1567
1568         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
1569             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1570                 if (adapter->hw.mac.type == e1000_82545)
1571                         fiber_type = IFM_1000_LX;
1572                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1573         } else {
1574                 switch (adapter->link_speed) {
1575                 case 10:
1576                         ifmr->ifm_active |= IFM_10_T;
1577                         break;
1578                 case 100:
1579                         ifmr->ifm_active |= IFM_100_TX;
1580                         break;
1581                 case 1000:
1582                         ifmr->ifm_active |= IFM_1000_T;
1583                         break;
1584                 }
1585                 if (adapter->link_duplex == FULL_DUPLEX)
1586                         ifmr->ifm_active |= IFM_FDX;
1587                 else
1588                         ifmr->ifm_active |= IFM_HDX;
1589         }
1590 }
1591
1592 /*********************************************************************
1593  *
1594  *  Media Ioctl callback
1595  *
1596  *  This routine is called when the user changes speed/duplex using
1597  *  media/mediopt option with ifconfig.
1598  *
1599  **********************************************************************/
1600 static int
1601 em_if_media_change(if_ctx_t ctx)
1602 {
1603         struct adapter *adapter = iflib_get_softc(ctx);
1604         struct ifmedia *ifm = iflib_get_media(ctx);
1605
1606         INIT_DEBUGOUT("em_if_media_change: begin");
1607
1608         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1609                 return (EINVAL);
1610
1611         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1612         case IFM_AUTO:
1613                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1614                 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1615                 break;
1616         case IFM_1000_LX:
1617         case IFM_1000_SX:
1618         case IFM_1000_T:
1619                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1620                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1621                 break;
1622         case IFM_100_TX:
1623                 adapter->hw.mac.autoneg = FALSE;
1624                 adapter->hw.phy.autoneg_advertised = 0;
1625                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1626                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1627                 else
1628                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1629                 break;
1630         case IFM_10_T:
1631                 adapter->hw.mac.autoneg = FALSE;
1632                 adapter->hw.phy.autoneg_advertised = 0;
1633                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1634                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1635                 else
1636                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1637                 break;
1638         default:
1639                 device_printf(adapter->dev, "Unsupported media type\n");
1640         }
1641
1642         em_if_init(ctx);
1643
1644         return (0);
1645 }
1646
1647 static int
1648 em_if_set_promisc(if_ctx_t ctx, int flags)
1649 {
1650         struct adapter *adapter = iflib_get_softc(ctx);
1651         struct ifnet *ifp = iflib_get_ifp(ctx);
1652         u32 reg_rctl;
1653         int mcnt = 0;
1654
1655         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1656         reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE);
1657         if (flags & IFF_ALLMULTI)
1658                 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1659         else
1660                 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES);
1661
1662         if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1663                 reg_rctl &= (~E1000_RCTL_MPE);
1664         E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1665
1666         if (flags & IFF_PROMISC) {
1667                 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1668                 em_if_vlan_filter_disable(adapter);
1669                 /* Turn this on if you want to see bad packets */
1670                 if (em_debug_sbp)
1671                         reg_rctl |= E1000_RCTL_SBP;
1672                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1673         } else {
1674                 if (flags & IFF_ALLMULTI) {
1675                         reg_rctl |= E1000_RCTL_MPE;
1676                         reg_rctl &= ~E1000_RCTL_UPE;
1677                         E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1678                 }
1679                 if (em_if_vlan_filter_used(adapter))
1680                         em_if_vlan_filter_enable(adapter);
1681         }
1682         return (0);
1683 }
1684
1685 static u_int
1686 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx)
1687 {
1688         u8 *mta = arg;
1689
1690         if (idx == MAX_NUM_MULTICAST_ADDRESSES)
1691                 return (0);
1692
1693         bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1694
1695         return (1);
1696 }
1697
1698 /*********************************************************************
1699  *  Multicast Update
1700  *
1701  *  This routine is called whenever multicast address list is updated.
1702  *
1703  **********************************************************************/
1704 static void
1705 em_if_multi_set(if_ctx_t ctx)
1706 {
1707         struct adapter *adapter = iflib_get_softc(ctx);
1708         struct ifnet *ifp = iflib_get_ifp(ctx);
1709         u8  *mta; /* Multicast array memory */
1710         u32 reg_rctl = 0;
1711         int mcnt = 0;
1712
1713         IOCTL_DEBUGOUT("em_set_multi: begin");
1714
1715         mta = adapter->mta;
1716         bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1717
1718         if (adapter->hw.mac.type == e1000_82542 &&
1719             adapter->hw.revision_id == E1000_REVISION_2) {
1720                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1721                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1722                         e1000_pci_clear_mwi(&adapter->hw);
1723                 reg_rctl |= E1000_RCTL_RST;
1724                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1725                 msec_delay(5);
1726         }
1727
1728         mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta);
1729
1730         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1731
1732         if (if_getflags(ifp) & IFF_PROMISC)
1733                 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1734         else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES ||
1735             if_getflags(ifp) & IFF_ALLMULTI) {
1736                 reg_rctl |= E1000_RCTL_MPE;
1737                 reg_rctl &= ~E1000_RCTL_UPE;
1738         } else
1739                 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
1740
1741         E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1742
1743         if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1744                 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
1745
1746         if (adapter->hw.mac.type == e1000_82542 &&
1747             adapter->hw.revision_id == E1000_REVISION_2) {
1748                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1749                 reg_rctl &= ~E1000_RCTL_RST;
1750                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1751                 msec_delay(5);
1752                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1753                         e1000_pci_set_mwi(&adapter->hw);
1754         }
1755 }
1756
1757 /*********************************************************************
1758  *  Timer routine
1759  *
1760  *  This routine schedules em_if_update_admin_status() to check for
1761  *  link status and to gather statistics as well as to perform some
1762  *  controller-specific hardware patting.
1763  *
1764  **********************************************************************/
1765 static void
1766 em_if_timer(if_ctx_t ctx, uint16_t qid)
1767 {
1768
1769         if (qid != 0)
1770                 return;
1771
1772         iflib_admin_intr_deferred(ctx);
1773 }
1774
1775 static void
1776 em_if_update_admin_status(if_ctx_t ctx)
1777 {
1778         struct adapter *adapter = iflib_get_softc(ctx);
1779         struct e1000_hw *hw = &adapter->hw;
1780         device_t dev = iflib_get_dev(ctx);
1781         u32 link_check, thstat, ctrl;
1782
1783         link_check = thstat = ctrl = 0;
1784         /* Get the cached link value or read phy for real */
1785         switch (hw->phy.media_type) {
1786         case e1000_media_type_copper:
1787                 if (hw->mac.get_link_status) {
1788                         if (hw->mac.type == e1000_pch_spt)
1789                                 msec_delay(50);
1790                         /* Do the work to read phy */
1791                         e1000_check_for_link(hw);
1792                         link_check = !hw->mac.get_link_status;
1793                         if (link_check) /* ESB2 fix */
1794                                 e1000_cfg_on_link_up(hw);
1795                 } else {
1796                         link_check = TRUE;
1797                 }
1798                 break;
1799         case e1000_media_type_fiber:
1800                 e1000_check_for_link(hw);
1801                 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1802                             E1000_STATUS_LU);
1803                 break;
1804         case e1000_media_type_internal_serdes:
1805                 e1000_check_for_link(hw);
1806                 link_check = hw->mac.serdes_has_link;
1807                 break;
1808         /* VF device is type_unknown */
1809         case e1000_media_type_unknown:
1810                 e1000_check_for_link(hw);
1811                 link_check = !hw->mac.get_link_status;
1812                 /* FALLTHROUGH */
1813         default:
1814                 break;
1815         }
1816
1817         /* Check for thermal downshift or shutdown */
1818         if (hw->mac.type == e1000_i350) {
1819                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1820                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1821         }
1822
1823         /* Now check for a transition */
1824         if (link_check && (adapter->link_active == 0)) {
1825                 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
1826                     &adapter->link_duplex);
1827                 /* Check if we must disable SPEED_MODE bit on PCI-E */
1828                 if ((adapter->link_speed != SPEED_1000) &&
1829                     ((hw->mac.type == e1000_82571) ||
1830                     (hw->mac.type == e1000_82572))) {
1831                         int tarc0;
1832                         tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1833                         tarc0 &= ~TARC_SPEED_MODE_BIT;
1834                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1835                 }
1836                 if (bootverbose)
1837                         device_printf(dev, "Link is up %d Mbps %s\n",
1838                             adapter->link_speed,
1839                             ((adapter->link_duplex == FULL_DUPLEX) ?
1840                             "Full Duplex" : "Half Duplex"));
1841                 adapter->link_active = 1;
1842                 adapter->smartspeed = 0;
1843                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) ==
1844                     E1000_CTRL_EXT_LINK_MODE_GMII &&
1845                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1846                         device_printf(dev, "Link: thermal downshift\n");
1847                 /* Delay Link Up for Phy update */
1848                 if (((hw->mac.type == e1000_i210) ||
1849                     (hw->mac.type == e1000_i211)) &&
1850                     (hw->phy.id == I210_I_PHY_ID))
1851                         msec_delay(I210_LINK_DELAY);
1852                 /* Reset if the media type changed. */
1853                 if (hw->dev_spec._82575.media_changed &&
1854                     hw->mac.type >= igb_mac_min) {
1855                         hw->dev_spec._82575.media_changed = false;
1856                         adapter->flags |= IGB_MEDIA_RESET;
1857                         em_reset(ctx);
1858                 }
1859                 iflib_link_state_change(ctx, LINK_STATE_UP,
1860                     IF_Mbps(adapter->link_speed));
1861         } else if (!link_check && (adapter->link_active == 1)) {
1862                 adapter->link_speed = 0;
1863                 adapter->link_duplex = 0;
1864                 adapter->link_active = 0;
1865                 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
1866         }
1867         em_update_stats_counters(adapter);
1868
1869         /* Reset LAA into RAR[0] on 82571 */
1870         if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw))
1871                 e1000_rar_set(hw, hw->mac.addr, 0);
1872
1873         if (hw->mac.type < em_mac_min)
1874                 lem_smartspeed(adapter);
1875         else if (hw->mac.type >= igb_mac_min &&
1876             adapter->intr_type == IFLIB_INTR_MSIX) {
1877                 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC);
1878                 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1879         } else if (hw->mac.type == e1000_82574 &&
1880             adapter->intr_type == IFLIB_INTR_MSIX)
1881                 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
1882 }
1883
1884 static void
1885 em_if_watchdog_reset(if_ctx_t ctx)
1886 {
1887         struct adapter *adapter = iflib_get_softc(ctx);
1888
1889         /*
1890          * Just count the event; iflib(4) will already trigger a
1891          * sufficient reset of the controller.
1892          */
1893         adapter->watchdog_events++;
1894 }
1895
1896 /*********************************************************************
1897  *
1898  *  This routine disables all traffic on the adapter by issuing a
1899  *  global reset on the MAC.
1900  *
1901  **********************************************************************/
1902 static void
1903 em_if_stop(if_ctx_t ctx)
1904 {
1905         struct adapter *adapter = iflib_get_softc(ctx);
1906
1907         INIT_DEBUGOUT("em_if_stop: begin");
1908
1909         e1000_reset_hw(&adapter->hw);
1910         if (adapter->hw.mac.type >= e1000_82544)
1911                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0);
1912
1913         e1000_led_off(&adapter->hw);
1914         e1000_cleanup_led(&adapter->hw);
1915 }
1916
1917 /*********************************************************************
1918  *
1919  *  Determine hardware revision.
1920  *
1921  **********************************************************************/
1922 static void
1923 em_identify_hardware(if_ctx_t ctx)
1924 {
1925         device_t dev = iflib_get_dev(ctx);
1926         struct adapter *adapter = iflib_get_softc(ctx);
1927
1928         /* Make sure our PCI config space has the necessary stuff set */
1929         adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1930
1931         /* Save off the information about this board */
1932         adapter->hw.vendor_id = pci_get_vendor(dev);
1933         adapter->hw.device_id = pci_get_device(dev);
1934         adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1935         adapter->hw.subsystem_vendor_id =
1936             pci_read_config(dev, PCIR_SUBVEND_0, 2);
1937         adapter->hw.subsystem_device_id =
1938             pci_read_config(dev, PCIR_SUBDEV_0, 2);
1939
1940         /* Do Shared Code Init and Setup */
1941         if (e1000_set_mac_type(&adapter->hw)) {
1942                 device_printf(dev, "Setup init failure\n");
1943                 return;
1944         }
1945
1946         /* Are we a VF device? */
1947         if ((adapter->hw.mac.type == e1000_vfadapt) ||
1948             (adapter->hw.mac.type == e1000_vfadapt_i350))
1949                 adapter->vf_ifp = 1;
1950         else
1951                 adapter->vf_ifp = 0;
1952 }
1953
1954 static int
1955 em_allocate_pci_resources(if_ctx_t ctx)
1956 {
1957         struct adapter *adapter = iflib_get_softc(ctx);
1958         device_t dev = iflib_get_dev(ctx);
1959         int rid, val;
1960
1961         rid = PCIR_BAR(0);
1962         adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1963             &rid, RF_ACTIVE);
1964         if (adapter->memory == NULL) {
1965                 device_printf(dev, "Unable to allocate bus resource: memory\n");
1966                 return (ENXIO);
1967         }
1968         adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory);
1969         adapter->osdep.mem_bus_space_handle =
1970             rman_get_bushandle(adapter->memory);
1971         adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle;
1972
1973         /* Only older adapters use IO mapping */
1974         if (adapter->hw.mac.type < em_mac_min &&
1975             adapter->hw.mac.type > e1000_82543) {
1976                 /* Figure our where our IO BAR is ? */
1977                 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1978                         val = pci_read_config(dev, rid, 4);
1979                         if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1980                                 break;
1981                         }
1982                         rid += 4;
1983                         /* check for 64bit BAR */
1984                         if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1985                                 rid += 4;
1986                 }
1987                 if (rid >= PCIR_CIS) {
1988                         device_printf(dev, "Unable to locate IO BAR\n");
1989                         return (ENXIO);
1990                 }
1991                 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
1992                     &rid, RF_ACTIVE);
1993                 if (adapter->ioport == NULL) {
1994                         device_printf(dev, "Unable to allocate bus resource: "
1995                             "ioport\n");
1996                         return (ENXIO);
1997                 }
1998                 adapter->hw.io_base = 0;
1999                 adapter->osdep.io_bus_space_tag =
2000                     rman_get_bustag(adapter->ioport);
2001                 adapter->osdep.io_bus_space_handle =
2002                     rman_get_bushandle(adapter->ioport);
2003         }
2004
2005         adapter->hw.back = &adapter->osdep;
2006
2007         return (0);
2008 }
2009
2010 /*********************************************************************
2011  *
2012  *  Set up the MSI-X Interrupt handlers
2013  *
2014  **********************************************************************/
2015 static int
2016 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
2017 {
2018         struct adapter *adapter = iflib_get_softc(ctx);
2019         struct em_rx_queue *rx_que = adapter->rx_queues;
2020         struct em_tx_queue *tx_que = adapter->tx_queues;
2021         int error, rid, i, vector = 0, rx_vectors;
2022         char buf[16];
2023
2024         /* First set up ring resources */
2025         for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) {
2026                 rid = vector + 1;
2027                 snprintf(buf, sizeof(buf), "rxq%d", i);
2028                 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
2029                 if (error) {
2030                         device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
2031                         adapter->rx_num_queues = i + 1;
2032                         goto fail;
2033                 }
2034
2035                 rx_que->msix =  vector;
2036
2037                 /*
2038                  * Set the bit to enable interrupt
2039                  * in E1000_IMS -- bits 20 and 21
2040                  * are for RX0 and RX1, note this has
2041                  * NOTHING to do with the MSI-X vector
2042                  */
2043                 if (adapter->hw.mac.type == e1000_82574) {
2044                         rx_que->eims = 1 << (20 + i);
2045                         adapter->ims |= rx_que->eims;
2046                         adapter->ivars |= (8 | rx_que->msix) << (i * 4);
2047                 } else if (adapter->hw.mac.type == e1000_82575)
2048                         rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
2049                 else
2050                         rx_que->eims = 1 << vector;
2051         }
2052         rx_vectors = vector;
2053
2054         vector = 0;
2055         for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) {
2056                 snprintf(buf, sizeof(buf), "txq%d", i);
2057                 tx_que = &adapter->tx_queues[i];
2058                 iflib_softirq_alloc_generic(ctx,
2059                     &adapter->rx_queues[i % adapter->rx_num_queues].que_irq,
2060                     IFLIB_INTR_TX, tx_que, tx_que->me, buf);
2061
2062                 tx_que->msix = (vector % adapter->rx_num_queues);
2063
2064                 /*
2065                  * Set the bit to enable interrupt
2066                  * in E1000_IMS -- bits 22 and 23
2067                  * are for TX0 and TX1, note this has
2068                  * NOTHING to do with the MSI-X vector
2069                  */
2070                 if (adapter->hw.mac.type == e1000_82574) {
2071                         tx_que->eims = 1 << (22 + i);
2072                         adapter->ims |= tx_que->eims;
2073                         adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
2074                 } else if (adapter->hw.mac.type == e1000_82575) {
2075                         tx_que->eims = E1000_EICR_TX_QUEUE0 << i;
2076                 } else {
2077                         tx_que->eims = 1 << i;
2078                 }
2079         }
2080
2081         /* Link interrupt */
2082         rid = rx_vectors + 1;
2083         error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq");
2084
2085         if (error) {
2086                 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
2087                 goto fail;
2088         }
2089         adapter->linkvec = rx_vectors;
2090         if (adapter->hw.mac.type < igb_mac_min) {
2091                 adapter->ivars |=  (8 | rx_vectors) << 16;
2092                 adapter->ivars |= 0x80000000;
2093                 /* Enable the "Other" interrupt type for link status change */
2094                 adapter->ims |= E1000_IMS_OTHER;
2095         }
2096
2097         return (0);
2098 fail:
2099         iflib_irq_free(ctx, &adapter->irq);
2100         rx_que = adapter->rx_queues;
2101         for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++)
2102                 iflib_irq_free(ctx, &rx_que->que_irq);
2103         return (error);
2104 }
2105
2106 static void
2107 igb_configure_queues(struct adapter *adapter)
2108 {
2109         struct e1000_hw *hw = &adapter->hw;
2110         struct em_rx_queue *rx_que;
2111         struct em_tx_queue *tx_que;
2112         u32 tmp, ivar = 0, newitr = 0;
2113
2114         /* First turn on RSS capability */
2115         if (hw->mac.type != e1000_82575)
2116                 E1000_WRITE_REG(hw, E1000_GPIE,
2117                     E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
2118                     E1000_GPIE_PBA | E1000_GPIE_NSICR);
2119
2120         /* Turn on MSI-X */
2121         switch (hw->mac.type) {
2122         case e1000_82580:
2123         case e1000_i350:
2124         case e1000_i354:
2125         case e1000_i210:
2126         case e1000_i211:
2127         case e1000_vfadapt:
2128         case e1000_vfadapt_i350:
2129                 /* RX entries */
2130                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2131                         u32 index = i >> 1;
2132                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2133                         rx_que = &adapter->rx_queues[i];
2134                         if (i & 1) {
2135                                 ivar &= 0xFF00FFFF;
2136                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2137                         } else {
2138                                 ivar &= 0xFFFFFF00;
2139                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2140                         }
2141                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2142                 }
2143                 /* TX entries */
2144                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2145                         u32 index = i >> 1;
2146                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2147                         tx_que = &adapter->tx_queues[i];
2148                         if (i & 1) {
2149                                 ivar &= 0x00FFFFFF;
2150                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2151                         } else {
2152                                 ivar &= 0xFFFF00FF;
2153                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2154                         }
2155                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2156                         adapter->que_mask |= tx_que->eims;
2157                 }
2158
2159                 /* And for the link interrupt */
2160                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2161                 adapter->link_mask = 1 << adapter->linkvec;
2162                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2163                 break;
2164         case e1000_82576:
2165                 /* RX entries */
2166                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2167                         u32 index = i & 0x7; /* Each IVAR has two entries */
2168                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2169                         rx_que = &adapter->rx_queues[i];
2170                         if (i < 8) {
2171                                 ivar &= 0xFFFFFF00;
2172                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2173                         } else {
2174                                 ivar &= 0xFF00FFFF;
2175                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2176                         }
2177                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2178                         adapter->que_mask |= rx_que->eims;
2179                 }
2180                 /* TX entries */
2181                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2182                         u32 index = i & 0x7; /* Each IVAR has two entries */
2183                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2184                         tx_que = &adapter->tx_queues[i];
2185                         if (i < 8) {
2186                                 ivar &= 0xFFFF00FF;
2187                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2188                         } else {
2189                                 ivar &= 0x00FFFFFF;
2190                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2191                         }
2192                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2193                         adapter->que_mask |= tx_que->eims;
2194                 }
2195
2196                 /* And for the link interrupt */
2197                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2198                 adapter->link_mask = 1 << adapter->linkvec;
2199                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2200                 break;
2201
2202         case e1000_82575:
2203                 /* enable MSI-X support*/
2204                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2205                 tmp |= E1000_CTRL_EXT_PBA_CLR;
2206                 /* Auto-Mask interrupts upon ICR read. */
2207                 tmp |= E1000_CTRL_EXT_EIAME;
2208                 tmp |= E1000_CTRL_EXT_IRCA;
2209                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2210
2211                 /* Queues */
2212                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2213                         rx_que = &adapter->rx_queues[i];
2214                         tmp = E1000_EICR_RX_QUEUE0 << i;
2215                         tmp |= E1000_EICR_TX_QUEUE0 << i;
2216                         rx_que->eims = tmp;
2217                         E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2218                             i, rx_que->eims);
2219                         adapter->que_mask |= rx_que->eims;
2220                 }
2221
2222                 /* Link */
2223                 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec),
2224                     E1000_EIMS_OTHER);
2225                 adapter->link_mask |= E1000_EIMS_OTHER;
2226         default:
2227                 break;
2228         }
2229
2230         /* Set the starting interrupt rate */
2231         if (em_max_interrupt_rate > 0)
2232                 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2233
2234         if (hw->mac.type == e1000_82575)
2235                 newitr |= newitr << 16;
2236         else
2237                 newitr |= E1000_EITR_CNT_IGNR;
2238
2239         for (int i = 0; i < adapter->rx_num_queues; i++) {
2240                 rx_que = &adapter->rx_queues[i];
2241                 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2242         }
2243
2244         return;
2245 }
2246
2247 static void
2248 em_free_pci_resources(if_ctx_t ctx)
2249 {
2250         struct adapter *adapter = iflib_get_softc(ctx);
2251         struct em_rx_queue *que = adapter->rx_queues;
2252         device_t dev = iflib_get_dev(ctx);
2253
2254         /* Release all MSI-X queue resources */
2255         if (adapter->intr_type == IFLIB_INTR_MSIX)
2256                 iflib_irq_free(ctx, &adapter->irq);
2257
2258         if (que != NULL) {
2259                 for (int i = 0; i < adapter->rx_num_queues; i++, que++) {
2260                         iflib_irq_free(ctx, &que->que_irq);
2261                 }
2262         }
2263
2264         if (adapter->memory != NULL) {
2265                 bus_release_resource(dev, SYS_RES_MEMORY,
2266                     rman_get_rid(adapter->memory), adapter->memory);
2267                 adapter->memory = NULL;
2268         }
2269
2270         if (adapter->flash != NULL) {
2271                 bus_release_resource(dev, SYS_RES_MEMORY,
2272                     rman_get_rid(adapter->flash), adapter->flash);
2273                 adapter->flash = NULL;
2274         }
2275
2276         if (adapter->ioport != NULL) {
2277                 bus_release_resource(dev, SYS_RES_IOPORT,
2278                     rman_get_rid(adapter->ioport), adapter->ioport);
2279                 adapter->ioport = NULL;
2280         }
2281 }
2282
2283 /* Set up MSI or MSI-X */
2284 static int
2285 em_setup_msix(if_ctx_t ctx)
2286 {
2287         struct adapter *adapter = iflib_get_softc(ctx);
2288
2289         if (adapter->hw.mac.type == e1000_82574) {
2290                 em_enable_vectors_82574(ctx);
2291         }
2292         return (0);
2293 }
2294
2295 /*********************************************************************
2296  *
2297  *  Workaround for SmartSpeed on 82541 and 82547 controllers
2298  *
2299  **********************************************************************/
2300 static void
2301 lem_smartspeed(struct adapter *adapter)
2302 {
2303         u16 phy_tmp;
2304
2305         if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) ||
2306             adapter->hw.mac.autoneg == 0 ||
2307             (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2308                 return;
2309
2310         if (adapter->smartspeed == 0) {
2311                 /* If Master/Slave config fault is asserted twice,
2312                  * we assume back-to-back */
2313                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2314                 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2315                         return;
2316                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2317                 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2318                         e1000_read_phy_reg(&adapter->hw,
2319                             PHY_1000T_CTRL, &phy_tmp);
2320                         if(phy_tmp & CR_1000T_MS_ENABLE) {
2321                                 phy_tmp &= ~CR_1000T_MS_ENABLE;
2322                                 e1000_write_phy_reg(&adapter->hw,
2323                                     PHY_1000T_CTRL, phy_tmp);
2324                                 adapter->smartspeed++;
2325                                 if(adapter->hw.mac.autoneg &&
2326                                    !e1000_copper_link_autoneg(&adapter->hw) &&
2327                                    !e1000_read_phy_reg(&adapter->hw,
2328                                     PHY_CONTROL, &phy_tmp)) {
2329                                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2330                                                     MII_CR_RESTART_AUTO_NEG);
2331                                         e1000_write_phy_reg(&adapter->hw,
2332                                             PHY_CONTROL, phy_tmp);
2333                                 }
2334                         }
2335                 }
2336                 return;
2337         } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2338                 /* If still no link, perhaps using 2/3 pair cable */
2339                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2340                 phy_tmp |= CR_1000T_MS_ENABLE;
2341                 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2342                 if(adapter->hw.mac.autoneg &&
2343                    !e1000_copper_link_autoneg(&adapter->hw) &&
2344                    !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2345                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2346                                     MII_CR_RESTART_AUTO_NEG);
2347                         e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2348                 }
2349         }
2350         /* Restart process after EM_SMARTSPEED_MAX iterations */
2351         if(adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2352                 adapter->smartspeed = 0;
2353 }
2354
2355 /*********************************************************************
2356  *
2357  *  Initialize the DMA Coalescing feature
2358  *
2359  **********************************************************************/
2360 static void
2361 igb_init_dmac(struct adapter *adapter, u32 pba)
2362 {
2363         device_t        dev = adapter->dev;
2364         struct e1000_hw *hw = &adapter->hw;
2365         u32             dmac, reg = ~E1000_DMACR_DMAC_EN;
2366         u16             hwm;
2367         u16             max_frame_size;
2368
2369         if (hw->mac.type == e1000_i211)
2370                 return;
2371
2372         max_frame_size = adapter->shared->isc_max_frame_size;
2373         if (hw->mac.type > e1000_82580) {
2374
2375                 if (adapter->dmac == 0) { /* Disabling it */
2376                         E1000_WRITE_REG(hw, E1000_DMACR, reg);
2377                         return;
2378                 } else
2379                         device_printf(dev, "DMA Coalescing enabled\n");
2380
2381                 /* Set starting threshold */
2382                 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
2383
2384                 hwm = 64 * pba - max_frame_size / 16;
2385                 if (hwm < 64 * (pba - 6))
2386                         hwm = 64 * (pba - 6);
2387                 reg = E1000_READ_REG(hw, E1000_FCRTC);
2388                 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
2389                 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
2390                     & E1000_FCRTC_RTH_COAL_MASK);
2391                 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
2392
2393
2394                 dmac = pba - max_frame_size / 512;
2395                 if (dmac < pba - 10)
2396                         dmac = pba - 10;
2397                 reg = E1000_READ_REG(hw, E1000_DMACR);
2398                 reg &= ~E1000_DMACR_DMACTHR_MASK;
2399                 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT)
2400                     & E1000_DMACR_DMACTHR_MASK);
2401
2402                 /* transition to L0x or L1 if available..*/
2403                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
2404
2405                 /* Check if status is 2.5Gb backplane connection
2406                 * before configuration of watchdog timer, which is
2407                 * in msec values in 12.8usec intervals
2408                 * watchdog timer= msec values in 32usec intervals
2409                 * for non 2.5Gb connection
2410                 */
2411                 if (hw->mac.type == e1000_i354) {
2412                         int status = E1000_READ_REG(hw, E1000_STATUS);
2413                         if ((status & E1000_STATUS_2P5_SKU) &&
2414                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2415                                 reg |= ((adapter->dmac * 5) >> 6);
2416                         else
2417                                 reg |= (adapter->dmac >> 5);
2418                 } else {
2419                         reg |= (adapter->dmac >> 5);
2420                 }
2421
2422                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2423
2424                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
2425
2426                 /* Set the interval before transition */
2427                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
2428                 if (hw->mac.type == e1000_i350)
2429                         reg |= IGB_DMCTLX_DCFLUSH_DIS;
2430                 /*
2431                 ** in 2.5Gb connection, TTLX unit is 0.4 usec
2432                 ** which is 0x4*2 = 0xA. But delay is still 4 usec
2433                 */
2434                 if (hw->mac.type == e1000_i354) {
2435                         int status = E1000_READ_REG(hw, E1000_STATUS);
2436                         if ((status & E1000_STATUS_2P5_SKU) &&
2437                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2438                                 reg |= 0xA;
2439                         else
2440                                 reg |= 0x4;
2441                 } else {
2442                         reg |= 0x4;
2443                 }
2444
2445                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
2446
2447                 /* free space in tx packet buffer to wake from DMA coal */
2448                 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE -
2449                     (2 * max_frame_size)) >> 6);
2450
2451                 /* make low power state decision controlled by DMA coal */
2452                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2453                 reg &= ~E1000_PCIEMISC_LX_DECISION;
2454                 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
2455
2456         } else if (hw->mac.type == e1000_82580) {
2457                 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2458                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
2459                     reg & ~E1000_PCIEMISC_LX_DECISION);
2460                 E1000_WRITE_REG(hw, E1000_DMACR, 0);
2461         }
2462 }
2463
2464 /*********************************************************************
2465  *
2466  *  Initialize the hardware to a configuration as specified by the
2467  *  adapter structure.
2468  *
2469  **********************************************************************/
2470 static void
2471 em_reset(if_ctx_t ctx)
2472 {
2473         device_t dev = iflib_get_dev(ctx);
2474         struct adapter *adapter = iflib_get_softc(ctx);
2475         struct ifnet *ifp = iflib_get_ifp(ctx);
2476         struct e1000_hw *hw = &adapter->hw;
2477         u16 rx_buffer_size;
2478         u32 pba;
2479
2480         INIT_DEBUGOUT("em_reset: begin");
2481         /* Let the firmware know the OS is in control */
2482         em_get_hw_control(adapter);
2483
2484         /* Set up smart power down as default off on newer adapters. */
2485         if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2486             hw->mac.type == e1000_82572)) {
2487                 u16 phy_tmp = 0;
2488
2489                 /* Speed up time to link by disabling smart power down. */
2490                 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2491                 phy_tmp &= ~IGP02E1000_PM_SPD;
2492                 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2493         }
2494
2495         /*
2496          * Packet Buffer Allocation (PBA)
2497          * Writing PBA sets the receive portion of the buffer
2498          * the remainder is used for the transmit buffer.
2499          */
2500         switch (hw->mac.type) {
2501         /* 82547: Total Packet Buffer is 40K */
2502         case e1000_82547:
2503         case e1000_82547_rev_2:
2504                 if (hw->mac.max_frame_size > 8192)
2505                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
2506                 else
2507                         pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
2508                 break;
2509         /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */
2510         case e1000_82571:
2511         case e1000_82572:
2512         case e1000_80003es2lan:
2513                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2514                 break;
2515         /* 82573: Total Packet Buffer is 32K */
2516         case e1000_82573:
2517                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2518                 break;
2519         case e1000_82574:
2520         case e1000_82583:
2521                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2522                 break;
2523         case e1000_ich8lan:
2524                 pba = E1000_PBA_8K;
2525                 break;
2526         case e1000_ich9lan:
2527         case e1000_ich10lan:
2528                 /* Boost Receive side for jumbo frames */
2529                 if (hw->mac.max_frame_size > 4096)
2530                         pba = E1000_PBA_14K;
2531                 else
2532                         pba = E1000_PBA_10K;
2533                 break;
2534         case e1000_pchlan:
2535         case e1000_pch2lan:
2536         case e1000_pch_lpt:
2537         case e1000_pch_spt:
2538         case e1000_pch_cnp:
2539         case e1000_pch_tgp:
2540         case e1000_pch_adp:
2541         case e1000_pch_mtp:
2542                 pba = E1000_PBA_26K;
2543                 break;
2544         case e1000_82575:
2545                 pba = E1000_PBA_32K;
2546                 break;
2547         case e1000_82576:
2548         case e1000_vfadapt:
2549                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2550                 pba &= E1000_RXPBS_SIZE_MASK_82576;
2551                 break;
2552         case e1000_82580:
2553         case e1000_i350:
2554         case e1000_i354:
2555         case e1000_vfadapt_i350:
2556                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2557                 pba = e1000_rxpbs_adjust_82580(pba);
2558                 break;
2559         case e1000_i210:
2560         case e1000_i211:
2561                 pba = E1000_PBA_34K;
2562                 break;
2563         default:
2564                 /* Remaining devices assumed to have a Packet Buffer of 64K. */
2565                 if (hw->mac.max_frame_size > 8192)
2566                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2567                 else
2568                         pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2569         }
2570
2571         /* Special needs in case of Jumbo frames */
2572         if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) {
2573                 u32 tx_space, min_tx, min_rx;
2574                 pba = E1000_READ_REG(hw, E1000_PBA);
2575                 tx_space = pba >> 16;
2576                 pba &= 0xffff;
2577                 min_tx = (hw->mac.max_frame_size +
2578                     sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
2579                 min_tx = roundup2(min_tx, 1024);
2580                 min_tx >>= 10;
2581                 min_rx = hw->mac.max_frame_size;
2582                 min_rx = roundup2(min_rx, 1024);
2583                 min_rx >>= 10;
2584                 if (tx_space < min_tx &&
2585                     ((min_tx - tx_space) < pba)) {
2586                         pba = pba - (min_tx - tx_space);
2587                         /*
2588                          * if short on rx space, rx wins
2589                          * and must trump tx adjustment
2590                          */
2591                         if (pba < min_rx)
2592                                 pba = min_rx;
2593                 }
2594                 E1000_WRITE_REG(hw, E1000_PBA, pba);
2595         }
2596
2597         if (hw->mac.type < igb_mac_min)
2598                 E1000_WRITE_REG(hw, E1000_PBA, pba);
2599
2600         INIT_DEBUGOUT1("em_reset: pba=%dK",pba);
2601
2602         /*
2603          * These parameters control the automatic generation (Tx) and
2604          * response (Rx) to Ethernet PAUSE frames.
2605          * - High water mark should allow for at least two frames to be
2606          *   received after sending an XOFF.
2607          * - Low water mark works best when it is very near the high water mark.
2608          *   This allows the receiver to restart by sending XON when it has
2609          *   drained a bit. Here we use an arbitrary value of 1500 which will
2610          *   restart after one full frame is pulled from the buffer. There
2611          *   could be several smaller frames in the buffer and if so they will
2612          *   not trigger the XON until their total number reduces the buffer
2613          *   by 1500.
2614          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2615          */
2616         rx_buffer_size = (pba & 0xffff) << 10;
2617         hw->fc.high_water = rx_buffer_size -
2618             roundup2(hw->mac.max_frame_size, 1024);
2619         hw->fc.low_water = hw->fc.high_water - 1500;
2620
2621         if (adapter->fc) /* locally set flow control value? */
2622                 hw->fc.requested_mode = adapter->fc;
2623         else
2624                 hw->fc.requested_mode = e1000_fc_full;
2625
2626         if (hw->mac.type == e1000_80003es2lan)
2627                 hw->fc.pause_time = 0xFFFF;
2628         else
2629                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
2630
2631         hw->fc.send_xon = TRUE;
2632
2633         /* Device specific overrides/settings */
2634         switch (hw->mac.type) {
2635         case e1000_pchlan:
2636                 /* Workaround: no TX flow ctrl for PCH */
2637                 hw->fc.requested_mode = e1000_fc_rx_pause;
2638                 hw->fc.pause_time = 0xFFFF; /* override */
2639                 if (if_getmtu(ifp) > ETHERMTU) {
2640                         hw->fc.high_water = 0x3500;
2641                         hw->fc.low_water = 0x1500;
2642                 } else {
2643                         hw->fc.high_water = 0x5000;
2644                         hw->fc.low_water = 0x3000;
2645                 }
2646                 hw->fc.refresh_time = 0x1000;
2647                 break;
2648         case e1000_pch2lan:
2649         case e1000_pch_lpt:
2650         case e1000_pch_spt:
2651         case e1000_pch_cnp:
2652         case e1000_pch_tgp:
2653         case e1000_pch_adp:
2654         case e1000_pch_mtp:
2655                 hw->fc.high_water = 0x5C20;
2656                 hw->fc.low_water = 0x5048;
2657                 hw->fc.pause_time = 0x0650;
2658                 hw->fc.refresh_time = 0x0400;
2659                 /* Jumbos need adjusted PBA */
2660                 if (if_getmtu(ifp) > ETHERMTU)
2661                         E1000_WRITE_REG(hw, E1000_PBA, 12);
2662                 else
2663                         E1000_WRITE_REG(hw, E1000_PBA, 26);
2664                 break;
2665         case e1000_82575:
2666         case e1000_82576:
2667                 /* 8-byte granularity */
2668                 hw->fc.low_water = hw->fc.high_water - 8;
2669                 break;
2670         case e1000_82580:
2671         case e1000_i350:
2672         case e1000_i354:
2673         case e1000_i210:
2674         case e1000_i211:
2675         case e1000_vfadapt:
2676         case e1000_vfadapt_i350:
2677                 /* 16-byte granularity */
2678                 hw->fc.low_water = hw->fc.high_water - 16;
2679                 break;
2680         case e1000_ich9lan:
2681         case e1000_ich10lan:
2682                 if (if_getmtu(ifp) > ETHERMTU) {
2683                         hw->fc.high_water = 0x2800;
2684                         hw->fc.low_water = hw->fc.high_water - 8;
2685                         break;
2686                 }
2687                 /* FALLTHROUGH */
2688         default:
2689                 if (hw->mac.type == e1000_80003es2lan)
2690                         hw->fc.pause_time = 0xFFFF;
2691                 break;
2692         }
2693
2694         /* Issue a global reset */
2695         e1000_reset_hw(hw);
2696         if (hw->mac.type >= igb_mac_min) {
2697                 E1000_WRITE_REG(hw, E1000_WUC, 0);
2698         } else {
2699                 E1000_WRITE_REG(hw, E1000_WUFC, 0);
2700                 em_disable_aspm(adapter);
2701         }
2702         if (adapter->flags & IGB_MEDIA_RESET) {
2703                 e1000_setup_init_funcs(hw, TRUE);
2704                 e1000_get_bus_info(hw);
2705                 adapter->flags &= ~IGB_MEDIA_RESET;
2706         }
2707         /* and a re-init */
2708         if (e1000_init_hw(hw) < 0) {
2709                 device_printf(dev, "Hardware Initialization Failed\n");
2710                 return;
2711         }
2712         if (hw->mac.type >= igb_mac_min)
2713                 igb_init_dmac(adapter, pba);
2714
2715         E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2716         e1000_get_phy_info(hw);
2717         e1000_check_for_link(hw);
2718 }
2719
2720 /*
2721  * Initialise the RSS mapping for NICs that support multiple transmit/
2722  * receive rings.
2723  */
2724
2725 #define RSSKEYLEN 10
2726 static void
2727 em_initialize_rss_mapping(struct adapter *adapter)
2728 {
2729         uint8_t  rss_key[4 * RSSKEYLEN];
2730         uint32_t reta = 0;
2731         struct e1000_hw *hw = &adapter->hw;
2732         int i;
2733
2734         /*
2735          * Configure RSS key
2736          */
2737         arc4rand(rss_key, sizeof(rss_key), 0);
2738         for (i = 0; i < RSSKEYLEN; ++i) {
2739                 uint32_t rssrk = 0;
2740
2741                 rssrk = EM_RSSRK_VAL(rss_key, i);
2742                 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2743         }
2744
2745         /*
2746          * Configure RSS redirect table in following fashion:
2747          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2748          */
2749         for (i = 0; i < sizeof(reta); ++i) {
2750                 uint32_t q;
2751
2752                 q = (i % adapter->rx_num_queues) << 7;
2753                 reta |= q << (8 * i);
2754         }
2755
2756         for (i = 0; i < 32; ++i)
2757                 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2758
2759         E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2760                         E1000_MRQC_RSS_FIELD_IPV4_TCP |
2761                         E1000_MRQC_RSS_FIELD_IPV4 |
2762                         E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2763                         E1000_MRQC_RSS_FIELD_IPV6_EX |
2764                         E1000_MRQC_RSS_FIELD_IPV6);
2765 }
2766
2767 static void
2768 igb_initialize_rss_mapping(struct adapter *adapter)
2769 {
2770         struct e1000_hw *hw = &adapter->hw;
2771         int i;
2772         int queue_id;
2773         u32 reta;
2774         u32 rss_key[10], mrqc, shift = 0;
2775
2776         /* XXX? */
2777         if (hw->mac.type == e1000_82575)
2778                 shift = 6;
2779
2780         /*
2781          * The redirection table controls which destination
2782          * queue each bucket redirects traffic to.
2783          * Each DWORD represents four queues, with the LSB
2784          * being the first queue in the DWORD.
2785          *
2786          * This just allocates buckets to queues using round-robin
2787          * allocation.
2788          *
2789          * NOTE: It Just Happens to line up with the default
2790          * RSS allocation method.
2791          */
2792
2793         /* Warning FM follows */
2794         reta = 0;
2795         for (i = 0; i < 128; i++) {
2796 #ifdef RSS
2797                 queue_id = rss_get_indirection_to_bucket(i);
2798                 /*
2799                  * If we have more queues than buckets, we'll
2800                  * end up mapping buckets to a subset of the
2801                  * queues.
2802                  *
2803                  * If we have more buckets than queues, we'll
2804                  * end up instead assigning multiple buckets
2805                  * to queues.
2806                  *
2807                  * Both are suboptimal, but we need to handle
2808                  * the case so we don't go out of bounds
2809                  * indexing arrays and such.
2810                  */
2811                 queue_id = queue_id % adapter->rx_num_queues;
2812 #else
2813                 queue_id = (i % adapter->rx_num_queues);
2814 #endif
2815                 /* Adjust if required */
2816                 queue_id = queue_id << shift;
2817
2818                 /*
2819                  * The low 8 bits are for hash value (n+0);
2820                  * The next 8 bits are for hash value (n+1), etc.
2821                  */
2822                 reta = reta >> 8;
2823                 reta = reta | ( ((uint32_t) queue_id) << 24);
2824                 if ((i & 3) == 3) {
2825                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2826                         reta = 0;
2827                 }
2828         }
2829
2830         /* Now fill in hash table */
2831
2832         /*
2833          * MRQC: Multiple Receive Queues Command
2834          * Set queuing to RSS control, number depends on the device.
2835          */
2836         mrqc = E1000_MRQC_ENABLE_RSS_MQ;
2837
2838 #ifdef RSS
2839         /* XXX ew typecasting */
2840         rss_getkey((uint8_t *) &rss_key);
2841 #else
2842         arc4rand(&rss_key, sizeof(rss_key), 0);
2843 #endif
2844         for (i = 0; i < 10; i++)
2845                 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]);
2846
2847         /*
2848          * Configure the RSS fields to hash upon.
2849          */
2850         mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2851             E1000_MRQC_RSS_FIELD_IPV4_TCP);
2852         mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2853             E1000_MRQC_RSS_FIELD_IPV6_TCP);
2854         mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2855             E1000_MRQC_RSS_FIELD_IPV6_UDP);
2856         mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2857             E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2858
2859         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2860 }
2861
2862 /*********************************************************************
2863  *
2864  *  Setup networking device structure and register interface media.
2865  *
2866  **********************************************************************/
2867 static int
2868 em_setup_interface(if_ctx_t ctx)
2869 {
2870         struct ifnet *ifp = iflib_get_ifp(ctx);
2871         struct adapter *adapter = iflib_get_softc(ctx);
2872         if_softc_ctx_t scctx = adapter->shared;
2873
2874         INIT_DEBUGOUT("em_setup_interface: begin");
2875
2876         /* Single Queue */
2877         if (adapter->tx_num_queues == 1) {
2878                 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
2879                 if_setsendqready(ifp);
2880         }
2881
2882         /*
2883          * Specify the media types supported by this adapter and register
2884          * callbacks to update media and link information
2885          */
2886         if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2887             adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
2888                 u_char fiber_type = IFM_1000_SX;        /* default type */
2889
2890                 if (adapter->hw.mac.type == e1000_82545)
2891                         fiber_type = IFM_1000_LX;
2892                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
2893                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2894         } else {
2895                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2896                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2897                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2898                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2899                 if (adapter->hw.phy.type != e1000_phy_ife) {
2900                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2901                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2902                 }
2903         }
2904         ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2905         ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO);
2906         return (0);
2907 }
2908
2909 static int
2910 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
2911 {
2912         struct adapter *adapter = iflib_get_softc(ctx);
2913         if_softc_ctx_t scctx = adapter->shared;
2914         int error = E1000_SUCCESS;
2915         struct em_tx_queue *que;
2916         int i, j;
2917
2918         MPASS(adapter->tx_num_queues > 0);
2919         MPASS(adapter->tx_num_queues == ntxqsets);
2920
2921         /* First allocate the top level queue structs */
2922         if (!(adapter->tx_queues =
2923             (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
2924             adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2925                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2926                 return(ENOMEM);
2927         }
2928
2929         for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) {
2930                 /* Set up some basics */
2931
2932                 struct tx_ring *txr = &que->txr;
2933                 txr->adapter = que->adapter = adapter;
2934                 que->me = txr->me =  i;
2935
2936                 /* Allocate report status array */
2937                 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2938                         device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n");
2939                         error = ENOMEM;
2940                         goto fail;
2941                 }
2942                 for (j = 0; j < scctx->isc_ntxd[0]; j++)
2943                         txr->tx_rsq[j] = QIDX_INVALID;
2944                 /* get the virtual and physical address of the hardware queues */
2945                 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
2946                 txr->tx_paddr = paddrs[i*ntxqs];
2947         }
2948
2949         if (bootverbose)
2950                 device_printf(iflib_get_dev(ctx),
2951                     "allocated for %d tx_queues\n", adapter->tx_num_queues);
2952         return (0);
2953 fail:
2954         em_if_queues_free(ctx);
2955         return (error);
2956 }
2957
2958 static int
2959 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
2960 {
2961         struct adapter *adapter = iflib_get_softc(ctx);
2962         int error = E1000_SUCCESS;
2963         struct em_rx_queue *que;
2964         int i;
2965
2966         MPASS(adapter->rx_num_queues > 0);
2967         MPASS(adapter->rx_num_queues == nrxqsets);
2968
2969         /* First allocate the top level queue structs */
2970         if (!(adapter->rx_queues =
2971             (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
2972             adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2973                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2974                 error = ENOMEM;
2975                 goto fail;
2976         }
2977
2978         for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) {
2979                 /* Set up some basics */
2980                 struct rx_ring *rxr = &que->rxr;
2981                 rxr->adapter = que->adapter = adapter;
2982                 rxr->que = que;
2983                 que->me = rxr->me =  i;
2984
2985                 /* get the virtual and physical address of the hardware queues */
2986                 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
2987                 rxr->rx_paddr = paddrs[i*nrxqs];
2988         }
2989
2990         if (bootverbose)
2991                 device_printf(iflib_get_dev(ctx),
2992                     "allocated for %d rx_queues\n", adapter->rx_num_queues);
2993
2994         return (0);
2995 fail:
2996         em_if_queues_free(ctx);
2997         return (error);
2998 }
2999
3000 static void
3001 em_if_queues_free(if_ctx_t ctx)
3002 {
3003         struct adapter *adapter = iflib_get_softc(ctx);
3004         struct em_tx_queue *tx_que = adapter->tx_queues;
3005         struct em_rx_queue *rx_que = adapter->rx_queues;
3006
3007         if (tx_que != NULL) {
3008                 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
3009                         struct tx_ring *txr = &tx_que->txr;
3010                         if (txr->tx_rsq == NULL)
3011                                 break;
3012
3013                         free(txr->tx_rsq, M_DEVBUF);
3014                         txr->tx_rsq = NULL;
3015                 }
3016                 free(adapter->tx_queues, M_DEVBUF);
3017                 adapter->tx_queues = NULL;
3018         }
3019
3020         if (rx_que != NULL) {
3021                 free(adapter->rx_queues, M_DEVBUF);
3022                 adapter->rx_queues = NULL;
3023         }
3024 }
3025
3026 /*********************************************************************
3027  *
3028  *  Enable transmit unit.
3029  *
3030  **********************************************************************/
3031 static void
3032 em_initialize_transmit_unit(if_ctx_t ctx)
3033 {
3034         struct adapter *adapter = iflib_get_softc(ctx);
3035         if_softc_ctx_t scctx = adapter->shared;
3036         struct em_tx_queue *que;
3037         struct tx_ring  *txr;
3038         struct e1000_hw *hw = &adapter->hw;
3039         u32 tctl, txdctl = 0, tarc, tipg = 0;
3040
3041         INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
3042
3043         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
3044                 u64 bus_addr;
3045                 caddr_t offp, endp;
3046
3047                 que = &adapter->tx_queues[i];
3048                 txr = &que->txr;
3049                 bus_addr = txr->tx_paddr;
3050
3051                 /* Clear checksum offload context. */
3052                 offp = (caddr_t)&txr->csum_flags;
3053                 endp = (caddr_t)(txr + 1);
3054                 bzero(offp, endp - offp);
3055
3056                 /* Base and Len of TX Ring */
3057                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
3058                     scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
3059                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
3060                     (u32)(bus_addr >> 32));
3061                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
3062                     (u32)bus_addr);
3063                 /* Init the HEAD/TAIL indices */
3064                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
3065                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
3066
3067                 HW_DEBUGOUT2("Base = %x, Length = %x\n",
3068                     E1000_READ_REG(hw, E1000_TDBAL(i)),
3069                     E1000_READ_REG(hw, E1000_TDLEN(i)));
3070
3071                 txdctl = 0; /* clear txdctl */
3072                 txdctl |= 0x1f; /* PTHRESH */
3073                 txdctl |= 1 << 8; /* HTHRESH */
3074                 txdctl |= 1 << 16;/* WTHRESH */
3075                 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
3076                 txdctl |= E1000_TXDCTL_GRAN;
3077                 txdctl |= 1 << 25; /* LWTHRESH */
3078
3079                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
3080         }
3081
3082         /* Set the default values for the Tx Inter Packet Gap timer */
3083         switch (hw->mac.type) {
3084         case e1000_80003es2lan:
3085                 tipg = DEFAULT_82543_TIPG_IPGR1;
3086                 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
3087                     E1000_TIPG_IPGR2_SHIFT;
3088                 break;
3089         case e1000_82542:
3090                 tipg = DEFAULT_82542_TIPG_IPGT;
3091                 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3092                 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3093                 break;
3094         default:
3095                 if (hw->phy.media_type == e1000_media_type_fiber ||
3096                     hw->phy.media_type == e1000_media_type_internal_serdes)
3097                         tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
3098                 else
3099                         tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
3100                 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3101                 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3102         }
3103
3104         E1000_WRITE_REG(hw, E1000_TIPG, tipg);
3105         E1000_WRITE_REG(hw, E1000_TIDV, adapter->tx_int_delay.value);
3106
3107         if(hw->mac.type >= e1000_82540)
3108                 E1000_WRITE_REG(hw, E1000_TADV,
3109                     adapter->tx_abs_int_delay.value);
3110
3111         if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) {
3112                 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3113                 tarc |= TARC_SPEED_MODE_BIT;
3114                 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3115         } else if (hw->mac.type == e1000_80003es2lan) {
3116                 /* errata: program both queues to unweighted RR */
3117                 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3118                 tarc |= 1;
3119                 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3120                 tarc = E1000_READ_REG(hw, E1000_TARC(1));
3121                 tarc |= 1;
3122                 E1000_WRITE_REG(hw, E1000_TARC(1), tarc);
3123         } else if (hw->mac.type == e1000_82574) {
3124                 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3125                 tarc |= TARC_ERRATA_BIT;
3126                 if ( adapter->tx_num_queues > 1) {
3127                         tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
3128                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3129                         E1000_WRITE_REG(hw, E1000_TARC(1), tarc);
3130                 } else
3131                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3132         }
3133
3134         if (adapter->tx_int_delay.value > 0)
3135                 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3136
3137         /* Program the Transmit Control Register */
3138         tctl = E1000_READ_REG(hw, E1000_TCTL);
3139         tctl &= ~E1000_TCTL_CT;
3140         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
3141                    (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
3142
3143         if (hw->mac.type >= e1000_82571)
3144                 tctl |= E1000_TCTL_MULR;
3145
3146         /* This write will effectively turn on the transmit unit. */
3147         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
3148
3149         /* SPT and KBL errata workarounds */
3150         if (hw->mac.type == e1000_pch_spt) {
3151                 u32 reg;
3152                 reg = E1000_READ_REG(hw, E1000_IOSFPC);
3153                 reg |= E1000_RCTL_RDMTS_HEX;
3154                 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
3155                 /* i218-i219 Specification Update 1.5.4.5 */
3156                 reg = E1000_READ_REG(hw, E1000_TARC(0));
3157                 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3158                 reg |= E1000_TARC0_CB_MULTIQ_2_REQ;
3159                 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3160         }
3161 }
3162
3163 /*********************************************************************
3164  *
3165  *  Enable receive unit.
3166  *
3167  **********************************************************************/
3168 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1)
3169
3170 static void
3171 em_initialize_receive_unit(if_ctx_t ctx)
3172 {
3173         struct adapter *adapter = iflib_get_softc(ctx);
3174         if_softc_ctx_t scctx = adapter->shared;
3175         struct ifnet *ifp = iflib_get_ifp(ctx);
3176         struct e1000_hw *hw = &adapter->hw;
3177         struct em_rx_queue *que;
3178         int i;
3179         uint32_t rctl, rxcsum;
3180
3181         INIT_DEBUGOUT("em_initialize_receive_units: begin");
3182
3183         /*
3184          * Make sure receives are disabled while setting
3185          * up the descriptor ring
3186          */
3187         rctl = E1000_READ_REG(hw, E1000_RCTL);
3188         /* Do not disable if ever enabled on this hardware */
3189         if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
3190                 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3191
3192         /* Setup the Receive Control Register */
3193         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3194         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3195             E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3196             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3197
3198         /* Do not store bad packets */
3199         rctl &= ~E1000_RCTL_SBP;
3200
3201         /* Enable Long Packet receive */
3202         if (if_getmtu(ifp) > ETHERMTU)
3203                 rctl |= E1000_RCTL_LPE;
3204         else
3205                 rctl &= ~E1000_RCTL_LPE;
3206
3207         /* Strip the CRC */
3208         if (!em_disable_crc_stripping)
3209                 rctl |= E1000_RCTL_SECRC;
3210
3211         if (hw->mac.type >= e1000_82540) {
3212                 E1000_WRITE_REG(hw, E1000_RADV,
3213                     adapter->rx_abs_int_delay.value);
3214
3215                 /*
3216                  * Set the interrupt throttling rate. Value is calculated
3217                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
3218                  */
3219                 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
3220         }
3221         E1000_WRITE_REG(hw, E1000_RDTR, adapter->rx_int_delay.value);
3222
3223         if (hw->mac.type >= em_mac_min) {
3224                 uint32_t rfctl;
3225                 /* Use extended rx descriptor formats */
3226                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3227                 rfctl |= E1000_RFCTL_EXTEN;
3228
3229                 /*
3230                  * When using MSI-X interrupts we need to throttle
3231                  * using the EITR register (82574 only)
3232                  */
3233                 if (hw->mac.type == e1000_82574) {
3234                         for (int i = 0; i < 4; i++)
3235                                 E1000_WRITE_REG(hw, E1000_EITR_82574(i),
3236                                     DEFAULT_ITR);
3237                         /* Disable accelerated acknowledge */
3238                         rfctl |= E1000_RFCTL_ACK_DIS;
3239                 }
3240                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3241         }
3242
3243         /* Set up L3 and L4 csum Rx descriptor offloads */
3244         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
3245         if (scctx->isc_capenable & IFCAP_RXCSUM) {
3246                 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
3247                 if (hw->mac.type > e1000_82575)
3248                         rxcsum |= E1000_RXCSUM_CRCOFL;
3249                 else if (hw->mac.type < em_mac_min &&
3250                     scctx->isc_capenable & IFCAP_HWCSUM_IPV6)
3251                         rxcsum |= E1000_RXCSUM_IPV6OFL;
3252         } else {
3253                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
3254                 if (hw->mac.type > e1000_82575)
3255                         rxcsum &= ~E1000_RXCSUM_CRCOFL;
3256                 else if (hw->mac.type < em_mac_min)
3257                         rxcsum &= ~E1000_RXCSUM_IPV6OFL;
3258         }
3259
3260         if (adapter->rx_num_queues > 1) {
3261                 /* RSS hash needed in the Rx descriptor */
3262                 rxcsum |= E1000_RXCSUM_PCSD;
3263
3264                 if (hw->mac.type >= igb_mac_min)
3265                         igb_initialize_rss_mapping(adapter);
3266                 else
3267                         em_initialize_rss_mapping(adapter);
3268         }
3269         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
3270
3271         /*
3272          * XXX TEMPORARY WORKAROUND: on some systems with 82573
3273          * long latencies are observed, like Lenovo X60. This
3274          * change eliminates the problem, but since having positive
3275          * values in RDTR is a known source of problems on other
3276          * platforms another solution is being sought.
3277          */
3278         if (hw->mac.type == e1000_82573)
3279                 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
3280
3281         for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3282                 struct rx_ring *rxr = &que->rxr;
3283                 /* Setup the Base and Length of the Rx Descriptor Ring */
3284                 u64 bus_addr = rxr->rx_paddr;
3285 #if 0
3286                 u32 rdt = adapter->rx_num_queues -1;  /* default */
3287 #endif
3288
3289                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3290                     scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
3291                 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
3292                 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
3293                 /* Setup the Head and Tail Descriptor Pointers */
3294                 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
3295                 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
3296         }
3297
3298         /*
3299          * Set PTHRESH for improved jumbo performance
3300          * According to 10.2.5.11 of Intel 82574 Datasheet,
3301          * RXDCTL(1) is written whenever RXDCTL(0) is written.
3302          * Only write to RXDCTL(1) if there is a need for different
3303          * settings.
3304          */
3305         if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan ||
3306             hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) {
3307                 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
3308                 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
3309         } else if (hw->mac.type == e1000_82574) {
3310                 for (int i = 0; i < adapter->rx_num_queues; i++) {
3311                         u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3312                         rxdctl |= 0x20; /* PTHRESH */
3313                         rxdctl |= 4 << 8; /* HTHRESH */
3314                         rxdctl |= 4 << 16;/* WTHRESH */
3315                         rxdctl |= 1 << 24; /* Switch to granularity */
3316                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3317                 }
3318         } else if (hw->mac.type >= igb_mac_min) {
3319                 u32 psize, srrctl = 0;
3320
3321                 if (if_getmtu(ifp) > ETHERMTU) {
3322                         psize = scctx->isc_max_frame_size;
3323                         /* are we on a vlan? */
3324                         if (ifp->if_vlantrunk != NULL)
3325                                 psize += VLAN_TAG_SIZE;
3326
3327                         if (adapter->vf_ifp)
3328                                 e1000_rlpml_set_vf(hw, psize);
3329                         else
3330                                 E1000_WRITE_REG(hw, E1000_RLPML, psize);
3331                 }
3332
3333                 /* Set maximum packet buffer len */
3334                 srrctl |= (adapter->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >>
3335                     E1000_SRRCTL_BSIZEPKT_SHIFT;
3336
3337                 /*
3338                  * If TX flow control is disabled and there's >1 queue defined,
3339                  * enable DROP.
3340                  *
3341                  * This drops frames rather than hanging the RX MAC for all queues.
3342                  */
3343                 if ((adapter->rx_num_queues > 1) &&
3344                     (adapter->fc == e1000_fc_none ||
3345                      adapter->fc == e1000_fc_rx_pause)) {
3346                         srrctl |= E1000_SRRCTL_DROP_EN;
3347                 }
3348                         /* Setup the Base and Length of the Rx Descriptor Rings */
3349                 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3350                         struct rx_ring *rxr = &que->rxr;
3351                         u64 bus_addr = rxr->rx_paddr;
3352                         u32 rxdctl;
3353
3354 #ifdef notyet
3355                         /* Configure for header split? -- ignore for now */
3356                         rxr->hdr_split = igb_header_split;
3357 #else
3358                         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3359 #endif
3360
3361                         E1000_WRITE_REG(hw, E1000_RDLEN(i),
3362                                         scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3363                         E1000_WRITE_REG(hw, E1000_RDBAH(i),
3364                                         (uint32_t)(bus_addr >> 32));
3365                         E1000_WRITE_REG(hw, E1000_RDBAL(i),
3366                                         (uint32_t)bus_addr);
3367                         E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3368                         /* Enable this Queue */
3369                         rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3370                         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3371                         rxdctl &= 0xFFF00000;
3372                         rxdctl |= IGB_RX_PTHRESH;
3373                         rxdctl |= IGB_RX_HTHRESH << 8;
3374                         rxdctl |= IGB_RX_WTHRESH << 16;
3375                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3376                 }
3377         } else if (hw->mac.type >= e1000_pch2lan) {
3378                 if (if_getmtu(ifp) > ETHERMTU)
3379                         e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
3380                 else
3381                         e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
3382         }
3383
3384         /* Make sure VLAN Filters are off */
3385         rctl &= ~E1000_RCTL_VFE;
3386
3387         /* Set up packet buffer size, overridden by per queue srrctl on igb */
3388         if (hw->mac.type < igb_mac_min) {
3389                 if (adapter->rx_mbuf_sz > 2048 && adapter->rx_mbuf_sz <= 4096)
3390                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3391                 else if (adapter->rx_mbuf_sz > 4096 && adapter->rx_mbuf_sz <= 8192)
3392                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3393                 else if (adapter->rx_mbuf_sz > 8192)
3394                         rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX;
3395                 else {
3396                         rctl |= E1000_RCTL_SZ_2048;
3397                         rctl &= ~E1000_RCTL_BSEX;
3398                 }
3399         } else
3400                 rctl |= E1000_RCTL_SZ_2048;
3401
3402         /*
3403          * rctl bits 11:10 are as follows
3404          * lem: reserved
3405          * em: DTYPE
3406          * igb: reserved
3407          * and should be 00 on all of the above
3408          */
3409         rctl &= ~0x00000C00;
3410
3411         /* Write out the settings */
3412         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3413
3414         return;
3415 }
3416
3417 static void
3418 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3419 {
3420         struct adapter *adapter = iflib_get_softc(ctx);
3421         u32 index, bit;
3422
3423         index = (vtag >> 5) & 0x7F;
3424         bit = vtag & 0x1F;
3425         adapter->shadow_vfta[index] |= (1 << bit);
3426         ++adapter->num_vlans;
3427         em_if_vlan_filter_write(adapter);
3428 }
3429
3430 static void
3431 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3432 {
3433         struct adapter *adapter = iflib_get_softc(ctx);
3434         u32 index, bit;
3435
3436         index = (vtag >> 5) & 0x7F;
3437         bit = vtag & 0x1F;
3438         adapter->shadow_vfta[index] &= ~(1 << bit);
3439         --adapter->num_vlans;
3440         em_if_vlan_filter_write(adapter);
3441 }
3442
3443 static bool
3444 em_if_vlan_filter_capable(struct adapter *adapter)
3445 {
3446         if_softc_ctx_t scctx = adapter->shared;
3447
3448         if ((scctx->isc_capenable & IFCAP_VLAN_HWFILTER) &&
3449             !em_disable_crc_stripping)
3450                 return (true);
3451
3452         return (false);
3453 }
3454
3455 static bool
3456 em_if_vlan_filter_used(struct adapter *adapter)
3457 {
3458         if (!em_if_vlan_filter_capable(adapter))
3459                 return (false);
3460
3461         for (int i = 0; i < EM_VFTA_SIZE; i++)
3462                 if (adapter->shadow_vfta[i] != 0)
3463                         return (true);
3464
3465         return (false);
3466 }
3467
3468 static void
3469 em_if_vlan_filter_enable(struct adapter *adapter)
3470 {
3471         struct e1000_hw *hw = &adapter->hw;
3472         u32 reg;
3473
3474         reg = E1000_READ_REG(hw, E1000_RCTL);
3475         reg &= ~E1000_RCTL_CFIEN;
3476         reg |= E1000_RCTL_VFE;
3477         E1000_WRITE_REG(hw, E1000_RCTL, reg);
3478 }
3479
3480 static void
3481 em_if_vlan_filter_disable(struct adapter *adapter)
3482 {
3483         struct e1000_hw *hw = &adapter->hw;
3484         u32 reg;
3485
3486         reg = E1000_READ_REG(hw, E1000_RCTL);
3487         reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
3488         E1000_WRITE_REG(hw, E1000_RCTL, reg);
3489 }
3490
3491 static void
3492 em_if_vlan_filter_write(struct adapter *adapter)
3493 {
3494         struct e1000_hw *hw = &adapter->hw;
3495
3496         if (adapter->vf_ifp)
3497                 return;
3498
3499         /* Disable interrupts for lem-class devices during the filter change */
3500         if (hw->mac.type < em_mac_min)
3501                 em_if_intr_disable(adapter->ctx);
3502
3503         for (int i = 0; i < EM_VFTA_SIZE; i++)
3504                 if (adapter->shadow_vfta[i] != 0) {
3505                         /* XXXKB: incomplete VF support, we return early above */
3506                         if (adapter->vf_ifp)
3507                                 e1000_vfta_set_vf(hw, adapter->shadow_vfta[i], TRUE);
3508                         else
3509                                 e1000_write_vfta(hw, i, adapter->shadow_vfta[i]);
3510                 }
3511
3512         /* Re-enable interrupts for lem-class devices */
3513         if (hw->mac.type < em_mac_min)
3514                 em_if_intr_enable(adapter->ctx);
3515 }
3516
3517 static void
3518 em_setup_vlan_hw_support(struct adapter *adapter)
3519 {
3520         if_softc_ctx_t scctx = adapter->shared;
3521         struct e1000_hw *hw = &adapter->hw;
3522         u32 reg;
3523
3524         /* XXXKB: Return early if we are a VF until VF decap and filter management
3525          * is ready and tested.
3526          */
3527         if (adapter->vf_ifp)
3528                 return;
3529
3530         if (scctx->isc_capenable & IFCAP_VLAN_HWTAGGING &&
3531             !em_disable_crc_stripping) {
3532                 reg = E1000_READ_REG(hw, E1000_CTRL);
3533                 reg |= E1000_CTRL_VME;
3534                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
3535         } else {
3536                 reg = E1000_READ_REG(hw, E1000_CTRL);
3537                 reg &= ~E1000_CTRL_VME;
3538                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
3539         }
3540
3541         /* If we aren't doing HW filtering, we're done */
3542         if (!em_if_vlan_filter_capable(adapter))  {
3543                 em_if_vlan_filter_disable(adapter);
3544                 return;
3545         }
3546
3547         /*
3548          * A soft reset zero's out the VFTA, so
3549          * we need to repopulate it now.
3550          */
3551         em_if_vlan_filter_write(adapter);
3552
3553         /* Enable the Filter Table */
3554         em_if_vlan_filter_enable(adapter);
3555 }
3556
3557 static void
3558 em_if_intr_enable(if_ctx_t ctx)
3559 {
3560         struct adapter *adapter = iflib_get_softc(ctx);
3561         struct e1000_hw *hw = &adapter->hw;
3562         u32 ims_mask = IMS_ENABLE_MASK;
3563
3564         if (adapter->intr_type == IFLIB_INTR_MSIX) {
3565                 E1000_WRITE_REG(hw, EM_EIAC, adapter->ims);
3566                 ims_mask |= adapter->ims;
3567         }
3568         E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3569         E1000_WRITE_FLUSH(hw);
3570 }
3571
3572 static void
3573 em_if_intr_disable(if_ctx_t ctx)
3574 {
3575         struct adapter *adapter = iflib_get_softc(ctx);
3576         struct e1000_hw *hw = &adapter->hw;
3577
3578         if (adapter->intr_type == IFLIB_INTR_MSIX)
3579                 E1000_WRITE_REG(hw, EM_EIAC, 0);
3580         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3581         E1000_WRITE_FLUSH(hw);
3582 }
3583
3584 static void
3585 igb_if_intr_enable(if_ctx_t ctx)
3586 {
3587         struct adapter *adapter = iflib_get_softc(ctx);
3588         struct e1000_hw *hw = &adapter->hw;
3589         u32 mask;
3590
3591         if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) {
3592                 mask = (adapter->que_mask | adapter->link_mask);
3593                 E1000_WRITE_REG(hw, E1000_EIAC, mask);
3594                 E1000_WRITE_REG(hw, E1000_EIAM, mask);
3595                 E1000_WRITE_REG(hw, E1000_EIMS, mask);
3596                 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
3597         } else
3598                 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
3599         E1000_WRITE_FLUSH(hw);
3600 }
3601
3602 static void
3603 igb_if_intr_disable(if_ctx_t ctx)
3604 {
3605         struct adapter *adapter = iflib_get_softc(ctx);
3606         struct e1000_hw *hw = &adapter->hw;
3607
3608         if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) {
3609                 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff);
3610                 E1000_WRITE_REG(hw, E1000_EIAC, 0);
3611         }
3612         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3613         E1000_WRITE_FLUSH(hw);
3614 }
3615
3616 /*
3617  * Bit of a misnomer, what this really means is
3618  * to enable OS management of the system... aka
3619  * to disable special hardware management features
3620  */
3621 static void
3622 em_init_manageability(struct adapter *adapter)
3623 {
3624         /* A shared code workaround */
3625 #define E1000_82542_MANC2H E1000_MANC2H
3626         if (adapter->has_manage) {
3627                 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3628                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3629
3630                 /* disable hardware interception of ARP */
3631                 manc &= ~(E1000_MANC_ARP_EN);
3632
3633                 /* enable receiving management packets to the host */
3634                 manc |= E1000_MANC_EN_MNG2HOST;
3635 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3636 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3637                 manc2h |= E1000_MNG2HOST_PORT_623;
3638                 manc2h |= E1000_MNG2HOST_PORT_664;
3639                 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3640                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3641         }
3642 }
3643
3644 /*
3645  * Give control back to hardware management
3646  * controller if there is one.
3647  */
3648 static void
3649 em_release_manageability(struct adapter *adapter)
3650 {
3651         if (adapter->has_manage) {
3652                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3653
3654                 /* re-enable hardware interception of ARP */
3655                 manc |= E1000_MANC_ARP_EN;
3656                 manc &= ~E1000_MANC_EN_MNG2HOST;
3657
3658                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3659         }
3660 }
3661
3662 /*
3663  * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3664  * For ASF and Pass Through versions of f/w this means
3665  * that the driver is loaded. For AMT version type f/w
3666  * this means that the network i/f is open.
3667  */
3668 static void
3669 em_get_hw_control(struct adapter *adapter)
3670 {
3671         u32 ctrl_ext, swsm;
3672
3673         if (adapter->vf_ifp)
3674                 return;
3675
3676         if (adapter->hw.mac.type == e1000_82573) {
3677                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3678                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3679                     swsm | E1000_SWSM_DRV_LOAD);
3680                 return;
3681         }
3682         /* else */
3683         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3684         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3685             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3686 }
3687
3688 /*
3689  * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3690  * For ASF and Pass Through versions of f/w this means that
3691  * the driver is no longer loaded. For AMT versions of the
3692  * f/w this means that the network i/f is closed.
3693  */
3694 static void
3695 em_release_hw_control(struct adapter *adapter)
3696 {
3697         u32 ctrl_ext, swsm;
3698
3699         if (!adapter->has_manage)
3700                 return;
3701
3702         if (adapter->hw.mac.type == e1000_82573) {
3703                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3704                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3705                     swsm & ~E1000_SWSM_DRV_LOAD);
3706                 return;
3707         }
3708         /* else */
3709         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3710         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3711             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3712         return;
3713 }
3714
3715 static int
3716 em_is_valid_ether_addr(u8 *addr)
3717 {
3718         char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3719
3720         if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3721                 return (FALSE);
3722         }
3723
3724         return (TRUE);
3725 }
3726
3727 /*
3728 ** Parse the interface capabilities with regard
3729 ** to both system management and wake-on-lan for
3730 ** later use.
3731 */
3732 static void
3733 em_get_wakeup(if_ctx_t ctx)
3734 {
3735         struct adapter *adapter = iflib_get_softc(ctx);
3736         device_t dev = iflib_get_dev(ctx);
3737         u16 eeprom_data = 0, device_id, apme_mask;
3738
3739         adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
3740         apme_mask = EM_EEPROM_APME;
3741
3742         switch (adapter->hw.mac.type) {
3743         case e1000_82542:
3744         case e1000_82543:
3745                 break;
3746         case e1000_82544:
3747                 e1000_read_nvm(&adapter->hw,
3748                     NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3749                 apme_mask = EM_82544_APME;
3750                 break;
3751         case e1000_82546:
3752         case e1000_82546_rev_3:
3753                 if (adapter->hw.bus.func == 1) {
3754                         e1000_read_nvm(&adapter->hw,
3755                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3756                         break;
3757                 } else
3758                         e1000_read_nvm(&adapter->hw,
3759                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3760                 break;
3761         case e1000_82573:
3762         case e1000_82583:
3763                 adapter->has_amt = TRUE;
3764                 /* FALLTHROUGH */
3765         case e1000_82571:
3766         case e1000_82572:
3767         case e1000_80003es2lan:
3768                 if (adapter->hw.bus.func == 1) {
3769                         e1000_read_nvm(&adapter->hw,
3770                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3771                         break;
3772                 } else
3773                         e1000_read_nvm(&adapter->hw,
3774                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3775                 break;
3776         case e1000_ich8lan:
3777         case e1000_ich9lan:
3778         case e1000_ich10lan:
3779         case e1000_pchlan:
3780         case e1000_pch2lan:
3781         case e1000_pch_lpt:
3782         case e1000_pch_spt:
3783         case e1000_82575:       /* listing all igb devices */
3784         case e1000_82576:
3785         case e1000_82580:
3786         case e1000_i350:
3787         case e1000_i354:
3788         case e1000_i210:
3789         case e1000_i211:
3790         case e1000_vfadapt:
3791         case e1000_vfadapt_i350:
3792                 apme_mask = E1000_WUC_APME;
3793                 adapter->has_amt = TRUE;
3794                 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
3795                 break;
3796         default:
3797                 e1000_read_nvm(&adapter->hw,
3798                     NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3799                 break;
3800         }
3801         if (eeprom_data & apme_mask)
3802                 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
3803         /*
3804          * We have the eeprom settings, now apply the special cases
3805          * where the eeprom may be wrong or the board won't support
3806          * wake on lan on a particular port
3807          */
3808         device_id = pci_get_device(dev);
3809         switch (device_id) {
3810         case E1000_DEV_ID_82546GB_PCIE:
3811                 adapter->wol = 0;
3812                 break;
3813         case E1000_DEV_ID_82546EB_FIBER:
3814         case E1000_DEV_ID_82546GB_FIBER:
3815                 /* Wake events only supported on port A for dual fiber
3816                  * regardless of eeprom setting */
3817                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3818                     E1000_STATUS_FUNC_1)
3819                         adapter->wol = 0;
3820                 break;
3821         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
3822                 /* if quad port adapter, disable WoL on all but port A */
3823                 if (global_quad_port_a != 0)
3824                         adapter->wol = 0;
3825                 /* Reset for multiple quad port adapters */
3826                 if (++global_quad_port_a == 4)
3827                         global_quad_port_a = 0;
3828                 break;
3829         case E1000_DEV_ID_82571EB_FIBER:
3830                 /* Wake events only supported on port A for dual fiber
3831                  * regardless of eeprom setting */
3832                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3833                     E1000_STATUS_FUNC_1)
3834                         adapter->wol = 0;
3835                 break;
3836         case E1000_DEV_ID_82571EB_QUAD_COPPER:
3837         case E1000_DEV_ID_82571EB_QUAD_FIBER:
3838         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
3839                 /* if quad port adapter, disable WoL on all but port A */
3840                 if (global_quad_port_a != 0)
3841                         adapter->wol = 0;
3842                 /* Reset for multiple quad port adapters */
3843                 if (++global_quad_port_a == 4)
3844                         global_quad_port_a = 0;
3845                 break;
3846         }
3847         return;
3848 }
3849
3850
3851 /*
3852  * Enable PCI Wake On Lan capability
3853  */
3854 static void
3855 em_enable_wakeup(if_ctx_t ctx)
3856 {
3857         struct adapter *adapter = iflib_get_softc(ctx);
3858         device_t dev = iflib_get_dev(ctx);
3859         if_t ifp = iflib_get_ifp(ctx);
3860         int error = 0;
3861         u32 pmc, ctrl, ctrl_ext, rctl;
3862         u16 status;
3863
3864         if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
3865                 return;
3866
3867         /*
3868          * Determine type of Wakeup: note that wol
3869          * is set with all bits on by default.
3870          */
3871         if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
3872                 adapter->wol &= ~E1000_WUFC_MAG;
3873
3874         if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
3875                 adapter->wol &= ~E1000_WUFC_EX;
3876
3877         if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
3878                 adapter->wol &= ~E1000_WUFC_MC;
3879         else {
3880                 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3881                 rctl |= E1000_RCTL_MPE;
3882                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3883         }
3884
3885         if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC)))
3886                 goto pme;
3887
3888         /* Advertise the wakeup capability */
3889         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
3890         ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
3891         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
3892
3893         /* Keep the laser running on Fiber adapters */
3894         if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3895             adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
3896                 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3897                 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
3898                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext);
3899         }
3900
3901         if ((adapter->hw.mac.type == e1000_ich8lan) ||
3902             (adapter->hw.mac.type == e1000_pchlan) ||
3903             (adapter->hw.mac.type == e1000_ich9lan) ||
3904             (adapter->hw.mac.type == e1000_ich10lan))
3905                 e1000_suspend_workarounds_ich8lan(&adapter->hw);
3906
3907         if ( adapter->hw.mac.type >= e1000_pchlan) {
3908                 error = em_enable_phy_wakeup(adapter);
3909                 if (error)
3910                         goto pme;
3911         } else {
3912                 /* Enable wakeup by the MAC */
3913                 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
3914                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
3915         }
3916
3917         if (adapter->hw.phy.type == e1000_phy_igp_3)
3918                 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
3919
3920 pme:
3921         status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
3922         status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3923         if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
3924                 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3925         pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
3926
3927         return;
3928 }
3929
3930 /*
3931  * WOL in the newer chipset interfaces (pchlan)
3932  * require thing to be copied into the phy
3933  */
3934 static int
3935 em_enable_phy_wakeup(struct adapter *adapter)
3936 {
3937         struct e1000_hw *hw = &adapter->hw;
3938         u32 mreg, ret = 0;
3939         u16 preg;
3940
3941         /* copy MAC RARs to PHY RARs */
3942         e1000_copy_rx_addrs_to_phy_ich8lan(hw);
3943
3944         /* copy MAC MTA to PHY MTA */
3945         for (int i = 0; i < hw->mac.mta_reg_count; i++) {
3946                 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
3947                 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
3948                 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
3949                     (u16)((mreg >> 16) & 0xFFFF));
3950         }
3951
3952         /* configure PHY Rx Control register */
3953         e1000_read_phy_reg(hw, BM_RCTL, &preg);
3954         mreg = E1000_READ_REG(hw, E1000_RCTL);
3955         if (mreg & E1000_RCTL_UPE)
3956                 preg |= BM_RCTL_UPE;
3957         if (mreg & E1000_RCTL_MPE)
3958                 preg |= BM_RCTL_MPE;
3959         preg &= ~(BM_RCTL_MO_MASK);
3960         if (mreg & E1000_RCTL_MO_3)
3961                 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
3962                                 << BM_RCTL_MO_SHIFT);
3963         if (mreg & E1000_RCTL_BAM)
3964                 preg |= BM_RCTL_BAM;
3965         if (mreg & E1000_RCTL_PMCF)
3966                 preg |= BM_RCTL_PMCF;
3967         mreg = E1000_READ_REG(hw, E1000_CTRL);
3968         if (mreg & E1000_CTRL_RFCE)
3969                 preg |= BM_RCTL_RFCE;
3970         e1000_write_phy_reg(hw, BM_RCTL, preg);
3971
3972         /* enable PHY wakeup in MAC register */
3973         E1000_WRITE_REG(hw, E1000_WUC,
3974             E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
3975         E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol);
3976
3977         /* configure and enable PHY wakeup in PHY registers */
3978         e1000_write_phy_reg(hw, BM_WUFC, adapter->wol);
3979         e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN);
3980
3981         /* activate PHY wakeup */
3982         ret = hw->phy.ops.acquire(hw);
3983         if (ret) {
3984                 printf("Could not acquire PHY\n");
3985                 return ret;
3986         }
3987         e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3988                                  (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3989         ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
3990         if (ret) {
3991                 printf("Could not read PHY page 769\n");
3992                 goto out;
3993         }
3994         preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
3995         ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
3996         if (ret)
3997                 printf("Could not set PHY Host Wakeup bit\n");
3998 out:
3999         hw->phy.ops.release(hw);
4000
4001         return ret;
4002 }
4003
4004 static void
4005 em_if_led_func(if_ctx_t ctx, int onoff)
4006 {
4007         struct adapter *adapter = iflib_get_softc(ctx);
4008
4009         if (onoff) {
4010                 e1000_setup_led(&adapter->hw);
4011                 e1000_led_on(&adapter->hw);
4012         } else {
4013                 e1000_led_off(&adapter->hw);
4014                 e1000_cleanup_led(&adapter->hw);
4015         }
4016 }
4017
4018 /*
4019  * Disable the L0S and L1 LINK states
4020  */
4021 static void
4022 em_disable_aspm(struct adapter *adapter)
4023 {
4024         int base, reg;
4025         u16 link_cap,link_ctrl;
4026         device_t dev = adapter->dev;
4027
4028         switch (adapter->hw.mac.type) {
4029         case e1000_82573:
4030         case e1000_82574:
4031         case e1000_82583:
4032                 break;
4033         default:
4034                 return;
4035         }
4036         if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
4037                 return;
4038         reg = base + PCIER_LINK_CAP;
4039         link_cap = pci_read_config(dev, reg, 2);
4040         if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
4041                 return;
4042         reg = base + PCIER_LINK_CTL;
4043         link_ctrl = pci_read_config(dev, reg, 2);
4044         link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
4045         pci_write_config(dev, reg, link_ctrl, 2);
4046         return;
4047 }
4048
4049 /**********************************************************************
4050  *
4051  *  Update the board statistics counters.
4052  *
4053  **********************************************************************/
4054 static void
4055 em_update_stats_counters(struct adapter *adapter)
4056 {
4057         u64 prev_xoffrxc = adapter->stats.xoffrxc;
4058
4059         if(adapter->hw.phy.media_type == e1000_media_type_copper ||
4060            (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
4061                 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
4062                 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
4063         }
4064         adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
4065         adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
4066         adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
4067         adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
4068
4069         adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
4070         adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
4071         adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
4072         adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
4073         adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
4074         adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
4075         adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
4076         adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
4077         /*
4078          ** For watchdog management we need to know if we have been
4079          ** paused during the last interval, so capture that here.
4080         */
4081         if (adapter->stats.xoffrxc != prev_xoffrxc)
4082                 adapter->shared->isc_pause_frames = 1;
4083         adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
4084         adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
4085         adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
4086         adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
4087         adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
4088         adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
4089         adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
4090         adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
4091         adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
4092         adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
4093         adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
4094         adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
4095
4096         /* For the 64-bit byte counters the low dword must be read first. */
4097         /* Both registers clear on the read of the high dword */
4098
4099         adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) +
4100             ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32);
4101         adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) +
4102             ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32);
4103
4104         adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
4105         adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
4106         adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
4107         adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
4108         adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
4109
4110         adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
4111         adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
4112
4113         adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
4114         adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
4115         adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
4116         adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
4117         adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
4118         adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
4119         adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
4120         adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
4121         adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
4122         adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
4123
4124         /* Interrupt Counts */
4125
4126         adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC);
4127         adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC);
4128         adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC);
4129         adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC);
4130         adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC);
4131         adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC);
4132         adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC);
4133         adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC);
4134         adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC);
4135
4136         if (adapter->hw.mac.type >= e1000_82543) {
4137                 adapter->stats.algnerrc +=
4138                 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
4139                 adapter->stats.rxerrc +=
4140                 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
4141                 adapter->stats.tncrs +=
4142                 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
4143                 adapter->stats.cexterr +=
4144                 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
4145                 adapter->stats.tsctc +=
4146                 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
4147                 adapter->stats.tsctfc +=
4148                 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
4149         }
4150 }
4151
4152 static uint64_t
4153 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
4154 {
4155         struct adapter *adapter = iflib_get_softc(ctx);
4156         struct ifnet *ifp = iflib_get_ifp(ctx);
4157
4158         switch (cnt) {
4159         case IFCOUNTER_COLLISIONS:
4160                 return (adapter->stats.colc);
4161         case IFCOUNTER_IERRORS:
4162                 return (adapter->dropped_pkts + adapter->stats.rxerrc +
4163                     adapter->stats.crcerrs + adapter->stats.algnerrc +
4164                     adapter->stats.ruc + adapter->stats.roc +
4165                     adapter->stats.mpc + adapter->stats.cexterr);
4166         case IFCOUNTER_OERRORS:
4167                 return (adapter->stats.ecol + adapter->stats.latecol +
4168                     adapter->watchdog_events);
4169         default:
4170                 return (if_get_counter_default(ifp, cnt));
4171         }
4172 }
4173
4174 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized
4175  * @ctx: iflib context
4176  * @event: event code to check
4177  *
4178  * Defaults to returning true for unknown events.
4179  *
4180  * @returns true if iflib needs to reinit the interface
4181  */
4182 static bool
4183 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
4184 {
4185         switch (event) {
4186         case IFLIB_RESTART_VLAN_CONFIG:
4187                 return (false);
4188         default:
4189                 return (true);
4190         }
4191 }
4192
4193 /* Export a single 32-bit register via a read-only sysctl. */
4194 static int
4195 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
4196 {
4197         struct adapter *adapter;
4198         u_int val;
4199
4200         adapter = oidp->oid_arg1;
4201         val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2);
4202         return (sysctl_handle_int(oidp, &val, 0, req));
4203 }
4204
4205 /*
4206  * Add sysctl variables, one per statistic, to the system.
4207  */
4208 static void
4209 em_add_hw_stats(struct adapter *adapter)
4210 {
4211         device_t dev = iflib_get_dev(adapter->ctx);
4212         struct em_tx_queue *tx_que = adapter->tx_queues;
4213         struct em_rx_queue *rx_que = adapter->rx_queues;
4214
4215         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
4216         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
4217         struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
4218         struct e1000_hw_stats *stats = &adapter->stats;
4219
4220         struct sysctl_oid *stat_node, *queue_node, *int_node;
4221         struct sysctl_oid_list *stat_list, *queue_list, *int_list;
4222
4223 #define QUEUE_NAME_LEN 32
4224         char namebuf[QUEUE_NAME_LEN];
4225
4226         /* Driver Statistics */
4227         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
4228                         CTLFLAG_RD, &adapter->dropped_pkts,
4229                         "Driver dropped packets");
4230         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
4231                         CTLFLAG_RD, &adapter->link_irq,
4232                         "Link MSI-X IRQ Handled");
4233         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
4234                         CTLFLAG_RD, &adapter->rx_overruns,
4235                         "RX overruns");
4236         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
4237                         CTLFLAG_RD, &adapter->watchdog_events,
4238                         "Watchdog timeouts");
4239         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
4240             CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
4241             adapter, E1000_CTRL, em_sysctl_reg_handler, "IU",
4242             "Device Control Register");
4243         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
4244             CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
4245             adapter, E1000_RCTL, em_sysctl_reg_handler, "IU",
4246             "Receiver Control Register");
4247         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
4248                         CTLFLAG_RD, &adapter->hw.fc.high_water, 0,
4249                         "Flow Control High Watermark");
4250         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
4251                         CTLFLAG_RD, &adapter->hw.fc.low_water, 0,
4252                         "Flow Control Low Watermark");
4253
4254         for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
4255                 struct tx_ring *txr = &tx_que->txr;
4256                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
4257                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4258                     CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name");
4259                 queue_list = SYSCTL_CHILDREN(queue_node);
4260
4261                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
4262                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4263                     E1000_TDH(txr->me), em_sysctl_reg_handler, "IU",
4264                     "Transmit Descriptor Head");
4265                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
4266                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4267                     E1000_TDT(txr->me), em_sysctl_reg_handler, "IU",
4268                     "Transmit Descriptor Tail");
4269                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
4270                                 CTLFLAG_RD, &txr->tx_irq,
4271                                 "Queue MSI-X Transmit Interrupts");
4272         }
4273
4274         for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) {
4275                 struct rx_ring *rxr = &rx_que->rxr;
4276                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
4277                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4278                     CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name");
4279                 queue_list = SYSCTL_CHILDREN(queue_node);
4280
4281                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
4282                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4283                     E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU",
4284                     "Receive Descriptor Head");
4285                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
4286                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4287                     E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU",
4288                     "Receive Descriptor Tail");
4289                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
4290                                 CTLFLAG_RD, &rxr->rx_irq,
4291                                 "Queue MSI-X Receive Interrupts");
4292         }
4293
4294         /* MAC stats get their own sub node */
4295
4296         stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
4297             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics");
4298         stat_list = SYSCTL_CHILDREN(stat_node);
4299
4300         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
4301                         CTLFLAG_RD, &stats->ecol,
4302                         "Excessive collisions");
4303         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
4304                         CTLFLAG_RD, &stats->scc,
4305                         "Single collisions");
4306         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
4307                         CTLFLAG_RD, &stats->mcc,
4308                         "Multiple collisions");
4309         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
4310                         CTLFLAG_RD, &stats->latecol,
4311                         "Late collisions");
4312         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
4313                         CTLFLAG_RD, &stats->colc,
4314                         "Collision Count");
4315         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
4316                         CTLFLAG_RD, &adapter->stats.symerrs,
4317                         "Symbol Errors");
4318         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
4319                         CTLFLAG_RD, &adapter->stats.sec,
4320                         "Sequence Errors");
4321         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
4322                         CTLFLAG_RD, &adapter->stats.dc,
4323                         "Defer Count");
4324         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
4325                         CTLFLAG_RD, &adapter->stats.mpc,
4326                         "Missed Packets");
4327         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
4328                         CTLFLAG_RD, &adapter->stats.rnbc,
4329                         "Receive No Buffers");
4330         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
4331                         CTLFLAG_RD, &adapter->stats.ruc,
4332                         "Receive Undersize");
4333         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
4334                         CTLFLAG_RD, &adapter->stats.rfc,
4335                         "Fragmented Packets Received ");
4336         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
4337                         CTLFLAG_RD, &adapter->stats.roc,
4338                         "Oversized Packets Received");
4339         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
4340                         CTLFLAG_RD, &adapter->stats.rjc,
4341                         "Recevied Jabber");
4342         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
4343                         CTLFLAG_RD, &adapter->stats.rxerrc,
4344                         "Receive Errors");
4345         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
4346                         CTLFLAG_RD, &adapter->stats.crcerrs,
4347                         "CRC errors");
4348         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
4349                         CTLFLAG_RD, &adapter->stats.algnerrc,
4350                         "Alignment Errors");
4351         /* On 82575 these are collision counts */
4352         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
4353                         CTLFLAG_RD, &adapter->stats.cexterr,
4354                         "Collision/Carrier extension errors");
4355         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
4356                         CTLFLAG_RD, &adapter->stats.xonrxc,
4357                         "XON Received");
4358         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
4359                         CTLFLAG_RD, &adapter->stats.xontxc,
4360                         "XON Transmitted");
4361         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
4362                         CTLFLAG_RD, &adapter->stats.xoffrxc,
4363                         "XOFF Received");
4364         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
4365                         CTLFLAG_RD, &adapter->stats.xofftxc,
4366                         "XOFF Transmitted");
4367
4368         /* Packet Reception Stats */
4369         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
4370                         CTLFLAG_RD, &adapter->stats.tpr,
4371                         "Total Packets Received ");
4372         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
4373                         CTLFLAG_RD, &adapter->stats.gprc,
4374                         "Good Packets Received");
4375         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
4376                         CTLFLAG_RD, &adapter->stats.bprc,
4377                         "Broadcast Packets Received");
4378         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
4379                         CTLFLAG_RD, &adapter->stats.mprc,
4380                         "Multicast Packets Received");
4381         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
4382                         CTLFLAG_RD, &adapter->stats.prc64,
4383                         "64 byte frames received ");
4384         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
4385                         CTLFLAG_RD, &adapter->stats.prc127,
4386                         "65-127 byte frames received");
4387         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
4388                         CTLFLAG_RD, &adapter->stats.prc255,
4389                         "128-255 byte frames received");
4390         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
4391                         CTLFLAG_RD, &adapter->stats.prc511,
4392                         "256-511 byte frames received");
4393         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
4394                         CTLFLAG_RD, &adapter->stats.prc1023,
4395                         "512-1023 byte frames received");
4396         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
4397                         CTLFLAG_RD, &adapter->stats.prc1522,
4398                         "1023-1522 byte frames received");
4399         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
4400                         CTLFLAG_RD, &adapter->stats.gorc,
4401                         "Good Octets Received");
4402
4403         /* Packet Transmission Stats */
4404         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
4405                         CTLFLAG_RD, &adapter->stats.gotc,
4406                         "Good Octets Transmitted");
4407         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
4408                         CTLFLAG_RD, &adapter->stats.tpt,
4409                         "Total Packets Transmitted");
4410         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
4411                         CTLFLAG_RD, &adapter->stats.gptc,
4412                         "Good Packets Transmitted");
4413         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
4414                         CTLFLAG_RD, &adapter->stats.bptc,
4415                         "Broadcast Packets Transmitted");
4416         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
4417                         CTLFLAG_RD, &adapter->stats.mptc,
4418                         "Multicast Packets Transmitted");
4419         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
4420                         CTLFLAG_RD, &adapter->stats.ptc64,
4421                         "64 byte frames transmitted ");
4422         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
4423                         CTLFLAG_RD, &adapter->stats.ptc127,
4424                         "65-127 byte frames transmitted");
4425         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
4426                         CTLFLAG_RD, &adapter->stats.ptc255,
4427                         "128-255 byte frames transmitted");
4428         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
4429                         CTLFLAG_RD, &adapter->stats.ptc511,
4430                         "256-511 byte frames transmitted");
4431         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
4432                         CTLFLAG_RD, &adapter->stats.ptc1023,
4433                         "512-1023 byte frames transmitted");
4434         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
4435                         CTLFLAG_RD, &adapter->stats.ptc1522,
4436                         "1024-1522 byte frames transmitted");
4437         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
4438                         CTLFLAG_RD, &adapter->stats.tsctc,
4439                         "TSO Contexts Transmitted");
4440         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
4441                         CTLFLAG_RD, &adapter->stats.tsctfc,
4442                         "TSO Contexts Failed");
4443
4444
4445         /* Interrupt Stats */
4446
4447         int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
4448             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics");
4449         int_list = SYSCTL_CHILDREN(int_node);
4450
4451         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
4452                         CTLFLAG_RD, &adapter->stats.iac,
4453                         "Interrupt Assertion Count");
4454
4455         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
4456                         CTLFLAG_RD, &adapter->stats.icrxptc,
4457                         "Interrupt Cause Rx Pkt Timer Expire Count");
4458
4459         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
4460                         CTLFLAG_RD, &adapter->stats.icrxatc,
4461                         "Interrupt Cause Rx Abs Timer Expire Count");
4462
4463         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
4464                         CTLFLAG_RD, &adapter->stats.ictxptc,
4465                         "Interrupt Cause Tx Pkt Timer Expire Count");
4466
4467         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
4468                         CTLFLAG_RD, &adapter->stats.ictxatc,
4469                         "Interrupt Cause Tx Abs Timer Expire Count");
4470
4471         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
4472                         CTLFLAG_RD, &adapter->stats.ictxqec,
4473                         "Interrupt Cause Tx Queue Empty Count");
4474
4475         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
4476                         CTLFLAG_RD, &adapter->stats.ictxqmtc,
4477                         "Interrupt Cause Tx Queue Min Thresh Count");
4478
4479         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
4480                         CTLFLAG_RD, &adapter->stats.icrxdmtc,
4481                         "Interrupt Cause Rx Desc Min Thresh Count");
4482
4483         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
4484                         CTLFLAG_RD, &adapter->stats.icrxoc,
4485                         "Interrupt Cause Receiver Overrun Count");
4486 }
4487
4488 /**********************************************************************
4489  *
4490  *  This routine provides a way to dump out the adapter eeprom,
4491  *  often a useful debug/service tool. This only dumps the first
4492  *  32 words, stuff that matters is in that extent.
4493  *
4494  **********************************************************************/
4495 static int
4496 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4497 {
4498         struct adapter *adapter = (struct adapter *)arg1;
4499         int error;
4500         int result;
4501
4502         result = -1;
4503         error = sysctl_handle_int(oidp, &result, 0, req);
4504
4505         if (error || !req->newptr)
4506                 return (error);
4507
4508         /*
4509          * This value will cause a hex dump of the
4510          * first 32 16-bit words of the EEPROM to
4511          * the screen.
4512          */
4513         if (result == 1)
4514                 em_print_nvm_info(adapter);
4515
4516         return (error);
4517 }
4518
4519 static void
4520 em_print_nvm_info(struct adapter *adapter)
4521 {
4522         u16 eeprom_data;
4523         int i, j, row = 0;
4524
4525         /* Its a bit crude, but it gets the job done */
4526         printf("\nInterface EEPROM Dump:\n");
4527         printf("Offset\n0x0000  ");
4528         for (i = 0, j = 0; i < 32; i++, j++) {
4529                 if (j == 8) { /* Make the offset block */
4530                         j = 0; ++row;
4531                         printf("\n0x00%x0  ",row);
4532                 }
4533                 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
4534                 printf("%04x ", eeprom_data);
4535         }
4536         printf("\n");
4537 }
4538
4539 static int
4540 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4541 {
4542         struct em_int_delay_info *info;
4543         struct adapter *adapter;
4544         u32 regval;
4545         int error, usecs, ticks;
4546
4547         info = (struct em_int_delay_info *) arg1;
4548         usecs = info->value;
4549         error = sysctl_handle_int(oidp, &usecs, 0, req);
4550         if (error != 0 || req->newptr == NULL)
4551                 return (error);
4552         if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4553                 return (EINVAL);
4554         info->value = usecs;
4555         ticks = EM_USECS_TO_TICKS(usecs);
4556         if (info->offset == E1000_ITR)  /* units are 256ns here */
4557                 ticks *= 4;
4558
4559         adapter = info->adapter;
4560
4561         regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
4562         regval = (regval & ~0xffff) | (ticks & 0xffff);
4563         /* Handle a few special cases. */
4564         switch (info->offset) {
4565         case E1000_RDTR:
4566                 break;
4567         case E1000_TIDV:
4568                 if (ticks == 0) {
4569                         adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
4570                         /* Don't write 0 into the TIDV register. */
4571                         regval++;
4572                 } else
4573                         adapter->txd_cmd |= E1000_TXD_CMD_IDE;
4574                 break;
4575         }
4576         E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
4577         return (0);
4578 }
4579
4580 static void
4581 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
4582         const char *description, struct em_int_delay_info *info,
4583         int offset, int value)
4584 {
4585         info->adapter = adapter;
4586         info->offset = offset;
4587         info->value = value;
4588         SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev),
4589             SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4590             OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
4591             info, 0, em_sysctl_int_delay, "I", description);
4592 }
4593
4594 /*
4595  * Set flow control using sysctl:
4596  * Flow control values:
4597  *      0 - off
4598  *      1 - rx pause
4599  *      2 - tx pause
4600  *      3 - full
4601  */
4602 static int
4603 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4604 {
4605         int error;
4606         static int input = 3; /* default is full */
4607         struct adapter  *adapter = (struct adapter *) arg1;
4608
4609         error = sysctl_handle_int(oidp, &input, 0, req);
4610
4611         if ((error) || (req->newptr == NULL))
4612                 return (error);
4613
4614         if (input == adapter->fc) /* no change? */
4615                 return (error);
4616
4617         switch (input) {
4618         case e1000_fc_rx_pause:
4619         case e1000_fc_tx_pause:
4620         case e1000_fc_full:
4621         case e1000_fc_none:
4622                 adapter->hw.fc.requested_mode = input;
4623                 adapter->fc = input;
4624                 break;
4625         default:
4626                 /* Do nothing */
4627                 return (error);
4628         }
4629
4630         adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
4631         e1000_force_mac_fc(&adapter->hw);
4632         return (error);
4633 }
4634
4635 /*
4636  * Manage Energy Efficient Ethernet:
4637  * Control values:
4638  *     0/1 - enabled/disabled
4639  */
4640 static int
4641 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4642 {
4643         struct adapter *adapter = (struct adapter *) arg1;
4644         int error, value;
4645
4646         value = adapter->hw.dev_spec.ich8lan.eee_disable;
4647         error = sysctl_handle_int(oidp, &value, 0, req);
4648         if (error || req->newptr == NULL)
4649                 return (error);
4650         adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4651         em_if_init(adapter->ctx);
4652
4653         return (0);
4654 }
4655
4656 static int
4657 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4658 {
4659         struct adapter *adapter;
4660         int error;
4661         int result;
4662
4663         result = -1;
4664         error = sysctl_handle_int(oidp, &result, 0, req);
4665
4666         if (error || !req->newptr)
4667                 return (error);
4668
4669         if (result == 1) {
4670                 adapter = (struct adapter *) arg1;
4671                 em_print_debug_info(adapter);
4672         }
4673
4674         return (error);
4675 }
4676
4677 static int
4678 em_get_rs(SYSCTL_HANDLER_ARGS)
4679 {
4680         struct adapter *adapter = (struct adapter *) arg1;
4681         int error;
4682         int result;
4683
4684         result = 0;
4685         error = sysctl_handle_int(oidp, &result, 0, req);
4686
4687         if (error || !req->newptr || result != 1)
4688                 return (error);
4689         em_dump_rs(adapter);
4690
4691         return (error);
4692 }
4693
4694 static void
4695 em_if_debug(if_ctx_t ctx)
4696 {
4697         em_dump_rs(iflib_get_softc(ctx));
4698 }
4699
4700 /*
4701  * This routine is meant to be fluid, add whatever is
4702  * needed for debugging a problem.  -jfv
4703  */
4704 static void
4705 em_print_debug_info(struct adapter *adapter)
4706 {
4707         device_t dev = iflib_get_dev(adapter->ctx);
4708         struct ifnet *ifp = iflib_get_ifp(adapter->ctx);
4709         struct tx_ring *txr = &adapter->tx_queues->txr;
4710         struct rx_ring *rxr = &adapter->rx_queues->rxr;
4711
4712         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
4713                 printf("Interface is RUNNING ");
4714         else
4715                 printf("Interface is NOT RUNNING\n");
4716
4717         if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
4718                 printf("and INACTIVE\n");
4719         else
4720                 printf("and ACTIVE\n");
4721
4722         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
4723                 device_printf(dev, "TX Queue %d ------\n", i);
4724                 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
4725                         E1000_READ_REG(&adapter->hw, E1000_TDH(i)),
4726                         E1000_READ_REG(&adapter->hw, E1000_TDT(i)));
4727
4728         }
4729         for (int j=0; j < adapter->rx_num_queues; j++, rxr++) {
4730                 device_printf(dev, "RX Queue %d ------\n", j);
4731                 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
4732                         E1000_READ_REG(&adapter->hw, E1000_RDH(j)),
4733                         E1000_READ_REG(&adapter->hw, E1000_RDT(j)));
4734         }
4735 }
4736
4737 /*
4738  * 82574 only:
4739  * Write a new value to the EEPROM increasing the number of MSI-X
4740  * vectors from 3 to 5, for proper multiqueue support.
4741  */
4742 static void
4743 em_enable_vectors_82574(if_ctx_t ctx)
4744 {
4745         struct adapter *adapter = iflib_get_softc(ctx);
4746         struct e1000_hw *hw = &adapter->hw;
4747         device_t dev = iflib_get_dev(ctx);
4748         u16 edata;
4749
4750         e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4751         if (bootverbose)
4752                 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata);
4753         if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
4754                 device_printf(dev, "Writing to eeprom: increasing "
4755                     "reported MSI-X vectors from 3 to 5...\n");
4756                 edata &= ~(EM_NVM_MSIX_N_MASK);
4757                 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
4758                 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4759                 e1000_update_nvm_checksum(hw);
4760                 device_printf(dev, "Writing to eeprom: done\n");
4761         }
4762 }