sys/dev/e1000/if_em.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /* $FreeBSD$ */
  30 #include "if_em.h"
  31 #include <sys/sbuf.h>
  32 #include <machine/_inttypes.h>
  33
  34 #define em_mac_min e1000_82571
  35 #define igb_mac_min e1000_82575
  36
  37 /*********************************************************************
  38  *  Driver version:
  39  *********************************************************************/
  40 char em_driver_version[] = "7.6.1-k";
  41
  42 /*********************************************************************
  43  *  PCI Device ID Table
  44  *
  45  *  Used by probe to select devices to load on
  46  *  Last field stores an index into e1000_strings
  47  *  Last entry must be all 0s
  48  *
  49  *  { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
  50  *********************************************************************/
  51
  52 static pci_vendor_info_t em_vendor_info_array[] =
  53 {
  54         /* Intel(R) PRO/1000 Network Connection - Legacy em*/
  55         PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"),
  56         PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"),
  57         PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"),
  58         PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"),
  59         PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"),
  60
  61         PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"),
  62         PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"),
  63         PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"),
  64         PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  65         PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"),
  66         PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"),
  67         PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  68
  69         PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"),
  70
  71         PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"),
  72         PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
  73
  74         PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
  75         PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
  76         PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
  77         PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"),
  78
  79         PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"),
  80         PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"),
  81         PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"),
  82         PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"),
  83         PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"),
  84
  85         PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  86         PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
  87         PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
  88         PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  89         PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"),
  90         PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"),
  91         PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"),
  92         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
  93         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"),
  94
  95         PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"),
  96         PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  97         PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"),
  98
  99         /* Intel(R) PRO/1000 Network Connection - em */
 100         PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
 101         PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
 102         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"),
 103         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"),
 104         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"),
 105         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 106         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"),
 107         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"),
 108         PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 109         PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"),
 110         PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
 111         PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
 112         PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"),
 113         PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"),
 114         PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"),
 115         PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"),
 116         PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"),
 117         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"),
 118         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"),
 119         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"),
 120         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"),
 121         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
 122         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 123         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"),
 124         PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"),
 125         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
 126         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"),
 127         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"),
 128         PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"),
 129         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
 130         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 131         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"),
 132         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"),
 133         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"),
 134         PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"),
 135         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
 136         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"),
 137         PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"),
 138         PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"),
 139         PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"),
 140         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"),
 141         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"),
 142         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"),
 143         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"),
 144         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"),
 145         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"),
 146         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"),
 147         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"),
 148         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"),
 149         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"),
 150         PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"),
 151         PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"),
 152         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"),
 153         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"),
 154         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"),
 155         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"),
 156         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"),
 157         PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"),
 158         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"),
 159         PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"),
 160         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"),
 161         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"),
 162         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"),
 163         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"),
 164         PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"),
 165         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"),
 166         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"),
 167         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"),
 168         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"),
 169         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) PRO/1000 Network Connection"),
 170         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) PRO/1000 Network Connection"),
 171         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) PRO/1000 Network Connection"),
 172         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) PRO/1000 Network Connection"),
 173         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) PRO/1000 Network Connection"),
 174         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) PRO/1000 Network Connection"),
 175         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) PRO/1000 Network Connection"),
 176         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) PRO/1000 Network Connection"),
 177         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) PRO/1000 Network Connection"),
 178         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) PRO/1000 Network Connection"),
 179         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) PRO/1000 Network Connection"),
 180         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) PRO/1000 Network Connection"),
 181         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) PRO/1000 Network Connection"),
 182         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) PRO/1000 Network Connection"),
 183         /* required last entry */
 184         PVID_END
 185 };
 186
 187 static pci_vendor_info_t igb_vendor_info_array[] =
 188 {
 189         /* Intel(R) PRO/1000 Network Connection - igb */
 190         PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 191         PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 192         PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 193         PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 194         PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 195         PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 196         PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 197         PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 198         PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 199         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 200         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 201         PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 202         PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 203         PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 204         PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 205         PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 206         PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 207         PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 208         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 209         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 210         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 211         PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 212         PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 213         PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 214         PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 215         PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 216         PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 217         PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 218         PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 219         PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 220         PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 221         PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 222         PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 223         PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 224         PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 225         PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 226         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 227         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 228         PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 229         /* required last entry */
 230         PVID_END
 231 };
 232
 233 /*********************************************************************
 234  *  Function prototypes
 235  *********************************************************************/
 236 static void     *em_register(device_t dev);
 237 static void     *igb_register(device_t dev);
 238 static int      em_if_attach_pre(if_ctx_t ctx);
 239 static int      em_if_attach_post(if_ctx_t ctx);
 240 static int      em_if_detach(if_ctx_t ctx);
 241 static int      em_if_shutdown(if_ctx_t ctx);
 242 static int      em_if_suspend(if_ctx_t ctx);
 243 static int      em_if_resume(if_ctx_t ctx);
 244
 245 static int      em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets);
 246 static int      em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets);
 247 static void     em_if_queues_free(if_ctx_t ctx);
 248
 249 static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
 250 static void     em_if_init(if_ctx_t ctx);
 251 static void     em_if_stop(if_ctx_t ctx);
 252 static void     em_if_media_status(if_ctx_t, struct ifmediareq *);
 253 static int      em_if_media_change(if_ctx_t ctx);
 254 static int      em_if_mtu_set(if_ctx_t ctx, uint32_t mtu);
 255 static void     em_if_timer(if_ctx_t ctx, uint16_t qid);
 256 static void     em_if_vlan_register(if_ctx_t ctx, u16 vtag);
 257 static void     em_if_vlan_unregister(if_ctx_t ctx, u16 vtag);
 258 static void     em_if_watchdog_reset(if_ctx_t ctx);
 259 static bool     em_if_needs_restart(if_ctx_t ctx, enum iflib_restart_event event);
 260
 261 static void     em_identify_hardware(if_ctx_t ctx);
 262 static int      em_allocate_pci_resources(if_ctx_t ctx);
 263 static void     em_free_pci_resources(if_ctx_t ctx);
 264 static void     em_reset(if_ctx_t ctx);
 265 static int      em_setup_interface(if_ctx_t ctx);
 266 static int      em_setup_msix(if_ctx_t ctx);
 267
 268 static void     em_initialize_transmit_unit(if_ctx_t ctx);
 269 static void     em_initialize_receive_unit(if_ctx_t ctx);
 270
 271 static void     em_if_intr_enable(if_ctx_t ctx);
 272 static void     em_if_intr_disable(if_ctx_t ctx);
 273 static void     igb_if_intr_enable(if_ctx_t ctx);
 274 static void     igb_if_intr_disable(if_ctx_t ctx);
 275 static int      em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 276 static int      em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
 277 static int      igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 278 static int      igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
 279 static void     em_if_multi_set(if_ctx_t ctx);
 280 static void     em_if_update_admin_status(if_ctx_t ctx);
 281 static void     em_if_debug(if_ctx_t ctx);
 282 static void     em_update_stats_counters(struct adapter *);
 283 static void     em_add_hw_stats(struct adapter *adapter);
 284 static int      em_if_set_promisc(if_ctx_t ctx, int flags);
 285 static void     em_setup_vlan_hw_support(struct adapter *);
 286 static int      em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
 287 static void     em_print_nvm_info(struct adapter *);
 288 static int      em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 289 static int      em_get_rs(SYSCTL_HANDLER_ARGS);
 290 static void     em_print_debug_info(struct adapter *);
 291 static int      em_is_valid_ether_addr(u8 *);
 292 static int      em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
 293 static void     em_add_int_delay_sysctl(struct adapter *, const char *,
 294                     const char *, struct em_int_delay_info *, int, int);
 295 /* Management and WOL Support */
 296 static void     em_init_manageability(struct adapter *);
 297 static void     em_release_manageability(struct adapter *);
 298 static void     em_get_hw_control(struct adapter *);
 299 static void     em_release_hw_control(struct adapter *);
 300 static void     em_get_wakeup(if_ctx_t ctx);
 301 static void     em_enable_wakeup(if_ctx_t ctx);
 302 static int      em_enable_phy_wakeup(struct adapter *);
 303 static void     em_disable_aspm(struct adapter *);
 304
 305 int             em_intr(void *arg);
 306 static void     em_disable_promisc(if_ctx_t ctx);
 307
 308 /* MSI-X handlers */
 309 static int      em_if_msix_intr_assign(if_ctx_t, int);
 310 static int      em_msix_link(void *);
 311 static void     em_handle_link(void *context);
 312
 313 static void     em_enable_vectors_82574(if_ctx_t);
 314
 315 static int      em_set_flowcntl(SYSCTL_HANDLER_ARGS);
 316 static int      em_sysctl_eee(SYSCTL_HANDLER_ARGS);
 317 static void     em_if_led_func(if_ctx_t ctx, int onoff);
 318
 319 static int      em_get_regs(SYSCTL_HANDLER_ARGS);
 320
 321 static void     lem_smartspeed(struct adapter *adapter);
 322 static void     igb_configure_queues(struct adapter *adapter);
 323
 324
 325 /*********************************************************************
 326  *  FreeBSD Device Interface Entry Points
 327  *********************************************************************/
 328 static device_method_t em_methods[] = {
 329         /* Device interface */
 330         DEVMETHOD(device_register, em_register),
 331         DEVMETHOD(device_probe, iflib_device_probe),
 332         DEVMETHOD(device_attach, iflib_device_attach),
 333         DEVMETHOD(device_detach, iflib_device_detach),
 334         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 335         DEVMETHOD(device_suspend, iflib_device_suspend),
 336         DEVMETHOD(device_resume, iflib_device_resume),
 337         DEVMETHOD_END
 338 };
 339
 340 static device_method_t igb_methods[] = {
 341         /* Device interface */
 342         DEVMETHOD(device_register, igb_register),
 343         DEVMETHOD(device_probe, iflib_device_probe),
 344         DEVMETHOD(device_attach, iflib_device_attach),
 345         DEVMETHOD(device_detach, iflib_device_detach),
 346         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 347         DEVMETHOD(device_suspend, iflib_device_suspend),
 348         DEVMETHOD(device_resume, iflib_device_resume),
 349         DEVMETHOD_END
 350 };
 351
 352
 353 static driver_t em_driver = {
 354         "em", em_methods, sizeof(struct adapter),
 355 };
 356
 357 static devclass_t em_devclass;
 358 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
 359
 360 MODULE_DEPEND(em, pci, 1, 1, 1);
 361 MODULE_DEPEND(em, ether, 1, 1, 1);
 362 MODULE_DEPEND(em, iflib, 1, 1, 1);
 363
 364 IFLIB_PNP_INFO(pci, em, em_vendor_info_array);
 365
 366 static driver_t igb_driver = {
 367         "igb", igb_methods, sizeof(struct adapter),
 368 };
 369
 370 static devclass_t igb_devclass;
 371 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
 372
 373 MODULE_DEPEND(igb, pci, 1, 1, 1);
 374 MODULE_DEPEND(igb, ether, 1, 1, 1);
 375 MODULE_DEPEND(igb, iflib, 1, 1, 1);
 376
 377 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array);
 378
 379 static device_method_t em_if_methods[] = {
 380         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 381         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 382         DEVMETHOD(ifdi_detach, em_if_detach),
 383         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 384         DEVMETHOD(ifdi_suspend, em_if_suspend),
 385         DEVMETHOD(ifdi_resume, em_if_resume),
 386         DEVMETHOD(ifdi_init, em_if_init),
 387         DEVMETHOD(ifdi_stop, em_if_stop),
 388         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 389         DEVMETHOD(ifdi_intr_enable, em_if_intr_enable),
 390         DEVMETHOD(ifdi_intr_disable, em_if_intr_disable),
 391         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 392         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 393         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 394         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 395         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 396         DEVMETHOD(ifdi_media_status, em_if_media_status),
 397         DEVMETHOD(ifdi_media_change, em_if_media_change),
 398         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 399         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 400         DEVMETHOD(ifdi_timer, em_if_timer),
 401         DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
 402         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 403         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 404         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 405         DEVMETHOD(ifdi_led_func, em_if_led_func),
 406         DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable),
 407         DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable),
 408         DEVMETHOD(ifdi_debug, em_if_debug),
 409         DEVMETHOD(ifdi_needs_restart, em_if_needs_restart),
 410         DEVMETHOD_END
 411 };
 412
 413 static driver_t em_if_driver = {
 414         "em_if", em_if_methods, sizeof(struct adapter)
 415 };
 416
 417 static device_method_t igb_if_methods[] = {
 418         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 419         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 420         DEVMETHOD(ifdi_detach, em_if_detach),
 421         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 422         DEVMETHOD(ifdi_suspend, em_if_suspend),
 423         DEVMETHOD(ifdi_resume, em_if_resume),
 424         DEVMETHOD(ifdi_init, em_if_init),
 425         DEVMETHOD(ifdi_stop, em_if_stop),
 426         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 427         DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable),
 428         DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable),
 429         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 430         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 431         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 432         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 433         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 434         DEVMETHOD(ifdi_media_status, em_if_media_status),
 435         DEVMETHOD(ifdi_media_change, em_if_media_change),
 436         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 437         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 438         DEVMETHOD(ifdi_timer, em_if_timer),
 439         DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
 440         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 441         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 442         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 443         DEVMETHOD(ifdi_led_func, em_if_led_func),
 444         DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable),
 445         DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable),
 446         DEVMETHOD(ifdi_debug, em_if_debug),
 447         DEVMETHOD(ifdi_needs_restart, em_if_needs_restart),
 448         DEVMETHOD_END
 449 };
 450
 451 static driver_t igb_if_driver = {
 452         "igb_if", igb_if_methods, sizeof(struct adapter)
 453 };
 454
 455 /*********************************************************************
 456  *  Tunable default values.
 457  *********************************************************************/
 458
 459 #define EM_TICKS_TO_USECS(ticks)        ((1024 * (ticks) + 500) / 1000)
 460 #define EM_USECS_TO_TICKS(usecs)        ((1000 * (usecs) + 512) / 1024)
 461
 462 #define MAX_INTS_PER_SEC        8000
 463 #define DEFAULT_ITR             (1000000000/(MAX_INTS_PER_SEC * 256))
 464
 465 /* Allow common code without TSO */
 466 #ifndef CSUM_TSO
 467 #define CSUM_TSO        0
 468 #endif
 469
 470 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
 471     "EM driver parameters");
 472
 473 static int em_disable_crc_stripping = 0;
 474 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
 475     &em_disable_crc_stripping, 0, "Disable CRC Stripping");
 476
 477 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
 478 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
 479 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
 480     0, "Default transmit interrupt delay in usecs");
 481 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
 482     0, "Default receive interrupt delay in usecs");
 483
 484 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
 485 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
 486 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
 487     &em_tx_abs_int_delay_dflt, 0,
 488     "Default transmit interrupt delay limit in usecs");
 489 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
 490     &em_rx_abs_int_delay_dflt, 0,
 491     "Default receive interrupt delay limit in usecs");
 492
 493 static int em_smart_pwr_down = FALSE;
 494 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
 495     0, "Set to true to leave smart power down enabled on newer adapters");
 496
 497 /* Controls whether promiscuous also shows bad packets */
 498 static int em_debug_sbp = FALSE;
 499 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
 500     "Show bad packets in promiscuous mode");
 501
 502 /* How many packets rxeof tries to clean at a time */
 503 static int em_rx_process_limit = 100;
 504 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
 505     &em_rx_process_limit, 0,
 506     "Maximum number of received packets to process "
 507     "at a time, -1 means unlimited");
 508
 509 /* Energy efficient ethernet - default to OFF */
 510 static int eee_setting = 1;
 511 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
 512     "Enable Energy Efficient Ethernet");
 513
 514 /*
 515 ** Tuneable Interrupt rate
 516 */
 517 static int em_max_interrupt_rate = 8000;
 518 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
 519     &em_max_interrupt_rate, 0, "Maximum interrupts per second");
 520
 521
 522
 523 /* Global used in WOL setup with multiport cards */
 524 static int global_quad_port_a = 0;
 525
 526 extern struct if_txrx igb_txrx;
 527 extern struct if_txrx em_txrx;
 528 extern struct if_txrx lem_txrx;
 529
 530 static struct if_shared_ctx em_sctx_init = {
 531         .isc_magic = IFLIB_MAGIC,
 532         .isc_q_align = PAGE_SIZE,
 533         .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 534         .isc_tx_maxsegsize = PAGE_SIZE,
 535         .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 536         .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
 537         .isc_rx_maxsize = MJUM9BYTES,
 538         .isc_rx_nsegments = 1,
 539         .isc_rx_maxsegsize = MJUM9BYTES,
 540         .isc_nfl = 1,
 541         .isc_nrxqs = 1,
 542         .isc_ntxqs = 1,
 543         .isc_admin_intrcnt = 1,
 544         .isc_vendor_info = em_vendor_info_array,
 545         .isc_driver_version = em_driver_version,
 546         .isc_driver = &em_if_driver,
 547         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 548
 549         .isc_nrxd_min = {EM_MIN_RXD},
 550         .isc_ntxd_min = {EM_MIN_TXD},
 551         .isc_nrxd_max = {EM_MAX_RXD},
 552         .isc_ntxd_max = {EM_MAX_TXD},
 553         .isc_nrxd_default = {EM_DEFAULT_RXD},
 554         .isc_ntxd_default = {EM_DEFAULT_TXD},
 555 };
 556
 557 static struct if_shared_ctx igb_sctx_init = {
 558         .isc_magic = IFLIB_MAGIC,
 559         .isc_q_align = PAGE_SIZE,
 560         .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 561         .isc_tx_maxsegsize = PAGE_SIZE,
 562         .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 563         .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
 564         .isc_rx_maxsize = MJUM9BYTES,
 565         .isc_rx_nsegments = 1,
 566         .isc_rx_maxsegsize = MJUM9BYTES,
 567         .isc_nfl = 1,
 568         .isc_nrxqs = 1,
 569         .isc_ntxqs = 1,
 570         .isc_admin_intrcnt = 1,
 571         .isc_vendor_info = igb_vendor_info_array,
 572         .isc_driver_version = em_driver_version,
 573         .isc_driver = &igb_if_driver,
 574         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 575
 576         .isc_nrxd_min = {EM_MIN_RXD},
 577         .isc_ntxd_min = {EM_MIN_TXD},
 578         .isc_nrxd_max = {IGB_MAX_RXD},
 579         .isc_ntxd_max = {IGB_MAX_TXD},
 580         .isc_nrxd_default = {EM_DEFAULT_RXD},
 581         .isc_ntxd_default = {EM_DEFAULT_TXD},
 582 };
 583
 584 /*****************************************************************
 585  *
 586  * Dump Registers
 587  *
 588  ****************************************************************/
 589 #define IGB_REGS_LEN 739
 590
 591 static int em_get_regs(SYSCTL_HANDLER_ARGS)
 592 {
 593         struct adapter *adapter = (struct adapter *)arg1;
 594         struct e1000_hw *hw = &adapter->hw;
 595         struct sbuf *sb;
 596         u32 *regs_buff;
 597         int rc;
 598
 599         regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK);
 600         memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
 601
 602         rc = sysctl_wire_old_buffer(req, 0);
 603         MPASS(rc == 0);
 604         if (rc != 0) {
 605                 free(regs_buff, M_DEVBUF);
 606                 return (rc);
 607         }
 608
 609         sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
 610         MPASS(sb != NULL);
 611         if (sb == NULL) {
 612                 free(regs_buff, M_DEVBUF);
 613                 return (ENOMEM);
 614         }
 615
 616         /* General Registers */
 617         regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
 618         regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
 619         regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
 620         regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
 621         regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
 622         regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
 623         regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
 624         regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
 625         regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
 626         regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
 627         regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
 628         regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
 629         regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
 630         regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
 631         regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
 632         regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
 633         regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
 634         regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
 635         regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
 636         regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
 637         regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
 638         regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
 639
 640         sbuf_printf(sb, "General Registers\n");
 641         sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
 642         sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
 643         sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]);
 644
 645         sbuf_printf(sb, "Interrupt Registers\n");
 646         sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
 647
 648         sbuf_printf(sb, "RX Registers\n");
 649         sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
 650         sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
 651         sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
 652         sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
 653         sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
 654         sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
 655         sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
 656
 657         sbuf_printf(sb, "TX Registers\n");
 658         sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
 659         sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
 660         sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
 661         sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
 662         sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
 663         sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
 664         sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
 665         sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
 666         sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
 667         sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
 668         sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
 669
 670         free(regs_buff, M_DEVBUF);
 671
 672 #ifdef DUMP_DESCS
 673         {
 674                 if_softc_ctx_t scctx = adapter->shared;
 675                 struct rx_ring *rxr = &rx_que->rxr;
 676                 struct tx_ring *txr = &tx_que->txr;
 677                 int ntxd = scctx->isc_ntxd[0];
 678                 int nrxd = scctx->isc_nrxd[0];
 679                 int j;
 680
 681         for (j = 0; j < nrxd; j++) {
 682                 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
 683                 u32 length =  le32toh(rxr->rx_base[j].wb.upper.length);
 684                 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 "  Error:%d  Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
 685         }
 686
 687         for (j = 0; j < min(ntxd, 256); j++) {
 688                 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
 689
 690                 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x  eop: %d DD=%d\n",
 691                             j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
 692                             buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
 693
 694         }
 695         }
 696 #endif
 697
 698         rc = sbuf_finish(sb);
 699         sbuf_delete(sb);
 700         return(rc);
 701 }
 702
 703 static void *
 704 em_register(device_t dev)
 705 {
 706         return (&em_sctx_init);
 707 }
 708
 709 static void *
 710 igb_register(device_t dev)
 711 {
 712         return (&igb_sctx_init);
 713 }
 714
 715 static int
 716 em_set_num_queues(if_ctx_t ctx)
 717 {
 718         struct adapter *adapter = iflib_get_softc(ctx);
 719         int maxqueues;
 720
 721         /* Sanity check based on HW */
 722         switch (adapter->hw.mac.type) {
 723         case e1000_82576:
 724         case e1000_82580:
 725         case e1000_i350:
 726         case e1000_i354:
 727                 maxqueues = 8;
 728                 break;
 729         case e1000_i210:
 730         case e1000_82575:
 731                 maxqueues = 4;
 732                 break;
 733         case e1000_i211:
 734         case e1000_82574:
 735                 maxqueues = 2;
 736                 break;
 737         default:
 738                 maxqueues = 1;
 739                 break;
 740         }
 741
 742         return (maxqueues);
 743 }
 744
 745 #define LEM_CAPS                                                        \
 746     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 747     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER
 748
 749 #define EM_CAPS                                                         \
 750     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 751     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 |  \
 752     IFCAP_LRO | IFCAP_VLAN_HWTSO
 753
 754 #define IGB_CAPS                                                        \
 755     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 756     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 |  \
 757     IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\
 758     IFCAP_TSO6
 759
 760 /*********************************************************************
 761  *  Device initialization routine
 762  *
 763  *  The attach entry point is called when the driver is being loaded.
 764  *  This routine identifies the type of hardware, allocates all resources
 765  *  and initializes the hardware.
 766  *
 767  *  return 0 on success, positive on failure
 768  *********************************************************************/
 769 static int
 770 em_if_attach_pre(if_ctx_t ctx)
 771 {
 772         struct adapter *adapter;
 773         if_softc_ctx_t scctx;
 774         device_t dev;
 775         struct e1000_hw *hw;
 776         int error = 0;
 777
 778         INIT_DEBUGOUT("em_if_attach_pre: begin");
 779         dev = iflib_get_dev(ctx);
 780         adapter = iflib_get_softc(ctx);
 781
 782         adapter->ctx = adapter->osdep.ctx = ctx;
 783         adapter->dev = adapter->osdep.dev = dev;
 784         scctx = adapter->shared = iflib_get_softc_ctx(ctx);
 785         adapter->media = iflib_get_media(ctx);
 786         hw = &adapter->hw;
 787
 788         adapter->tx_process_limit = scctx->isc_ntxd[0];
 789
 790         /* SYSCTL stuff */
 791         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 792             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 793             OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
 794             adapter, 0, em_sysctl_nvm_info, "I", "NVM Information");
 795
 796         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 797             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 798             OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
 799             adapter, 0, em_sysctl_debug_info, "I", "Debug Information");
 800
 801         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 802             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 803             OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
 804             adapter, 0, em_set_flowcntl, "I", "Flow Control");
 805
 806         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 807             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 808             OID_AUTO, "reg_dump",
 809             CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 0,
 810             em_get_regs, "A", "Dump Registers");
 811
 812         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 813             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 814             OID_AUTO, "rs_dump",
 815             CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, adapter, 0,
 816             em_get_rs, "I", "Dump RS indexes");
 817
 818         /* Determine hardware and mac info */
 819         em_identify_hardware(ctx);
 820
 821         scctx->isc_tx_nsegments = EM_MAX_SCATTER;
 822         scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
 823         if (bootverbose)
 824                 device_printf(dev, "attach_pre capping queues at %d\n",
 825                     scctx->isc_ntxqsets_max);
 826
 827         if (hw->mac.type >= igb_mac_min) {
 828                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
 829                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
 830                 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
 831                 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
 832                 scctx->isc_txrx = &igb_txrx;
 833                 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
 834                 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 835                 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 836                 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS;
 837                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO |
 838                      CSUM_IP6_TCP | CSUM_IP6_UDP;
 839                 if (hw->mac.type != e1000_82575)
 840                         scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
 841                 /*
 842                 ** Some new devices, as with ixgbe, now may
 843                 ** use a different BAR, so we need to keep
 844                 ** track of which is used.
 845                 */
 846                 scctx->isc_msix_bar = pci_msix_table_bar(dev);
 847         } else if (hw->mac.type >= em_mac_min) {
 848                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 849                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
 850                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 851                 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
 852                 scctx->isc_txrx = &em_txrx;
 853                 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
 854                 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 855                 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 856                 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS;
 857                 /*
 858                  * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO}
 859                  * by default as we don't have workarounds for all associated
 860                  * silicon errata.  E. g., with several MACs such as 82573E,
 861                  * TSO only works at Gigabit speed and otherwise can cause the
 862                  * hardware to hang (which also would be next to impossible to
 863                  * work around given that already queued TSO-using descriptors
 864                  * would need to be flushed and vlan(4) reconfigured at runtime
 865                  * in case of a link speed change).  Moreover, MACs like 82579
 866                  * still can hang at Gigabit even with all publicly documented
 867                  * TSO workarounds implemented.  Generally, the penality of
 868                  * these workarounds is rather high and may involve copying
 869                  * mbuf data around so advantages of TSO lapse.  Still, TSO may
 870                  * work for a few MACs of this class - at least when sticking
 871                  * with Gigabit - in which case users may enable TSO manually.
 872                  */
 873                 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
 874                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 875                 /*
 876                  * We support MSI-X with 82574 only, but indicate to iflib(4)
 877                  * that it shall give MSI at least a try with other devices.
 878                  */
 879                 if (hw->mac.type == e1000_82574) {
 880                         scctx->isc_msix_bar = pci_msix_table_bar(dev);;
 881                 } else {
 882                         scctx->isc_msix_bar = -1;
 883                         scctx->isc_disable_msix = 1;
 884                 }
 885         } else {
 886                 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 887                 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
 888                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 889                 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
 890                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP;
 891                 scctx->isc_txrx = &lem_txrx;
 892                 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS;
 893                 if (hw->mac.type < e1000_82543)
 894                         scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
 895                 /* INTx only */
 896                 scctx->isc_msix_bar = 0;
 897         }
 898
 899         /* Setup PCI resources */
 900         if (em_allocate_pci_resources(ctx)) {
 901                 device_printf(dev, "Allocation of PCI resources failed\n");
 902                 error = ENXIO;
 903                 goto err_pci;
 904         }
 905
 906         /*
 907         ** For ICH8 and family we need to
 908         ** map the flash memory, and this
 909         ** must happen after the MAC is
 910         ** identified
 911         */
 912         if ((hw->mac.type == e1000_ich8lan) ||
 913             (hw->mac.type == e1000_ich9lan) ||
 914             (hw->mac.type == e1000_ich10lan) ||
 915             (hw->mac.type == e1000_pchlan) ||
 916             (hw->mac.type == e1000_pch2lan) ||
 917             (hw->mac.type == e1000_pch_lpt)) {
 918                 int rid = EM_BAR_TYPE_FLASH;
 919                 adapter->flash = bus_alloc_resource_any(dev,
 920                     SYS_RES_MEMORY, &rid, RF_ACTIVE);
 921                 if (adapter->flash == NULL) {
 922                         device_printf(dev, "Mapping of Flash failed\n");
 923                         error = ENXIO;
 924                         goto err_pci;
 925                 }
 926                 /* This is used in the shared code */
 927                 hw->flash_address = (u8 *)adapter->flash;
 928                 adapter->osdep.flash_bus_space_tag =
 929                     rman_get_bustag(adapter->flash);
 930                 adapter->osdep.flash_bus_space_handle =
 931                     rman_get_bushandle(adapter->flash);
 932         }
 933         /*
 934         ** In the new SPT device flash is not  a
 935         ** separate BAR, rather it is also in BAR0,
 936         ** so use the same tag and an offset handle for the
 937         ** FLASH read/write macros in the shared code.
 938         */
 939         else if (hw->mac.type >= e1000_pch_spt) {
 940                 adapter->osdep.flash_bus_space_tag =
 941                     adapter->osdep.mem_bus_space_tag;
 942                 adapter->osdep.flash_bus_space_handle =
 943                     adapter->osdep.mem_bus_space_handle
 944                     + E1000_FLASH_BASE_ADDR;
 945         }
 946
 947         /* Do Shared Code initialization */
 948         error = e1000_setup_init_funcs(hw, TRUE);
 949         if (error) {
 950                 device_printf(dev, "Setup of Shared code failed, error %d\n",
 951                     error);
 952                 error = ENXIO;
 953                 goto err_pci;
 954         }
 955
 956         em_setup_msix(ctx);
 957         e1000_get_bus_info(hw);
 958
 959         /* Set up some sysctls for the tunable interrupt delays */
 960         em_add_int_delay_sysctl(adapter, "rx_int_delay",
 961             "receive interrupt delay in usecs", &adapter->rx_int_delay,
 962             E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
 963         em_add_int_delay_sysctl(adapter, "tx_int_delay",
 964             "transmit interrupt delay in usecs", &adapter->tx_int_delay,
 965             E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
 966         em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
 967             "receive interrupt delay limit in usecs",
 968             &adapter->rx_abs_int_delay,
 969             E1000_REGISTER(hw, E1000_RADV),
 970             em_rx_abs_int_delay_dflt);
 971         em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
 972             "transmit interrupt delay limit in usecs",
 973             &adapter->tx_abs_int_delay,
 974             E1000_REGISTER(hw, E1000_TADV),
 975             em_tx_abs_int_delay_dflt);
 976         em_add_int_delay_sysctl(adapter, "itr",
 977             "interrupt delay limit in usecs/4",
 978             &adapter->tx_itr,
 979             E1000_REGISTER(hw, E1000_ITR),
 980             DEFAULT_ITR);
 981
 982         hw->mac.autoneg = DO_AUTO_NEG;
 983         hw->phy.autoneg_wait_to_complete = FALSE;
 984         hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 985
 986         if (hw->mac.type < em_mac_min) {
 987                 e1000_init_script_state_82541(hw, TRUE);
 988                 e1000_set_tbi_compatibility_82543(hw, TRUE);
 989         }
 990         /* Copper options */
 991         if (hw->phy.media_type == e1000_media_type_copper) {
 992                 hw->phy.mdix = AUTO_ALL_MODES;
 993                 hw->phy.disable_polarity_correction = FALSE;
 994                 hw->phy.ms_type = EM_MASTER_SLAVE;
 995         }
 996
 997         /*
 998          * Set the frame limits assuming
 999          * standard ethernet sized frames.
1000          */
1001         scctx->isc_max_frame_size = hw->mac.max_frame_size =
1002             ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
1003
1004         /*
1005          * This controls when hardware reports transmit completion
1006          * status.
1007          */
1008         hw->mac.report_tx_early = 1;
1009
1010         /* Allocate multicast array memory. */
1011         adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN *
1012             MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
1013         if (adapter->mta == NULL) {
1014                 device_printf(dev, "Can not allocate multicast setup array\n");
1015                 error = ENOMEM;
1016                 goto err_late;
1017         }
1018
1019         /* Check SOL/IDER usage */
1020         if (e1000_check_reset_block(hw))
1021                 device_printf(dev, "PHY reset is blocked"
1022                               " due to SOL/IDER session.\n");
1023
1024         /* Sysctl for setting Energy Efficient Ethernet */
1025         hw->dev_spec.ich8lan.eee_disable = eee_setting;
1026         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1027             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1028             OID_AUTO, "eee_control",
1029             CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
1030             adapter, 0, em_sysctl_eee, "I",
1031             "Disable Energy Efficient Ethernet");
1032
1033         /*
1034         ** Start from a known state, this is
1035         ** important in reading the nvm and
1036         ** mac from that.
1037         */
1038         e1000_reset_hw(hw);
1039
1040         /* Make sure we have a good EEPROM before we read from it */
1041         if (e1000_validate_nvm_checksum(hw) < 0) {
1042                 /*
1043                 ** Some PCI-E parts fail the first check due to
1044                 ** the link being in sleep state, call it again,
1045                 ** if it fails a second time its a real issue.
1046                 */
1047                 if (e1000_validate_nvm_checksum(hw) < 0) {
1048                         device_printf(dev,
1049                             "The EEPROM Checksum Is Not Valid\n");
1050                         error = EIO;
1051                         goto err_late;
1052                 }
1053         }
1054
1055         /* Copy the permanent MAC address out of the EEPROM */
1056         if (e1000_read_mac_addr(hw) < 0) {
1057                 device_printf(dev, "EEPROM read error while reading MAC"
1058                               " address\n");
1059                 error = EIO;
1060                 goto err_late;
1061         }
1062
1063         if (!em_is_valid_ether_addr(hw->mac.addr)) {
1064                 if (adapter->vf_ifp) {
1065                         u8 addr[ETHER_ADDR_LEN];
1066                         arc4rand(&addr, sizeof(addr), 0);
1067                         addr[0] &= 0xFE;
1068                         addr[0] |= 0x02;
1069                         bcopy(addr, hw->mac.addr, sizeof(addr));
1070                 } else {
1071                         device_printf(dev, "Invalid MAC address\n");
1072                         error = EIO;
1073                         goto err_late;
1074                 }
1075         }
1076
1077         /* Disable ULP support */
1078         e1000_disable_ulp_lpt_lp(hw, TRUE);
1079
1080         /*
1081          * Get Wake-on-Lan and Management info for later use
1082          */
1083         em_get_wakeup(ctx);
1084
1085         /* Enable only WOL MAGIC by default */
1086         scctx->isc_capenable &= ~IFCAP_WOL;
1087         if (adapter->wol != 0)
1088                 scctx->isc_capenable |= IFCAP_WOL_MAGIC;
1089
1090         iflib_set_mac(ctx, hw->mac.addr);
1091
1092         return (0);
1093
1094 err_late:
1095         em_release_hw_control(adapter);
1096 err_pci:
1097         em_free_pci_resources(ctx);
1098         free(adapter->mta, M_DEVBUF);
1099
1100         return (error);
1101 }
1102
1103 static int
1104 em_if_attach_post(if_ctx_t ctx)
1105 {
1106         struct adapter *adapter = iflib_get_softc(ctx);
1107         struct e1000_hw *hw = &adapter->hw;
1108         int error = 0;
1109
1110         /* Setup OS specific network interface */
1111         error = em_setup_interface(ctx);
1112         if (error != 0) {
1113                 device_printf(adapter->dev, "Interface setup failed: %d\n", error);
1114                 goto err_late;
1115         }
1116
1117         em_reset(ctx);
1118
1119         /* Initialize statistics */
1120         em_update_stats_counters(adapter);
1121         hw->mac.get_link_status = 1;
1122         em_if_update_admin_status(ctx);
1123         em_add_hw_stats(adapter);
1124
1125         /* Non-AMT based hardware can now take control from firmware */
1126         if (adapter->has_manage && !adapter->has_amt)
1127                 em_get_hw_control(adapter);
1128
1129         INIT_DEBUGOUT("em_if_attach_post: end");
1130
1131         return (0);
1132
1133 err_late:
1134         /* upon attach_post() error, iflib calls _if_detach() to free resources. */
1135         return (error);
1136 }
1137
1138 /*********************************************************************
1139  *  Device removal routine
1140  *
1141  *  The detach entry point is called when the driver is being removed.
1142  *  This routine stops the adapter and deallocates all the resources
1143  *  that were allocated for driver operation.
1144  *
1145  *  return 0 on success, positive on failure
1146  *********************************************************************/
1147 static int
1148 em_if_detach(if_ctx_t ctx)
1149 {
1150         struct adapter  *adapter = iflib_get_softc(ctx);
1151
1152         INIT_DEBUGOUT("em_if_detach: begin");
1153
1154         e1000_phy_hw_reset(&adapter->hw);
1155
1156         em_release_manageability(adapter);
1157         em_release_hw_control(adapter);
1158         em_free_pci_resources(ctx);
1159         free(adapter->mta, M_DEVBUF);
1160         adapter->mta = NULL;
1161
1162         return (0);
1163 }
1164
1165 /*********************************************************************
1166  *
1167  *  Shutdown entry point
1168  *
1169  **********************************************************************/
1170
1171 static int
1172 em_if_shutdown(if_ctx_t ctx)
1173 {
1174         return em_if_suspend(ctx);
1175 }
1176
1177 /*
1178  * Suspend/resume device methods.
1179  */
1180 static int
1181 em_if_suspend(if_ctx_t ctx)
1182 {
1183         struct adapter *adapter = iflib_get_softc(ctx);
1184
1185         em_release_manageability(adapter);
1186         em_release_hw_control(adapter);
1187         em_enable_wakeup(ctx);
1188         return (0);
1189 }
1190
1191 static int
1192 em_if_resume(if_ctx_t ctx)
1193 {
1194         struct adapter *adapter = iflib_get_softc(ctx);
1195
1196         if (adapter->hw.mac.type == e1000_pch2lan)
1197                 e1000_resume_workarounds_pchlan(&adapter->hw);
1198         em_if_init(ctx);
1199         em_init_manageability(adapter);
1200
1201         return(0);
1202 }
1203
1204 static int
1205 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1206 {
1207         int max_frame_size;
1208         struct adapter *adapter = iflib_get_softc(ctx);
1209         if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1210
1211         IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1212
1213         switch (adapter->hw.mac.type) {
1214         case e1000_82571:
1215         case e1000_82572:
1216         case e1000_ich9lan:
1217         case e1000_ich10lan:
1218         case e1000_pch2lan:
1219         case e1000_pch_lpt:
1220         case e1000_pch_spt:
1221         case e1000_pch_cnp:
1222         case e1000_82574:
1223         case e1000_82583:
1224         case e1000_80003es2lan:
1225                 /* 9K Jumbo Frame size */
1226                 max_frame_size = 9234;
1227                 break;
1228         case e1000_pchlan:
1229                 max_frame_size = 4096;
1230                 break;
1231         case e1000_82542:
1232         case e1000_ich8lan:
1233                 /* Adapters that do not support jumbo frames */
1234                 max_frame_size = ETHER_MAX_LEN;
1235                 break;
1236         default:
1237                 if (adapter->hw.mac.type >= igb_mac_min)
1238                         max_frame_size = 9234;
1239                 else /* lem */
1240                         max_frame_size = MAX_JUMBO_FRAME_SIZE;
1241         }
1242         if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1243                 return (EINVAL);
1244         }
1245
1246         scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
1247             mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1248         return (0);
1249 }
1250
1251 /*********************************************************************
1252  *  Init entry point
1253  *
1254  *  This routine is used in two ways. It is used by the stack as
1255  *  init entry point in network interface structure. It is also used
1256  *  by the driver as a hw/sw initialization routine to get to a
1257  *  consistent state.
1258  *
1259  **********************************************************************/
1260 static void
1261 em_if_init(if_ctx_t ctx)
1262 {
1263         struct adapter *adapter = iflib_get_softc(ctx);
1264         if_softc_ctx_t scctx = adapter->shared;
1265         struct ifnet *ifp = iflib_get_ifp(ctx);
1266         struct em_tx_queue *tx_que;
1267         int i;
1268
1269         INIT_DEBUGOUT("em_if_init: begin");
1270
1271         /* Get the latest mac address, User can use a LAA */
1272         bcopy(if_getlladdr(ifp), adapter->hw.mac.addr,
1273             ETHER_ADDR_LEN);
1274
1275         /* Put the address into the Receive Address Array */
1276         e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1277
1278         /*
1279          * With the 82571 adapter, RAR[0] may be overwritten
1280          * when the other port is reset, we make a duplicate
1281          * in RAR[14] for that eventuality, this assures
1282          * the interface continues to function.
1283          */
1284         if (adapter->hw.mac.type == e1000_82571) {
1285                 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1286                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1287                     E1000_RAR_ENTRIES - 1);
1288         }
1289
1290
1291         /* Initialize the hardware */
1292         em_reset(ctx);
1293         em_if_update_admin_status(ctx);
1294
1295         for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) {
1296                 struct tx_ring *txr = &tx_que->txr;
1297
1298                 txr->tx_rs_cidx = txr->tx_rs_pidx;
1299
1300                 /* Initialize the last processed descriptor to be the end of
1301                  * the ring, rather than the start, so that we avoid an
1302                  * off-by-one error when calculating how many descriptors are
1303                  * done in the credits_update function.
1304                  */
1305                 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
1306         }
1307
1308         /* Setup VLAN support, basic and offload if available */
1309         E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1310
1311         /* Clear bad data from Rx FIFOs */
1312         if (adapter->hw.mac.type >= igb_mac_min)
1313                 e1000_rx_fifo_flush_82575(&adapter->hw);
1314
1315         /* Configure for OS presence */
1316         em_init_manageability(adapter);
1317
1318         /* Prepare transmit descriptors and buffers */
1319         em_initialize_transmit_unit(ctx);
1320
1321         /* Setup Multicast table */
1322         em_if_multi_set(ctx);
1323
1324         adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx);
1325         em_initialize_receive_unit(ctx);
1326
1327         /* Use real VLAN Filter support? */
1328         if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1329                 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
1330                         /* Use real VLAN Filter support */
1331                         em_setup_vlan_hw_support(adapter);
1332                 else {
1333                         u32 ctrl;
1334                         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1335                         ctrl |= E1000_CTRL_VME;
1336                         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1337                 }
1338         } else {
1339                 u32 ctrl;
1340                 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1341                 ctrl &= ~E1000_CTRL_VME;
1342                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1343         }
1344
1345         /* Don't lose promiscuous settings */
1346         em_if_set_promisc(ctx, if_getflags(ifp));
1347         e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1348
1349         /* MSI-X configuration for 82574 */
1350         if (adapter->hw.mac.type == e1000_82574) {
1351                 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1352
1353                 tmp |= E1000_CTRL_EXT_PBA_CLR;
1354                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1355                 /* Set the IVAR - interrupt vector routing. */
1356                 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars);
1357         } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1358                 igb_configure_queues(adapter);
1359
1360         /* this clears any pending interrupts */
1361         E1000_READ_REG(&adapter->hw, E1000_ICR);
1362         E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC);
1363
1364         /* AMT based hardware can now take control from firmware */
1365         if (adapter->has_manage && adapter->has_amt)
1366                 em_get_hw_control(adapter);
1367
1368         /* Set Energy Efficient Ethernet */
1369         if (adapter->hw.mac.type >= igb_mac_min &&
1370             adapter->hw.phy.media_type == e1000_media_type_copper) {
1371                 if (adapter->hw.mac.type == e1000_i354)
1372                         e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
1373                 else
1374                         e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
1375         }
1376 }
1377
1378 /*********************************************************************
1379  *
1380  *  Fast Legacy/MSI Combined Interrupt Service routine
1381  *
1382  *********************************************************************/
1383 int
1384 em_intr(void *arg)
1385 {
1386         struct adapter *adapter = arg;
1387         if_ctx_t ctx = adapter->ctx;
1388         u32 reg_icr;
1389
1390         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1391
1392         /* Hot eject? */
1393         if (reg_icr == 0xffffffff)
1394                 return FILTER_STRAY;
1395
1396         /* Definitely not our interrupt. */
1397         if (reg_icr == 0x0)
1398                 return FILTER_STRAY;
1399
1400         /*
1401          * Starting with the 82571 chip, bit 31 should be used to
1402          * determine whether the interrupt belongs to us.
1403          */
1404         if (adapter->hw.mac.type >= e1000_82571 &&
1405             (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1406                 return FILTER_STRAY;
1407
1408         /*
1409          * Only MSI-X interrupts have one-shot behavior by taking advantage
1410          * of the EIAC register.  Thus, explicitly disable interrupts.  This
1411          * also works around the MSI message reordering errata on certain
1412          * systems.
1413          */
1414         IFDI_INTR_DISABLE(ctx);
1415
1416         /* Link status change */
1417         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))
1418                 em_handle_link(ctx);
1419
1420         if (reg_icr & E1000_ICR_RXO)
1421                 adapter->rx_overruns++;
1422
1423         return (FILTER_SCHEDULE_THREAD);
1424 }
1425
1426 static int
1427 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1428 {
1429         struct adapter *adapter = iflib_get_softc(ctx);
1430         struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1431
1432         E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims);
1433         return (0);
1434 }
1435
1436 static int
1437 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1438 {
1439         struct adapter *adapter = iflib_get_softc(ctx);
1440         struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1441
1442         E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims);
1443         return (0);
1444 }
1445
1446 static int
1447 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1448 {
1449         struct adapter *adapter = iflib_get_softc(ctx);
1450         struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1451
1452         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims);
1453         return (0);
1454 }
1455
1456 static int
1457 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1458 {
1459         struct adapter *adapter = iflib_get_softc(ctx);
1460         struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1461
1462         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims);
1463         return (0);
1464 }
1465
1466 /*********************************************************************
1467  *
1468  *  MSI-X RX Interrupt Service routine
1469  *
1470  **********************************************************************/
1471 static int
1472 em_msix_que(void *arg)
1473 {
1474         struct em_rx_queue *que = arg;
1475
1476         ++que->irqs;
1477
1478         return (FILTER_SCHEDULE_THREAD);
1479 }
1480
1481 /*********************************************************************
1482  *
1483  *  MSI-X Link Fast Interrupt Service routine
1484  *
1485  **********************************************************************/
1486 static int
1487 em_msix_link(void *arg)
1488 {
1489         struct adapter *adapter = arg;
1490         u32 reg_icr;
1491
1492         ++adapter->link_irq;
1493         MPASS(adapter->hw.back != NULL);
1494         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1495
1496         if (reg_icr & E1000_ICR_RXO)
1497                 adapter->rx_overruns++;
1498
1499         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1500                 em_handle_link(adapter->ctx);
1501         } else if (adapter->hw.mac.type == e1000_82574) {
1502                 /* Only re-arm 82574 if em_if_update_admin_status() won't. */
1503                 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK |
1504                     E1000_IMS_LSC);
1505         }
1506
1507         if (adapter->hw.mac.type == e1000_82574) {
1508                 /*
1509                  * Because we must read the ICR for this interrupt it may
1510                  * clear other causes using autoclear, for this reason we
1511                  * simply create a soft interrupt for all these vectors.
1512                  */
1513                 if (reg_icr)
1514                         E1000_WRITE_REG(&adapter->hw, E1000_ICS, adapter->ims);
1515         } else {
1516                 /* Re-arm unconditionally */
1517                 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC);
1518                 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1519         }
1520
1521         return (FILTER_HANDLED);
1522 }
1523
1524 static void
1525 em_handle_link(void *context)
1526 {
1527         if_ctx_t ctx = context;
1528         struct adapter *adapter = iflib_get_softc(ctx);
1529
1530         adapter->hw.mac.get_link_status = 1;
1531         iflib_admin_intr_deferred(ctx);
1532 }
1533
1534 /*********************************************************************
1535  *
1536  *  Media Ioctl callback
1537  *
1538  *  This routine is called whenever the user queries the status of
1539  *  the interface using ifconfig.
1540  *
1541  **********************************************************************/
1542 static void
1543 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1544 {
1545         struct adapter *adapter = iflib_get_softc(ctx);
1546         u_char fiber_type = IFM_1000_SX;
1547
1548         INIT_DEBUGOUT("em_if_media_status: begin");
1549
1550         iflib_admin_intr_deferred(ctx);
1551
1552         ifmr->ifm_status = IFM_AVALID;
1553         ifmr->ifm_active = IFM_ETHER;
1554
1555         if (!adapter->link_active) {
1556                 return;
1557         }
1558
1559         ifmr->ifm_status |= IFM_ACTIVE;
1560
1561         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
1562             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1563                 if (adapter->hw.mac.type == e1000_82545)
1564                         fiber_type = IFM_1000_LX;
1565                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1566         } else {
1567                 switch (adapter->link_speed) {
1568                 case 10:
1569                         ifmr->ifm_active |= IFM_10_T;
1570                         break;
1571                 case 100:
1572                         ifmr->ifm_active |= IFM_100_TX;
1573                         break;
1574                 case 1000:
1575                         ifmr->ifm_active |= IFM_1000_T;
1576                         break;
1577                 }
1578                 if (adapter->link_duplex == FULL_DUPLEX)
1579                         ifmr->ifm_active |= IFM_FDX;
1580                 else
1581                         ifmr->ifm_active |= IFM_HDX;
1582         }
1583 }
1584
1585 /*********************************************************************
1586  *
1587  *  Media Ioctl callback
1588  *
1589  *  This routine is called when the user changes speed/duplex using
1590  *  media/mediopt option with ifconfig.
1591  *
1592  **********************************************************************/
1593 static int
1594 em_if_media_change(if_ctx_t ctx)
1595 {
1596         struct adapter *adapter = iflib_get_softc(ctx);
1597         struct ifmedia *ifm = iflib_get_media(ctx);
1598
1599         INIT_DEBUGOUT("em_if_media_change: begin");
1600
1601         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1602                 return (EINVAL);
1603
1604         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1605         case IFM_AUTO:
1606                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1607                 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1608                 break;
1609         case IFM_1000_LX:
1610         case IFM_1000_SX:
1611         case IFM_1000_T:
1612                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1613                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1614                 break;
1615         case IFM_100_TX:
1616                 adapter->hw.mac.autoneg = FALSE;
1617                 adapter->hw.phy.autoneg_advertised = 0;
1618                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1619                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1620                 else
1621                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1622                 break;
1623         case IFM_10_T:
1624                 adapter->hw.mac.autoneg = FALSE;
1625                 adapter->hw.phy.autoneg_advertised = 0;
1626                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1627                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1628                 else
1629                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1630                 break;
1631         default:
1632                 device_printf(adapter->dev, "Unsupported media type\n");
1633         }
1634
1635         em_if_init(ctx);
1636
1637         return (0);
1638 }
1639
1640 static int
1641 em_if_set_promisc(if_ctx_t ctx, int flags)
1642 {
1643         struct adapter *adapter = iflib_get_softc(ctx);
1644         u32 reg_rctl;
1645
1646         em_disable_promisc(ctx);
1647
1648         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1649
1650         if (flags & IFF_PROMISC) {
1651                 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1652                 /* Turn this on if you want to see bad packets */
1653                 if (em_debug_sbp)
1654                         reg_rctl |= E1000_RCTL_SBP;
1655                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1656         } else if (flags & IFF_ALLMULTI) {
1657                 reg_rctl |= E1000_RCTL_MPE;
1658                 reg_rctl &= ~E1000_RCTL_UPE;
1659                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1660         }
1661         return (0);
1662 }
1663
1664 static void
1665 em_disable_promisc(if_ctx_t ctx)
1666 {
1667         struct adapter *adapter = iflib_get_softc(ctx);
1668         struct ifnet *ifp = iflib_get_ifp(ctx);
1669         u32 reg_rctl;
1670         int mcnt = 0;
1671
1672         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1673         reg_rctl &= (~E1000_RCTL_UPE);
1674         if (if_getflags(ifp) & IFF_ALLMULTI)
1675                 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1676         else
1677                 mcnt = if_llmaddr_count(ifp);
1678         /* Don't disable if in MAX groups */
1679         if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1680                 reg_rctl &=  (~E1000_RCTL_MPE);
1681         reg_rctl &=  (~E1000_RCTL_SBP);
1682         E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1683 }
1684
1685
1686 static u_int
1687 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1688 {
1689         u8 *mta = arg;
1690
1691         if (cnt == MAX_NUM_MULTICAST_ADDRESSES)
1692                 return (1);
1693
1694         bcopy(LLADDR(sdl), &mta[cnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1695
1696         return (1);
1697 }
1698
1699 /*********************************************************************
1700  *  Multicast Update
1701  *
1702  *  This routine is called whenever multicast address list is updated.
1703  *
1704  **********************************************************************/
1705
1706 static void
1707 em_if_multi_set(if_ctx_t ctx)
1708 {
1709         struct adapter *adapter = iflib_get_softc(ctx);
1710         struct ifnet *ifp = iflib_get_ifp(ctx);
1711         u32 reg_rctl = 0;
1712         u8  *mta; /* Multicast array memory */
1713         int mcnt = 0;
1714
1715         IOCTL_DEBUGOUT("em_set_multi: begin");
1716
1717         mta = adapter->mta;
1718         bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1719
1720         if (adapter->hw.mac.type == e1000_82542 &&
1721             adapter->hw.revision_id == E1000_REVISION_2) {
1722                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1723                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1724                         e1000_pci_clear_mwi(&adapter->hw);
1725                 reg_rctl |= E1000_RCTL_RST;
1726                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1727                 msec_delay(5);
1728         }
1729
1730         mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta);
1731
1732         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1733                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1734                 reg_rctl |= E1000_RCTL_MPE;
1735                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1736         } else
1737                 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
1738
1739         if (adapter->hw.mac.type == e1000_82542 &&
1740             adapter->hw.revision_id == E1000_REVISION_2) {
1741                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1742                 reg_rctl &= ~E1000_RCTL_RST;
1743                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1744                 msec_delay(5);
1745                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1746                         e1000_pci_set_mwi(&adapter->hw);
1747         }
1748 }
1749
1750 /*********************************************************************
1751  *  Timer routine
1752  *
1753  *  This routine schedules em_if_update_admin_status() to check for
1754  *  link status and to gather statistics as well as to perform some
1755  *  controller-specific hardware patting.
1756  *
1757  **********************************************************************/
1758 static void
1759 em_if_timer(if_ctx_t ctx, uint16_t qid)
1760 {
1761
1762         if (qid != 0)
1763                 return;
1764
1765         iflib_admin_intr_deferred(ctx);
1766 }
1767
1768 static void
1769 em_if_update_admin_status(if_ctx_t ctx)
1770 {
1771         struct adapter *adapter = iflib_get_softc(ctx);
1772         struct e1000_hw *hw = &adapter->hw;
1773         device_t dev = iflib_get_dev(ctx);
1774         u32 link_check, thstat, ctrl;
1775
1776         link_check = thstat = ctrl = 0;
1777         /* Get the cached link value or read phy for real */
1778         switch (hw->phy.media_type) {
1779         case e1000_media_type_copper:
1780                 if (hw->mac.get_link_status) {
1781                         if (hw->mac.type == e1000_pch_spt)
1782                                 msec_delay(50);
1783                         /* Do the work to read phy */
1784                         e1000_check_for_link(hw);
1785                         link_check = !hw->mac.get_link_status;
1786                         if (link_check) /* ESB2 fix */
1787                                 e1000_cfg_on_link_up(hw);
1788                 } else {
1789                         link_check = TRUE;
1790                 }
1791                 break;
1792         case e1000_media_type_fiber:
1793                 e1000_check_for_link(hw);
1794                 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1795                             E1000_STATUS_LU);
1796                 break;
1797         case e1000_media_type_internal_serdes:
1798                 e1000_check_for_link(hw);
1799                 link_check = hw->mac.serdes_has_link;
1800                 break;
1801         /* VF device is type_unknown */
1802         case e1000_media_type_unknown:
1803                 e1000_check_for_link(hw);
1804                 link_check = !hw->mac.get_link_status;
1805                 /* FALLTHROUGH */
1806         default:
1807                 break;
1808         }
1809
1810         /* Check for thermal downshift or shutdown */
1811         if (hw->mac.type == e1000_i350) {
1812                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1813                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1814         }
1815
1816         /* Now check for a transition */
1817         if (link_check && (adapter->link_active == 0)) {
1818                 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
1819                     &adapter->link_duplex);
1820                 /* Check if we must disable SPEED_MODE bit on PCI-E */
1821                 if ((adapter->link_speed != SPEED_1000) &&
1822                     ((hw->mac.type == e1000_82571) ||
1823                     (hw->mac.type == e1000_82572))) {
1824                         int tarc0;
1825                         tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1826                         tarc0 &= ~TARC_SPEED_MODE_BIT;
1827                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1828                 }
1829                 if (bootverbose)
1830                         device_printf(dev, "Link is up %d Mbps %s\n",
1831                             adapter->link_speed,
1832                             ((adapter->link_duplex == FULL_DUPLEX) ?
1833                             "Full Duplex" : "Half Duplex"));
1834                 adapter->link_active = 1;
1835                 adapter->smartspeed = 0;
1836                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) ==
1837                     E1000_CTRL_EXT_LINK_MODE_GMII &&
1838                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1839                         device_printf(dev, "Link: thermal downshift\n");
1840                 /* Delay Link Up for Phy update */
1841                 if (((hw->mac.type == e1000_i210) ||
1842                     (hw->mac.type == e1000_i211)) &&
1843                     (hw->phy.id == I210_I_PHY_ID))
1844                         msec_delay(I210_LINK_DELAY);
1845                 /* Reset if the media type changed. */
1846                 if (hw->dev_spec._82575.media_changed &&
1847                     hw->mac.type >= igb_mac_min) {
1848                         hw->dev_spec._82575.media_changed = false;
1849                         adapter->flags |= IGB_MEDIA_RESET;
1850                         em_reset(ctx);
1851                 }
1852                 iflib_link_state_change(ctx, LINK_STATE_UP,
1853                     IF_Mbps(adapter->link_speed));
1854         } else if (!link_check && (adapter->link_active == 1)) {
1855                 adapter->link_speed = 0;
1856                 adapter->link_duplex = 0;
1857                 adapter->link_active = 0;
1858                 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
1859         }
1860         em_update_stats_counters(adapter);
1861
1862         /* Reset LAA into RAR[0] on 82571 */
1863         if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw))
1864                 e1000_rar_set(hw, hw->mac.addr, 0);
1865
1866         if (hw->mac.type < em_mac_min)
1867                 lem_smartspeed(adapter);
1868         else if (hw->mac.type == e1000_82574 &&
1869             adapter->intr_type == IFLIB_INTR_MSIX)
1870                 E1000_WRITE_REG(hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC);
1871 }
1872
1873 static void
1874 em_if_watchdog_reset(if_ctx_t ctx)
1875 {
1876         struct adapter *adapter = iflib_get_softc(ctx);
1877
1878         /*
1879          * Just count the event; iflib(4) will already trigger a
1880          * sufficient reset of the controller.
1881          */
1882         adapter->watchdog_events++;
1883 }
1884
1885 /*********************************************************************
1886  *
1887  *  This routine disables all traffic on the adapter by issuing a
1888  *  global reset on the MAC.
1889  *
1890  **********************************************************************/
1891 static void
1892 em_if_stop(if_ctx_t ctx)
1893 {
1894         struct adapter *adapter = iflib_get_softc(ctx);
1895
1896         INIT_DEBUGOUT("em_if_stop: begin");
1897
1898         e1000_reset_hw(&adapter->hw);
1899         if (adapter->hw.mac.type >= e1000_82544)
1900                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0);
1901
1902         e1000_led_off(&adapter->hw);
1903         e1000_cleanup_led(&adapter->hw);
1904 }
1905
1906 /*********************************************************************
1907  *
1908  *  Determine hardware revision.
1909  *
1910  **********************************************************************/
1911 static void
1912 em_identify_hardware(if_ctx_t ctx)
1913 {
1914         device_t dev = iflib_get_dev(ctx);
1915         struct adapter *adapter = iflib_get_softc(ctx);
1916
1917         /* Make sure our PCI config space has the necessary stuff set */
1918         adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1919
1920         /* Save off the information about this board */
1921         adapter->hw.vendor_id = pci_get_vendor(dev);
1922         adapter->hw.device_id = pci_get_device(dev);
1923         adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1924         adapter->hw.subsystem_vendor_id =
1925             pci_read_config(dev, PCIR_SUBVEND_0, 2);
1926         adapter->hw.subsystem_device_id =
1927             pci_read_config(dev, PCIR_SUBDEV_0, 2);
1928
1929         /* Do Shared Code Init and Setup */
1930         if (e1000_set_mac_type(&adapter->hw)) {
1931                 device_printf(dev, "Setup init failure\n");
1932                 return;
1933         }
1934
1935         /* Are we a VF device? */
1936         if ((adapter->hw.mac.type == e1000_vfadapt) ||
1937             (adapter->hw.mac.type == e1000_vfadapt_i350))
1938                 adapter->vf_ifp = 1;
1939         else
1940                 adapter->vf_ifp = 0;
1941 }
1942
1943 static int
1944 em_allocate_pci_resources(if_ctx_t ctx)
1945 {
1946         struct adapter *adapter = iflib_get_softc(ctx);
1947         device_t dev = iflib_get_dev(ctx);
1948         int rid, val;
1949
1950         rid = PCIR_BAR(0);
1951         adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1952             &rid, RF_ACTIVE);
1953         if (adapter->memory == NULL) {
1954                 device_printf(dev, "Unable to allocate bus resource: memory\n");
1955                 return (ENXIO);
1956         }
1957         adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory);
1958         adapter->osdep.mem_bus_space_handle =
1959             rman_get_bushandle(adapter->memory);
1960         adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle;
1961
1962         /* Only older adapters use IO mapping */
1963         if (adapter->hw.mac.type < em_mac_min &&
1964             adapter->hw.mac.type > e1000_82543) {
1965                 /* Figure our where our IO BAR is ? */
1966                 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1967                         val = pci_read_config(dev, rid, 4);
1968                         if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1969                                 break;
1970                         }
1971                         rid += 4;
1972                         /* check for 64bit BAR */
1973                         if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1974                                 rid += 4;
1975                 }
1976                 if (rid >= PCIR_CIS) {
1977                         device_printf(dev, "Unable to locate IO BAR\n");
1978                         return (ENXIO);
1979                 }
1980                 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
1981                     &rid, RF_ACTIVE);
1982                 if (adapter->ioport == NULL) {
1983                         device_printf(dev, "Unable to allocate bus resource: "
1984                             "ioport\n");
1985                         return (ENXIO);
1986                 }
1987                 adapter->hw.io_base = 0;
1988                 adapter->osdep.io_bus_space_tag =
1989                     rman_get_bustag(adapter->ioport);
1990                 adapter->osdep.io_bus_space_handle =
1991                     rman_get_bushandle(adapter->ioport);
1992         }
1993
1994         adapter->hw.back = &adapter->osdep;
1995
1996         return (0);
1997 }
1998
1999 /*********************************************************************
2000  *
2001  *  Set up the MSI-X Interrupt handlers
2002  *
2003  **********************************************************************/
2004 static int
2005 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
2006 {
2007         struct adapter *adapter = iflib_get_softc(ctx);
2008         struct em_rx_queue *rx_que = adapter->rx_queues;
2009         struct em_tx_queue *tx_que = adapter->tx_queues;
2010         int error, rid, i, vector = 0, rx_vectors;
2011         char buf[16];
2012
2013         /* First set up ring resources */
2014         for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) {
2015                 rid = vector + 1;
2016                 snprintf(buf, sizeof(buf), "rxq%d", i);
2017                 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
2018                 if (error) {
2019                         device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
2020                         adapter->rx_num_queues = i + 1;
2021                         goto fail;
2022                 }
2023
2024                 rx_que->msix =  vector;
2025
2026                 /*
2027                  * Set the bit to enable interrupt
2028                  * in E1000_IMS -- bits 20 and 21
2029                  * are for RX0 and RX1, note this has
2030                  * NOTHING to do with the MSI-X vector
2031                  */
2032                 if (adapter->hw.mac.type == e1000_82574) {
2033                         rx_que->eims = 1 << (20 + i);
2034                         adapter->ims |= rx_que->eims;
2035                         adapter->ivars |= (8 | rx_que->msix) << (i * 4);
2036                 } else if (adapter->hw.mac.type == e1000_82575)
2037                         rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
2038                 else
2039                         rx_que->eims = 1 << vector;
2040         }
2041         rx_vectors = vector;
2042
2043         vector = 0;
2044         for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) {
2045                 snprintf(buf, sizeof(buf), "txq%d", i);
2046                 tx_que = &adapter->tx_queues[i];
2047                 iflib_softirq_alloc_generic(ctx,
2048                     &adapter->rx_queues[i % adapter->rx_num_queues].que_irq,
2049                     IFLIB_INTR_TX, tx_que, tx_que->me, buf);
2050
2051                 tx_que->msix = (vector % adapter->rx_num_queues);
2052
2053                 /*
2054                  * Set the bit to enable interrupt
2055                  * in E1000_IMS -- bits 22 and 23
2056                  * are for TX0 and TX1, note this has
2057                  * NOTHING to do with the MSI-X vector
2058                  */
2059                 if (adapter->hw.mac.type == e1000_82574) {
2060                         tx_que->eims = 1 << (22 + i);
2061                         adapter->ims |= tx_que->eims;
2062                         adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
2063                 } else if (adapter->hw.mac.type == e1000_82575) {
2064                         tx_que->eims = E1000_EICR_TX_QUEUE0 << i;
2065                 } else {
2066                         tx_que->eims = 1 << i;
2067                 }
2068         }
2069
2070         /* Link interrupt */
2071         rid = rx_vectors + 1;
2072         error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq");
2073
2074         if (error) {
2075                 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
2076                 goto fail;
2077         }
2078         adapter->linkvec = rx_vectors;
2079         if (adapter->hw.mac.type < igb_mac_min) {
2080                 adapter->ivars |=  (8 | rx_vectors) << 16;
2081                 adapter->ivars |= 0x80000000;
2082         }
2083         return (0);
2084 fail:
2085         iflib_irq_free(ctx, &adapter->irq);
2086         rx_que = adapter->rx_queues;
2087         for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++)
2088                 iflib_irq_free(ctx, &rx_que->que_irq);
2089         return (error);
2090 }
2091
2092 static void
2093 igb_configure_queues(struct adapter *adapter)
2094 {
2095         struct e1000_hw *hw = &adapter->hw;
2096         struct em_rx_queue *rx_que;
2097         struct em_tx_queue *tx_que;
2098         u32 tmp, ivar = 0, newitr = 0;
2099
2100         /* First turn on RSS capability */
2101         if (hw->mac.type != e1000_82575)
2102                 E1000_WRITE_REG(hw, E1000_GPIE,
2103                     E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
2104                     E1000_GPIE_PBA | E1000_GPIE_NSICR);
2105
2106         /* Turn on MSI-X */
2107         switch (hw->mac.type) {
2108         case e1000_82580:
2109         case e1000_i350:
2110         case e1000_i354:
2111         case e1000_i210:
2112         case e1000_i211:
2113         case e1000_vfadapt:
2114         case e1000_vfadapt_i350:
2115                 /* RX entries */
2116                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2117                         u32 index = i >> 1;
2118                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2119                         rx_que = &adapter->rx_queues[i];
2120                         if (i & 1) {
2121                                 ivar &= 0xFF00FFFF;
2122                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2123                         } else {
2124                                 ivar &= 0xFFFFFF00;
2125                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2126                         }
2127                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2128                 }
2129                 /* TX entries */
2130                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2131                         u32 index = i >> 1;
2132                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2133                         tx_que = &adapter->tx_queues[i];
2134                         if (i & 1) {
2135                                 ivar &= 0x00FFFFFF;
2136                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2137                         } else {
2138                                 ivar &= 0xFFFF00FF;
2139                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2140                         }
2141                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2142                         adapter->que_mask |= tx_que->eims;
2143                 }
2144
2145                 /* And for the link interrupt */
2146                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2147                 adapter->link_mask = 1 << adapter->linkvec;
2148                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2149                 break;
2150         case e1000_82576:
2151                 /* RX entries */
2152                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2153                         u32 index = i & 0x7; /* Each IVAR has two entries */
2154                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2155                         rx_que = &adapter->rx_queues[i];
2156                         if (i < 8) {
2157                                 ivar &= 0xFFFFFF00;
2158                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2159                         } else {
2160                                 ivar &= 0xFF00FFFF;
2161                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2162                         }
2163                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2164                         adapter->que_mask |= rx_que->eims;
2165                 }
2166                 /* TX entries */
2167                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2168                         u32 index = i & 0x7; /* Each IVAR has two entries */
2169                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2170                         tx_que = &adapter->tx_queues[i];
2171                         if (i < 8) {
2172                                 ivar &= 0xFFFF00FF;
2173                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2174                         } else {
2175                                 ivar &= 0x00FFFFFF;
2176                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2177                         }
2178                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2179                         adapter->que_mask |= tx_que->eims;
2180                 }
2181
2182                 /* And for the link interrupt */
2183                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2184                 adapter->link_mask = 1 << adapter->linkvec;
2185                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2186                 break;
2187
2188         case e1000_82575:
2189                 /* enable MSI-X support*/
2190                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2191                 tmp |= E1000_CTRL_EXT_PBA_CLR;
2192                 /* Auto-Mask interrupts upon ICR read. */
2193                 tmp |= E1000_CTRL_EXT_EIAME;
2194                 tmp |= E1000_CTRL_EXT_IRCA;
2195                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2196
2197                 /* Queues */
2198                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2199                         rx_que = &adapter->rx_queues[i];
2200                         tmp = E1000_EICR_RX_QUEUE0 << i;
2201                         tmp |= E1000_EICR_TX_QUEUE0 << i;
2202                         rx_que->eims = tmp;
2203                         E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2204                             i, rx_que->eims);
2205                         adapter->que_mask |= rx_que->eims;
2206                 }
2207
2208                 /* Link */
2209                 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec),
2210                     E1000_EIMS_OTHER);
2211                 adapter->link_mask |= E1000_EIMS_OTHER;
2212         default:
2213                 break;
2214         }
2215
2216         /* Set the starting interrupt rate */
2217         if (em_max_interrupt_rate > 0)
2218                 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2219
2220         if (hw->mac.type == e1000_82575)
2221                 newitr |= newitr << 16;
2222         else
2223                 newitr |= E1000_EITR_CNT_IGNR;
2224
2225         for (int i = 0; i < adapter->rx_num_queues; i++) {
2226                 rx_que = &adapter->rx_queues[i];
2227                 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2228         }
2229
2230         return;
2231 }
2232
2233 static void
2234 em_free_pci_resources(if_ctx_t ctx)
2235 {
2236         struct adapter *adapter = iflib_get_softc(ctx);
2237         struct em_rx_queue *que = adapter->rx_queues;
2238         device_t dev = iflib_get_dev(ctx);
2239
2240         /* Release all MSI-X queue resources */
2241         if (adapter->intr_type == IFLIB_INTR_MSIX)
2242                 iflib_irq_free(ctx, &adapter->irq);
2243
2244         if (que != NULL) {
2245                 for (int i = 0; i < adapter->rx_num_queues; i++, que++) {
2246                         iflib_irq_free(ctx, &que->que_irq);
2247                 }
2248         }
2249
2250         if (adapter->memory != NULL) {
2251                 bus_release_resource(dev, SYS_RES_MEMORY,
2252                     rman_get_rid(adapter->memory), adapter->memory);
2253                 adapter->memory = NULL;
2254         }
2255
2256         if (adapter->flash != NULL) {
2257                 bus_release_resource(dev, SYS_RES_MEMORY,
2258                     rman_get_rid(adapter->flash), adapter->flash);
2259                 adapter->flash = NULL;
2260         }
2261
2262         if (adapter->ioport != NULL) {
2263                 bus_release_resource(dev, SYS_RES_IOPORT,
2264                     rman_get_rid(adapter->ioport), adapter->ioport);
2265                 adapter->ioport = NULL;
2266         }
2267 }
2268
2269 /* Set up MSI or MSI-X */
2270 static int
2271 em_setup_msix(if_ctx_t ctx)
2272 {
2273         struct adapter *adapter = iflib_get_softc(ctx);
2274
2275         if (adapter->hw.mac.type == e1000_82574) {
2276                 em_enable_vectors_82574(ctx);
2277         }
2278         return (0);
2279 }
2280
2281 /*********************************************************************
2282  *
2283  *  Workaround for SmartSpeed on 82541 and 82547 controllers
2284  *
2285  **********************************************************************/
2286 static void
2287 lem_smartspeed(struct adapter *adapter)
2288 {
2289         u16 phy_tmp;
2290
2291         if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) ||
2292             adapter->hw.mac.autoneg == 0 ||
2293             (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2294                 return;
2295
2296         if (adapter->smartspeed == 0) {
2297                 /* If Master/Slave config fault is asserted twice,
2298                  * we assume back-to-back */
2299                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2300                 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2301                         return;
2302                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2303                 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2304                         e1000_read_phy_reg(&adapter->hw,
2305                             PHY_1000T_CTRL, &phy_tmp);
2306                         if(phy_tmp & CR_1000T_MS_ENABLE) {
2307                                 phy_tmp &= ~CR_1000T_MS_ENABLE;
2308                                 e1000_write_phy_reg(&adapter->hw,
2309                                     PHY_1000T_CTRL, phy_tmp);
2310                                 adapter->smartspeed++;
2311                                 if(adapter->hw.mac.autoneg &&
2312                                    !e1000_copper_link_autoneg(&adapter->hw) &&
2313                                    !e1000_read_phy_reg(&adapter->hw,
2314                                     PHY_CONTROL, &phy_tmp)) {
2315                                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2316                                                     MII_CR_RESTART_AUTO_NEG);
2317                                         e1000_write_phy_reg(&adapter->hw,
2318                                             PHY_CONTROL, phy_tmp);
2319                                 }
2320                         }
2321                 }
2322                 return;
2323         } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2324                 /* If still no link, perhaps using 2/3 pair cable */
2325                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2326                 phy_tmp |= CR_1000T_MS_ENABLE;
2327                 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2328                 if(adapter->hw.mac.autoneg &&
2329                    !e1000_copper_link_autoneg(&adapter->hw) &&
2330                    !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2331                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2332                                     MII_CR_RESTART_AUTO_NEG);
2333                         e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2334                 }
2335         }
2336         /* Restart process after EM_SMARTSPEED_MAX iterations */
2337         if(adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2338                 adapter->smartspeed = 0;
2339 }
2340
2341 /*********************************************************************
2342  *
2343  *  Initialize the DMA Coalescing feature
2344  *
2345  **********************************************************************/
2346 static void
2347 igb_init_dmac(struct adapter *adapter, u32 pba)
2348 {
2349         device_t        dev = adapter->dev;
2350         struct e1000_hw *hw = &adapter->hw;
2351         u32             dmac, reg = ~E1000_DMACR_DMAC_EN;
2352         u16             hwm;
2353         u16             max_frame_size;
2354
2355         if (hw->mac.type == e1000_i211)
2356                 return;
2357
2358         max_frame_size = adapter->shared->isc_max_frame_size;
2359         if (hw->mac.type > e1000_82580) {
2360
2361                 if (adapter->dmac == 0) { /* Disabling it */
2362                         E1000_WRITE_REG(hw, E1000_DMACR, reg);
2363                         return;
2364                 } else
2365                         device_printf(dev, "DMA Coalescing enabled\n");
2366
2367                 /* Set starting threshold */
2368                 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
2369
2370                 hwm = 64 * pba - max_frame_size / 16;
2371                 if (hwm < 64 * (pba - 6))
2372                         hwm = 64 * (pba - 6);
2373                 reg = E1000_READ_REG(hw, E1000_FCRTC);
2374                 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
2375                 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
2376                     & E1000_FCRTC_RTH_COAL_MASK);
2377                 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
2378
2379
2380                 dmac = pba - max_frame_size / 512;
2381                 if (dmac < pba - 10)
2382                         dmac = pba - 10;
2383                 reg = E1000_READ_REG(hw, E1000_DMACR);
2384                 reg &= ~E1000_DMACR_DMACTHR_MASK;
2385                 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT)
2386                     & E1000_DMACR_DMACTHR_MASK);
2387
2388                 /* transition to L0x or L1 if available..*/
2389                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
2390
2391                 /* Check if status is 2.5Gb backplane connection
2392                 * before configuration of watchdog timer, which is
2393                 * in msec values in 12.8usec intervals
2394                 * watchdog timer= msec values in 32usec intervals
2395                 * for non 2.5Gb connection
2396                 */
2397                 if (hw->mac.type == e1000_i354) {
2398                         int status = E1000_READ_REG(hw, E1000_STATUS);
2399                         if ((status & E1000_STATUS_2P5_SKU) &&
2400                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2401                                 reg |= ((adapter->dmac * 5) >> 6);
2402                         else
2403                                 reg |= (adapter->dmac >> 5);
2404                 } else {
2405                         reg |= (adapter->dmac >> 5);
2406                 }
2407
2408                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2409
2410                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
2411
2412                 /* Set the interval before transition */
2413                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
2414                 if (hw->mac.type == e1000_i350)
2415                         reg |= IGB_DMCTLX_DCFLUSH_DIS;
2416                 /*
2417                 ** in 2.5Gb connection, TTLX unit is 0.4 usec
2418                 ** which is 0x4*2 = 0xA. But delay is still 4 usec
2419                 */
2420                 if (hw->mac.type == e1000_i354) {
2421                         int status = E1000_READ_REG(hw, E1000_STATUS);
2422                         if ((status & E1000_STATUS_2P5_SKU) &&
2423                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2424                                 reg |= 0xA;
2425                         else
2426                                 reg |= 0x4;
2427                 } else {
2428                         reg |= 0x4;
2429                 }
2430
2431                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
2432
2433                 /* free space in tx packet buffer to wake from DMA coal */
2434                 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE -
2435                     (2 * max_frame_size)) >> 6);
2436
2437                 /* make low power state decision controlled by DMA coal */
2438                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2439                 reg &= ~E1000_PCIEMISC_LX_DECISION;
2440                 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
2441
2442         } else if (hw->mac.type == e1000_82580) {
2443                 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2444                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
2445                     reg & ~E1000_PCIEMISC_LX_DECISION);
2446                 E1000_WRITE_REG(hw, E1000_DMACR, 0);
2447         }
2448 }
2449
2450 /*********************************************************************
2451  *
2452  *  Initialize the hardware to a configuration as specified by the
2453  *  adapter structure.
2454  *
2455  **********************************************************************/
2456 static void
2457 em_reset(if_ctx_t ctx)
2458 {
2459         device_t dev = iflib_get_dev(ctx);
2460         struct adapter *adapter = iflib_get_softc(ctx);
2461         struct ifnet *ifp = iflib_get_ifp(ctx);
2462         struct e1000_hw *hw = &adapter->hw;
2463         u16 rx_buffer_size;
2464         u32 pba;
2465
2466         INIT_DEBUGOUT("em_reset: begin");
2467         /* Let the firmware know the OS is in control */
2468         em_get_hw_control(adapter);
2469
2470         /* Set up smart power down as default off on newer adapters. */
2471         if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2472             hw->mac.type == e1000_82572)) {
2473                 u16 phy_tmp = 0;
2474
2475                 /* Speed up time to link by disabling smart power down. */
2476                 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2477                 phy_tmp &= ~IGP02E1000_PM_SPD;
2478                 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2479         }
2480
2481         /*
2482          * Packet Buffer Allocation (PBA)
2483          * Writing PBA sets the receive portion of the buffer
2484          * the remainder is used for the transmit buffer.
2485          */
2486         switch (hw->mac.type) {
2487         /* 82547: Total Packet Buffer is 40K */
2488         case e1000_82547:
2489         case e1000_82547_rev_2:
2490                 if (hw->mac.max_frame_size > 8192)
2491                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
2492                 else
2493                         pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
2494                 break;
2495         /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */
2496         case e1000_82571:
2497         case e1000_82572:
2498         case e1000_80003es2lan:
2499                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2500                 break;
2501         /* 82573: Total Packet Buffer is 32K */
2502         case e1000_82573:
2503                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2504                 break;
2505         case e1000_82574:
2506         case e1000_82583:
2507                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2508                 break;
2509         case e1000_ich8lan:
2510                 pba = E1000_PBA_8K;
2511                 break;
2512         case e1000_ich9lan:
2513         case e1000_ich10lan:
2514                 /* Boost Receive side for jumbo frames */
2515                 if (hw->mac.max_frame_size > 4096)
2516                         pba = E1000_PBA_14K;
2517                 else
2518                         pba = E1000_PBA_10K;
2519                 break;
2520         case e1000_pchlan:
2521         case e1000_pch2lan:
2522         case e1000_pch_lpt:
2523         case e1000_pch_spt:
2524         case e1000_pch_cnp:
2525                 pba = E1000_PBA_26K;
2526                 break;
2527         case e1000_82575:
2528                 pba = E1000_PBA_32K;
2529                 break;
2530         case e1000_82576:
2531         case e1000_vfadapt:
2532                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2533                 pba &= E1000_RXPBS_SIZE_MASK_82576;
2534                 break;
2535         case e1000_82580:
2536         case e1000_i350:
2537         case e1000_i354:
2538         case e1000_vfadapt_i350:
2539                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2540                 pba = e1000_rxpbs_adjust_82580(pba);
2541                 break;
2542         case e1000_i210:
2543         case e1000_i211:
2544                 pba = E1000_PBA_34K;
2545                 break;
2546         default:
2547                 /* Remaining devices assumed to have a Packet Buffer of 64K. */
2548                 if (hw->mac.max_frame_size > 8192)
2549                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2550                 else
2551                         pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2552         }
2553
2554         /* Special needs in case of Jumbo frames */
2555         if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) {
2556                 u32 tx_space, min_tx, min_rx;
2557                 pba = E1000_READ_REG(hw, E1000_PBA);
2558                 tx_space = pba >> 16;
2559                 pba &= 0xffff;
2560                 min_tx = (hw->mac.max_frame_size +
2561                     sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
2562                 min_tx = roundup2(min_tx, 1024);
2563                 min_tx >>= 10;
2564                 min_rx = hw->mac.max_frame_size;
2565                 min_rx = roundup2(min_rx, 1024);
2566                 min_rx >>= 10;
2567                 if (tx_space < min_tx &&
2568                     ((min_tx - tx_space) < pba)) {
2569                         pba = pba - (min_tx - tx_space);
2570                         /*
2571                          * if short on rx space, rx wins
2572                          * and must trump tx adjustment
2573                          */
2574                         if (pba < min_rx)
2575                                 pba = min_rx;
2576                 }
2577                 E1000_WRITE_REG(hw, E1000_PBA, pba);
2578         }
2579
2580         if (hw->mac.type < igb_mac_min)
2581                 E1000_WRITE_REG(hw, E1000_PBA, pba);
2582
2583         INIT_DEBUGOUT1("em_reset: pba=%dK",pba);
2584
2585         /*
2586          * These parameters control the automatic generation (Tx) and
2587          * response (Rx) to Ethernet PAUSE frames.
2588          * - High water mark should allow for at least two frames to be
2589          *   received after sending an XOFF.
2590          * - Low water mark works best when it is very near the high water mark.
2591          *   This allows the receiver to restart by sending XON when it has
2592          *   drained a bit. Here we use an arbitrary value of 1500 which will
2593          *   restart after one full frame is pulled from the buffer. There
2594          *   could be several smaller frames in the buffer and if so they will
2595          *   not trigger the XON until their total number reduces the buffer
2596          *   by 1500.
2597          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2598          */
2599         rx_buffer_size = (pba & 0xffff) << 10;
2600         hw->fc.high_water = rx_buffer_size -
2601             roundup2(hw->mac.max_frame_size, 1024);
2602         hw->fc.low_water = hw->fc.high_water - 1500;
2603
2604         if (adapter->fc) /* locally set flow control value? */
2605                 hw->fc.requested_mode = adapter->fc;
2606         else
2607                 hw->fc.requested_mode = e1000_fc_full;
2608
2609         if (hw->mac.type == e1000_80003es2lan)
2610                 hw->fc.pause_time = 0xFFFF;
2611         else
2612                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
2613
2614         hw->fc.send_xon = TRUE;
2615
2616         /* Device specific overrides/settings */
2617         switch (hw->mac.type) {
2618         case e1000_pchlan:
2619                 /* Workaround: no TX flow ctrl for PCH */
2620                 hw->fc.requested_mode = e1000_fc_rx_pause;
2621                 hw->fc.pause_time = 0xFFFF; /* override */
2622                 if (if_getmtu(ifp) > ETHERMTU) {
2623                         hw->fc.high_water = 0x3500;
2624                         hw->fc.low_water = 0x1500;
2625                 } else {
2626                         hw->fc.high_water = 0x5000;
2627                         hw->fc.low_water = 0x3000;
2628                 }
2629                 hw->fc.refresh_time = 0x1000;
2630                 break;
2631         case e1000_pch2lan:
2632         case e1000_pch_lpt:
2633         case e1000_pch_spt:
2634         case e1000_pch_cnp:
2635                 hw->fc.high_water = 0x5C20;
2636                 hw->fc.low_water = 0x5048;
2637                 hw->fc.pause_time = 0x0650;
2638                 hw->fc.refresh_time = 0x0400;
2639                 /* Jumbos need adjusted PBA */
2640                 if (if_getmtu(ifp) > ETHERMTU)
2641                         E1000_WRITE_REG(hw, E1000_PBA, 12);
2642                 else
2643                         E1000_WRITE_REG(hw, E1000_PBA, 26);
2644                 break;
2645         case e1000_82575:
2646         case e1000_82576:
2647                 /* 8-byte granularity */
2648                 hw->fc.low_water = hw->fc.high_water - 8;
2649                 break;
2650         case e1000_82580:
2651         case e1000_i350:
2652         case e1000_i354:
2653         case e1000_i210:
2654         case e1000_i211:
2655         case e1000_vfadapt:
2656         case e1000_vfadapt_i350:
2657                 /* 16-byte granularity */
2658                 hw->fc.low_water = hw->fc.high_water - 16;
2659                 break;
2660         case e1000_ich9lan:
2661         case e1000_ich10lan:
2662                 if (if_getmtu(ifp) > ETHERMTU) {
2663                         hw->fc.high_water = 0x2800;
2664                         hw->fc.low_water = hw->fc.high_water - 8;
2665                         break;
2666                 }
2667                 /* FALLTHROUGH */
2668         default:
2669                 if (hw->mac.type == e1000_80003es2lan)
2670                         hw->fc.pause_time = 0xFFFF;
2671                 break;
2672         }
2673
2674         /* Issue a global reset */
2675         e1000_reset_hw(hw);
2676         if (hw->mac.type >= igb_mac_min) {
2677                 E1000_WRITE_REG(hw, E1000_WUC, 0);
2678         } else {
2679                 E1000_WRITE_REG(hw, E1000_WUFC, 0);
2680                 em_disable_aspm(adapter);
2681         }
2682         if (adapter->flags & IGB_MEDIA_RESET) {
2683                 e1000_setup_init_funcs(hw, TRUE);
2684                 e1000_get_bus_info(hw);
2685                 adapter->flags &= ~IGB_MEDIA_RESET;
2686         }
2687         /* and a re-init */
2688         if (e1000_init_hw(hw) < 0) {
2689                 device_printf(dev, "Hardware Initialization Failed\n");
2690                 return;
2691         }
2692         if (hw->mac.type >= igb_mac_min)
2693                 igb_init_dmac(adapter, pba);
2694
2695         E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2696         e1000_get_phy_info(hw);
2697         e1000_check_for_link(hw);
2698 }
2699
2700 /*
2701  * Initialise the RSS mapping for NICs that support multiple transmit/
2702  * receive rings.
2703  */
2704
2705 #define RSSKEYLEN 10
2706 static void
2707 em_initialize_rss_mapping(struct adapter *adapter)
2708 {
2709         uint8_t  rss_key[4 * RSSKEYLEN];
2710         uint32_t reta = 0;
2711         struct e1000_hw *hw = &adapter->hw;
2712         int i;
2713
2714         /*
2715          * Configure RSS key
2716          */
2717         arc4rand(rss_key, sizeof(rss_key), 0);
2718         for (i = 0; i < RSSKEYLEN; ++i) {
2719                 uint32_t rssrk = 0;
2720
2721                 rssrk = EM_RSSRK_VAL(rss_key, i);
2722                 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2723         }
2724
2725         /*
2726          * Configure RSS redirect table in following fashion:
2727          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2728          */
2729         for (i = 0; i < sizeof(reta); ++i) {
2730                 uint32_t q;
2731
2732                 q = (i % adapter->rx_num_queues) << 7;
2733                 reta |= q << (8 * i);
2734         }
2735
2736         for (i = 0; i < 32; ++i)
2737                 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2738
2739         E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2740                         E1000_MRQC_RSS_FIELD_IPV4_TCP |
2741                         E1000_MRQC_RSS_FIELD_IPV4 |
2742                         E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2743                         E1000_MRQC_RSS_FIELD_IPV6_EX |
2744                         E1000_MRQC_RSS_FIELD_IPV6);
2745 }
2746
2747 static void
2748 igb_initialize_rss_mapping(struct adapter *adapter)
2749 {
2750         struct e1000_hw *hw = &adapter->hw;
2751         int i;
2752         int queue_id;
2753         u32 reta;
2754         u32 rss_key[10], mrqc, shift = 0;
2755
2756         /* XXX? */
2757         if (hw->mac.type == e1000_82575)
2758                 shift = 6;
2759
2760         /*
2761          * The redirection table controls which destination
2762          * queue each bucket redirects traffic to.
2763          * Each DWORD represents four queues, with the LSB
2764          * being the first queue in the DWORD.
2765          *
2766          * This just allocates buckets to queues using round-robin
2767          * allocation.
2768          *
2769          * NOTE: It Just Happens to line up with the default
2770          * RSS allocation method.
2771          */
2772
2773         /* Warning FM follows */
2774         reta = 0;
2775         for (i = 0; i < 128; i++) {
2776 #ifdef RSS
2777                 queue_id = rss_get_indirection_to_bucket(i);
2778                 /*
2779                  * If we have more queues than buckets, we'll
2780                  * end up mapping buckets to a subset of the
2781                  * queues.
2782                  *
2783                  * If we have more buckets than queues, we'll
2784                  * end up instead assigning multiple buckets
2785                  * to queues.
2786                  *
2787                  * Both are suboptimal, but we need to handle
2788                  * the case so we don't go out of bounds
2789                  * indexing arrays and such.
2790                  */
2791                 queue_id = queue_id % adapter->rx_num_queues;
2792 #else
2793                 queue_id = (i % adapter->rx_num_queues);
2794 #endif
2795                 /* Adjust if required */
2796                 queue_id = queue_id << shift;
2797
2798                 /*
2799                  * The low 8 bits are for hash value (n+0);
2800                  * The next 8 bits are for hash value (n+1), etc.
2801                  */
2802                 reta = reta >> 8;
2803                 reta = reta | ( ((uint32_t) queue_id) << 24);
2804                 if ((i & 3) == 3) {
2805                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2806                         reta = 0;
2807                 }
2808         }
2809
2810         /* Now fill in hash table */
2811
2812         /*
2813          * MRQC: Multiple Receive Queues Command
2814          * Set queuing to RSS control, number depends on the device.
2815          */
2816         mrqc = E1000_MRQC_ENABLE_RSS_8Q;
2817
2818 #ifdef RSS
2819         /* XXX ew typecasting */
2820         rss_getkey((uint8_t *) &rss_key);
2821 #else
2822         arc4rand(&rss_key, sizeof(rss_key), 0);
2823 #endif
2824         for (i = 0; i < 10; i++)
2825                 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]);
2826
2827         /*
2828          * Configure the RSS fields to hash upon.
2829          */
2830         mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2831             E1000_MRQC_RSS_FIELD_IPV4_TCP);
2832         mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2833             E1000_MRQC_RSS_FIELD_IPV6_TCP);
2834         mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2835             E1000_MRQC_RSS_FIELD_IPV6_UDP);
2836         mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2837             E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2838
2839         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2840 }
2841
2842 /*********************************************************************
2843  *
2844  *  Setup networking device structure and register interface media.
2845  *
2846  **********************************************************************/
2847 static int
2848 em_setup_interface(if_ctx_t ctx)
2849 {
2850         struct ifnet *ifp = iflib_get_ifp(ctx);
2851         struct adapter *adapter = iflib_get_softc(ctx);
2852         if_softc_ctx_t scctx = adapter->shared;
2853
2854         INIT_DEBUGOUT("em_setup_interface: begin");
2855
2856         /* Single Queue */
2857         if (adapter->tx_num_queues == 1) {
2858                 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
2859                 if_setsendqready(ifp);
2860         }
2861
2862         /*
2863          * Specify the media types supported by this adapter and register
2864          * callbacks to update media and link information
2865          */
2866         if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2867             adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
2868                 u_char fiber_type = IFM_1000_SX;        /* default type */
2869
2870                 if (adapter->hw.mac.type == e1000_82545)
2871                         fiber_type = IFM_1000_LX;
2872                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
2873                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2874         } else {
2875                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2876                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2877                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2878                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2879                 if (adapter->hw.phy.type != e1000_phy_ife) {
2880                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2881                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2882                 }
2883         }
2884         ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2885         ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO);
2886         return (0);
2887 }
2888
2889 static int
2890 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
2891 {
2892         struct adapter *adapter = iflib_get_softc(ctx);
2893         if_softc_ctx_t scctx = adapter->shared;
2894         int error = E1000_SUCCESS;
2895         struct em_tx_queue *que;
2896         int i, j;
2897
2898         MPASS(adapter->tx_num_queues > 0);
2899         MPASS(adapter->tx_num_queues == ntxqsets);
2900
2901         /* First allocate the top level queue structs */
2902         if (!(adapter->tx_queues =
2903             (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
2904             adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2905                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2906                 return(ENOMEM);
2907         }
2908
2909         for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) {
2910                 /* Set up some basics */
2911
2912                 struct tx_ring *txr = &que->txr;
2913                 txr->adapter = que->adapter = adapter;
2914                 que->me = txr->me =  i;
2915
2916                 /* Allocate report status array */
2917                 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2918                         device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n");
2919                         error = ENOMEM;
2920                         goto fail;
2921                 }
2922                 for (j = 0; j < scctx->isc_ntxd[0]; j++)
2923                         txr->tx_rsq[j] = QIDX_INVALID;
2924                 /* get the virtual and physical address of the hardware queues */
2925                 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
2926                 txr->tx_paddr = paddrs[i*ntxqs];
2927         }
2928
2929         if (bootverbose)
2930                 device_printf(iflib_get_dev(ctx),
2931                     "allocated for %d tx_queues\n", adapter->tx_num_queues);
2932         return (0);
2933 fail:
2934         em_if_queues_free(ctx);
2935         return (error);
2936 }
2937
2938 static int
2939 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
2940 {
2941         struct adapter *adapter = iflib_get_softc(ctx);
2942         int error = E1000_SUCCESS;
2943         struct em_rx_queue *que;
2944         int i;
2945
2946         MPASS(adapter->rx_num_queues > 0);
2947         MPASS(adapter->rx_num_queues == nrxqsets);
2948
2949         /* First allocate the top level queue structs */
2950         if (!(adapter->rx_queues =
2951             (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
2952             adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2953                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2954                 error = ENOMEM;
2955                 goto fail;
2956         }
2957
2958         for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) {
2959                 /* Set up some basics */
2960                 struct rx_ring *rxr = &que->rxr;
2961                 rxr->adapter = que->adapter = adapter;
2962                 rxr->que = que;
2963                 que->me = rxr->me =  i;
2964
2965                 /* get the virtual and physical address of the hardware queues */
2966                 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
2967                 rxr->rx_paddr = paddrs[i*nrxqs];
2968         }
2969
2970         if (bootverbose)
2971                 device_printf(iflib_get_dev(ctx),
2972                     "allocated for %d rx_queues\n", adapter->rx_num_queues);
2973
2974         return (0);
2975 fail:
2976         em_if_queues_free(ctx);
2977         return (error);
2978 }
2979
2980 static void
2981 em_if_queues_free(if_ctx_t ctx)
2982 {
2983         struct adapter *adapter = iflib_get_softc(ctx);
2984         struct em_tx_queue *tx_que = adapter->tx_queues;
2985         struct em_rx_queue *rx_que = adapter->rx_queues;
2986
2987         if (tx_que != NULL) {
2988                 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
2989                         struct tx_ring *txr = &tx_que->txr;
2990                         if (txr->tx_rsq == NULL)
2991                                 break;
2992
2993                         free(txr->tx_rsq, M_DEVBUF);
2994                         txr->tx_rsq = NULL;
2995                 }
2996                 free(adapter->tx_queues, M_DEVBUF);
2997                 adapter->tx_queues = NULL;
2998         }
2999
3000         if (rx_que != NULL) {
3001                 free(adapter->rx_queues, M_DEVBUF);
3002                 adapter->rx_queues = NULL;
3003         }
3004 }
3005
3006 /*********************************************************************
3007  *
3008  *  Enable transmit unit.
3009  *
3010  **********************************************************************/
3011 static void
3012 em_initialize_transmit_unit(if_ctx_t ctx)
3013 {
3014         struct adapter *adapter = iflib_get_softc(ctx);
3015         if_softc_ctx_t scctx = adapter->shared;
3016         struct em_tx_queue *que;
3017         struct tx_ring  *txr;
3018         struct e1000_hw *hw = &adapter->hw;
3019         u32 tctl, txdctl = 0, tarc, tipg = 0;
3020
3021         INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
3022
3023         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
3024                 u64 bus_addr;
3025                 caddr_t offp, endp;
3026
3027                 que = &adapter->tx_queues[i];
3028                 txr = &que->txr;
3029                 bus_addr = txr->tx_paddr;
3030
3031                 /* Clear checksum offload context. */
3032                 offp = (caddr_t)&txr->csum_flags;
3033                 endp = (caddr_t)(txr + 1);
3034                 bzero(offp, endp - offp);
3035
3036                 /* Base and Len of TX Ring */
3037                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
3038                     scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
3039                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
3040                     (u32)(bus_addr >> 32));
3041                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
3042                     (u32)bus_addr);
3043                 /* Init the HEAD/TAIL indices */
3044                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
3045                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
3046
3047                 HW_DEBUGOUT2("Base = %x, Length = %x\n",
3048                     E1000_READ_REG(hw, E1000_TDBAL(i)),
3049                     E1000_READ_REG(hw, E1000_TDLEN(i)));
3050
3051                 txdctl = 0; /* clear txdctl */
3052                 txdctl |= 0x1f; /* PTHRESH */
3053                 txdctl |= 1 << 8; /* HTHRESH */
3054                 txdctl |= 1 << 16;/* WTHRESH */
3055                 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
3056                 txdctl |= E1000_TXDCTL_GRAN;
3057                 txdctl |= 1 << 25; /* LWTHRESH */
3058
3059                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
3060         }
3061
3062         /* Set the default values for the Tx Inter Packet Gap timer */
3063         switch (hw->mac.type) {
3064         case e1000_80003es2lan:
3065                 tipg = DEFAULT_82543_TIPG_IPGR1;
3066                 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
3067                     E1000_TIPG_IPGR2_SHIFT;
3068                 break;
3069         case e1000_82542:
3070                 tipg = DEFAULT_82542_TIPG_IPGT;
3071                 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3072                 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3073                 break;
3074         default:
3075                 if (hw->phy.media_type == e1000_media_type_fiber ||
3076                     hw->phy.media_type == e1000_media_type_internal_serdes)
3077                         tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
3078                 else
3079                         tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
3080                 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3081                 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3082         }
3083
3084         E1000_WRITE_REG(hw, E1000_TIPG, tipg);
3085         E1000_WRITE_REG(hw, E1000_TIDV, adapter->tx_int_delay.value);
3086
3087         if(hw->mac.type >= e1000_82540)
3088                 E1000_WRITE_REG(hw, E1000_TADV,
3089                     adapter->tx_abs_int_delay.value);
3090
3091         if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) {
3092                 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3093                 tarc |= TARC_SPEED_MODE_BIT;
3094                 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3095         } else if (hw->mac.type == e1000_80003es2lan) {
3096                 /* errata: program both queues to unweighted RR */
3097                 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3098                 tarc |= 1;
3099                 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3100                 tarc = E1000_READ_REG(hw, E1000_TARC(1));
3101                 tarc |= 1;
3102                 E1000_WRITE_REG(hw, E1000_TARC(1), tarc);
3103         } else if (hw->mac.type == e1000_82574) {
3104                 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3105                 tarc |= TARC_ERRATA_BIT;
3106                 if ( adapter->tx_num_queues > 1) {
3107                         tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
3108                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3109                         E1000_WRITE_REG(hw, E1000_TARC(1), tarc);
3110                 } else
3111                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3112         }
3113
3114         if (adapter->tx_int_delay.value > 0)
3115                 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3116
3117         /* Program the Transmit Control Register */
3118         tctl = E1000_READ_REG(hw, E1000_TCTL);
3119         tctl &= ~E1000_TCTL_CT;
3120         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
3121                    (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
3122
3123         if (hw->mac.type >= e1000_82571)
3124                 tctl |= E1000_TCTL_MULR;
3125
3126         /* This write will effectively turn on the transmit unit. */
3127         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
3128
3129         /* SPT and KBL errata workarounds */
3130         if (hw->mac.type == e1000_pch_spt) {
3131                 u32 reg;
3132                 reg = E1000_READ_REG(hw, E1000_IOSFPC);
3133                 reg |= E1000_RCTL_RDMTS_HEX;
3134                 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
3135                 /* i218-i219 Specification Update 1.5.4.5 */
3136                 reg = E1000_READ_REG(hw, E1000_TARC(0));
3137                 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3138                 reg |= E1000_TARC0_CB_MULTIQ_2_REQ;
3139                 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3140         }
3141 }
3142
3143 /*********************************************************************
3144  *
3145  *  Enable receive unit.
3146  *
3147  **********************************************************************/
3148
3149 static void
3150 em_initialize_receive_unit(if_ctx_t ctx)
3151 {
3152         struct adapter *adapter = iflib_get_softc(ctx);
3153         if_softc_ctx_t scctx = adapter->shared;
3154         struct ifnet *ifp = iflib_get_ifp(ctx);
3155         struct e1000_hw *hw = &adapter->hw;
3156         struct em_rx_queue *que;
3157         int i;
3158         u32 rctl, rxcsum, rfctl;
3159
3160         INIT_DEBUGOUT("em_initialize_receive_units: begin");
3161
3162         /*
3163          * Make sure receives are disabled while setting
3164          * up the descriptor ring
3165          */
3166         rctl = E1000_READ_REG(hw, E1000_RCTL);
3167         /* Do not disable if ever enabled on this hardware */
3168         if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
3169                 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3170
3171         /* Setup the Receive Control Register */
3172         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3173         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3174             E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3175             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3176
3177         /* Do not store bad packets */
3178         rctl &= ~E1000_RCTL_SBP;
3179
3180         /* Enable Long Packet receive */
3181         if (if_getmtu(ifp) > ETHERMTU)
3182                 rctl |= E1000_RCTL_LPE;
3183         else
3184                 rctl &= ~E1000_RCTL_LPE;
3185
3186         /* Strip the CRC */
3187         if (!em_disable_crc_stripping)
3188                 rctl |= E1000_RCTL_SECRC;
3189
3190         if (hw->mac.type >= e1000_82540) {
3191                 E1000_WRITE_REG(hw, E1000_RADV,
3192                     adapter->rx_abs_int_delay.value);
3193
3194                 /*
3195                  * Set the interrupt throttling rate. Value is calculated
3196                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
3197                  */
3198                 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
3199         }
3200         E1000_WRITE_REG(hw, E1000_RDTR, adapter->rx_int_delay.value);
3201
3202         /* Use extended rx descriptor formats */
3203         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3204         rfctl |= E1000_RFCTL_EXTEN;
3205         /*
3206          * When using MSI-X interrupts we need to throttle
3207          * using the EITR register (82574 only)
3208          */
3209         if (hw->mac.type == e1000_82574) {
3210                 for (int i = 0; i < 4; i++)
3211                         E1000_WRITE_REG(hw, E1000_EITR_82574(i),
3212                             DEFAULT_ITR);
3213                 /* Disable accelerated acknowledge */
3214                 rfctl |= E1000_RFCTL_ACK_DIS;
3215         }
3216         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3217
3218         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
3219         if (if_getcapenable(ifp) & IFCAP_RXCSUM &&
3220             hw->mac.type >= e1000_82543) {
3221                 if (adapter->tx_num_queues > 1) {
3222                         if (hw->mac.type >= igb_mac_min) {
3223                                 rxcsum |= E1000_RXCSUM_PCSD;
3224                                 if (hw->mac.type != e1000_82575)
3225                                         rxcsum |= E1000_RXCSUM_CRCOFL;
3226                         } else
3227                                 rxcsum |= E1000_RXCSUM_TUOFL |
3228                                         E1000_RXCSUM_IPOFL |
3229                                         E1000_RXCSUM_PCSD;
3230                 } else {
3231                         if (hw->mac.type >= igb_mac_min)
3232                                 rxcsum |= E1000_RXCSUM_IPPCSE;
3233                         else
3234                                 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
3235                         if (hw->mac.type > e1000_82575)
3236                                 rxcsum |= E1000_RXCSUM_CRCOFL;
3237                 }
3238         } else
3239                 rxcsum &= ~E1000_RXCSUM_TUOFL;
3240
3241         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
3242
3243         if (adapter->rx_num_queues > 1) {
3244                 if (hw->mac.type >= igb_mac_min)
3245                         igb_initialize_rss_mapping(adapter);
3246                 else
3247                         em_initialize_rss_mapping(adapter);
3248         }
3249
3250         /*
3251          * XXX TEMPORARY WORKAROUND: on some systems with 82573
3252          * long latencies are observed, like Lenovo X60. This
3253          * change eliminates the problem, but since having positive
3254          * values in RDTR is a known source of problems on other
3255          * platforms another solution is being sought.
3256          */
3257         if (hw->mac.type == e1000_82573)
3258                 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
3259
3260         for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3261                 struct rx_ring *rxr = &que->rxr;
3262                 /* Setup the Base and Length of the Rx Descriptor Ring */
3263                 u64 bus_addr = rxr->rx_paddr;
3264 #if 0
3265                 u32 rdt = adapter->rx_num_queues -1;  /* default */
3266 #endif
3267
3268                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3269                     scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
3270                 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
3271                 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
3272                 /* Setup the Head and Tail Descriptor Pointers */
3273                 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
3274                 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
3275         }
3276
3277         /*
3278          * Set PTHRESH for improved jumbo performance
3279          * According to 10.2.5.11 of Intel 82574 Datasheet,
3280          * RXDCTL(1) is written whenever RXDCTL(0) is written.
3281          * Only write to RXDCTL(1) if there is a need for different
3282          * settings.
3283          */
3284         if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan ||
3285             hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) {
3286                 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
3287                 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
3288         } else if (hw->mac.type == e1000_82574) {
3289                 for (int i = 0; i < adapter->rx_num_queues; i++) {
3290                         u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3291                         rxdctl |= 0x20; /* PTHRESH */
3292                         rxdctl |= 4 << 8; /* HTHRESH */
3293                         rxdctl |= 4 << 16;/* WTHRESH */
3294                         rxdctl |= 1 << 24; /* Switch to granularity */
3295                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3296                 }
3297         } else if (hw->mac.type >= igb_mac_min) {
3298                 u32 psize, srrctl = 0;
3299
3300                 if (if_getmtu(ifp) > ETHERMTU) {
3301                         /* Set maximum packet len */
3302                         if (adapter->rx_mbuf_sz <= 4096) {
3303                                 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3304                                 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3305                         } else if (adapter->rx_mbuf_sz > 4096) {
3306                                 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3307                                 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3308                         }
3309                         psize = scctx->isc_max_frame_size;
3310                         /* are we on a vlan? */
3311                         if (ifp->if_vlantrunk != NULL)
3312                                 psize += VLAN_TAG_SIZE;
3313                         E1000_WRITE_REG(hw, E1000_RLPML, psize);
3314                 } else {
3315                         srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3316                         rctl |= E1000_RCTL_SZ_2048;
3317                 }
3318
3319                 /*
3320                  * If TX flow control is disabled and there's >1 queue defined,
3321                  * enable DROP.
3322                  *
3323                  * This drops frames rather than hanging the RX MAC for all queues.
3324                  */
3325                 if ((adapter->rx_num_queues > 1) &&
3326                     (adapter->fc == e1000_fc_none ||
3327                      adapter->fc == e1000_fc_rx_pause)) {
3328                         srrctl |= E1000_SRRCTL_DROP_EN;
3329                 }
3330                         /* Setup the Base and Length of the Rx Descriptor Rings */
3331                 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3332                         struct rx_ring *rxr = &que->rxr;
3333                         u64 bus_addr = rxr->rx_paddr;
3334                         u32 rxdctl;
3335
3336 #ifdef notyet
3337                         /* Configure for header split? -- ignore for now */
3338                         rxr->hdr_split = igb_header_split;
3339 #else
3340                         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3341 #endif
3342
3343                         E1000_WRITE_REG(hw, E1000_RDLEN(i),
3344                                         scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3345                         E1000_WRITE_REG(hw, E1000_RDBAH(i),
3346                                         (uint32_t)(bus_addr >> 32));
3347                         E1000_WRITE_REG(hw, E1000_RDBAL(i),
3348                                         (uint32_t)bus_addr);
3349                         E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3350                         /* Enable this Queue */
3351                         rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3352                         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3353                         rxdctl &= 0xFFF00000;
3354                         rxdctl |= IGB_RX_PTHRESH;
3355                         rxdctl |= IGB_RX_HTHRESH << 8;
3356                         rxdctl |= IGB_RX_WTHRESH << 16;
3357                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3358                 }
3359         } else if (hw->mac.type >= e1000_pch2lan) {
3360                 if (if_getmtu(ifp) > ETHERMTU)
3361                         e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
3362                 else
3363                         e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
3364         }
3365
3366         /* Make sure VLAN Filters are off */
3367         rctl &= ~E1000_RCTL_VFE;
3368
3369         if (hw->mac.type < igb_mac_min) {
3370                 if (adapter->rx_mbuf_sz == MCLBYTES)
3371                         rctl |= E1000_RCTL_SZ_2048;
3372                 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE)
3373                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3374                 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE)
3375                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3376
3377                 /* ensure we clear use DTYPE of 00 here */
3378                 rctl &= ~0x00000C00;
3379         }
3380
3381         /* Write out the settings */
3382         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3383
3384         return;
3385 }
3386
3387 static void
3388 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3389 {
3390         struct adapter *adapter = iflib_get_softc(ctx);
3391         u32 index, bit;
3392
3393         index = (vtag >> 5) & 0x7F;
3394         bit = vtag & 0x1F;
3395         adapter->shadow_vfta[index] |= (1 << bit);
3396         ++adapter->num_vlans;
3397 }
3398
3399 static void
3400 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3401 {
3402         struct adapter *adapter = iflib_get_softc(ctx);
3403         u32 index, bit;
3404
3405         index = (vtag >> 5) & 0x7F;
3406         bit = vtag & 0x1F;
3407         adapter->shadow_vfta[index] &= ~(1 << bit);
3408         --adapter->num_vlans;
3409 }
3410
3411 static void
3412 em_setup_vlan_hw_support(struct adapter *adapter)
3413 {
3414         struct e1000_hw *hw = &adapter->hw;
3415         u32 reg;
3416
3417         /*
3418          * We get here thru init_locked, meaning
3419          * a soft reset, this has already cleared
3420          * the VFTA and other state, so if there
3421          * have been no vlan's registered do nothing.
3422          */
3423         if (adapter->num_vlans == 0)
3424                 return;
3425
3426         /*
3427          * A soft reset zero's out the VFTA, so
3428          * we need to repopulate it now.
3429          */
3430         for (int i = 0; i < EM_VFTA_SIZE; i++)
3431                 if (adapter->shadow_vfta[i] != 0)
3432                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
3433                             i, adapter->shadow_vfta[i]);
3434
3435         reg = E1000_READ_REG(hw, E1000_CTRL);
3436         reg |= E1000_CTRL_VME;
3437         E1000_WRITE_REG(hw, E1000_CTRL, reg);
3438
3439         /* Enable the Filter Table */
3440         reg = E1000_READ_REG(hw, E1000_RCTL);
3441         reg &= ~E1000_RCTL_CFIEN;
3442         reg |= E1000_RCTL_VFE;
3443         E1000_WRITE_REG(hw, E1000_RCTL, reg);
3444 }
3445
3446 static void
3447 em_if_intr_enable(if_ctx_t ctx)
3448 {
3449         struct adapter *adapter = iflib_get_softc(ctx);
3450         struct e1000_hw *hw = &adapter->hw;
3451         u32 ims_mask = IMS_ENABLE_MASK;
3452
3453         if (hw->mac.type == e1000_82574) {
3454                 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK);
3455                 ims_mask |= adapter->ims;
3456         }
3457         E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3458 }
3459
3460 static void
3461 em_if_intr_disable(if_ctx_t ctx)
3462 {
3463         struct adapter *adapter = iflib_get_softc(ctx);
3464         struct e1000_hw *hw = &adapter->hw;
3465
3466         if (hw->mac.type == e1000_82574)
3467                 E1000_WRITE_REG(hw, EM_EIAC, 0);
3468         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3469 }
3470
3471 static void
3472 igb_if_intr_enable(if_ctx_t ctx)
3473 {
3474         struct adapter *adapter = iflib_get_softc(ctx);
3475         struct e1000_hw *hw = &adapter->hw;
3476         u32 mask;
3477
3478         if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) {
3479                 mask = (adapter->que_mask | adapter->link_mask);
3480                 E1000_WRITE_REG(hw, E1000_EIAC, mask);
3481                 E1000_WRITE_REG(hw, E1000_EIAM, mask);
3482                 E1000_WRITE_REG(hw, E1000_EIMS, mask);
3483                 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
3484         } else
3485                 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
3486         E1000_WRITE_FLUSH(hw);
3487 }
3488
3489 static void
3490 igb_if_intr_disable(if_ctx_t ctx)
3491 {
3492         struct adapter *adapter = iflib_get_softc(ctx);
3493         struct e1000_hw *hw = &adapter->hw;
3494
3495         if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) {
3496                 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff);
3497                 E1000_WRITE_REG(hw, E1000_EIAC, 0);
3498         }
3499         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3500         E1000_WRITE_FLUSH(hw);
3501 }
3502
3503 /*
3504  * Bit of a misnomer, what this really means is
3505  * to enable OS management of the system... aka
3506  * to disable special hardware management features
3507  */
3508 static void
3509 em_init_manageability(struct adapter *adapter)
3510 {
3511         /* A shared code workaround */
3512 #define E1000_82542_MANC2H E1000_MANC2H
3513         if (adapter->has_manage) {
3514                 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3515                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3516
3517                 /* disable hardware interception of ARP */
3518                 manc &= ~(E1000_MANC_ARP_EN);
3519
3520                 /* enable receiving management packets to the host */
3521                 manc |= E1000_MANC_EN_MNG2HOST;
3522 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3523 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3524                 manc2h |= E1000_MNG2HOST_PORT_623;
3525                 manc2h |= E1000_MNG2HOST_PORT_664;
3526                 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3527                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3528         }
3529 }
3530
3531 /*
3532  * Give control back to hardware management
3533  * controller if there is one.
3534  */
3535 static void
3536 em_release_manageability(struct adapter *adapter)
3537 {
3538         if (adapter->has_manage) {
3539                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3540
3541                 /* re-enable hardware interception of ARP */
3542                 manc |= E1000_MANC_ARP_EN;
3543                 manc &= ~E1000_MANC_EN_MNG2HOST;
3544
3545                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3546         }
3547 }
3548
3549 /*
3550  * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3551  * For ASF and Pass Through versions of f/w this means
3552  * that the driver is loaded. For AMT version type f/w
3553  * this means that the network i/f is open.
3554  */
3555 static void
3556 em_get_hw_control(struct adapter *adapter)
3557 {
3558         u32 ctrl_ext, swsm;
3559
3560         if (adapter->vf_ifp)
3561                 return;
3562
3563         if (adapter->hw.mac.type == e1000_82573) {
3564                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3565                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3566                     swsm | E1000_SWSM_DRV_LOAD);
3567                 return;
3568         }
3569         /* else */
3570         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3571         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3572             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3573 }
3574
3575 /*
3576  * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3577  * For ASF and Pass Through versions of f/w this means that
3578  * the driver is no longer loaded. For AMT versions of the
3579  * f/w this means that the network i/f is closed.
3580  */
3581 static void
3582 em_release_hw_control(struct adapter *adapter)
3583 {
3584         u32 ctrl_ext, swsm;
3585
3586         if (!adapter->has_manage)
3587                 return;
3588
3589         if (adapter->hw.mac.type == e1000_82573) {
3590                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3591                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3592                     swsm & ~E1000_SWSM_DRV_LOAD);
3593                 return;
3594         }
3595         /* else */
3596         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3597         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3598             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3599         return;
3600 }
3601
3602 static int
3603 em_is_valid_ether_addr(u8 *addr)
3604 {
3605         char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3606
3607         if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3608                 return (FALSE);
3609         }
3610
3611         return (TRUE);
3612 }
3613
3614 /*
3615 ** Parse the interface capabilities with regard
3616 ** to both system management and wake-on-lan for
3617 ** later use.
3618 */
3619 static void
3620 em_get_wakeup(if_ctx_t ctx)
3621 {
3622         struct adapter *adapter = iflib_get_softc(ctx);
3623         device_t dev = iflib_get_dev(ctx);
3624         u16 eeprom_data = 0, device_id, apme_mask;
3625
3626         adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
3627         apme_mask = EM_EEPROM_APME;
3628
3629         switch (adapter->hw.mac.type) {
3630         case e1000_82542:
3631         case e1000_82543:
3632                 break;
3633         case e1000_82544:
3634                 e1000_read_nvm(&adapter->hw,
3635                     NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3636                 apme_mask = EM_82544_APME;
3637                 break;
3638         case e1000_82546:
3639         case e1000_82546_rev_3:
3640                 if (adapter->hw.bus.func == 1) {
3641                         e1000_read_nvm(&adapter->hw,
3642                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3643                         break;
3644                 } else
3645                         e1000_read_nvm(&adapter->hw,
3646                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3647                 break;
3648         case e1000_82573:
3649         case e1000_82583:
3650                 adapter->has_amt = TRUE;
3651                 /* FALLTHROUGH */
3652         case e1000_82571:
3653         case e1000_82572:
3654         case e1000_80003es2lan:
3655                 if (adapter->hw.bus.func == 1) {
3656                         e1000_read_nvm(&adapter->hw,
3657                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3658                         break;
3659                 } else
3660                         e1000_read_nvm(&adapter->hw,
3661                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3662                 break;
3663         case e1000_ich8lan:
3664         case e1000_ich9lan:
3665         case e1000_ich10lan:
3666         case e1000_pchlan:
3667         case e1000_pch2lan:
3668         case e1000_pch_lpt:
3669         case e1000_pch_spt:
3670         case e1000_82575:       /* listing all igb devices */
3671         case e1000_82576:
3672         case e1000_82580:
3673         case e1000_i350:
3674         case e1000_i354:
3675         case e1000_i210:
3676         case e1000_i211:
3677         case e1000_vfadapt:
3678         case e1000_vfadapt_i350:
3679                 apme_mask = E1000_WUC_APME;
3680                 adapter->has_amt = TRUE;
3681                 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
3682                 break;
3683         default:
3684                 e1000_read_nvm(&adapter->hw,
3685                     NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3686                 break;
3687         }
3688         if (eeprom_data & apme_mask)
3689                 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
3690         /*
3691          * We have the eeprom settings, now apply the special cases
3692          * where the eeprom may be wrong or the board won't support
3693          * wake on lan on a particular port
3694          */
3695         device_id = pci_get_device(dev);
3696         switch (device_id) {
3697         case E1000_DEV_ID_82546GB_PCIE:
3698                 adapter->wol = 0;
3699                 break;
3700         case E1000_DEV_ID_82546EB_FIBER:
3701         case E1000_DEV_ID_82546GB_FIBER:
3702                 /* Wake events only supported on port A for dual fiber
3703                  * regardless of eeprom setting */
3704                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3705                     E1000_STATUS_FUNC_1)
3706                         adapter->wol = 0;
3707                 break;
3708         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
3709                 /* if quad port adapter, disable WoL on all but port A */
3710                 if (global_quad_port_a != 0)
3711                         adapter->wol = 0;
3712                 /* Reset for multiple quad port adapters */
3713                 if (++global_quad_port_a == 4)
3714                         global_quad_port_a = 0;
3715                 break;
3716         case E1000_DEV_ID_82571EB_FIBER:
3717                 /* Wake events only supported on port A for dual fiber
3718                  * regardless of eeprom setting */
3719                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3720                     E1000_STATUS_FUNC_1)
3721                         adapter->wol = 0;
3722                 break;
3723         case E1000_DEV_ID_82571EB_QUAD_COPPER:
3724         case E1000_DEV_ID_82571EB_QUAD_FIBER:
3725         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
3726                 /* if quad port adapter, disable WoL on all but port A */
3727                 if (global_quad_port_a != 0)
3728                         adapter->wol = 0;
3729                 /* Reset for multiple quad port adapters */
3730                 if (++global_quad_port_a == 4)
3731                         global_quad_port_a = 0;
3732                 break;
3733         }
3734         return;
3735 }
3736
3737
3738 /*
3739  * Enable PCI Wake On Lan capability
3740  */
3741 static void
3742 em_enable_wakeup(if_ctx_t ctx)
3743 {
3744         struct adapter *adapter = iflib_get_softc(ctx);
3745         device_t dev = iflib_get_dev(ctx);
3746         if_t ifp = iflib_get_ifp(ctx);
3747         int error = 0;
3748         u32 pmc, ctrl, ctrl_ext, rctl;
3749         u16 status;
3750
3751         if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
3752                 return;
3753
3754         /*
3755          * Determine type of Wakeup: note that wol
3756          * is set with all bits on by default.
3757          */
3758         if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
3759                 adapter->wol &= ~E1000_WUFC_MAG;
3760
3761         if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
3762                 adapter->wol &= ~E1000_WUFC_EX;
3763
3764         if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
3765                 adapter->wol &= ~E1000_WUFC_MC;
3766         else {
3767                 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3768                 rctl |= E1000_RCTL_MPE;
3769                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3770         }
3771
3772         if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC)))
3773                 goto pme;
3774
3775         /* Advertise the wakeup capability */
3776         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
3777         ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
3778         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
3779
3780         /* Keep the laser running on Fiber adapters */
3781         if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3782             adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
3783                 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3784                 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
3785                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext);
3786         }
3787
3788         if ((adapter->hw.mac.type == e1000_ich8lan) ||
3789             (adapter->hw.mac.type == e1000_pchlan) ||
3790             (adapter->hw.mac.type == e1000_ich9lan) ||
3791             (adapter->hw.mac.type == e1000_ich10lan))
3792                 e1000_suspend_workarounds_ich8lan(&adapter->hw);
3793
3794         if ( adapter->hw.mac.type >= e1000_pchlan) {
3795                 error = em_enable_phy_wakeup(adapter);
3796                 if (error)
3797                         goto pme;
3798         } else {
3799                 /* Enable wakeup by the MAC */
3800                 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
3801                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
3802         }
3803
3804         if (adapter->hw.phy.type == e1000_phy_igp_3)
3805                 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
3806
3807 pme:
3808         status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
3809         status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3810         if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
3811                 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3812         pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
3813
3814         return;
3815 }
3816
3817 /*
3818  * WOL in the newer chipset interfaces (pchlan)
3819  * require thing to be copied into the phy
3820  */
3821 static int
3822 em_enable_phy_wakeup(struct adapter *adapter)
3823 {
3824         struct e1000_hw *hw = &adapter->hw;
3825         u32 mreg, ret = 0;
3826         u16 preg;
3827
3828         /* copy MAC RARs to PHY RARs */
3829         e1000_copy_rx_addrs_to_phy_ich8lan(hw);
3830
3831         /* copy MAC MTA to PHY MTA */
3832         for (int i = 0; i < hw->mac.mta_reg_count; i++) {
3833                 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
3834                 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
3835                 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
3836                     (u16)((mreg >> 16) & 0xFFFF));
3837         }
3838
3839         /* configure PHY Rx Control register */
3840         e1000_read_phy_reg(hw, BM_RCTL, &preg);
3841         mreg = E1000_READ_REG(hw, E1000_RCTL);
3842         if (mreg & E1000_RCTL_UPE)
3843                 preg |= BM_RCTL_UPE;
3844         if (mreg & E1000_RCTL_MPE)
3845                 preg |= BM_RCTL_MPE;
3846         preg &= ~(BM_RCTL_MO_MASK);
3847         if (mreg & E1000_RCTL_MO_3)
3848                 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
3849                                 << BM_RCTL_MO_SHIFT);
3850         if (mreg & E1000_RCTL_BAM)
3851                 preg |= BM_RCTL_BAM;
3852         if (mreg & E1000_RCTL_PMCF)
3853                 preg |= BM_RCTL_PMCF;
3854         mreg = E1000_READ_REG(hw, E1000_CTRL);
3855         if (mreg & E1000_CTRL_RFCE)
3856                 preg |= BM_RCTL_RFCE;
3857         e1000_write_phy_reg(hw, BM_RCTL, preg);
3858
3859         /* enable PHY wakeup in MAC register */
3860         E1000_WRITE_REG(hw, E1000_WUC,
3861             E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
3862         E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol);
3863
3864         /* configure and enable PHY wakeup in PHY registers */
3865         e1000_write_phy_reg(hw, BM_WUFC, adapter->wol);
3866         e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN);
3867
3868         /* activate PHY wakeup */
3869         ret = hw->phy.ops.acquire(hw);
3870         if (ret) {
3871                 printf("Could not acquire PHY\n");
3872                 return ret;
3873         }
3874         e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3875                                  (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3876         ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
3877         if (ret) {
3878                 printf("Could not read PHY page 769\n");
3879                 goto out;
3880         }
3881         preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
3882         ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
3883         if (ret)
3884                 printf("Could not set PHY Host Wakeup bit\n");
3885 out:
3886         hw->phy.ops.release(hw);
3887
3888         return ret;
3889 }
3890
3891 static void
3892 em_if_led_func(if_ctx_t ctx, int onoff)
3893 {
3894         struct adapter *adapter = iflib_get_softc(ctx);
3895
3896         if (onoff) {
3897                 e1000_setup_led(&adapter->hw);
3898                 e1000_led_on(&adapter->hw);
3899         } else {
3900                 e1000_led_off(&adapter->hw);
3901                 e1000_cleanup_led(&adapter->hw);
3902         }
3903 }
3904
3905 /*
3906  * Disable the L0S and L1 LINK states
3907  */
3908 static void
3909 em_disable_aspm(struct adapter *adapter)
3910 {
3911         int base, reg;
3912         u16 link_cap,link_ctrl;
3913         device_t dev = adapter->dev;
3914
3915         switch (adapter->hw.mac.type) {
3916         case e1000_82573:
3917         case e1000_82574:
3918         case e1000_82583:
3919                 break;
3920         default:
3921                 return;
3922         }
3923         if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
3924                 return;
3925         reg = base + PCIER_LINK_CAP;
3926         link_cap = pci_read_config(dev, reg, 2);
3927         if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
3928                 return;
3929         reg = base + PCIER_LINK_CTL;
3930         link_ctrl = pci_read_config(dev, reg, 2);
3931         link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
3932         pci_write_config(dev, reg, link_ctrl, 2);
3933         return;
3934 }
3935
3936 /**********************************************************************
3937  *
3938  *  Update the board statistics counters.
3939  *
3940  **********************************************************************/
3941 static void
3942 em_update_stats_counters(struct adapter *adapter)
3943 {
3944         u64 prev_xoffrxc = adapter->stats.xoffrxc;
3945
3946         if(adapter->hw.phy.media_type == e1000_media_type_copper ||
3947            (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3948                 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
3949                 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
3950         }
3951         adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
3952         adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
3953         adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
3954         adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
3955
3956         adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
3957         adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
3958         adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
3959         adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
3960         adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
3961         adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
3962         adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
3963         adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
3964         /*
3965          ** For watchdog management we need to know if we have been
3966          ** paused during the last interval, so capture that here.
3967         */
3968         if (adapter->stats.xoffrxc != prev_xoffrxc)
3969                 adapter->shared->isc_pause_frames = 1;
3970         adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
3971         adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
3972         adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
3973         adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
3974         adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
3975         adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
3976         adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
3977         adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
3978         adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
3979         adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
3980         adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
3981         adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
3982
3983         /* For the 64-bit byte counters the low dword must be read first. */
3984         /* Both registers clear on the read of the high dword */
3985
3986         adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) +
3987             ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32);
3988         adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) +
3989             ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32);
3990
3991         adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
3992         adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
3993         adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
3994         adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
3995         adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
3996
3997         adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
3998         adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
3999
4000         adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
4001         adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
4002         adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
4003         adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
4004         adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
4005         adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
4006         adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
4007         adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
4008         adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
4009         adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
4010
4011         /* Interrupt Counts */
4012
4013         adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC);
4014         adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC);
4015         adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC);
4016         adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC);
4017         adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC);
4018         adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC);
4019         adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC);
4020         adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC);
4021         adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC);
4022
4023         if (adapter->hw.mac.type >= e1000_82543) {
4024                 adapter->stats.algnerrc +=
4025                 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
4026                 adapter->stats.rxerrc +=
4027                 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
4028                 adapter->stats.tncrs +=
4029                 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
4030                 adapter->stats.cexterr +=
4031                 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
4032                 adapter->stats.tsctc +=
4033                 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
4034                 adapter->stats.tsctfc +=
4035                 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
4036         }
4037 }
4038
4039 static uint64_t
4040 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
4041 {
4042         struct adapter *adapter = iflib_get_softc(ctx);
4043         struct ifnet *ifp = iflib_get_ifp(ctx);
4044
4045         switch (cnt) {
4046         case IFCOUNTER_COLLISIONS:
4047                 return (adapter->stats.colc);
4048         case IFCOUNTER_IERRORS:
4049                 return (adapter->dropped_pkts + adapter->stats.rxerrc +
4050                     adapter->stats.crcerrs + adapter->stats.algnerrc +
4051                     adapter->stats.ruc + adapter->stats.roc +
4052                     adapter->stats.mpc + adapter->stats.cexterr);
4053         case IFCOUNTER_OERRORS:
4054                 return (adapter->stats.ecol + adapter->stats.latecol +
4055                     adapter->watchdog_events);
4056         default:
4057                 return (if_get_counter_default(ifp, cnt));
4058         }
4059 }
4060
4061 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized
4062  * @ctx: iflib context
4063  * @event: event code to check
4064  *
4065  * Defaults to returning true for unknown events.
4066  *
4067  * @returns true if iflib needs to reinit the interface
4068  */
4069 static bool
4070 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
4071 {
4072         switch (event) {
4073         case IFLIB_RESTART_VLAN_CONFIG:
4074         default:
4075                 return (true);
4076         }
4077 }
4078
4079 /* Export a single 32-bit register via a read-only sysctl. */
4080 static int
4081 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
4082 {
4083         struct adapter *adapter;
4084         u_int val;
4085
4086         adapter = oidp->oid_arg1;
4087         val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2);
4088         return (sysctl_handle_int(oidp, &val, 0, req));
4089 }
4090
4091 /*
4092  * Add sysctl variables, one per statistic, to the system.
4093  */
4094 static void
4095 em_add_hw_stats(struct adapter *adapter)
4096 {
4097         device_t dev = iflib_get_dev(adapter->ctx);
4098         struct em_tx_queue *tx_que = adapter->tx_queues;
4099         struct em_rx_queue *rx_que = adapter->rx_queues;
4100
4101         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
4102         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
4103         struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
4104         struct e1000_hw_stats *stats = &adapter->stats;
4105
4106         struct sysctl_oid *stat_node, *queue_node, *int_node;
4107         struct sysctl_oid_list *stat_list, *queue_list, *int_list;
4108
4109 #define QUEUE_NAME_LEN 32
4110         char namebuf[QUEUE_NAME_LEN];
4111
4112         /* Driver Statistics */
4113         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
4114                         CTLFLAG_RD, &adapter->dropped_pkts,
4115                         "Driver dropped packets");
4116         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
4117                         CTLFLAG_RD, &adapter->link_irq,
4118                         "Link MSI-X IRQ Handled");
4119         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
4120                         CTLFLAG_RD, &adapter->rx_overruns,
4121                         "RX overruns");
4122         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
4123                         CTLFLAG_RD, &adapter->watchdog_events,
4124                         "Watchdog timeouts");
4125         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
4126             CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
4127             adapter, E1000_CTRL, em_sysctl_reg_handler, "IU",
4128             "Device Control Register");
4129         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
4130             CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
4131             adapter, E1000_RCTL, em_sysctl_reg_handler, "IU",
4132             "Receiver Control Register");
4133         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
4134                         CTLFLAG_RD, &adapter->hw.fc.high_water, 0,
4135                         "Flow Control High Watermark");
4136         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
4137                         CTLFLAG_RD, &adapter->hw.fc.low_water, 0,
4138                         "Flow Control Low Watermark");
4139
4140         for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
4141                 struct tx_ring *txr = &tx_que->txr;
4142                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
4143                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4144                     CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name");
4145                 queue_list = SYSCTL_CHILDREN(queue_node);
4146
4147                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
4148                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4149                     E1000_TDH(txr->me), em_sysctl_reg_handler, "IU",
4150                     "Transmit Descriptor Head");
4151                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
4152                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4153                     E1000_TDT(txr->me), em_sysctl_reg_handler, "IU",
4154                     "Transmit Descriptor Tail");
4155                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
4156                                 CTLFLAG_RD, &txr->tx_irq,
4157                                 "Queue MSI-X Transmit Interrupts");
4158         }
4159
4160         for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) {
4161                 struct rx_ring *rxr = &rx_que->rxr;
4162                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
4163                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4164                     CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name");
4165                 queue_list = SYSCTL_CHILDREN(queue_node);
4166
4167                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
4168                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4169                     E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU",
4170                     "Receive Descriptor Head");
4171                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
4172                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4173                     E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU",
4174                     "Receive Descriptor Tail");
4175                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
4176                                 CTLFLAG_RD, &rxr->rx_irq,
4177                                 "Queue MSI-X Receive Interrupts");
4178         }
4179
4180         /* MAC stats get their own sub node */
4181
4182         stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
4183             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics");
4184         stat_list = SYSCTL_CHILDREN(stat_node);
4185
4186         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
4187                         CTLFLAG_RD, &stats->ecol,
4188                         "Excessive collisions");
4189         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
4190                         CTLFLAG_RD, &stats->scc,
4191                         "Single collisions");
4192         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
4193                         CTLFLAG_RD, &stats->mcc,
4194                         "Multiple collisions");
4195         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
4196                         CTLFLAG_RD, &stats->latecol,
4197                         "Late collisions");
4198         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
4199                         CTLFLAG_RD, &stats->colc,
4200                         "Collision Count");
4201         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
4202                         CTLFLAG_RD, &adapter->stats.symerrs,
4203                         "Symbol Errors");
4204         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
4205                         CTLFLAG_RD, &adapter->stats.sec,
4206                         "Sequence Errors");
4207         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
4208                         CTLFLAG_RD, &adapter->stats.dc,
4209                         "Defer Count");
4210         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
4211                         CTLFLAG_RD, &adapter->stats.mpc,
4212                         "Missed Packets");
4213         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
4214                         CTLFLAG_RD, &adapter->stats.rnbc,
4215                         "Receive No Buffers");
4216         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
4217                         CTLFLAG_RD, &adapter->stats.ruc,
4218                         "Receive Undersize");
4219         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
4220                         CTLFLAG_RD, &adapter->stats.rfc,
4221                         "Fragmented Packets Received ");
4222         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
4223                         CTLFLAG_RD, &adapter->stats.roc,
4224                         "Oversized Packets Received");
4225         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
4226                         CTLFLAG_RD, &adapter->stats.rjc,
4227                         "Recevied Jabber");
4228         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
4229                         CTLFLAG_RD, &adapter->stats.rxerrc,
4230                         "Receive Errors");
4231         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
4232                         CTLFLAG_RD, &adapter->stats.crcerrs,
4233                         "CRC errors");
4234         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
4235                         CTLFLAG_RD, &adapter->stats.algnerrc,
4236                         "Alignment Errors");
4237         /* On 82575 these are collision counts */
4238         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
4239                         CTLFLAG_RD, &adapter->stats.cexterr,
4240                         "Collision/Carrier extension errors");
4241         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
4242                         CTLFLAG_RD, &adapter->stats.xonrxc,
4243                         "XON Received");
4244         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
4245                         CTLFLAG_RD, &adapter->stats.xontxc,
4246                         "XON Transmitted");
4247         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
4248                         CTLFLAG_RD, &adapter->stats.xoffrxc,
4249                         "XOFF Received");
4250         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
4251                         CTLFLAG_RD, &adapter->stats.xofftxc,
4252                         "XOFF Transmitted");
4253
4254         /* Packet Reception Stats */
4255         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
4256                         CTLFLAG_RD, &adapter->stats.tpr,
4257                         "Total Packets Received ");
4258         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
4259                         CTLFLAG_RD, &adapter->stats.gprc,
4260                         "Good Packets Received");
4261         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
4262                         CTLFLAG_RD, &adapter->stats.bprc,
4263                         "Broadcast Packets Received");
4264         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
4265                         CTLFLAG_RD, &adapter->stats.mprc,
4266                         "Multicast Packets Received");
4267         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
4268                         CTLFLAG_RD, &adapter->stats.prc64,
4269                         "64 byte frames received ");
4270         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
4271                         CTLFLAG_RD, &adapter->stats.prc127,
4272                         "65-127 byte frames received");
4273         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
4274                         CTLFLAG_RD, &adapter->stats.prc255,
4275                         "128-255 byte frames received");
4276         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
4277                         CTLFLAG_RD, &adapter->stats.prc511,
4278                         "256-511 byte frames received");
4279         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
4280                         CTLFLAG_RD, &adapter->stats.prc1023,
4281                         "512-1023 byte frames received");
4282         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
4283                         CTLFLAG_RD, &adapter->stats.prc1522,
4284                         "1023-1522 byte frames received");
4285         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
4286                         CTLFLAG_RD, &adapter->stats.gorc,
4287                         "Good Octets Received");
4288
4289         /* Packet Transmission Stats */
4290         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
4291                         CTLFLAG_RD, &adapter->stats.gotc,
4292                         "Good Octets Transmitted");
4293         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
4294                         CTLFLAG_RD, &adapter->stats.tpt,
4295                         "Total Packets Transmitted");
4296         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
4297                         CTLFLAG_RD, &adapter->stats.gptc,
4298                         "Good Packets Transmitted");
4299         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
4300                         CTLFLAG_RD, &adapter->stats.bptc,
4301                         "Broadcast Packets Transmitted");
4302         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
4303                         CTLFLAG_RD, &adapter->stats.mptc,
4304                         "Multicast Packets Transmitted");
4305         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
4306                         CTLFLAG_RD, &adapter->stats.ptc64,
4307                         "64 byte frames transmitted ");
4308         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
4309                         CTLFLAG_RD, &adapter->stats.ptc127,
4310                         "65-127 byte frames transmitted");
4311         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
4312                         CTLFLAG_RD, &adapter->stats.ptc255,
4313                         "128-255 byte frames transmitted");
4314         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
4315                         CTLFLAG_RD, &adapter->stats.ptc511,
4316                         "256-511 byte frames transmitted");
4317         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
4318                         CTLFLAG_RD, &adapter->stats.ptc1023,
4319                         "512-1023 byte frames transmitted");
4320         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
4321                         CTLFLAG_RD, &adapter->stats.ptc1522,
4322                         "1024-1522 byte frames transmitted");
4323         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
4324                         CTLFLAG_RD, &adapter->stats.tsctc,
4325                         "TSO Contexts Transmitted");
4326         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
4327                         CTLFLAG_RD, &adapter->stats.tsctfc,
4328                         "TSO Contexts Failed");
4329
4330
4331         /* Interrupt Stats */
4332
4333         int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
4334             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics");
4335         int_list = SYSCTL_CHILDREN(int_node);
4336
4337         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
4338                         CTLFLAG_RD, &adapter->stats.iac,
4339                         "Interrupt Assertion Count");
4340
4341         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
4342                         CTLFLAG_RD, &adapter->stats.icrxptc,
4343                         "Interrupt Cause Rx Pkt Timer Expire Count");
4344
4345         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
4346                         CTLFLAG_RD, &adapter->stats.icrxatc,
4347                         "Interrupt Cause Rx Abs Timer Expire Count");
4348
4349         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
4350                         CTLFLAG_RD, &adapter->stats.ictxptc,
4351                         "Interrupt Cause Tx Pkt Timer Expire Count");
4352
4353         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
4354                         CTLFLAG_RD, &adapter->stats.ictxatc,
4355                         "Interrupt Cause Tx Abs Timer Expire Count");
4356
4357         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
4358                         CTLFLAG_RD, &adapter->stats.ictxqec,
4359                         "Interrupt Cause Tx Queue Empty Count");
4360
4361         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
4362                         CTLFLAG_RD, &adapter->stats.ictxqmtc,
4363                         "Interrupt Cause Tx Queue Min Thresh Count");
4364
4365         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
4366                         CTLFLAG_RD, &adapter->stats.icrxdmtc,
4367                         "Interrupt Cause Rx Desc Min Thresh Count");
4368
4369         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
4370                         CTLFLAG_RD, &adapter->stats.icrxoc,
4371                         "Interrupt Cause Receiver Overrun Count");
4372 }
4373
4374 /**********************************************************************
4375  *
4376  *  This routine provides a way to dump out the adapter eeprom,
4377  *  often a useful debug/service tool. This only dumps the first
4378  *  32 words, stuff that matters is in that extent.
4379  *
4380  **********************************************************************/
4381 static int
4382 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4383 {
4384         struct adapter *adapter = (struct adapter *)arg1;
4385         int error;
4386         int result;
4387
4388         result = -1;
4389         error = sysctl_handle_int(oidp, &result, 0, req);
4390
4391         if (error || !req->newptr)
4392                 return (error);
4393
4394         /*
4395          * This value will cause a hex dump of the
4396          * first 32 16-bit words of the EEPROM to
4397          * the screen.
4398          */
4399         if (result == 1)
4400                 em_print_nvm_info(adapter);
4401
4402         return (error);
4403 }
4404
4405 static void
4406 em_print_nvm_info(struct adapter *adapter)
4407 {
4408         u16 eeprom_data;
4409         int i, j, row = 0;
4410
4411         /* Its a bit crude, but it gets the job done */
4412         printf("\nInterface EEPROM Dump:\n");
4413         printf("Offset\n0x0000  ");
4414         for (i = 0, j = 0; i < 32; i++, j++) {
4415                 if (j == 8) { /* Make the offset block */
4416                         j = 0; ++row;
4417                         printf("\n0x00%x0  ",row);
4418                 }
4419                 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
4420                 printf("%04x ", eeprom_data);
4421         }
4422         printf("\n");
4423 }
4424
4425 static int
4426 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4427 {
4428         struct em_int_delay_info *info;
4429         struct adapter *adapter;
4430         u32 regval;
4431         int error, usecs, ticks;
4432
4433         info = (struct em_int_delay_info *) arg1;
4434         usecs = info->value;
4435         error = sysctl_handle_int(oidp, &usecs, 0, req);
4436         if (error != 0 || req->newptr == NULL)
4437                 return (error);
4438         if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4439                 return (EINVAL);
4440         info->value = usecs;
4441         ticks = EM_USECS_TO_TICKS(usecs);
4442         if (info->offset == E1000_ITR)  /* units are 256ns here */
4443                 ticks *= 4;
4444
4445         adapter = info->adapter;
4446
4447         regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
4448         regval = (regval & ~0xffff) | (ticks & 0xffff);
4449         /* Handle a few special cases. */
4450         switch (info->offset) {
4451         case E1000_RDTR:
4452                 break;
4453         case E1000_TIDV:
4454                 if (ticks == 0) {
4455                         adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
4456                         /* Don't write 0 into the TIDV register. */
4457                         regval++;
4458                 } else
4459                         adapter->txd_cmd |= E1000_TXD_CMD_IDE;
4460                 break;
4461         }
4462         E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
4463         return (0);
4464 }
4465
4466 static void
4467 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
4468         const char *description, struct em_int_delay_info *info,
4469         int offset, int value)
4470 {
4471         info->adapter = adapter;
4472         info->offset = offset;
4473         info->value = value;
4474         SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev),
4475             SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4476             OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
4477             info, 0, em_sysctl_int_delay, "I", description);
4478 }
4479
4480 /*
4481  * Set flow control using sysctl:
4482  * Flow control values:
4483  *      0 - off
4484  *      1 - rx pause
4485  *      2 - tx pause
4486  *      3 - full
4487  */
4488 static int
4489 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4490 {
4491         int error;
4492         static int input = 3; /* default is full */
4493         struct adapter  *adapter = (struct adapter *) arg1;
4494
4495         error = sysctl_handle_int(oidp, &input, 0, req);
4496
4497         if ((error) || (req->newptr == NULL))
4498                 return (error);
4499
4500         if (input == adapter->fc) /* no change? */
4501                 return (error);
4502
4503         switch (input) {
4504         case e1000_fc_rx_pause:
4505         case e1000_fc_tx_pause:
4506         case e1000_fc_full:
4507         case e1000_fc_none:
4508                 adapter->hw.fc.requested_mode = input;
4509                 adapter->fc = input;
4510                 break;
4511         default:
4512                 /* Do nothing */
4513                 return (error);
4514         }
4515
4516         adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
4517         e1000_force_mac_fc(&adapter->hw);
4518         return (error);
4519 }
4520
4521 /*
4522  * Manage Energy Efficient Ethernet:
4523  * Control values:
4524  *     0/1 - enabled/disabled
4525  */
4526 static int
4527 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4528 {
4529         struct adapter *adapter = (struct adapter *) arg1;
4530         int error, value;
4531
4532         value = adapter->hw.dev_spec.ich8lan.eee_disable;
4533         error = sysctl_handle_int(oidp, &value, 0, req);
4534         if (error || req->newptr == NULL)
4535                 return (error);
4536         adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4537         em_if_init(adapter->ctx);
4538
4539         return (0);
4540 }
4541
4542 static int
4543 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4544 {
4545         struct adapter *adapter;
4546         int error;
4547         int result;
4548
4549         result = -1;
4550         error = sysctl_handle_int(oidp, &result, 0, req);
4551
4552         if (error || !req->newptr)
4553                 return (error);
4554
4555         if (result == 1) {
4556                 adapter = (struct adapter *) arg1;
4557                 em_print_debug_info(adapter);
4558         }
4559
4560         return (error);
4561 }
4562
4563 static int
4564 em_get_rs(SYSCTL_HANDLER_ARGS)
4565 {
4566         struct adapter *adapter = (struct adapter *) arg1;
4567         int error;
4568         int result;
4569
4570         result = 0;
4571         error = sysctl_handle_int(oidp, &result, 0, req);
4572
4573         if (error || !req->newptr || result != 1)
4574                 return (error);
4575         em_dump_rs(adapter);
4576
4577         return (error);
4578 }
4579
4580 static void
4581 em_if_debug(if_ctx_t ctx)
4582 {
4583         em_dump_rs(iflib_get_softc(ctx));
4584 }
4585
4586 /*
4587  * This routine is meant to be fluid, add whatever is
4588  * needed for debugging a problem.  -jfv
4589  */
4590 static void
4591 em_print_debug_info(struct adapter *adapter)
4592 {
4593         device_t dev = iflib_get_dev(adapter->ctx);
4594         struct ifnet *ifp = iflib_get_ifp(adapter->ctx);
4595         struct tx_ring *txr = &adapter->tx_queues->txr;
4596         struct rx_ring *rxr = &adapter->rx_queues->rxr;
4597
4598         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
4599                 printf("Interface is RUNNING ");
4600         else
4601                 printf("Interface is NOT RUNNING\n");
4602
4603         if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
4604                 printf("and INACTIVE\n");
4605         else
4606                 printf("and ACTIVE\n");
4607
4608         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
4609                 device_printf(dev, "TX Queue %d ------\n", i);
4610                 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
4611                         E1000_READ_REG(&adapter->hw, E1000_TDH(i)),
4612                         E1000_READ_REG(&adapter->hw, E1000_TDT(i)));
4613
4614         }
4615         for (int j=0; j < adapter->rx_num_queues; j++, rxr++) {
4616                 device_printf(dev, "RX Queue %d ------\n", j);
4617                 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
4618                         E1000_READ_REG(&adapter->hw, E1000_RDH(j)),
4619                         E1000_READ_REG(&adapter->hw, E1000_RDT(j)));
4620         }
4621 }
4622
4623 /*
4624  * 82574 only:
4625  * Write a new value to the EEPROM increasing the number of MSI-X
4626  * vectors from 3 to 5, for proper multiqueue support.
4627  */
4628 static void
4629 em_enable_vectors_82574(if_ctx_t ctx)
4630 {
4631         struct adapter *adapter = iflib_get_softc(ctx);
4632         struct e1000_hw *hw = &adapter->hw;
4633         device_t dev = iflib_get_dev(ctx);
4634         u16 edata;
4635
4636         e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4637         if (bootverbose)
4638                 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata);
4639         if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
4640                 device_printf(dev, "Writing to eeprom: increasing "
4641                     "reported MSI-X vectors from 3 to 5...\n");
4642                 edata &= ~(EM_NVM_MSIX_N_MASK);
4643                 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
4644                 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4645                 e1000_update_nvm_checksum(hw);
4646                 device_printf(dev, "Writing to eeprom: done\n");
4647         }
4648 }