2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <machine/_inttypes.h>
34 #define em_mac_min e1000_82547
35 #define igb_mac_min e1000_82575
37 /*********************************************************************
39 *********************************************************************/
40 char em_driver_version[] = "7.6.1-k";
42 /*********************************************************************
45 * Used by probe to select devices to load on
46 * Last field stores an index into e1000_strings
47 * Last entry must be all 0s
49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
50 *********************************************************************/
52 static pci_vendor_info_t em_vendor_info_array[] =
54 /* Intel(R) PRO/1000 Network Connection - Legacy em*/
55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"),
56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"),
57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"),
58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"),
59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"),
61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"),
62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"),
63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"),
64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"),
66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"),
67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"),
71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"),
72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"),
79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"),
80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"),
81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"),
82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"),
83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"),
85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"),
89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"),
90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"),
91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"),
92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"),
95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"),
96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"),
99 /* Intel(R) PRO/1000 Network Connection - em */
100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"),
103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"),
104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"),
105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"),
107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"),
108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"),
110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"),
113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"),
114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"),
115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"),
116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"),
117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"),
118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"),
119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"),
120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"),
121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"),
124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"),
125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"),
127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"),
128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"),
129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"),
132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"),
133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"),
134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"),
135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"),
137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"),
138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"),
139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"),
140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"),
141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"),
142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"),
143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"),
144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"),
145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"),
146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"),
147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"),
148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"),
149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"),
150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"),
151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"),
152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"),
153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"),
154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"),
155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"),
156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"),
157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"),
158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"),
159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"),
160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"),
161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"),
162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"),
163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"),
164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"),
165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"),
166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"),
167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"),
168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"),
169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) PRO/1000 Network Connection"),
170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) PRO/1000 Network Connection"),
171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) PRO/1000 Network Connection"),
172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) PRO/1000 Network Connection"),
173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) PRO/1000 Network Connection"),
174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) PRO/1000 Network Connection"),
175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) PRO/1000 Network Connection"),
176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) PRO/1000 Network Connection"),
177 /* required last entry */
181 static pci_vendor_info_t igb_vendor_info_array[] =
183 /* Intel(R) PRO/1000 Network Connection - igb */
184 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
185 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
186 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
187 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"),
188 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
189 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
190 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
191 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
192 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"),
193 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
194 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"),
195 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
196 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
197 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
198 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
199 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
200 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"),
201 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
202 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
203 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
204 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"),
205 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"),
206 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
207 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
208 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
209 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
210 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
211 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
212 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"),
213 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"),
214 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
215 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
216 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
217 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
218 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
219 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
220 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
221 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
222 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
223 /* required last entry */
227 /*********************************************************************
228 * Function prototypes
229 *********************************************************************/
230 static void *em_register(device_t dev);
231 static void *igb_register(device_t dev);
232 static int em_if_attach_pre(if_ctx_t ctx);
233 static int em_if_attach_post(if_ctx_t ctx);
234 static int em_if_detach(if_ctx_t ctx);
235 static int em_if_shutdown(if_ctx_t ctx);
236 static int em_if_suspend(if_ctx_t ctx);
237 static int em_if_resume(if_ctx_t ctx);
239 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets);
240 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets);
241 static void em_if_queues_free(if_ctx_t ctx);
243 static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
244 static void em_if_init(if_ctx_t ctx);
245 static void em_if_stop(if_ctx_t ctx);
246 static void em_if_media_status(if_ctx_t, struct ifmediareq *);
247 static int em_if_media_change(if_ctx_t ctx);
248 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu);
249 static void em_if_timer(if_ctx_t ctx, uint16_t qid);
250 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag);
251 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag);
253 static void em_identify_hardware(if_ctx_t ctx);
254 static int em_allocate_pci_resources(if_ctx_t ctx);
255 static void em_free_pci_resources(if_ctx_t ctx);
256 static void em_reset(if_ctx_t ctx);
257 static int em_setup_interface(if_ctx_t ctx);
258 static int em_setup_msix(if_ctx_t ctx);
260 static void em_initialize_transmit_unit(if_ctx_t ctx);
261 static void em_initialize_receive_unit(if_ctx_t ctx);
263 static void em_if_enable_intr(if_ctx_t ctx);
264 static void em_if_disable_intr(if_ctx_t ctx);
265 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
266 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
267 static void em_if_multi_set(if_ctx_t ctx);
268 static void em_if_update_admin_status(if_ctx_t ctx);
269 static void em_if_debug(if_ctx_t ctx);
270 static void em_update_stats_counters(struct adapter *);
271 static void em_add_hw_stats(struct adapter *adapter);
272 static int em_if_set_promisc(if_ctx_t ctx, int flags);
273 static void em_setup_vlan_hw_support(struct adapter *);
274 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
275 static void em_print_nvm_info(struct adapter *);
276 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
277 static int em_get_rs(SYSCTL_HANDLER_ARGS);
278 static void em_print_debug_info(struct adapter *);
279 static int em_is_valid_ether_addr(u8 *);
280 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
281 static void em_add_int_delay_sysctl(struct adapter *, const char *,
282 const char *, struct em_int_delay_info *, int, int);
283 /* Management and WOL Support */
284 static void em_init_manageability(struct adapter *);
285 static void em_release_manageability(struct adapter *);
286 static void em_get_hw_control(struct adapter *);
287 static void em_release_hw_control(struct adapter *);
288 static void em_get_wakeup(if_ctx_t ctx);
289 static void em_enable_wakeup(if_ctx_t ctx);
290 static int em_enable_phy_wakeup(struct adapter *);
291 static void em_disable_aspm(struct adapter *);
293 int em_intr(void *arg);
294 static void em_disable_promisc(if_ctx_t ctx);
297 static int em_if_msix_intr_assign(if_ctx_t, int);
298 static int em_msix_link(void *);
299 static void em_handle_link(void *context);
301 static void em_enable_vectors_82574(if_ctx_t);
303 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS);
304 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS);
305 static void em_if_led_func(if_ctx_t ctx, int onoff);
307 static int em_get_regs(SYSCTL_HANDLER_ARGS);
309 static void lem_smartspeed(struct adapter *adapter);
310 static void igb_configure_queues(struct adapter *adapter);
313 /*********************************************************************
314 * FreeBSD Device Interface Entry Points
315 *********************************************************************/
316 static device_method_t em_methods[] = {
317 /* Device interface */
318 DEVMETHOD(device_register, em_register),
319 DEVMETHOD(device_probe, iflib_device_probe),
320 DEVMETHOD(device_attach, iflib_device_attach),
321 DEVMETHOD(device_detach, iflib_device_detach),
322 DEVMETHOD(device_shutdown, iflib_device_shutdown),
323 DEVMETHOD(device_suspend, iflib_device_suspend),
324 DEVMETHOD(device_resume, iflib_device_resume),
328 static device_method_t igb_methods[] = {
329 /* Device interface */
330 DEVMETHOD(device_register, igb_register),
331 DEVMETHOD(device_probe, iflib_device_probe),
332 DEVMETHOD(device_attach, iflib_device_attach),
333 DEVMETHOD(device_detach, iflib_device_detach),
334 DEVMETHOD(device_shutdown, iflib_device_shutdown),
335 DEVMETHOD(device_suspend, iflib_device_suspend),
336 DEVMETHOD(device_resume, iflib_device_resume),
341 static driver_t em_driver = {
342 "em", em_methods, sizeof(struct adapter),
345 static devclass_t em_devclass;
346 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
348 MODULE_DEPEND(em, pci, 1, 1, 1);
349 MODULE_DEPEND(em, ether, 1, 1, 1);
350 MODULE_DEPEND(em, iflib, 1, 1, 1);
352 IFLIB_PNP_INFO(pci, em, em_vendor_info_array);
354 static driver_t igb_driver = {
355 "igb", igb_methods, sizeof(struct adapter),
358 static devclass_t igb_devclass;
359 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
361 MODULE_DEPEND(igb, pci, 1, 1, 1);
362 MODULE_DEPEND(igb, ether, 1, 1, 1);
363 MODULE_DEPEND(igb, iflib, 1, 1, 1);
365 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array);
367 static device_method_t em_if_methods[] = {
368 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
369 DEVMETHOD(ifdi_attach_post, em_if_attach_post),
370 DEVMETHOD(ifdi_detach, em_if_detach),
371 DEVMETHOD(ifdi_shutdown, em_if_shutdown),
372 DEVMETHOD(ifdi_suspend, em_if_suspend),
373 DEVMETHOD(ifdi_resume, em_if_resume),
374 DEVMETHOD(ifdi_init, em_if_init),
375 DEVMETHOD(ifdi_stop, em_if_stop),
376 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
377 DEVMETHOD(ifdi_intr_enable, em_if_enable_intr),
378 DEVMETHOD(ifdi_intr_disable, em_if_disable_intr),
379 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
380 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
381 DEVMETHOD(ifdi_queues_free, em_if_queues_free),
382 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
383 DEVMETHOD(ifdi_multi_set, em_if_multi_set),
384 DEVMETHOD(ifdi_media_status, em_if_media_status),
385 DEVMETHOD(ifdi_media_change, em_if_media_change),
386 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
387 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
388 DEVMETHOD(ifdi_timer, em_if_timer),
389 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
390 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
391 DEVMETHOD(ifdi_get_counter, em_if_get_counter),
392 DEVMETHOD(ifdi_led_func, em_if_led_func),
393 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable),
394 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable),
395 DEVMETHOD(ifdi_debug, em_if_debug),
400 * note that if (adapter->msix_mem) is replaced by:
401 * if (adapter->intr_type == IFLIB_INTR_MSIX)
403 static driver_t em_if_driver = {
404 "em_if", em_if_methods, sizeof(struct adapter)
407 /*********************************************************************
408 * Tunable default values.
409 *********************************************************************/
411 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000)
412 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024)
414 #define MAX_INTS_PER_SEC 8000
415 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256))
417 /* Allow common code without TSO */
422 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters");
424 static int em_disable_crc_stripping = 0;
425 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
426 &em_disable_crc_stripping, 0, "Disable CRC Stripping");
428 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
429 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
430 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
431 0, "Default transmit interrupt delay in usecs");
432 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
433 0, "Default receive interrupt delay in usecs");
435 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
436 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
437 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
438 &em_tx_abs_int_delay_dflt, 0,
439 "Default transmit interrupt delay limit in usecs");
440 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
441 &em_rx_abs_int_delay_dflt, 0,
442 "Default receive interrupt delay limit in usecs");
444 static int em_smart_pwr_down = FALSE;
445 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
446 0, "Set to true to leave smart power down enabled on newer adapters");
448 /* Controls whether promiscuous also shows bad packets */
449 static int em_debug_sbp = TRUE;
450 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
451 "Show bad packets in promiscuous mode");
453 /* How many packets rxeof tries to clean at a time */
454 static int em_rx_process_limit = 100;
455 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
456 &em_rx_process_limit, 0,
457 "Maximum number of received packets to process "
458 "at a time, -1 means unlimited");
460 /* Energy efficient ethernet - default to OFF */
461 static int eee_setting = 1;
462 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
463 "Enable Energy Efficient Ethernet");
466 ** Tuneable Interrupt rate
468 static int em_max_interrupt_rate = 8000;
469 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
470 &em_max_interrupt_rate, 0, "Maximum interrupts per second");
474 /* Global used in WOL setup with multiport cards */
475 static int global_quad_port_a = 0;
477 extern struct if_txrx igb_txrx;
478 extern struct if_txrx em_txrx;
479 extern struct if_txrx lem_txrx;
481 static struct if_shared_ctx em_sctx_init = {
482 .isc_magic = IFLIB_MAGIC,
483 .isc_q_align = PAGE_SIZE,
484 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
485 .isc_tx_maxsegsize = PAGE_SIZE,
486 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
487 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
488 .isc_rx_maxsize = MJUM9BYTES,
489 .isc_rx_nsegments = 1,
490 .isc_rx_maxsegsize = MJUM9BYTES,
494 .isc_admin_intrcnt = 1,
495 .isc_vendor_info = em_vendor_info_array,
496 .isc_driver_version = em_driver_version,
497 .isc_driver = &em_if_driver,
498 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
500 .isc_nrxd_min = {EM_MIN_RXD},
501 .isc_ntxd_min = {EM_MIN_TXD},
502 .isc_nrxd_max = {EM_MAX_RXD},
503 .isc_ntxd_max = {EM_MAX_TXD},
504 .isc_nrxd_default = {EM_DEFAULT_RXD},
505 .isc_ntxd_default = {EM_DEFAULT_TXD},
508 if_shared_ctx_t em_sctx = &em_sctx_init;
510 static struct if_shared_ctx igb_sctx_init = {
511 .isc_magic = IFLIB_MAGIC,
512 .isc_q_align = PAGE_SIZE,
513 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
514 .isc_tx_maxsegsize = PAGE_SIZE,
515 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
516 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
517 .isc_rx_maxsize = MJUM9BYTES,
518 .isc_rx_nsegments = 1,
519 .isc_rx_maxsegsize = MJUM9BYTES,
523 .isc_admin_intrcnt = 1,
524 .isc_vendor_info = igb_vendor_info_array,
525 .isc_driver_version = em_driver_version,
526 .isc_driver = &em_if_driver,
527 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
529 .isc_nrxd_min = {EM_MIN_RXD},
530 .isc_ntxd_min = {EM_MIN_TXD},
531 .isc_nrxd_max = {IGB_MAX_RXD},
532 .isc_ntxd_max = {IGB_MAX_TXD},
533 .isc_nrxd_default = {EM_DEFAULT_RXD},
534 .isc_ntxd_default = {EM_DEFAULT_TXD},
537 if_shared_ctx_t igb_sctx = &igb_sctx_init;
539 /*****************************************************************
543 ****************************************************************/
544 #define IGB_REGS_LEN 739
546 static int em_get_regs(SYSCTL_HANDLER_ARGS)
548 struct adapter *adapter = (struct adapter *)arg1;
549 struct e1000_hw *hw = &adapter->hw;
554 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK);
555 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
557 rc = sysctl_wire_old_buffer(req, 0);
560 free(regs_buff, M_DEVBUF);
564 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
567 free(regs_buff, M_DEVBUF);
571 /* General Registers */
572 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
573 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
574 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
575 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
576 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
577 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
578 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
579 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
580 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
581 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
582 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
583 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
584 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
585 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
586 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
587 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
588 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
589 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
590 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
591 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
592 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
593 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
595 sbuf_printf(sb, "General Registers\n");
596 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
597 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
598 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]);
600 sbuf_printf(sb, "Interrupt Registers\n");
601 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
603 sbuf_printf(sb, "RX Registers\n");
604 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
605 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
606 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
607 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
608 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
609 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
610 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
612 sbuf_printf(sb, "TX Registers\n");
613 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
614 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
615 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
616 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
617 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
618 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
619 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
620 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
621 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
622 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
623 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
625 free(regs_buff, M_DEVBUF);
629 if_softc_ctx_t scctx = adapter->shared;
630 struct rx_ring *rxr = &rx_que->rxr;
631 struct tx_ring *txr = &tx_que->txr;
632 int ntxd = scctx->isc_ntxd[0];
633 int nrxd = scctx->isc_nrxd[0];
636 for (j = 0; j < nrxd; j++) {
637 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
638 u32 length = le32toh(rxr->rx_base[j].wb.upper.length);
639 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
642 for (j = 0; j < min(ntxd, 256); j++) {
643 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
645 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n",
646 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
647 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
653 rc = sbuf_finish(sb);
659 em_register(device_t dev)
665 igb_register(device_t dev)
671 em_set_num_queues(if_ctx_t ctx)
673 struct adapter *adapter = iflib_get_softc(ctx);
676 /* Sanity check based on HW */
677 switch (adapter->hw.mac.type) {
701 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
702 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER
705 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
706 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \
707 IFCAP_LRO | IFCAP_VLAN_HWTSO
710 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
711 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \
712 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6;
714 /*********************************************************************
715 * Device initialization routine
717 * The attach entry point is called when the driver is being loaded.
718 * This routine identifies the type of hardware, allocates all resources
719 * and initializes the hardware.
721 * return 0 on success, positive on failure
722 *********************************************************************/
725 em_if_attach_pre(if_ctx_t ctx)
727 struct adapter *adapter;
728 if_softc_ctx_t scctx;
733 INIT_DEBUGOUT("em_if_attach_pre begin");
734 dev = iflib_get_dev(ctx);
735 adapter = iflib_get_softc(ctx);
737 if (resource_disabled("em", device_get_unit(dev))) {
738 device_printf(dev, "Disabled by device hint\n");
742 adapter->ctx = adapter->osdep.ctx = ctx;
743 adapter->dev = adapter->osdep.dev = dev;
744 scctx = adapter->shared = iflib_get_softc_ctx(ctx);
745 adapter->media = iflib_get_media(ctx);
748 adapter->tx_process_limit = scctx->isc_ntxd[0];
751 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
752 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
753 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
754 em_sysctl_nvm_info, "I", "NVM Information");
756 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
757 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
758 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
759 em_sysctl_debug_info, "I", "Debug Information");
761 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
762 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
763 OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
764 em_set_flowcntl, "I", "Flow Control");
766 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
767 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
768 OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0,
769 em_get_regs, "A", "Dump Registers");
771 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
772 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
773 OID_AUTO, "rs_dump", CTLTYPE_INT | CTLFLAG_RW, adapter, 0,
774 em_get_rs, "I", "Dump RS indexes");
776 /* Determine hardware and mac info */
777 em_identify_hardware(ctx);
779 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR);
780 scctx->isc_tx_nsegments = EM_MAX_SCATTER;
781 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
782 device_printf(dev, "attach_pre capping queues at %d\n", scctx->isc_ntxqsets_max);
784 if (adapter->hw.mac.type >= igb_mac_min) {
787 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
788 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
789 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
790 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
791 scctx->isc_txrx = &igb_txrx;
792 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
793 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
794 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
795 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS;
796 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | CSUM_IP6_TCP \
797 | CSUM_IP6_UDP | CSUM_IP6_TCP;
798 if (adapter->hw.mac.type != e1000_82575)
799 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
802 ** Some new devices, as with ixgbe, now may
803 ** use a different BAR, so we need to keep
804 ** track of which is used.
806 try_second_bar = pci_read_config(dev, scctx->isc_msix_bar, 4);
807 if (try_second_bar == 0)
808 scctx->isc_msix_bar += 4;
809 } else if (adapter->hw.mac.type >= em_mac_min) {
810 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
811 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
812 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
813 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
814 scctx->isc_txrx = &em_txrx;
815 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
816 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
817 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
818 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS;
820 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO}
821 * by default as we don't have workarounds for all associated
822 * silicon errata. E. g., with several MACs such as 82573E,
823 * TSO only works at Gigabit speed and otherwise can cause the
824 * hardware to hang (which also would be next to impossible to
825 * work around given that already queued TSO-using descriptors
826 * would need to be flushed and vlan(4) reconfigured at runtime
827 * in case of a link speed change). Moreover, MACs like 82579
828 * still can hang at Gigabit even with all publicly documented
829 * TSO workarounds implemented. Generally, the penality of
830 * these workarounds is rather high and may involve copying
831 * mbuf data around so advantages of TSO lapse. Still, TSO may
832 * work for a few MACs of this class - at least when sticking
833 * with Gigabit - in which case users may enable TSO manually.
835 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
836 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
838 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
839 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
840 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
841 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
842 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP;
843 scctx->isc_txrx = &lem_txrx;
844 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS;
845 if (adapter->hw.mac.type < e1000_82543)
846 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
847 scctx->isc_msix_bar = 0;
850 /* Setup PCI resources */
851 if (em_allocate_pci_resources(ctx)) {
852 device_printf(dev, "Allocation of PCI resources failed\n");
858 ** For ICH8 and family we need to
859 ** map the flash memory, and this
860 ** must happen after the MAC is
863 if ((hw->mac.type == e1000_ich8lan) ||
864 (hw->mac.type == e1000_ich9lan) ||
865 (hw->mac.type == e1000_ich10lan) ||
866 (hw->mac.type == e1000_pchlan) ||
867 (hw->mac.type == e1000_pch2lan) ||
868 (hw->mac.type == e1000_pch_lpt)) {
869 int rid = EM_BAR_TYPE_FLASH;
870 adapter->flash = bus_alloc_resource_any(dev,
871 SYS_RES_MEMORY, &rid, RF_ACTIVE);
872 if (adapter->flash == NULL) {
873 device_printf(dev, "Mapping of Flash failed\n");
877 /* This is used in the shared code */
878 hw->flash_address = (u8 *)adapter->flash;
879 adapter->osdep.flash_bus_space_tag =
880 rman_get_bustag(adapter->flash);
881 adapter->osdep.flash_bus_space_handle =
882 rman_get_bushandle(adapter->flash);
885 ** In the new SPT device flash is not a
886 ** separate BAR, rather it is also in BAR0,
887 ** so use the same tag and an offset handle for the
888 ** FLASH read/write macros in the shared code.
890 else if (hw->mac.type >= e1000_pch_spt) {
891 adapter->osdep.flash_bus_space_tag =
892 adapter->osdep.mem_bus_space_tag;
893 adapter->osdep.flash_bus_space_handle =
894 adapter->osdep.mem_bus_space_handle
895 + E1000_FLASH_BASE_ADDR;
898 /* Do Shared Code initialization */
899 error = e1000_setup_init_funcs(hw, TRUE);
901 device_printf(dev, "Setup of Shared code failed, error %d\n",
908 e1000_get_bus_info(hw);
910 /* Set up some sysctls for the tunable interrupt delays */
911 em_add_int_delay_sysctl(adapter, "rx_int_delay",
912 "receive interrupt delay in usecs", &adapter->rx_int_delay,
913 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
914 em_add_int_delay_sysctl(adapter, "tx_int_delay",
915 "transmit interrupt delay in usecs", &adapter->tx_int_delay,
916 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
917 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
918 "receive interrupt delay limit in usecs",
919 &adapter->rx_abs_int_delay,
920 E1000_REGISTER(hw, E1000_RADV),
921 em_rx_abs_int_delay_dflt);
922 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
923 "transmit interrupt delay limit in usecs",
924 &adapter->tx_abs_int_delay,
925 E1000_REGISTER(hw, E1000_TADV),
926 em_tx_abs_int_delay_dflt);
927 em_add_int_delay_sysctl(adapter, "itr",
928 "interrupt delay limit in usecs/4",
930 E1000_REGISTER(hw, E1000_ITR),
933 hw->mac.autoneg = DO_AUTO_NEG;
934 hw->phy.autoneg_wait_to_complete = FALSE;
935 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
937 if (adapter->hw.mac.type < em_mac_min) {
938 e1000_init_script_state_82541(&adapter->hw, TRUE);
939 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
942 if (hw->phy.media_type == e1000_media_type_copper) {
943 hw->phy.mdix = AUTO_ALL_MODES;
944 hw->phy.disable_polarity_correction = FALSE;
945 hw->phy.ms_type = EM_MASTER_SLAVE;
949 * Set the frame limits assuming
950 * standard ethernet sized frames.
952 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
953 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
956 * This controls when hardware reports transmit completion
959 hw->mac.report_tx_early = 1;
961 /* Allocate multicast array memory. */
962 adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN *
963 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
964 if (adapter->mta == NULL) {
965 device_printf(dev, "Can not allocate multicast setup array\n");
970 /* Check SOL/IDER usage */
971 if (e1000_check_reset_block(hw))
972 device_printf(dev, "PHY reset is blocked"
973 " due to SOL/IDER session.\n");
975 /* Sysctl for setting Energy Efficient Ethernet */
976 hw->dev_spec.ich8lan.eee_disable = eee_setting;
977 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
978 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
979 OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW,
980 adapter, 0, em_sysctl_eee, "I",
981 "Disable Energy Efficient Ethernet");
984 ** Start from a known state, this is
985 ** important in reading the nvm and
990 /* Make sure we have a good EEPROM before we read from it */
991 if (e1000_validate_nvm_checksum(hw) < 0) {
993 ** Some PCI-E parts fail the first check due to
994 ** the link being in sleep state, call it again,
995 ** if it fails a second time its a real issue.
997 if (e1000_validate_nvm_checksum(hw) < 0) {
999 "The EEPROM Checksum Is Not Valid\n");
1005 /* Copy the permanent MAC address out of the EEPROM */
1006 if (e1000_read_mac_addr(hw) < 0) {
1007 device_printf(dev, "EEPROM read error while reading MAC"
1013 if (!em_is_valid_ether_addr(hw->mac.addr)) {
1014 device_printf(dev, "Invalid MAC address\n");
1019 /* Disable ULP support */
1020 e1000_disable_ulp_lpt_lp(hw, TRUE);
1023 * Get Wake-on-Lan and Management info for later use
1027 /* Enable only WOL MAGIC by default */
1028 scctx->isc_capenable &= ~IFCAP_WOL;
1029 if (adapter->wol != 0)
1030 scctx->isc_capenable |= IFCAP_WOL_MAGIC;
1032 iflib_set_mac(ctx, hw->mac.addr);
1037 em_release_hw_control(adapter);
1039 em_free_pci_resources(ctx);
1040 free(adapter->mta, M_DEVBUF);
1046 em_if_attach_post(if_ctx_t ctx)
1048 struct adapter *adapter = iflib_get_softc(ctx);
1049 struct e1000_hw *hw = &adapter->hw;
1052 /* Setup OS specific network interface */
1053 error = em_setup_interface(ctx);
1060 /* Initialize statistics */
1061 em_update_stats_counters(adapter);
1062 hw->mac.get_link_status = 1;
1063 em_if_update_admin_status(ctx);
1064 em_add_hw_stats(adapter);
1066 /* Non-AMT based hardware can now take control from firmware */
1067 if (adapter->has_manage && !adapter->has_amt)
1068 em_get_hw_control(adapter);
1070 INIT_DEBUGOUT("em_if_attach_post: end");
1075 em_release_hw_control(adapter);
1076 em_free_pci_resources(ctx);
1077 em_if_queues_free(ctx);
1078 free(adapter->mta, M_DEVBUF);
1083 /*********************************************************************
1084 * Device removal routine
1086 * The detach entry point is called when the driver is being removed.
1087 * This routine stops the adapter and deallocates all the resources
1088 * that were allocated for driver operation.
1090 * return 0 on success, positive on failure
1091 *********************************************************************/
1094 em_if_detach(if_ctx_t ctx)
1096 struct adapter *adapter = iflib_get_softc(ctx);
1098 INIT_DEBUGOUT("em_detach: begin");
1100 e1000_phy_hw_reset(&adapter->hw);
1102 em_release_manageability(adapter);
1103 em_release_hw_control(adapter);
1104 em_free_pci_resources(ctx);
1109 /*********************************************************************
1111 * Shutdown entry point
1113 **********************************************************************/
1116 em_if_shutdown(if_ctx_t ctx)
1118 return em_if_suspend(ctx);
1122 * Suspend/resume device methods.
1125 em_if_suspend(if_ctx_t ctx)
1127 struct adapter *adapter = iflib_get_softc(ctx);
1129 em_release_manageability(adapter);
1130 em_release_hw_control(adapter);
1131 em_enable_wakeup(ctx);
1136 em_if_resume(if_ctx_t ctx)
1138 struct adapter *adapter = iflib_get_softc(ctx);
1140 if (adapter->hw.mac.type == e1000_pch2lan)
1141 e1000_resume_workarounds_pchlan(&adapter->hw);
1143 em_init_manageability(adapter);
1149 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1152 struct adapter *adapter = iflib_get_softc(ctx);
1153 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1155 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1157 switch (adapter->hw.mac.type) {
1161 case e1000_ich10lan:
1168 case e1000_80003es2lan:
1169 /* 9K Jumbo Frame size */
1170 max_frame_size = 9234;
1173 max_frame_size = 4096;
1177 /* Adapters that do not support jumbo frames */
1178 max_frame_size = ETHER_MAX_LEN;
1181 if (adapter->hw.mac.type >= igb_mac_min)
1182 max_frame_size = 9234;
1184 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1186 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1190 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
1191 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1195 /*********************************************************************
1198 * This routine is used in two ways. It is used by the stack as
1199 * init entry point in network interface structure. It is also used
1200 * by the driver as a hw/sw initialization routine to get to a
1203 * return 0 on success, positive on failure
1204 **********************************************************************/
1207 em_if_init(if_ctx_t ctx)
1209 struct adapter *adapter = iflib_get_softc(ctx);
1210 struct ifnet *ifp = iflib_get_ifp(ctx);
1211 struct em_tx_queue *tx_que;
1213 INIT_DEBUGOUT("em_if_init: begin");
1215 /* Get the latest mac address, User can use a LAA */
1216 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr,
1219 /* Put the address into the Receive Address Array */
1220 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1223 * With the 82571 adapter, RAR[0] may be overwritten
1224 * when the other port is reset, we make a duplicate
1225 * in RAR[14] for that eventuality, this assures
1226 * the interface continues to function.
1228 if (adapter->hw.mac.type == e1000_82571) {
1229 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1230 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1231 E1000_RAR_ENTRIES - 1);
1235 /* Initialize the hardware */
1237 em_if_update_admin_status(ctx);
1239 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) {
1240 struct tx_ring *txr = &tx_que->txr;
1242 txr->tx_rs_cidx = txr->tx_rs_pidx = txr->tx_cidx_processed = 0;
1245 /* Setup VLAN support, basic and offload if available */
1246 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1248 /* Clear bad data from Rx FIFOs */
1249 if (adapter->hw.mac.type >= igb_mac_min)
1250 e1000_rx_fifo_flush_82575(&adapter->hw);
1252 /* Configure for OS presence */
1253 em_init_manageability(adapter);
1255 /* Prepare transmit descriptors and buffers */
1256 em_initialize_transmit_unit(ctx);
1258 /* Setup Multicast table */
1259 em_if_multi_set(ctx);
1262 * Figure out the desired mbuf
1263 * pool for doing jumbos
1265 if (adapter->hw.mac.max_frame_size <= 2048)
1266 adapter->rx_mbuf_sz = MCLBYTES;
1267 #ifndef CONTIGMALLOC_WORKS
1269 adapter->rx_mbuf_sz = MJUMPAGESIZE;
1271 else if (adapter->hw.mac.max_frame_size <= 4096)
1272 adapter->rx_mbuf_sz = MJUMPAGESIZE;
1274 adapter->rx_mbuf_sz = MJUM9BYTES;
1276 em_initialize_receive_unit(ctx);
1278 /* Use real VLAN Filter support? */
1279 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1280 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
1281 /* Use real VLAN Filter support */
1282 em_setup_vlan_hw_support(adapter);
1285 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1286 ctrl |= E1000_CTRL_VME;
1287 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1291 /* Don't lose promiscuous settings */
1292 em_if_set_promisc(ctx, IFF_PROMISC);
1293 e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1295 /* MSI/X configuration for 82574 */
1296 if (adapter->hw.mac.type == e1000_82574) {
1297 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1299 tmp |= E1000_CTRL_EXT_PBA_CLR;
1300 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1301 /* Set the IVAR - interrupt vector routing. */
1302 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars);
1303 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1304 igb_configure_queues(adapter);
1306 /* this clears any pending interrupts */
1307 E1000_READ_REG(&adapter->hw, E1000_ICR);
1308 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC);
1310 /* AMT based hardware can now take control from firmware */
1311 if (adapter->has_manage && adapter->has_amt)
1312 em_get_hw_control(adapter);
1314 /* Set Energy Efficient Ethernet */
1315 if (adapter->hw.mac.type >= igb_mac_min &&
1316 adapter->hw.phy.media_type == e1000_media_type_copper) {
1317 if (adapter->hw.mac.type == e1000_i354)
1318 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
1320 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
1324 /*********************************************************************
1326 * Fast Legacy/MSI Combined Interrupt Service routine
1328 *********************************************************************/
1332 struct adapter *adapter = arg;
1333 if_ctx_t ctx = adapter->ctx;
1336 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1338 if (adapter->intr_type != IFLIB_INTR_LEGACY)
1341 if (reg_icr == 0xffffffff)
1342 return FILTER_STRAY;
1344 /* Definitely not our interrupt. */
1346 return FILTER_STRAY;
1349 * Starting with the 82571 chip, bit 31 should be used to
1350 * determine whether the interrupt belongs to us.
1352 if (adapter->hw.mac.type >= e1000_82571 &&
1353 (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1354 return FILTER_STRAY;
1357 /* Link status change */
1358 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1359 adapter->hw.mac.get_link_status = 1;
1360 iflib_admin_intr_deferred(ctx);
1363 if (reg_icr & E1000_ICR_RXO)
1364 adapter->rx_overruns++;
1366 return (FILTER_SCHEDULE_THREAD);
1370 igb_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq)
1372 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims);
1376 em_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq)
1378 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims);
1382 igb_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq)
1384 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims);
1388 em_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq)
1390 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims);
1394 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1396 struct adapter *adapter = iflib_get_softc(ctx);
1397 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1399 if (adapter->hw.mac.type >= igb_mac_min)
1400 igb_rx_enable_queue(adapter, rxq);
1402 em_rx_enable_queue(adapter, rxq);
1407 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1409 struct adapter *adapter = iflib_get_softc(ctx);
1410 struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1412 if (adapter->hw.mac.type >= igb_mac_min)
1413 igb_tx_enable_queue(adapter, txq);
1415 em_tx_enable_queue(adapter, txq);
1419 /*********************************************************************
1421 * MSIX RX Interrupt Service routine
1423 **********************************************************************/
1425 em_msix_que(void *arg)
1427 struct em_rx_queue *que = arg;
1431 return (FILTER_SCHEDULE_THREAD);
1434 /*********************************************************************
1436 * MSIX Link Fast Interrupt Service routine
1438 **********************************************************************/
1440 em_msix_link(void *arg)
1442 struct adapter *adapter = arg;
1445 ++adapter->link_irq;
1446 MPASS(adapter->hw.back != NULL);
1447 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1449 if (reg_icr & E1000_ICR_RXO)
1450 adapter->rx_overruns++;
1452 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1453 em_handle_link(adapter->ctx);
1455 E1000_WRITE_REG(&adapter->hw, E1000_IMS,
1456 EM_MSIX_LINK | E1000_IMS_LSC);
1457 if (adapter->hw.mac.type >= igb_mac_min)
1458 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1462 * Because we must read the ICR for this interrupt
1463 * it may clear other causes using autoclear, for
1464 * this reason we simply create a soft interrupt
1465 * for all these vectors.
1467 if (reg_icr && adapter->hw.mac.type < igb_mac_min) {
1468 E1000_WRITE_REG(&adapter->hw,
1469 E1000_ICS, adapter->ims);
1472 return (FILTER_HANDLED);
1476 em_handle_link(void *context)
1478 if_ctx_t ctx = context;
1479 struct adapter *adapter = iflib_get_softc(ctx);
1481 adapter->hw.mac.get_link_status = 1;
1482 iflib_admin_intr_deferred(ctx);
1486 /*********************************************************************
1488 * Media Ioctl callback
1490 * This routine is called whenever the user queries the status of
1491 * the interface using ifconfig.
1493 **********************************************************************/
1495 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1497 struct adapter *adapter = iflib_get_softc(ctx);
1498 u_char fiber_type = IFM_1000_SX;
1500 INIT_DEBUGOUT("em_if_media_status: begin");
1502 iflib_admin_intr_deferred(ctx);
1504 ifmr->ifm_status = IFM_AVALID;
1505 ifmr->ifm_active = IFM_ETHER;
1507 if (!adapter->link_active) {
1511 ifmr->ifm_status |= IFM_ACTIVE;
1513 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
1514 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1515 if (adapter->hw.mac.type == e1000_82545)
1516 fiber_type = IFM_1000_LX;
1517 ifmr->ifm_active |= fiber_type | IFM_FDX;
1519 switch (adapter->link_speed) {
1521 ifmr->ifm_active |= IFM_10_T;
1524 ifmr->ifm_active |= IFM_100_TX;
1527 ifmr->ifm_active |= IFM_1000_T;
1530 if (adapter->link_duplex == FULL_DUPLEX)
1531 ifmr->ifm_active |= IFM_FDX;
1533 ifmr->ifm_active |= IFM_HDX;
1537 /*********************************************************************
1539 * Media Ioctl callback
1541 * This routine is called when the user changes speed/duplex using
1542 * media/mediopt option with ifconfig.
1544 **********************************************************************/
1546 em_if_media_change(if_ctx_t ctx)
1548 struct adapter *adapter = iflib_get_softc(ctx);
1549 struct ifmedia *ifm = iflib_get_media(ctx);
1551 INIT_DEBUGOUT("em_if_media_change: begin");
1553 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1556 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1558 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1559 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1564 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1565 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1568 adapter->hw.mac.autoneg = FALSE;
1569 adapter->hw.phy.autoneg_advertised = 0;
1570 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1571 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1573 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1576 adapter->hw.mac.autoneg = FALSE;
1577 adapter->hw.phy.autoneg_advertised = 0;
1578 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1579 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1581 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1584 device_printf(adapter->dev, "Unsupported media type\n");
1593 em_if_set_promisc(if_ctx_t ctx, int flags)
1595 struct adapter *adapter = iflib_get_softc(ctx);
1598 em_disable_promisc(ctx);
1600 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1602 if (flags & IFF_PROMISC) {
1603 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1604 /* Turn this on if you want to see bad packets */
1606 reg_rctl |= E1000_RCTL_SBP;
1607 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1608 } else if (flags & IFF_ALLMULTI) {
1609 reg_rctl |= E1000_RCTL_MPE;
1610 reg_rctl &= ~E1000_RCTL_UPE;
1611 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1617 em_disable_promisc(if_ctx_t ctx)
1619 struct adapter *adapter = iflib_get_softc(ctx);
1620 struct ifnet *ifp = iflib_get_ifp(ctx);
1624 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1625 reg_rctl &= (~E1000_RCTL_UPE);
1626 if (if_getflags(ifp) & IFF_ALLMULTI)
1627 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1629 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES);
1630 /* Don't disable if in MAX groups */
1631 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1632 reg_rctl &= (~E1000_RCTL_MPE);
1633 reg_rctl &= (~E1000_RCTL_SBP);
1634 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1638 /*********************************************************************
1641 * This routine is called whenever multicast address list is updated.
1643 **********************************************************************/
1646 em_if_multi_set(if_ctx_t ctx)
1648 struct adapter *adapter = iflib_get_softc(ctx);
1649 struct ifnet *ifp = iflib_get_ifp(ctx);
1651 u8 *mta; /* Multicast array memory */
1654 IOCTL_DEBUGOUT("em_set_multi: begin");
1657 bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1659 if (adapter->hw.mac.type == e1000_82542 &&
1660 adapter->hw.revision_id == E1000_REVISION_2) {
1661 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1662 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1663 e1000_pci_clear_mwi(&adapter->hw);
1664 reg_rctl |= E1000_RCTL_RST;
1665 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1669 if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES);
1671 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1672 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1673 reg_rctl |= E1000_RCTL_MPE;
1674 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1676 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
1678 if (adapter->hw.mac.type == e1000_82542 &&
1679 adapter->hw.revision_id == E1000_REVISION_2) {
1680 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1681 reg_rctl &= ~E1000_RCTL_RST;
1682 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1684 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1685 e1000_pci_set_mwi(&adapter->hw);
1690 /*********************************************************************
1693 * This routine checks for link status and updates statistics.
1695 **********************************************************************/
1698 em_if_timer(if_ctx_t ctx, uint16_t qid)
1700 struct adapter *adapter = iflib_get_softc(ctx);
1701 struct em_rx_queue *que;
1708 iflib_admin_intr_deferred(ctx);
1710 /* Mask to use in the irq trigger */
1711 if (adapter->intr_type == IFLIB_INTR_MSIX) {
1712 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++)
1713 trigger |= que->eims;
1715 trigger = E1000_ICS_RXDMT0;
1721 em_if_update_admin_status(if_ctx_t ctx)
1723 struct adapter *adapter = iflib_get_softc(ctx);
1724 struct e1000_hw *hw = &adapter->hw;
1725 device_t dev = iflib_get_dev(ctx);
1726 u32 link_check, thstat, ctrl;
1728 link_check = thstat = ctrl = 0;
1729 /* Get the cached link value or read phy for real */
1730 switch (hw->phy.media_type) {
1731 case e1000_media_type_copper:
1732 if (hw->mac.get_link_status) {
1733 if (hw->mac.type == e1000_pch_spt)
1735 /* Do the work to read phy */
1736 e1000_check_for_link(hw);
1737 link_check = !hw->mac.get_link_status;
1738 if (link_check) /* ESB2 fix */
1739 e1000_cfg_on_link_up(hw);
1744 case e1000_media_type_fiber:
1745 e1000_check_for_link(hw);
1746 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1749 case e1000_media_type_internal_serdes:
1750 e1000_check_for_link(hw);
1751 link_check = adapter->hw.mac.serdes_has_link;
1753 /* VF device is type_unknown */
1754 case e1000_media_type_unknown:
1755 e1000_check_for_link(hw);
1756 link_check = !hw->mac.get_link_status;
1762 /* Check for thermal downshift or shutdown */
1763 if (hw->mac.type == e1000_i350) {
1764 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1765 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1768 /* Now check for a transition */
1769 if (link_check && (adapter->link_active == 0)) {
1770 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
1771 &adapter->link_duplex);
1772 /* Check if we must disable SPEED_MODE bit on PCI-E */
1773 if ((adapter->link_speed != SPEED_1000) &&
1774 ((hw->mac.type == e1000_82571) ||
1775 (hw->mac.type == e1000_82572))) {
1777 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1778 tarc0 &= ~TARC_SPEED_MODE_BIT;
1779 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1782 device_printf(dev, "Link is up %d Mbps %s\n",
1783 adapter->link_speed,
1784 ((adapter->link_duplex == FULL_DUPLEX) ?
1785 "Full Duplex" : "Half Duplex"));
1786 adapter->link_active = 1;
1787 adapter->smartspeed = 0;
1788 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) ==
1789 E1000_CTRL_EXT_LINK_MODE_GMII &&
1790 (thstat & E1000_THSTAT_LINK_THROTTLE))
1791 device_printf(dev, "Link: thermal downshift\n");
1792 /* Delay Link Up for Phy update */
1793 if (((hw->mac.type == e1000_i210) ||
1794 (hw->mac.type == e1000_i211)) &&
1795 (hw->phy.id == I210_I_PHY_ID))
1796 msec_delay(I210_LINK_DELAY);
1797 /* Reset if the media type changed. */
1798 if ((hw->dev_spec._82575.media_changed) &&
1799 (adapter->hw.mac.type >= igb_mac_min)) {
1800 hw->dev_spec._82575.media_changed = false;
1801 adapter->flags |= IGB_MEDIA_RESET;
1804 iflib_link_state_change(ctx, LINK_STATE_UP,
1805 IF_Mbps(adapter->link_speed));
1806 printf("Link state changed to up\n");
1807 } else if (!link_check && (adapter->link_active == 1)) {
1808 adapter->link_speed = 0;
1809 adapter->link_duplex = 0;
1810 adapter->link_active = 0;
1811 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
1812 printf("Link state changed to down\n");
1814 em_update_stats_counters(adapter);
1816 /* Reset LAA into RAR[0] on 82571 */
1817 if ((adapter->hw.mac.type == e1000_82571) &&
1818 e1000_get_laa_state_82571(&adapter->hw))
1819 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1821 if (adapter->hw.mac.type < em_mac_min)
1822 lem_smartspeed(adapter);
1824 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC);
1827 /*********************************************************************
1829 * This routine disables all traffic on the adapter by issuing a
1830 * global reset on the MAC and deallocates TX/RX buffers.
1832 * This routine should always be called with BOTH the CORE
1834 **********************************************************************/
1837 em_if_stop(if_ctx_t ctx)
1839 struct adapter *adapter = iflib_get_softc(ctx);
1841 INIT_DEBUGOUT("em_stop: begin");
1843 e1000_reset_hw(&adapter->hw);
1844 if (adapter->hw.mac.type >= e1000_82544)
1845 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0);
1847 e1000_led_off(&adapter->hw);
1848 e1000_cleanup_led(&adapter->hw);
1852 /*********************************************************************
1854 * Determine hardware revision.
1856 **********************************************************************/
1858 em_identify_hardware(if_ctx_t ctx)
1860 device_t dev = iflib_get_dev(ctx);
1861 struct adapter *adapter = iflib_get_softc(ctx);
1863 /* Make sure our PCI config space has the necessary stuff set */
1864 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1866 /* Save off the information about this board */
1867 adapter->hw.vendor_id = pci_get_vendor(dev);
1868 adapter->hw.device_id = pci_get_device(dev);
1869 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1870 adapter->hw.subsystem_vendor_id =
1871 pci_read_config(dev, PCIR_SUBVEND_0, 2);
1872 adapter->hw.subsystem_device_id =
1873 pci_read_config(dev, PCIR_SUBDEV_0, 2);
1875 /* Do Shared Code Init and Setup */
1876 if (e1000_set_mac_type(&adapter->hw)) {
1877 device_printf(dev, "Setup init failure\n");
1883 em_allocate_pci_resources(if_ctx_t ctx)
1885 struct adapter *adapter = iflib_get_softc(ctx);
1886 device_t dev = iflib_get_dev(ctx);
1890 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1892 if (adapter->memory == NULL) {
1893 device_printf(dev, "Unable to allocate bus resource: memory\n");
1896 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory);
1897 adapter->osdep.mem_bus_space_handle =
1898 rman_get_bushandle(adapter->memory);
1899 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle;
1901 /* Only older adapters use IO mapping */
1902 if (adapter->hw.mac.type < em_mac_min &&
1903 adapter->hw.mac.type > e1000_82543) {
1904 /* Figure our where our IO BAR is ? */
1905 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1906 val = pci_read_config(dev, rid, 4);
1907 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1908 adapter->io_rid = rid;
1912 /* check for 64bit BAR */
1913 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1916 if (rid >= PCIR_CIS) {
1917 device_printf(dev, "Unable to locate IO BAR\n");
1920 adapter->ioport = bus_alloc_resource_any(dev,
1921 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE);
1922 if (adapter->ioport == NULL) {
1923 device_printf(dev, "Unable to allocate bus resource: "
1927 adapter->hw.io_base = 0;
1928 adapter->osdep.io_bus_space_tag =
1929 rman_get_bustag(adapter->ioport);
1930 adapter->osdep.io_bus_space_handle =
1931 rman_get_bushandle(adapter->ioport);
1934 adapter->hw.back = &adapter->osdep;
1939 /*********************************************************************
1941 * Setup the MSIX Interrupt handlers
1943 **********************************************************************/
1945 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
1947 struct adapter *adapter = iflib_get_softc(ctx);
1948 struct em_rx_queue *rx_que = adapter->rx_queues;
1949 struct em_tx_queue *tx_que = adapter->tx_queues;
1950 int error, rid, i, vector = 0, rx_vectors;
1953 /* First set up ring resources */
1954 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) {
1956 snprintf(buf, sizeof(buf), "rxq%d", i);
1957 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
1959 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
1960 adapter->rx_num_queues = i + 1;
1964 rx_que->msix = vector;
1967 * Set the bit to enable interrupt
1968 * in E1000_IMS -- bits 20 and 21
1969 * are for RX0 and RX1, note this has
1970 * NOTHING to do with the MSIX vector
1972 if (adapter->hw.mac.type == e1000_82574) {
1973 rx_que->eims = 1 << (20 + i);
1974 adapter->ims |= rx_que->eims;
1975 adapter->ivars |= (8 | rx_que->msix) << (i * 4);
1976 } else if (adapter->hw.mac.type == e1000_82575)
1977 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
1979 rx_que->eims = 1 << vector;
1981 rx_vectors = vector;
1984 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) {
1985 snprintf(buf, sizeof(buf), "txq%d", i);
1986 tx_que = &adapter->tx_queues[i];
1987 iflib_softirq_alloc_generic(ctx,
1988 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq,
1989 IFLIB_INTR_TX, tx_que, tx_que->me, buf);
1991 tx_que->msix = (vector % adapter->tx_num_queues);
1994 * Set the bit to enable interrupt
1995 * in E1000_IMS -- bits 22 and 23
1996 * are for TX0 and TX1, note this has
1997 * NOTHING to do with the MSIX vector
1999 if (adapter->hw.mac.type == e1000_82574) {
2000 tx_que->eims = 1 << (22 + i);
2001 adapter->ims |= tx_que->eims;
2002 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
2003 } else if (adapter->hw.mac.type == e1000_82575) {
2004 tx_que->eims = E1000_EICR_TX_QUEUE0 << (i % adapter->tx_num_queues);
2006 tx_que->eims = 1 << (i % adapter->tx_num_queues);
2010 /* Link interrupt */
2011 rid = rx_vectors + 1;
2012 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq");
2015 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
2018 adapter->linkvec = rx_vectors;
2019 if (adapter->hw.mac.type < igb_mac_min) {
2020 adapter->ivars |= (8 | rx_vectors) << 16;
2021 adapter->ivars |= 0x80000000;
2025 iflib_irq_free(ctx, &adapter->irq);
2026 rx_que = adapter->rx_queues;
2027 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++)
2028 iflib_irq_free(ctx, &rx_que->que_irq);
2033 igb_configure_queues(struct adapter *adapter)
2035 struct e1000_hw *hw = &adapter->hw;
2036 struct em_rx_queue *rx_que;
2037 struct em_tx_queue *tx_que;
2038 u32 tmp, ivar = 0, newitr = 0;
2040 /* First turn on RSS capability */
2041 if (adapter->hw.mac.type != e1000_82575)
2042 E1000_WRITE_REG(hw, E1000_GPIE,
2043 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
2044 E1000_GPIE_PBA | E1000_GPIE_NSICR);
2047 switch (adapter->hw.mac.type) {
2054 case e1000_vfadapt_i350:
2056 for (int i = 0; i < adapter->rx_num_queues; i++) {
2058 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2059 rx_que = &adapter->rx_queues[i];
2062 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2065 ivar |= rx_que->msix | E1000_IVAR_VALID;
2067 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2070 for (int i = 0; i < adapter->tx_num_queues; i++) {
2072 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2073 tx_que = &adapter->tx_queues[i];
2076 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2079 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2081 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2082 adapter->que_mask |= tx_que->eims;
2085 /* And for the link interrupt */
2086 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2087 adapter->link_mask = 1 << adapter->linkvec;
2088 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2092 for (int i = 0; i < adapter->rx_num_queues; i++) {
2093 u32 index = i & 0x7; /* Each IVAR has two entries */
2094 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2095 rx_que = &adapter->rx_queues[i];
2098 ivar |= rx_que->msix | E1000_IVAR_VALID;
2101 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2103 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2104 adapter->que_mask |= rx_que->eims;
2107 for (int i = 0; i < adapter->tx_num_queues; i++) {
2108 u32 index = i & 0x7; /* Each IVAR has two entries */
2109 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2110 tx_que = &adapter->tx_queues[i];
2113 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2116 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2118 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2119 adapter->que_mask |= tx_que->eims;
2122 /* And for the link interrupt */
2123 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2124 adapter->link_mask = 1 << adapter->linkvec;
2125 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2129 /* enable MSI-X support*/
2130 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2131 tmp |= E1000_CTRL_EXT_PBA_CLR;
2132 /* Auto-Mask interrupts upon ICR read. */
2133 tmp |= E1000_CTRL_EXT_EIAME;
2134 tmp |= E1000_CTRL_EXT_IRCA;
2135 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2138 for (int i = 0; i < adapter->rx_num_queues; i++) {
2139 rx_que = &adapter->rx_queues[i];
2140 tmp = E1000_EICR_RX_QUEUE0 << i;
2141 tmp |= E1000_EICR_TX_QUEUE0 << i;
2143 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2145 adapter->que_mask |= rx_que->eims;
2149 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec),
2151 adapter->link_mask |= E1000_EIMS_OTHER;
2156 /* Set the starting interrupt rate */
2157 if (em_max_interrupt_rate > 0)
2158 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2160 if (hw->mac.type == e1000_82575)
2161 newitr |= newitr << 16;
2163 newitr |= E1000_EITR_CNT_IGNR;
2165 for (int i = 0; i < adapter->rx_num_queues; i++) {
2166 rx_que = &adapter->rx_queues[i];
2167 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2174 em_free_pci_resources(if_ctx_t ctx)
2176 struct adapter *adapter = iflib_get_softc(ctx);
2177 struct em_rx_queue *que = adapter->rx_queues;
2178 device_t dev = iflib_get_dev(ctx);
2180 /* Release all msix queue resources */
2181 if (adapter->intr_type == IFLIB_INTR_MSIX)
2182 iflib_irq_free(ctx, &adapter->irq);
2184 for (int i = 0; i < adapter->rx_num_queues; i++, que++) {
2185 iflib_irq_free(ctx, &que->que_irq);
2188 /* First release all the interrupt resources */
2189 if (adapter->memory != NULL) {
2190 bus_release_resource(dev, SYS_RES_MEMORY,
2191 PCIR_BAR(0), adapter->memory);
2192 adapter->memory = NULL;
2195 if (adapter->flash != NULL) {
2196 bus_release_resource(dev, SYS_RES_MEMORY,
2197 EM_FLASH, adapter->flash);
2198 adapter->flash = NULL;
2200 if (adapter->ioport != NULL)
2201 bus_release_resource(dev, SYS_RES_IOPORT,
2202 adapter->io_rid, adapter->ioport);
2205 /* Setup MSI or MSI/X */
2207 em_setup_msix(if_ctx_t ctx)
2209 struct adapter *adapter = iflib_get_softc(ctx);
2211 if (adapter->hw.mac.type == e1000_82574) {
2212 em_enable_vectors_82574(ctx);
2217 /*********************************************************************
2219 * Initialize the hardware to a configuration
2220 * as specified by the adapter structure.
2222 **********************************************************************/
2225 lem_smartspeed(struct adapter *adapter)
2229 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) ||
2230 adapter->hw.mac.autoneg == 0 ||
2231 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2234 if (adapter->smartspeed == 0) {
2235 /* If Master/Slave config fault is asserted twice,
2236 * we assume back-to-back */
2237 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2238 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2240 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2241 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2242 e1000_read_phy_reg(&adapter->hw,
2243 PHY_1000T_CTRL, &phy_tmp);
2244 if(phy_tmp & CR_1000T_MS_ENABLE) {
2245 phy_tmp &= ~CR_1000T_MS_ENABLE;
2246 e1000_write_phy_reg(&adapter->hw,
2247 PHY_1000T_CTRL, phy_tmp);
2248 adapter->smartspeed++;
2249 if(adapter->hw.mac.autoneg &&
2250 !e1000_copper_link_autoneg(&adapter->hw) &&
2251 !e1000_read_phy_reg(&adapter->hw,
2252 PHY_CONTROL, &phy_tmp)) {
2253 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2254 MII_CR_RESTART_AUTO_NEG);
2255 e1000_write_phy_reg(&adapter->hw,
2256 PHY_CONTROL, phy_tmp);
2261 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2262 /* If still no link, perhaps using 2/3 pair cable */
2263 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2264 phy_tmp |= CR_1000T_MS_ENABLE;
2265 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2266 if(adapter->hw.mac.autoneg &&
2267 !e1000_copper_link_autoneg(&adapter->hw) &&
2268 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2269 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2270 MII_CR_RESTART_AUTO_NEG);
2271 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2274 /* Restart process after EM_SMARTSPEED_MAX iterations */
2275 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2276 adapter->smartspeed = 0;
2279 /*********************************************************************
2281 * Initialize the DMA Coalescing feature
2283 **********************************************************************/
2285 igb_init_dmac(struct adapter *adapter, u32 pba)
2287 device_t dev = adapter->dev;
2288 struct e1000_hw *hw = &adapter->hw;
2289 u32 dmac, reg = ~E1000_DMACR_DMAC_EN;
2293 if (hw->mac.type == e1000_i211)
2296 max_frame_size = adapter->shared->isc_max_frame_size;
2297 if (hw->mac.type > e1000_82580) {
2299 if (adapter->dmac == 0) { /* Disabling it */
2300 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2303 device_printf(dev, "DMA Coalescing enabled\n");
2305 /* Set starting threshold */
2306 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
2308 hwm = 64 * pba - max_frame_size / 16;
2309 if (hwm < 64 * (pba - 6))
2310 hwm = 64 * (pba - 6);
2311 reg = E1000_READ_REG(hw, E1000_FCRTC);
2312 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
2313 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
2314 & E1000_FCRTC_RTH_COAL_MASK);
2315 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
2318 dmac = pba - max_frame_size / 512;
2319 if (dmac < pba - 10)
2321 reg = E1000_READ_REG(hw, E1000_DMACR);
2322 reg &= ~E1000_DMACR_DMACTHR_MASK;
2323 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT)
2324 & E1000_DMACR_DMACTHR_MASK);
2326 /* transition to L0x or L1 if available..*/
2327 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
2329 /* Check if status is 2.5Gb backplane connection
2330 * before configuration of watchdog timer, which is
2331 * in msec values in 12.8usec intervals
2332 * watchdog timer= msec values in 32usec intervals
2333 * for non 2.5Gb connection
2335 if (hw->mac.type == e1000_i354) {
2336 int status = E1000_READ_REG(hw, E1000_STATUS);
2337 if ((status & E1000_STATUS_2P5_SKU) &&
2338 (!(status & E1000_STATUS_2P5_SKU_OVER)))
2339 reg |= ((adapter->dmac * 5) >> 6);
2341 reg |= (adapter->dmac >> 5);
2343 reg |= (adapter->dmac >> 5);
2346 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2348 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
2350 /* Set the interval before transition */
2351 reg = E1000_READ_REG(hw, E1000_DMCTLX);
2352 if (hw->mac.type == e1000_i350)
2353 reg |= IGB_DMCTLX_DCFLUSH_DIS;
2355 ** in 2.5Gb connection, TTLX unit is 0.4 usec
2356 ** which is 0x4*2 = 0xA. But delay is still 4 usec
2358 if (hw->mac.type == e1000_i354) {
2359 int status = E1000_READ_REG(hw, E1000_STATUS);
2360 if ((status & E1000_STATUS_2P5_SKU) &&
2361 (!(status & E1000_STATUS_2P5_SKU_OVER)))
2369 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
2371 /* free space in tx packet buffer to wake from DMA coal */
2372 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE -
2373 (2 * max_frame_size)) >> 6);
2375 /* make low power state decision controlled by DMA coal */
2376 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2377 reg &= ~E1000_PCIEMISC_LX_DECISION;
2378 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
2380 } else if (hw->mac.type == e1000_82580) {
2381 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2382 E1000_WRITE_REG(hw, E1000_PCIEMISC,
2383 reg & ~E1000_PCIEMISC_LX_DECISION);
2384 E1000_WRITE_REG(hw, E1000_DMACR, 0);
2389 em_reset(if_ctx_t ctx)
2391 device_t dev = iflib_get_dev(ctx);
2392 struct adapter *adapter = iflib_get_softc(ctx);
2393 struct ifnet *ifp = iflib_get_ifp(ctx);
2394 struct e1000_hw *hw = &adapter->hw;
2398 INIT_DEBUGOUT("em_reset: begin");
2399 /* Let the firmware know the OS is in control */
2400 em_get_hw_control(adapter);
2402 /* Set up smart power down as default off on newer adapters. */
2403 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2404 hw->mac.type == e1000_82572)) {
2407 /* Speed up time to link by disabling smart power down. */
2408 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2409 phy_tmp &= ~IGP02E1000_PM_SPD;
2410 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2414 * Packet Buffer Allocation (PBA)
2415 * Writing PBA sets the receive portion of the buffer
2416 * the remainder is used for the transmit buffer.
2418 switch (hw->mac.type) {
2419 /* Total Packet Buffer on these is 48K */
2422 case e1000_80003es2lan:
2423 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2425 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
2426 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2430 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2436 case e1000_ich10lan:
2437 /* Boost Receive side for jumbo frames */
2438 if (adapter->hw.mac.max_frame_size > 4096)
2439 pba = E1000_PBA_14K;
2441 pba = E1000_PBA_10K;
2448 pba = E1000_PBA_26K;
2451 pba = E1000_PBA_32K;
2455 pba = E1000_READ_REG(hw, E1000_RXPBS);
2456 pba &= E1000_RXPBS_SIZE_MASK_82576;
2461 case e1000_vfadapt_i350:
2462 pba = E1000_READ_REG(hw, E1000_RXPBS);
2463 pba = e1000_rxpbs_adjust_82580(pba);
2467 pba = E1000_PBA_34K;
2470 if (adapter->hw.mac.max_frame_size > 8192)
2471 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2473 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2476 /* Special needs in case of Jumbo frames */
2477 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) {
2478 u32 tx_space, min_tx, min_rx;
2479 pba = E1000_READ_REG(hw, E1000_PBA);
2480 tx_space = pba >> 16;
2482 min_tx = (adapter->hw.mac.max_frame_size +
2483 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
2484 min_tx = roundup2(min_tx, 1024);
2486 min_rx = adapter->hw.mac.max_frame_size;
2487 min_rx = roundup2(min_rx, 1024);
2489 if (tx_space < min_tx &&
2490 ((min_tx - tx_space) < pba)) {
2491 pba = pba - (min_tx - tx_space);
2493 * if short on rx space, rx wins
2494 * and must trump tx adjustment
2499 E1000_WRITE_REG(hw, E1000_PBA, pba);
2502 if (hw->mac.type < igb_mac_min)
2503 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
2505 INIT_DEBUGOUT1("em_reset: pba=%dK",pba);
2508 * These parameters control the automatic generation (Tx) and
2509 * response (Rx) to Ethernet PAUSE frames.
2510 * - High water mark should allow for at least two frames to be
2511 * received after sending an XOFF.
2512 * - Low water mark works best when it is very near the high water mark.
2513 * This allows the receiver to restart by sending XON when it has
2514 * drained a bit. Here we use an arbitrary value of 1500 which will
2515 * restart after one full frame is pulled from the buffer. There
2516 * could be several smaller frames in the buffer and if so they will
2517 * not trigger the XON until their total number reduces the buffer
2519 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2521 rx_buffer_size = (pba & 0xffff) << 10;
2522 hw->fc.high_water = rx_buffer_size -
2523 roundup2(adapter->hw.mac.max_frame_size, 1024);
2524 hw->fc.low_water = hw->fc.high_water - 1500;
2526 if (adapter->fc) /* locally set flow control value? */
2527 hw->fc.requested_mode = adapter->fc;
2529 hw->fc.requested_mode = e1000_fc_full;
2531 if (hw->mac.type == e1000_80003es2lan)
2532 hw->fc.pause_time = 0xFFFF;
2534 hw->fc.pause_time = EM_FC_PAUSE_TIME;
2536 hw->fc.send_xon = TRUE;
2538 /* Device specific overrides/settings */
2539 switch (hw->mac.type) {
2541 /* Workaround: no TX flow ctrl for PCH */
2542 hw->fc.requested_mode = e1000_fc_rx_pause;
2543 hw->fc.pause_time = 0xFFFF; /* override */
2544 if (if_getmtu(ifp) > ETHERMTU) {
2545 hw->fc.high_water = 0x3500;
2546 hw->fc.low_water = 0x1500;
2548 hw->fc.high_water = 0x5000;
2549 hw->fc.low_water = 0x3000;
2551 hw->fc.refresh_time = 0x1000;
2557 hw->fc.high_water = 0x5C20;
2558 hw->fc.low_water = 0x5048;
2559 hw->fc.pause_time = 0x0650;
2560 hw->fc.refresh_time = 0x0400;
2561 /* Jumbos need adjusted PBA */
2562 if (if_getmtu(ifp) > ETHERMTU)
2563 E1000_WRITE_REG(hw, E1000_PBA, 12);
2565 E1000_WRITE_REG(hw, E1000_PBA, 26);
2569 /* 8-byte granularity */
2570 hw->fc.low_water = hw->fc.high_water - 8;
2578 case e1000_vfadapt_i350:
2579 /* 16-byte granularity */
2580 hw->fc.low_water = hw->fc.high_water - 16;
2583 case e1000_ich10lan:
2584 if (if_getmtu(ifp) > ETHERMTU) {
2585 hw->fc.high_water = 0x2800;
2586 hw->fc.low_water = hw->fc.high_water - 8;
2591 if (hw->mac.type == e1000_80003es2lan)
2592 hw->fc.pause_time = 0xFFFF;
2596 /* Issue a global reset */
2598 if (adapter->hw.mac.type >= igb_mac_min) {
2599 E1000_WRITE_REG(hw, E1000_WUC, 0);
2601 E1000_WRITE_REG(hw, E1000_WUFC, 0);
2602 em_disable_aspm(adapter);
2604 if (adapter->flags & IGB_MEDIA_RESET) {
2605 e1000_setup_init_funcs(hw, TRUE);
2606 e1000_get_bus_info(hw);
2607 adapter->flags &= ~IGB_MEDIA_RESET;
2610 if (e1000_init_hw(hw) < 0) {
2611 device_printf(dev, "Hardware Initialization Failed\n");
2614 if (adapter->hw.mac.type >= igb_mac_min)
2615 igb_init_dmac(adapter, pba);
2617 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2618 e1000_get_phy_info(hw);
2619 e1000_check_for_link(hw);
2622 #define RSSKEYLEN 10
2624 em_initialize_rss_mapping(struct adapter *adapter)
2626 uint8_t rss_key[4 * RSSKEYLEN];
2628 struct e1000_hw *hw = &adapter->hw;
2634 arc4rand(rss_key, sizeof(rss_key), 0);
2635 for (i = 0; i < RSSKEYLEN; ++i) {
2638 rssrk = EM_RSSRK_VAL(rss_key, i);
2639 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2643 * Configure RSS redirect table in following fashion:
2644 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2646 for (i = 0; i < sizeof(reta); ++i) {
2649 q = (i % adapter->rx_num_queues) << 7;
2650 reta |= q << (8 * i);
2653 for (i = 0; i < 32; ++i)
2654 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2656 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2657 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2658 E1000_MRQC_RSS_FIELD_IPV4 |
2659 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2660 E1000_MRQC_RSS_FIELD_IPV6_EX |
2661 E1000_MRQC_RSS_FIELD_IPV6);
2666 igb_initialize_rss_mapping(struct adapter *adapter)
2668 struct e1000_hw *hw = &adapter->hw;
2672 u32 rss_key[10], mrqc, shift = 0;
2675 if (adapter->hw.mac.type == e1000_82575)
2679 * The redirection table controls which destination
2680 * queue each bucket redirects traffic to.
2681 * Each DWORD represents four queues, with the LSB
2682 * being the first queue in the DWORD.
2684 * This just allocates buckets to queues using round-robin
2687 * NOTE: It Just Happens to line up with the default
2688 * RSS allocation method.
2691 /* Warning FM follows */
2693 for (i = 0; i < 128; i++) {
2695 queue_id = rss_get_indirection_to_bucket(i);
2697 * If we have more queues than buckets, we'll
2698 * end up mapping buckets to a subset of the
2701 * If we have more buckets than queues, we'll
2702 * end up instead assigning multiple buckets
2705 * Both are suboptimal, but we need to handle
2706 * the case so we don't go out of bounds
2707 * indexing arrays and such.
2709 queue_id = queue_id % adapter->rx_num_queues;
2711 queue_id = (i % adapter->rx_num_queues);
2713 /* Adjust if required */
2714 queue_id = queue_id << shift;
2717 * The low 8 bits are for hash value (n+0);
2718 * The next 8 bits are for hash value (n+1), etc.
2721 reta = reta | ( ((uint32_t) queue_id) << 24);
2723 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2728 /* Now fill in hash table */
2731 * MRQC: Multiple Receive Queues Command
2732 * Set queuing to RSS control, number depends on the device.
2734 mrqc = E1000_MRQC_ENABLE_RSS_8Q;
2737 /* XXX ew typecasting */
2738 rss_getkey((uint8_t *) &rss_key);
2740 arc4rand(&rss_key, sizeof(rss_key), 0);
2742 for (i = 0; i < 10; i++)
2743 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]);
2746 * Configure the RSS fields to hash upon.
2748 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2749 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2750 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2751 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2752 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2753 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2754 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2755 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2757 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2760 /*********************************************************************
2762 * Setup networking device structure and register an interface.
2764 **********************************************************************/
2766 em_setup_interface(if_ctx_t ctx)
2768 struct ifnet *ifp = iflib_get_ifp(ctx);
2769 struct adapter *adapter = iflib_get_softc(ctx);
2770 if_softc_ctx_t scctx = adapter->shared;
2772 INIT_DEBUGOUT("em_setup_interface: begin");
2775 if (adapter->tx_num_queues == 1) {
2776 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
2777 if_setsendqready(ifp);
2781 * Specify the media types supported by this adapter and register
2782 * callbacks to update media and link information
2784 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
2785 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
2786 u_char fiber_type = IFM_1000_SX; /* default type */
2788 if (adapter->hw.mac.type == e1000_82545)
2789 fiber_type = IFM_1000_LX;
2790 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
2791 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2793 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2794 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2795 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2796 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2797 if (adapter->hw.phy.type != e1000_phy_ife) {
2798 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2799 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2802 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2803 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO);
2808 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
2810 struct adapter *adapter = iflib_get_softc(ctx);
2811 if_softc_ctx_t scctx = adapter->shared;
2812 int error = E1000_SUCCESS;
2813 struct em_tx_queue *que;
2816 MPASS(adapter->tx_num_queues > 0);
2817 MPASS(adapter->tx_num_queues == ntxqsets);
2819 /* First allocate the top level queue structs */
2820 if (!(adapter->tx_queues =
2821 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
2822 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2823 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2827 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) {
2828 /* Set up some basics */
2830 struct tx_ring *txr = &que->txr;
2831 txr->adapter = que->adapter = adapter;
2832 que->me = txr->me = i;
2834 /* Allocate report status array */
2835 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2836 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n");
2840 for (j = 0; j < scctx->isc_ntxd[0]; j++)
2841 txr->tx_rsq[j] = QIDX_INVALID;
2842 /* get the virtual and physical address of the hardware queues */
2843 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
2844 txr->tx_paddr = paddrs[i*ntxqs];
2847 device_printf(iflib_get_dev(ctx), "allocated for %d tx_queues\n", adapter->tx_num_queues);
2850 em_if_queues_free(ctx);
2855 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
2857 struct adapter *adapter = iflib_get_softc(ctx);
2858 int error = E1000_SUCCESS;
2859 struct em_rx_queue *que;
2862 MPASS(adapter->rx_num_queues > 0);
2863 MPASS(adapter->rx_num_queues == nrxqsets);
2865 /* First allocate the top level queue structs */
2866 if (!(adapter->rx_queues =
2867 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
2868 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2869 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2874 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) {
2875 /* Set up some basics */
2876 struct rx_ring *rxr = &que->rxr;
2877 rxr->adapter = que->adapter = adapter;
2879 que->me = rxr->me = i;
2881 /* get the virtual and physical address of the hardware queues */
2882 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
2883 rxr->rx_paddr = paddrs[i*nrxqs];
2886 device_printf(iflib_get_dev(ctx), "allocated for %d rx_queues\n", adapter->rx_num_queues);
2890 em_if_queues_free(ctx);
2895 em_if_queues_free(if_ctx_t ctx)
2897 struct adapter *adapter = iflib_get_softc(ctx);
2898 struct em_tx_queue *tx_que = adapter->tx_queues;
2899 struct em_rx_queue *rx_que = adapter->rx_queues;
2901 if (tx_que != NULL) {
2902 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
2903 struct tx_ring *txr = &tx_que->txr;
2904 if (txr->tx_rsq == NULL)
2907 free(txr->tx_rsq, M_DEVBUF);
2910 free(adapter->tx_queues, M_DEVBUF);
2911 adapter->tx_queues = NULL;
2914 if (rx_que != NULL) {
2915 free(adapter->rx_queues, M_DEVBUF);
2916 adapter->rx_queues = NULL;
2919 em_release_hw_control(adapter);
2921 if (adapter->mta != NULL) {
2922 free(adapter->mta, M_DEVBUF);
2926 /*********************************************************************
2928 * Enable transmit unit.
2930 **********************************************************************/
2932 em_initialize_transmit_unit(if_ctx_t ctx)
2934 struct adapter *adapter = iflib_get_softc(ctx);
2935 if_softc_ctx_t scctx = adapter->shared;
2936 struct em_tx_queue *que;
2937 struct tx_ring *txr;
2938 struct e1000_hw *hw = &adapter->hw;
2939 u32 tctl, txdctl = 0, tarc, tipg = 0;
2941 INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
2943 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
2947 que = &adapter->tx_queues[i];
2949 bus_addr = txr->tx_paddr;
2951 /* Clear checksum offload context. */
2952 offp = (caddr_t)&txr->csum_flags;
2953 endp = (caddr_t)(txr + 1);
2954 bzero(offp, endp - offp);
2956 /* Base and Len of TX Ring */
2957 E1000_WRITE_REG(hw, E1000_TDLEN(i),
2958 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
2959 E1000_WRITE_REG(hw, E1000_TDBAH(i),
2960 (u32)(bus_addr >> 32));
2961 E1000_WRITE_REG(hw, E1000_TDBAL(i),
2963 /* Init the HEAD/TAIL indices */
2964 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
2965 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
2967 HW_DEBUGOUT2("Base = %x, Length = %x\n",
2968 E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)),
2969 E1000_READ_REG(&adapter->hw, E1000_TDLEN(i)));
2971 txdctl = 0; /* clear txdctl */
2972 txdctl |= 0x1f; /* PTHRESH */
2973 txdctl |= 1 << 8; /* HTHRESH */
2974 txdctl |= 1 << 16;/* WTHRESH */
2975 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
2976 txdctl |= E1000_TXDCTL_GRAN;
2977 txdctl |= 1 << 25; /* LWTHRESH */
2979 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
2982 /* Set the default values for the Tx Inter Packet Gap timer */
2983 switch (adapter->hw.mac.type) {
2984 case e1000_80003es2lan:
2985 tipg = DEFAULT_82543_TIPG_IPGR1;
2986 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2987 E1000_TIPG_IPGR2_SHIFT;
2990 tipg = DEFAULT_82542_TIPG_IPGT;
2991 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2992 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2995 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
2996 (adapter->hw.phy.media_type ==
2997 e1000_media_type_internal_serdes))
2998 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
3000 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
3001 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3002 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3005 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
3006 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value);
3008 if(adapter->hw.mac.type >= e1000_82540)
3009 E1000_WRITE_REG(&adapter->hw, E1000_TADV,
3010 adapter->tx_abs_int_delay.value);
3012 if ((adapter->hw.mac.type == e1000_82571) ||
3013 (adapter->hw.mac.type == e1000_82572)) {
3014 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3015 tarc |= TARC_SPEED_MODE_BIT;
3016 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3017 } else if (adapter->hw.mac.type == e1000_80003es2lan) {
3018 /* errata: program both queues to unweighted RR */
3019 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3021 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3022 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
3024 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
3025 } else if (adapter->hw.mac.type == e1000_82574) {
3026 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3027 tarc |= TARC_ERRATA_BIT;
3028 if ( adapter->tx_num_queues > 1) {
3029 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
3030 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3031 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
3033 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3036 if (adapter->tx_int_delay.value > 0)
3037 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3039 /* Program the Transmit Control Register */
3040 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
3041 tctl &= ~E1000_TCTL_CT;
3042 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
3043 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
3045 if (adapter->hw.mac.type >= e1000_82571)
3046 tctl |= E1000_TCTL_MULR;
3048 /* This write will effectively turn on the transmit unit. */
3049 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
3051 /* SPT and KBL errata workarounds */
3052 if (hw->mac.type == e1000_pch_spt) {
3054 reg = E1000_READ_REG(hw, E1000_IOSFPC);
3055 reg |= E1000_RCTL_RDMTS_HEX;
3056 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
3057 /* i218-i219 Specification Update 1.5.4.5 */
3058 reg = E1000_READ_REG(hw, E1000_TARC(0));
3059 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3060 reg |= E1000_TARC0_CB_MULTIQ_2_REQ;
3061 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3065 /*********************************************************************
3067 * Enable receive unit.
3069 **********************************************************************/
3072 em_initialize_receive_unit(if_ctx_t ctx)
3074 struct adapter *adapter = iflib_get_softc(ctx);
3075 if_softc_ctx_t scctx = adapter->shared;
3076 struct ifnet *ifp = iflib_get_ifp(ctx);
3077 struct e1000_hw *hw = &adapter->hw;
3078 struct em_rx_queue *que;
3080 u32 rctl, rxcsum, rfctl;
3082 INIT_DEBUGOUT("em_initialize_receive_units: begin");
3085 * Make sure receives are disabled while setting
3086 * up the descriptor ring
3088 rctl = E1000_READ_REG(hw, E1000_RCTL);
3089 /* Do not disable if ever enabled on this hardware */
3090 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
3091 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3093 /* Setup the Receive Control Register */
3094 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3095 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3096 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3097 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3099 /* Do not store bad packets */
3100 rctl &= ~E1000_RCTL_SBP;
3102 /* Enable Long Packet receive */
3103 if (if_getmtu(ifp) > ETHERMTU)
3104 rctl |= E1000_RCTL_LPE;
3106 rctl &= ~E1000_RCTL_LPE;
3109 if (!em_disable_crc_stripping)
3110 rctl |= E1000_RCTL_SECRC;
3112 if (adapter->hw.mac.type >= e1000_82540) {
3113 E1000_WRITE_REG(&adapter->hw, E1000_RADV,
3114 adapter->rx_abs_int_delay.value);
3117 * Set the interrupt throttling rate. Value is calculated
3118 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
3120 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
3122 E1000_WRITE_REG(&adapter->hw, E1000_RDTR,
3123 adapter->rx_int_delay.value);
3125 /* Use extended rx descriptor formats */
3126 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3127 rfctl |= E1000_RFCTL_EXTEN;
3129 * When using MSIX interrupts we need to throttle
3130 * using the EITR register (82574 only)
3132 if (hw->mac.type == e1000_82574) {
3133 for (int i = 0; i < 4; i++)
3134 E1000_WRITE_REG(hw, E1000_EITR_82574(i),
3136 /* Disable accelerated acknowledge */
3137 rfctl |= E1000_RFCTL_ACK_DIS;
3139 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3141 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
3142 if (if_getcapenable(ifp) & IFCAP_RXCSUM &&
3143 adapter->hw.mac.type >= e1000_82543) {
3144 if (adapter->tx_num_queues > 1) {
3145 if (adapter->hw.mac.type >= igb_mac_min) {
3146 rxcsum |= E1000_RXCSUM_PCSD;
3147 if (hw->mac.type != e1000_82575)
3148 rxcsum |= E1000_RXCSUM_CRCOFL;
3150 rxcsum |= E1000_RXCSUM_TUOFL |
3151 E1000_RXCSUM_IPOFL |
3154 if (adapter->hw.mac.type >= igb_mac_min)
3155 rxcsum |= E1000_RXCSUM_IPPCSE;
3157 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
3158 if (adapter->hw.mac.type > e1000_82575)
3159 rxcsum |= E1000_RXCSUM_CRCOFL;
3162 rxcsum &= ~E1000_RXCSUM_TUOFL;
3164 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
3166 if (adapter->rx_num_queues > 1) {
3167 if (adapter->hw.mac.type >= igb_mac_min)
3168 igb_initialize_rss_mapping(adapter);
3170 em_initialize_rss_mapping(adapter);
3174 * XXX TEMPORARY WORKAROUND: on some systems with 82573
3175 * long latencies are observed, like Lenovo X60. This
3176 * change eliminates the problem, but since having positive
3177 * values in RDTR is a known source of problems on other
3178 * platforms another solution is being sought.
3180 if (hw->mac.type == e1000_82573)
3181 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
3183 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3184 struct rx_ring *rxr = &que->rxr;
3185 /* Setup the Base and Length of the Rx Descriptor Ring */
3186 u64 bus_addr = rxr->rx_paddr;
3188 u32 rdt = adapter->rx_num_queues -1; /* default */
3191 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3192 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
3193 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
3194 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
3195 /* Setup the Head and Tail Descriptor Pointers */
3196 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
3197 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
3201 * Set PTHRESH for improved jumbo performance
3202 * According to 10.2.5.11 of Intel 82574 Datasheet,
3203 * RXDCTL(1) is written whenever RXDCTL(0) is written.
3204 * Only write to RXDCTL(1) if there is a need for different
3208 if (((adapter->hw.mac.type == e1000_ich9lan) ||
3209 (adapter->hw.mac.type == e1000_pch2lan) ||
3210 (adapter->hw.mac.type == e1000_ich10lan)) &&
3211 (if_getmtu(ifp) > ETHERMTU)) {
3212 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
3213 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
3214 } else if (adapter->hw.mac.type == e1000_82574) {
3215 for (int i = 0; i < adapter->rx_num_queues; i++) {
3216 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3217 rxdctl |= 0x20; /* PTHRESH */
3218 rxdctl |= 4 << 8; /* HTHRESH */
3219 rxdctl |= 4 << 16;/* WTHRESH */
3220 rxdctl |= 1 << 24; /* Switch to granularity */
3221 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3223 } else if (adapter->hw.mac.type >= igb_mac_min) {
3224 u32 psize, srrctl = 0;
3226 if (if_getmtu(ifp) > ETHERMTU) {
3227 /* Set maximum packet len */
3228 if (adapter->rx_mbuf_sz <= 4096) {
3229 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3230 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3231 } else if (adapter->rx_mbuf_sz > 4096) {
3232 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3233 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3235 psize = scctx->isc_max_frame_size;
3236 /* are we on a vlan? */
3237 if (ifp->if_vlantrunk != NULL)
3238 psize += VLAN_TAG_SIZE;
3239 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
3241 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3242 rctl |= E1000_RCTL_SZ_2048;
3246 * If TX flow control is disabled and there's >1 queue defined,
3249 * This drops frames rather than hanging the RX MAC for all queues.
3251 if ((adapter->rx_num_queues > 1) &&
3252 (adapter->fc == e1000_fc_none ||
3253 adapter->fc == e1000_fc_rx_pause)) {
3254 srrctl |= E1000_SRRCTL_DROP_EN;
3256 /* Setup the Base and Length of the Rx Descriptor Rings */
3257 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3258 struct rx_ring *rxr = &que->rxr;
3259 u64 bus_addr = rxr->rx_paddr;
3263 /* Configure for header split? -- ignore for now */
3264 rxr->hdr_split = igb_header_split;
3266 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3269 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3270 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3271 E1000_WRITE_REG(hw, E1000_RDBAH(i),
3272 (uint32_t)(bus_addr >> 32));
3273 E1000_WRITE_REG(hw, E1000_RDBAL(i),
3274 (uint32_t)bus_addr);
3275 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3276 /* Enable this Queue */
3277 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3278 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3279 rxdctl &= 0xFFF00000;
3280 rxdctl |= IGB_RX_PTHRESH;
3281 rxdctl |= IGB_RX_HTHRESH << 8;
3282 rxdctl |= IGB_RX_WTHRESH << 16;
3283 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3285 } else if (adapter->hw.mac.type >= e1000_pch2lan) {
3286 if (if_getmtu(ifp) > ETHERMTU)
3287 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
3289 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
3292 /* Make sure VLAN Filters are off */
3293 rctl &= ~E1000_RCTL_VFE;
3295 if (adapter->hw.mac.type < igb_mac_min) {
3296 if (adapter->rx_mbuf_sz == MCLBYTES)
3297 rctl |= E1000_RCTL_SZ_2048;
3298 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE)
3299 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3300 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE)
3301 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3303 /* ensure we clear use DTYPE of 00 here */
3304 rctl &= ~0x00000C00;
3307 /* Write out the settings */
3308 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3314 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3316 struct adapter *adapter = iflib_get_softc(ctx);
3319 index = (vtag >> 5) & 0x7F;
3321 adapter->shadow_vfta[index] |= (1 << bit);
3322 ++adapter->num_vlans;
3326 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3328 struct adapter *adapter = iflib_get_softc(ctx);
3331 index = (vtag >> 5) & 0x7F;
3333 adapter->shadow_vfta[index] &= ~(1 << bit);
3334 --adapter->num_vlans;
3338 em_setup_vlan_hw_support(struct adapter *adapter)
3340 struct e1000_hw *hw = &adapter->hw;
3344 * We get here thru init_locked, meaning
3345 * a soft reset, this has already cleared
3346 * the VFTA and other state, so if there
3347 * have been no vlan's registered do nothing.
3349 if (adapter->num_vlans == 0)
3353 * A soft reset zero's out the VFTA, so
3354 * we need to repopulate it now.
3356 for (int i = 0; i < EM_VFTA_SIZE; i++)
3357 if (adapter->shadow_vfta[i] != 0)
3358 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
3359 i, adapter->shadow_vfta[i]);
3361 reg = E1000_READ_REG(hw, E1000_CTRL);
3362 reg |= E1000_CTRL_VME;
3363 E1000_WRITE_REG(hw, E1000_CTRL, reg);
3365 /* Enable the Filter Table */
3366 reg = E1000_READ_REG(hw, E1000_RCTL);
3367 reg &= ~E1000_RCTL_CFIEN;
3368 reg |= E1000_RCTL_VFE;
3369 E1000_WRITE_REG(hw, E1000_RCTL, reg);
3373 em_if_enable_intr(if_ctx_t ctx)
3375 struct adapter *adapter = iflib_get_softc(ctx);
3376 struct e1000_hw *hw = &adapter->hw;
3377 u32 ims_mask = IMS_ENABLE_MASK;
3379 if (hw->mac.type == e1000_82574) {
3380 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK);
3381 ims_mask |= adapter->ims;
3382 } else if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min) {
3383 u32 mask = (adapter->que_mask | adapter->link_mask);
3385 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask);
3386 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask);
3387 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask);
3388 ims_mask = E1000_IMS_LSC;
3391 E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3395 em_if_disable_intr(if_ctx_t ctx)
3397 struct adapter *adapter = iflib_get_softc(ctx);
3398 struct e1000_hw *hw = &adapter->hw;
3400 if (adapter->intr_type == IFLIB_INTR_MSIX) {
3401 if (hw->mac.type >= igb_mac_min)
3402 E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0);
3403 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0);
3405 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
3409 * Bit of a misnomer, what this really means is
3410 * to enable OS management of the system... aka
3411 * to disable special hardware management features
3414 em_init_manageability(struct adapter *adapter)
3416 /* A shared code workaround */
3417 #define E1000_82542_MANC2H E1000_MANC2H
3418 if (adapter->has_manage) {
3419 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3420 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3422 /* disable hardware interception of ARP */
3423 manc &= ~(E1000_MANC_ARP_EN);
3425 /* enable receiving management packets to the host */
3426 manc |= E1000_MANC_EN_MNG2HOST;
3427 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3428 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3429 manc2h |= E1000_MNG2HOST_PORT_623;
3430 manc2h |= E1000_MNG2HOST_PORT_664;
3431 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3432 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3437 * Give control back to hardware management
3438 * controller if there is one.
3441 em_release_manageability(struct adapter *adapter)
3443 if (adapter->has_manage) {
3444 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3446 /* re-enable hardware interception of ARP */
3447 manc |= E1000_MANC_ARP_EN;
3448 manc &= ~E1000_MANC_EN_MNG2HOST;
3450 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3455 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3456 * For ASF and Pass Through versions of f/w this means
3457 * that the driver is loaded. For AMT version type f/w
3458 * this means that the network i/f is open.
3461 em_get_hw_control(struct adapter *adapter)
3465 if (adapter->vf_ifp)
3468 if (adapter->hw.mac.type == e1000_82573) {
3469 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3470 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3471 swsm | E1000_SWSM_DRV_LOAD);
3475 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3476 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3477 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3481 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3482 * For ASF and Pass Through versions of f/w this means that
3483 * the driver is no longer loaded. For AMT versions of the
3484 * f/w this means that the network i/f is closed.
3487 em_release_hw_control(struct adapter *adapter)
3491 if (!adapter->has_manage)
3494 if (adapter->hw.mac.type == e1000_82573) {
3495 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3496 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3497 swsm & ~E1000_SWSM_DRV_LOAD);
3501 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3502 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3503 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3508 em_is_valid_ether_addr(u8 *addr)
3510 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3512 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3520 ** Parse the interface capabilities with regard
3521 ** to both system management and wake-on-lan for
3525 em_get_wakeup(if_ctx_t ctx)
3527 struct adapter *adapter = iflib_get_softc(ctx);
3528 device_t dev = iflib_get_dev(ctx);
3529 u16 eeprom_data = 0, device_id, apme_mask;
3531 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
3532 apme_mask = EM_EEPROM_APME;
3534 switch (adapter->hw.mac.type) {
3539 e1000_read_nvm(&adapter->hw,
3540 NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3541 apme_mask = EM_82544_APME;
3544 case e1000_82546_rev_3:
3545 if (adapter->hw.bus.func == 1) {
3546 e1000_read_nvm(&adapter->hw,
3547 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3550 e1000_read_nvm(&adapter->hw,
3551 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3555 adapter->has_amt = TRUE;
3559 case e1000_80003es2lan:
3560 if (adapter->hw.bus.func == 1) {
3561 e1000_read_nvm(&adapter->hw,
3562 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3565 e1000_read_nvm(&adapter->hw,
3566 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3570 case e1000_ich10lan:
3575 case e1000_82575: /* listing all igb devices */
3583 case e1000_vfadapt_i350:
3584 apme_mask = E1000_WUC_APME;
3585 adapter->has_amt = TRUE;
3586 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
3589 e1000_read_nvm(&adapter->hw,
3590 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3593 if (eeprom_data & apme_mask)
3594 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
3596 * We have the eeprom settings, now apply the special cases
3597 * where the eeprom may be wrong or the board won't support
3598 * wake on lan on a particular port
3600 device_id = pci_get_device(dev);
3601 switch (device_id) {
3602 case E1000_DEV_ID_82546GB_PCIE:
3605 case E1000_DEV_ID_82546EB_FIBER:
3606 case E1000_DEV_ID_82546GB_FIBER:
3607 /* Wake events only supported on port A for dual fiber
3608 * regardless of eeprom setting */
3609 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3610 E1000_STATUS_FUNC_1)
3613 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
3614 /* if quad port adapter, disable WoL on all but port A */
3615 if (global_quad_port_a != 0)
3617 /* Reset for multiple quad port adapters */
3618 if (++global_quad_port_a == 4)
3619 global_quad_port_a = 0;
3621 case E1000_DEV_ID_82571EB_FIBER:
3622 /* Wake events only supported on port A for dual fiber
3623 * regardless of eeprom setting */
3624 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3625 E1000_STATUS_FUNC_1)
3628 case E1000_DEV_ID_82571EB_QUAD_COPPER:
3629 case E1000_DEV_ID_82571EB_QUAD_FIBER:
3630 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
3631 /* if quad port adapter, disable WoL on all but port A */
3632 if (global_quad_port_a != 0)
3634 /* Reset for multiple quad port adapters */
3635 if (++global_quad_port_a == 4)
3636 global_quad_port_a = 0;
3644 * Enable PCI Wake On Lan capability
3647 em_enable_wakeup(if_ctx_t ctx)
3649 struct adapter *adapter = iflib_get_softc(ctx);
3650 device_t dev = iflib_get_dev(ctx);
3651 if_t ifp = iflib_get_ifp(ctx);
3653 u32 pmc, ctrl, ctrl_ext, rctl;
3656 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
3660 * Determine type of Wakeup: note that wol
3661 * is set with all bits on by default.
3663 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
3664 adapter->wol &= ~E1000_WUFC_MAG;
3666 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
3667 adapter->wol &= ~E1000_WUFC_EX;
3669 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
3670 adapter->wol &= ~E1000_WUFC_MC;
3672 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3673 rctl |= E1000_RCTL_MPE;
3674 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3677 if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC)))
3680 /* Advertise the wakeup capability */
3681 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
3682 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
3683 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
3685 /* Keep the laser running on Fiber adapters */
3686 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3687 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
3688 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3689 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
3690 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext);
3693 if ((adapter->hw.mac.type == e1000_ich8lan) ||
3694 (adapter->hw.mac.type == e1000_pchlan) ||
3695 (adapter->hw.mac.type == e1000_ich9lan) ||
3696 (adapter->hw.mac.type == e1000_ich10lan))
3697 e1000_suspend_workarounds_ich8lan(&adapter->hw);
3699 if ( adapter->hw.mac.type >= e1000_pchlan) {
3700 error = em_enable_phy_wakeup(adapter);
3704 /* Enable wakeup by the MAC */
3705 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
3706 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
3709 if (adapter->hw.phy.type == e1000_phy_igp_3)
3710 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
3713 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
3714 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3715 if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
3716 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3717 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
3723 * WOL in the newer chipset interfaces (pchlan)
3724 * require thing to be copied into the phy
3727 em_enable_phy_wakeup(struct adapter *adapter)
3729 struct e1000_hw *hw = &adapter->hw;
3733 /* copy MAC RARs to PHY RARs */
3734 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
3736 /* copy MAC MTA to PHY MTA */
3737 for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
3738 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
3739 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
3740 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
3741 (u16)((mreg >> 16) & 0xFFFF));
3744 /* configure PHY Rx Control register */
3745 e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg);
3746 mreg = E1000_READ_REG(hw, E1000_RCTL);
3747 if (mreg & E1000_RCTL_UPE)
3748 preg |= BM_RCTL_UPE;
3749 if (mreg & E1000_RCTL_MPE)
3750 preg |= BM_RCTL_MPE;
3751 preg &= ~(BM_RCTL_MO_MASK);
3752 if (mreg & E1000_RCTL_MO_3)
3753 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
3754 << BM_RCTL_MO_SHIFT);
3755 if (mreg & E1000_RCTL_BAM)
3756 preg |= BM_RCTL_BAM;
3757 if (mreg & E1000_RCTL_PMCF)
3758 preg |= BM_RCTL_PMCF;
3759 mreg = E1000_READ_REG(hw, E1000_CTRL);
3760 if (mreg & E1000_CTRL_RFCE)
3761 preg |= BM_RCTL_RFCE;
3762 e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg);
3764 /* enable PHY wakeup in MAC register */
3765 E1000_WRITE_REG(hw, E1000_WUC,
3766 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
3767 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol);
3769 /* configure and enable PHY wakeup in PHY registers */
3770 e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol);
3771 e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
3773 /* activate PHY wakeup */
3774 ret = hw->phy.ops.acquire(hw);
3776 printf("Could not acquire PHY\n");
3779 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3780 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3781 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
3783 printf("Could not read PHY page 769\n");
3786 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
3787 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
3789 printf("Could not set PHY Host Wakeup bit\n");
3791 hw->phy.ops.release(hw);
3797 em_if_led_func(if_ctx_t ctx, int onoff)
3799 struct adapter *adapter = iflib_get_softc(ctx);
3802 e1000_setup_led(&adapter->hw);
3803 e1000_led_on(&adapter->hw);
3805 e1000_led_off(&adapter->hw);
3806 e1000_cleanup_led(&adapter->hw);
3811 * Disable the L0S and L1 LINK states
3814 em_disable_aspm(struct adapter *adapter)
3817 u16 link_cap,link_ctrl;
3818 device_t dev = adapter->dev;
3820 switch (adapter->hw.mac.type) {
3828 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
3830 reg = base + PCIER_LINK_CAP;
3831 link_cap = pci_read_config(dev, reg, 2);
3832 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
3834 reg = base + PCIER_LINK_CTL;
3835 link_ctrl = pci_read_config(dev, reg, 2);
3836 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
3837 pci_write_config(dev, reg, link_ctrl, 2);
3841 /**********************************************************************
3843 * Update the board statistics counters.
3845 **********************************************************************/
3847 em_update_stats_counters(struct adapter *adapter)
3850 if(adapter->hw.phy.media_type == e1000_media_type_copper ||
3851 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3852 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
3853 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
3855 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
3856 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
3857 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
3858 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
3860 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
3861 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
3862 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
3863 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
3864 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
3865 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
3866 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
3867 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
3869 ** For watchdog management we need to know if we have been
3870 ** paused during the last interval, so capture that here.
3872 adapter->shared->isc_pause_frames = adapter->stats.xoffrxc;
3873 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
3874 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
3875 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
3876 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
3877 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
3878 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
3879 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
3880 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
3881 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
3882 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
3883 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
3884 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
3886 /* For the 64-bit byte counters the low dword must be read first. */
3887 /* Both registers clear on the read of the high dword */
3889 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) +
3890 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32);
3891 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) +
3892 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32);
3894 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
3895 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
3896 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
3897 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
3898 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
3900 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
3901 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
3903 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
3904 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
3905 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
3906 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
3907 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
3908 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
3909 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
3910 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
3911 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
3912 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
3914 /* Interrupt Counts */
3916 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC);
3917 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC);
3918 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC);
3919 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC);
3920 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC);
3921 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC);
3922 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC);
3923 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC);
3924 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC);
3926 if (adapter->hw.mac.type >= e1000_82543) {
3927 adapter->stats.algnerrc +=
3928 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
3929 adapter->stats.rxerrc +=
3930 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
3931 adapter->stats.tncrs +=
3932 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
3933 adapter->stats.cexterr +=
3934 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
3935 adapter->stats.tsctc +=
3936 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
3937 adapter->stats.tsctfc +=
3938 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
3943 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
3945 struct adapter *adapter = iflib_get_softc(ctx);
3946 struct ifnet *ifp = iflib_get_ifp(ctx);
3949 case IFCOUNTER_COLLISIONS:
3950 return (adapter->stats.colc);
3951 case IFCOUNTER_IERRORS:
3952 return (adapter->dropped_pkts + adapter->stats.rxerrc +
3953 adapter->stats.crcerrs + adapter->stats.algnerrc +
3954 adapter->stats.ruc + adapter->stats.roc +
3955 adapter->stats.mpc + adapter->stats.cexterr);
3956 case IFCOUNTER_OERRORS:
3957 return (adapter->stats.ecol + adapter->stats.latecol +
3958 adapter->watchdog_events);
3960 return (if_get_counter_default(ifp, cnt));
3964 /* Export a single 32-bit register via a read-only sysctl. */
3966 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
3968 struct adapter *adapter;
3971 adapter = oidp->oid_arg1;
3972 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2);
3973 return (sysctl_handle_int(oidp, &val, 0, req));
3977 * Add sysctl variables, one per statistic, to the system.
3980 em_add_hw_stats(struct adapter *adapter)
3982 device_t dev = iflib_get_dev(adapter->ctx);
3983 struct em_tx_queue *tx_que = adapter->tx_queues;
3984 struct em_rx_queue *rx_que = adapter->rx_queues;
3986 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
3987 struct sysctl_oid *tree = device_get_sysctl_tree(dev);
3988 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
3989 struct e1000_hw_stats *stats = &adapter->stats;
3991 struct sysctl_oid *stat_node, *queue_node, *int_node;
3992 struct sysctl_oid_list *stat_list, *queue_list, *int_list;
3994 #define QUEUE_NAME_LEN 32
3995 char namebuf[QUEUE_NAME_LEN];
3997 /* Driver Statistics */
3998 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
3999 CTLFLAG_RD, &adapter->dropped_pkts,
4000 "Driver dropped packets");
4001 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
4002 CTLFLAG_RD, &adapter->link_irq,
4003 "Link MSIX IRQ Handled");
4004 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "mbuf_defrag_fail",
4005 CTLFLAG_RD, &adapter->mbuf_defrag_failed,
4006 "Defragmenting mbuf chain failed");
4007 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "tx_dma_fail",
4008 CTLFLAG_RD, &adapter->no_tx_dma_setup,
4009 "Driver tx dma failure in xmit");
4010 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
4011 CTLFLAG_RD, &adapter->rx_overruns,
4013 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
4014 CTLFLAG_RD, &adapter->watchdog_events,
4015 "Watchdog timeouts");
4016 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
4017 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL,
4018 em_sysctl_reg_handler, "IU",
4019 "Device Control Register");
4020 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
4021 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL,
4022 em_sysctl_reg_handler, "IU",
4023 "Receiver Control Register");
4024 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
4025 CTLFLAG_RD, &adapter->hw.fc.high_water, 0,
4026 "Flow Control High Watermark");
4027 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
4028 CTLFLAG_RD, &adapter->hw.fc.low_water, 0,
4029 "Flow Control Low Watermark");
4031 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
4032 struct tx_ring *txr = &tx_que->txr;
4033 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
4034 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4035 CTLFLAG_RD, NULL, "TX Queue Name");
4036 queue_list = SYSCTL_CHILDREN(queue_node);
4038 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
4039 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4041 em_sysctl_reg_handler, "IU",
4042 "Transmit Descriptor Head");
4043 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
4044 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4046 em_sysctl_reg_handler, "IU",
4047 "Transmit Descriptor Tail");
4048 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
4049 CTLFLAG_RD, &txr->tx_irq,
4050 "Queue MSI-X Transmit Interrupts");
4053 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) {
4054 struct rx_ring *rxr = &rx_que->rxr;
4055 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
4056 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4057 CTLFLAG_RD, NULL, "RX Queue Name");
4058 queue_list = SYSCTL_CHILDREN(queue_node);
4060 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
4061 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4063 em_sysctl_reg_handler, "IU",
4064 "Receive Descriptor Head");
4065 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
4066 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4068 em_sysctl_reg_handler, "IU",
4069 "Receive Descriptor Tail");
4070 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
4071 CTLFLAG_RD, &rxr->rx_irq,
4072 "Queue MSI-X Receive Interrupts");
4075 /* MAC stats get their own sub node */
4077 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
4078 CTLFLAG_RD, NULL, "Statistics");
4079 stat_list = SYSCTL_CHILDREN(stat_node);
4081 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
4082 CTLFLAG_RD, &stats->ecol,
4083 "Excessive collisions");
4084 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
4085 CTLFLAG_RD, &stats->scc,
4086 "Single collisions");
4087 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
4088 CTLFLAG_RD, &stats->mcc,
4089 "Multiple collisions");
4090 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
4091 CTLFLAG_RD, &stats->latecol,
4093 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
4094 CTLFLAG_RD, &stats->colc,
4096 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
4097 CTLFLAG_RD, &adapter->stats.symerrs,
4099 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
4100 CTLFLAG_RD, &adapter->stats.sec,
4102 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
4103 CTLFLAG_RD, &adapter->stats.dc,
4105 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
4106 CTLFLAG_RD, &adapter->stats.mpc,
4108 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
4109 CTLFLAG_RD, &adapter->stats.rnbc,
4110 "Receive No Buffers");
4111 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
4112 CTLFLAG_RD, &adapter->stats.ruc,
4113 "Receive Undersize");
4114 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
4115 CTLFLAG_RD, &adapter->stats.rfc,
4116 "Fragmented Packets Received ");
4117 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
4118 CTLFLAG_RD, &adapter->stats.roc,
4119 "Oversized Packets Received");
4120 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
4121 CTLFLAG_RD, &adapter->stats.rjc,
4123 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
4124 CTLFLAG_RD, &adapter->stats.rxerrc,
4126 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
4127 CTLFLAG_RD, &adapter->stats.crcerrs,
4129 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
4130 CTLFLAG_RD, &adapter->stats.algnerrc,
4131 "Alignment Errors");
4132 /* On 82575 these are collision counts */
4133 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
4134 CTLFLAG_RD, &adapter->stats.cexterr,
4135 "Collision/Carrier extension errors");
4136 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
4137 CTLFLAG_RD, &adapter->stats.xonrxc,
4139 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
4140 CTLFLAG_RD, &adapter->stats.xontxc,
4142 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
4143 CTLFLAG_RD, &adapter->stats.xoffrxc,
4145 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
4146 CTLFLAG_RD, &adapter->stats.xofftxc,
4147 "XOFF Transmitted");
4149 /* Packet Reception Stats */
4150 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
4151 CTLFLAG_RD, &adapter->stats.tpr,
4152 "Total Packets Received ");
4153 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
4154 CTLFLAG_RD, &adapter->stats.gprc,
4155 "Good Packets Received");
4156 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
4157 CTLFLAG_RD, &adapter->stats.bprc,
4158 "Broadcast Packets Received");
4159 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
4160 CTLFLAG_RD, &adapter->stats.mprc,
4161 "Multicast Packets Received");
4162 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
4163 CTLFLAG_RD, &adapter->stats.prc64,
4164 "64 byte frames received ");
4165 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
4166 CTLFLAG_RD, &adapter->stats.prc127,
4167 "65-127 byte frames received");
4168 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
4169 CTLFLAG_RD, &adapter->stats.prc255,
4170 "128-255 byte frames received");
4171 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
4172 CTLFLAG_RD, &adapter->stats.prc511,
4173 "256-511 byte frames received");
4174 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
4175 CTLFLAG_RD, &adapter->stats.prc1023,
4176 "512-1023 byte frames received");
4177 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
4178 CTLFLAG_RD, &adapter->stats.prc1522,
4179 "1023-1522 byte frames received");
4180 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
4181 CTLFLAG_RD, &adapter->stats.gorc,
4182 "Good Octets Received");
4184 /* Packet Transmission Stats */
4185 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
4186 CTLFLAG_RD, &adapter->stats.gotc,
4187 "Good Octets Transmitted");
4188 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
4189 CTLFLAG_RD, &adapter->stats.tpt,
4190 "Total Packets Transmitted");
4191 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
4192 CTLFLAG_RD, &adapter->stats.gptc,
4193 "Good Packets Transmitted");
4194 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
4195 CTLFLAG_RD, &adapter->stats.bptc,
4196 "Broadcast Packets Transmitted");
4197 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
4198 CTLFLAG_RD, &adapter->stats.mptc,
4199 "Multicast Packets Transmitted");
4200 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
4201 CTLFLAG_RD, &adapter->stats.ptc64,
4202 "64 byte frames transmitted ");
4203 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
4204 CTLFLAG_RD, &adapter->stats.ptc127,
4205 "65-127 byte frames transmitted");
4206 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
4207 CTLFLAG_RD, &adapter->stats.ptc255,
4208 "128-255 byte frames transmitted");
4209 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
4210 CTLFLAG_RD, &adapter->stats.ptc511,
4211 "256-511 byte frames transmitted");
4212 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
4213 CTLFLAG_RD, &adapter->stats.ptc1023,
4214 "512-1023 byte frames transmitted");
4215 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
4216 CTLFLAG_RD, &adapter->stats.ptc1522,
4217 "1024-1522 byte frames transmitted");
4218 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
4219 CTLFLAG_RD, &adapter->stats.tsctc,
4220 "TSO Contexts Transmitted");
4221 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
4222 CTLFLAG_RD, &adapter->stats.tsctfc,
4223 "TSO Contexts Failed");
4226 /* Interrupt Stats */
4228 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
4229 CTLFLAG_RD, NULL, "Interrupt Statistics");
4230 int_list = SYSCTL_CHILDREN(int_node);
4232 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
4233 CTLFLAG_RD, &adapter->stats.iac,
4234 "Interrupt Assertion Count");
4236 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
4237 CTLFLAG_RD, &adapter->stats.icrxptc,
4238 "Interrupt Cause Rx Pkt Timer Expire Count");
4240 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
4241 CTLFLAG_RD, &adapter->stats.icrxatc,
4242 "Interrupt Cause Rx Abs Timer Expire Count");
4244 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
4245 CTLFLAG_RD, &adapter->stats.ictxptc,
4246 "Interrupt Cause Tx Pkt Timer Expire Count");
4248 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
4249 CTLFLAG_RD, &adapter->stats.ictxatc,
4250 "Interrupt Cause Tx Abs Timer Expire Count");
4252 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
4253 CTLFLAG_RD, &adapter->stats.ictxqec,
4254 "Interrupt Cause Tx Queue Empty Count");
4256 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
4257 CTLFLAG_RD, &adapter->stats.ictxqmtc,
4258 "Interrupt Cause Tx Queue Min Thresh Count");
4260 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
4261 CTLFLAG_RD, &adapter->stats.icrxdmtc,
4262 "Interrupt Cause Rx Desc Min Thresh Count");
4264 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
4265 CTLFLAG_RD, &adapter->stats.icrxoc,
4266 "Interrupt Cause Receiver Overrun Count");
4269 /**********************************************************************
4271 * This routine provides a way to dump out the adapter eeprom,
4272 * often a useful debug/service tool. This only dumps the first
4273 * 32 words, stuff that matters is in that extent.
4275 **********************************************************************/
4277 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4279 struct adapter *adapter = (struct adapter *)arg1;
4284 error = sysctl_handle_int(oidp, &result, 0, req);
4286 if (error || !req->newptr)
4290 * This value will cause a hex dump of the
4291 * first 32 16-bit words of the EEPROM to
4295 em_print_nvm_info(adapter);
4301 em_print_nvm_info(struct adapter *adapter)
4306 /* Its a bit crude, but it gets the job done */
4307 printf("\nInterface EEPROM Dump:\n");
4308 printf("Offset\n0x0000 ");
4309 for (i = 0, j = 0; i < 32; i++, j++) {
4310 if (j == 8) { /* Make the offset block */
4312 printf("\n0x00%x0 ",row);
4314 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
4315 printf("%04x ", eeprom_data);
4321 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4323 struct em_int_delay_info *info;
4324 struct adapter *adapter;
4326 int error, usecs, ticks;
4328 info = (struct em_int_delay_info *) arg1;
4329 usecs = info->value;
4330 error = sysctl_handle_int(oidp, &usecs, 0, req);
4331 if (error != 0 || req->newptr == NULL)
4333 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4335 info->value = usecs;
4336 ticks = EM_USECS_TO_TICKS(usecs);
4337 if (info->offset == E1000_ITR) /* units are 256ns here */
4340 adapter = info->adapter;
4342 regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
4343 regval = (regval & ~0xffff) | (ticks & 0xffff);
4344 /* Handle a few special cases. */
4345 switch (info->offset) {
4350 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
4351 /* Don't write 0 into the TIDV register. */
4354 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
4357 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
4362 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
4363 const char *description, struct em_int_delay_info *info,
4364 int offset, int value)
4366 info->adapter = adapter;
4367 info->offset = offset;
4368 info->value = value;
4369 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev),
4370 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4371 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
4372 info, 0, em_sysctl_int_delay, "I", description);
4376 * Set flow control using sysctl:
4377 * Flow control values:
4384 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4387 static int input = 3; /* default is full */
4388 struct adapter *adapter = (struct adapter *) arg1;
4390 error = sysctl_handle_int(oidp, &input, 0, req);
4392 if ((error) || (req->newptr == NULL))
4395 if (input == adapter->fc) /* no change? */
4399 case e1000_fc_rx_pause:
4400 case e1000_fc_tx_pause:
4403 adapter->hw.fc.requested_mode = input;
4404 adapter->fc = input;
4411 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
4412 e1000_force_mac_fc(&adapter->hw);
4417 * Manage Energy Efficient Ethernet:
4419 * 0/1 - enabled/disabled
4422 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4424 struct adapter *adapter = (struct adapter *) arg1;
4427 value = adapter->hw.dev_spec.ich8lan.eee_disable;
4428 error = sysctl_handle_int(oidp, &value, 0, req);
4429 if (error || req->newptr == NULL)
4431 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4432 em_if_init(adapter->ctx);
4438 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4440 struct adapter *adapter;
4445 error = sysctl_handle_int(oidp, &result, 0, req);
4447 if (error || !req->newptr)
4451 adapter = (struct adapter *) arg1;
4452 em_print_debug_info(adapter);
4459 em_get_rs(SYSCTL_HANDLER_ARGS)
4461 struct adapter *adapter = (struct adapter *) arg1;
4466 error = sysctl_handle_int(oidp, &result, 0, req);
4468 if (error || !req->newptr || result != 1)
4470 em_dump_rs(adapter);
4476 em_if_debug(if_ctx_t ctx)
4478 em_dump_rs(iflib_get_softc(ctx));
4482 * This routine is meant to be fluid, add whatever is
4483 * needed for debugging a problem. -jfv
4486 em_print_debug_info(struct adapter *adapter)
4488 device_t dev = iflib_get_dev(adapter->ctx);
4489 struct ifnet *ifp = iflib_get_ifp(adapter->ctx);
4490 struct tx_ring *txr = &adapter->tx_queues->txr;
4491 struct rx_ring *rxr = &adapter->rx_queues->rxr;
4493 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
4494 printf("Interface is RUNNING ");
4496 printf("Interface is NOT RUNNING\n");
4498 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
4499 printf("and INACTIVE\n");
4501 printf("and ACTIVE\n");
4503 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
4504 device_printf(dev, "TX Queue %d ------\n", i);
4505 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
4506 E1000_READ_REG(&adapter->hw, E1000_TDH(i)),
4507 E1000_READ_REG(&adapter->hw, E1000_TDT(i)));
4510 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) {
4511 device_printf(dev, "RX Queue %d ------\n", j);
4512 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
4513 E1000_READ_REG(&adapter->hw, E1000_RDH(j)),
4514 E1000_READ_REG(&adapter->hw, E1000_RDT(j)));
4520 * Write a new value to the EEPROM increasing the number of MSIX
4521 * vectors from 3 to 5, for proper multiqueue support.
4524 em_enable_vectors_82574(if_ctx_t ctx)
4526 struct adapter *adapter = iflib_get_softc(ctx);
4527 struct e1000_hw *hw = &adapter->hw;
4528 device_t dev = iflib_get_dev(ctx);
4531 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4532 printf("Current cap: %#06x\n", edata);
4533 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
4534 device_printf(dev, "Writing to eeprom: increasing "
4535 "reported MSIX vectors from 3 to 5...\n");
4536 edata &= ~(EM_NVM_MSIX_N_MASK);
4537 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
4538 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4539 e1000_update_nvm_checksum(hw);
4540 device_printf(dev, "Writing to eeprom: done\n");