sys/dev/e1000/if_em.c

   1 /*-
   2  * Copyright (c) 2016 Matt Macy <mmacy@nextbsd.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 /* $FreeBSD$ */
  28 #include "if_em.h"
  29 #include <sys/sbuf.h>
  30 #include <machine/_inttypes.h>
  31
  32 #define em_mac_min e1000_82547
  33 #define igb_mac_min e1000_82575
  34
  35 /*********************************************************************
  36  *  Driver version:
  37  *********************************************************************/
  38 char em_driver_version[] = "7.6.1-k";
  39
  40 /*********************************************************************
  41  *  PCI Device ID Table
  42  *
  43  *  Used by probe to select devices to load on
  44  *  Last field stores an index into e1000_strings
  45  *  Last entry must be all 0s
  46  *
  47  *  { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
  48  *********************************************************************/
  49
  50 static pci_vendor_info_t em_vendor_info_array[] =
  51 {
  52         /* Intel(R) PRO/1000 Network Connection - Legacy em*/
  53         PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"),
  54         PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"),
  55         PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"),
  56         PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"),
  57         PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"),
  58
  59         PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"),
  60         PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"),
  61         PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"),
  62         PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  63         PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"),
  64         PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"),
  65         PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  66
  67         PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"),
  68
  69         PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"),
  70         PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
  71
  72         PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
  73         PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
  74         PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
  75         PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"),
  76
  77         PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"),
  78         PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"),
  79         PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"),
  80         PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"),
  81         PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"),
  82
  83         PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  84         PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
  85         PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
  86         PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  87         PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"),
  88         PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"),
  89         PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"),
  90         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
  91         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"),
  92
  93         PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"),
  94         PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  95         PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"),
  96
  97         /* Intel(R) PRO/1000 Network Connection - em */
  98         PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  99         PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
 100         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"),
 101         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"),
 102         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"),
 103         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 104         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"),
 105         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"),
 106         PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 107         PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"),
 108         PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
 109         PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
 110         PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"),
 111         PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"),
 112         PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"),
 113         PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"),
 114         PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"),
 115         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"),
 116         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"),
 117         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"),
 118         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"),
 119         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
 120         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 121         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"),
 122         PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"),
 123         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
 124         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"),
 125         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"),
 126         PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"),
 127         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
 128         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 129         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"),
 130         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"),
 131         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"),
 132         PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"),
 133         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
 134         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"),
 135         PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"),
 136         PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"),
 137         PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"),
 138         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"),
 139         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"),
 140         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"),
 141         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"),
 142         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"),
 143         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"),
 144         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"),
 145         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"),
 146         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"),
 147         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"),
 148         PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"),
 149         PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"),
 150         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"),
 151         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"),
 152         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"),
 153         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"),
 154         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"),
 155         PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"),
 156         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"),
 157         PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"),
 158         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"),
 159         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"),
 160         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"),
 161         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"),
 162         PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"),
 163         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"),
 164         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"),
 165         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"),
 166         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"),
 167         /* required last entry */
 168         PVID_END
 169 };
 170
 171 static pci_vendor_info_t igb_vendor_info_array[] =
 172 {
 173         /* Intel(R) PRO/1000 Network Connection - igb */
 174         PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 175         PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 176         PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 177         PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 178         PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 179         PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 180         PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 181         PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 182         PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 183         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 184         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 185         PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 186         PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 187         PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 188         PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 189         PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 190         PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 191         PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 192         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 193         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 194         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 195         PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 196         PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 197         PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 198         PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 199         PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 200         PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 201         PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 202         PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 203         PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 204         PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 205         PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 206         PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 207         PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 208         PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 209         PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 210         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 211         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 212         PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 213         /* required last entry */
 214         PVID_END
 215 };
 216
 217 /*********************************************************************
 218  *  Function prototypes
 219  *********************************************************************/
 220 static void     *em_register(device_t dev);
 221 static void     *igb_register(device_t dev);
 222 static int      em_if_attach_pre(if_ctx_t ctx);
 223 static int      em_if_attach_post(if_ctx_t ctx);
 224 static int      em_if_detach(if_ctx_t ctx);
 225 static int      em_if_shutdown(if_ctx_t ctx);
 226 static int      em_if_suspend(if_ctx_t ctx);
 227 static int      em_if_resume(if_ctx_t ctx);
 228
 229 static int      em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets);
 230 static int      em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets);
 231 static void     em_if_queues_free(if_ctx_t ctx);
 232
 233 static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
 234 static void     em_if_init(if_ctx_t ctx);
 235 static void     em_if_stop(if_ctx_t ctx);
 236 static void     em_if_media_status(if_ctx_t, struct ifmediareq *);
 237 static int      em_if_media_change(if_ctx_t ctx);
 238 static int      em_if_mtu_set(if_ctx_t ctx, uint32_t mtu);
 239 static void     em_if_timer(if_ctx_t ctx, uint16_t qid);
 240 static void     em_if_vlan_register(if_ctx_t ctx, u16 vtag);
 241 static void     em_if_vlan_unregister(if_ctx_t ctx, u16 vtag);
 242
 243 static void     em_identify_hardware(if_ctx_t ctx);
 244 static int      em_allocate_pci_resources(if_ctx_t ctx);
 245 static void     em_free_pci_resources(if_ctx_t ctx);
 246 static void     em_reset(if_ctx_t ctx);
 247 static int      em_setup_interface(if_ctx_t ctx);
 248 static int      em_setup_msix(if_ctx_t ctx);
 249
 250 static void     em_initialize_transmit_unit(if_ctx_t ctx);
 251 static void     em_initialize_receive_unit(if_ctx_t ctx);
 252
 253 static void     em_if_enable_intr(if_ctx_t ctx);
 254 static void     em_if_disable_intr(if_ctx_t ctx);
 255 static int      em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 256 static int      em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
 257 static void     em_if_multi_set(if_ctx_t ctx);
 258 static void     em_if_update_admin_status(if_ctx_t ctx);
 259 static void     em_if_debug(if_ctx_t ctx);
 260 static void     em_update_stats_counters(struct adapter *);
 261 static void     em_add_hw_stats(struct adapter *adapter);
 262 static int      em_if_set_promisc(if_ctx_t ctx, int flags);
 263 static void     em_setup_vlan_hw_support(struct adapter *);
 264 static int      em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
 265 static void     em_print_nvm_info(struct adapter *);
 266 static int      em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 267 static int      em_get_rs(SYSCTL_HANDLER_ARGS);
 268 static void     em_print_debug_info(struct adapter *);
 269 static int      em_is_valid_ether_addr(u8 *);
 270 static int      em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
 271 static void     em_add_int_delay_sysctl(struct adapter *, const char *,
 272                     const char *, struct em_int_delay_info *, int, int);
 273 /* Management and WOL Support */
 274 static void     em_init_manageability(struct adapter *);
 275 static void     em_release_manageability(struct adapter *);
 276 static void     em_get_hw_control(struct adapter *);
 277 static void     em_release_hw_control(struct adapter *);
 278 static void     em_get_wakeup(if_ctx_t ctx);
 279 static void     em_enable_wakeup(if_ctx_t ctx);
 280 static int      em_enable_phy_wakeup(struct adapter *);
 281 static void     em_disable_aspm(struct adapter *);
 282
 283 int             em_intr(void *arg);
 284 static void     em_disable_promisc(if_ctx_t ctx);
 285
 286 /* MSIX handlers */
 287 static int      em_if_msix_intr_assign(if_ctx_t, int);
 288 static int      em_msix_link(void *);
 289 static void     em_handle_link(void *context);
 290
 291 static void     em_enable_vectors_82574(if_ctx_t);
 292
 293 static int      em_set_flowcntl(SYSCTL_HANDLER_ARGS);
 294 static int      em_sysctl_eee(SYSCTL_HANDLER_ARGS);
 295 static void     em_if_led_func(if_ctx_t ctx, int onoff);
 296
 297 static int      em_get_regs(SYSCTL_HANDLER_ARGS);
 298
 299 static void     lem_smartspeed(struct adapter *adapter);
 300 static void     igb_configure_queues(struct adapter *adapter);
 301
 302
 303 /*********************************************************************
 304  *  FreeBSD Device Interface Entry Points
 305  *********************************************************************/
 306 static device_method_t em_methods[] = {
 307         /* Device interface */
 308         DEVMETHOD(device_register, em_register),
 309         DEVMETHOD(device_probe, iflib_device_probe),
 310         DEVMETHOD(device_attach, iflib_device_attach),
 311         DEVMETHOD(device_detach, iflib_device_detach),
 312         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 313         DEVMETHOD(device_suspend, iflib_device_suspend),
 314         DEVMETHOD(device_resume, iflib_device_resume),
 315         DEVMETHOD_END
 316 };
 317
 318 static device_method_t igb_methods[] = {
 319         /* Device interface */
 320         DEVMETHOD(device_register, igb_register),
 321         DEVMETHOD(device_probe, iflib_device_probe),
 322         DEVMETHOD(device_attach, iflib_device_attach),
 323         DEVMETHOD(device_detach, iflib_device_detach),
 324         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 325         DEVMETHOD(device_suspend, iflib_device_suspend),
 326         DEVMETHOD(device_resume, iflib_device_resume),
 327         DEVMETHOD_END
 328 };
 329
 330
 331 static driver_t em_driver = {
 332         "em", em_methods, sizeof(struct adapter),
 333 };
 334
 335 static devclass_t em_devclass;
 336 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
 337
 338 MODULE_DEPEND(em, pci, 1, 1, 1);
 339 MODULE_DEPEND(em, ether, 1, 1, 1);
 340 MODULE_DEPEND(em, iflib, 1, 1, 1);
 341
 342 static driver_t igb_driver = {
 343         "igb", igb_methods, sizeof(struct adapter),
 344 };
 345
 346 static devclass_t igb_devclass;
 347 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
 348
 349 MODULE_DEPEND(igb, pci, 1, 1, 1);
 350 MODULE_DEPEND(igb, ether, 1, 1, 1);
 351 MODULE_DEPEND(igb, iflib, 1, 1, 1);
 352
 353
 354 static device_method_t em_if_methods[] = {
 355         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 356         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 357         DEVMETHOD(ifdi_detach, em_if_detach),
 358         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 359         DEVMETHOD(ifdi_suspend, em_if_suspend),
 360         DEVMETHOD(ifdi_resume, em_if_resume),
 361         DEVMETHOD(ifdi_init, em_if_init),
 362         DEVMETHOD(ifdi_stop, em_if_stop),
 363         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 364         DEVMETHOD(ifdi_intr_enable, em_if_enable_intr),
 365         DEVMETHOD(ifdi_intr_disable, em_if_disable_intr),
 366         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 367         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 368         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 369         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 370         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 371         DEVMETHOD(ifdi_media_status, em_if_media_status),
 372         DEVMETHOD(ifdi_media_change, em_if_media_change),
 373         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 374         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 375         DEVMETHOD(ifdi_timer, em_if_timer),
 376         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 377         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 378         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 379         DEVMETHOD(ifdi_led_func, em_if_led_func),
 380         DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable),
 381         DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable),
 382         DEVMETHOD(ifdi_debug, em_if_debug),
 383         DEVMETHOD_END
 384 };
 385
 386 /*
 387  * note that if (adapter->msix_mem) is replaced by:
 388  * if (adapter->intr_type == IFLIB_INTR_MSIX)
 389  */
 390 static driver_t em_if_driver = {
 391         "em_if", em_if_methods, sizeof(struct adapter)
 392 };
 393
 394 /*********************************************************************
 395  *  Tunable default values.
 396  *********************************************************************/
 397
 398 #define EM_TICKS_TO_USECS(ticks)        ((1024 * (ticks) + 500) / 1000)
 399 #define EM_USECS_TO_TICKS(usecs)        ((1000 * (usecs) + 512) / 1024)
 400 #define M_TSO_LEN                       66
 401
 402 #define MAX_INTS_PER_SEC        8000
 403 #define DEFAULT_ITR             (1000000000/(MAX_INTS_PER_SEC * 256))
 404
 405 /* Allow common code without TSO */
 406 #ifndef CSUM_TSO
 407 #define CSUM_TSO        0
 408 #endif
 409
 410 #define TSO_WORKAROUND  4
 411
 412 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters");
 413
 414 static int em_disable_crc_stripping = 0;
 415 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
 416     &em_disable_crc_stripping, 0, "Disable CRC Stripping");
 417
 418 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
 419 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
 420 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
 421     0, "Default transmit interrupt delay in usecs");
 422 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
 423     0, "Default receive interrupt delay in usecs");
 424
 425 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
 426 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
 427 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
 428     &em_tx_abs_int_delay_dflt, 0,
 429     "Default transmit interrupt delay limit in usecs");
 430 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
 431     &em_rx_abs_int_delay_dflt, 0,
 432     "Default receive interrupt delay limit in usecs");
 433
 434 static int em_smart_pwr_down = FALSE;
 435 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
 436     0, "Set to true to leave smart power down enabled on newer adapters");
 437
 438 /* Controls whether promiscuous also shows bad packets */
 439 static int em_debug_sbp = TRUE;
 440 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
 441     "Show bad packets in promiscuous mode");
 442
 443 /* How many packets rxeof tries to clean at a time */
 444 static int em_rx_process_limit = 100;
 445 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
 446     &em_rx_process_limit, 0,
 447     "Maximum number of received packets to process "
 448     "at a time, -1 means unlimited");
 449
 450 /* Energy efficient ethernet - default to OFF */
 451 static int eee_setting = 1;
 452 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
 453     "Enable Energy Efficient Ethernet");
 454
 455 /*
 456 ** Tuneable Interrupt rate
 457 */
 458 static int em_max_interrupt_rate = 8000;
 459 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
 460     &em_max_interrupt_rate, 0, "Maximum interrupts per second");
 461
 462
 463
 464 /* Global used in WOL setup with multiport cards */
 465 static int global_quad_port_a = 0;
 466
 467 extern struct if_txrx igb_txrx;
 468 extern struct if_txrx em_txrx;
 469 extern struct if_txrx lem_txrx;
 470
 471 static struct if_shared_ctx em_sctx_init = {
 472         .isc_magic = IFLIB_MAGIC,
 473         .isc_q_align = PAGE_SIZE,
 474         .isc_tx_maxsize = EM_TSO_SIZE,
 475         .isc_tx_maxsegsize = PAGE_SIZE,
 476         .isc_rx_maxsize = MJUM9BYTES,
 477         .isc_rx_nsegments = 1,
 478         .isc_rx_maxsegsize = MJUM9BYTES,
 479         .isc_nfl = 1,
 480         .isc_nrxqs = 1,
 481         .isc_ntxqs = 1,
 482         .isc_admin_intrcnt = 1,
 483         .isc_vendor_info = em_vendor_info_array,
 484         .isc_driver_version = em_driver_version,
 485         .isc_driver = &em_if_driver,
 486         .isc_flags = IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 487
 488         .isc_nrxd_min = {EM_MIN_RXD},
 489         .isc_ntxd_min = {EM_MIN_TXD},
 490         .isc_nrxd_max = {EM_MAX_RXD},
 491         .isc_ntxd_max = {EM_MAX_TXD},
 492         .isc_nrxd_default = {EM_DEFAULT_RXD},
 493         .isc_ntxd_default = {EM_DEFAULT_TXD},
 494 };
 495
 496 if_shared_ctx_t em_sctx = &em_sctx_init;
 497
 498
 499 static struct if_shared_ctx igb_sctx_init = {
 500         .isc_magic = IFLIB_MAGIC,
 501         .isc_q_align = PAGE_SIZE,
 502         .isc_tx_maxsize = EM_TSO_SIZE,
 503         .isc_tx_maxsegsize = PAGE_SIZE,
 504         .isc_rx_maxsize = MJUM9BYTES,
 505         .isc_rx_nsegments = 1,
 506         .isc_rx_maxsegsize = MJUM9BYTES,
 507         .isc_nfl = 1,
 508         .isc_nrxqs = 1,
 509         .isc_ntxqs = 1,
 510         .isc_admin_intrcnt = 1,
 511         .isc_vendor_info = igb_vendor_info_array,
 512         .isc_driver_version = em_driver_version,
 513         .isc_driver = &em_if_driver,
 514         .isc_flags = IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 515
 516         .isc_nrxd_min = {EM_MIN_RXD},
 517         .isc_ntxd_min = {EM_MIN_TXD},
 518         .isc_nrxd_max = {IGB_MAX_RXD},
 519         .isc_ntxd_max = {IGB_MAX_TXD},
 520         .isc_nrxd_default = {EM_DEFAULT_RXD},
 521         .isc_ntxd_default = {EM_DEFAULT_TXD},
 522 };
 523
 524 if_shared_ctx_t igb_sctx = &igb_sctx_init;
 525
 526 /*****************************************************************
 527  *
 528  * Dump Registers
 529  *
 530  ****************************************************************/
 531 #define IGB_REGS_LEN 739
 532
 533 static int em_get_regs(SYSCTL_HANDLER_ARGS)
 534 {
 535         struct adapter *adapter = (struct adapter *)arg1;
 536         struct e1000_hw *hw = &adapter->hw;
 537         struct sbuf *sb;
 538         u32 *regs_buff;
 539         int rc;
 540
 541         regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK);
 542         memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
 543
 544         rc = sysctl_wire_old_buffer(req, 0);
 545         MPASS(rc == 0);
 546         if (rc != 0) {
 547                 free(regs_buff, M_DEVBUF);
 548                 return (rc);
 549         }
 550
 551         sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
 552         MPASS(sb != NULL);
 553         if (sb == NULL) {
 554                 free(regs_buff, M_DEVBUF);
 555                 return (ENOMEM);
 556         }
 557
 558         /* General Registers */
 559         regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
 560         regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
 561         regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
 562         regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
 563         regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
 564         regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
 565         regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
 566         regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
 567         regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
 568         regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
 569         regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
 570         regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
 571         regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
 572         regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
 573         regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
 574         regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
 575         regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
 576         regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
 577         regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
 578         regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
 579         regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
 580         regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
 581
 582         sbuf_printf(sb, "General Registers\n");
 583         sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
 584         sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
 585         sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]);
 586
 587         sbuf_printf(sb, "Interrupt Registers\n");
 588         sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
 589
 590         sbuf_printf(sb, "RX Registers\n");
 591         sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
 592         sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
 593         sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
 594         sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
 595         sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
 596         sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
 597         sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
 598
 599         sbuf_printf(sb, "TX Registers\n");
 600         sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
 601         sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
 602         sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
 603         sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
 604         sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
 605         sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
 606         sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
 607         sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
 608         sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
 609         sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
 610         sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
 611
 612         free(regs_buff, M_DEVBUF);
 613
 614 #ifdef DUMP_DESCS
 615         {
 616                 if_softc_ctx_t scctx = adapter->shared;
 617                 struct rx_ring *rxr = &rx_que->rxr;
 618                 struct tx_ring *txr = &tx_que->txr;
 619                 int ntxd = scctx->isc_ntxd[0];
 620                 int nrxd = scctx->isc_nrxd[0];
 621                 int j;
 622
 623         for (j = 0; j < nrxd; j++) {
 624                 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
 625                 u32 length =  le32toh(rxr->rx_base[j].wb.upper.length);
 626                 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 "  Error:%d  Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
 627         }
 628
 629         for (j = 0; j < min(ntxd, 256); j++) {
 630                 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
 631
 632                 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x  eop: %d DD=%d\n",
 633                             j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
 634                             buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
 635
 636         }
 637         }
 638 #endif
 639
 640         rc = sbuf_finish(sb);
 641         sbuf_delete(sb);
 642         return(rc);
 643 }
 644
 645 static void *
 646 em_register(device_t dev)
 647 {
 648         return (em_sctx);
 649 }
 650
 651 static void *
 652 igb_register(device_t dev)
 653 {
 654         return (igb_sctx);
 655 }
 656
 657 static int
 658 em_set_num_queues(if_ctx_t ctx)
 659 {
 660         struct adapter *adapter = iflib_get_softc(ctx);
 661         int maxqueues;
 662
 663         /* Sanity check based on HW */
 664         switch (adapter->hw.mac.type) {
 665         case e1000_82576:
 666         case e1000_82580:
 667         case e1000_i350:
 668         case e1000_i354:
 669                 maxqueues = 8;
 670                 break;
 671         case e1000_i210:
 672         case e1000_82575:
 673                 maxqueues = 4;
 674                 break;
 675         case e1000_i211:
 676         case e1000_82574:
 677                 maxqueues = 2;
 678                 break;
 679         default:
 680                 maxqueues = 1;
 681                 break;
 682         }
 683
 684         return (maxqueues);
 685 }
 686
 687
 688 #define EM_CAPS \
 689         IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \
 690         IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | \
 691         IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU;
 692
 693 #define IGB_CAPS \
 694         IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \
 695         IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM | \
 696         IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU | IFCAP_TXCSUM_IPV6 | IFCAP_HWCSUM_IPV6 | IFCAP_JUMBO_MTU;
 697
 698 /*********************************************************************
 699  *  Device initialization routine
 700  *
 701  *  The attach entry point is called when the driver is being loaded.
 702  *  This routine identifies the type of hardware, allocates all resources
 703  *  and initializes the hardware.
 704  *
 705  *  return 0 on success, positive on failure
 706  *********************************************************************/
 707
 708 static int
 709 em_if_attach_pre(if_ctx_t ctx)
 710 {
 711         struct adapter *adapter;
 712         if_softc_ctx_t scctx;
 713         device_t dev;
 714         struct e1000_hw *hw;
 715         int error = 0;
 716
 717         INIT_DEBUGOUT("em_if_attach_pre begin");
 718         dev = iflib_get_dev(ctx);
 719         adapter = iflib_get_softc(ctx);
 720
 721         if (resource_disabled("em", device_get_unit(dev))) {
 722                 device_printf(dev, "Disabled by device hint\n");
 723                 return (ENXIO);
 724         }
 725
 726         adapter->ctx = adapter->osdep.ctx = ctx;
 727         adapter->dev = adapter->osdep.dev = dev;
 728         scctx = adapter->shared = iflib_get_softc_ctx(ctx);
 729         adapter->media = iflib_get_media(ctx);
 730         hw = &adapter->hw;
 731
 732         adapter->tx_process_limit = scctx->isc_ntxd[0];
 733
 734         /* SYSCTL stuff */
 735         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 736             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 737             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 738             em_sysctl_nvm_info, "I", "NVM Information");
 739
 740         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 741             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 742             OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 743             em_sysctl_debug_info, "I", "Debug Information");
 744
 745         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 746             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 747             OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 748             em_set_flowcntl, "I", "Flow Control");
 749
 750         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 751             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 752             OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0,
 753             em_get_regs, "A", "Dump Registers");
 754
 755         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 756             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 757             OID_AUTO, "rs_dump", CTLTYPE_INT | CTLFLAG_RW, adapter, 0,
 758             em_get_rs, "I", "Dump RS indexes");
 759
 760         /* Determine hardware and mac info */
 761         em_identify_hardware(ctx);
 762
 763         /* Set isc_msix_bar */
 764         scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR);
 765         scctx->isc_tx_nsegments = EM_MAX_SCATTER;
 766         scctx->isc_tx_tso_segments_max = scctx->isc_tx_nsegments;
 767         scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 768         scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 769         scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
 770         device_printf(dev, "attach_pre capping queues at %d\n", scctx->isc_ntxqsets_max);
 771
 772         scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 773
 774
 775         if (adapter->hw.mac.type >= igb_mac_min) {
 776                 int try_second_bar;
 777
 778                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
 779                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
 780                 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
 781                 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
 782                 scctx->isc_txrx = &igb_txrx;
 783                 scctx->isc_capenable = IGB_CAPS;
 784                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | CSUM_IP6_TCP \
 785                         | CSUM_IP6_UDP | CSUM_IP6_TCP;
 786                 if (adapter->hw.mac.type != e1000_82575)
 787                         scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
 788
 789                 /*
 790                 ** Some new devices, as with ixgbe, now may
 791                 ** use a different BAR, so we need to keep
 792                 ** track of which is used.
 793                 */
 794                 try_second_bar = pci_read_config(dev, scctx->isc_msix_bar, 4);
 795                 if (try_second_bar == 0)
 796                         scctx->isc_msix_bar += 4;
 797
 798         } else if (adapter->hw.mac.type >= em_mac_min) {
 799                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 800                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
 801                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 802                 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
 803                 scctx->isc_txrx = &em_txrx;
 804                 scctx->isc_capenable = EM_CAPS;
 805                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 806         } else {
 807                 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 808                 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
 809                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 810                 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
 811                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 812                 scctx->isc_txrx = &lem_txrx;
 813                 scctx->isc_capenable = EM_CAPS;
 814                 if (adapter->hw.mac.type < e1000_82543)
 815                         scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
 816                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 817                 scctx->isc_msix_bar = 0;
 818         }
 819
 820         /* Setup PCI resources */
 821         if (em_allocate_pci_resources(ctx)) {
 822                 device_printf(dev, "Allocation of PCI resources failed\n");
 823                 error = ENXIO;
 824                 goto err_pci;
 825         }
 826
 827         /*
 828         ** For ICH8 and family we need to
 829         ** map the flash memory, and this
 830         ** must happen after the MAC is
 831         ** identified
 832         */
 833         if ((hw->mac.type == e1000_ich8lan) ||
 834             (hw->mac.type == e1000_ich9lan) ||
 835             (hw->mac.type == e1000_ich10lan) ||
 836             (hw->mac.type == e1000_pchlan) ||
 837             (hw->mac.type == e1000_pch2lan) ||
 838             (hw->mac.type == e1000_pch_lpt)) {
 839                 int rid = EM_BAR_TYPE_FLASH;
 840                 adapter->flash = bus_alloc_resource_any(dev,
 841                     SYS_RES_MEMORY, &rid, RF_ACTIVE);
 842                 if (adapter->flash == NULL) {
 843                         device_printf(dev, "Mapping of Flash failed\n");
 844                         error = ENXIO;
 845                         goto err_pci;
 846                 }
 847                 /* This is used in the shared code */
 848                 hw->flash_address = (u8 *)adapter->flash;
 849                 adapter->osdep.flash_bus_space_tag =
 850                     rman_get_bustag(adapter->flash);
 851                 adapter->osdep.flash_bus_space_handle =
 852                     rman_get_bushandle(adapter->flash);
 853         }
 854         /*
 855         ** In the new SPT device flash is not  a
 856         ** separate BAR, rather it is also in BAR0,
 857         ** so use the same tag and an offset handle for the
 858         ** FLASH read/write macros in the shared code.
 859         */
 860         else if (hw->mac.type == e1000_pch_spt) {
 861                 adapter->osdep.flash_bus_space_tag =
 862                     adapter->osdep.mem_bus_space_tag;
 863                 adapter->osdep.flash_bus_space_handle =
 864                     adapter->osdep.mem_bus_space_handle
 865                     + E1000_FLASH_BASE_ADDR;
 866         }
 867
 868         /* Do Shared Code initialization */
 869         error = e1000_setup_init_funcs(hw, TRUE);
 870         if (error) {
 871                 device_printf(dev, "Setup of Shared code failed, error %d\n",
 872                     error);
 873                 error = ENXIO;
 874                 goto err_pci;
 875         }
 876
 877         em_setup_msix(ctx);
 878         e1000_get_bus_info(hw);
 879
 880         /* Set up some sysctls for the tunable interrupt delays */
 881         em_add_int_delay_sysctl(adapter, "rx_int_delay",
 882             "receive interrupt delay in usecs", &adapter->rx_int_delay,
 883             E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
 884         em_add_int_delay_sysctl(adapter, "tx_int_delay",
 885             "transmit interrupt delay in usecs", &adapter->tx_int_delay,
 886             E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
 887         em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
 888             "receive interrupt delay limit in usecs",
 889             &adapter->rx_abs_int_delay,
 890             E1000_REGISTER(hw, E1000_RADV),
 891             em_rx_abs_int_delay_dflt);
 892         em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
 893             "transmit interrupt delay limit in usecs",
 894             &adapter->tx_abs_int_delay,
 895             E1000_REGISTER(hw, E1000_TADV),
 896             em_tx_abs_int_delay_dflt);
 897         em_add_int_delay_sysctl(adapter, "itr",
 898             "interrupt delay limit in usecs/4",
 899             &adapter->tx_itr,
 900             E1000_REGISTER(hw, E1000_ITR),
 901             DEFAULT_ITR);
 902
 903         hw->mac.autoneg = DO_AUTO_NEG;
 904         hw->phy.autoneg_wait_to_complete = FALSE;
 905         hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 906
 907         if (adapter->hw.mac.type < em_mac_min) {
 908                 e1000_init_script_state_82541(&adapter->hw, TRUE);
 909                 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
 910         }
 911         /* Copper options */
 912         if (hw->phy.media_type == e1000_media_type_copper) {
 913                 hw->phy.mdix = AUTO_ALL_MODES;
 914                 hw->phy.disable_polarity_correction = FALSE;
 915                 hw->phy.ms_type = EM_MASTER_SLAVE;
 916         }
 917
 918         /*
 919          * Set the frame limits assuming
 920          * standard ethernet sized frames.
 921          */
 922         scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
 923             ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
 924
 925         /*
 926          * This controls when hardware reports transmit completion
 927          * status.
 928          */
 929         hw->mac.report_tx_early = 1;
 930
 931         /* Allocate multicast array memory. */
 932         adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN *
 933             MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
 934         if (adapter->mta == NULL) {
 935                 device_printf(dev, "Can not allocate multicast setup array\n");
 936                 error = ENOMEM;
 937                 goto err_late;
 938         }
 939
 940         /* Check SOL/IDER usage */
 941         if (e1000_check_reset_block(hw))
 942                 device_printf(dev, "PHY reset is blocked"
 943                               " due to SOL/IDER session.\n");
 944
 945         /* Sysctl for setting Energy Efficient Ethernet */
 946         hw->dev_spec.ich8lan.eee_disable = eee_setting;
 947         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 948             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 949             OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW,
 950             adapter, 0, em_sysctl_eee, "I",
 951             "Disable Energy Efficient Ethernet");
 952
 953         /*
 954         ** Start from a known state, this is
 955         ** important in reading the nvm and
 956         ** mac from that.
 957         */
 958         e1000_reset_hw(hw);
 959
 960         /* Make sure we have a good EEPROM before we read from it */
 961         if (e1000_validate_nvm_checksum(hw) < 0) {
 962                 /*
 963                 ** Some PCI-E parts fail the first check due to
 964                 ** the link being in sleep state, call it again,
 965                 ** if it fails a second time its a real issue.
 966                 */
 967                 if (e1000_validate_nvm_checksum(hw) < 0) {
 968                         device_printf(dev,
 969                             "The EEPROM Checksum Is Not Valid\n");
 970                         error = EIO;
 971                         goto err_late;
 972                 }
 973         }
 974
 975         /* Copy the permanent MAC address out of the EEPROM */
 976         if (e1000_read_mac_addr(hw) < 0) {
 977                 device_printf(dev, "EEPROM read error while reading MAC"
 978                               " address\n");
 979                 error = EIO;
 980                 goto err_late;
 981         }
 982
 983         if (!em_is_valid_ether_addr(hw->mac.addr)) {
 984                 device_printf(dev, "Invalid MAC address\n");
 985                 error = EIO;
 986                 goto err_late;
 987         }
 988
 989         /* Disable ULP support */
 990         e1000_disable_ulp_lpt_lp(hw, TRUE);
 991
 992         /*
 993          * Get Wake-on-Lan and Management info for later use
 994          */
 995         em_get_wakeup(ctx);
 996
 997         iflib_set_mac(ctx, hw->mac.addr);
 998
 999         return (0);
1000
1001 err_late:
1002         em_release_hw_control(adapter);
1003 err_pci:
1004         em_free_pci_resources(ctx);
1005         free(adapter->mta, M_DEVBUF);
1006
1007         return (error);
1008 }
1009
1010 static int
1011 em_if_attach_post(if_ctx_t ctx)
1012 {
1013         struct adapter *adapter = iflib_get_softc(ctx);
1014         struct e1000_hw *hw = &adapter->hw;
1015         int error = 0;
1016
1017         /* Setup OS specific network interface */
1018         error = em_setup_interface(ctx);
1019         if (error != 0) {
1020                 goto err_late;
1021         }
1022
1023         em_reset(ctx);
1024
1025         /* Initialize statistics */
1026         em_update_stats_counters(adapter);
1027         hw->mac.get_link_status = 1;
1028         em_if_update_admin_status(ctx);
1029         em_add_hw_stats(adapter);
1030
1031         /* Non-AMT based hardware can now take control from firmware */
1032         if (adapter->has_manage && !adapter->has_amt)
1033                 em_get_hw_control(adapter);
1034
1035         INIT_DEBUGOUT("em_if_attach_post: end");
1036
1037         return (error);
1038
1039 err_late:
1040         em_release_hw_control(adapter);
1041         em_free_pci_resources(ctx);
1042         em_if_queues_free(ctx);
1043         free(adapter->mta, M_DEVBUF);
1044
1045         return (error);
1046 }
1047
1048 /*********************************************************************
1049  *  Device removal routine
1050  *
1051  *  The detach entry point is called when the driver is being removed.
1052  *  This routine stops the adapter and deallocates all the resources
1053  *  that were allocated for driver operation.
1054  *
1055  *  return 0 on success, positive on failure
1056  *********************************************************************/
1057
1058 static int
1059 em_if_detach(if_ctx_t ctx)
1060 {
1061         struct adapter  *adapter = iflib_get_softc(ctx);
1062
1063         INIT_DEBUGOUT("em_detach: begin");
1064
1065         e1000_phy_hw_reset(&adapter->hw);
1066
1067         em_release_manageability(adapter);
1068         em_release_hw_control(adapter);
1069         em_free_pci_resources(ctx);
1070
1071         return (0);
1072 }
1073
1074 /*********************************************************************
1075  *
1076  *  Shutdown entry point
1077  *
1078  **********************************************************************/
1079
1080 static int
1081 em_if_shutdown(if_ctx_t ctx)
1082 {
1083         return em_if_suspend(ctx);
1084 }
1085
1086 /*
1087  * Suspend/resume device methods.
1088  */
1089 static int
1090 em_if_suspend(if_ctx_t ctx)
1091 {
1092         struct adapter *adapter = iflib_get_softc(ctx);
1093
1094         em_release_manageability(adapter);
1095         em_release_hw_control(adapter);
1096         em_enable_wakeup(ctx);
1097         return (0);
1098 }
1099
1100 static int
1101 em_if_resume(if_ctx_t ctx)
1102 {
1103         struct adapter *adapter = iflib_get_softc(ctx);
1104
1105         if (adapter->hw.mac.type == e1000_pch2lan)
1106                 e1000_resume_workarounds_pchlan(&adapter->hw);
1107         em_if_init(ctx);
1108         em_init_manageability(adapter);
1109
1110         return(0);
1111 }
1112
1113 static int
1114 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1115 {
1116         int max_frame_size;
1117         struct adapter *adapter = iflib_get_softc(ctx);
1118         if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1119
1120          IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1121
1122         switch (adapter->hw.mac.type) {
1123         case e1000_82571:
1124         case e1000_82572:
1125         case e1000_ich9lan:
1126         case e1000_ich10lan:
1127         case e1000_pch2lan:
1128         case e1000_pch_lpt:
1129         case e1000_pch_spt:
1130         case e1000_82574:
1131         case e1000_82583:
1132         case e1000_80003es2lan:
1133                 /* 9K Jumbo Frame size */
1134                 max_frame_size = 9234;
1135                 break;
1136         case e1000_pchlan:
1137                 max_frame_size = 4096;
1138                 break;
1139         case e1000_82542:
1140         case e1000_ich8lan:
1141                 /* Adapters that do not support jumbo frames */
1142                 max_frame_size = ETHER_MAX_LEN;
1143                 break;
1144         default:
1145                 if (adapter->hw.mac.type >= igb_mac_min)
1146                         max_frame_size = 9234;
1147                 else /* lem */
1148                         max_frame_size = MAX_JUMBO_FRAME_SIZE;
1149         }
1150         if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1151                 return (EINVAL);
1152         }
1153
1154         scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
1155             mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1156         return (0);
1157 }
1158
1159 /*********************************************************************
1160  *  Init entry point
1161  *
1162  *  This routine is used in two ways. It is used by the stack as
1163  *  init entry point in network interface structure. It is also used
1164  *  by the driver as a hw/sw initialization routine to get to a
1165  *  consistent state.
1166  *
1167  *  return 0 on success, positive on failure
1168  **********************************************************************/
1169
1170 static void
1171 em_if_init(if_ctx_t ctx)
1172 {
1173         struct adapter *adapter = iflib_get_softc(ctx);
1174         struct ifnet *ifp = iflib_get_ifp(ctx);
1175         struct em_tx_queue *tx_que;
1176         int i;
1177         INIT_DEBUGOUT("em_if_init: begin");
1178
1179         /* Get the latest mac address, User can use a LAA */
1180         bcopy(if_getlladdr(ifp), adapter->hw.mac.addr,
1181             ETHER_ADDR_LEN);
1182
1183         /* Put the address into the Receive Address Array */
1184         e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1185
1186         /*
1187          * With the 82571 adapter, RAR[0] may be overwritten
1188          * when the other port is reset, we make a duplicate
1189          * in RAR[14] for that eventuality, this assures
1190          * the interface continues to function.
1191          */
1192         if (adapter->hw.mac.type == e1000_82571) {
1193                 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1194                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1195                     E1000_RAR_ENTRIES - 1);
1196         }
1197
1198
1199         /* Initialize the hardware */
1200         em_reset(ctx);
1201         em_if_update_admin_status(ctx);
1202
1203         for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) {
1204                 struct tx_ring *txr = &tx_que->txr;
1205
1206                 txr->tx_rs_cidx = txr->tx_rs_pidx = txr->tx_cidx_processed = 0;
1207         }
1208
1209         /* Setup VLAN support, basic and offload if available */
1210         E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1211
1212         /* Clear bad data from Rx FIFOs */
1213         if (adapter->hw.mac.type >= igb_mac_min)
1214                 e1000_rx_fifo_flush_82575(&adapter->hw);
1215
1216         /* Configure for OS presence */
1217         em_init_manageability(adapter);
1218
1219         /* Prepare transmit descriptors and buffers */
1220         em_initialize_transmit_unit(ctx);
1221
1222         /* Setup Multicast table */
1223         em_if_multi_set(ctx);
1224
1225         /*
1226          * Figure out the desired mbuf
1227          * pool for doing jumbos
1228          */
1229         if (adapter->hw.mac.max_frame_size <= 2048)
1230                 adapter->rx_mbuf_sz = MCLBYTES;
1231 #ifndef CONTIGMALLOC_WORKS
1232         else
1233                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
1234 #else
1235         else if (adapter->hw.mac.max_frame_size <= 4096)
1236                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
1237         else
1238                 adapter->rx_mbuf_sz = MJUM9BYTES;
1239 #endif
1240         em_initialize_receive_unit(ctx);
1241
1242         /* Use real VLAN Filter support? */
1243         if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1244                 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
1245                         /* Use real VLAN Filter support */
1246                         em_setup_vlan_hw_support(adapter);
1247                 else {
1248                         u32 ctrl;
1249                         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1250                         ctrl |= E1000_CTRL_VME;
1251                         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1252                 }
1253         }
1254
1255         /* Don't lose promiscuous settings */
1256         em_if_set_promisc(ctx, IFF_PROMISC);
1257         e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1258
1259         /* MSI/X configuration for 82574 */
1260         if (adapter->hw.mac.type == e1000_82574) {
1261                 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1262
1263                 tmp |= E1000_CTRL_EXT_PBA_CLR;
1264                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1265                 /* Set the IVAR - interrupt vector routing. */
1266                 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars);
1267         } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1268                 igb_configure_queues(adapter);
1269
1270         /* this clears any pending interrupts */
1271         E1000_READ_REG(&adapter->hw, E1000_ICR);
1272         E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC);
1273
1274         /* AMT based hardware can now take control from firmware */
1275         if (adapter->has_manage && adapter->has_amt)
1276                 em_get_hw_control(adapter);
1277
1278         /* Set Energy Efficient Ethernet */
1279         if (adapter->hw.mac.type >= igb_mac_min &&
1280             adapter->hw.phy.media_type == e1000_media_type_copper) {
1281                 if (adapter->hw.mac.type == e1000_i354)
1282                         e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
1283                 else
1284                         e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
1285         }
1286 }
1287
1288 /*********************************************************************
1289  *
1290  *  Fast Legacy/MSI Combined Interrupt Service routine
1291  *
1292  *********************************************************************/
1293 int
1294 em_intr(void *arg)
1295 {
1296         struct adapter *adapter = arg;
1297         if_ctx_t ctx = adapter->ctx;
1298         u32 reg_icr;
1299
1300         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1301
1302         if (adapter->intr_type != IFLIB_INTR_LEGACY)
1303                 goto skip_stray;
1304         /* Hot eject? */
1305         if (reg_icr == 0xffffffff)
1306                 return FILTER_STRAY;
1307
1308         /* Definitely not our interrupt. */
1309         if (reg_icr == 0x0)
1310                 return FILTER_STRAY;
1311
1312         /*
1313          * Starting with the 82571 chip, bit 31 should be used to
1314          * determine whether the interrupt belongs to us.
1315          */
1316         if (adapter->hw.mac.type >= e1000_82571 &&
1317             (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1318                 return FILTER_STRAY;
1319
1320 skip_stray:
1321         /* Link status change */
1322         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1323                 adapter->hw.mac.get_link_status = 1;
1324                 iflib_admin_intr_deferred(ctx);
1325         }
1326
1327         if (reg_icr & E1000_ICR_RXO)
1328                 adapter->rx_overruns++;
1329
1330         return (FILTER_SCHEDULE_THREAD);
1331 }
1332
1333 static void
1334 igb_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq)
1335 {
1336         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims);
1337 }
1338
1339 static void
1340 em_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq)
1341 {
1342         E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims);
1343 }
1344
1345 static void
1346 igb_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq)
1347 {
1348         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims);
1349 }
1350
1351 static void
1352 em_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq)
1353 {
1354         E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims);
1355 }
1356
1357 static int
1358 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1359 {
1360         struct adapter *adapter = iflib_get_softc(ctx);
1361         struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1362
1363         if (adapter->hw.mac.type >= igb_mac_min)
1364                 igb_rx_enable_queue(adapter, rxq);
1365         else
1366                 em_rx_enable_queue(adapter, rxq);
1367         return (0);
1368 }
1369
1370 static int
1371 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1372 {
1373         struct adapter *adapter = iflib_get_softc(ctx);
1374         struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1375
1376         if (adapter->hw.mac.type >= igb_mac_min)
1377                 igb_tx_enable_queue(adapter, txq);
1378         else
1379                 em_tx_enable_queue(adapter, txq);
1380         return (0);
1381 }
1382
1383 /*********************************************************************
1384  *
1385  *  MSIX RX Interrupt Service routine
1386  *
1387  **********************************************************************/
1388 static int
1389 em_msix_que(void *arg)
1390 {
1391         struct em_rx_queue *que = arg;
1392
1393         ++que->irqs;
1394
1395         return (FILTER_SCHEDULE_THREAD);
1396 }
1397
1398 /*********************************************************************
1399  *
1400  *  MSIX Link Fast Interrupt Service routine
1401  *
1402  **********************************************************************/
1403 static int
1404 em_msix_link(void *arg)
1405 {
1406         struct adapter *adapter = arg;
1407         u32 reg_icr;
1408         int is_igb;
1409
1410         is_igb = (adapter->hw.mac.type >= igb_mac_min);
1411         ++adapter->link_irq;
1412         MPASS(adapter->hw.back != NULL);
1413         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1414
1415         if (reg_icr & E1000_ICR_RXO)
1416                 adapter->rx_overruns++;
1417
1418         if (is_igb) {
1419                 if (reg_icr & E1000_ICR_LSC)
1420                         em_handle_link(adapter->ctx);
1421                 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC);
1422                 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1423         } else {
1424                 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1425                         em_handle_link(adapter->ctx);
1426                 }
1427                 E1000_WRITE_REG(&adapter->hw, E1000_IMS,
1428                                         EM_MSIX_LINK | E1000_IMS_LSC);
1429
1430                 /*
1431                  * Because we must read the ICR for this interrupt
1432                  * it may clear other causes using autoclear, for
1433                  * this reason we simply create a soft interrupt
1434                  * for all these vectors.
1435                  */
1436                 if (reg_icr) {
1437                         E1000_WRITE_REG(&adapter->hw,
1438                                         E1000_ICS, adapter->ims);
1439                 }
1440         }
1441         return (FILTER_HANDLED);
1442 }
1443
1444 static void
1445 em_handle_link(void *context)
1446 {
1447         if_ctx_t ctx = context;
1448         struct adapter *adapter = iflib_get_softc(ctx);
1449
1450         adapter->hw.mac.get_link_status = 1;
1451         iflib_admin_intr_deferred(ctx);
1452 }
1453
1454
1455 /*********************************************************************
1456  *
1457  *  Media Ioctl callback
1458  *
1459  *  This routine is called whenever the user queries the status of
1460  *  the interface using ifconfig.
1461  *
1462  **********************************************************************/
1463 static void
1464 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1465 {
1466         struct adapter *adapter = iflib_get_softc(ctx);
1467         u_char fiber_type = IFM_1000_SX;
1468
1469         INIT_DEBUGOUT("em_if_media_status: begin");
1470
1471         iflib_admin_intr_deferred(ctx);
1472
1473         ifmr->ifm_status = IFM_AVALID;
1474         ifmr->ifm_active = IFM_ETHER;
1475
1476         if (!adapter->link_active) {
1477                 return;
1478         }
1479
1480         ifmr->ifm_status |= IFM_ACTIVE;
1481
1482         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
1483             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1484                 if (adapter->hw.mac.type == e1000_82545)
1485                         fiber_type = IFM_1000_LX;
1486                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1487         } else {
1488                 switch (adapter->link_speed) {
1489                 case 10:
1490                         ifmr->ifm_active |= IFM_10_T;
1491                         break;
1492                 case 100:
1493                         ifmr->ifm_active |= IFM_100_TX;
1494                         break;
1495                 case 1000:
1496                         ifmr->ifm_active |= IFM_1000_T;
1497                         break;
1498                 }
1499                 if (adapter->link_duplex == FULL_DUPLEX)
1500                         ifmr->ifm_active |= IFM_FDX;
1501                 else
1502                         ifmr->ifm_active |= IFM_HDX;
1503         }
1504 }
1505
1506 /*********************************************************************
1507  *
1508  *  Media Ioctl callback
1509  *
1510  *  This routine is called when the user changes speed/duplex using
1511  *  media/mediopt option with ifconfig.
1512  *
1513  **********************************************************************/
1514 static int
1515 em_if_media_change(if_ctx_t ctx)
1516 {
1517         struct adapter *adapter = iflib_get_softc(ctx);
1518         struct ifmedia *ifm = iflib_get_media(ctx);
1519
1520         INIT_DEBUGOUT("em_if_media_change: begin");
1521
1522         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1523                 return (EINVAL);
1524
1525         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1526         case IFM_AUTO:
1527                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1528                 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1529                 break;
1530         case IFM_1000_LX:
1531         case IFM_1000_SX:
1532         case IFM_1000_T:
1533                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1534                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1535                 break;
1536         case IFM_100_TX:
1537                 adapter->hw.mac.autoneg = FALSE;
1538                 adapter->hw.phy.autoneg_advertised = 0;
1539                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1540                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1541                 else
1542                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1543                 break;
1544         case IFM_10_T:
1545                 adapter->hw.mac.autoneg = FALSE;
1546                 adapter->hw.phy.autoneg_advertised = 0;
1547                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1548                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1549                 else
1550                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1551                 break;
1552         default:
1553                 device_printf(adapter->dev, "Unsupported media type\n");
1554         }
1555
1556         em_if_init(ctx);
1557
1558         return (0);
1559 }
1560
1561 static int
1562 em_if_set_promisc(if_ctx_t ctx, int flags)
1563 {
1564         struct adapter *adapter = iflib_get_softc(ctx);
1565         u32 reg_rctl;
1566
1567         em_disable_promisc(ctx);
1568
1569         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1570
1571         if (flags & IFF_PROMISC) {
1572                 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1573                 /* Turn this on if you want to see bad packets */
1574                 if (em_debug_sbp)
1575                         reg_rctl |= E1000_RCTL_SBP;
1576                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1577         } else if (flags & IFF_ALLMULTI) {
1578                 reg_rctl |= E1000_RCTL_MPE;
1579                 reg_rctl &= ~E1000_RCTL_UPE;
1580                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1581         }
1582         return (0);
1583 }
1584
1585 static void
1586 em_disable_promisc(if_ctx_t ctx)
1587 {
1588         struct adapter *adapter = iflib_get_softc(ctx);
1589         struct ifnet *ifp = iflib_get_ifp(ctx);
1590         u32 reg_rctl;
1591         int mcnt = 0;
1592
1593         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1594         reg_rctl &= (~E1000_RCTL_UPE);
1595         if (if_getflags(ifp) & IFF_ALLMULTI)
1596                 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1597         else
1598                 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES);
1599         /* Don't disable if in MAX groups */
1600         if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1601                 reg_rctl &=  (~E1000_RCTL_MPE);
1602         reg_rctl &=  (~E1000_RCTL_SBP);
1603         E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1604 }
1605
1606
1607 /*********************************************************************
1608  *  Multicast Update
1609  *
1610  *  This routine is called whenever multicast address list is updated.
1611  *
1612  **********************************************************************/
1613
1614 static void
1615 em_if_multi_set(if_ctx_t ctx)
1616 {
1617         struct adapter *adapter = iflib_get_softc(ctx);
1618         struct ifnet *ifp = iflib_get_ifp(ctx);
1619         u32 reg_rctl = 0;
1620         u8  *mta; /* Multicast array memory */
1621         int mcnt = 0;
1622
1623         IOCTL_DEBUGOUT("em_set_multi: begin");
1624
1625         mta = adapter->mta;
1626         bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1627
1628         if (adapter->hw.mac.type == e1000_82542 &&
1629             adapter->hw.revision_id == E1000_REVISION_2) {
1630                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1631                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1632                         e1000_pci_clear_mwi(&adapter->hw);
1633                 reg_rctl |= E1000_RCTL_RST;
1634                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1635                 msec_delay(5);
1636         }
1637
1638         if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES);
1639
1640         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1641                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1642                 reg_rctl |= E1000_RCTL_MPE;
1643                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1644         } else
1645                 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
1646
1647         if (adapter->hw.mac.type == e1000_82542 &&
1648             adapter->hw.revision_id == E1000_REVISION_2) {
1649                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1650                 reg_rctl &= ~E1000_RCTL_RST;
1651                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1652                 msec_delay(5);
1653                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1654                         e1000_pci_set_mwi(&adapter->hw);
1655         }
1656 }
1657
1658
1659 /*********************************************************************
1660  *  Timer routine
1661  *
1662  *  This routine checks for link status and updates statistics.
1663  *
1664  **********************************************************************/
1665
1666 static void
1667 em_if_timer(if_ctx_t ctx, uint16_t qid)
1668 {
1669         struct adapter *adapter = iflib_get_softc(ctx);
1670         struct em_rx_queue *que;
1671         int i;
1672         int trigger = 0;
1673
1674         if (qid != 0)
1675                 return;
1676
1677         iflib_admin_intr_deferred(ctx);
1678
1679         /* Mask to use in the irq trigger */
1680         if (adapter->intr_type == IFLIB_INTR_MSIX) {
1681                 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++)
1682                         trigger |= que->eims;
1683         } else {
1684                 trigger = E1000_ICS_RXDMT0;
1685         }
1686 }
1687
1688
1689 static void
1690 em_if_update_admin_status(if_ctx_t ctx)
1691 {
1692         struct adapter *adapter = iflib_get_softc(ctx);
1693         struct e1000_hw *hw = &adapter->hw;
1694         struct ifnet *ifp = iflib_get_ifp(ctx);
1695         device_t dev = iflib_get_dev(ctx);
1696         u32 link_check, thstat, ctrl;
1697
1698         link_check = thstat = ctrl = 0;
1699         /* Get the cached link value or read phy for real */
1700         switch (hw->phy.media_type) {
1701         case e1000_media_type_copper:
1702                 if (hw->mac.get_link_status) {
1703                         if (hw->mac.type == e1000_pch_spt)
1704                                 msec_delay(50);
1705                         /* Do the work to read phy */
1706                         e1000_check_for_link(hw);
1707                         link_check = !hw->mac.get_link_status;
1708                         if (link_check) /* ESB2 fix */
1709                                 e1000_cfg_on_link_up(hw);
1710                 } else {
1711                         link_check = TRUE;
1712                 }
1713                 break;
1714         case e1000_media_type_fiber:
1715                 e1000_check_for_link(hw);
1716                 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1717                             E1000_STATUS_LU);
1718                 break;
1719         case e1000_media_type_internal_serdes:
1720                 e1000_check_for_link(hw);
1721                 link_check = adapter->hw.mac.serdes_has_link;
1722                 break;
1723         /* VF device is type_unknown */
1724         case e1000_media_type_unknown:
1725                 e1000_check_for_link(hw);
1726                 link_check = !hw->mac.get_link_status;
1727                 /* FALLTHROUGH */
1728         default:
1729                 break;
1730         }
1731
1732         /* Check for thermal downshift or shutdown */
1733         if (hw->mac.type == e1000_i350) {
1734                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1735                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1736         }
1737
1738         /* Now check for a transition */
1739         if (link_check && (adapter->link_active == 0)) {
1740                 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
1741                     &adapter->link_duplex);
1742                 /* Check if we must disable SPEED_MODE bit on PCI-E */
1743                 if ((adapter->link_speed != SPEED_1000) &&
1744                     ((hw->mac.type == e1000_82571) ||
1745                     (hw->mac.type == e1000_82572))) {
1746                         int tarc0;
1747                         tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1748                         tarc0 &= ~TARC_SPEED_MODE_BIT;
1749                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1750                 }
1751                 if (bootverbose)
1752                         device_printf(dev, "Link is up %d Mbps %s\n",
1753                             adapter->link_speed,
1754                             ((adapter->link_duplex == FULL_DUPLEX) ?
1755                             "Full Duplex" : "Half Duplex"));
1756                 adapter->link_active = 1;
1757                 adapter->smartspeed = 0;
1758                 if_setbaudrate(ifp, adapter->link_speed * 1000000);
1759                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1760                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1761                         device_printf(dev, "Link: thermal downshift\n");
1762                 /* Delay Link Up for Phy update */
1763                 if (((hw->mac.type == e1000_i210) ||
1764                     (hw->mac.type == e1000_i211)) &&
1765                     (hw->phy.id == I210_I_PHY_ID))
1766                         msec_delay(I210_LINK_DELAY);
1767                 /* Reset if the media type changed. */
1768                 if ((hw->dev_spec._82575.media_changed) &&
1769                         (adapter->hw.mac.type >= igb_mac_min)) {
1770                         hw->dev_spec._82575.media_changed = false;
1771                         adapter->flags |= IGB_MEDIA_RESET;
1772                         em_reset(ctx);
1773                 }
1774                 iflib_link_state_change(ctx, LINK_STATE_UP, ifp->if_baudrate);
1775                 printf("Link state changed to up\n");
1776         } else if (!link_check && (adapter->link_active == 1)) {
1777                 if_setbaudrate(ifp, 0);
1778                 adapter->link_speed = 0;
1779                 adapter->link_duplex = 0;
1780                 if (bootverbose)
1781                         device_printf(dev, "Link is Down\n");
1782                 adapter->link_active = 0;
1783                 iflib_link_state_change(ctx, LINK_STATE_DOWN, ifp->if_baudrate);
1784                 printf("link state changed to down\n");
1785         }
1786         em_update_stats_counters(adapter);
1787
1788         /* Reset LAA into RAR[0] on 82571 */
1789         if ((adapter->hw.mac.type == e1000_82571) &&
1790             e1000_get_laa_state_82571(&adapter->hw))
1791                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1792
1793         if (adapter->hw.mac.type < em_mac_min)
1794                 lem_smartspeed(adapter);
1795
1796         E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC);
1797 }
1798
1799 /*********************************************************************
1800  *
1801  *  This routine disables all traffic on the adapter by issuing a
1802  *  global reset on the MAC and deallocates TX/RX buffers.
1803  *
1804  *  This routine should always be called with BOTH the CORE
1805  *  and TX locks.
1806  **********************************************************************/
1807
1808 static void
1809 em_if_stop(if_ctx_t ctx)
1810 {
1811         struct adapter *adapter = iflib_get_softc(ctx);
1812
1813         INIT_DEBUGOUT("em_stop: begin");
1814
1815         e1000_reset_hw(&adapter->hw);
1816         if (adapter->hw.mac.type >= e1000_82544)
1817                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0);
1818
1819         e1000_led_off(&adapter->hw);
1820         e1000_cleanup_led(&adapter->hw);
1821 }
1822
1823
1824 /*********************************************************************
1825  *
1826  *  Determine hardware revision.
1827  *
1828  **********************************************************************/
1829 static void
1830 em_identify_hardware(if_ctx_t ctx)
1831 {
1832         device_t dev = iflib_get_dev(ctx);
1833         struct adapter *adapter = iflib_get_softc(ctx);
1834
1835         /* Make sure our PCI config space has the necessary stuff set */
1836         adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1837
1838         /* Save off the information about this board */
1839         adapter->hw.vendor_id = pci_get_vendor(dev);
1840         adapter->hw.device_id = pci_get_device(dev);
1841         adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1842         adapter->hw.subsystem_vendor_id =
1843             pci_read_config(dev, PCIR_SUBVEND_0, 2);
1844         adapter->hw.subsystem_device_id =
1845             pci_read_config(dev, PCIR_SUBDEV_0, 2);
1846
1847         /* Do Shared Code Init and Setup */
1848         if (e1000_set_mac_type(&adapter->hw)) {
1849                 device_printf(dev, "Setup init failure\n");
1850                 return;
1851         }
1852 }
1853
1854 static int
1855 em_allocate_pci_resources(if_ctx_t ctx)
1856 {
1857         struct adapter *adapter = iflib_get_softc(ctx);
1858         device_t dev = iflib_get_dev(ctx);
1859         int rid, val;
1860
1861         rid = PCIR_BAR(0);
1862         adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1863             &rid, RF_ACTIVE);
1864         if (adapter->memory == NULL) {
1865                 device_printf(dev, "Unable to allocate bus resource: memory\n");
1866                 return (ENXIO);
1867         }
1868         adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory);
1869         adapter->osdep.mem_bus_space_handle =
1870             rman_get_bushandle(adapter->memory);
1871         adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle;
1872
1873         /* Only older adapters use IO mapping */
1874         if (adapter->hw.mac.type < em_mac_min &&
1875             adapter->hw.mac.type > e1000_82543) {
1876                 /* Figure our where our IO BAR is ? */
1877                 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1878                         val = pci_read_config(dev, rid, 4);
1879                         if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1880                                 adapter->io_rid = rid;
1881                                 break;
1882                         }
1883                         rid += 4;
1884                         /* check for 64bit BAR */
1885                         if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1886                                 rid += 4;
1887                 }
1888                 if (rid >= PCIR_CIS) {
1889                         device_printf(dev, "Unable to locate IO BAR\n");
1890                         return (ENXIO);
1891                 }
1892                 adapter->ioport = bus_alloc_resource_any(dev,
1893                     SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE);
1894                 if (adapter->ioport == NULL) {
1895                         device_printf(dev, "Unable to allocate bus resource: "
1896                             "ioport\n");
1897                         return (ENXIO);
1898                 }
1899                 adapter->hw.io_base = 0;
1900                 adapter->osdep.io_bus_space_tag =
1901                     rman_get_bustag(adapter->ioport);
1902                 adapter->osdep.io_bus_space_handle =
1903                     rman_get_bushandle(adapter->ioport);
1904         }
1905
1906         adapter->hw.back = &adapter->osdep;
1907
1908         return (0);
1909 }
1910
1911 static int
1912 igb_intr_assign(if_ctx_t ctx, int msix)
1913 {
1914         struct adapter *adapter = iflib_get_softc(ctx);
1915         struct em_rx_queue *rx_que = adapter->rx_queues;
1916         struct em_tx_queue *tx_que = adapter->tx_queues;
1917         int error, rid, i, vector = 0, rx_vectors;
1918         char buf[16];
1919
1920         /* First set up ring resources */
1921         for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) {
1922                 rid = vector + 1;
1923                 snprintf(buf, sizeof(buf), "rxq%d", i);
1924                 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX,
1925                                 em_msix_que, rx_que, rx_que->me, buf);
1926                 if (error) {
1927                         device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d\n", i, error);
1928                         adapter->rx_num_queues = i;
1929                         goto fail;
1930                 }
1931
1932                 rx_que->msix =  vector;
1933
1934                 /*
1935                  * Set the bit to enable interrupt
1936                  * in E1000_IMS -- bits 20 and 21
1937                  * are for RX0 and RX1, note this has
1938                  * NOTHING to do with the MSIX vector
1939                  */
1940                 if (adapter->hw.mac.type == e1000_82574) {
1941                         rx_que->eims = 1 << (20 + i);
1942                         adapter->ims |= rx_que->eims;
1943                         adapter->ivars |= (8 | rx_que->msix) << (i * 4);
1944                 } else if (adapter->hw.mac.type == e1000_82575)
1945                         rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
1946                 else
1947                         rx_que->eims = 1 << vector;
1948         }
1949         rx_vectors = vector;
1950
1951         vector = 0;
1952         for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) {
1953                 snprintf(buf, sizeof(buf), "txq%d", i);
1954                 tx_que = &adapter->tx_queues[i];
1955                 tx_que->msix = adapter->rx_queues[i % adapter->rx_num_queues].msix;
1956                 rid = rman_get_start(adapter->rx_queues[i % adapter->rx_num_queues].que_irq.ii_res);
1957                 iflib_softirq_alloc_generic(ctx, rid, IFLIB_INTR_TX, tx_que, tx_que->me, buf);
1958
1959                 if (adapter->hw.mac.type == e1000_82574) {
1960                         tx_que->eims = 1 << (22 + i);
1961                         adapter->ims |= tx_que->eims;
1962                         adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
1963                 } else if (adapter->hw.mac.type == e1000_82575) {
1964                         tx_que->eims = E1000_EICR_TX_QUEUE0 << (i %  adapter->tx_num_queues);
1965                 } else {
1966                         tx_que->eims = 1 << (i %  adapter->tx_num_queues);
1967                 }
1968         }
1969
1970         /* Link interrupt */
1971         rid = rx_vectors + 1;
1972         error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq");
1973
1974         if (error) {
1975                 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
1976                 goto fail;
1977         }
1978         adapter->linkvec = rx_vectors;
1979         if (adapter->hw.mac.type < igb_mac_min) {
1980                 adapter->ivars |=  (8 | rx_vectors) << 16;
1981                 adapter->ivars |= 0x80000000;
1982         }
1983         return (0);
1984 fail:
1985         iflib_irq_free(ctx, &adapter->irq);
1986         rx_que = adapter->rx_queues;
1987         for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++)
1988                 iflib_irq_free(ctx, &rx_que->que_irq);
1989         return (error);
1990 }
1991
1992 /*********************************************************************
1993  *
1994  *  Setup the MSIX Interrupt handlers
1995  *
1996  **********************************************************************/
1997 static int
1998 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
1999 {
2000         struct adapter *adapter = iflib_get_softc(ctx);
2001         struct em_rx_queue *rx_que = adapter->rx_queues;
2002         struct em_tx_queue *tx_que = adapter->tx_queues;
2003         int error, rid, i, vector = 0;
2004         char buf[16];
2005
2006         if (adapter->hw.mac.type >= igb_mac_min) {
2007                 return igb_intr_assign(ctx, msix);
2008         }
2009
2010         /* First set up ring resources */
2011         for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) {
2012                 rid = vector + 1;
2013                 snprintf(buf, sizeof(buf), "rxq%d", i);
2014                 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RX, em_msix_que, rx_que, rx_que->me, buf);
2015                 if (error) {
2016                         device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
2017                         adapter->rx_num_queues = i + 1;
2018                         goto fail;
2019                 }
2020
2021                 rx_que->msix =  vector;
2022
2023                 /*
2024                  * Set the bit to enable interrupt
2025                  * in E1000_IMS -- bits 20 and 21
2026                  * are for RX0 and RX1, note this has
2027                  * NOTHING to do with the MSIX vector
2028                  */
2029                 if (adapter->hw.mac.type == e1000_82574) {
2030                         rx_que->eims = 1 << (20 + i);
2031                         adapter->ims |= rx_que->eims;
2032                         adapter->ivars |= (8 | rx_que->msix) << (i * 4);
2033                 } else if (adapter->hw.mac.type == e1000_82575)
2034                         rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
2035                 else
2036                         rx_que->eims = 1 << vector;
2037         }
2038
2039         for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) {
2040                 rid = vector + 1;
2041                 snprintf(buf, sizeof(buf), "txq%d", i);
2042                 tx_que = &adapter->tx_queues[i];
2043
2044                 error = iflib_irq_alloc_generic(ctx, &tx_que->que_irq, rid, IFLIB_INTR_TX, em_msix_que, tx_que, tx_que->me, buf);
2045                 if (error) {
2046                         device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
2047                         adapter->tx_num_queues = i + 1;
2048                         goto fail;
2049                 }
2050                 tx_que->msix = vector;
2051
2052                 /*
2053                  * Set the bit to enable interrupt
2054                  * in E1000_IMS -- bits 22 and 23
2055                  * are for TX0 and TX1, note this has
2056                  * NOTHING to do with the MSIX vector
2057                  */
2058                 if (adapter->hw.mac.type == e1000_82574) {
2059                         tx_que->eims = 1 << (22 + i);
2060                         adapter->ims |= tx_que->eims;
2061                         adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
2062                 } else if (adapter->hw.mac.type == e1000_82575) {
2063                         tx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
2064                 } else {
2065                         tx_que->eims = 1 << vector;
2066                 }
2067         }
2068
2069         /* Link interrupt */
2070         rid = vector + 1;
2071         error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq");
2072
2073         if (error) {
2074                 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
2075                 goto fail;
2076         }
2077
2078         adapter->linkvec = vector;
2079         if (adapter->hw.mac.type < igb_mac_min) {
2080                 adapter->ivars |=  (8 | vector) << 16;
2081                 adapter->ivars |= 0x80000000;
2082         }
2083         return (0);
2084 fail:
2085         iflib_irq_free(ctx, &adapter->irq);
2086         rx_que = adapter->rx_queues;
2087         for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++)
2088                 iflib_irq_free(ctx, &rx_que->que_irq);
2089         return (error);
2090 }
2091
2092 static void
2093 igb_configure_queues(struct adapter *adapter)
2094 {
2095         struct e1000_hw *hw = &adapter->hw;
2096         struct em_rx_queue *rx_que;
2097         struct em_tx_queue *tx_que;
2098         u32 tmp, ivar = 0, newitr = 0;
2099
2100         /* First turn on RSS capability */
2101         if (adapter->hw.mac.type != e1000_82575)
2102                 E1000_WRITE_REG(hw, E1000_GPIE,
2103                     E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
2104                     E1000_GPIE_PBA | E1000_GPIE_NSICR);
2105
2106         /* Turn on MSIX */
2107         switch (adapter->hw.mac.type) {
2108         case e1000_82580:
2109         case e1000_i350:
2110         case e1000_i354:
2111         case e1000_i210:
2112         case e1000_i211:
2113         case e1000_vfadapt:
2114         case e1000_vfadapt_i350:
2115                 /* RX entries */
2116                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2117                         u32 index = i >> 1;
2118                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2119                         rx_que = &adapter->rx_queues[i];
2120                         if (i & 1) {
2121                                 ivar &= 0xFF00FFFF;
2122                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2123                         } else {
2124                                 ivar &= 0xFFFFFF00;
2125                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2126                         }
2127                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2128                 }
2129                 /* TX entries */
2130                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2131                         u32 index = i >> 1;
2132                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2133                         tx_que = &adapter->tx_queues[i];
2134                         if (i & 1) {
2135                                 ivar &= 0x00FFFFFF;
2136                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2137                         } else {
2138                                 ivar &= 0xFFFF00FF;
2139                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2140                         }
2141                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2142                         adapter->que_mask |= tx_que->eims;
2143                 }
2144
2145                 /* And for the link interrupt */
2146                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2147                 adapter->link_mask = 1 << adapter->linkvec;
2148                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2149                 break;
2150         case e1000_82576:
2151                 /* RX entries */
2152                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2153                         u32 index = i & 0x7; /* Each IVAR has two entries */
2154                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2155                         rx_que = &adapter->rx_queues[i];
2156                         if (i < 8) {
2157                                 ivar &= 0xFFFFFF00;
2158                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2159                         } else {
2160                                 ivar &= 0xFF00FFFF;
2161                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2162                         }
2163                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2164                         adapter->que_mask |= rx_que->eims;
2165                 }
2166                 /* TX entries */
2167                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2168                         u32 index = i & 0x7; /* Each IVAR has two entries */
2169                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2170                         tx_que = &adapter->tx_queues[i];
2171                         if (i < 8) {
2172                                 ivar &= 0xFFFF00FF;
2173                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2174                         } else {
2175                                 ivar &= 0x00FFFFFF;
2176                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2177                         }
2178                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2179                         adapter->que_mask |= tx_que->eims;
2180                 }
2181
2182                 /* And for the link interrupt */
2183                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2184                 adapter->link_mask = 1 << adapter->linkvec;
2185                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2186                 break;
2187
2188         case e1000_82575:
2189                 /* enable MSI-X support*/
2190                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2191                 tmp |= E1000_CTRL_EXT_PBA_CLR;
2192                 /* Auto-Mask interrupts upon ICR read. */
2193                 tmp |= E1000_CTRL_EXT_EIAME;
2194                 tmp |= E1000_CTRL_EXT_IRCA;
2195                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2196
2197                 /* Queues */
2198                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2199                         rx_que = &adapter->rx_queues[i];
2200                         tmp = E1000_EICR_RX_QUEUE0 << i;
2201                         tmp |= E1000_EICR_TX_QUEUE0 << i;
2202                         rx_que->eims = tmp;
2203                         E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2204                             i, rx_que->eims);
2205                         adapter->que_mask |= rx_que->eims;
2206                 }
2207
2208                 /* Link */
2209                 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec),
2210                     E1000_EIMS_OTHER);
2211                 adapter->link_mask |= E1000_EIMS_OTHER;
2212         default:
2213                 break;
2214         }
2215
2216         /* Set the starting interrupt rate */
2217         if (em_max_interrupt_rate > 0)
2218                 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2219
2220         if (hw->mac.type == e1000_82575)
2221                 newitr |= newitr << 16;
2222         else
2223                 newitr |= E1000_EITR_CNT_IGNR;
2224
2225         for (int i = 0; i < adapter->rx_num_queues; i++) {
2226                 rx_que = &adapter->rx_queues[i];
2227                 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2228         }
2229
2230         return;
2231 }
2232
2233 static void
2234 em_free_pci_resources(if_ctx_t ctx)
2235 {
2236         struct adapter *adapter = iflib_get_softc(ctx);
2237         struct em_rx_queue *rxque = adapter->rx_queues;
2238         struct em_tx_queue *txque = adapter->tx_queues;
2239         device_t dev = iflib_get_dev(ctx);
2240         int is_igb;
2241
2242         is_igb = (adapter->hw.mac.type >= igb_mac_min);
2243         /* Release all msix queue resources */
2244         if (adapter->intr_type == IFLIB_INTR_MSIX)
2245                 iflib_irq_free(ctx, &adapter->irq);
2246
2247         for (int i = 0; i < adapter->rx_num_queues; i++, rxque++) {
2248                 iflib_irq_free(ctx, &rxque->que_irq);
2249         }
2250
2251         if (!is_igb) {
2252                 for (int i = 0; i < adapter->tx_num_queues; i++, txque++) {
2253                         iflib_irq_free(ctx, &txque->que_irq);
2254                 }
2255         }
2256
2257         /* First release all the interrupt resources */
2258         if (adapter->memory != NULL) {
2259                 bus_release_resource(dev, SYS_RES_MEMORY,
2260                                      PCIR_BAR(0), adapter->memory);
2261                 adapter->memory = NULL;
2262         }
2263
2264         if (adapter->flash != NULL) {
2265                 bus_release_resource(dev, SYS_RES_MEMORY,
2266                                      EM_FLASH, adapter->flash);
2267                 adapter->flash = NULL;
2268         }
2269         if (adapter->ioport != NULL)
2270                 bus_release_resource(dev, SYS_RES_IOPORT,
2271                     adapter->io_rid, adapter->ioport);
2272 }
2273
2274 /* Setup MSI or MSI/X */
2275 static int
2276 em_setup_msix(if_ctx_t ctx)
2277 {
2278         struct adapter *adapter = iflib_get_softc(ctx);
2279
2280         if (adapter->hw.mac.type == e1000_82574) {
2281                 em_enable_vectors_82574(ctx);
2282         }
2283         return (0);
2284 }
2285
2286 /*********************************************************************
2287  *
2288  *  Initialize the hardware to a configuration
2289  *  as specified by the adapter structure.
2290  *
2291  **********************************************************************/
2292
2293 static void
2294 lem_smartspeed(struct adapter *adapter)
2295 {
2296         u16 phy_tmp;
2297
2298         if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) ||
2299             adapter->hw.mac.autoneg == 0 ||
2300             (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2301                 return;
2302
2303         if (adapter->smartspeed == 0) {
2304                 /* If Master/Slave config fault is asserted twice,
2305                  * we assume back-to-back */
2306                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2307                 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2308                         return;
2309                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2310                 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2311                         e1000_read_phy_reg(&adapter->hw,
2312                             PHY_1000T_CTRL, &phy_tmp);
2313                         if(phy_tmp & CR_1000T_MS_ENABLE) {
2314                                 phy_tmp &= ~CR_1000T_MS_ENABLE;
2315                                 e1000_write_phy_reg(&adapter->hw,
2316                                     PHY_1000T_CTRL, phy_tmp);
2317                                 adapter->smartspeed++;
2318                                 if(adapter->hw.mac.autoneg &&
2319                                    !e1000_copper_link_autoneg(&adapter->hw) &&
2320                                    !e1000_read_phy_reg(&adapter->hw,
2321                                     PHY_CONTROL, &phy_tmp)) {
2322                                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2323                                                     MII_CR_RESTART_AUTO_NEG);
2324                                         e1000_write_phy_reg(&adapter->hw,
2325                                             PHY_CONTROL, phy_tmp);
2326                                 }
2327                         }
2328                 }
2329                 return;
2330         } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2331                 /* If still no link, perhaps using 2/3 pair cable */
2332                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2333                 phy_tmp |= CR_1000T_MS_ENABLE;
2334                 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2335                 if(adapter->hw.mac.autoneg &&
2336                    !e1000_copper_link_autoneg(&adapter->hw) &&
2337                    !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2338                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2339                                     MII_CR_RESTART_AUTO_NEG);
2340                         e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2341                 }
2342         }
2343         /* Restart process after EM_SMARTSPEED_MAX iterations */
2344         if(adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2345                 adapter->smartspeed = 0;
2346 }
2347
2348 /*********************************************************************
2349  *
2350  *  Initialize the DMA Coalescing feature
2351  *
2352  **********************************************************************/
2353 static void
2354 igb_init_dmac(struct adapter *adapter, u32 pba)
2355 {
2356         device_t        dev = adapter->dev;
2357         struct e1000_hw *hw = &adapter->hw;
2358         u32             dmac, reg = ~E1000_DMACR_DMAC_EN;
2359         u16             hwm;
2360         u16             max_frame_size;
2361
2362         if (hw->mac.type == e1000_i211)
2363                 return;
2364
2365         max_frame_size = adapter->shared->isc_max_frame_size;
2366         if (hw->mac.type > e1000_82580) {
2367
2368                 if (adapter->dmac == 0) { /* Disabling it */
2369                         E1000_WRITE_REG(hw, E1000_DMACR, reg);
2370                         return;
2371                 } else
2372                         device_printf(dev, "DMA Coalescing enabled\n");
2373
2374                 /* Set starting threshold */
2375                 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
2376
2377                 hwm = 64 * pba - max_frame_size / 16;
2378                 if (hwm < 64 * (pba - 6))
2379                         hwm = 64 * (pba - 6);
2380                 reg = E1000_READ_REG(hw, E1000_FCRTC);
2381                 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
2382                 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
2383                     & E1000_FCRTC_RTH_COAL_MASK);
2384                 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
2385
2386
2387                 dmac = pba - max_frame_size / 512;
2388                 if (dmac < pba - 10)
2389                         dmac = pba - 10;
2390                 reg = E1000_READ_REG(hw, E1000_DMACR);
2391                 reg &= ~E1000_DMACR_DMACTHR_MASK;
2392                 reg = ((dmac << E1000_DMACR_DMACTHR_SHIFT)
2393                     & E1000_DMACR_DMACTHR_MASK);
2394
2395                 /* transition to L0x or L1 if available..*/
2396                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
2397
2398                 /* Check if status is 2.5Gb backplane connection
2399                 * before configuration of watchdog timer, which is
2400                 * in msec values in 12.8usec intervals
2401                 * watchdog timer= msec values in 32usec intervals
2402                 * for non 2.5Gb connection
2403                 */
2404                 if (hw->mac.type == e1000_i354) {
2405                         int status = E1000_READ_REG(hw, E1000_STATUS);
2406                         if ((status & E1000_STATUS_2P5_SKU) &&
2407                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2408                                 reg |= ((adapter->dmac * 5) >> 6);
2409                         else
2410                                 reg |= (adapter->dmac >> 5);
2411                 } else {
2412                         reg |= (adapter->dmac >> 5);
2413                 }
2414
2415                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2416
2417                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
2418
2419                 /* Set the interval before transition */
2420                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
2421                 if (hw->mac.type == e1000_i350)
2422                         reg |= IGB_DMCTLX_DCFLUSH_DIS;
2423                 /*
2424                 ** in 2.5Gb connection, TTLX unit is 0.4 usec
2425                 ** which is 0x4*2 = 0xA. But delay is still 4 usec
2426                 */
2427                 if (hw->mac.type == e1000_i354) {
2428                         int status = E1000_READ_REG(hw, E1000_STATUS);
2429                         if ((status & E1000_STATUS_2P5_SKU) &&
2430                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2431                                 reg |= 0xA;
2432                         else
2433                                 reg |= 0x4;
2434                 } else {
2435                         reg |= 0x4;
2436                 }
2437
2438                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
2439
2440                 /* free space in tx packet buffer to wake from DMA coal */
2441                 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE -
2442                     (2 * max_frame_size)) >> 6);
2443
2444                 /* make low power state decision controlled by DMA coal */
2445                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2446                 reg &= ~E1000_PCIEMISC_LX_DECISION;
2447                 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
2448
2449         } else if (hw->mac.type == e1000_82580) {
2450                 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2451                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
2452                     reg & ~E1000_PCIEMISC_LX_DECISION);
2453                 E1000_WRITE_REG(hw, E1000_DMACR, 0);
2454         }
2455 }
2456
2457 static void
2458 em_reset(if_ctx_t ctx)
2459 {
2460         device_t dev = iflib_get_dev(ctx);
2461         struct adapter *adapter = iflib_get_softc(ctx);
2462         struct ifnet *ifp = iflib_get_ifp(ctx);
2463         struct e1000_hw *hw = &adapter->hw;
2464         u16 rx_buffer_size;
2465         u32 pba;
2466
2467         INIT_DEBUGOUT("em_reset: begin");
2468         /* Let the firmware know the OS is in control */
2469         em_get_hw_control(adapter);
2470
2471         /* Set up smart power down as default off on newer adapters. */
2472         if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2473             hw->mac.type == e1000_82572)) {
2474                 u16 phy_tmp = 0;
2475
2476                 /* Speed up time to link by disabling smart power down. */
2477                 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2478                 phy_tmp &= ~IGP02E1000_PM_SPD;
2479                 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2480         }
2481
2482         /*
2483          * Packet Buffer Allocation (PBA)
2484          * Writing PBA sets the receive portion of the buffer
2485          * the remainder is used for the transmit buffer.
2486          */
2487         switch (hw->mac.type) {
2488         /* Total Packet Buffer on these is 48K */
2489         case e1000_82571:
2490         case e1000_82572:
2491         case e1000_80003es2lan:
2492                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2493                 break;
2494         case e1000_82573: /* 82573: Total Packet Buffer is 32K */
2495                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2496                 break;
2497         case e1000_82574:
2498         case e1000_82583:
2499                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2500                 break;
2501         case e1000_ich8lan:
2502                 pba = E1000_PBA_8K;
2503                 break;
2504         case e1000_ich9lan:
2505         case e1000_ich10lan:
2506                 /* Boost Receive side for jumbo frames */
2507                 if (adapter->hw.mac.max_frame_size > 4096)
2508                         pba = E1000_PBA_14K;
2509                 else
2510                         pba = E1000_PBA_10K;
2511                 break;
2512         case e1000_pchlan:
2513         case e1000_pch2lan:
2514         case e1000_pch_lpt:
2515         case e1000_pch_spt:
2516                 pba = E1000_PBA_26K;
2517                 break;
2518         case e1000_82575:
2519                 pba = E1000_PBA_32K;
2520                 break;
2521         case e1000_82576:
2522         case e1000_vfadapt:
2523                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2524                 pba &= E1000_RXPBS_SIZE_MASK_82576;
2525                 break;
2526         case e1000_82580:
2527         case e1000_i350:
2528         case e1000_i354:
2529         case e1000_vfadapt_i350:
2530                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2531                 pba = e1000_rxpbs_adjust_82580(pba);
2532                 break;
2533         case e1000_i210:
2534         case e1000_i211:
2535                 pba = E1000_PBA_34K;
2536                 break;
2537         default:
2538                 if (adapter->hw.mac.max_frame_size > 8192)
2539                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2540                 else
2541                         pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2542         }
2543
2544         /* Special needs in case of Jumbo frames */
2545         if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) {
2546                 u32 tx_space, min_tx, min_rx;
2547                 pba = E1000_READ_REG(hw, E1000_PBA);
2548                 tx_space = pba >> 16;
2549                 pba &= 0xffff;
2550                 min_tx = (adapter->hw.mac.max_frame_size +
2551                     sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
2552                 min_tx = roundup2(min_tx, 1024);
2553                 min_tx >>= 10;
2554                 min_rx = adapter->hw.mac.max_frame_size;
2555                 min_rx = roundup2(min_rx, 1024);
2556                 min_rx >>= 10;
2557                 if (tx_space < min_tx &&
2558                     ((min_tx - tx_space) < pba)) {
2559                         pba = pba - (min_tx - tx_space);
2560                         /*
2561                          * if short on rx space, rx wins
2562                          * and must trump tx adjustment
2563                          */
2564                         if (pba < min_rx)
2565                                 pba = min_rx;
2566                 }
2567                 E1000_WRITE_REG(hw, E1000_PBA, pba);
2568         }
2569
2570         if (hw->mac.type < igb_mac_min)
2571                 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
2572
2573         INIT_DEBUGOUT1("em_reset: pba=%dK",pba);
2574
2575         /*
2576          * These parameters control the automatic generation (Tx) and
2577          * response (Rx) to Ethernet PAUSE frames.
2578          * - High water mark should allow for at least two frames to be
2579          *   received after sending an XOFF.
2580          * - Low water mark works best when it is very near the high water mark.
2581          *   This allows the receiver to restart by sending XON when it has
2582          *   drained a bit. Here we use an arbitrary value of 1500 which will
2583          *   restart after one full frame is pulled from the buffer. There
2584          *   could be several smaller frames in the buffer and if so they will
2585          *   not trigger the XON until their total number reduces the buffer
2586          *   by 1500.
2587          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2588          */
2589         rx_buffer_size = (pba & 0xffff) << 10;
2590         hw->fc.high_water = rx_buffer_size -
2591             roundup2(adapter->hw.mac.max_frame_size, 1024);
2592         hw->fc.low_water = hw->fc.high_water - 1500;
2593
2594         if (adapter->fc) /* locally set flow control value? */
2595                 hw->fc.requested_mode = adapter->fc;
2596         else
2597                 hw->fc.requested_mode = e1000_fc_full;
2598
2599         if (hw->mac.type == e1000_80003es2lan)
2600                 hw->fc.pause_time = 0xFFFF;
2601         else
2602                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
2603
2604         hw->fc.send_xon = TRUE;
2605
2606         /* Device specific overrides/settings */
2607         switch (hw->mac.type) {
2608         case e1000_pchlan:
2609                 /* Workaround: no TX flow ctrl for PCH */
2610                 hw->fc.requested_mode = e1000_fc_rx_pause;
2611                 hw->fc.pause_time = 0xFFFF; /* override */
2612                 if (if_getmtu(ifp) > ETHERMTU) {
2613                         hw->fc.high_water = 0x3500;
2614                         hw->fc.low_water = 0x1500;
2615                 } else {
2616                         hw->fc.high_water = 0x5000;
2617                         hw->fc.low_water = 0x3000;
2618                 }
2619                 hw->fc.refresh_time = 0x1000;
2620                 break;
2621         case e1000_pch2lan:
2622         case e1000_pch_lpt:
2623         case e1000_pch_spt:
2624                 hw->fc.high_water = 0x5C20;
2625                 hw->fc.low_water = 0x5048;
2626                 hw->fc.pause_time = 0x0650;
2627                 hw->fc.refresh_time = 0x0400;
2628                 /* Jumbos need adjusted PBA */
2629                 if (if_getmtu(ifp) > ETHERMTU)
2630                         E1000_WRITE_REG(hw, E1000_PBA, 12);
2631                 else
2632                         E1000_WRITE_REG(hw, E1000_PBA, 26);
2633                 break;
2634         case e1000_82575:
2635         case e1000_82576:
2636                 /* 8-byte granularity */
2637                 hw->fc.low_water = hw->fc.high_water - 8;
2638                 break;
2639         case e1000_82580:
2640         case e1000_i350:
2641         case e1000_i354:
2642         case e1000_i210:
2643         case e1000_i211:
2644         case e1000_vfadapt:
2645         case e1000_vfadapt_i350:
2646                 /* 16-byte granularity */
2647                 hw->fc.low_water = hw->fc.high_water - 16;
2648                 break;
2649         case e1000_ich9lan:
2650         case e1000_ich10lan:
2651                 if (if_getmtu(ifp) > ETHERMTU) {
2652                         hw->fc.high_water = 0x2800;
2653                         hw->fc.low_water = hw->fc.high_water - 8;
2654                         break;
2655                 }
2656                 /* FALLTHROUGH */
2657         default:
2658                 if (hw->mac.type == e1000_80003es2lan)
2659                         hw->fc.pause_time = 0xFFFF;
2660                 break;
2661         }
2662
2663         /* Issue a global reset */
2664         e1000_reset_hw(hw);
2665         if (adapter->hw.mac.type >= igb_mac_min) {
2666                 E1000_WRITE_REG(hw, E1000_WUC, 0);
2667         } else {
2668                 E1000_WRITE_REG(hw, E1000_WUFC, 0);
2669                 em_disable_aspm(adapter);
2670         }
2671         if (adapter->flags & IGB_MEDIA_RESET) {
2672                 e1000_setup_init_funcs(hw, TRUE);
2673                 e1000_get_bus_info(hw);
2674                 adapter->flags &= ~IGB_MEDIA_RESET;
2675         }
2676         /* and a re-init */
2677         if (e1000_init_hw(hw) < 0) {
2678                 device_printf(dev, "Hardware Initialization Failed\n");
2679                 return;
2680         }
2681         if (adapter->hw.mac.type >= igb_mac_min)
2682                 igb_init_dmac(adapter, pba);
2683
2684         E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2685         e1000_get_phy_info(hw);
2686         e1000_check_for_link(hw);
2687 }
2688
2689 #define RSSKEYLEN 10
2690 static void
2691 em_initialize_rss_mapping(struct adapter *adapter)
2692 {
2693         uint8_t  rss_key[4 * RSSKEYLEN];
2694         uint32_t reta = 0;
2695         struct e1000_hw *hw = &adapter->hw;
2696         int i;
2697
2698         /*
2699          * Configure RSS key
2700          */
2701         arc4rand(rss_key, sizeof(rss_key), 0);
2702         for (i = 0; i < RSSKEYLEN; ++i) {
2703                 uint32_t rssrk = 0;
2704
2705                 rssrk = EM_RSSRK_VAL(rss_key, i);
2706                 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2707         }
2708
2709         /*
2710          * Configure RSS redirect table in following fashion:
2711          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2712          */
2713         for (i = 0; i < sizeof(reta); ++i) {
2714                 uint32_t q;
2715
2716                 q = (i % adapter->rx_num_queues) << 7;
2717                 reta |= q << (8 * i);
2718         }
2719
2720         for (i = 0; i < 32; ++i)
2721                 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2722
2723         E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2724                         E1000_MRQC_RSS_FIELD_IPV4_TCP |
2725                         E1000_MRQC_RSS_FIELD_IPV4 |
2726                         E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2727                         E1000_MRQC_RSS_FIELD_IPV6_EX |
2728                         E1000_MRQC_RSS_FIELD_IPV6);
2729
2730 }
2731
2732 static void
2733 igb_initialize_rss_mapping(struct adapter *adapter)
2734 {
2735         struct e1000_hw *hw = &adapter->hw;
2736         int i;
2737         int queue_id;
2738         u32 reta;
2739         u32 rss_key[10], mrqc, shift = 0;
2740
2741         /* XXX? */
2742         if (adapter->hw.mac.type == e1000_82575)
2743                 shift = 6;
2744
2745         /*
2746          * The redirection table controls which destination
2747          * queue each bucket redirects traffic to.
2748          * Each DWORD represents four queues, with the LSB
2749          * being the first queue in the DWORD.
2750          *
2751          * This just allocates buckets to queues using round-robin
2752          * allocation.
2753          *
2754          * NOTE: It Just Happens to line up with the default
2755          * RSS allocation method.
2756          */
2757
2758         /* Warning FM follows */
2759         reta = 0;
2760         for (i = 0; i < 128; i++) {
2761 #ifdef RSS
2762                 queue_id = rss_get_indirection_to_bucket(i);
2763                 /*
2764                  * If we have more queues than buckets, we'll
2765                  * end up mapping buckets to a subset of the
2766                  * queues.
2767                  *
2768                  * If we have more buckets than queues, we'll
2769                  * end up instead assigning multiple buckets
2770                  * to queues.
2771                  *
2772                  * Both are suboptimal, but we need to handle
2773                  * the case so we don't go out of bounds
2774                  * indexing arrays and such.
2775                  */
2776                 queue_id = queue_id % adapter->rx_num_queues;
2777 #else
2778                 queue_id = (i % adapter->rx_num_queues);
2779 #endif
2780                 /* Adjust if required */
2781                 queue_id = queue_id << shift;
2782
2783                 /*
2784                  * The low 8 bits are for hash value (n+0);
2785                  * The next 8 bits are for hash value (n+1), etc.
2786                  */
2787                 reta = reta >> 8;
2788                 reta = reta | ( ((uint32_t) queue_id) << 24);
2789                 if ((i & 3) == 3) {
2790                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2791                         reta = 0;
2792                 }
2793         }
2794
2795         /* Now fill in hash table */
2796
2797         /*
2798          * MRQC: Multiple Receive Queues Command
2799          * Set queuing to RSS control, number depends on the device.
2800          */
2801         mrqc = E1000_MRQC_ENABLE_RSS_8Q;
2802
2803 #ifdef RSS
2804         /* XXX ew typecasting */
2805         rss_getkey((uint8_t *) &rss_key);
2806 #else
2807         arc4rand(&rss_key, sizeof(rss_key), 0);
2808 #endif
2809         for (i = 0; i < 10; i++)
2810                 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]);
2811
2812         /*
2813          * Configure the RSS fields to hash upon.
2814          */
2815         mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2816             E1000_MRQC_RSS_FIELD_IPV4_TCP);
2817         mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2818             E1000_MRQC_RSS_FIELD_IPV6_TCP);
2819         mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2820             E1000_MRQC_RSS_FIELD_IPV6_UDP);
2821         mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2822             E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2823
2824         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2825 }
2826
2827 /*********************************************************************
2828  *
2829  *  Setup networking device structure and register an interface.
2830  *
2831  **********************************************************************/
2832 static int
2833 em_setup_interface(if_ctx_t ctx)
2834 {
2835         struct ifnet *ifp = iflib_get_ifp(ctx);
2836         struct adapter *adapter = iflib_get_softc(ctx);
2837         if_softc_ctx_t scctx = adapter->shared;
2838         uint64_t cap = 0;
2839
2840         INIT_DEBUGOUT("em_setup_interface: begin");
2841
2842         /* TSO parameters */
2843         if_sethwtsomax(ifp, IP_MAXPACKET);
2844         /* Take m_pullup(9)'s in em_xmit() w/ TSO into acount. */
2845         if_sethwtsomaxsegcount(ifp, EM_MAX_SCATTER - 5);
2846         if_sethwtsomaxsegsize(ifp, EM_TSO_SEG_SIZE);
2847
2848         /* Single Queue */
2849         if (adapter->tx_num_queues == 1) {
2850                 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
2851                 if_setsendqready(ifp);
2852         }
2853
2854         cap = IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4;
2855         cap |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU;
2856
2857         /*
2858          * Tell the upper layer(s) we
2859          * support full VLAN capability
2860          */
2861         if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
2862         if_setcapabilitiesbit(ifp, cap, 0);
2863
2864         /*
2865          * Don't turn this on by default, if vlans are
2866          * created on another pseudo device (eg. lagg)
2867          * then vlan events are not passed thru, breaking
2868          * operation, but with HW FILTER off it works. If
2869          * using vlans directly on the em driver you can
2870          * enable this and get full hardware tag filtering.
2871          */
2872         if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWFILTER,0);
2873
2874         /* Enable only WOL MAGIC by default */
2875         if (adapter->wol) {
2876                 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC,
2877                             IFCAP_WOL_MCAST| IFCAP_WOL_UCAST);
2878         } else {
2879                 if_setcapenablebit(ifp, 0, IFCAP_WOL_MAGIC |
2880                              IFCAP_WOL_MCAST| IFCAP_WOL_UCAST);
2881         }
2882
2883         /*
2884          * Specify the media types supported by this adapter and register
2885          * callbacks to update media and link information
2886          */
2887         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
2888             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
2889                 u_char fiber_type = IFM_1000_SX;        /* default type */
2890
2891                 if (adapter->hw.mac.type == e1000_82545)
2892                         fiber_type = IFM_1000_LX;
2893                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
2894                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2895         } else {
2896                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2897                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2898                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2899                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2900                 if (adapter->hw.phy.type != e1000_phy_ife) {
2901                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2902                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2903                 }
2904         }
2905         ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2906         ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO);
2907         return (0);
2908 }
2909
2910 static int
2911 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
2912 {
2913         struct adapter *adapter = iflib_get_softc(ctx);
2914         if_softc_ctx_t scctx = adapter->shared;
2915         int error = E1000_SUCCESS;
2916         struct em_tx_queue *que;
2917         int i, j;
2918
2919         MPASS(adapter->tx_num_queues > 0);
2920         MPASS(adapter->tx_num_queues == ntxqsets);
2921
2922         /* First allocate the top level queue structs */
2923         if (!(adapter->tx_queues =
2924             (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
2925             adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2926                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2927                 return(ENOMEM);
2928         }
2929
2930         for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) {
2931                 /* Set up some basics */
2932
2933                 struct tx_ring *txr = &que->txr;
2934                 txr->adapter = que->adapter = adapter;
2935                 que->me = txr->me =  i;
2936
2937                 /* Allocate report status array */
2938                 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2939                         device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n");
2940                         error = ENOMEM;
2941                         goto fail;
2942                 }
2943                 for (j = 0; j < scctx->isc_ntxd[0]; j++)
2944                         txr->tx_rsq[j] = QIDX_INVALID;
2945                 /* get the virtual and physical address of the hardware queues */
2946                 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
2947                 txr->tx_paddr = paddrs[i*ntxqs];
2948         }
2949
2950         device_printf(iflib_get_dev(ctx), "allocated for %d tx_queues\n", adapter->tx_num_queues);
2951         return (0);
2952 fail:
2953         em_if_queues_free(ctx);
2954         return (error);
2955 }
2956
2957 static int
2958 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
2959 {
2960         struct adapter *adapter = iflib_get_softc(ctx);
2961         int error = E1000_SUCCESS;
2962         struct em_rx_queue *que;
2963         int i;
2964
2965         MPASS(adapter->rx_num_queues > 0);
2966         MPASS(adapter->rx_num_queues == nrxqsets);
2967
2968         /* First allocate the top level queue structs */
2969         if (!(adapter->rx_queues =
2970             (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
2971             adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2972                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2973                 error = ENOMEM;
2974                 goto fail;
2975         }
2976
2977         for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) {
2978                 /* Set up some basics */
2979                 struct rx_ring *rxr = &que->rxr;
2980                 rxr->adapter = que->adapter = adapter;
2981                 rxr->que = que;
2982                 que->me = rxr->me =  i;
2983
2984                 /* get the virtual and physical address of the hardware queues */
2985                 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
2986                 rxr->rx_paddr = paddrs[i*nrxqs];
2987         }
2988
2989         device_printf(iflib_get_dev(ctx), "allocated for %d rx_queues\n", adapter->rx_num_queues);
2990
2991         return (0);
2992 fail:
2993         em_if_queues_free(ctx);
2994         return (error);
2995 }
2996
2997 static void
2998 em_if_queues_free(if_ctx_t ctx)
2999 {
3000         struct adapter *adapter = iflib_get_softc(ctx);
3001         struct em_tx_queue *tx_que = adapter->tx_queues;
3002         struct em_rx_queue *rx_que = adapter->rx_queues;
3003
3004         if (tx_que != NULL) {
3005                 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
3006                         struct tx_ring *txr = &tx_que->txr;
3007                         if (txr->tx_rsq == NULL)
3008                                 break;
3009
3010                         free(txr->tx_rsq, M_DEVBUF);
3011                         txr->tx_rsq = NULL;
3012                 }
3013                 free(adapter->tx_queues, M_DEVBUF);
3014                 adapter->tx_queues = NULL;
3015         }
3016
3017         if (rx_que != NULL) {
3018                 free(adapter->rx_queues, M_DEVBUF);
3019                 adapter->rx_queues = NULL;
3020         }
3021
3022         em_release_hw_control(adapter);
3023
3024         if (adapter->mta != NULL) {
3025                 free(adapter->mta, M_DEVBUF);
3026         }
3027 }
3028
3029 /*********************************************************************
3030  *
3031  *  Enable transmit unit.
3032  *
3033  **********************************************************************/
3034 static void
3035 em_initialize_transmit_unit(if_ctx_t ctx)
3036 {
3037         struct adapter *adapter = iflib_get_softc(ctx);
3038         if_softc_ctx_t scctx = adapter->shared;
3039         struct em_tx_queue *que;
3040         struct tx_ring  *txr;
3041         struct e1000_hw *hw = &adapter->hw;
3042         u32 tctl, txdctl = 0, tarc, tipg = 0;
3043
3044         INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
3045
3046         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
3047                 u64 bus_addr;
3048                 caddr_t offp, endp;
3049
3050                 que = &adapter->tx_queues[i];
3051                 txr = &que->txr;
3052                 bus_addr = txr->tx_paddr;
3053
3054                 /* Clear checksum offload context. */
3055                 offp = (caddr_t)&txr->csum_flags;
3056                 endp = (caddr_t)(txr + 1);
3057                 bzero(offp, endp - offp);
3058
3059                 /* Base and Len of TX Ring */
3060                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
3061                     scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
3062                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
3063                     (u32)(bus_addr >> 32));
3064                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
3065                     (u32)bus_addr);
3066                 /* Init the HEAD/TAIL indices */
3067                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
3068                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
3069
3070                 HW_DEBUGOUT2("Base = %x, Length = %x\n",
3071                     E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)),
3072                     E1000_READ_REG(&adapter->hw, E1000_TDLEN(i)));
3073
3074                 txdctl = 0; /* clear txdctl */
3075                 txdctl |= 0x1f; /* PTHRESH */
3076                 txdctl |= 1 << 8; /* HTHRESH */
3077                 txdctl |= 1 << 16;/* WTHRESH */
3078                 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
3079                 txdctl |= E1000_TXDCTL_GRAN;
3080                 txdctl |= 1 << 25; /* LWTHRESH */
3081
3082                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
3083         }
3084
3085         /* Set the default values for the Tx Inter Packet Gap timer */
3086         switch (adapter->hw.mac.type) {
3087         case e1000_80003es2lan:
3088                 tipg = DEFAULT_82543_TIPG_IPGR1;
3089                 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
3090                     E1000_TIPG_IPGR2_SHIFT;
3091                 break;
3092         case e1000_82542:
3093                 tipg = DEFAULT_82542_TIPG_IPGT;
3094                 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3095                 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3096                 break;
3097         default:
3098                 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
3099                     (adapter->hw.phy.media_type ==
3100                     e1000_media_type_internal_serdes))
3101                         tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
3102                 else
3103                         tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
3104                 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3105                 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3106         }
3107
3108         E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
3109         E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value);
3110
3111         if(adapter->hw.mac.type >= e1000_82540)
3112                 E1000_WRITE_REG(&adapter->hw, E1000_TADV,
3113                     adapter->tx_abs_int_delay.value);
3114
3115         if ((adapter->hw.mac.type == e1000_82571) ||
3116             (adapter->hw.mac.type == e1000_82572)) {
3117                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3118                 tarc |= TARC_SPEED_MODE_BIT;
3119                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3120         } else if (adapter->hw.mac.type == e1000_80003es2lan) {
3121                 /* errata: program both queues to unweighted RR */
3122                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3123                 tarc |= 1;
3124                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3125                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
3126                 tarc |= 1;
3127                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
3128         } else if (adapter->hw.mac.type == e1000_82574) {
3129                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3130                 tarc |= TARC_ERRATA_BIT;
3131                 if ( adapter->tx_num_queues > 1) {
3132                         tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
3133                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3134                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
3135                 } else
3136                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3137         }
3138
3139         if (adapter->tx_int_delay.value > 0)
3140                 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3141
3142         /* Program the Transmit Control Register */
3143         tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
3144         tctl &= ~E1000_TCTL_CT;
3145         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
3146                    (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
3147
3148         if (adapter->hw.mac.type >= e1000_82571)
3149                 tctl |= E1000_TCTL_MULR;
3150
3151         /* This write will effectively turn on the transmit unit. */
3152         E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
3153
3154         if (hw->mac.type == e1000_pch_spt) {
3155                 u32 reg;
3156                 reg = E1000_READ_REG(hw, E1000_IOSFPC);
3157                 reg |= E1000_RCTL_RDMTS_HEX;
3158                 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
3159                 reg = E1000_READ_REG(hw, E1000_TARC(0));
3160                 reg |= E1000_TARC0_CB_MULTIQ_3_REQ;
3161                 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3162         }
3163 }
3164
3165 /*********************************************************************
3166  *
3167  *  Enable receive unit.
3168  *
3169  **********************************************************************/
3170
3171 static void
3172 em_initialize_receive_unit(if_ctx_t ctx)
3173 {
3174         struct adapter *adapter = iflib_get_softc(ctx);
3175         if_softc_ctx_t scctx = adapter->shared;
3176         struct ifnet *ifp = iflib_get_ifp(ctx);
3177         struct e1000_hw *hw = &adapter->hw;
3178         struct em_rx_queue *que;
3179         int i;
3180         u32 rctl, rxcsum, rfctl;
3181
3182         INIT_DEBUGOUT("em_initialize_receive_units: begin");
3183
3184         /*
3185          * Make sure receives are disabled while setting
3186          * up the descriptor ring
3187          */
3188         rctl = E1000_READ_REG(hw, E1000_RCTL);
3189         /* Do not disable if ever enabled on this hardware */
3190         if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
3191                 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3192
3193         /* Setup the Receive Control Register */
3194         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3195         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3196             E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3197             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3198
3199         /* Do not store bad packets */
3200         rctl &= ~E1000_RCTL_SBP;
3201
3202         /* Enable Long Packet receive */
3203         if (if_getmtu(ifp) > ETHERMTU)
3204                 rctl |= E1000_RCTL_LPE;
3205         else
3206                 rctl &= ~E1000_RCTL_LPE;
3207
3208         /* Strip the CRC */
3209         if (!em_disable_crc_stripping)
3210                 rctl |= E1000_RCTL_SECRC;
3211
3212         if (adapter->hw.mac.type >= e1000_82540) {
3213                 E1000_WRITE_REG(&adapter->hw, E1000_RADV,
3214                             adapter->rx_abs_int_delay.value);
3215
3216                 /*
3217                  * Set the interrupt throttling rate. Value is calculated
3218                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
3219                  */
3220                 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
3221         }
3222         E1000_WRITE_REG(&adapter->hw, E1000_RDTR,
3223             adapter->rx_int_delay.value);
3224
3225         /* Use extended rx descriptor formats */
3226         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3227         rfctl |= E1000_RFCTL_EXTEN;
3228         /*
3229          * When using MSIX interrupts we need to throttle
3230          * using the EITR register (82574 only)
3231          */
3232         if (hw->mac.type == e1000_82574) {
3233                 for (int i = 0; i < 4; i++)
3234                         E1000_WRITE_REG(hw, E1000_EITR_82574(i),
3235                             DEFAULT_ITR);
3236                 /* Disable accelerated acknowledge */
3237                 rfctl |= E1000_RFCTL_ACK_DIS;
3238         }
3239         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3240
3241         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
3242         if (if_getcapenable(ifp) & IFCAP_RXCSUM &&
3243             adapter->hw.mac.type >= e1000_82543) {
3244                 if (adapter->tx_num_queues > 1) {
3245                         if (adapter->hw.mac.type >= igb_mac_min) {
3246                                 rxcsum |= E1000_RXCSUM_PCSD;
3247                                 if (hw->mac.type != e1000_82575)
3248                                         rxcsum |= E1000_RXCSUM_CRCOFL;
3249                         } else
3250                                 rxcsum |= E1000_RXCSUM_TUOFL |
3251                                         E1000_RXCSUM_IPOFL |
3252                                         E1000_RXCSUM_PCSD;
3253                 } else {
3254                         if (adapter->hw.mac.type >= igb_mac_min)
3255                                 rxcsum |= E1000_RXCSUM_IPPCSE;
3256                         else
3257                                 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
3258                         if (adapter->hw.mac.type > e1000_82575)
3259                                 rxcsum |= E1000_RXCSUM_CRCOFL;
3260                 }
3261         } else
3262                 rxcsum &= ~E1000_RXCSUM_TUOFL;
3263
3264         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
3265
3266         if (adapter->rx_num_queues > 1) {
3267                 if (adapter->hw.mac.type >= igb_mac_min)
3268                         igb_initialize_rss_mapping(adapter);
3269                 else
3270                         em_initialize_rss_mapping(adapter);
3271         }
3272
3273         /*
3274          * XXX TEMPORARY WORKAROUND: on some systems with 82573
3275          * long latencies are observed, like Lenovo X60. This
3276          * change eliminates the problem, but since having positive
3277          * values in RDTR is a known source of problems on other
3278          * platforms another solution is being sought.
3279          */
3280         if (hw->mac.type == e1000_82573)
3281                 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
3282
3283         for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3284                 struct rx_ring *rxr = &que->rxr;
3285                 /* Setup the Base and Length of the Rx Descriptor Ring */
3286                 u64 bus_addr = rxr->rx_paddr;
3287 #if 0
3288                 u32 rdt = adapter->rx_num_queues -1;  /* default */
3289 #endif
3290
3291                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3292                     scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
3293                 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
3294                 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
3295                 /* Setup the Head and Tail Descriptor Pointers */
3296                 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
3297                 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
3298         }
3299
3300         /*
3301          * Set PTHRESH for improved jumbo performance
3302          * According to 10.2.5.11 of Intel 82574 Datasheet,
3303          * RXDCTL(1) is written whenever RXDCTL(0) is written.
3304          * Only write to RXDCTL(1) if there is a need for different
3305          * settings.
3306          */
3307
3308         if (((adapter->hw.mac.type == e1000_ich9lan) ||
3309             (adapter->hw.mac.type == e1000_pch2lan) ||
3310             (adapter->hw.mac.type == e1000_ich10lan)) &&
3311             (if_getmtu(ifp) > ETHERMTU)) {
3312                 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
3313                 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
3314         } else if (adapter->hw.mac.type == e1000_82574) {
3315                 for (int i = 0; i < adapter->rx_num_queues; i++) {
3316                         u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3317                         rxdctl |= 0x20; /* PTHRESH */
3318                         rxdctl |= 4 << 8; /* HTHRESH */
3319                         rxdctl |= 4 << 16;/* WTHRESH */
3320                         rxdctl |= 1 << 24; /* Switch to granularity */
3321                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3322                 }
3323         } else if (adapter->hw.mac.type >= igb_mac_min) {
3324                 u32 psize, srrctl = 0;
3325
3326                 if (if_getmtu(ifp) > ETHERMTU) {
3327                         /* Set maximum packet len */
3328                         if (adapter->rx_mbuf_sz <= 4096) {
3329                                 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3330                                 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3331                         } else if (adapter->rx_mbuf_sz > 4096) {
3332                                 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3333                                 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3334                         }
3335                         psize = scctx->isc_max_frame_size;
3336                         /* are we on a vlan? */
3337                         if (ifp->if_vlantrunk != NULL)
3338                                 psize += VLAN_TAG_SIZE;
3339                         E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
3340                 } else {
3341                         srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3342                         rctl |= E1000_RCTL_SZ_2048;
3343                 }
3344
3345                 /*
3346                  * If TX flow control is disabled and there's >1 queue defined,
3347                  * enable DROP.
3348                  *
3349                  * This drops frames rather than hanging the RX MAC for all queues.
3350                  */
3351                 if ((adapter->rx_num_queues > 1) &&
3352                     (adapter->fc == e1000_fc_none ||
3353                      adapter->fc == e1000_fc_rx_pause)) {
3354                         srrctl |= E1000_SRRCTL_DROP_EN;
3355                 }
3356                         /* Setup the Base and Length of the Rx Descriptor Rings */
3357                 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3358                         struct rx_ring *rxr = &que->rxr;
3359                         u64 bus_addr = rxr->rx_paddr;
3360                         u32 rxdctl;
3361
3362 #ifdef notyet
3363                         /* Configure for header split? -- ignore for now */
3364                         rxr->hdr_split = igb_header_split;
3365 #else
3366                         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3367 #endif
3368
3369                         E1000_WRITE_REG(hw, E1000_RDLEN(i),
3370                                         scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3371                         E1000_WRITE_REG(hw, E1000_RDBAH(i),
3372                                         (uint32_t)(bus_addr >> 32));
3373                         E1000_WRITE_REG(hw, E1000_RDBAL(i),
3374                                         (uint32_t)bus_addr);
3375                         E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3376                         /* Enable this Queue */
3377                         rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3378                         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3379                         rxdctl &= 0xFFF00000;
3380                         rxdctl |= IGB_RX_PTHRESH;
3381                         rxdctl |= IGB_RX_HTHRESH << 8;
3382                         rxdctl |= IGB_RX_WTHRESH << 16;
3383                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3384                 }
3385         } else if (adapter->hw.mac.type >= e1000_pch2lan) {
3386                 if (if_getmtu(ifp) > ETHERMTU)
3387                         e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
3388                 else
3389                         e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
3390         }
3391
3392         /* Make sure VLAN Filters are off */
3393         rctl &= ~E1000_RCTL_VFE;
3394
3395         if (adapter->hw.mac.type < igb_mac_min) {
3396                 if (adapter->rx_mbuf_sz == MCLBYTES)
3397                         rctl |= E1000_RCTL_SZ_2048;
3398                 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE)
3399                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3400                 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE)
3401                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3402
3403                 /* ensure we clear use DTYPE of 00 here */
3404                 rctl &= ~0x00000C00;
3405         }
3406
3407         /* Write out the settings */
3408         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3409
3410         return;
3411 }
3412
3413 static void
3414 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3415 {
3416         struct adapter *adapter = iflib_get_softc(ctx);
3417         u32 index, bit;
3418
3419         index = (vtag >> 5) & 0x7F;
3420         bit = vtag & 0x1F;
3421         adapter->shadow_vfta[index] |= (1 << bit);
3422         ++adapter->num_vlans;
3423 }
3424
3425 static void
3426 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3427 {
3428         struct adapter *adapter = iflib_get_softc(ctx);
3429         u32 index, bit;
3430
3431         index = (vtag >> 5) & 0x7F;
3432         bit = vtag & 0x1F;
3433         adapter->shadow_vfta[index] &= ~(1 << bit);
3434         --adapter->num_vlans;
3435 }
3436
3437 static void
3438 em_setup_vlan_hw_support(struct adapter *adapter)
3439 {
3440         struct e1000_hw *hw = &adapter->hw;
3441         u32 reg;
3442
3443         /*
3444          * We get here thru init_locked, meaning
3445          * a soft reset, this has already cleared
3446          * the VFTA and other state, so if there
3447          * have been no vlan's registered do nothing.
3448          */
3449         if (adapter->num_vlans == 0)
3450                 return;
3451
3452         /*
3453          * A soft reset zero's out the VFTA, so
3454          * we need to repopulate it now.
3455          */
3456         for (int i = 0; i < EM_VFTA_SIZE; i++)
3457                 if (adapter->shadow_vfta[i] != 0)
3458                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
3459                             i, adapter->shadow_vfta[i]);
3460
3461         reg = E1000_READ_REG(hw, E1000_CTRL);
3462         reg |= E1000_CTRL_VME;
3463         E1000_WRITE_REG(hw, E1000_CTRL, reg);
3464
3465         /* Enable the Filter Table */
3466         reg = E1000_READ_REG(hw, E1000_RCTL);
3467         reg &= ~E1000_RCTL_CFIEN;
3468         reg |= E1000_RCTL_VFE;
3469         E1000_WRITE_REG(hw, E1000_RCTL, reg);
3470 }
3471
3472 static void
3473 em_if_enable_intr(if_ctx_t ctx)
3474 {
3475         struct adapter *adapter = iflib_get_softc(ctx);
3476         struct e1000_hw *hw = &adapter->hw;
3477         u32 ims_mask = IMS_ENABLE_MASK;
3478
3479         if (hw->mac.type == e1000_82574) {
3480                 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK);
3481                 ims_mask |= adapter->ims;
3482         } else if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min)  {
3483                 u32 mask = (adapter->que_mask | adapter->link_mask);
3484
3485                 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask);
3486                 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask);
3487                 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask);
3488                 ims_mask = E1000_IMS_LSC;
3489         }
3490
3491         E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3492 }
3493
3494 static void
3495 em_if_disable_intr(if_ctx_t ctx)
3496 {
3497         struct adapter *adapter = iflib_get_softc(ctx);
3498         struct e1000_hw *hw = &adapter->hw;
3499
3500         if (adapter->intr_type == IFLIB_INTR_MSIX) {
3501                 if (hw->mac.type >= igb_mac_min)
3502                         E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0);
3503                 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0);
3504         }
3505         E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
3506 }
3507
3508 /*
3509  * Bit of a misnomer, what this really means is
3510  * to enable OS management of the system... aka
3511  * to disable special hardware management features
3512  */
3513 static void
3514 em_init_manageability(struct adapter *adapter)
3515 {
3516         /* A shared code workaround */
3517 #define E1000_82542_MANC2H E1000_MANC2H
3518         if (adapter->has_manage) {
3519                 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3520                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3521
3522                 /* disable hardware interception of ARP */
3523                 manc &= ~(E1000_MANC_ARP_EN);
3524
3525                 /* enable receiving management packets to the host */
3526                 manc |= E1000_MANC_EN_MNG2HOST;
3527 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3528 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3529                 manc2h |= E1000_MNG2HOST_PORT_623;
3530                 manc2h |= E1000_MNG2HOST_PORT_664;
3531                 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3532                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3533         }
3534 }
3535
3536 /*
3537  * Give control back to hardware management
3538  * controller if there is one.
3539  */
3540 static void
3541 em_release_manageability(struct adapter *adapter)
3542 {
3543         if (adapter->has_manage) {
3544                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3545
3546                 /* re-enable hardware interception of ARP */
3547                 manc |= E1000_MANC_ARP_EN;
3548                 manc &= ~E1000_MANC_EN_MNG2HOST;
3549
3550                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3551         }
3552 }
3553
3554 /*
3555  * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3556  * For ASF and Pass Through versions of f/w this means
3557  * that the driver is loaded. For AMT version type f/w
3558  * this means that the network i/f is open.
3559  */
3560 static void
3561 em_get_hw_control(struct adapter *adapter)
3562 {
3563         u32 ctrl_ext, swsm;
3564
3565         if (adapter->vf_ifp)
3566                 return;
3567
3568         if (adapter->hw.mac.type == e1000_82573) {
3569                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3570                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3571                     swsm | E1000_SWSM_DRV_LOAD);
3572                 return;
3573         }
3574         /* else */
3575         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3576         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3577             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3578 }
3579
3580 /*
3581  * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3582  * For ASF and Pass Through versions of f/w this means that
3583  * the driver is no longer loaded. For AMT versions of the
3584  * f/w this means that the network i/f is closed.
3585  */
3586 static void
3587 em_release_hw_control(struct adapter *adapter)
3588 {
3589         u32 ctrl_ext, swsm;
3590
3591         if (!adapter->has_manage)
3592                 return;
3593
3594         if (adapter->hw.mac.type == e1000_82573) {
3595                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3596                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3597                     swsm & ~E1000_SWSM_DRV_LOAD);
3598                 return;
3599         }
3600         /* else */
3601         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3602         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3603             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3604         return;
3605 }
3606
3607 static int
3608 em_is_valid_ether_addr(u8 *addr)
3609 {
3610         char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3611
3612         if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3613                 return (FALSE);
3614         }
3615
3616         return (TRUE);
3617 }
3618
3619 /*
3620 ** Parse the interface capabilities with regard
3621 ** to both system management and wake-on-lan for
3622 ** later use.
3623 */
3624 static void
3625 em_get_wakeup(if_ctx_t ctx)
3626 {
3627         struct adapter *adapter = iflib_get_softc(ctx);
3628         device_t dev = iflib_get_dev(ctx);
3629         u16 eeprom_data = 0, device_id, apme_mask;
3630
3631         adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
3632         apme_mask = EM_EEPROM_APME;
3633
3634         switch (adapter->hw.mac.type) {
3635         case e1000_82542:
3636         case e1000_82543:
3637                 break;
3638         case e1000_82544:
3639                 e1000_read_nvm(&adapter->hw,
3640                     NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3641                 apme_mask = EM_82544_APME;
3642                 break;
3643         case e1000_82546:
3644         case e1000_82546_rev_3:
3645                 if (adapter->hw.bus.func == 1) {
3646                         e1000_read_nvm(&adapter->hw,
3647                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3648                         break;
3649                 } else
3650                         e1000_read_nvm(&adapter->hw,
3651                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3652                 break;
3653         case e1000_82573:
3654         case e1000_82583:
3655                 adapter->has_amt = TRUE;
3656                 /* FALLTHROUGH */
3657         case e1000_82571:
3658         case e1000_82572:
3659         case e1000_80003es2lan:
3660                 if (adapter->hw.bus.func == 1) {
3661                         e1000_read_nvm(&adapter->hw,
3662                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3663                         break;
3664                 } else
3665                         e1000_read_nvm(&adapter->hw,
3666                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3667                 break;
3668         case e1000_ich8lan:
3669         case e1000_ich9lan:
3670         case e1000_ich10lan:
3671         case e1000_pchlan:
3672         case e1000_pch2lan:
3673         case e1000_pch_lpt:
3674         case e1000_pch_spt:
3675         case e1000_82575:       /* listing all igb devices */
3676         case e1000_82576:
3677         case e1000_82580:
3678         case e1000_i350:
3679         case e1000_i354:
3680         case e1000_i210:
3681         case e1000_i211:
3682         case e1000_vfadapt:
3683         case e1000_vfadapt_i350:
3684                 apme_mask = E1000_WUC_APME;
3685                 adapter->has_amt = TRUE;
3686                 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
3687                 break;
3688         default:
3689                 e1000_read_nvm(&adapter->hw,
3690                     NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3691                 break;
3692         }
3693         if (eeprom_data & apme_mask)
3694                 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
3695         /*
3696          * We have the eeprom settings, now apply the special cases
3697          * where the eeprom may be wrong or the board won't support
3698          * wake on lan on a particular port
3699          */
3700         device_id = pci_get_device(dev);
3701         switch (device_id) {
3702         case E1000_DEV_ID_82546GB_PCIE:
3703                 adapter->wol = 0;
3704                 break;
3705         case E1000_DEV_ID_82546EB_FIBER:
3706         case E1000_DEV_ID_82546GB_FIBER:
3707                 /* Wake events only supported on port A for dual fiber
3708                  * regardless of eeprom setting */
3709                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3710                     E1000_STATUS_FUNC_1)
3711                         adapter->wol = 0;
3712                 break;
3713         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
3714                 /* if quad port adapter, disable WoL on all but port A */
3715                 if (global_quad_port_a != 0)
3716                         adapter->wol = 0;
3717                 /* Reset for multiple quad port adapters */
3718                 if (++global_quad_port_a == 4)
3719                         global_quad_port_a = 0;
3720                 break;
3721         case E1000_DEV_ID_82571EB_FIBER:
3722                 /* Wake events only supported on port A for dual fiber
3723                  * regardless of eeprom setting */
3724                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3725                     E1000_STATUS_FUNC_1)
3726                         adapter->wol = 0;
3727                 break;
3728         case E1000_DEV_ID_82571EB_QUAD_COPPER:
3729         case E1000_DEV_ID_82571EB_QUAD_FIBER:
3730         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
3731                 /* if quad port adapter, disable WoL on all but port A */
3732                 if (global_quad_port_a != 0)
3733                         adapter->wol = 0;
3734                 /* Reset for multiple quad port adapters */
3735                 if (++global_quad_port_a == 4)
3736                         global_quad_port_a = 0;
3737                 break;
3738         }
3739         return;
3740 }
3741
3742
3743 /*
3744  * Enable PCI Wake On Lan capability
3745  */
3746 static void
3747 em_enable_wakeup(if_ctx_t ctx)
3748 {
3749         struct adapter *adapter = iflib_get_softc(ctx);
3750         device_t dev = iflib_get_dev(ctx);
3751         if_t ifp = iflib_get_ifp(ctx);
3752         int error = 0;
3753         u32 pmc, ctrl, ctrl_ext, rctl;
3754         u16 status;
3755
3756         if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
3757                 return;
3758
3759         /*
3760          * Determine type of Wakeup: note that wol
3761          * is set with all bits on by default.
3762          */
3763         if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
3764                 adapter->wol &= ~E1000_WUFC_MAG;
3765
3766         if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
3767                 adapter->wol &= ~E1000_WUFC_EX;
3768
3769         if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
3770                 adapter->wol &= ~E1000_WUFC_MC;
3771         else {
3772                 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3773                 rctl |= E1000_RCTL_MPE;
3774                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3775         }
3776
3777         if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC)))
3778                 goto pme;
3779
3780         /* Advertise the wakeup capability */
3781         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
3782         ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
3783         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
3784
3785         /* Keep the laser running on Fiber adapters */
3786         if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3787             adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
3788                 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3789                 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
3790                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext);
3791         }
3792
3793         if ((adapter->hw.mac.type == e1000_ich8lan) ||
3794             (adapter->hw.mac.type == e1000_pchlan) ||
3795             (adapter->hw.mac.type == e1000_ich9lan) ||
3796             (adapter->hw.mac.type == e1000_ich10lan))
3797                 e1000_suspend_workarounds_ich8lan(&adapter->hw);
3798
3799         if ( adapter->hw.mac.type >= e1000_pchlan) {
3800                 error = em_enable_phy_wakeup(adapter);
3801                 if (error)
3802                         goto pme;
3803         } else {
3804                 /* Enable wakeup by the MAC */
3805                 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
3806                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
3807         }
3808
3809         if (adapter->hw.phy.type == e1000_phy_igp_3)
3810                 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
3811
3812 pme:
3813         status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
3814         status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3815         if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
3816                 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3817         pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
3818
3819         return;
3820 }
3821
3822 /*
3823  * WOL in the newer chipset interfaces (pchlan)
3824  * require thing to be copied into the phy
3825  */
3826 static int
3827 em_enable_phy_wakeup(struct adapter *adapter)
3828 {
3829         struct e1000_hw *hw = &adapter->hw;
3830         u32 mreg, ret = 0;
3831         u16 preg;
3832
3833         /* copy MAC RARs to PHY RARs */
3834         e1000_copy_rx_addrs_to_phy_ich8lan(hw);
3835
3836         /* copy MAC MTA to PHY MTA */
3837         for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
3838                 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
3839                 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
3840                 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
3841                     (u16)((mreg >> 16) & 0xFFFF));
3842         }
3843
3844         /* configure PHY Rx Control register */
3845         e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg);
3846         mreg = E1000_READ_REG(hw, E1000_RCTL);
3847         if (mreg & E1000_RCTL_UPE)
3848                 preg |= BM_RCTL_UPE;
3849         if (mreg & E1000_RCTL_MPE)
3850                 preg |= BM_RCTL_MPE;
3851         preg &= ~(BM_RCTL_MO_MASK);
3852         if (mreg & E1000_RCTL_MO_3)
3853                 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
3854                                 << BM_RCTL_MO_SHIFT);
3855         if (mreg & E1000_RCTL_BAM)
3856                 preg |= BM_RCTL_BAM;
3857         if (mreg & E1000_RCTL_PMCF)
3858                 preg |= BM_RCTL_PMCF;
3859         mreg = E1000_READ_REG(hw, E1000_CTRL);
3860         if (mreg & E1000_CTRL_RFCE)
3861                 preg |= BM_RCTL_RFCE;
3862         e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg);
3863
3864         /* enable PHY wakeup in MAC register */
3865         E1000_WRITE_REG(hw, E1000_WUC,
3866             E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
3867         E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol);
3868
3869         /* configure and enable PHY wakeup in PHY registers */
3870         e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol);
3871         e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
3872
3873         /* activate PHY wakeup */
3874         ret = hw->phy.ops.acquire(hw);
3875         if (ret) {
3876                 printf("Could not acquire PHY\n");
3877                 return ret;
3878         }
3879         e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3880                                  (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3881         ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
3882         if (ret) {
3883                 printf("Could not read PHY page 769\n");
3884                 goto out;
3885         }
3886         preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
3887         ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
3888         if (ret)
3889                 printf("Could not set PHY Host Wakeup bit\n");
3890 out:
3891         hw->phy.ops.release(hw);
3892
3893         return ret;
3894 }
3895
3896 static void
3897 em_if_led_func(if_ctx_t ctx, int onoff)
3898 {
3899         struct adapter *adapter = iflib_get_softc(ctx);
3900
3901         if (onoff) {
3902                 e1000_setup_led(&adapter->hw);
3903                 e1000_led_on(&adapter->hw);
3904         } else {
3905                 e1000_led_off(&adapter->hw);
3906                 e1000_cleanup_led(&adapter->hw);
3907         }
3908 }
3909
3910 /*
3911  * Disable the L0S and L1 LINK states
3912  */
3913 static void
3914 em_disable_aspm(struct adapter *adapter)
3915 {
3916         int base, reg;
3917         u16 link_cap,link_ctrl;
3918         device_t dev = adapter->dev;
3919
3920         switch (adapter->hw.mac.type) {
3921         case e1000_82573:
3922         case e1000_82574:
3923         case e1000_82583:
3924                 break;
3925         default:
3926                 return;
3927         }
3928         if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
3929                 return;
3930         reg = base + PCIER_LINK_CAP;
3931         link_cap = pci_read_config(dev, reg, 2);
3932         if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
3933                 return;
3934         reg = base + PCIER_LINK_CTL;
3935         link_ctrl = pci_read_config(dev, reg, 2);
3936         link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
3937         pci_write_config(dev, reg, link_ctrl, 2);
3938         return;
3939 }
3940
3941 /**********************************************************************
3942  *
3943  *  Update the board statistics counters.
3944  *
3945  **********************************************************************/
3946 static void
3947 em_update_stats_counters(struct adapter *adapter)
3948 {
3949
3950         if(adapter->hw.phy.media_type == e1000_media_type_copper ||
3951            (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3952                 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
3953                 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
3954         }
3955         adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
3956         adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
3957         adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
3958         adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
3959
3960         adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
3961         adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
3962         adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
3963         adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
3964         adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
3965         adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
3966         adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
3967         adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
3968         /*
3969          ** For watchdog management we need to know if we have been
3970          ** paused during the last interval, so capture that here.
3971         */
3972         adapter->shared->isc_pause_frames = adapter->stats.xoffrxc;
3973         adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
3974         adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
3975         adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
3976         adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
3977         adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
3978         adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
3979         adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
3980         adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
3981         adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
3982         adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
3983         adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
3984         adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
3985
3986         /* For the 64-bit byte counters the low dword must be read first. */
3987         /* Both registers clear on the read of the high dword */
3988
3989         adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) +
3990             ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32);
3991         adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) +
3992             ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32);
3993
3994         adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
3995         adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
3996         adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
3997         adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
3998         adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
3999
4000         adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
4001         adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
4002
4003         adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
4004         adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
4005         adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
4006         adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
4007         adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
4008         adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
4009         adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
4010         adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
4011         adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
4012         adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
4013
4014         /* Interrupt Counts */
4015
4016         adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC);
4017         adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC);
4018         adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC);
4019         adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC);
4020         adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC);
4021         adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC);
4022         adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC);
4023         adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC);
4024         adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC);
4025
4026         if (adapter->hw.mac.type >= e1000_82543) {
4027                 adapter->stats.algnerrc +=
4028                 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
4029                 adapter->stats.rxerrc +=
4030                 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
4031                 adapter->stats.tncrs +=
4032                 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
4033                 adapter->stats.cexterr +=
4034                 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
4035                 adapter->stats.tsctc +=
4036                 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
4037                 adapter->stats.tsctfc +=
4038                 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
4039         }
4040 }
4041
4042 static uint64_t
4043 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
4044 {
4045         struct adapter *adapter = iflib_get_softc(ctx);
4046         struct ifnet *ifp = iflib_get_ifp(ctx);
4047
4048         switch (cnt) {
4049         case IFCOUNTER_COLLISIONS:
4050                 return (adapter->stats.colc);
4051         case IFCOUNTER_IERRORS:
4052                 return (adapter->dropped_pkts + adapter->stats.rxerrc +
4053                     adapter->stats.crcerrs + adapter->stats.algnerrc +
4054                     adapter->stats.ruc + adapter->stats.roc +
4055                     adapter->stats.mpc + adapter->stats.cexterr);
4056         case IFCOUNTER_OERRORS:
4057                 return (adapter->stats.ecol + adapter->stats.latecol +
4058                     adapter->watchdog_events);
4059         default:
4060                 return (if_get_counter_default(ifp, cnt));
4061         }
4062 }
4063
4064 /* Export a single 32-bit register via a read-only sysctl. */
4065 static int
4066 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
4067 {
4068         struct adapter *adapter;
4069         u_int val;
4070
4071         adapter = oidp->oid_arg1;
4072         val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2);
4073         return (sysctl_handle_int(oidp, &val, 0, req));
4074 }
4075
4076 /*
4077  * Add sysctl variables, one per statistic, to the system.
4078  */
4079 static void
4080 em_add_hw_stats(struct adapter *adapter)
4081 {
4082         device_t dev = iflib_get_dev(adapter->ctx);
4083         struct em_tx_queue *tx_que = adapter->tx_queues;
4084         struct em_rx_queue *rx_que = adapter->rx_queues;
4085
4086         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
4087         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
4088         struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
4089         struct e1000_hw_stats *stats = &adapter->stats;
4090
4091         struct sysctl_oid *stat_node, *queue_node, *int_node;
4092         struct sysctl_oid_list *stat_list, *queue_list, *int_list;
4093
4094 #define QUEUE_NAME_LEN 32
4095         char namebuf[QUEUE_NAME_LEN];
4096
4097         /* Driver Statistics */
4098         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
4099                         CTLFLAG_RD, &adapter->dropped_pkts,
4100                         "Driver dropped packets");
4101         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
4102                         CTLFLAG_RD, &adapter->link_irq,
4103                         "Link MSIX IRQ Handled");
4104         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "mbuf_defrag_fail",
4105                          CTLFLAG_RD, &adapter->mbuf_defrag_failed,
4106                          "Defragmenting mbuf chain failed");
4107         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "tx_dma_fail",
4108                         CTLFLAG_RD, &adapter->no_tx_dma_setup,
4109                         "Driver tx dma failure in xmit");
4110         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
4111                         CTLFLAG_RD, &adapter->rx_overruns,
4112                         "RX overruns");
4113         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
4114                         CTLFLAG_RD, &adapter->watchdog_events,
4115                         "Watchdog timeouts");
4116         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
4117                         CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL,
4118                         em_sysctl_reg_handler, "IU",
4119                         "Device Control Register");
4120         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
4121                         CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL,
4122                         em_sysctl_reg_handler, "IU",
4123                         "Receiver Control Register");
4124         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
4125                         CTLFLAG_RD, &adapter->hw.fc.high_water, 0,
4126                         "Flow Control High Watermark");
4127         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
4128                         CTLFLAG_RD, &adapter->hw.fc.low_water, 0,
4129                         "Flow Control Low Watermark");
4130
4131         for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
4132                 struct tx_ring *txr = &tx_que->txr;
4133                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
4134                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4135                                             CTLFLAG_RD, NULL, "TX Queue Name");
4136                 queue_list = SYSCTL_CHILDREN(queue_node);
4137
4138                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
4139                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4140                                 E1000_TDH(txr->me),
4141                                 em_sysctl_reg_handler, "IU",
4142                                 "Transmit Descriptor Head");
4143                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
4144                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4145                                 E1000_TDT(txr->me),
4146                                 em_sysctl_reg_handler, "IU",
4147                                 "Transmit Descriptor Tail");
4148                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
4149                                 CTLFLAG_RD, &txr->tx_irq,
4150                                 "Queue MSI-X Transmit Interrupts");
4151         }
4152
4153         for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) {
4154                 struct rx_ring *rxr = &rx_que->rxr;
4155                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
4156                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4157                                             CTLFLAG_RD, NULL, "RX Queue Name");
4158                 queue_list = SYSCTL_CHILDREN(queue_node);
4159
4160                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
4161                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4162                                 E1000_RDH(rxr->me),
4163                                 em_sysctl_reg_handler, "IU",
4164                                 "Receive Descriptor Head");
4165                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
4166                                 CTLTYPE_UINT | CTLFLAG_RD, adapter,
4167                                 E1000_RDT(rxr->me),
4168                                 em_sysctl_reg_handler, "IU",
4169                                 "Receive Descriptor Tail");
4170                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
4171                                 CTLFLAG_RD, &rxr->rx_irq,
4172                                 "Queue MSI-X Receive Interrupts");
4173         }
4174
4175         /* MAC stats get their own sub node */
4176
4177         stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
4178                                     CTLFLAG_RD, NULL, "Statistics");
4179         stat_list = SYSCTL_CHILDREN(stat_node);
4180
4181         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
4182                         CTLFLAG_RD, &stats->ecol,
4183                         "Excessive collisions");
4184         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
4185                         CTLFLAG_RD, &stats->scc,
4186                         "Single collisions");
4187         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
4188                         CTLFLAG_RD, &stats->mcc,
4189                         "Multiple collisions");
4190         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
4191                         CTLFLAG_RD, &stats->latecol,
4192                         "Late collisions");
4193         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
4194                         CTLFLAG_RD, &stats->colc,
4195                         "Collision Count");
4196         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
4197                         CTLFLAG_RD, &adapter->stats.symerrs,
4198                         "Symbol Errors");
4199         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
4200                         CTLFLAG_RD, &adapter->stats.sec,
4201                         "Sequence Errors");
4202         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
4203                         CTLFLAG_RD, &adapter->stats.dc,
4204                         "Defer Count");
4205         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
4206                         CTLFLAG_RD, &adapter->stats.mpc,
4207                         "Missed Packets");
4208         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
4209                         CTLFLAG_RD, &adapter->stats.rnbc,
4210                         "Receive No Buffers");
4211         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
4212                         CTLFLAG_RD, &adapter->stats.ruc,
4213                         "Receive Undersize");
4214         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
4215                         CTLFLAG_RD, &adapter->stats.rfc,
4216                         "Fragmented Packets Received ");
4217         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
4218                         CTLFLAG_RD, &adapter->stats.roc,
4219                         "Oversized Packets Received");
4220         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
4221                         CTLFLAG_RD, &adapter->stats.rjc,
4222                         "Recevied Jabber");
4223         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
4224                         CTLFLAG_RD, &adapter->stats.rxerrc,
4225                         "Receive Errors");
4226         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
4227                         CTLFLAG_RD, &adapter->stats.crcerrs,
4228                         "CRC errors");
4229         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
4230                         CTLFLAG_RD, &adapter->stats.algnerrc,
4231                         "Alignment Errors");
4232         /* On 82575 these are collision counts */
4233         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
4234                         CTLFLAG_RD, &adapter->stats.cexterr,
4235                         "Collision/Carrier extension errors");
4236         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
4237                         CTLFLAG_RD, &adapter->stats.xonrxc,
4238                         "XON Received");
4239         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
4240                         CTLFLAG_RD, &adapter->stats.xontxc,
4241                         "XON Transmitted");
4242         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
4243                         CTLFLAG_RD, &adapter->stats.xoffrxc,
4244                         "XOFF Received");
4245         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
4246                         CTLFLAG_RD, &adapter->stats.xofftxc,
4247                         "XOFF Transmitted");
4248
4249         /* Packet Reception Stats */
4250         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
4251                         CTLFLAG_RD, &adapter->stats.tpr,
4252                         "Total Packets Received ");
4253         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
4254                         CTLFLAG_RD, &adapter->stats.gprc,
4255                         "Good Packets Received");
4256         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
4257                         CTLFLAG_RD, &adapter->stats.bprc,
4258                         "Broadcast Packets Received");
4259         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
4260                         CTLFLAG_RD, &adapter->stats.mprc,
4261                         "Multicast Packets Received");
4262         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
4263                         CTLFLAG_RD, &adapter->stats.prc64,
4264                         "64 byte frames received ");
4265         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
4266                         CTLFLAG_RD, &adapter->stats.prc127,
4267                         "65-127 byte frames received");
4268         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
4269                         CTLFLAG_RD, &adapter->stats.prc255,
4270                         "128-255 byte frames received");
4271         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
4272                         CTLFLAG_RD, &adapter->stats.prc511,
4273                         "256-511 byte frames received");
4274         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
4275                         CTLFLAG_RD, &adapter->stats.prc1023,
4276                         "512-1023 byte frames received");
4277         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
4278                         CTLFLAG_RD, &adapter->stats.prc1522,
4279                         "1023-1522 byte frames received");
4280         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
4281                         CTLFLAG_RD, &adapter->stats.gorc,
4282                         "Good Octets Received");
4283
4284         /* Packet Transmission Stats */
4285         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
4286                         CTLFLAG_RD, &adapter->stats.gotc,
4287                         "Good Octets Transmitted");
4288         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
4289                         CTLFLAG_RD, &adapter->stats.tpt,
4290                         "Total Packets Transmitted");
4291         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
4292                         CTLFLAG_RD, &adapter->stats.gptc,
4293                         "Good Packets Transmitted");
4294         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
4295                         CTLFLAG_RD, &adapter->stats.bptc,
4296                         "Broadcast Packets Transmitted");
4297         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
4298                         CTLFLAG_RD, &adapter->stats.mptc,
4299                         "Multicast Packets Transmitted");
4300         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
4301                         CTLFLAG_RD, &adapter->stats.ptc64,
4302                         "64 byte frames transmitted ");
4303         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
4304                         CTLFLAG_RD, &adapter->stats.ptc127,
4305                         "65-127 byte frames transmitted");
4306         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
4307                         CTLFLAG_RD, &adapter->stats.ptc255,
4308                         "128-255 byte frames transmitted");
4309         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
4310                         CTLFLAG_RD, &adapter->stats.ptc511,
4311                         "256-511 byte frames transmitted");
4312         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
4313                         CTLFLAG_RD, &adapter->stats.ptc1023,
4314                         "512-1023 byte frames transmitted");
4315         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
4316                         CTLFLAG_RD, &adapter->stats.ptc1522,
4317                         "1024-1522 byte frames transmitted");
4318         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
4319                         CTLFLAG_RD, &adapter->stats.tsctc,
4320                         "TSO Contexts Transmitted");
4321         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
4322                         CTLFLAG_RD, &adapter->stats.tsctfc,
4323                         "TSO Contexts Failed");
4324
4325
4326         /* Interrupt Stats */
4327
4328         int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
4329                                     CTLFLAG_RD, NULL, "Interrupt Statistics");
4330         int_list = SYSCTL_CHILDREN(int_node);
4331
4332         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
4333                         CTLFLAG_RD, &adapter->stats.iac,
4334                         "Interrupt Assertion Count");
4335
4336         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
4337                         CTLFLAG_RD, &adapter->stats.icrxptc,
4338                         "Interrupt Cause Rx Pkt Timer Expire Count");
4339
4340         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
4341                         CTLFLAG_RD, &adapter->stats.icrxatc,
4342                         "Interrupt Cause Rx Abs Timer Expire Count");
4343
4344         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
4345                         CTLFLAG_RD, &adapter->stats.ictxptc,
4346                         "Interrupt Cause Tx Pkt Timer Expire Count");
4347
4348         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
4349                         CTLFLAG_RD, &adapter->stats.ictxatc,
4350                         "Interrupt Cause Tx Abs Timer Expire Count");
4351
4352         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
4353                         CTLFLAG_RD, &adapter->stats.ictxqec,
4354                         "Interrupt Cause Tx Queue Empty Count");
4355
4356         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
4357                         CTLFLAG_RD, &adapter->stats.ictxqmtc,
4358                         "Interrupt Cause Tx Queue Min Thresh Count");
4359
4360         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
4361                         CTLFLAG_RD, &adapter->stats.icrxdmtc,
4362                         "Interrupt Cause Rx Desc Min Thresh Count");
4363
4364         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
4365                         CTLFLAG_RD, &adapter->stats.icrxoc,
4366                         "Interrupt Cause Receiver Overrun Count");
4367 }
4368
4369 /**********************************************************************
4370  *
4371  *  This routine provides a way to dump out the adapter eeprom,
4372  *  often a useful debug/service tool. This only dumps the first
4373  *  32 words, stuff that matters is in that extent.
4374  *
4375  **********************************************************************/
4376 static int
4377 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4378 {
4379         struct adapter *adapter = (struct adapter *)arg1;
4380         int error;
4381         int result;
4382
4383         result = -1;
4384         error = sysctl_handle_int(oidp, &result, 0, req);
4385
4386         if (error || !req->newptr)
4387                 return (error);
4388
4389         /*
4390          * This value will cause a hex dump of the
4391          * first 32 16-bit words of the EEPROM to
4392          * the screen.
4393          */
4394         if (result == 1)
4395                 em_print_nvm_info(adapter);
4396
4397         return (error);
4398 }
4399
4400 static void
4401 em_print_nvm_info(struct adapter *adapter)
4402 {
4403         u16 eeprom_data;
4404         int i, j, row = 0;
4405
4406         /* Its a bit crude, but it gets the job done */
4407         printf("\nInterface EEPROM Dump:\n");
4408         printf("Offset\n0x0000  ");
4409         for (i = 0, j = 0; i < 32; i++, j++) {
4410                 if (j == 8) { /* Make the offset block */
4411                         j = 0; ++row;
4412                         printf("\n0x00%x0  ",row);
4413                 }
4414                 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
4415                 printf("%04x ", eeprom_data);
4416         }
4417         printf("\n");
4418 }
4419
4420 static int
4421 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4422 {
4423         struct em_int_delay_info *info;
4424         struct adapter *adapter;
4425         u32 regval;
4426         int error, usecs, ticks;
4427
4428         info = (struct em_int_delay_info *) arg1;
4429         usecs = info->value;
4430         error = sysctl_handle_int(oidp, &usecs, 0, req);
4431         if (error != 0 || req->newptr == NULL)
4432                 return (error);
4433         if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4434                 return (EINVAL);
4435         info->value = usecs;
4436         ticks = EM_USECS_TO_TICKS(usecs);
4437         if (info->offset == E1000_ITR)  /* units are 256ns here */
4438                 ticks *= 4;
4439
4440         adapter = info->adapter;
4441
4442         regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
4443         regval = (regval & ~0xffff) | (ticks & 0xffff);
4444         /* Handle a few special cases. */
4445         switch (info->offset) {
4446         case E1000_RDTR:
4447                 break;
4448         case E1000_TIDV:
4449                 if (ticks == 0) {
4450                         adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
4451                         /* Don't write 0 into the TIDV register. */
4452                         regval++;
4453                 } else
4454                         adapter->txd_cmd |= E1000_TXD_CMD_IDE;
4455                 break;
4456         }
4457         E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
4458         return (0);
4459 }
4460
4461 static void
4462 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
4463         const char *description, struct em_int_delay_info *info,
4464         int offset, int value)
4465 {
4466         info->adapter = adapter;
4467         info->offset = offset;
4468         info->value = value;
4469         SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev),
4470             SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4471             OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
4472             info, 0, em_sysctl_int_delay, "I", description);
4473 }
4474
4475 /*
4476  * Set flow control using sysctl:
4477  * Flow control values:
4478  *      0 - off
4479  *      1 - rx pause
4480  *      2 - tx pause
4481  *      3 - full
4482  */
4483 static int
4484 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4485 {
4486         int error;
4487         static int input = 3; /* default is full */
4488         struct adapter  *adapter = (struct adapter *) arg1;
4489
4490         error = sysctl_handle_int(oidp, &input, 0, req);
4491
4492         if ((error) || (req->newptr == NULL))
4493                 return (error);
4494
4495         if (input == adapter->fc) /* no change? */
4496                 return (error);
4497
4498         switch (input) {
4499         case e1000_fc_rx_pause:
4500         case e1000_fc_tx_pause:
4501         case e1000_fc_full:
4502         case e1000_fc_none:
4503                 adapter->hw.fc.requested_mode = input;
4504                 adapter->fc = input;
4505                 break;
4506         default:
4507                 /* Do nothing */
4508                 return (error);
4509         }
4510
4511         adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
4512         e1000_force_mac_fc(&adapter->hw);
4513         return (error);
4514 }
4515
4516 /*
4517  * Manage Energy Efficient Ethernet:
4518  * Control values:
4519  *     0/1 - enabled/disabled
4520  */
4521 static int
4522 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4523 {
4524         struct adapter *adapter = (struct adapter *) arg1;
4525         int error, value;
4526
4527         value = adapter->hw.dev_spec.ich8lan.eee_disable;
4528         error = sysctl_handle_int(oidp, &value, 0, req);
4529         if (error || req->newptr == NULL)
4530                 return (error);
4531         adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4532         em_if_init(adapter->ctx);
4533
4534         return (0);
4535 }
4536
4537 static int
4538 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4539 {
4540         struct adapter *adapter;
4541         int error;
4542         int result;
4543
4544         result = -1;
4545         error = sysctl_handle_int(oidp, &result, 0, req);
4546
4547         if (error || !req->newptr)
4548                 return (error);
4549
4550         if (result == 1) {
4551                 adapter = (struct adapter *) arg1;
4552                 em_print_debug_info(adapter);
4553         }
4554
4555         return (error);
4556 }
4557
4558 static int
4559 em_get_rs(SYSCTL_HANDLER_ARGS)
4560 {
4561         struct adapter *adapter = (struct adapter *) arg1;
4562         int error;
4563         int result;
4564
4565         result = 0;
4566         error = sysctl_handle_int(oidp, &result, 0, req);
4567
4568         if (error || !req->newptr || result != 1)
4569                 return (error);
4570         em_dump_rs(adapter);
4571
4572         return (error);
4573 }
4574
4575 static void
4576 em_if_debug(if_ctx_t ctx)
4577 {
4578         em_dump_rs(iflib_get_softc(ctx));
4579 }
4580
4581 /*
4582  * This routine is meant to be fluid, add whatever is
4583  * needed for debugging a problem.  -jfv
4584  */
4585 static void
4586 em_print_debug_info(struct adapter *adapter)
4587 {
4588         device_t dev = iflib_get_dev(adapter->ctx);
4589         struct ifnet *ifp = iflib_get_ifp(adapter->ctx);
4590         struct tx_ring *txr = &adapter->tx_queues->txr;
4591         struct rx_ring *rxr = &adapter->rx_queues->rxr;
4592
4593         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
4594                 printf("Interface is RUNNING ");
4595         else
4596                 printf("Interface is NOT RUNNING\n");
4597
4598         if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
4599                 printf("and INACTIVE\n");
4600         else
4601                 printf("and ACTIVE\n");
4602
4603         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
4604                 device_printf(dev, "TX Queue %d ------\n", i);
4605                 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
4606                         E1000_READ_REG(&adapter->hw, E1000_TDH(i)),
4607                         E1000_READ_REG(&adapter->hw, E1000_TDT(i)));
4608
4609         }
4610         for (int j=0; j < adapter->rx_num_queues; j++, rxr++) {
4611                 device_printf(dev, "RX Queue %d ------\n", j);
4612                 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
4613                         E1000_READ_REG(&adapter->hw, E1000_RDH(j)),
4614                         E1000_READ_REG(&adapter->hw, E1000_RDT(j)));
4615         }
4616 }
4617
4618 /*
4619  * 82574 only:
4620  * Write a new value to the EEPROM increasing the number of MSIX
4621  * vectors from 3 to 5, for proper multiqueue support.
4622  */
4623 static void
4624 em_enable_vectors_82574(if_ctx_t ctx)
4625 {
4626         struct adapter *adapter = iflib_get_softc(ctx);
4627         struct e1000_hw *hw = &adapter->hw;
4628         device_t dev = iflib_get_dev(ctx);
4629         u16 edata;
4630
4631         e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4632         printf("Current cap: %#06x\n", edata);
4633         if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
4634                 device_printf(dev, "Writing to eeprom: increasing "
4635                     "reported MSIX vectors from 3 to 5...\n");
4636                 edata &= ~(EM_NVM_MSIX_N_MASK);
4637                 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
4638                 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4639                 e1000_update_nvm_checksum(hw);
4640                 device_printf(dev, "Writing to eeprom: done\n");
4641         }
4642 }