sys/dev/e1000/if_em.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /* $FreeBSD$ */
  30 #include "if_em.h"
  31 #include <sys/sbuf.h>
  32 #include <machine/_inttypes.h>
  33
  34 #define em_mac_min e1000_82547
  35 #define igb_mac_min e1000_82575
  36
  37 /*********************************************************************
  38  *  Driver version:
  39  *********************************************************************/
  40 char em_driver_version[] = "7.6.1-k";
  41
  42 /*********************************************************************
  43  *  PCI Device ID Table
  44  *
  45  *  Used by probe to select devices to load on
  46  *  Last field stores an index into e1000_strings
  47  *  Last entry must be all 0s
  48  *
  49  *  { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
  50  *********************************************************************/
  51
  52 static pci_vendor_info_t em_vendor_info_array[] =
  53 {
  54         /* Intel(R) PRO/1000 Network Connection - Legacy em*/
  55         PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"),
  56         PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"),
  57         PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"),
  58         PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"),
  59         PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"),
  60
  61         PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"),
  62         PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"),
  63         PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"),
  64         PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  65         PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"),
  66         PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"),
  67         PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  68
  69         PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"),
  70
  71         PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"),
  72         PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
  73
  74         PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
  75         PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
  76         PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
  77         PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"),
  78
  79         PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"),
  80         PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"),
  81         PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"),
  82         PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"),
  83         PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"),
  84
  85         PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  86         PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
  87         PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
  88         PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  89         PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"),
  90         PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"),
  91         PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"),
  92         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
  93         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"),
  94
  95         PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"),
  96         PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  97         PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"),
  98
  99         /* Intel(R) PRO/1000 Network Connection - em */
 100         PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
 101         PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
 102         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"),
 103         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"),
 104         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"),
 105         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 106         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"),
 107         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"),
 108         PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 109         PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"),
 110         PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
 111         PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
 112         PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"),
 113         PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"),
 114         PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"),
 115         PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"),
 116         PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"),
 117         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"),
 118         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"),
 119         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"),
 120         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"),
 121         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
 122         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 123         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"),
 124         PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"),
 125         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
 126         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"),
 127         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"),
 128         PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"),
 129         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
 130         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 131         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"),
 132         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"),
 133         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"),
 134         PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"),
 135         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
 136         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"),
 137         PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"),
 138         PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"),
 139         PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"),
 140         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"),
 141         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"),
 142         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"),
 143         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"),
 144         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"),
 145         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"),
 146         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"),
 147         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"),
 148         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"),
 149         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"),
 150         PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"),
 151         PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"),
 152         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"),
 153         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"),
 154         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"),
 155         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"),
 156         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"),
 157         PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"),
 158         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"),
 159         PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"),
 160         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"),
 161         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"),
 162         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"),
 163         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"),
 164         PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"),
 165         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"),
 166         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"),
 167         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"),
 168         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"),
 169         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) PRO/1000 Network Connection"),
 170         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) PRO/1000 Network Connection"),
 171         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) PRO/1000 Network Connection"),
 172         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) PRO/1000 Network Connection"),
 173         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) PRO/1000 Network Connection"),
 174         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) PRO/1000 Network Connection"),
 175         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) PRO/1000 Network Connection"),
 176         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) PRO/1000 Network Connection"),
 177         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V10, "Intel(R) PRO/1000 Network Connection"),
 178         /* required last entry */
 179         PVID_END
 180 };
 181
 182 static pci_vendor_info_t igb_vendor_info_array[] =
 183 {
 184         /* Intel(R) PRO/1000 Network Connection - igb */
 185         PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 186         PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 187         PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 188         PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 189         PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 190         PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 191         PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 192         PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 193         PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 194         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 195         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 196         PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 197         PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 198         PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 199         PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 200         PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 201         PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 202         PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 203         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 204         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 205         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 206         PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 207         PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 208         PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 209         PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 210         PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 211         PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 212         PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 213         PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 214         PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 215         PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 216         PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 217         PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 218         PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 219         PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 220         PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 221         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 222         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 223         PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 224         /* required last entry */
 225         PVID_END
 226 };
 227
 228 /*********************************************************************
 229  *  Function prototypes
 230  *********************************************************************/
 231 static void     *em_register(device_t dev);
 232 static void     *igb_register(device_t dev);
 233 static int      em_if_attach_pre(if_ctx_t ctx);
 234 static int      em_if_attach_post(if_ctx_t ctx);
 235 static int      em_if_detach(if_ctx_t ctx);
 236 static int      em_if_shutdown(if_ctx_t ctx);
 237 static int      em_if_suspend(if_ctx_t ctx);
 238 static int      em_if_resume(if_ctx_t ctx);
 239
 240 static int      em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets);
 241 static int      em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets);
 242 static void     em_if_queues_free(if_ctx_t ctx);
 243
 244 static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
 245 static void     em_if_init(if_ctx_t ctx);
 246 static void     em_if_stop(if_ctx_t ctx);
 247 static void     em_if_media_status(if_ctx_t, struct ifmediareq *);
 248 static int      em_if_media_change(if_ctx_t ctx);
 249 static int      em_if_mtu_set(if_ctx_t ctx, uint32_t mtu);
 250 static void     em_if_timer(if_ctx_t ctx, uint16_t qid);
 251 static void     em_if_vlan_register(if_ctx_t ctx, u16 vtag);
 252 static void     em_if_vlan_unregister(if_ctx_t ctx, u16 vtag);
 253 static void     em_if_watchdog_reset(if_ctx_t ctx);
 254 static bool     em_if_needs_restart(if_ctx_t ctx, enum iflib_restart_event event);
 255
 256 static void     em_identify_hardware(if_ctx_t ctx);
 257 static int      em_allocate_pci_resources(if_ctx_t ctx);
 258 static void     em_free_pci_resources(if_ctx_t ctx);
 259 static void     em_reset(if_ctx_t ctx);
 260 static int      em_setup_interface(if_ctx_t ctx);
 261 static int      em_setup_msix(if_ctx_t ctx);
 262
 263 static void     em_initialize_transmit_unit(if_ctx_t ctx);
 264 static void     em_initialize_receive_unit(if_ctx_t ctx);
 265
 266 static void     em_if_intr_enable(if_ctx_t ctx);
 267 static void     em_if_intr_disable(if_ctx_t ctx);
 268 static void     igb_if_intr_enable(if_ctx_t ctx);
 269 static void     igb_if_intr_disable(if_ctx_t ctx);
 270 static int      em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 271 static int      em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
 272 static int      igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 273 static int      igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
 274 static void     em_if_multi_set(if_ctx_t ctx);
 275 static void     em_if_update_admin_status(if_ctx_t ctx);
 276 static void     em_if_debug(if_ctx_t ctx);
 277 static void     em_update_stats_counters(struct adapter *);
 278 static void     em_add_hw_stats(struct adapter *adapter);
 279 static int      em_if_set_promisc(if_ctx_t ctx, int flags);
 280 static void     em_setup_vlan_hw_support(struct adapter *);
 281 static int      em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
 282 static void     em_print_nvm_info(struct adapter *);
 283 static int      em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 284 static int      em_get_rs(SYSCTL_HANDLER_ARGS);
 285 static void     em_print_debug_info(struct adapter *);
 286 static int      em_is_valid_ether_addr(u8 *);
 287 static int      em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
 288 static void     em_add_int_delay_sysctl(struct adapter *, const char *,
 289                     const char *, struct em_int_delay_info *, int, int);
 290 /* Management and WOL Support */
 291 static void     em_init_manageability(struct adapter *);
 292 static void     em_release_manageability(struct adapter *);
 293 static void     em_get_hw_control(struct adapter *);
 294 static void     em_release_hw_control(struct adapter *);
 295 static void     em_get_wakeup(if_ctx_t ctx);
 296 static void     em_enable_wakeup(if_ctx_t ctx);
 297 static int      em_enable_phy_wakeup(struct adapter *);
 298 static void     em_disable_aspm(struct adapter *);
 299
 300 int             em_intr(void *arg);
 301 static void     em_disable_promisc(if_ctx_t ctx);
 302
 303 /* MSI-X handlers */
 304 static int      em_if_msix_intr_assign(if_ctx_t, int);
 305 static int      em_msix_link(void *);
 306 static void     em_handle_link(void *context);
 307
 308 static void     em_enable_vectors_82574(if_ctx_t);
 309
 310 static int      em_set_flowcntl(SYSCTL_HANDLER_ARGS);
 311 static int      em_sysctl_eee(SYSCTL_HANDLER_ARGS);
 312 static void     em_if_led_func(if_ctx_t ctx, int onoff);
 313
 314 static int      em_get_regs(SYSCTL_HANDLER_ARGS);
 315
 316 static void     lem_smartspeed(struct adapter *adapter);
 317 static void     igb_configure_queues(struct adapter *adapter);
 318
 319
 320 /*********************************************************************
 321  *  FreeBSD Device Interface Entry Points
 322  *********************************************************************/
 323 static device_method_t em_methods[] = {
 324         /* Device interface */
 325         DEVMETHOD(device_register, em_register),
 326         DEVMETHOD(device_probe, iflib_device_probe),
 327         DEVMETHOD(device_attach, iflib_device_attach),
 328         DEVMETHOD(device_detach, iflib_device_detach),
 329         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 330         DEVMETHOD(device_suspend, iflib_device_suspend),
 331         DEVMETHOD(device_resume, iflib_device_resume),
 332         DEVMETHOD_END
 333 };
 334
 335 static device_method_t igb_methods[] = {
 336         /* Device interface */
 337         DEVMETHOD(device_register, igb_register),
 338         DEVMETHOD(device_probe, iflib_device_probe),
 339         DEVMETHOD(device_attach, iflib_device_attach),
 340         DEVMETHOD(device_detach, iflib_device_detach),
 341         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 342         DEVMETHOD(device_suspend, iflib_device_suspend),
 343         DEVMETHOD(device_resume, iflib_device_resume),
 344         DEVMETHOD_END
 345 };
 346
 347
 348 static driver_t em_driver = {
 349         "em", em_methods, sizeof(struct adapter),
 350 };
 351
 352 static devclass_t em_devclass;
 353 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
 354
 355 MODULE_DEPEND(em, pci, 1, 1, 1);
 356 MODULE_DEPEND(em, ether, 1, 1, 1);
 357 MODULE_DEPEND(em, iflib, 1, 1, 1);
 358
 359 IFLIB_PNP_INFO(pci, em, em_vendor_info_array);
 360
 361 static driver_t igb_driver = {
 362         "igb", igb_methods, sizeof(struct adapter),
 363 };
 364
 365 static devclass_t igb_devclass;
 366 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
 367
 368 MODULE_DEPEND(igb, pci, 1, 1, 1);
 369 MODULE_DEPEND(igb, ether, 1, 1, 1);
 370 MODULE_DEPEND(igb, iflib, 1, 1, 1);
 371
 372 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array);
 373
 374 static device_method_t em_if_methods[] = {
 375         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 376         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 377         DEVMETHOD(ifdi_detach, em_if_detach),
 378         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 379         DEVMETHOD(ifdi_suspend, em_if_suspend),
 380         DEVMETHOD(ifdi_resume, em_if_resume),
 381         DEVMETHOD(ifdi_init, em_if_init),
 382         DEVMETHOD(ifdi_stop, em_if_stop),
 383         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 384         DEVMETHOD(ifdi_intr_enable, em_if_intr_enable),
 385         DEVMETHOD(ifdi_intr_disable, em_if_intr_disable),
 386         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 387         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 388         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 389         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 390         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 391         DEVMETHOD(ifdi_media_status, em_if_media_status),
 392         DEVMETHOD(ifdi_media_change, em_if_media_change),
 393         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 394         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 395         DEVMETHOD(ifdi_timer, em_if_timer),
 396         DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
 397         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 398         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 399         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 400         DEVMETHOD(ifdi_led_func, em_if_led_func),
 401         DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable),
 402         DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable),
 403         DEVMETHOD(ifdi_debug, em_if_debug),
 404         DEVMETHOD(ifdi_needs_restart, em_if_needs_restart),
 405         DEVMETHOD_END
 406 };
 407
 408 static driver_t em_if_driver = {
 409         "em_if", em_if_methods, sizeof(struct adapter)
 410 };
 411
 412 static device_method_t igb_if_methods[] = {
 413         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 414         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 415         DEVMETHOD(ifdi_detach, em_if_detach),
 416         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 417         DEVMETHOD(ifdi_suspend, em_if_suspend),
 418         DEVMETHOD(ifdi_resume, em_if_resume),
 419         DEVMETHOD(ifdi_init, em_if_init),
 420         DEVMETHOD(ifdi_stop, em_if_stop),
 421         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 422         DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable),
 423         DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable),
 424         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 425         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 426         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 427         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 428         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 429         DEVMETHOD(ifdi_media_status, em_if_media_status),
 430         DEVMETHOD(ifdi_media_change, em_if_media_change),
 431         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 432         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 433         DEVMETHOD(ifdi_timer, em_if_timer),
 434         DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
 435         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 436         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 437         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 438         DEVMETHOD(ifdi_led_func, em_if_led_func),
 439         DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable),
 440         DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable),
 441         DEVMETHOD(ifdi_debug, em_if_debug),
 442         DEVMETHOD(ifdi_needs_restart, em_if_needs_restart),
 443         DEVMETHOD_END
 444 };
 445
 446 static driver_t igb_if_driver = {
 447         "igb_if", igb_if_methods, sizeof(struct adapter)
 448 };
 449
 450 /*********************************************************************
 451  *  Tunable default values.
 452  *********************************************************************/
 453
 454 #define EM_TICKS_TO_USECS(ticks)        ((1024 * (ticks) + 500) / 1000)
 455 #define EM_USECS_TO_TICKS(usecs)        ((1000 * (usecs) + 512) / 1024)
 456
 457 #define MAX_INTS_PER_SEC        8000
 458 #define DEFAULT_ITR             (1000000000/(MAX_INTS_PER_SEC * 256))
 459
 460 /* Allow common code without TSO */
 461 #ifndef CSUM_TSO
 462 #define CSUM_TSO        0
 463 #endif
 464
 465 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
 466     "EM driver parameters");
 467
 468 static int em_disable_crc_stripping = 0;
 469 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
 470     &em_disable_crc_stripping, 0, "Disable CRC Stripping");
 471
 472 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
 473 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
 474 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
 475     0, "Default transmit interrupt delay in usecs");
 476 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
 477     0, "Default receive interrupt delay in usecs");
 478
 479 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
 480 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
 481 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
 482     &em_tx_abs_int_delay_dflt, 0,
 483     "Default transmit interrupt delay limit in usecs");
 484 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
 485     &em_rx_abs_int_delay_dflt, 0,
 486     "Default receive interrupt delay limit in usecs");
 487
 488 static int em_smart_pwr_down = FALSE;
 489 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
 490     0, "Set to true to leave smart power down enabled on newer adapters");
 491
 492 /* Controls whether promiscuous also shows bad packets */
 493 static int em_debug_sbp = TRUE;
 494 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
 495     "Show bad packets in promiscuous mode");
 496
 497 /* How many packets rxeof tries to clean at a time */
 498 static int em_rx_process_limit = 100;
 499 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
 500     &em_rx_process_limit, 0,
 501     "Maximum number of received packets to process "
 502     "at a time, -1 means unlimited");
 503
 504 /* Energy efficient ethernet - default to OFF */
 505 static int eee_setting = 1;
 506 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
 507     "Enable Energy Efficient Ethernet");
 508
 509 /*
 510 ** Tuneable Interrupt rate
 511 */
 512 static int em_max_interrupt_rate = 8000;
 513 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
 514     &em_max_interrupt_rate, 0, "Maximum interrupts per second");
 515
 516
 517
 518 /* Global used in WOL setup with multiport cards */
 519 static int global_quad_port_a = 0;
 520
 521 extern struct if_txrx igb_txrx;
 522 extern struct if_txrx em_txrx;
 523 extern struct if_txrx lem_txrx;
 524
 525 static struct if_shared_ctx em_sctx_init = {
 526         .isc_magic = IFLIB_MAGIC,
 527         .isc_q_align = PAGE_SIZE,
 528         .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 529         .isc_tx_maxsegsize = PAGE_SIZE,
 530         .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 531         .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
 532         .isc_rx_maxsize = MJUM9BYTES,
 533         .isc_rx_nsegments = 1,
 534         .isc_rx_maxsegsize = MJUM9BYTES,
 535         .isc_nfl = 1,
 536         .isc_nrxqs = 1,
 537         .isc_ntxqs = 1,
 538         .isc_admin_intrcnt = 1,
 539         .isc_vendor_info = em_vendor_info_array,
 540         .isc_driver_version = em_driver_version,
 541         .isc_driver = &em_if_driver,
 542         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 543
 544         .isc_nrxd_min = {EM_MIN_RXD},
 545         .isc_ntxd_min = {EM_MIN_TXD},
 546         .isc_nrxd_max = {EM_MAX_RXD},
 547         .isc_ntxd_max = {EM_MAX_TXD},
 548         .isc_nrxd_default = {EM_DEFAULT_RXD},
 549         .isc_ntxd_default = {EM_DEFAULT_TXD},
 550 };
 551
 552 if_shared_ctx_t em_sctx = &em_sctx_init;
 553
 554 static struct if_shared_ctx igb_sctx_init = {
 555         .isc_magic = IFLIB_MAGIC,
 556         .isc_q_align = PAGE_SIZE,
 557         .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 558         .isc_tx_maxsegsize = PAGE_SIZE,
 559         .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 560         .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
 561         .isc_rx_maxsize = MJUM9BYTES,
 562         .isc_rx_nsegments = 1,
 563         .isc_rx_maxsegsize = MJUM9BYTES,
 564         .isc_nfl = 1,
 565         .isc_nrxqs = 1,
 566         .isc_ntxqs = 1,
 567         .isc_admin_intrcnt = 1,
 568         .isc_vendor_info = igb_vendor_info_array,
 569         .isc_driver_version = em_driver_version,
 570         .isc_driver = &igb_if_driver,
 571         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 572
 573         .isc_nrxd_min = {EM_MIN_RXD},
 574         .isc_ntxd_min = {EM_MIN_TXD},
 575         .isc_nrxd_max = {IGB_MAX_RXD},
 576         .isc_ntxd_max = {IGB_MAX_TXD},
 577         .isc_nrxd_default = {EM_DEFAULT_RXD},
 578         .isc_ntxd_default = {EM_DEFAULT_TXD},
 579 };
 580
 581 if_shared_ctx_t igb_sctx = &igb_sctx_init;
 582
 583 /*****************************************************************
 584  *
 585  * Dump Registers
 586  *
 587  ****************************************************************/
 588 #define IGB_REGS_LEN 739
 589
 590 static int em_get_regs(SYSCTL_HANDLER_ARGS)
 591 {
 592         struct adapter *adapter = (struct adapter *)arg1;
 593         struct e1000_hw *hw = &adapter->hw;
 594         struct sbuf *sb;
 595         u32 *regs_buff;
 596         int rc;
 597
 598         regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK);
 599         memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
 600
 601         rc = sysctl_wire_old_buffer(req, 0);
 602         MPASS(rc == 0);
 603         if (rc != 0) {
 604                 free(regs_buff, M_DEVBUF);
 605                 return (rc);
 606         }
 607
 608         sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
 609         MPASS(sb != NULL);
 610         if (sb == NULL) {
 611                 free(regs_buff, M_DEVBUF);
 612                 return (ENOMEM);
 613         }
 614
 615         /* General Registers */
 616         regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
 617         regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
 618         regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
 619         regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
 620         regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
 621         regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
 622         regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
 623         regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
 624         regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
 625         regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
 626         regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
 627         regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
 628         regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
 629         regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
 630         regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
 631         regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
 632         regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
 633         regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
 634         regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
 635         regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
 636         regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
 637         regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
 638
 639         sbuf_printf(sb, "General Registers\n");
 640         sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
 641         sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
 642         sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]);
 643
 644         sbuf_printf(sb, "Interrupt Registers\n");
 645         sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
 646
 647         sbuf_printf(sb, "RX Registers\n");
 648         sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
 649         sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
 650         sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
 651         sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
 652         sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
 653         sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
 654         sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
 655
 656         sbuf_printf(sb, "TX Registers\n");
 657         sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
 658         sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
 659         sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
 660         sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
 661         sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
 662         sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
 663         sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
 664         sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
 665         sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
 666         sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
 667         sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
 668
 669         free(regs_buff, M_DEVBUF);
 670
 671 #ifdef DUMP_DESCS
 672         {
 673                 if_softc_ctx_t scctx = adapter->shared;
 674                 struct rx_ring *rxr = &rx_que->rxr;
 675                 struct tx_ring *txr = &tx_que->txr;
 676                 int ntxd = scctx->isc_ntxd[0];
 677                 int nrxd = scctx->isc_nrxd[0];
 678                 int j;
 679
 680         for (j = 0; j < nrxd; j++) {
 681                 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
 682                 u32 length =  le32toh(rxr->rx_base[j].wb.upper.length);
 683                 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 "  Error:%d  Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
 684         }
 685
 686         for (j = 0; j < min(ntxd, 256); j++) {
 687                 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
 688
 689                 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x  eop: %d DD=%d\n",
 690                             j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
 691                             buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
 692
 693         }
 694         }
 695 #endif
 696
 697         rc = sbuf_finish(sb);
 698         sbuf_delete(sb);
 699         return(rc);
 700 }
 701
 702 static void *
 703 em_register(device_t dev)
 704 {
 705         return (em_sctx);
 706 }
 707
 708 static void *
 709 igb_register(device_t dev)
 710 {
 711         return (igb_sctx);
 712 }
 713
 714 static int
 715 em_set_num_queues(if_ctx_t ctx)
 716 {
 717         struct adapter *adapter = iflib_get_softc(ctx);
 718         int maxqueues;
 719
 720         /* Sanity check based on HW */
 721         switch (adapter->hw.mac.type) {
 722         case e1000_82576:
 723         case e1000_82580:
 724         case e1000_i350:
 725         case e1000_i354:
 726                 maxqueues = 8;
 727                 break;
 728         case e1000_i210:
 729         case e1000_82575:
 730                 maxqueues = 4;
 731                 break;
 732         case e1000_i211:
 733         case e1000_82574:
 734                 maxqueues = 2;
 735                 break;
 736         default:
 737                 maxqueues = 1;
 738                 break;
 739         }
 740
 741         return (maxqueues);
 742 }
 743
 744 #define LEM_CAPS                                                        \
 745     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 746     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER
 747
 748 #define EM_CAPS                                                         \
 749     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 750     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 |  \
 751     IFCAP_LRO | IFCAP_VLAN_HWTSO
 752
 753 #define IGB_CAPS                                                        \
 754     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 755     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 |  \
 756     IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\
 757     IFCAP_TSO6
 758
 759 /*********************************************************************
 760  *  Device initialization routine
 761  *
 762  *  The attach entry point is called when the driver is being loaded.
 763  *  This routine identifies the type of hardware, allocates all resources
 764  *  and initializes the hardware.
 765  *
 766  *  return 0 on success, positive on failure
 767  *********************************************************************/
 768 static int
 769 em_if_attach_pre(if_ctx_t ctx)
 770 {
 771         struct adapter *adapter;
 772         if_softc_ctx_t scctx;
 773         device_t dev;
 774         struct e1000_hw *hw;
 775         int error = 0;
 776
 777         INIT_DEBUGOUT("em_if_attach_pre: begin");
 778         dev = iflib_get_dev(ctx);
 779         adapter = iflib_get_softc(ctx);
 780
 781         adapter->ctx = adapter->osdep.ctx = ctx;
 782         adapter->dev = adapter->osdep.dev = dev;
 783         scctx = adapter->shared = iflib_get_softc_ctx(ctx);
 784         adapter->media = iflib_get_media(ctx);
 785         hw = &adapter->hw;
 786
 787         adapter->tx_process_limit = scctx->isc_ntxd[0];
 788
 789         /* SYSCTL stuff */
 790         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 791             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 792             OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
 793             adapter, 0, em_sysctl_nvm_info, "I", "NVM Information");
 794
 795         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 796             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 797             OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
 798             adapter, 0, em_sysctl_debug_info, "I", "Debug Information");
 799
 800         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 801             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 802             OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
 803             adapter, 0, em_set_flowcntl, "I", "Flow Control");
 804
 805         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 806             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 807             OID_AUTO, "reg_dump",
 808             CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 0,
 809             em_get_regs, "A", "Dump Registers");
 810
 811         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 812             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 813             OID_AUTO, "rs_dump",
 814             CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, adapter, 0,
 815             em_get_rs, "I", "Dump RS indexes");
 816
 817         /* Determine hardware and mac info */
 818         em_identify_hardware(ctx);
 819
 820         scctx->isc_tx_nsegments = EM_MAX_SCATTER;
 821         scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
 822         if (bootverbose)
 823                 device_printf(dev, "attach_pre capping queues at %d\n",
 824                     scctx->isc_ntxqsets_max);
 825
 826         if (adapter->hw.mac.type >= igb_mac_min) {
 827                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
 828                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
 829                 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
 830                 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
 831                 scctx->isc_txrx = &igb_txrx;
 832                 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
 833                 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 834                 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 835                 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS;
 836                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO |
 837                      CSUM_IP6_TCP | CSUM_IP6_UDP;
 838                 if (adapter->hw.mac.type != e1000_82575)
 839                         scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
 840                 /*
 841                 ** Some new devices, as with ixgbe, now may
 842                 ** use a different BAR, so we need to keep
 843                 ** track of which is used.
 844                 */
 845                 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR);
 846                 if (pci_read_config(dev, scctx->isc_msix_bar, 4) == 0)
 847                         scctx->isc_msix_bar += 4;
 848         } else if (adapter->hw.mac.type >= em_mac_min) {
 849                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 850                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
 851                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 852                 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
 853                 scctx->isc_txrx = &em_txrx;
 854                 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
 855                 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 856                 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 857                 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS;
 858                 /*
 859                  * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO}
 860                  * by default as we don't have workarounds for all associated
 861                  * silicon errata.  E. g., with several MACs such as 82573E,
 862                  * TSO only works at Gigabit speed and otherwise can cause the
 863                  * hardware to hang (which also would be next to impossible to
 864                  * work around given that already queued TSO-using descriptors
 865                  * would need to be flushed and vlan(4) reconfigured at runtime
 866                  * in case of a link speed change).  Moreover, MACs like 82579
 867                  * still can hang at Gigabit even with all publicly documented
 868                  * TSO workarounds implemented.  Generally, the penality of
 869                  * these workarounds is rather high and may involve copying
 870                  * mbuf data around so advantages of TSO lapse.  Still, TSO may
 871                  * work for a few MACs of this class - at least when sticking
 872                  * with Gigabit - in which case users may enable TSO manually.
 873                  */
 874                 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
 875                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 876                 /*
 877                  * We support MSI-X with 82574 only, but indicate to iflib(4)
 878                  * that it shall give MSI at least a try with other devices.
 879                  */
 880                 if (adapter->hw.mac.type == e1000_82574) {
 881                         scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR);
 882                 } else {
 883                         scctx->isc_msix_bar = -1;
 884                         scctx->isc_disable_msix = 1;
 885                 }
 886         } else {
 887                 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 888                 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
 889                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 890                 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
 891                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP;
 892                 scctx->isc_txrx = &lem_txrx;
 893                 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS;
 894                 if (adapter->hw.mac.type < e1000_82543)
 895                         scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
 896                 /* INTx only */
 897                 scctx->isc_msix_bar = 0;
 898         }
 899
 900         /* Setup PCI resources */
 901         if (em_allocate_pci_resources(ctx)) {
 902                 device_printf(dev, "Allocation of PCI resources failed\n");
 903                 error = ENXIO;
 904                 goto err_pci;
 905         }
 906
 907         /*
 908         ** For ICH8 and family we need to
 909         ** map the flash memory, and this
 910         ** must happen after the MAC is
 911         ** identified
 912         */
 913         if ((hw->mac.type == e1000_ich8lan) ||
 914             (hw->mac.type == e1000_ich9lan) ||
 915             (hw->mac.type == e1000_ich10lan) ||
 916             (hw->mac.type == e1000_pchlan) ||
 917             (hw->mac.type == e1000_pch2lan) ||
 918             (hw->mac.type == e1000_pch_lpt)) {
 919                 int rid = EM_BAR_TYPE_FLASH;
 920                 adapter->flash = bus_alloc_resource_any(dev,
 921                     SYS_RES_MEMORY, &rid, RF_ACTIVE);
 922                 if (adapter->flash == NULL) {
 923                         device_printf(dev, "Mapping of Flash failed\n");
 924                         error = ENXIO;
 925                         goto err_pci;
 926                 }
 927                 /* This is used in the shared code */
 928                 hw->flash_address = (u8 *)adapter->flash;
 929                 adapter->osdep.flash_bus_space_tag =
 930                     rman_get_bustag(adapter->flash);
 931                 adapter->osdep.flash_bus_space_handle =
 932                     rman_get_bushandle(adapter->flash);
 933         }
 934         /*
 935         ** In the new SPT device flash is not  a
 936         ** separate BAR, rather it is also in BAR0,
 937         ** so use the same tag and an offset handle for the
 938         ** FLASH read/write macros in the shared code.
 939         */
 940         else if (hw->mac.type >= e1000_pch_spt) {
 941                 adapter->osdep.flash_bus_space_tag =
 942                     adapter->osdep.mem_bus_space_tag;
 943                 adapter->osdep.flash_bus_space_handle =
 944                     adapter->osdep.mem_bus_space_handle
 945                     + E1000_FLASH_BASE_ADDR;
 946         }
 947
 948         /* Do Shared Code initialization */
 949         error = e1000_setup_init_funcs(hw, TRUE);
 950         if (error) {
 951                 device_printf(dev, "Setup of Shared code failed, error %d\n",
 952                     error);
 953                 error = ENXIO;
 954                 goto err_pci;
 955         }
 956
 957         em_setup_msix(ctx);
 958         e1000_get_bus_info(hw);
 959
 960         /* Set up some sysctls for the tunable interrupt delays */
 961         em_add_int_delay_sysctl(adapter, "rx_int_delay",
 962             "receive interrupt delay in usecs", &adapter->rx_int_delay,
 963             E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
 964         em_add_int_delay_sysctl(adapter, "tx_int_delay",
 965             "transmit interrupt delay in usecs", &adapter->tx_int_delay,
 966             E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
 967         em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
 968             "receive interrupt delay limit in usecs",
 969             &adapter->rx_abs_int_delay,
 970             E1000_REGISTER(hw, E1000_RADV),
 971             em_rx_abs_int_delay_dflt);
 972         em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
 973             "transmit interrupt delay limit in usecs",
 974             &adapter->tx_abs_int_delay,
 975             E1000_REGISTER(hw, E1000_TADV),
 976             em_tx_abs_int_delay_dflt);
 977         em_add_int_delay_sysctl(adapter, "itr",
 978             "interrupt delay limit in usecs/4",
 979             &adapter->tx_itr,
 980             E1000_REGISTER(hw, E1000_ITR),
 981             DEFAULT_ITR);
 982
 983         hw->mac.autoneg = DO_AUTO_NEG;
 984         hw->phy.autoneg_wait_to_complete = FALSE;
 985         hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 986
 987         if (adapter->hw.mac.type < em_mac_min) {
 988                 e1000_init_script_state_82541(&adapter->hw, TRUE);
 989                 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
 990         }
 991         /* Copper options */
 992         if (hw->phy.media_type == e1000_media_type_copper) {
 993                 hw->phy.mdix = AUTO_ALL_MODES;
 994                 hw->phy.disable_polarity_correction = FALSE;
 995                 hw->phy.ms_type = EM_MASTER_SLAVE;
 996         }
 997
 998         /*
 999          * Set the frame limits assuming
1000          * standard ethernet sized frames.
1001          */
1002         scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
1003             ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
1004
1005         /*
1006          * This controls when hardware reports transmit completion
1007          * status.
1008          */
1009         hw->mac.report_tx_early = 1;
1010
1011         /* Allocate multicast array memory. */
1012         adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN *
1013             MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
1014         if (adapter->mta == NULL) {
1015                 device_printf(dev, "Can not allocate multicast setup array\n");
1016                 error = ENOMEM;
1017                 goto err_late;
1018         }
1019
1020         /* Check SOL/IDER usage */
1021         if (e1000_check_reset_block(hw))
1022                 device_printf(dev, "PHY reset is blocked"
1023                               " due to SOL/IDER session.\n");
1024
1025         /* Sysctl for setting Energy Efficient Ethernet */
1026         hw->dev_spec.ich8lan.eee_disable = eee_setting;
1027         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1028             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1029             OID_AUTO, "eee_control",
1030             CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
1031             adapter, 0, em_sysctl_eee, "I",
1032             "Disable Energy Efficient Ethernet");
1033
1034         /*
1035         ** Start from a known state, this is
1036         ** important in reading the nvm and
1037         ** mac from that.
1038         */
1039         e1000_reset_hw(hw);
1040
1041         /* Make sure we have a good EEPROM before we read from it */
1042         if (e1000_validate_nvm_checksum(hw) < 0) {
1043                 /*
1044                 ** Some PCI-E parts fail the first check due to
1045                 ** the link being in sleep state, call it again,
1046                 ** if it fails a second time its a real issue.
1047                 */
1048                 if (e1000_validate_nvm_checksum(hw) < 0) {
1049                         device_printf(dev,
1050                             "The EEPROM Checksum Is Not Valid\n");
1051                         error = EIO;
1052                         goto err_late;
1053                 }
1054         }
1055
1056         /* Copy the permanent MAC address out of the EEPROM */
1057         if (e1000_read_mac_addr(hw) < 0) {
1058                 device_printf(dev, "EEPROM read error while reading MAC"
1059                               " address\n");
1060                 error = EIO;
1061                 goto err_late;
1062         }
1063
1064         if (!em_is_valid_ether_addr(hw->mac.addr)) {
1065                 device_printf(dev, "Invalid MAC address\n");
1066                 error = EIO;
1067                 goto err_late;
1068         }
1069
1070         /* Disable ULP support */
1071         e1000_disable_ulp_lpt_lp(hw, TRUE);
1072
1073         /*
1074          * Get Wake-on-Lan and Management info for later use
1075          */
1076         em_get_wakeup(ctx);
1077
1078         /* Enable only WOL MAGIC by default */
1079         scctx->isc_capenable &= ~IFCAP_WOL;
1080         if (adapter->wol != 0)
1081                 scctx->isc_capenable |= IFCAP_WOL_MAGIC;
1082
1083         iflib_set_mac(ctx, hw->mac.addr);
1084
1085         return (0);
1086
1087 err_late:
1088         em_release_hw_control(adapter);
1089 err_pci:
1090         em_free_pci_resources(ctx);
1091         free(adapter->mta, M_DEVBUF);
1092
1093         return (error);
1094 }
1095
1096 static int
1097 em_if_attach_post(if_ctx_t ctx)
1098 {
1099         struct adapter *adapter = iflib_get_softc(ctx);
1100         struct e1000_hw *hw = &adapter->hw;
1101         int error = 0;
1102
1103         /* Setup OS specific network interface */
1104         error = em_setup_interface(ctx);
1105         if (error != 0) {
1106                 goto err_late;
1107         }
1108
1109         em_reset(ctx);
1110
1111         /* Initialize statistics */
1112         em_update_stats_counters(adapter);
1113         hw->mac.get_link_status = 1;
1114         em_if_update_admin_status(ctx);
1115         em_add_hw_stats(adapter);
1116
1117         /* Non-AMT based hardware can now take control from firmware */
1118         if (adapter->has_manage && !adapter->has_amt)
1119                 em_get_hw_control(adapter);
1120
1121         INIT_DEBUGOUT("em_if_attach_post: end");
1122
1123         return (error);
1124
1125 err_late:
1126         em_release_hw_control(adapter);
1127         em_free_pci_resources(ctx);
1128         em_if_queues_free(ctx);
1129         free(adapter->mta, M_DEVBUF);
1130
1131         return (error);
1132 }
1133
1134 /*********************************************************************
1135  *  Device removal routine
1136  *
1137  *  The detach entry point is called when the driver is being removed.
1138  *  This routine stops the adapter and deallocates all the resources
1139  *  that were allocated for driver operation.
1140  *
1141  *  return 0 on success, positive on failure
1142  *********************************************************************/
1143 static int
1144 em_if_detach(if_ctx_t ctx)
1145 {
1146         struct adapter  *adapter = iflib_get_softc(ctx);
1147
1148         INIT_DEBUGOUT("em_if_detach: begin");
1149
1150         e1000_phy_hw_reset(&adapter->hw);
1151
1152         em_release_manageability(adapter);
1153         em_release_hw_control(adapter);
1154         em_free_pci_resources(ctx);
1155
1156         return (0);
1157 }
1158
1159 /*********************************************************************
1160  *
1161  *  Shutdown entry point
1162  *
1163  **********************************************************************/
1164
1165 static int
1166 em_if_shutdown(if_ctx_t ctx)
1167 {
1168         return em_if_suspend(ctx);
1169 }
1170
1171 /*
1172  * Suspend/resume device methods.
1173  */
1174 static int
1175 em_if_suspend(if_ctx_t ctx)
1176 {
1177         struct adapter *adapter = iflib_get_softc(ctx);
1178
1179         em_release_manageability(adapter);
1180         em_release_hw_control(adapter);
1181         em_enable_wakeup(ctx);
1182         return (0);
1183 }
1184
1185 static int
1186 em_if_resume(if_ctx_t ctx)
1187 {
1188         struct adapter *adapter = iflib_get_softc(ctx);
1189
1190         if (adapter->hw.mac.type == e1000_pch2lan)
1191                 e1000_resume_workarounds_pchlan(&adapter->hw);
1192         em_if_init(ctx);
1193         em_init_manageability(adapter);
1194
1195         return(0);
1196 }
1197
1198 static int
1199 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1200 {
1201         int max_frame_size;
1202         struct adapter *adapter = iflib_get_softc(ctx);
1203         if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1204
1205          IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1206
1207         switch (adapter->hw.mac.type) {
1208         case e1000_82571:
1209         case e1000_82572:
1210         case e1000_ich9lan:
1211         case e1000_ich10lan:
1212         case e1000_pch2lan:
1213         case e1000_pch_lpt:
1214         case e1000_pch_spt:
1215         case e1000_pch_cnp:
1216         case e1000_82574:
1217         case e1000_82583:
1218         case e1000_80003es2lan:
1219                 /* 9K Jumbo Frame size */
1220                 max_frame_size = 9234;
1221                 break;
1222         case e1000_pchlan:
1223                 max_frame_size = 4096;
1224                 break;
1225         case e1000_82542:
1226         case e1000_ich8lan:
1227                 /* Adapters that do not support jumbo frames */
1228                 max_frame_size = ETHER_MAX_LEN;
1229                 break;
1230         default:
1231                 if (adapter->hw.mac.type >= igb_mac_min)
1232                         max_frame_size = 9234;
1233                 else /* lem */
1234                         max_frame_size = MAX_JUMBO_FRAME_SIZE;
1235         }
1236         if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1237                 return (EINVAL);
1238         }
1239
1240         scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
1241             mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1242         return (0);
1243 }
1244
1245 /*********************************************************************
1246  *  Init entry point
1247  *
1248  *  This routine is used in two ways. It is used by the stack as
1249  *  init entry point in network interface structure. It is also used
1250  *  by the driver as a hw/sw initialization routine to get to a
1251  *  consistent state.
1252  *
1253  **********************************************************************/
1254 static void
1255 em_if_init(if_ctx_t ctx)
1256 {
1257         struct adapter *adapter = iflib_get_softc(ctx);
1258         if_softc_ctx_t scctx = adapter->shared;
1259         struct ifnet *ifp = iflib_get_ifp(ctx);
1260         struct em_tx_queue *tx_que;
1261         int i;
1262
1263         INIT_DEBUGOUT("em_if_init: begin");
1264
1265         /* Get the latest mac address, User can use a LAA */
1266         bcopy(if_getlladdr(ifp), adapter->hw.mac.addr,
1267             ETHER_ADDR_LEN);
1268
1269         /* Put the address into the Receive Address Array */
1270         e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1271
1272         /*
1273          * With the 82571 adapter, RAR[0] may be overwritten
1274          * when the other port is reset, we make a duplicate
1275          * in RAR[14] for that eventuality, this assures
1276          * the interface continues to function.
1277          */
1278         if (adapter->hw.mac.type == e1000_82571) {
1279                 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1280                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1281                     E1000_RAR_ENTRIES - 1);
1282         }
1283
1284
1285         /* Initialize the hardware */
1286         em_reset(ctx);
1287         em_if_update_admin_status(ctx);
1288
1289         for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) {
1290                 struct tx_ring *txr = &tx_que->txr;
1291
1292                 txr->tx_rs_cidx = txr->tx_rs_pidx;
1293
1294                 /* Initialize the last processed descriptor to be the end of
1295                  * the ring, rather than the start, so that we avoid an
1296                  * off-by-one error when calculating how many descriptors are
1297                  * done in the credits_update function.
1298                  */
1299                 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
1300         }
1301
1302         /* Setup VLAN support, basic and offload if available */
1303         E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1304
1305         /* Clear bad data from Rx FIFOs */
1306         if (adapter->hw.mac.type >= igb_mac_min)
1307                 e1000_rx_fifo_flush_82575(&adapter->hw);
1308
1309         /* Configure for OS presence */
1310         em_init_manageability(adapter);
1311
1312         /* Prepare transmit descriptors and buffers */
1313         em_initialize_transmit_unit(ctx);
1314
1315         /* Setup Multicast table */
1316         em_if_multi_set(ctx);
1317
1318         adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx);
1319         em_initialize_receive_unit(ctx);
1320
1321         /* Use real VLAN Filter support? */
1322         if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1323                 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
1324                         /* Use real VLAN Filter support */
1325                         em_setup_vlan_hw_support(adapter);
1326                 else {
1327                         u32 ctrl;
1328                         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1329                         ctrl |= E1000_CTRL_VME;
1330                         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1331                 }
1332         }
1333
1334         /* Don't lose promiscuous settings */
1335         em_if_set_promisc(ctx, IFF_PROMISC);
1336         e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1337
1338         /* MSI-X configuration for 82574 */
1339         if (adapter->hw.mac.type == e1000_82574) {
1340                 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1341
1342                 tmp |= E1000_CTRL_EXT_PBA_CLR;
1343                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1344                 /* Set the IVAR - interrupt vector routing. */
1345                 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars);
1346         } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1347                 igb_configure_queues(adapter);
1348
1349         /* this clears any pending interrupts */
1350         E1000_READ_REG(&adapter->hw, E1000_ICR);
1351         E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC);
1352
1353         /* AMT based hardware can now take control from firmware */
1354         if (adapter->has_manage && adapter->has_amt)
1355                 em_get_hw_control(adapter);
1356
1357         /* Set Energy Efficient Ethernet */
1358         if (adapter->hw.mac.type >= igb_mac_min &&
1359             adapter->hw.phy.media_type == e1000_media_type_copper) {
1360                 if (adapter->hw.mac.type == e1000_i354)
1361                         e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
1362                 else
1363                         e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
1364         }
1365 }
1366
1367 /*********************************************************************
1368  *
1369  *  Fast Legacy/MSI Combined Interrupt Service routine
1370  *
1371  *********************************************************************/
1372 int
1373 em_intr(void *arg)
1374 {
1375         struct adapter *adapter = arg;
1376         if_ctx_t ctx = adapter->ctx;
1377         u32 reg_icr;
1378
1379         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1380
1381         /* Hot eject? */
1382         if (reg_icr == 0xffffffff)
1383                 return FILTER_STRAY;
1384
1385         /* Definitely not our interrupt. */
1386         if (reg_icr == 0x0)
1387                 return FILTER_STRAY;
1388
1389         /*
1390          * Starting with the 82571 chip, bit 31 should be used to
1391          * determine whether the interrupt belongs to us.
1392          */
1393         if (adapter->hw.mac.type >= e1000_82571 &&
1394             (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1395                 return FILTER_STRAY;
1396
1397         /*
1398          * Only MSI-X interrupts have one-shot behavior by taking advantage
1399          * of the EIAC register.  Thus, explicitly disable interrupts.  This
1400          * also works around the MSI message reordering errata on certain
1401          * systems.
1402          */
1403         IFDI_INTR_DISABLE(ctx);
1404
1405         /* Link status change */
1406         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))
1407                 em_handle_link(ctx);
1408
1409         if (reg_icr & E1000_ICR_RXO)
1410                 adapter->rx_overruns++;
1411
1412         return (FILTER_SCHEDULE_THREAD);
1413 }
1414
1415 static int
1416 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1417 {
1418         struct adapter *adapter = iflib_get_softc(ctx);
1419         struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1420
1421         E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims);
1422         return (0);
1423 }
1424
1425 static int
1426 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1427 {
1428         struct adapter *adapter = iflib_get_softc(ctx);
1429         struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1430
1431         E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims);
1432         return (0);
1433 }
1434
1435 static int
1436 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1437 {
1438         struct adapter *adapter = iflib_get_softc(ctx);
1439         struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1440
1441         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims);
1442         return (0);
1443 }
1444
1445 static int
1446 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1447 {
1448         struct adapter *adapter = iflib_get_softc(ctx);
1449         struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1450
1451         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims);
1452         return (0);
1453 }
1454
1455 /*********************************************************************
1456  *
1457  *  MSI-X RX Interrupt Service routine
1458  *
1459  **********************************************************************/
1460 static int
1461 em_msix_que(void *arg)
1462 {
1463         struct em_rx_queue *que = arg;
1464
1465         ++que->irqs;
1466
1467         return (FILTER_SCHEDULE_THREAD);
1468 }
1469
1470 /*********************************************************************
1471  *
1472  *  MSI-X Link Fast Interrupt Service routine
1473  *
1474  **********************************************************************/
1475 static int
1476 em_msix_link(void *arg)
1477 {
1478         struct adapter *adapter = arg;
1479         u32 reg_icr;
1480
1481         ++adapter->link_irq;
1482         MPASS(adapter->hw.back != NULL);
1483         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1484
1485         if (reg_icr & E1000_ICR_RXO)
1486                 adapter->rx_overruns++;
1487
1488         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1489                 em_handle_link(adapter->ctx);
1490         } else if (adapter->hw.mac.type == e1000_82574) {
1491                 /* Only re-arm 82574 if em_if_update_admin_status() won't. */
1492                 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK |
1493                     E1000_IMS_LSC);
1494         }
1495
1496         if (adapter->hw.mac.type == e1000_82574) {
1497                 /*
1498                  * Because we must read the ICR for this interrupt it may
1499                  * clear other causes using autoclear, for this reason we
1500                  * simply create a soft interrupt for all these vectors.
1501                  */
1502                 if (reg_icr)
1503                         E1000_WRITE_REG(&adapter->hw, E1000_ICS, adapter->ims);
1504         } else {
1505                 /* Re-arm unconditionally */
1506                 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC);
1507                 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1508         }
1509
1510         return (FILTER_HANDLED);
1511 }
1512
1513 static void
1514 em_handle_link(void *context)
1515 {
1516         if_ctx_t ctx = context;
1517         struct adapter *adapter = iflib_get_softc(ctx);
1518
1519         adapter->hw.mac.get_link_status = 1;
1520         iflib_admin_intr_deferred(ctx);
1521 }
1522
1523 /*********************************************************************
1524  *
1525  *  Media Ioctl callback
1526  *
1527  *  This routine is called whenever the user queries the status of
1528  *  the interface using ifconfig.
1529  *
1530  **********************************************************************/
1531 static void
1532 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1533 {
1534         struct adapter *adapter = iflib_get_softc(ctx);
1535         u_char fiber_type = IFM_1000_SX;
1536
1537         INIT_DEBUGOUT("em_if_media_status: begin");
1538
1539         iflib_admin_intr_deferred(ctx);
1540
1541         ifmr->ifm_status = IFM_AVALID;
1542         ifmr->ifm_active = IFM_ETHER;
1543
1544         if (!adapter->link_active) {
1545                 return;
1546         }
1547
1548         ifmr->ifm_status |= IFM_ACTIVE;
1549
1550         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
1551             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1552                 if (adapter->hw.mac.type == e1000_82545)
1553                         fiber_type = IFM_1000_LX;
1554                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1555         } else {
1556                 switch (adapter->link_speed) {
1557                 case 10:
1558                         ifmr->ifm_active |= IFM_10_T;
1559                         break;
1560                 case 100:
1561                         ifmr->ifm_active |= IFM_100_TX;
1562                         break;
1563                 case 1000:
1564                         ifmr->ifm_active |= IFM_1000_T;
1565                         break;
1566                 }
1567                 if (adapter->link_duplex == FULL_DUPLEX)
1568                         ifmr->ifm_active |= IFM_FDX;
1569                 else
1570                         ifmr->ifm_active |= IFM_HDX;
1571         }
1572 }
1573
1574 /*********************************************************************
1575  *
1576  *  Media Ioctl callback
1577  *
1578  *  This routine is called when the user changes speed/duplex using
1579  *  media/mediopt option with ifconfig.
1580  *
1581  **********************************************************************/
1582 static int
1583 em_if_media_change(if_ctx_t ctx)
1584 {
1585         struct adapter *adapter = iflib_get_softc(ctx);
1586         struct ifmedia *ifm = iflib_get_media(ctx);
1587
1588         INIT_DEBUGOUT("em_if_media_change: begin");
1589
1590         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1591                 return (EINVAL);
1592
1593         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1594         case IFM_AUTO:
1595                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1596                 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1597                 break;
1598         case IFM_1000_LX:
1599         case IFM_1000_SX:
1600         case IFM_1000_T:
1601                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1602                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1603                 break;
1604         case IFM_100_TX:
1605                 adapter->hw.mac.autoneg = FALSE;
1606                 adapter->hw.phy.autoneg_advertised = 0;
1607                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1608                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1609                 else
1610                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1611                 break;
1612         case IFM_10_T:
1613                 adapter->hw.mac.autoneg = FALSE;
1614                 adapter->hw.phy.autoneg_advertised = 0;
1615                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1616                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1617                 else
1618                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1619                 break;
1620         default:
1621                 device_printf(adapter->dev, "Unsupported media type\n");
1622         }
1623
1624         em_if_init(ctx);
1625
1626         return (0);
1627 }
1628
1629 static int
1630 em_if_set_promisc(if_ctx_t ctx, int flags)
1631 {
1632         struct adapter *adapter = iflib_get_softc(ctx);
1633         u32 reg_rctl;
1634
1635         em_disable_promisc(ctx);
1636
1637         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1638
1639         if (flags & IFF_PROMISC) {
1640                 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1641                 /* Turn this on if you want to see bad packets */
1642                 if (em_debug_sbp)
1643                         reg_rctl |= E1000_RCTL_SBP;
1644                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1645         } else if (flags & IFF_ALLMULTI) {
1646                 reg_rctl |= E1000_RCTL_MPE;
1647                 reg_rctl &= ~E1000_RCTL_UPE;
1648                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1649         }
1650         return (0);
1651 }
1652
1653 static void
1654 em_disable_promisc(if_ctx_t ctx)
1655 {
1656         struct adapter *adapter = iflib_get_softc(ctx);
1657         struct ifnet *ifp = iflib_get_ifp(ctx);
1658         u32 reg_rctl;
1659         int mcnt = 0;
1660
1661         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1662         reg_rctl &= (~E1000_RCTL_UPE);
1663         if (if_getflags(ifp) & IFF_ALLMULTI)
1664                 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1665         else
1666                 mcnt = if_llmaddr_count(ifp);
1667         /* Don't disable if in MAX groups */
1668         if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1669                 reg_rctl &=  (~E1000_RCTL_MPE);
1670         reg_rctl &=  (~E1000_RCTL_SBP);
1671         E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1672 }
1673
1674
1675 static u_int
1676 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1677 {
1678         u8 *mta = arg;
1679
1680         if (cnt == MAX_NUM_MULTICAST_ADDRESSES)
1681                 return (1);
1682
1683         bcopy(LLADDR(sdl), &mta[cnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1684
1685         return (1);
1686 }
1687
1688 /*********************************************************************
1689  *  Multicast Update
1690  *
1691  *  This routine is called whenever multicast address list is updated.
1692  *
1693  **********************************************************************/
1694
1695 static void
1696 em_if_multi_set(if_ctx_t ctx)
1697 {
1698         struct adapter *adapter = iflib_get_softc(ctx);
1699         struct ifnet *ifp = iflib_get_ifp(ctx);
1700         u32 reg_rctl = 0;
1701         u8  *mta; /* Multicast array memory */
1702         int mcnt = 0;
1703
1704         IOCTL_DEBUGOUT("em_set_multi: begin");
1705
1706         mta = adapter->mta;
1707         bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1708
1709         if (adapter->hw.mac.type == e1000_82542 &&
1710             adapter->hw.revision_id == E1000_REVISION_2) {
1711                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1712                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1713                         e1000_pci_clear_mwi(&adapter->hw);
1714                 reg_rctl |= E1000_RCTL_RST;
1715                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1716                 msec_delay(5);
1717         }
1718
1719         mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta);
1720
1721         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1722                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1723                 reg_rctl |= E1000_RCTL_MPE;
1724                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1725         } else
1726                 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
1727
1728         if (adapter->hw.mac.type == e1000_82542 &&
1729             adapter->hw.revision_id == E1000_REVISION_2) {
1730                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1731                 reg_rctl &= ~E1000_RCTL_RST;
1732                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1733                 msec_delay(5);
1734                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1735                         e1000_pci_set_mwi(&adapter->hw);
1736         }
1737 }
1738
1739 /*********************************************************************
1740  *  Timer routine
1741  *
1742  *  This routine schedules em_if_update_admin_status() to check for
1743  *  link status and to gather statistics as well as to perform some
1744  *  controller-specific hardware patting.
1745  *
1746  **********************************************************************/
1747 static void
1748 em_if_timer(if_ctx_t ctx, uint16_t qid)
1749 {
1750
1751         if (qid != 0)
1752                 return;
1753
1754         iflib_admin_intr_deferred(ctx);
1755 }
1756
1757 static void
1758 em_if_update_admin_status(if_ctx_t ctx)
1759 {
1760         struct adapter *adapter = iflib_get_softc(ctx);
1761         struct e1000_hw *hw = &adapter->hw;
1762         device_t dev = iflib_get_dev(ctx);
1763         u32 link_check, thstat, ctrl;
1764
1765         link_check = thstat = ctrl = 0;
1766         /* Get the cached link value or read phy for real */
1767         switch (hw->phy.media_type) {
1768         case e1000_media_type_copper:
1769                 if (hw->mac.get_link_status) {
1770                         if (hw->mac.type == e1000_pch_spt)
1771                                 msec_delay(50);
1772                         /* Do the work to read phy */
1773                         e1000_check_for_link(hw);
1774                         link_check = !hw->mac.get_link_status;
1775                         if (link_check) /* ESB2 fix */
1776                                 e1000_cfg_on_link_up(hw);
1777                 } else {
1778                         link_check = TRUE;
1779                 }
1780                 break;
1781         case e1000_media_type_fiber:
1782                 e1000_check_for_link(hw);
1783                 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1784                             E1000_STATUS_LU);
1785                 break;
1786         case e1000_media_type_internal_serdes:
1787                 e1000_check_for_link(hw);
1788                 link_check = adapter->hw.mac.serdes_has_link;
1789                 break;
1790         /* VF device is type_unknown */
1791         case e1000_media_type_unknown:
1792                 e1000_check_for_link(hw);
1793                 link_check = !hw->mac.get_link_status;
1794                 /* FALLTHROUGH */
1795         default:
1796                 break;
1797         }
1798
1799         /* Check for thermal downshift or shutdown */
1800         if (hw->mac.type == e1000_i350) {
1801                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1802                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1803         }
1804
1805         /* Now check for a transition */
1806         if (link_check && (adapter->link_active == 0)) {
1807                 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
1808                     &adapter->link_duplex);
1809                 /* Check if we must disable SPEED_MODE bit on PCI-E */
1810                 if ((adapter->link_speed != SPEED_1000) &&
1811                     ((hw->mac.type == e1000_82571) ||
1812                     (hw->mac.type == e1000_82572))) {
1813                         int tarc0;
1814                         tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1815                         tarc0 &= ~TARC_SPEED_MODE_BIT;
1816                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1817                 }
1818                 if (bootverbose)
1819                         device_printf(dev, "Link is up %d Mbps %s\n",
1820                             adapter->link_speed,
1821                             ((adapter->link_duplex == FULL_DUPLEX) ?
1822                             "Full Duplex" : "Half Duplex"));
1823                 adapter->link_active = 1;
1824                 adapter->smartspeed = 0;
1825                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) ==
1826                     E1000_CTRL_EXT_LINK_MODE_GMII &&
1827                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1828                         device_printf(dev, "Link: thermal downshift\n");
1829                 /* Delay Link Up for Phy update */
1830                 if (((hw->mac.type == e1000_i210) ||
1831                     (hw->mac.type == e1000_i211)) &&
1832                     (hw->phy.id == I210_I_PHY_ID))
1833                         msec_delay(I210_LINK_DELAY);
1834                 /* Reset if the media type changed. */
1835                 if ((hw->dev_spec._82575.media_changed) &&
1836                         (adapter->hw.mac.type >= igb_mac_min)) {
1837                         hw->dev_spec._82575.media_changed = false;
1838                         adapter->flags |= IGB_MEDIA_RESET;
1839                         em_reset(ctx);
1840                 }
1841                 iflib_link_state_change(ctx, LINK_STATE_UP,
1842                     IF_Mbps(adapter->link_speed));
1843         } else if (!link_check && (adapter->link_active == 1)) {
1844                 adapter->link_speed = 0;
1845                 adapter->link_duplex = 0;
1846                 adapter->link_active = 0;
1847                 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
1848         }
1849         em_update_stats_counters(adapter);
1850
1851         /* Reset LAA into RAR[0] on 82571 */
1852         if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw))
1853                 e1000_rar_set(hw, hw->mac.addr, 0);
1854
1855         if (hw->mac.type < em_mac_min)
1856                 lem_smartspeed(adapter);
1857         else if (hw->mac.type == e1000_82574 &&
1858             adapter->intr_type == IFLIB_INTR_MSIX)
1859                 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK |
1860                     E1000_IMS_LSC);
1861 }
1862
1863 static void
1864 em_if_watchdog_reset(if_ctx_t ctx)
1865 {
1866         struct adapter *adapter = iflib_get_softc(ctx);
1867
1868         /*
1869          * Just count the event; iflib(4) will already trigger a
1870          * sufficient reset of the controller.
1871          */
1872         adapter->watchdog_events++;
1873 }
1874
1875 /*********************************************************************
1876  *
1877  *  This routine disables all traffic on the adapter by issuing a
1878  *  global reset on the MAC.
1879  *
1880  **********************************************************************/
1881 static void
1882 em_if_stop(if_ctx_t ctx)
1883 {
1884         struct adapter *adapter = iflib_get_softc(ctx);
1885
1886         INIT_DEBUGOUT("em_if_stop: begin");
1887
1888         e1000_reset_hw(&adapter->hw);
1889         if (adapter->hw.mac.type >= e1000_82544)
1890                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0);
1891
1892         e1000_led_off(&adapter->hw);
1893         e1000_cleanup_led(&adapter->hw);
1894 }
1895
1896 /*********************************************************************
1897  *
1898  *  Determine hardware revision.
1899  *
1900  **********************************************************************/
1901 static void
1902 em_identify_hardware(if_ctx_t ctx)
1903 {
1904         device_t dev = iflib_get_dev(ctx);
1905         struct adapter *adapter = iflib_get_softc(ctx);
1906
1907         /* Make sure our PCI config space has the necessary stuff set */
1908         adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1909
1910         /* Save off the information about this board */
1911         adapter->hw.vendor_id = pci_get_vendor(dev);
1912         adapter->hw.device_id = pci_get_device(dev);
1913         adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1914         adapter->hw.subsystem_vendor_id =
1915             pci_read_config(dev, PCIR_SUBVEND_0, 2);
1916         adapter->hw.subsystem_device_id =
1917             pci_read_config(dev, PCIR_SUBDEV_0, 2);
1918
1919         /* Do Shared Code Init and Setup */
1920         if (e1000_set_mac_type(&adapter->hw)) {
1921                 device_printf(dev, "Setup init failure\n");
1922                 return;
1923         }
1924 }
1925
1926 static int
1927 em_allocate_pci_resources(if_ctx_t ctx)
1928 {
1929         struct adapter *adapter = iflib_get_softc(ctx);
1930         device_t dev = iflib_get_dev(ctx);
1931         int rid, val;
1932
1933         rid = PCIR_BAR(0);
1934         adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1935             &rid, RF_ACTIVE);
1936         if (adapter->memory == NULL) {
1937                 device_printf(dev, "Unable to allocate bus resource: memory\n");
1938                 return (ENXIO);
1939         }
1940         adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory);
1941         adapter->osdep.mem_bus_space_handle =
1942             rman_get_bushandle(adapter->memory);
1943         adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle;
1944
1945         /* Only older adapters use IO mapping */
1946         if (adapter->hw.mac.type < em_mac_min &&
1947             adapter->hw.mac.type > e1000_82543) {
1948                 /* Figure our where our IO BAR is ? */
1949                 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1950                         val = pci_read_config(dev, rid, 4);
1951                         if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1952                                 break;
1953                         }
1954                         rid += 4;
1955                         /* check for 64bit BAR */
1956                         if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1957                                 rid += 4;
1958                 }
1959                 if (rid >= PCIR_CIS) {
1960                         device_printf(dev, "Unable to locate IO BAR\n");
1961                         return (ENXIO);
1962                 }
1963                 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
1964                     &rid, RF_ACTIVE);
1965                 if (adapter->ioport == NULL) {
1966                         device_printf(dev, "Unable to allocate bus resource: "
1967                             "ioport\n");
1968                         return (ENXIO);
1969                 }
1970                 adapter->hw.io_base = 0;
1971                 adapter->osdep.io_bus_space_tag =
1972                     rman_get_bustag(adapter->ioport);
1973                 adapter->osdep.io_bus_space_handle =
1974                     rman_get_bushandle(adapter->ioport);
1975         }
1976
1977         adapter->hw.back = &adapter->osdep;
1978
1979         return (0);
1980 }
1981
1982 /*********************************************************************
1983  *
1984  *  Set up the MSI-X Interrupt handlers
1985  *
1986  **********************************************************************/
1987 static int
1988 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
1989 {
1990         struct adapter *adapter = iflib_get_softc(ctx);
1991         struct em_rx_queue *rx_que = adapter->rx_queues;
1992         struct em_tx_queue *tx_que = adapter->tx_queues;
1993         int error, rid, i, vector = 0, rx_vectors;
1994         char buf[16];
1995
1996         /* First set up ring resources */
1997         for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) {
1998                 rid = vector + 1;
1999                 snprintf(buf, sizeof(buf), "rxq%d", i);
2000                 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
2001                 if (error) {
2002                         device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
2003                         adapter->rx_num_queues = i + 1;
2004                         goto fail;
2005                 }
2006
2007                 rx_que->msix =  vector;
2008
2009                 /*
2010                  * Set the bit to enable interrupt
2011                  * in E1000_IMS -- bits 20 and 21
2012                  * are for RX0 and RX1, note this has
2013                  * NOTHING to do with the MSI-X vector
2014                  */
2015                 if (adapter->hw.mac.type == e1000_82574) {
2016                         rx_que->eims = 1 << (20 + i);
2017                         adapter->ims |= rx_que->eims;
2018                         adapter->ivars |= (8 | rx_que->msix) << (i * 4);
2019                 } else if (adapter->hw.mac.type == e1000_82575)
2020                         rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
2021                 else
2022                         rx_que->eims = 1 << vector;
2023         }
2024         rx_vectors = vector;
2025
2026         vector = 0;
2027         for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) {
2028                 snprintf(buf, sizeof(buf), "txq%d", i);
2029                 tx_que = &adapter->tx_queues[i];
2030                 iflib_softirq_alloc_generic(ctx,
2031                     &adapter->rx_queues[i % adapter->rx_num_queues].que_irq,
2032                     IFLIB_INTR_TX, tx_que, tx_que->me, buf);
2033
2034                 tx_que->msix = (vector % adapter->rx_num_queues);
2035
2036                 /*
2037                  * Set the bit to enable interrupt
2038                  * in E1000_IMS -- bits 22 and 23
2039                  * are for TX0 and TX1, note this has
2040                  * NOTHING to do with the MSI-X vector
2041                  */
2042                 if (adapter->hw.mac.type == e1000_82574) {
2043                         tx_que->eims = 1 << (22 + i);
2044                         adapter->ims |= tx_que->eims;
2045                         adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
2046                 } else if (adapter->hw.mac.type == e1000_82575) {
2047                         tx_que->eims = E1000_EICR_TX_QUEUE0 << i;
2048                 } else {
2049                         tx_que->eims = 1 << i;
2050                 }
2051         }
2052
2053         /* Link interrupt */
2054         rid = rx_vectors + 1;
2055         error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq");
2056
2057         if (error) {
2058                 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
2059                 goto fail;
2060         }
2061         adapter->linkvec = rx_vectors;
2062         if (adapter->hw.mac.type < igb_mac_min) {
2063                 adapter->ivars |=  (8 | rx_vectors) << 16;
2064                 adapter->ivars |= 0x80000000;
2065         }
2066         return (0);
2067 fail:
2068         iflib_irq_free(ctx, &adapter->irq);
2069         rx_que = adapter->rx_queues;
2070         for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++)
2071                 iflib_irq_free(ctx, &rx_que->que_irq);
2072         return (error);
2073 }
2074
2075 static void
2076 igb_configure_queues(struct adapter *adapter)
2077 {
2078         struct e1000_hw *hw = &adapter->hw;
2079         struct em_rx_queue *rx_que;
2080         struct em_tx_queue *tx_que;
2081         u32 tmp, ivar = 0, newitr = 0;
2082
2083         /* First turn on RSS capability */
2084         if (adapter->hw.mac.type != e1000_82575)
2085                 E1000_WRITE_REG(hw, E1000_GPIE,
2086                     E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
2087                     E1000_GPIE_PBA | E1000_GPIE_NSICR);
2088
2089         /* Turn on MSI-X */
2090         switch (adapter->hw.mac.type) {
2091         case e1000_82580:
2092         case e1000_i350:
2093         case e1000_i354:
2094         case e1000_i210:
2095         case e1000_i211:
2096         case e1000_vfadapt:
2097         case e1000_vfadapt_i350:
2098                 /* RX entries */
2099                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2100                         u32 index = i >> 1;
2101                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2102                         rx_que = &adapter->rx_queues[i];
2103                         if (i & 1) {
2104                                 ivar &= 0xFF00FFFF;
2105                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2106                         } else {
2107                                 ivar &= 0xFFFFFF00;
2108                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2109                         }
2110                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2111                 }
2112                 /* TX entries */
2113                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2114                         u32 index = i >> 1;
2115                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2116                         tx_que = &adapter->tx_queues[i];
2117                         if (i & 1) {
2118                                 ivar &= 0x00FFFFFF;
2119                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2120                         } else {
2121                                 ivar &= 0xFFFF00FF;
2122                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2123                         }
2124                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2125                         adapter->que_mask |= tx_que->eims;
2126                 }
2127
2128                 /* And for the link interrupt */
2129                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2130                 adapter->link_mask = 1 << adapter->linkvec;
2131                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2132                 break;
2133         case e1000_82576:
2134                 /* RX entries */
2135                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2136                         u32 index = i & 0x7; /* Each IVAR has two entries */
2137                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2138                         rx_que = &adapter->rx_queues[i];
2139                         if (i < 8) {
2140                                 ivar &= 0xFFFFFF00;
2141                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2142                         } else {
2143                                 ivar &= 0xFF00FFFF;
2144                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2145                         }
2146                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2147                         adapter->que_mask |= rx_que->eims;
2148                 }
2149                 /* TX entries */
2150                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2151                         u32 index = i & 0x7; /* Each IVAR has two entries */
2152                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2153                         tx_que = &adapter->tx_queues[i];
2154                         if (i < 8) {
2155                                 ivar &= 0xFFFF00FF;
2156                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2157                         } else {
2158                                 ivar &= 0x00FFFFFF;
2159                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2160                         }
2161                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2162                         adapter->que_mask |= tx_que->eims;
2163                 }
2164
2165                 /* And for the link interrupt */
2166                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2167                 adapter->link_mask = 1 << adapter->linkvec;
2168                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2169                 break;
2170
2171         case e1000_82575:
2172                 /* enable MSI-X support*/
2173                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2174                 tmp |= E1000_CTRL_EXT_PBA_CLR;
2175                 /* Auto-Mask interrupts upon ICR read. */
2176                 tmp |= E1000_CTRL_EXT_EIAME;
2177                 tmp |= E1000_CTRL_EXT_IRCA;
2178                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2179
2180                 /* Queues */
2181                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2182                         rx_que = &adapter->rx_queues[i];
2183                         tmp = E1000_EICR_RX_QUEUE0 << i;
2184                         tmp |= E1000_EICR_TX_QUEUE0 << i;
2185                         rx_que->eims = tmp;
2186                         E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2187                             i, rx_que->eims);
2188                         adapter->que_mask |= rx_que->eims;
2189                 }
2190
2191                 /* Link */
2192                 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec),
2193                     E1000_EIMS_OTHER);
2194                 adapter->link_mask |= E1000_EIMS_OTHER;
2195         default:
2196                 break;
2197         }
2198
2199         /* Set the starting interrupt rate */
2200         if (em_max_interrupt_rate > 0)
2201                 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2202
2203         if (hw->mac.type == e1000_82575)
2204                 newitr |= newitr << 16;
2205         else
2206                 newitr |= E1000_EITR_CNT_IGNR;
2207
2208         for (int i = 0; i < adapter->rx_num_queues; i++) {
2209                 rx_que = &adapter->rx_queues[i];
2210                 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2211         }
2212
2213         return;
2214 }
2215
2216 static void
2217 em_free_pci_resources(if_ctx_t ctx)
2218 {
2219         struct adapter *adapter = iflib_get_softc(ctx);
2220         struct em_rx_queue *que = adapter->rx_queues;
2221         device_t dev = iflib_get_dev(ctx);
2222
2223         /* Release all MSI-X queue resources */
2224         if (adapter->intr_type == IFLIB_INTR_MSIX)
2225                 iflib_irq_free(ctx, &adapter->irq);
2226
2227         for (int i = 0; i < adapter->rx_num_queues; i++, que++) {
2228                 iflib_irq_free(ctx, &que->que_irq);
2229         }
2230
2231         if (adapter->memory != NULL) {
2232                 bus_release_resource(dev, SYS_RES_MEMORY,
2233                     rman_get_rid(adapter->memory), adapter->memory);
2234                 adapter->memory = NULL;
2235         }
2236
2237         if (adapter->flash != NULL) {
2238                 bus_release_resource(dev, SYS_RES_MEMORY,
2239                     rman_get_rid(adapter->flash), adapter->flash);
2240                 adapter->flash = NULL;
2241         }
2242
2243         if (adapter->ioport != NULL) {
2244                 bus_release_resource(dev, SYS_RES_IOPORT,
2245                     rman_get_rid(adapter->ioport), adapter->ioport);
2246                 adapter->ioport = NULL;
2247         }
2248 }
2249
2250 /* Set up MSI or MSI-X */
2251 static int
2252 em_setup_msix(if_ctx_t ctx)
2253 {
2254         struct adapter *adapter = iflib_get_softc(ctx);
2255
2256         if (adapter->hw.mac.type == e1000_82574) {
2257                 em_enable_vectors_82574(ctx);
2258         }
2259         return (0);
2260 }
2261
2262 /*********************************************************************
2263  *
2264  *  Workaround for SmartSpeed on 82541 and 82547 controllers
2265  *
2266  **********************************************************************/
2267 static void
2268 lem_smartspeed(struct adapter *adapter)
2269 {
2270         u16 phy_tmp;
2271
2272         if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) ||
2273             adapter->hw.mac.autoneg == 0 ||
2274             (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2275                 return;
2276
2277         if (adapter->smartspeed == 0) {
2278                 /* If Master/Slave config fault is asserted twice,
2279                  * we assume back-to-back */
2280                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2281                 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2282                         return;
2283                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2284                 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2285                         e1000_read_phy_reg(&adapter->hw,
2286                             PHY_1000T_CTRL, &phy_tmp);
2287                         if(phy_tmp & CR_1000T_MS_ENABLE) {
2288                                 phy_tmp &= ~CR_1000T_MS_ENABLE;
2289                                 e1000_write_phy_reg(&adapter->hw,
2290                                     PHY_1000T_CTRL, phy_tmp);
2291                                 adapter->smartspeed++;
2292                                 if(adapter->hw.mac.autoneg &&
2293                                    !e1000_copper_link_autoneg(&adapter->hw) &&
2294                                    !e1000_read_phy_reg(&adapter->hw,
2295                                     PHY_CONTROL, &phy_tmp)) {
2296                                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2297                                                     MII_CR_RESTART_AUTO_NEG);
2298                                         e1000_write_phy_reg(&adapter->hw,
2299                                             PHY_CONTROL, phy_tmp);
2300                                 }
2301                         }
2302                 }
2303                 return;
2304         } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2305                 /* If still no link, perhaps using 2/3 pair cable */
2306                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2307                 phy_tmp |= CR_1000T_MS_ENABLE;
2308                 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2309                 if(adapter->hw.mac.autoneg &&
2310                    !e1000_copper_link_autoneg(&adapter->hw) &&
2311                    !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2312                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2313                                     MII_CR_RESTART_AUTO_NEG);
2314                         e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2315                 }
2316         }
2317         /* Restart process after EM_SMARTSPEED_MAX iterations */
2318         if(adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2319                 adapter->smartspeed = 0;
2320 }
2321
2322 /*********************************************************************
2323  *
2324  *  Initialize the DMA Coalescing feature
2325  *
2326  **********************************************************************/
2327 static void
2328 igb_init_dmac(struct adapter *adapter, u32 pba)
2329 {
2330         device_t        dev = adapter->dev;
2331         struct e1000_hw *hw = &adapter->hw;
2332         u32             dmac, reg = ~E1000_DMACR_DMAC_EN;
2333         u16             hwm;
2334         u16             max_frame_size;
2335
2336         if (hw->mac.type == e1000_i211)
2337                 return;
2338
2339         max_frame_size = adapter->shared->isc_max_frame_size;
2340         if (hw->mac.type > e1000_82580) {
2341
2342                 if (adapter->dmac == 0) { /* Disabling it */
2343                         E1000_WRITE_REG(hw, E1000_DMACR, reg);
2344                         return;
2345                 } else
2346                         device_printf(dev, "DMA Coalescing enabled\n");
2347
2348                 /* Set starting threshold */
2349                 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
2350
2351                 hwm = 64 * pba - max_frame_size / 16;
2352                 if (hwm < 64 * (pba - 6))
2353                         hwm = 64 * (pba - 6);
2354                 reg = E1000_READ_REG(hw, E1000_FCRTC);
2355                 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
2356                 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
2357                     & E1000_FCRTC_RTH_COAL_MASK);
2358                 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
2359
2360
2361                 dmac = pba - max_frame_size / 512;
2362                 if (dmac < pba - 10)
2363                         dmac = pba - 10;
2364                 reg = E1000_READ_REG(hw, E1000_DMACR);
2365                 reg &= ~E1000_DMACR_DMACTHR_MASK;
2366                 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT)
2367                     & E1000_DMACR_DMACTHR_MASK);
2368
2369                 /* transition to L0x or L1 if available..*/
2370                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
2371
2372                 /* Check if status is 2.5Gb backplane connection
2373                 * before configuration of watchdog timer, which is
2374                 * in msec values in 12.8usec intervals
2375                 * watchdog timer= msec values in 32usec intervals
2376                 * for non 2.5Gb connection
2377                 */
2378                 if (hw->mac.type == e1000_i354) {
2379                         int status = E1000_READ_REG(hw, E1000_STATUS);
2380                         if ((status & E1000_STATUS_2P5_SKU) &&
2381                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2382                                 reg |= ((adapter->dmac * 5) >> 6);
2383                         else
2384                                 reg |= (adapter->dmac >> 5);
2385                 } else {
2386                         reg |= (adapter->dmac >> 5);
2387                 }
2388
2389                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2390
2391                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
2392
2393                 /* Set the interval before transition */
2394                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
2395                 if (hw->mac.type == e1000_i350)
2396                         reg |= IGB_DMCTLX_DCFLUSH_DIS;
2397                 /*
2398                 ** in 2.5Gb connection, TTLX unit is 0.4 usec
2399                 ** which is 0x4*2 = 0xA. But delay is still 4 usec
2400                 */
2401                 if (hw->mac.type == e1000_i354) {
2402                         int status = E1000_READ_REG(hw, E1000_STATUS);
2403                         if ((status & E1000_STATUS_2P5_SKU) &&
2404                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2405                                 reg |= 0xA;
2406                         else
2407                                 reg |= 0x4;
2408                 } else {
2409                         reg |= 0x4;
2410                 }
2411
2412                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
2413
2414                 /* free space in tx packet buffer to wake from DMA coal */
2415                 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE -
2416                     (2 * max_frame_size)) >> 6);
2417
2418                 /* make low power state decision controlled by DMA coal */
2419                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2420                 reg &= ~E1000_PCIEMISC_LX_DECISION;
2421                 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
2422
2423         } else if (hw->mac.type == e1000_82580) {
2424                 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2425                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
2426                     reg & ~E1000_PCIEMISC_LX_DECISION);
2427                 E1000_WRITE_REG(hw, E1000_DMACR, 0);
2428         }
2429 }
2430
2431 /*********************************************************************
2432  *
2433  *  Initialize the hardware to a configuration as specified by the
2434  *  adapter structure.
2435  *
2436  **********************************************************************/
2437 static void
2438 em_reset(if_ctx_t ctx)
2439 {
2440         device_t dev = iflib_get_dev(ctx);
2441         struct adapter *adapter = iflib_get_softc(ctx);
2442         struct ifnet *ifp = iflib_get_ifp(ctx);
2443         struct e1000_hw *hw = &adapter->hw;
2444         u16 rx_buffer_size;
2445         u32 pba;
2446
2447         INIT_DEBUGOUT("em_reset: begin");
2448         /* Let the firmware know the OS is in control */
2449         em_get_hw_control(adapter);
2450
2451         /* Set up smart power down as default off on newer adapters. */
2452         if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2453             hw->mac.type == e1000_82572)) {
2454                 u16 phy_tmp = 0;
2455
2456                 /* Speed up time to link by disabling smart power down. */
2457                 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2458                 phy_tmp &= ~IGP02E1000_PM_SPD;
2459                 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2460         }
2461
2462         /*
2463          * Packet Buffer Allocation (PBA)
2464          * Writing PBA sets the receive portion of the buffer
2465          * the remainder is used for the transmit buffer.
2466          */
2467         switch (hw->mac.type) {
2468         /* Total Packet Buffer on these is 48K */
2469         case e1000_82571:
2470         case e1000_82572:
2471         case e1000_80003es2lan:
2472                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2473                 break;
2474         case e1000_82573: /* 82573: Total Packet Buffer is 32K */
2475                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2476                 break;
2477         case e1000_82574:
2478         case e1000_82583:
2479                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2480                 break;
2481         case e1000_ich8lan:
2482                 pba = E1000_PBA_8K;
2483                 break;
2484         case e1000_ich9lan:
2485         case e1000_ich10lan:
2486                 /* Boost Receive side for jumbo frames */
2487                 if (adapter->hw.mac.max_frame_size > 4096)
2488                         pba = E1000_PBA_14K;
2489                 else
2490                         pba = E1000_PBA_10K;
2491                 break;
2492         case e1000_pchlan:
2493         case e1000_pch2lan:
2494         case e1000_pch_lpt:
2495         case e1000_pch_spt:
2496         case e1000_pch_cnp:
2497                 pba = E1000_PBA_26K;
2498                 break;
2499         case e1000_82575:
2500                 pba = E1000_PBA_32K;
2501                 break;
2502         case e1000_82576:
2503         case e1000_vfadapt:
2504                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2505                 pba &= E1000_RXPBS_SIZE_MASK_82576;
2506                 break;
2507         case e1000_82580:
2508         case e1000_i350:
2509         case e1000_i354:
2510         case e1000_vfadapt_i350:
2511                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2512                 pba = e1000_rxpbs_adjust_82580(pba);
2513                 break;
2514         case e1000_i210:
2515         case e1000_i211:
2516                 pba = E1000_PBA_34K;
2517                 break;
2518         default:
2519                 if (adapter->hw.mac.max_frame_size > 8192)
2520                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2521                 else
2522                         pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2523         }
2524
2525         /* Special needs in case of Jumbo frames */
2526         if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) {
2527                 u32 tx_space, min_tx, min_rx;
2528                 pba = E1000_READ_REG(hw, E1000_PBA);
2529                 tx_space = pba >> 16;
2530                 pba &= 0xffff;
2531                 min_tx = (adapter->hw.mac.max_frame_size +
2532                     sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
2533                 min_tx = roundup2(min_tx, 1024);
2534                 min_tx >>= 10;
2535                 min_rx = adapter->hw.mac.max_frame_size;
2536                 min_rx = roundup2(min_rx, 1024);
2537                 min_rx >>= 10;
2538                 if (tx_space < min_tx &&
2539                     ((min_tx - tx_space) < pba)) {
2540                         pba = pba - (min_tx - tx_space);
2541                         /*
2542                          * if short on rx space, rx wins
2543                          * and must trump tx adjustment
2544                          */
2545                         if (pba < min_rx)
2546                                 pba = min_rx;
2547                 }
2548                 E1000_WRITE_REG(hw, E1000_PBA, pba);
2549         }
2550
2551         if (hw->mac.type < igb_mac_min)
2552                 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
2553
2554         INIT_DEBUGOUT1("em_reset: pba=%dK",pba);
2555
2556         /*
2557          * These parameters control the automatic generation (Tx) and
2558          * response (Rx) to Ethernet PAUSE frames.
2559          * - High water mark should allow for at least two frames to be
2560          *   received after sending an XOFF.
2561          * - Low water mark works best when it is very near the high water mark.
2562          *   This allows the receiver to restart by sending XON when it has
2563          *   drained a bit. Here we use an arbitrary value of 1500 which will
2564          *   restart after one full frame is pulled from the buffer. There
2565          *   could be several smaller frames in the buffer and if so they will
2566          *   not trigger the XON until their total number reduces the buffer
2567          *   by 1500.
2568          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2569          */
2570         rx_buffer_size = (pba & 0xffff) << 10;
2571         hw->fc.high_water = rx_buffer_size -
2572             roundup2(adapter->hw.mac.max_frame_size, 1024);
2573         hw->fc.low_water = hw->fc.high_water - 1500;
2574
2575         if (adapter->fc) /* locally set flow control value? */
2576                 hw->fc.requested_mode = adapter->fc;
2577         else
2578                 hw->fc.requested_mode = e1000_fc_full;
2579
2580         if (hw->mac.type == e1000_80003es2lan)
2581                 hw->fc.pause_time = 0xFFFF;
2582         else
2583                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
2584
2585         hw->fc.send_xon = TRUE;
2586
2587         /* Device specific overrides/settings */
2588         switch (hw->mac.type) {
2589         case e1000_pchlan:
2590                 /* Workaround: no TX flow ctrl for PCH */
2591                 hw->fc.requested_mode = e1000_fc_rx_pause;
2592                 hw->fc.pause_time = 0xFFFF; /* override */
2593                 if (if_getmtu(ifp) > ETHERMTU) {
2594                         hw->fc.high_water = 0x3500;
2595                         hw->fc.low_water = 0x1500;
2596                 } else {
2597                         hw->fc.high_water = 0x5000;
2598                         hw->fc.low_water = 0x3000;
2599                 }
2600                 hw->fc.refresh_time = 0x1000;
2601                 break;
2602         case e1000_pch2lan:
2603         case e1000_pch_lpt:
2604         case e1000_pch_spt:
2605         case e1000_pch_cnp:
2606                 hw->fc.high_water = 0x5C20;
2607                 hw->fc.low_water = 0x5048;
2608                 hw->fc.pause_time = 0x0650;
2609                 hw->fc.refresh_time = 0x0400;
2610                 /* Jumbos need adjusted PBA */
2611                 if (if_getmtu(ifp) > ETHERMTU)
2612                         E1000_WRITE_REG(hw, E1000_PBA, 12);
2613                 else
2614                         E1000_WRITE_REG(hw, E1000_PBA, 26);
2615                 break;
2616         case e1000_82575:
2617         case e1000_82576:
2618                 /* 8-byte granularity */
2619                 hw->fc.low_water = hw->fc.high_water - 8;
2620                 break;
2621         case e1000_82580:
2622         case e1000_i350:
2623         case e1000_i354:
2624         case e1000_i210:
2625         case e1000_i211:
2626         case e1000_vfadapt:
2627         case e1000_vfadapt_i350:
2628                 /* 16-byte granularity */
2629                 hw->fc.low_water = hw->fc.high_water - 16;
2630                 break;
2631         case e1000_ich9lan:
2632         case e1000_ich10lan:
2633                 if (if_getmtu(ifp) > ETHERMTU) {
2634                         hw->fc.high_water = 0x2800;
2635                         hw->fc.low_water = hw->fc.high_water - 8;
2636                         break;
2637                 }
2638                 /* FALLTHROUGH */
2639         default:
2640                 if (hw->mac.type == e1000_80003es2lan)
2641                         hw->fc.pause_time = 0xFFFF;
2642                 break;
2643         }
2644
2645         /* Issue a global reset */
2646         e1000_reset_hw(hw);
2647         if (adapter->hw.mac.type >= igb_mac_min) {
2648                 E1000_WRITE_REG(hw, E1000_WUC, 0);
2649         } else {
2650                 E1000_WRITE_REG(hw, E1000_WUFC, 0);
2651                 em_disable_aspm(adapter);
2652         }
2653         if (adapter->flags & IGB_MEDIA_RESET) {
2654                 e1000_setup_init_funcs(hw, TRUE);
2655                 e1000_get_bus_info(hw);
2656                 adapter->flags &= ~IGB_MEDIA_RESET;
2657         }
2658         /* and a re-init */
2659         if (e1000_init_hw(hw) < 0) {
2660                 device_printf(dev, "Hardware Initialization Failed\n");
2661                 return;
2662         }
2663         if (adapter->hw.mac.type >= igb_mac_min)
2664                 igb_init_dmac(adapter, pba);
2665
2666         E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2667         e1000_get_phy_info(hw);
2668         e1000_check_for_link(hw);
2669 }
2670
2671 /*
2672  * Initialise the RSS mapping for NICs that support multiple transmit/
2673  * receive rings.
2674  */
2675
2676 #define RSSKEYLEN 10
2677 static void
2678 em_initialize_rss_mapping(struct adapter *adapter)
2679 {
2680         uint8_t  rss_key[4 * RSSKEYLEN];
2681         uint32_t reta = 0;
2682         struct e1000_hw *hw = &adapter->hw;
2683         int i;
2684
2685         /*
2686          * Configure RSS key
2687          */
2688         arc4rand(rss_key, sizeof(rss_key), 0);
2689         for (i = 0; i < RSSKEYLEN; ++i) {
2690                 uint32_t rssrk = 0;
2691
2692                 rssrk = EM_RSSRK_VAL(rss_key, i);
2693                 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2694         }
2695
2696         /*
2697          * Configure RSS redirect table in following fashion:
2698          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2699          */
2700         for (i = 0; i < sizeof(reta); ++i) {
2701                 uint32_t q;
2702
2703                 q = (i % adapter->rx_num_queues) << 7;
2704                 reta |= q << (8 * i);
2705         }
2706
2707         for (i = 0; i < 32; ++i)
2708                 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2709
2710         E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2711                         E1000_MRQC_RSS_FIELD_IPV4_TCP |
2712                         E1000_MRQC_RSS_FIELD_IPV4 |
2713                         E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2714                         E1000_MRQC_RSS_FIELD_IPV6_EX |
2715                         E1000_MRQC_RSS_FIELD_IPV6);
2716 }
2717
2718 static void
2719 igb_initialize_rss_mapping(struct adapter *adapter)
2720 {
2721         struct e1000_hw *hw = &adapter->hw;
2722         int i;
2723         int queue_id;
2724         u32 reta;
2725         u32 rss_key[10], mrqc, shift = 0;
2726
2727         /* XXX? */
2728         if (adapter->hw.mac.type == e1000_82575)
2729                 shift = 6;
2730
2731         /*
2732          * The redirection table controls which destination
2733          * queue each bucket redirects traffic to.
2734          * Each DWORD represents four queues, with the LSB
2735          * being the first queue in the DWORD.
2736          *
2737          * This just allocates buckets to queues using round-robin
2738          * allocation.
2739          *
2740          * NOTE: It Just Happens to line up with the default
2741          * RSS allocation method.
2742          */
2743
2744         /* Warning FM follows */
2745         reta = 0;
2746         for (i = 0; i < 128; i++) {
2747 #ifdef RSS
2748                 queue_id = rss_get_indirection_to_bucket(i);
2749                 /*
2750                  * If we have more queues than buckets, we'll
2751                  * end up mapping buckets to a subset of the
2752                  * queues.
2753                  *
2754                  * If we have more buckets than queues, we'll
2755                  * end up instead assigning multiple buckets
2756                  * to queues.
2757                  *
2758                  * Both are suboptimal, but we need to handle
2759                  * the case so we don't go out of bounds
2760                  * indexing arrays and such.
2761                  */
2762                 queue_id = queue_id % adapter->rx_num_queues;
2763 #else
2764                 queue_id = (i % adapter->rx_num_queues);
2765 #endif
2766                 /* Adjust if required */
2767                 queue_id = queue_id << shift;
2768
2769                 /*
2770                  * The low 8 bits are for hash value (n+0);
2771                  * The next 8 bits are for hash value (n+1), etc.
2772                  */
2773                 reta = reta >> 8;
2774                 reta = reta | ( ((uint32_t) queue_id) << 24);
2775                 if ((i & 3) == 3) {
2776                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2777                         reta = 0;
2778                 }
2779         }
2780
2781         /* Now fill in hash table */
2782
2783         /*
2784          * MRQC: Multiple Receive Queues Command
2785          * Set queuing to RSS control, number depends on the device.
2786          */
2787         mrqc = E1000_MRQC_ENABLE_RSS_8Q;
2788
2789 #ifdef RSS
2790         /* XXX ew typecasting */
2791         rss_getkey((uint8_t *) &rss_key);
2792 #else
2793         arc4rand(&rss_key, sizeof(rss_key), 0);
2794 #endif
2795         for (i = 0; i < 10; i++)
2796                 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]);
2797
2798         /*
2799          * Configure the RSS fields to hash upon.
2800          */
2801         mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2802             E1000_MRQC_RSS_FIELD_IPV4_TCP);
2803         mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2804             E1000_MRQC_RSS_FIELD_IPV6_TCP);
2805         mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2806             E1000_MRQC_RSS_FIELD_IPV6_UDP);
2807         mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2808             E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2809
2810         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2811 }
2812
2813 /*********************************************************************
2814  *
2815  *  Setup networking device structure and register interface media.
2816  *
2817  **********************************************************************/
2818 static int
2819 em_setup_interface(if_ctx_t ctx)
2820 {
2821         struct ifnet *ifp = iflib_get_ifp(ctx);
2822         struct adapter *adapter = iflib_get_softc(ctx);
2823         if_softc_ctx_t scctx = adapter->shared;
2824
2825         INIT_DEBUGOUT("em_setup_interface: begin");
2826
2827         /* Single Queue */
2828         if (adapter->tx_num_queues == 1) {
2829                 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
2830                 if_setsendqready(ifp);
2831         }
2832
2833         /*
2834          * Specify the media types supported by this adapter and register
2835          * callbacks to update media and link information
2836          */
2837         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
2838             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
2839                 u_char fiber_type = IFM_1000_SX;        /* default type */
2840
2841                 if (adapter->hw.mac.type == e1000_82545)
2842                         fiber_type = IFM_1000_LX;
2843                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
2844                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2845         } else {
2846                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2847                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2848                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2849                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2850                 if (adapter->hw.phy.type != e1000_phy_ife) {
2851                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2852                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2853                 }
2854         }
2855         ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2856         ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO);
2857         return (0);
2858 }
2859
2860 static int
2861 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
2862 {
2863         struct adapter *adapter = iflib_get_softc(ctx);
2864         if_softc_ctx_t scctx = adapter->shared;
2865         int error = E1000_SUCCESS;
2866         struct em_tx_queue *que;
2867         int i, j;
2868
2869         MPASS(adapter->tx_num_queues > 0);
2870         MPASS(adapter->tx_num_queues == ntxqsets);
2871
2872         /* First allocate the top level queue structs */
2873         if (!(adapter->tx_queues =
2874             (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
2875             adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2876                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2877                 return(ENOMEM);
2878         }
2879
2880         for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) {
2881                 /* Set up some basics */
2882
2883                 struct tx_ring *txr = &que->txr;
2884                 txr->adapter = que->adapter = adapter;
2885                 que->me = txr->me =  i;
2886
2887                 /* Allocate report status array */
2888                 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2889                         device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n");
2890                         error = ENOMEM;
2891                         goto fail;
2892                 }
2893                 for (j = 0; j < scctx->isc_ntxd[0]; j++)
2894                         txr->tx_rsq[j] = QIDX_INVALID;
2895                 /* get the virtual and physical address of the hardware queues */
2896                 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
2897                 txr->tx_paddr = paddrs[i*ntxqs];
2898         }
2899
2900         if (bootverbose)
2901                 device_printf(iflib_get_dev(ctx),
2902                     "allocated for %d tx_queues\n", adapter->tx_num_queues);
2903         return (0);
2904 fail:
2905         em_if_queues_free(ctx);
2906         return (error);
2907 }
2908
2909 static int
2910 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
2911 {
2912         struct adapter *adapter = iflib_get_softc(ctx);
2913         int error = E1000_SUCCESS;
2914         struct em_rx_queue *que;
2915         int i;
2916
2917         MPASS(adapter->rx_num_queues > 0);
2918         MPASS(adapter->rx_num_queues == nrxqsets);
2919
2920         /* First allocate the top level queue structs */
2921         if (!(adapter->rx_queues =
2922             (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
2923             adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2924                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2925                 error = ENOMEM;
2926                 goto fail;
2927         }
2928
2929         for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) {
2930                 /* Set up some basics */
2931                 struct rx_ring *rxr = &que->rxr;
2932                 rxr->adapter = que->adapter = adapter;
2933                 rxr->que = que;
2934                 que->me = rxr->me =  i;
2935
2936                 /* get the virtual and physical address of the hardware queues */
2937                 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
2938                 rxr->rx_paddr = paddrs[i*nrxqs];
2939         }
2940
2941         if (bootverbose)
2942                 device_printf(iflib_get_dev(ctx),
2943                     "allocated for %d rx_queues\n", adapter->rx_num_queues);
2944
2945         return (0);
2946 fail:
2947         em_if_queues_free(ctx);
2948         return (error);
2949 }
2950
2951 static void
2952 em_if_queues_free(if_ctx_t ctx)
2953 {
2954         struct adapter *adapter = iflib_get_softc(ctx);
2955         struct em_tx_queue *tx_que = adapter->tx_queues;
2956         struct em_rx_queue *rx_que = adapter->rx_queues;
2957
2958         if (tx_que != NULL) {
2959                 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
2960                         struct tx_ring *txr = &tx_que->txr;
2961                         if (txr->tx_rsq == NULL)
2962                                 break;
2963
2964                         free(txr->tx_rsq, M_DEVBUF);
2965                         txr->tx_rsq = NULL;
2966                 }
2967                 free(adapter->tx_queues, M_DEVBUF);
2968                 adapter->tx_queues = NULL;
2969         }
2970
2971         if (rx_que != NULL) {
2972                 free(adapter->rx_queues, M_DEVBUF);
2973                 adapter->rx_queues = NULL;
2974         }
2975
2976         em_release_hw_control(adapter);
2977
2978         if (adapter->mta != NULL) {
2979                 free(adapter->mta, M_DEVBUF);
2980         }
2981 }
2982
2983 /*********************************************************************
2984  *
2985  *  Enable transmit unit.
2986  *
2987  **********************************************************************/
2988 static void
2989 em_initialize_transmit_unit(if_ctx_t ctx)
2990 {
2991         struct adapter *adapter = iflib_get_softc(ctx);
2992         if_softc_ctx_t scctx = adapter->shared;
2993         struct em_tx_queue *que;
2994         struct tx_ring  *txr;
2995         struct e1000_hw *hw = &adapter->hw;
2996         u32 tctl, txdctl = 0, tarc, tipg = 0;
2997
2998         INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
2999
3000         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
3001                 u64 bus_addr;
3002                 caddr_t offp, endp;
3003
3004                 que = &adapter->tx_queues[i];
3005                 txr = &que->txr;
3006                 bus_addr = txr->tx_paddr;
3007
3008                 /* Clear checksum offload context. */
3009                 offp = (caddr_t)&txr->csum_flags;
3010                 endp = (caddr_t)(txr + 1);
3011                 bzero(offp, endp - offp);
3012
3013                 /* Base and Len of TX Ring */
3014                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
3015                     scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
3016                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
3017                     (u32)(bus_addr >> 32));
3018                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
3019                     (u32)bus_addr);
3020                 /* Init the HEAD/TAIL indices */
3021                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
3022                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
3023
3024                 HW_DEBUGOUT2("Base = %x, Length = %x\n",
3025                     E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)),
3026                     E1000_READ_REG(&adapter->hw, E1000_TDLEN(i)));
3027
3028                 txdctl = 0; /* clear txdctl */
3029                 txdctl |= 0x1f; /* PTHRESH */
3030                 txdctl |= 1 << 8; /* HTHRESH */
3031                 txdctl |= 1 << 16;/* WTHRESH */
3032                 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
3033                 txdctl |= E1000_TXDCTL_GRAN;
3034                 txdctl |= 1 << 25; /* LWTHRESH */
3035
3036                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
3037         }
3038
3039         /* Set the default values for the Tx Inter Packet Gap timer */
3040         switch (adapter->hw.mac.type) {
3041         case e1000_80003es2lan:
3042                 tipg = DEFAULT_82543_TIPG_IPGR1;
3043                 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
3044                     E1000_TIPG_IPGR2_SHIFT;
3045                 break;
3046         case e1000_82542:
3047                 tipg = DEFAULT_82542_TIPG_IPGT;
3048                 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3049                 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3050                 break;
3051         default:
3052                 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
3053                     (adapter->hw.phy.media_type ==
3054                     e1000_media_type_internal_serdes))
3055                         tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
3056                 else
3057                         tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
3058                 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3059                 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3060         }
3061
3062         E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
3063         E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value);
3064
3065         if(adapter->hw.mac.type >= e1000_82540)
3066                 E1000_WRITE_REG(&adapter->hw, E1000_TADV,
3067                     adapter->tx_abs_int_delay.value);
3068
3069         if ((adapter->hw.mac.type == e1000_82571) ||
3070             (adapter->hw.mac.type == e1000_82572)) {
3071                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3072                 tarc |= TARC_SPEED_MODE_BIT;
3073                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3074         } else if (adapter->hw.mac.type == e1000_80003es2lan) {
3075                 /* errata: program both queues to unweighted RR */
3076                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3077                 tarc |= 1;
3078                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3079                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
3080                 tarc |= 1;
3081                 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
3082         } else if (adapter->hw.mac.type == e1000_82574) {
3083                 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
3084                 tarc |= TARC_ERRATA_BIT;
3085                 if ( adapter->tx_num_queues > 1) {
3086                         tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
3087                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3088                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
3089                 } else
3090                         E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
3091         }
3092
3093         if (adapter->tx_int_delay.value > 0)
3094                 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3095
3096         /* Program the Transmit Control Register */
3097         tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
3098         tctl &= ~E1000_TCTL_CT;
3099         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
3100                    (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
3101
3102         if (adapter->hw.mac.type >= e1000_82571)
3103                 tctl |= E1000_TCTL_MULR;
3104
3105         /* This write will effectively turn on the transmit unit. */
3106         E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
3107
3108         /* SPT and KBL errata workarounds */
3109         if (hw->mac.type == e1000_pch_spt) {
3110                 u32 reg;
3111                 reg = E1000_READ_REG(hw, E1000_IOSFPC);
3112                 reg |= E1000_RCTL_RDMTS_HEX;
3113                 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
3114                 /* i218-i219 Specification Update 1.5.4.5 */
3115                 reg = E1000_READ_REG(hw, E1000_TARC(0));
3116                 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3117                 reg |= E1000_TARC0_CB_MULTIQ_2_REQ;
3118                 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3119         }
3120 }
3121
3122 /*********************************************************************
3123  *
3124  *  Enable receive unit.
3125  *
3126  **********************************************************************/
3127
3128 static void
3129 em_initialize_receive_unit(if_ctx_t ctx)
3130 {
3131         struct adapter *adapter = iflib_get_softc(ctx);
3132         if_softc_ctx_t scctx = adapter->shared;
3133         struct ifnet *ifp = iflib_get_ifp(ctx);
3134         struct e1000_hw *hw = &adapter->hw;
3135         struct em_rx_queue *que;
3136         int i;
3137         u32 rctl, rxcsum, rfctl;
3138
3139         INIT_DEBUGOUT("em_initialize_receive_units: begin");
3140
3141         /*
3142          * Make sure receives are disabled while setting
3143          * up the descriptor ring
3144          */
3145         rctl = E1000_READ_REG(hw, E1000_RCTL);
3146         /* Do not disable if ever enabled on this hardware */
3147         if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
3148                 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3149
3150         /* Setup the Receive Control Register */
3151         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3152         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3153             E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3154             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3155
3156         /* Do not store bad packets */
3157         rctl &= ~E1000_RCTL_SBP;
3158
3159         /* Enable Long Packet receive */
3160         if (if_getmtu(ifp) > ETHERMTU)
3161                 rctl |= E1000_RCTL_LPE;
3162         else
3163                 rctl &= ~E1000_RCTL_LPE;
3164
3165         /* Strip the CRC */
3166         if (!em_disable_crc_stripping)
3167                 rctl |= E1000_RCTL_SECRC;
3168
3169         if (adapter->hw.mac.type >= e1000_82540) {
3170                 E1000_WRITE_REG(&adapter->hw, E1000_RADV,
3171                             adapter->rx_abs_int_delay.value);
3172
3173                 /*
3174                  * Set the interrupt throttling rate. Value is calculated
3175                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
3176                  */
3177                 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
3178         }
3179         E1000_WRITE_REG(&adapter->hw, E1000_RDTR,
3180             adapter->rx_int_delay.value);
3181
3182         /* Use extended rx descriptor formats */
3183         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3184         rfctl |= E1000_RFCTL_EXTEN;
3185         /*
3186          * When using MSI-X interrupts we need to throttle
3187          * using the EITR register (82574 only)
3188          */
3189         if (hw->mac.type == e1000_82574) {
3190                 for (int i = 0; i < 4; i++)
3191                         E1000_WRITE_REG(hw, E1000_EITR_82574(i),
3192                             DEFAULT_ITR);
3193                 /* Disable accelerated acknowledge */
3194                 rfctl |= E1000_RFCTL_ACK_DIS;
3195         }
3196         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3197
3198         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
3199         if (if_getcapenable(ifp) & IFCAP_RXCSUM &&
3200             adapter->hw.mac.type >= e1000_82543) {
3201                 if (adapter->tx_num_queues > 1) {
3202                         if (adapter->hw.mac.type >= igb_mac_min) {
3203                                 rxcsum |= E1000_RXCSUM_PCSD;
3204                                 if (hw->mac.type != e1000_82575)
3205                                         rxcsum |= E1000_RXCSUM_CRCOFL;
3206                         } else
3207                                 rxcsum |= E1000_RXCSUM_TUOFL |
3208                                         E1000_RXCSUM_IPOFL |
3209                                         E1000_RXCSUM_PCSD;
3210                 } else {
3211                         if (adapter->hw.mac.type >= igb_mac_min)
3212                                 rxcsum |= E1000_RXCSUM_IPPCSE;
3213                         else
3214                                 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
3215                         if (adapter->hw.mac.type > e1000_82575)
3216                                 rxcsum |= E1000_RXCSUM_CRCOFL;
3217                 }
3218         } else
3219                 rxcsum &= ~E1000_RXCSUM_TUOFL;
3220
3221         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
3222
3223         if (adapter->rx_num_queues > 1) {
3224                 if (adapter->hw.mac.type >= igb_mac_min)
3225                         igb_initialize_rss_mapping(adapter);
3226                 else
3227                         em_initialize_rss_mapping(adapter);
3228         }
3229
3230         /*
3231          * XXX TEMPORARY WORKAROUND: on some systems with 82573
3232          * long latencies are observed, like Lenovo X60. This
3233          * change eliminates the problem, but since having positive
3234          * values in RDTR is a known source of problems on other
3235          * platforms another solution is being sought.
3236          */
3237         if (hw->mac.type == e1000_82573)
3238                 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
3239
3240         for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3241                 struct rx_ring *rxr = &que->rxr;
3242                 /* Setup the Base and Length of the Rx Descriptor Ring */
3243                 u64 bus_addr = rxr->rx_paddr;
3244 #if 0
3245                 u32 rdt = adapter->rx_num_queues -1;  /* default */
3246 #endif
3247
3248                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3249                     scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
3250                 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
3251                 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
3252                 /* Setup the Head and Tail Descriptor Pointers */
3253                 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
3254                 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
3255         }
3256
3257         /*
3258          * Set PTHRESH for improved jumbo performance
3259          * According to 10.2.5.11 of Intel 82574 Datasheet,
3260          * RXDCTL(1) is written whenever RXDCTL(0) is written.
3261          * Only write to RXDCTL(1) if there is a need for different
3262          * settings.
3263          */
3264
3265         if (((adapter->hw.mac.type == e1000_ich9lan) ||
3266             (adapter->hw.mac.type == e1000_pch2lan) ||
3267             (adapter->hw.mac.type == e1000_ich10lan)) &&
3268             (if_getmtu(ifp) > ETHERMTU)) {
3269                 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
3270                 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
3271         } else if (adapter->hw.mac.type == e1000_82574) {
3272                 for (int i = 0; i < adapter->rx_num_queues; i++) {
3273                         u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3274                         rxdctl |= 0x20; /* PTHRESH */
3275                         rxdctl |= 4 << 8; /* HTHRESH */
3276                         rxdctl |= 4 << 16;/* WTHRESH */
3277                         rxdctl |= 1 << 24; /* Switch to granularity */
3278                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3279                 }
3280         } else if (adapter->hw.mac.type >= igb_mac_min) {
3281                 u32 psize, srrctl = 0;
3282
3283                 if (if_getmtu(ifp) > ETHERMTU) {
3284                         /* Set maximum packet len */
3285                         if (adapter->rx_mbuf_sz <= 4096) {
3286                                 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3287                                 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3288                         } else if (adapter->rx_mbuf_sz > 4096) {
3289                                 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3290                                 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3291                         }
3292                         psize = scctx->isc_max_frame_size;
3293                         /* are we on a vlan? */
3294                         if (ifp->if_vlantrunk != NULL)
3295                                 psize += VLAN_TAG_SIZE;
3296                         E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
3297                 } else {
3298                         srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3299                         rctl |= E1000_RCTL_SZ_2048;
3300                 }
3301
3302                 /*
3303                  * If TX flow control is disabled and there's >1 queue defined,
3304                  * enable DROP.
3305                  *
3306                  * This drops frames rather than hanging the RX MAC for all queues.
3307                  */
3308                 if ((adapter->rx_num_queues > 1) &&
3309                     (adapter->fc == e1000_fc_none ||
3310                      adapter->fc == e1000_fc_rx_pause)) {
3311                         srrctl |= E1000_SRRCTL_DROP_EN;
3312                 }
3313                         /* Setup the Base and Length of the Rx Descriptor Rings */
3314                 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3315                         struct rx_ring *rxr = &que->rxr;
3316                         u64 bus_addr = rxr->rx_paddr;
3317                         u32 rxdctl;
3318
3319 #ifdef notyet
3320                         /* Configure for header split? -- ignore for now */
3321                         rxr->hdr_split = igb_header_split;
3322 #else
3323                         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3324 #endif
3325
3326                         E1000_WRITE_REG(hw, E1000_RDLEN(i),
3327                                         scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3328                         E1000_WRITE_REG(hw, E1000_RDBAH(i),
3329                                         (uint32_t)(bus_addr >> 32));
3330                         E1000_WRITE_REG(hw, E1000_RDBAL(i),
3331                                         (uint32_t)bus_addr);
3332                         E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3333                         /* Enable this Queue */
3334                         rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3335                         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3336                         rxdctl &= 0xFFF00000;
3337                         rxdctl |= IGB_RX_PTHRESH;
3338                         rxdctl |= IGB_RX_HTHRESH << 8;
3339                         rxdctl |= IGB_RX_WTHRESH << 16;
3340                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3341                 }
3342         } else if (adapter->hw.mac.type >= e1000_pch2lan) {
3343                 if (if_getmtu(ifp) > ETHERMTU)
3344                         e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
3345                 else
3346                         e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
3347         }
3348
3349         /* Make sure VLAN Filters are off */
3350         rctl &= ~E1000_RCTL_VFE;
3351
3352         if (adapter->hw.mac.type < igb_mac_min) {
3353                 if (adapter->rx_mbuf_sz == MCLBYTES)
3354                         rctl |= E1000_RCTL_SZ_2048;
3355                 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE)
3356                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3357                 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE)
3358                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3359
3360                 /* ensure we clear use DTYPE of 00 here */
3361                 rctl &= ~0x00000C00;
3362         }
3363
3364         /* Write out the settings */
3365         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3366
3367         return;
3368 }
3369
3370 static void
3371 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3372 {
3373         struct adapter *adapter = iflib_get_softc(ctx);
3374         u32 index, bit;
3375
3376         index = (vtag >> 5) & 0x7F;
3377         bit = vtag & 0x1F;
3378         adapter->shadow_vfta[index] |= (1 << bit);
3379         ++adapter->num_vlans;
3380 }
3381
3382 static void
3383 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3384 {
3385         struct adapter *adapter = iflib_get_softc(ctx);
3386         u32 index, bit;
3387
3388         index = (vtag >> 5) & 0x7F;
3389         bit = vtag & 0x1F;
3390         adapter->shadow_vfta[index] &= ~(1 << bit);
3391         --adapter->num_vlans;
3392 }
3393
3394 static void
3395 em_setup_vlan_hw_support(struct adapter *adapter)
3396 {
3397         struct e1000_hw *hw = &adapter->hw;
3398         u32 reg;
3399
3400         /*
3401          * We get here thru init_locked, meaning
3402          * a soft reset, this has already cleared
3403          * the VFTA and other state, so if there
3404          * have been no vlan's registered do nothing.
3405          */
3406         if (adapter->num_vlans == 0)
3407                 return;
3408
3409         /*
3410          * A soft reset zero's out the VFTA, so
3411          * we need to repopulate it now.
3412          */
3413         for (int i = 0; i < EM_VFTA_SIZE; i++)
3414                 if (adapter->shadow_vfta[i] != 0)
3415                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
3416                             i, adapter->shadow_vfta[i]);
3417
3418         reg = E1000_READ_REG(hw, E1000_CTRL);
3419         reg |= E1000_CTRL_VME;
3420         E1000_WRITE_REG(hw, E1000_CTRL, reg);
3421
3422         /* Enable the Filter Table */
3423         reg = E1000_READ_REG(hw, E1000_RCTL);
3424         reg &= ~E1000_RCTL_CFIEN;
3425         reg |= E1000_RCTL_VFE;
3426         E1000_WRITE_REG(hw, E1000_RCTL, reg);
3427 }
3428
3429 static void
3430 em_if_intr_enable(if_ctx_t ctx)
3431 {
3432         struct adapter *adapter = iflib_get_softc(ctx);
3433         struct e1000_hw *hw = &adapter->hw;
3434         u32 ims_mask = IMS_ENABLE_MASK;
3435
3436         if (hw->mac.type == e1000_82574) {
3437                 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK);
3438                 ims_mask |= adapter->ims;
3439         }
3440         E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3441 }
3442
3443 static void
3444 em_if_intr_disable(if_ctx_t ctx)
3445 {
3446         struct adapter *adapter = iflib_get_softc(ctx);
3447         struct e1000_hw *hw = &adapter->hw;
3448
3449         if (hw->mac.type == e1000_82574)
3450                 E1000_WRITE_REG(hw, EM_EIAC, 0);
3451         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3452 }
3453
3454 static void
3455 igb_if_intr_enable(if_ctx_t ctx)
3456 {
3457         struct adapter *adapter = iflib_get_softc(ctx);
3458         struct e1000_hw *hw = &adapter->hw;
3459         u32 mask;
3460
3461         if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) {
3462                 mask = (adapter->que_mask | adapter->link_mask);
3463                 E1000_WRITE_REG(hw, E1000_EIAC, mask);
3464                 E1000_WRITE_REG(hw, E1000_EIAM, mask);
3465                 E1000_WRITE_REG(hw, E1000_EIMS, mask);
3466                 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
3467         } else
3468                 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
3469         E1000_WRITE_FLUSH(hw);
3470 }
3471
3472 static void
3473 igb_if_intr_disable(if_ctx_t ctx)
3474 {
3475         struct adapter *adapter = iflib_get_softc(ctx);
3476         struct e1000_hw *hw = &adapter->hw;
3477
3478         if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) {
3479                 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff);
3480                 E1000_WRITE_REG(hw, E1000_EIAC, 0);
3481         }
3482         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3483         E1000_WRITE_FLUSH(hw);
3484 }
3485
3486 /*
3487  * Bit of a misnomer, what this really means is
3488  * to enable OS management of the system... aka
3489  * to disable special hardware management features
3490  */
3491 static void
3492 em_init_manageability(struct adapter *adapter)
3493 {
3494         /* A shared code workaround */
3495 #define E1000_82542_MANC2H E1000_MANC2H
3496         if (adapter->has_manage) {
3497                 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3498                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3499
3500                 /* disable hardware interception of ARP */
3501                 manc &= ~(E1000_MANC_ARP_EN);
3502
3503                 /* enable receiving management packets to the host */
3504                 manc |= E1000_MANC_EN_MNG2HOST;
3505 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3506 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3507                 manc2h |= E1000_MNG2HOST_PORT_623;
3508                 manc2h |= E1000_MNG2HOST_PORT_664;
3509                 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3510                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3511         }
3512 }
3513
3514 /*
3515  * Give control back to hardware management
3516  * controller if there is one.
3517  */
3518 static void
3519 em_release_manageability(struct adapter *adapter)
3520 {
3521         if (adapter->has_manage) {
3522                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3523
3524                 /* re-enable hardware interception of ARP */
3525                 manc |= E1000_MANC_ARP_EN;
3526                 manc &= ~E1000_MANC_EN_MNG2HOST;
3527
3528                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3529         }
3530 }
3531
3532 /*
3533  * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3534  * For ASF and Pass Through versions of f/w this means
3535  * that the driver is loaded. For AMT version type f/w
3536  * this means that the network i/f is open.
3537  */
3538 static void
3539 em_get_hw_control(struct adapter *adapter)
3540 {
3541         u32 ctrl_ext, swsm;
3542
3543         if (adapter->vf_ifp)
3544                 return;
3545
3546         if (adapter->hw.mac.type == e1000_82573) {
3547                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3548                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3549                     swsm | E1000_SWSM_DRV_LOAD);
3550                 return;
3551         }
3552         /* else */
3553         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3554         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3555             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3556 }
3557
3558 /*
3559  * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3560  * For ASF and Pass Through versions of f/w this means that
3561  * the driver is no longer loaded. For AMT versions of the
3562  * f/w this means that the network i/f is closed.
3563  */
3564 static void
3565 em_release_hw_control(struct adapter *adapter)
3566 {
3567         u32 ctrl_ext, swsm;
3568
3569         if (!adapter->has_manage)
3570                 return;
3571
3572         if (adapter->hw.mac.type == e1000_82573) {
3573                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3574                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3575                     swsm & ~E1000_SWSM_DRV_LOAD);
3576                 return;
3577         }
3578         /* else */
3579         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3580         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3581             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3582         return;
3583 }
3584
3585 static int
3586 em_is_valid_ether_addr(u8 *addr)
3587 {
3588         char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3589
3590         if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3591                 return (FALSE);
3592         }
3593
3594         return (TRUE);
3595 }
3596
3597 /*
3598 ** Parse the interface capabilities with regard
3599 ** to both system management and wake-on-lan for
3600 ** later use.
3601 */
3602 static void
3603 em_get_wakeup(if_ctx_t ctx)
3604 {
3605         struct adapter *adapter = iflib_get_softc(ctx);
3606         device_t dev = iflib_get_dev(ctx);
3607         u16 eeprom_data = 0, device_id, apme_mask;
3608
3609         adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
3610         apme_mask = EM_EEPROM_APME;
3611
3612         switch (adapter->hw.mac.type) {
3613         case e1000_82542:
3614         case e1000_82543:
3615                 break;
3616         case e1000_82544:
3617                 e1000_read_nvm(&adapter->hw,
3618                     NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3619                 apme_mask = EM_82544_APME;
3620                 break;
3621         case e1000_82546:
3622         case e1000_82546_rev_3:
3623                 if (adapter->hw.bus.func == 1) {
3624                         e1000_read_nvm(&adapter->hw,
3625                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3626                         break;
3627                 } else
3628                         e1000_read_nvm(&adapter->hw,
3629                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3630                 break;
3631         case e1000_82573:
3632         case e1000_82583:
3633                 adapter->has_amt = TRUE;
3634                 /* FALLTHROUGH */
3635         case e1000_82571:
3636         case e1000_82572:
3637         case e1000_80003es2lan:
3638                 if (adapter->hw.bus.func == 1) {
3639                         e1000_read_nvm(&adapter->hw,
3640                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3641                         break;
3642                 } else
3643                         e1000_read_nvm(&adapter->hw,
3644                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3645                 break;
3646         case e1000_ich8lan:
3647         case e1000_ich9lan:
3648         case e1000_ich10lan:
3649         case e1000_pchlan:
3650         case e1000_pch2lan:
3651         case e1000_pch_lpt:
3652         case e1000_pch_spt:
3653         case e1000_82575:       /* listing all igb devices */
3654         case e1000_82576:
3655         case e1000_82580:
3656         case e1000_i350:
3657         case e1000_i354:
3658         case e1000_i210:
3659         case e1000_i211:
3660         case e1000_vfadapt:
3661         case e1000_vfadapt_i350:
3662                 apme_mask = E1000_WUC_APME;
3663                 adapter->has_amt = TRUE;
3664                 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
3665                 break;
3666         default:
3667                 e1000_read_nvm(&adapter->hw,
3668                     NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3669                 break;
3670         }
3671         if (eeprom_data & apme_mask)
3672                 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
3673         /*
3674          * We have the eeprom settings, now apply the special cases
3675          * where the eeprom may be wrong or the board won't support
3676          * wake on lan on a particular port
3677          */
3678         device_id = pci_get_device(dev);
3679         switch (device_id) {
3680         case E1000_DEV_ID_82546GB_PCIE:
3681                 adapter->wol = 0;
3682                 break;
3683         case E1000_DEV_ID_82546EB_FIBER:
3684         case E1000_DEV_ID_82546GB_FIBER:
3685                 /* Wake events only supported on port A for dual fiber
3686                  * regardless of eeprom setting */
3687                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3688                     E1000_STATUS_FUNC_1)
3689                         adapter->wol = 0;
3690                 break;
3691         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
3692                 /* if quad port adapter, disable WoL on all but port A */
3693                 if (global_quad_port_a != 0)
3694                         adapter->wol = 0;
3695                 /* Reset for multiple quad port adapters */
3696                 if (++global_quad_port_a == 4)
3697                         global_quad_port_a = 0;
3698                 break;
3699         case E1000_DEV_ID_82571EB_FIBER:
3700                 /* Wake events only supported on port A for dual fiber
3701                  * regardless of eeprom setting */
3702                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3703                     E1000_STATUS_FUNC_1)
3704                         adapter->wol = 0;
3705                 break;
3706         case E1000_DEV_ID_82571EB_QUAD_COPPER:
3707         case E1000_DEV_ID_82571EB_QUAD_FIBER:
3708         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
3709                 /* if quad port adapter, disable WoL on all but port A */
3710                 if (global_quad_port_a != 0)
3711                         adapter->wol = 0;
3712                 /* Reset for multiple quad port adapters */
3713                 if (++global_quad_port_a == 4)
3714                         global_quad_port_a = 0;
3715                 break;
3716         }
3717         return;
3718 }
3719
3720
3721 /*
3722  * Enable PCI Wake On Lan capability
3723  */
3724 static void
3725 em_enable_wakeup(if_ctx_t ctx)
3726 {
3727         struct adapter *adapter = iflib_get_softc(ctx);
3728         device_t dev = iflib_get_dev(ctx);
3729         if_t ifp = iflib_get_ifp(ctx);
3730         int error = 0;
3731         u32 pmc, ctrl, ctrl_ext, rctl;
3732         u16 status;
3733
3734         if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
3735                 return;
3736
3737         /*
3738          * Determine type of Wakeup: note that wol
3739          * is set with all bits on by default.
3740          */
3741         if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
3742                 adapter->wol &= ~E1000_WUFC_MAG;
3743
3744         if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
3745                 adapter->wol &= ~E1000_WUFC_EX;
3746
3747         if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
3748                 adapter->wol &= ~E1000_WUFC_MC;
3749         else {
3750                 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3751                 rctl |= E1000_RCTL_MPE;
3752                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3753         }
3754
3755         if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC)))
3756                 goto pme;
3757
3758         /* Advertise the wakeup capability */
3759         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
3760         ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
3761         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
3762
3763         /* Keep the laser running on Fiber adapters */
3764         if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3765             adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
3766                 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3767                 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
3768                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext);
3769         }
3770
3771         if ((adapter->hw.mac.type == e1000_ich8lan) ||
3772             (adapter->hw.mac.type == e1000_pchlan) ||
3773             (adapter->hw.mac.type == e1000_ich9lan) ||
3774             (adapter->hw.mac.type == e1000_ich10lan))
3775                 e1000_suspend_workarounds_ich8lan(&adapter->hw);
3776
3777         if ( adapter->hw.mac.type >= e1000_pchlan) {
3778                 error = em_enable_phy_wakeup(adapter);
3779                 if (error)
3780                         goto pme;
3781         } else {
3782                 /* Enable wakeup by the MAC */
3783                 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
3784                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
3785         }
3786
3787         if (adapter->hw.phy.type == e1000_phy_igp_3)
3788                 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
3789
3790 pme:
3791         status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
3792         status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3793         if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
3794                 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3795         pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
3796
3797         return;
3798 }
3799
3800 /*
3801  * WOL in the newer chipset interfaces (pchlan)
3802  * require thing to be copied into the phy
3803  */
3804 static int
3805 em_enable_phy_wakeup(struct adapter *adapter)
3806 {
3807         struct e1000_hw *hw = &adapter->hw;
3808         u32 mreg, ret = 0;
3809         u16 preg;
3810
3811         /* copy MAC RARs to PHY RARs */
3812         e1000_copy_rx_addrs_to_phy_ich8lan(hw);
3813
3814         /* copy MAC MTA to PHY MTA */
3815         for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
3816                 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
3817                 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
3818                 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
3819                     (u16)((mreg >> 16) & 0xFFFF));
3820         }
3821
3822         /* configure PHY Rx Control register */
3823         e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg);
3824         mreg = E1000_READ_REG(hw, E1000_RCTL);
3825         if (mreg & E1000_RCTL_UPE)
3826                 preg |= BM_RCTL_UPE;
3827         if (mreg & E1000_RCTL_MPE)
3828                 preg |= BM_RCTL_MPE;
3829         preg &= ~(BM_RCTL_MO_MASK);
3830         if (mreg & E1000_RCTL_MO_3)
3831                 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
3832                                 << BM_RCTL_MO_SHIFT);
3833         if (mreg & E1000_RCTL_BAM)
3834                 preg |= BM_RCTL_BAM;
3835         if (mreg & E1000_RCTL_PMCF)
3836                 preg |= BM_RCTL_PMCF;
3837         mreg = E1000_READ_REG(hw, E1000_CTRL);
3838         if (mreg & E1000_CTRL_RFCE)
3839                 preg |= BM_RCTL_RFCE;
3840         e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg);
3841
3842         /* enable PHY wakeup in MAC register */
3843         E1000_WRITE_REG(hw, E1000_WUC,
3844             E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
3845         E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol);
3846
3847         /* configure and enable PHY wakeup in PHY registers */
3848         e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol);
3849         e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
3850
3851         /* activate PHY wakeup */
3852         ret = hw->phy.ops.acquire(hw);
3853         if (ret) {
3854                 printf("Could not acquire PHY\n");
3855                 return ret;
3856         }
3857         e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3858                                  (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3859         ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
3860         if (ret) {
3861                 printf("Could not read PHY page 769\n");
3862                 goto out;
3863         }
3864         preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
3865         ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
3866         if (ret)
3867                 printf("Could not set PHY Host Wakeup bit\n");
3868 out:
3869         hw->phy.ops.release(hw);
3870
3871         return ret;
3872 }
3873
3874 static void
3875 em_if_led_func(if_ctx_t ctx, int onoff)
3876 {
3877         struct adapter *adapter = iflib_get_softc(ctx);
3878
3879         if (onoff) {
3880                 e1000_setup_led(&adapter->hw);
3881                 e1000_led_on(&adapter->hw);
3882         } else {
3883                 e1000_led_off(&adapter->hw);
3884                 e1000_cleanup_led(&adapter->hw);
3885         }
3886 }
3887
3888 /*
3889  * Disable the L0S and L1 LINK states
3890  */
3891 static void
3892 em_disable_aspm(struct adapter *adapter)
3893 {
3894         int base, reg;
3895         u16 link_cap,link_ctrl;
3896         device_t dev = adapter->dev;
3897
3898         switch (adapter->hw.mac.type) {
3899         case e1000_82573:
3900         case e1000_82574:
3901         case e1000_82583:
3902                 break;
3903         default:
3904                 return;
3905         }
3906         if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
3907                 return;
3908         reg = base + PCIER_LINK_CAP;
3909         link_cap = pci_read_config(dev, reg, 2);
3910         if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
3911                 return;
3912         reg = base + PCIER_LINK_CTL;
3913         link_ctrl = pci_read_config(dev, reg, 2);
3914         link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
3915         pci_write_config(dev, reg, link_ctrl, 2);
3916         return;
3917 }
3918
3919 /**********************************************************************
3920  *
3921  *  Update the board statistics counters.
3922  *
3923  **********************************************************************/
3924 static void
3925 em_update_stats_counters(struct adapter *adapter)
3926 {
3927         u64 prev_xoffrxc = adapter->stats.xoffrxc;
3928
3929         if(adapter->hw.phy.media_type == e1000_media_type_copper ||
3930            (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3931                 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
3932                 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
3933         }
3934         adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
3935         adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
3936         adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
3937         adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
3938
3939         adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
3940         adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
3941         adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
3942         adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
3943         adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
3944         adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
3945         adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
3946         adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
3947         /*
3948          ** For watchdog management we need to know if we have been
3949          ** paused during the last interval, so capture that here.
3950         */
3951         if (adapter->stats.xoffrxc != prev_xoffrxc)
3952                 adapter->shared->isc_pause_frames = 1;
3953         adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
3954         adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
3955         adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
3956         adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
3957         adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
3958         adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
3959         adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
3960         adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
3961         adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
3962         adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
3963         adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
3964         adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
3965
3966         /* For the 64-bit byte counters the low dword must be read first. */
3967         /* Both registers clear on the read of the high dword */
3968
3969         adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) +
3970             ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32);
3971         adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) +
3972             ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32);
3973
3974         adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
3975         adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
3976         adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
3977         adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
3978         adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
3979
3980         adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
3981         adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
3982
3983         adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
3984         adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
3985         adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
3986         adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
3987         adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
3988         adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
3989         adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
3990         adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
3991         adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
3992         adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
3993
3994         /* Interrupt Counts */
3995
3996         adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC);
3997         adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC);
3998         adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC);
3999         adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC);
4000         adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC);
4001         adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC);
4002         adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC);
4003         adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC);
4004         adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC);
4005
4006         if (adapter->hw.mac.type >= e1000_82543) {
4007                 adapter->stats.algnerrc +=
4008                 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
4009                 adapter->stats.rxerrc +=
4010                 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
4011                 adapter->stats.tncrs +=
4012                 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
4013                 adapter->stats.cexterr +=
4014                 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
4015                 adapter->stats.tsctc +=
4016                 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
4017                 adapter->stats.tsctfc +=
4018                 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
4019         }
4020 }
4021
4022 static uint64_t
4023 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
4024 {
4025         struct adapter *adapter = iflib_get_softc(ctx);
4026         struct ifnet *ifp = iflib_get_ifp(ctx);
4027
4028         switch (cnt) {
4029         case IFCOUNTER_COLLISIONS:
4030                 return (adapter->stats.colc);
4031         case IFCOUNTER_IERRORS:
4032                 return (adapter->dropped_pkts + adapter->stats.rxerrc +
4033                     adapter->stats.crcerrs + adapter->stats.algnerrc +
4034                     adapter->stats.ruc + adapter->stats.roc +
4035                     adapter->stats.mpc + adapter->stats.cexterr);
4036         case IFCOUNTER_OERRORS:
4037                 return (adapter->stats.ecol + adapter->stats.latecol +
4038                     adapter->watchdog_events);
4039         default:
4040                 return (if_get_counter_default(ifp, cnt));
4041         }
4042 }
4043
4044 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized
4045  * @ctx: iflib context
4046  * @event: event code to check
4047  *
4048  * Defaults to returning true for unknown events.
4049  *
4050  * @returns true if iflib needs to reinit the interface
4051  */
4052 static bool
4053 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
4054 {
4055         switch (event) {
4056         case IFLIB_RESTART_VLAN_CONFIG:
4057                 return (false);
4058         default:
4059                 return (true);
4060         }
4061 }
4062
4063 /* Export a single 32-bit register via a read-only sysctl. */
4064 static int
4065 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
4066 {
4067         struct adapter *adapter;
4068         u_int val;
4069
4070         adapter = oidp->oid_arg1;
4071         val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2);
4072         return (sysctl_handle_int(oidp, &val, 0, req));
4073 }
4074
4075 /*
4076  * Add sysctl variables, one per statistic, to the system.
4077  */
4078 static void
4079 em_add_hw_stats(struct adapter *adapter)
4080 {
4081         device_t dev = iflib_get_dev(adapter->ctx);
4082         struct em_tx_queue *tx_que = adapter->tx_queues;
4083         struct em_rx_queue *rx_que = adapter->rx_queues;
4084
4085         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
4086         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
4087         struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
4088         struct e1000_hw_stats *stats = &adapter->stats;
4089
4090         struct sysctl_oid *stat_node, *queue_node, *int_node;
4091         struct sysctl_oid_list *stat_list, *queue_list, *int_list;
4092
4093 #define QUEUE_NAME_LEN 32
4094         char namebuf[QUEUE_NAME_LEN];
4095
4096         /* Driver Statistics */
4097         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
4098                         CTLFLAG_RD, &adapter->dropped_pkts,
4099                         "Driver dropped packets");
4100         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
4101                         CTLFLAG_RD, &adapter->link_irq,
4102                         "Link MSI-X IRQ Handled");
4103         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
4104                         CTLFLAG_RD, &adapter->rx_overruns,
4105                         "RX overruns");
4106         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
4107                         CTLFLAG_RD, &adapter->watchdog_events,
4108                         "Watchdog timeouts");
4109         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
4110             CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
4111             adapter, E1000_CTRL, em_sysctl_reg_handler, "IU",
4112             "Device Control Register");
4113         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
4114             CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
4115             adapter, E1000_RCTL, em_sysctl_reg_handler, "IU",
4116             "Receiver Control Register");
4117         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
4118                         CTLFLAG_RD, &adapter->hw.fc.high_water, 0,
4119                         "Flow Control High Watermark");
4120         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
4121                         CTLFLAG_RD, &adapter->hw.fc.low_water, 0,
4122                         "Flow Control Low Watermark");
4123
4124         for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
4125                 struct tx_ring *txr = &tx_que->txr;
4126                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
4127                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4128                     CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name");
4129                 queue_list = SYSCTL_CHILDREN(queue_node);
4130
4131                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
4132                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4133                     E1000_TDH(txr->me), em_sysctl_reg_handler, "IU",
4134                     "Transmit Descriptor Head");
4135                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
4136                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4137                     E1000_TDT(txr->me), em_sysctl_reg_handler, "IU",
4138                     "Transmit Descriptor Tail");
4139                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
4140                                 CTLFLAG_RD, &txr->tx_irq,
4141                                 "Queue MSI-X Transmit Interrupts");
4142         }
4143
4144         for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) {
4145                 struct rx_ring *rxr = &rx_que->rxr;
4146                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
4147                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4148                     CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name");
4149                 queue_list = SYSCTL_CHILDREN(queue_node);
4150
4151                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
4152                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4153                     E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU",
4154                     "Receive Descriptor Head");
4155                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
4156                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4157                     E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU",
4158                     "Receive Descriptor Tail");
4159                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
4160                                 CTLFLAG_RD, &rxr->rx_irq,
4161                                 "Queue MSI-X Receive Interrupts");
4162         }
4163
4164         /* MAC stats get their own sub node */
4165
4166         stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
4167             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics");
4168         stat_list = SYSCTL_CHILDREN(stat_node);
4169
4170         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
4171                         CTLFLAG_RD, &stats->ecol,
4172                         "Excessive collisions");
4173         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
4174                         CTLFLAG_RD, &stats->scc,
4175                         "Single collisions");
4176         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
4177                         CTLFLAG_RD, &stats->mcc,
4178                         "Multiple collisions");
4179         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
4180                         CTLFLAG_RD, &stats->latecol,
4181                         "Late collisions");
4182         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
4183                         CTLFLAG_RD, &stats->colc,
4184                         "Collision Count");
4185         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
4186                         CTLFLAG_RD, &adapter->stats.symerrs,
4187                         "Symbol Errors");
4188         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
4189                         CTLFLAG_RD, &adapter->stats.sec,
4190                         "Sequence Errors");
4191         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
4192                         CTLFLAG_RD, &adapter->stats.dc,
4193                         "Defer Count");
4194         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
4195                         CTLFLAG_RD, &adapter->stats.mpc,
4196                         "Missed Packets");
4197         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
4198                         CTLFLAG_RD, &adapter->stats.rnbc,
4199                         "Receive No Buffers");
4200         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
4201                         CTLFLAG_RD, &adapter->stats.ruc,
4202                         "Receive Undersize");
4203         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
4204                         CTLFLAG_RD, &adapter->stats.rfc,
4205                         "Fragmented Packets Received ");
4206         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
4207                         CTLFLAG_RD, &adapter->stats.roc,
4208                         "Oversized Packets Received");
4209         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
4210                         CTLFLAG_RD, &adapter->stats.rjc,
4211                         "Recevied Jabber");
4212         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
4213                         CTLFLAG_RD, &adapter->stats.rxerrc,
4214                         "Receive Errors");
4215         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
4216                         CTLFLAG_RD, &adapter->stats.crcerrs,
4217                         "CRC errors");
4218         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
4219                         CTLFLAG_RD, &adapter->stats.algnerrc,
4220                         "Alignment Errors");
4221         /* On 82575 these are collision counts */
4222         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
4223                         CTLFLAG_RD, &adapter->stats.cexterr,
4224                         "Collision/Carrier extension errors");
4225         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
4226                         CTLFLAG_RD, &adapter->stats.xonrxc,
4227                         "XON Received");
4228         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
4229                         CTLFLAG_RD, &adapter->stats.xontxc,
4230                         "XON Transmitted");
4231         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
4232                         CTLFLAG_RD, &adapter->stats.xoffrxc,
4233                         "XOFF Received");
4234         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
4235                         CTLFLAG_RD, &adapter->stats.xofftxc,
4236                         "XOFF Transmitted");
4237
4238         /* Packet Reception Stats */
4239         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
4240                         CTLFLAG_RD, &adapter->stats.tpr,
4241                         "Total Packets Received ");
4242         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
4243                         CTLFLAG_RD, &adapter->stats.gprc,
4244                         "Good Packets Received");
4245         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
4246                         CTLFLAG_RD, &adapter->stats.bprc,
4247                         "Broadcast Packets Received");
4248         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
4249                         CTLFLAG_RD, &adapter->stats.mprc,
4250                         "Multicast Packets Received");
4251         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
4252                         CTLFLAG_RD, &adapter->stats.prc64,
4253                         "64 byte frames received ");
4254         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
4255                         CTLFLAG_RD, &adapter->stats.prc127,
4256                         "65-127 byte frames received");
4257         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
4258                         CTLFLAG_RD, &adapter->stats.prc255,
4259                         "128-255 byte frames received");
4260         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
4261                         CTLFLAG_RD, &adapter->stats.prc511,
4262                         "256-511 byte frames received");
4263         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
4264                         CTLFLAG_RD, &adapter->stats.prc1023,
4265                         "512-1023 byte frames received");
4266         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
4267                         CTLFLAG_RD, &adapter->stats.prc1522,
4268                         "1023-1522 byte frames received");
4269         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
4270                         CTLFLAG_RD, &adapter->stats.gorc,
4271                         "Good Octets Received");
4272
4273         /* Packet Transmission Stats */
4274         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
4275                         CTLFLAG_RD, &adapter->stats.gotc,
4276                         "Good Octets Transmitted");
4277         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
4278                         CTLFLAG_RD, &adapter->stats.tpt,
4279                         "Total Packets Transmitted");
4280         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
4281                         CTLFLAG_RD, &adapter->stats.gptc,
4282                         "Good Packets Transmitted");
4283         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
4284                         CTLFLAG_RD, &adapter->stats.bptc,
4285                         "Broadcast Packets Transmitted");
4286         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
4287                         CTLFLAG_RD, &adapter->stats.mptc,
4288                         "Multicast Packets Transmitted");
4289         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
4290                         CTLFLAG_RD, &adapter->stats.ptc64,
4291                         "64 byte frames transmitted ");
4292         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
4293                         CTLFLAG_RD, &adapter->stats.ptc127,
4294                         "65-127 byte frames transmitted");
4295         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
4296                         CTLFLAG_RD, &adapter->stats.ptc255,
4297                         "128-255 byte frames transmitted");
4298         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
4299                         CTLFLAG_RD, &adapter->stats.ptc511,
4300                         "256-511 byte frames transmitted");
4301         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
4302                         CTLFLAG_RD, &adapter->stats.ptc1023,
4303                         "512-1023 byte frames transmitted");
4304         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
4305                         CTLFLAG_RD, &adapter->stats.ptc1522,
4306                         "1024-1522 byte frames transmitted");
4307         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
4308                         CTLFLAG_RD, &adapter->stats.tsctc,
4309                         "TSO Contexts Transmitted");
4310         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
4311                         CTLFLAG_RD, &adapter->stats.tsctfc,
4312                         "TSO Contexts Failed");
4313
4314
4315         /* Interrupt Stats */
4316
4317         int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
4318             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics");
4319         int_list = SYSCTL_CHILDREN(int_node);
4320
4321         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
4322                         CTLFLAG_RD, &adapter->stats.iac,
4323                         "Interrupt Assertion Count");
4324
4325         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
4326                         CTLFLAG_RD, &adapter->stats.icrxptc,
4327                         "Interrupt Cause Rx Pkt Timer Expire Count");
4328
4329         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
4330                         CTLFLAG_RD, &adapter->stats.icrxatc,
4331                         "Interrupt Cause Rx Abs Timer Expire Count");
4332
4333         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
4334                         CTLFLAG_RD, &adapter->stats.ictxptc,
4335                         "Interrupt Cause Tx Pkt Timer Expire Count");
4336
4337         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
4338                         CTLFLAG_RD, &adapter->stats.ictxatc,
4339                         "Interrupt Cause Tx Abs Timer Expire Count");
4340
4341         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
4342                         CTLFLAG_RD, &adapter->stats.ictxqec,
4343                         "Interrupt Cause Tx Queue Empty Count");
4344
4345         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
4346                         CTLFLAG_RD, &adapter->stats.ictxqmtc,
4347                         "Interrupt Cause Tx Queue Min Thresh Count");
4348
4349         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
4350                         CTLFLAG_RD, &adapter->stats.icrxdmtc,
4351                         "Interrupt Cause Rx Desc Min Thresh Count");
4352
4353         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
4354                         CTLFLAG_RD, &adapter->stats.icrxoc,
4355                         "Interrupt Cause Receiver Overrun Count");
4356 }
4357
4358 /**********************************************************************
4359  *
4360  *  This routine provides a way to dump out the adapter eeprom,
4361  *  often a useful debug/service tool. This only dumps the first
4362  *  32 words, stuff that matters is in that extent.
4363  *
4364  **********************************************************************/
4365 static int
4366 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4367 {
4368         struct adapter *adapter = (struct adapter *)arg1;
4369         int error;
4370         int result;
4371
4372         result = -1;
4373         error = sysctl_handle_int(oidp, &result, 0, req);
4374
4375         if (error || !req->newptr)
4376                 return (error);
4377
4378         /*
4379          * This value will cause a hex dump of the
4380          * first 32 16-bit words of the EEPROM to
4381          * the screen.
4382          */
4383         if (result == 1)
4384                 em_print_nvm_info(adapter);
4385
4386         return (error);
4387 }
4388
4389 static void
4390 em_print_nvm_info(struct adapter *adapter)
4391 {
4392         u16 eeprom_data;
4393         int i, j, row = 0;
4394
4395         /* Its a bit crude, but it gets the job done */
4396         printf("\nInterface EEPROM Dump:\n");
4397         printf("Offset\n0x0000  ");
4398         for (i = 0, j = 0; i < 32; i++, j++) {
4399                 if (j == 8) { /* Make the offset block */
4400                         j = 0; ++row;
4401                         printf("\n0x00%x0  ",row);
4402                 }
4403                 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
4404                 printf("%04x ", eeprom_data);
4405         }
4406         printf("\n");
4407 }
4408
4409 static int
4410 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4411 {
4412         struct em_int_delay_info *info;
4413         struct adapter *adapter;
4414         u32 regval;
4415         int error, usecs, ticks;
4416
4417         info = (struct em_int_delay_info *) arg1;
4418         usecs = info->value;
4419         error = sysctl_handle_int(oidp, &usecs, 0, req);
4420         if (error != 0 || req->newptr == NULL)
4421                 return (error);
4422         if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4423                 return (EINVAL);
4424         info->value = usecs;
4425         ticks = EM_USECS_TO_TICKS(usecs);
4426         if (info->offset == E1000_ITR)  /* units are 256ns here */
4427                 ticks *= 4;
4428
4429         adapter = info->adapter;
4430
4431         regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
4432         regval = (regval & ~0xffff) | (ticks & 0xffff);
4433         /* Handle a few special cases. */
4434         switch (info->offset) {
4435         case E1000_RDTR:
4436                 break;
4437         case E1000_TIDV:
4438                 if (ticks == 0) {
4439                         adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
4440                         /* Don't write 0 into the TIDV register. */
4441                         regval++;
4442                 } else
4443                         adapter->txd_cmd |= E1000_TXD_CMD_IDE;
4444                 break;
4445         }
4446         E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
4447         return (0);
4448 }
4449
4450 static void
4451 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
4452         const char *description, struct em_int_delay_info *info,
4453         int offset, int value)
4454 {
4455         info->adapter = adapter;
4456         info->offset = offset;
4457         info->value = value;
4458         SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev),
4459             SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4460             OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
4461             info, 0, em_sysctl_int_delay, "I", description);
4462 }
4463
4464 /*
4465  * Set flow control using sysctl:
4466  * Flow control values:
4467  *      0 - off
4468  *      1 - rx pause
4469  *      2 - tx pause
4470  *      3 - full
4471  */
4472 static int
4473 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4474 {
4475         int error;
4476         static int input = 3; /* default is full */
4477         struct adapter  *adapter = (struct adapter *) arg1;
4478
4479         error = sysctl_handle_int(oidp, &input, 0, req);
4480
4481         if ((error) || (req->newptr == NULL))
4482                 return (error);
4483
4484         if (input == adapter->fc) /* no change? */
4485                 return (error);
4486
4487         switch (input) {
4488         case e1000_fc_rx_pause:
4489         case e1000_fc_tx_pause:
4490         case e1000_fc_full:
4491         case e1000_fc_none:
4492                 adapter->hw.fc.requested_mode = input;
4493                 adapter->fc = input;
4494                 break;
4495         default:
4496                 /* Do nothing */
4497                 return (error);
4498         }
4499
4500         adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
4501         e1000_force_mac_fc(&adapter->hw);
4502         return (error);
4503 }
4504
4505 /*
4506  * Manage Energy Efficient Ethernet:
4507  * Control values:
4508  *     0/1 - enabled/disabled
4509  */
4510 static int
4511 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4512 {
4513         struct adapter *adapter = (struct adapter *) arg1;
4514         int error, value;
4515
4516         value = adapter->hw.dev_spec.ich8lan.eee_disable;
4517         error = sysctl_handle_int(oidp, &value, 0, req);
4518         if (error || req->newptr == NULL)
4519                 return (error);
4520         adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4521         em_if_init(adapter->ctx);
4522
4523         return (0);
4524 }
4525
4526 static int
4527 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4528 {
4529         struct adapter *adapter;
4530         int error;
4531         int result;
4532
4533         result = -1;
4534         error = sysctl_handle_int(oidp, &result, 0, req);
4535
4536         if (error || !req->newptr)
4537                 return (error);
4538
4539         if (result == 1) {
4540                 adapter = (struct adapter *) arg1;
4541                 em_print_debug_info(adapter);
4542         }
4543
4544         return (error);
4545 }
4546
4547 static int
4548 em_get_rs(SYSCTL_HANDLER_ARGS)
4549 {
4550         struct adapter *adapter = (struct adapter *) arg1;
4551         int error;
4552         int result;
4553
4554         result = 0;
4555         error = sysctl_handle_int(oidp, &result, 0, req);
4556
4557         if (error || !req->newptr || result != 1)
4558                 return (error);
4559         em_dump_rs(adapter);
4560
4561         return (error);
4562 }
4563
4564 static void
4565 em_if_debug(if_ctx_t ctx)
4566 {
4567         em_dump_rs(iflib_get_softc(ctx));
4568 }
4569
4570 /*
4571  * This routine is meant to be fluid, add whatever is
4572  * needed for debugging a problem.  -jfv
4573  */
4574 static void
4575 em_print_debug_info(struct adapter *adapter)
4576 {
4577         device_t dev = iflib_get_dev(adapter->ctx);
4578         struct ifnet *ifp = iflib_get_ifp(adapter->ctx);
4579         struct tx_ring *txr = &adapter->tx_queues->txr;
4580         struct rx_ring *rxr = &adapter->rx_queues->rxr;
4581
4582         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
4583                 printf("Interface is RUNNING ");
4584         else
4585                 printf("Interface is NOT RUNNING\n");
4586
4587         if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
4588                 printf("and INACTIVE\n");
4589         else
4590                 printf("and ACTIVE\n");
4591
4592         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
4593                 device_printf(dev, "TX Queue %d ------\n", i);
4594                 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
4595                         E1000_READ_REG(&adapter->hw, E1000_TDH(i)),
4596                         E1000_READ_REG(&adapter->hw, E1000_TDT(i)));
4597
4598         }
4599         for (int j=0; j < adapter->rx_num_queues; j++, rxr++) {
4600                 device_printf(dev, "RX Queue %d ------\n", j);
4601                 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
4602                         E1000_READ_REG(&adapter->hw, E1000_RDH(j)),
4603                         E1000_READ_REG(&adapter->hw, E1000_RDT(j)));
4604         }
4605 }
4606
4607 /*
4608  * 82574 only:
4609  * Write a new value to the EEPROM increasing the number of MSI-X
4610  * vectors from 3 to 5, for proper multiqueue support.
4611  */
4612 static void
4613 em_enable_vectors_82574(if_ctx_t ctx)
4614 {
4615         struct adapter *adapter = iflib_get_softc(ctx);
4616         struct e1000_hw *hw = &adapter->hw;
4617         device_t dev = iflib_get_dev(ctx);
4618         u16 edata;
4619
4620         e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4621         if (bootverbose)
4622                 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata);
4623         if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
4624                 device_printf(dev, "Writing to eeprom: increasing "
4625                     "reported MSI-X vectors from 3 to 5...\n");
4626                 edata &= ~(EM_NVM_MSIX_N_MASK);
4627                 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
4628                 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4629                 e1000_update_nvm_checksum(hw);
4630                 device_printf(dev, "Writing to eeprom: done\n");
4631         }
4632 }