sys/dev/e1000/if_em.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /* $FreeBSD$ */
  30 #include "if_em.h"
  31 #include <sys/sbuf.h>
  32 #include <machine/_inttypes.h>
  33
  34 #define em_mac_min e1000_82547
  35 #define igb_mac_min e1000_82575
  36
  37 /*********************************************************************
  38  *  Driver version:
  39  *********************************************************************/
  40 char em_driver_version[] = "7.6.1-k";
  41
  42 /*********************************************************************
  43  *  PCI Device ID Table
  44  *
  45  *  Used by probe to select devices to load on
  46  *  Last field stores an index into e1000_strings
  47  *  Last entry must be all 0s
  48  *
  49  *  { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
  50  *********************************************************************/
  51
  52 static pci_vendor_info_t em_vendor_info_array[] =
  53 {
  54         /* Intel(R) PRO/1000 Network Connection - Legacy em*/
  55         PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"),
  56         PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"),
  57         PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"),
  58         PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"),
  59         PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"),
  60
  61         PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"),
  62         PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"),
  63         PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"),
  64         PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  65         PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"),
  66         PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"),
  67         PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  68
  69         PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"),
  70
  71         PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"),
  72         PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
  73
  74         PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
  75         PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
  76         PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"),
  77         PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"),
  78
  79         PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"),
  80         PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"),
  81         PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"),
  82         PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"),
  83         PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"),
  84
  85         PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  86         PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
  87         PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
  88         PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"),
  89         PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"),
  90         PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"),
  91         PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"),
  92         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
  93         PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"),
  94
  95         PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"),
  96         PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"),
  97         PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"),
  98
  99         /* Intel(R) PRO/1000 Network Connection - em */
 100         PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"),
 101         PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"),
 102         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"),
 103         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"),
 104         PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"),
 105         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 106         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"),
 107         PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"),
 108         PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"),
 109         PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"),
 110         PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"),
 111         PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"),
 112         PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"),
 113         PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"),
 114         PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"),
 115         PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"),
 116         PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"),
 117         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"),
 118         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"),
 119         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"),
 120         PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"),
 121         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
 122         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 123         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"),
 124         PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"),
 125         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
 126         PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"),
 127         PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"),
 128         PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"),
 129         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"),
 130         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"),
 131         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"),
 132         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"),
 133         PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"),
 134         PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"),
 135         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"),
 136         PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"),
 137         PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"),
 138         PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"),
 139         PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"),
 140         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"),
 141         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"),
 142         PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"),
 143         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"),
 144         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"),
 145         PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"),
 146         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"),
 147         PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"),
 148         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"),
 149         PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"),
 150         PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"),
 151         PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"),
 152         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"),
 153         PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"),
 154         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"),
 155         PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"),
 156         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"),
 157         PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"),
 158         PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"),
 159         PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"),
 160         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"),
 161         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"),
 162         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"),
 163         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"),
 164         PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"),
 165         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"),
 166         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"),
 167         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"),
 168         PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"),
 169         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) PRO/1000 Network Connection"),
 170         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) PRO/1000 Network Connection"),
 171         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) PRO/1000 Network Connection"),
 172         PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) PRO/1000 Network Connection"),
 173         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) PRO/1000 Network Connection"),
 174         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) PRO/1000 Network Connection"),
 175         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) PRO/1000 Network Connection"),
 176         PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) PRO/1000 Network Connection"),
 177         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) PRO/1000 Network Connection"),
 178         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) PRO/1000 Network Connection"),
 179         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) PRO/1000 Network Connection"),
 180         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) PRO/1000 Network Connection"),
 181         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) PRO/1000 Network Connection"),
 182         PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) PRO/1000 Network Connection"),
 183         /* required last entry */
 184         PVID_END
 185 };
 186
 187 static pci_vendor_info_t igb_vendor_info_array[] =
 188 {
 189         /* Intel(R) PRO/1000 Network Connection - igb */
 190         PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 191         PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 192         PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 193         PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 194         PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 195         PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 196         PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 197         PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 198         PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 199         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 200         PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 201         PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 202         PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 203         PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 204         PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 205         PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 206         PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 207         PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 208         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 209         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 210         PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 211         PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 212         PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 213         PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 214         PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 215         PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 216         PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 217         PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 218         PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 219         PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 220         PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 221         PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 222         PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 223         PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 224         PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 225         PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 226         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 227         PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 228         PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"),
 229         /* required last entry */
 230         PVID_END
 231 };
 232
 233 /*********************************************************************
 234  *  Function prototypes
 235  *********************************************************************/
 236 static void     *em_register(device_t dev);
 237 static void     *igb_register(device_t dev);
 238 static int      em_if_attach_pre(if_ctx_t ctx);
 239 static int      em_if_attach_post(if_ctx_t ctx);
 240 static int      em_if_detach(if_ctx_t ctx);
 241 static int      em_if_shutdown(if_ctx_t ctx);
 242 static int      em_if_suspend(if_ctx_t ctx);
 243 static int      em_if_resume(if_ctx_t ctx);
 244
 245 static int      em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets);
 246 static int      em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets);
 247 static void     em_if_queues_free(if_ctx_t ctx);
 248
 249 static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
 250 static void     em_if_init(if_ctx_t ctx);
 251 static void     em_if_stop(if_ctx_t ctx);
 252 static void     em_if_media_status(if_ctx_t, struct ifmediareq *);
 253 static int      em_if_media_change(if_ctx_t ctx);
 254 static int      em_if_mtu_set(if_ctx_t ctx, uint32_t mtu);
 255 static void     em_if_timer(if_ctx_t ctx, uint16_t qid);
 256 static void     em_if_vlan_register(if_ctx_t ctx, u16 vtag);
 257 static void     em_if_vlan_unregister(if_ctx_t ctx, u16 vtag);
 258 static void     em_if_watchdog_reset(if_ctx_t ctx);
 259 static bool     em_if_needs_restart(if_ctx_t ctx, enum iflib_restart_event event);
 260
 261 static void     em_identify_hardware(if_ctx_t ctx);
 262 static int      em_allocate_pci_resources(if_ctx_t ctx);
 263 static void     em_free_pci_resources(if_ctx_t ctx);
 264 static void     em_reset(if_ctx_t ctx);
 265 static int      em_setup_interface(if_ctx_t ctx);
 266 static int      em_setup_msix(if_ctx_t ctx);
 267
 268 static void     em_initialize_transmit_unit(if_ctx_t ctx);
 269 static void     em_initialize_receive_unit(if_ctx_t ctx);
 270
 271 static void     em_if_intr_enable(if_ctx_t ctx);
 272 static void     em_if_intr_disable(if_ctx_t ctx);
 273 static void     igb_if_intr_enable(if_ctx_t ctx);
 274 static void     igb_if_intr_disable(if_ctx_t ctx);
 275 static int      em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 276 static int      em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
 277 static int      igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid);
 278 static int      igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid);
 279 static void     em_if_multi_set(if_ctx_t ctx);
 280 static void     em_if_update_admin_status(if_ctx_t ctx);
 281 static void     em_if_debug(if_ctx_t ctx);
 282 static void     em_update_stats_counters(struct adapter *);
 283 static void     em_add_hw_stats(struct adapter *adapter);
 284 static int      em_if_set_promisc(if_ctx_t ctx, int flags);
 285 static void     em_setup_vlan_hw_support(struct adapter *);
 286 static int      em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
 287 static void     em_print_nvm_info(struct adapter *);
 288 static int      em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 289 static int      em_get_rs(SYSCTL_HANDLER_ARGS);
 290 static void     em_print_debug_info(struct adapter *);
 291 static int      em_is_valid_ether_addr(u8 *);
 292 static int      em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
 293 static void     em_add_int_delay_sysctl(struct adapter *, const char *,
 294                     const char *, struct em_int_delay_info *, int, int);
 295 /* Management and WOL Support */
 296 static void     em_init_manageability(struct adapter *);
 297 static void     em_release_manageability(struct adapter *);
 298 static void     em_get_hw_control(struct adapter *);
 299 static void     em_release_hw_control(struct adapter *);
 300 static void     em_get_wakeup(if_ctx_t ctx);
 301 static void     em_enable_wakeup(if_ctx_t ctx);
 302 static int      em_enable_phy_wakeup(struct adapter *);
 303 static void     em_disable_aspm(struct adapter *);
 304
 305 int             em_intr(void *arg);
 306 static void     em_disable_promisc(if_ctx_t ctx);
 307
 308 /* MSI-X handlers */
 309 static int      em_if_msix_intr_assign(if_ctx_t, int);
 310 static int      em_msix_link(void *);
 311 static void     em_handle_link(void *context);
 312
 313 static void     em_enable_vectors_82574(if_ctx_t);
 314
 315 static int      em_set_flowcntl(SYSCTL_HANDLER_ARGS);
 316 static int      em_sysctl_eee(SYSCTL_HANDLER_ARGS);
 317 static void     em_if_led_func(if_ctx_t ctx, int onoff);
 318
 319 static int      em_get_regs(SYSCTL_HANDLER_ARGS);
 320
 321 static void     lem_smartspeed(struct adapter *adapter);
 322 static void     igb_configure_queues(struct adapter *adapter);
 323
 324
 325 /*********************************************************************
 326  *  FreeBSD Device Interface Entry Points
 327  *********************************************************************/
 328 static device_method_t em_methods[] = {
 329         /* Device interface */
 330         DEVMETHOD(device_register, em_register),
 331         DEVMETHOD(device_probe, iflib_device_probe),
 332         DEVMETHOD(device_attach, iflib_device_attach),
 333         DEVMETHOD(device_detach, iflib_device_detach),
 334         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 335         DEVMETHOD(device_suspend, iflib_device_suspend),
 336         DEVMETHOD(device_resume, iflib_device_resume),
 337         DEVMETHOD_END
 338 };
 339
 340 static device_method_t igb_methods[] = {
 341         /* Device interface */
 342         DEVMETHOD(device_register, igb_register),
 343         DEVMETHOD(device_probe, iflib_device_probe),
 344         DEVMETHOD(device_attach, iflib_device_attach),
 345         DEVMETHOD(device_detach, iflib_device_detach),
 346         DEVMETHOD(device_shutdown, iflib_device_shutdown),
 347         DEVMETHOD(device_suspend, iflib_device_suspend),
 348         DEVMETHOD(device_resume, iflib_device_resume),
 349         DEVMETHOD_END
 350 };
 351
 352
 353 static driver_t em_driver = {
 354         "em", em_methods, sizeof(struct adapter),
 355 };
 356
 357 static devclass_t em_devclass;
 358 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
 359
 360 MODULE_DEPEND(em, pci, 1, 1, 1);
 361 MODULE_DEPEND(em, ether, 1, 1, 1);
 362 MODULE_DEPEND(em, iflib, 1, 1, 1);
 363
 364 IFLIB_PNP_INFO(pci, em, em_vendor_info_array);
 365
 366 static driver_t igb_driver = {
 367         "igb", igb_methods, sizeof(struct adapter),
 368 };
 369
 370 static devclass_t igb_devclass;
 371 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0);
 372
 373 MODULE_DEPEND(igb, pci, 1, 1, 1);
 374 MODULE_DEPEND(igb, ether, 1, 1, 1);
 375 MODULE_DEPEND(igb, iflib, 1, 1, 1);
 376
 377 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array);
 378
 379 static device_method_t em_if_methods[] = {
 380         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 381         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 382         DEVMETHOD(ifdi_detach, em_if_detach),
 383         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 384         DEVMETHOD(ifdi_suspend, em_if_suspend),
 385         DEVMETHOD(ifdi_resume, em_if_resume),
 386         DEVMETHOD(ifdi_init, em_if_init),
 387         DEVMETHOD(ifdi_stop, em_if_stop),
 388         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 389         DEVMETHOD(ifdi_intr_enable, em_if_intr_enable),
 390         DEVMETHOD(ifdi_intr_disable, em_if_intr_disable),
 391         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 392         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 393         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 394         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 395         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 396         DEVMETHOD(ifdi_media_status, em_if_media_status),
 397         DEVMETHOD(ifdi_media_change, em_if_media_change),
 398         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 399         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 400         DEVMETHOD(ifdi_timer, em_if_timer),
 401         DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
 402         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 403         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 404         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 405         DEVMETHOD(ifdi_led_func, em_if_led_func),
 406         DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable),
 407         DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable),
 408         DEVMETHOD(ifdi_debug, em_if_debug),
 409         DEVMETHOD(ifdi_needs_restart, em_if_needs_restart),
 410         DEVMETHOD_END
 411 };
 412
 413 static driver_t em_if_driver = {
 414         "em_if", em_if_methods, sizeof(struct adapter)
 415 };
 416
 417 static device_method_t igb_if_methods[] = {
 418         DEVMETHOD(ifdi_attach_pre, em_if_attach_pre),
 419         DEVMETHOD(ifdi_attach_post, em_if_attach_post),
 420         DEVMETHOD(ifdi_detach, em_if_detach),
 421         DEVMETHOD(ifdi_shutdown, em_if_shutdown),
 422         DEVMETHOD(ifdi_suspend, em_if_suspend),
 423         DEVMETHOD(ifdi_resume, em_if_resume),
 424         DEVMETHOD(ifdi_init, em_if_init),
 425         DEVMETHOD(ifdi_stop, em_if_stop),
 426         DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign),
 427         DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable),
 428         DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable),
 429         DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc),
 430         DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc),
 431         DEVMETHOD(ifdi_queues_free, em_if_queues_free),
 432         DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status),
 433         DEVMETHOD(ifdi_multi_set, em_if_multi_set),
 434         DEVMETHOD(ifdi_media_status, em_if_media_status),
 435         DEVMETHOD(ifdi_media_change, em_if_media_change),
 436         DEVMETHOD(ifdi_mtu_set, em_if_mtu_set),
 437         DEVMETHOD(ifdi_promisc_set, em_if_set_promisc),
 438         DEVMETHOD(ifdi_timer, em_if_timer),
 439         DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset),
 440         DEVMETHOD(ifdi_vlan_register, em_if_vlan_register),
 441         DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister),
 442         DEVMETHOD(ifdi_get_counter, em_if_get_counter),
 443         DEVMETHOD(ifdi_led_func, em_if_led_func),
 444         DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable),
 445         DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable),
 446         DEVMETHOD(ifdi_debug, em_if_debug),
 447         DEVMETHOD(ifdi_needs_restart, em_if_needs_restart),
 448         DEVMETHOD_END
 449 };
 450
 451 static driver_t igb_if_driver = {
 452         "igb_if", igb_if_methods, sizeof(struct adapter)
 453 };
 454
 455 /*********************************************************************
 456  *  Tunable default values.
 457  *********************************************************************/
 458
 459 #define EM_TICKS_TO_USECS(ticks)        ((1024 * (ticks) + 500) / 1000)
 460 #define EM_USECS_TO_TICKS(usecs)        ((1000 * (usecs) + 512) / 1024)
 461
 462 #define MAX_INTS_PER_SEC        8000
 463 #define DEFAULT_ITR             (1000000000/(MAX_INTS_PER_SEC * 256))
 464
 465 /* Allow common code without TSO */
 466 #ifndef CSUM_TSO
 467 #define CSUM_TSO        0
 468 #endif
 469
 470 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
 471     "EM driver parameters");
 472
 473 static int em_disable_crc_stripping = 0;
 474 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
 475     &em_disable_crc_stripping, 0, "Disable CRC Stripping");
 476
 477 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
 478 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
 479 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
 480     0, "Default transmit interrupt delay in usecs");
 481 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
 482     0, "Default receive interrupt delay in usecs");
 483
 484 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
 485 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
 486 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
 487     &em_tx_abs_int_delay_dflt, 0,
 488     "Default transmit interrupt delay limit in usecs");
 489 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
 490     &em_rx_abs_int_delay_dflt, 0,
 491     "Default receive interrupt delay limit in usecs");
 492
 493 static int em_smart_pwr_down = FALSE;
 494 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
 495     0, "Set to true to leave smart power down enabled on newer adapters");
 496
 497 /* Controls whether promiscuous also shows bad packets */
 498 static int em_debug_sbp = TRUE;
 499 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
 500     "Show bad packets in promiscuous mode");
 501
 502 /* How many packets rxeof tries to clean at a time */
 503 static int em_rx_process_limit = 100;
 504 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
 505     &em_rx_process_limit, 0,
 506     "Maximum number of received packets to process "
 507     "at a time, -1 means unlimited");
 508
 509 /* Energy efficient ethernet - default to OFF */
 510 static int eee_setting = 1;
 511 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
 512     "Enable Energy Efficient Ethernet");
 513
 514 /*
 515 ** Tuneable Interrupt rate
 516 */
 517 static int em_max_interrupt_rate = 8000;
 518 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
 519     &em_max_interrupt_rate, 0, "Maximum interrupts per second");
 520
 521
 522
 523 /* Global used in WOL setup with multiport cards */
 524 static int global_quad_port_a = 0;
 525
 526 extern struct if_txrx igb_txrx;
 527 extern struct if_txrx em_txrx;
 528 extern struct if_txrx lem_txrx;
 529
 530 static struct if_shared_ctx em_sctx_init = {
 531         .isc_magic = IFLIB_MAGIC,
 532         .isc_q_align = PAGE_SIZE,
 533         .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 534         .isc_tx_maxsegsize = PAGE_SIZE,
 535         .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 536         .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
 537         .isc_rx_maxsize = MJUM9BYTES,
 538         .isc_rx_nsegments = 1,
 539         .isc_rx_maxsegsize = MJUM9BYTES,
 540         .isc_nfl = 1,
 541         .isc_nrxqs = 1,
 542         .isc_ntxqs = 1,
 543         .isc_admin_intrcnt = 1,
 544         .isc_vendor_info = em_vendor_info_array,
 545         .isc_driver_version = em_driver_version,
 546         .isc_driver = &em_if_driver,
 547         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 548
 549         .isc_nrxd_min = {EM_MIN_RXD},
 550         .isc_ntxd_min = {EM_MIN_TXD},
 551         .isc_nrxd_max = {EM_MAX_RXD},
 552         .isc_ntxd_max = {EM_MAX_TXD},
 553         .isc_nrxd_default = {EM_DEFAULT_RXD},
 554         .isc_ntxd_default = {EM_DEFAULT_TXD},
 555 };
 556
 557 if_shared_ctx_t em_sctx = &em_sctx_init;
 558
 559 static struct if_shared_ctx igb_sctx_init = {
 560         .isc_magic = IFLIB_MAGIC,
 561         .isc_q_align = PAGE_SIZE,
 562         .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 563         .isc_tx_maxsegsize = PAGE_SIZE,
 564         .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header),
 565         .isc_tso_maxsegsize = EM_TSO_SEG_SIZE,
 566         .isc_rx_maxsize = MJUM9BYTES,
 567         .isc_rx_nsegments = 1,
 568         .isc_rx_maxsegsize = MJUM9BYTES,
 569         .isc_nfl = 1,
 570         .isc_nrxqs = 1,
 571         .isc_ntxqs = 1,
 572         .isc_admin_intrcnt = 1,
 573         .isc_vendor_info = igb_vendor_info_array,
 574         .isc_driver_version = em_driver_version,
 575         .isc_driver = &igb_if_driver,
 576         .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
 577
 578         .isc_nrxd_min = {EM_MIN_RXD},
 579         .isc_ntxd_min = {EM_MIN_TXD},
 580         .isc_nrxd_max = {IGB_MAX_RXD},
 581         .isc_ntxd_max = {IGB_MAX_TXD},
 582         .isc_nrxd_default = {EM_DEFAULT_RXD},
 583         .isc_ntxd_default = {EM_DEFAULT_TXD},
 584 };
 585
 586 if_shared_ctx_t igb_sctx = &igb_sctx_init;
 587
 588 /*****************************************************************
 589  *
 590  * Dump Registers
 591  *
 592  ****************************************************************/
 593 #define IGB_REGS_LEN 739
 594
 595 static int em_get_regs(SYSCTL_HANDLER_ARGS)
 596 {
 597         struct adapter *adapter = (struct adapter *)arg1;
 598         struct e1000_hw *hw = &adapter->hw;
 599         struct sbuf *sb;
 600         u32 *regs_buff;
 601         int rc;
 602
 603         regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK);
 604         memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32));
 605
 606         rc = sysctl_wire_old_buffer(req, 0);
 607         MPASS(rc == 0);
 608         if (rc != 0) {
 609                 free(regs_buff, M_DEVBUF);
 610                 return (rc);
 611         }
 612
 613         sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
 614         MPASS(sb != NULL);
 615         if (sb == NULL) {
 616                 free(regs_buff, M_DEVBUF);
 617                 return (ENOMEM);
 618         }
 619
 620         /* General Registers */
 621         regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);
 622         regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);
 623         regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);
 624         regs_buff[3] = E1000_READ_REG(hw, E1000_ICR);
 625         regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL);
 626         regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0));
 627         regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0));
 628         regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0));
 629         regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0));
 630         regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0));
 631         regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0));
 632         regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL);
 633         regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0));
 634         regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0));
 635         regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0));
 636         regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0));
 637         regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0));
 638         regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0));
 639         regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH);
 640         regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT);
 641         regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS);
 642         regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC);
 643
 644         sbuf_printf(sb, "General Registers\n");
 645         sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
 646         sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
 647         sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]);
 648
 649         sbuf_printf(sb, "Interrupt Registers\n");
 650         sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
 651
 652         sbuf_printf(sb, "RX Registers\n");
 653         sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
 654         sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
 655         sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
 656         sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
 657         sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
 658         sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
 659         sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
 660
 661         sbuf_printf(sb, "TX Registers\n");
 662         sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
 663         sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
 664         sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
 665         sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
 666         sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
 667         sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
 668         sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
 669         sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
 670         sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
 671         sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
 672         sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
 673
 674         free(regs_buff, M_DEVBUF);
 675
 676 #ifdef DUMP_DESCS
 677         {
 678                 if_softc_ctx_t scctx = adapter->shared;
 679                 struct rx_ring *rxr = &rx_que->rxr;
 680                 struct tx_ring *txr = &tx_que->txr;
 681                 int ntxd = scctx->isc_ntxd[0];
 682                 int nrxd = scctx->isc_nrxd[0];
 683                 int j;
 684
 685         for (j = 0; j < nrxd; j++) {
 686                 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
 687                 u32 length =  le32toh(rxr->rx_base[j].wb.upper.length);
 688                 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 "  Error:%d  Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
 689         }
 690
 691         for (j = 0; j < min(ntxd, 256); j++) {
 692                 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
 693
 694                 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x  eop: %d DD=%d\n",
 695                             j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
 696                             buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
 697
 698         }
 699         }
 700 #endif
 701
 702         rc = sbuf_finish(sb);
 703         sbuf_delete(sb);
 704         return(rc);
 705 }
 706
 707 static void *
 708 em_register(device_t dev)
 709 {
 710         return (em_sctx);
 711 }
 712
 713 static void *
 714 igb_register(device_t dev)
 715 {
 716         return (igb_sctx);
 717 }
 718
 719 static int
 720 em_set_num_queues(if_ctx_t ctx)
 721 {
 722         struct adapter *adapter = iflib_get_softc(ctx);
 723         int maxqueues;
 724
 725         /* Sanity check based on HW */
 726         switch (adapter->hw.mac.type) {
 727         case e1000_82576:
 728         case e1000_82580:
 729         case e1000_i350:
 730         case e1000_i354:
 731                 maxqueues = 8;
 732                 break;
 733         case e1000_i210:
 734         case e1000_82575:
 735                 maxqueues = 4;
 736                 break;
 737         case e1000_i211:
 738         case e1000_82574:
 739                 maxqueues = 2;
 740                 break;
 741         default:
 742                 maxqueues = 1;
 743                 break;
 744         }
 745
 746         return (maxqueues);
 747 }
 748
 749 #define LEM_CAPS                                                        \
 750     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 751     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER
 752
 753 #define EM_CAPS                                                         \
 754     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 755     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 |  \
 756     IFCAP_LRO | IFCAP_VLAN_HWTSO
 757
 758 #define IGB_CAPS                                                        \
 759     IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |              \
 760     IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 |  \
 761     IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\
 762     IFCAP_TSO6
 763
 764 /*********************************************************************
 765  *  Device initialization routine
 766  *
 767  *  The attach entry point is called when the driver is being loaded.
 768  *  This routine identifies the type of hardware, allocates all resources
 769  *  and initializes the hardware.
 770  *
 771  *  return 0 on success, positive on failure
 772  *********************************************************************/
 773 static int
 774 em_if_attach_pre(if_ctx_t ctx)
 775 {
 776         struct adapter *adapter;
 777         if_softc_ctx_t scctx;
 778         device_t dev;
 779         struct e1000_hw *hw;
 780         int error = 0;
 781
 782         INIT_DEBUGOUT("em_if_attach_pre: begin");
 783         dev = iflib_get_dev(ctx);
 784         adapter = iflib_get_softc(ctx);
 785
 786         adapter->ctx = adapter->osdep.ctx = ctx;
 787         adapter->dev = adapter->osdep.dev = dev;
 788         scctx = adapter->shared = iflib_get_softc_ctx(ctx);
 789         adapter->media = iflib_get_media(ctx);
 790         hw = &adapter->hw;
 791
 792         adapter->tx_process_limit = scctx->isc_ntxd[0];
 793
 794         /* SYSCTL stuff */
 795         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 796             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 797             OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
 798             adapter, 0, em_sysctl_nvm_info, "I", "NVM Information");
 799
 800         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 801             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 802             OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
 803             adapter, 0, em_sysctl_debug_info, "I", "Debug Information");
 804
 805         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 806             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 807             OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
 808             adapter, 0, em_set_flowcntl, "I", "Flow Control");
 809
 810         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 811             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 812             OID_AUTO, "reg_dump",
 813             CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 0,
 814             em_get_regs, "A", "Dump Registers");
 815
 816         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 817             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 818             OID_AUTO, "rs_dump",
 819             CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, adapter, 0,
 820             em_get_rs, "I", "Dump RS indexes");
 821
 822         /* Determine hardware and mac info */
 823         em_identify_hardware(ctx);
 824
 825         scctx->isc_tx_nsegments = EM_MAX_SCATTER;
 826         scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
 827         if (bootverbose)
 828                 device_printf(dev, "attach_pre capping queues at %d\n",
 829                     scctx->isc_ntxqsets_max);
 830
 831         if (hw->mac.type >= igb_mac_min) {
 832                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
 833                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
 834                 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
 835                 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
 836                 scctx->isc_txrx = &igb_txrx;
 837                 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
 838                 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 839                 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 840                 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS;
 841                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO |
 842                      CSUM_IP6_TCP | CSUM_IP6_UDP;
 843                 if (hw->mac.type != e1000_82575)
 844                         scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
 845                 /*
 846                 ** Some new devices, as with ixgbe, now may
 847                 ** use a different BAR, so we need to keep
 848                 ** track of which is used.
 849                 */
 850                 scctx->isc_msix_bar = pci_msix_table_bar(dev);
 851         } else if (hw->mac.type >= em_mac_min) {
 852                 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 853                 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
 854                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 855                 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
 856                 scctx->isc_txrx = &em_txrx;
 857                 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
 858                 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
 859                 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
 860                 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS;
 861                 /*
 862                  * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO}
 863                  * by default as we don't have workarounds for all associated
 864                  * silicon errata.  E. g., with several MACs such as 82573E,
 865                  * TSO only works at Gigabit speed and otherwise can cause the
 866                  * hardware to hang (which also would be next to impossible to
 867                  * work around given that already queued TSO-using descriptors
 868                  * would need to be flushed and vlan(4) reconfigured at runtime
 869                  * in case of a link speed change).  Moreover, MACs like 82579
 870                  * still can hang at Gigabit even with all publicly documented
 871                  * TSO workarounds implemented.  Generally, the penality of
 872                  * these workarounds is rather high and may involve copying
 873                  * mbuf data around so advantages of TSO lapse.  Still, TSO may
 874                  * work for a few MACs of this class - at least when sticking
 875                  * with Gigabit - in which case users may enable TSO manually.
 876                  */
 877                 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
 878                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO;
 879                 /*
 880                  * We support MSI-X with 82574 only, but indicate to iflib(4)
 881                  * that it shall give MSI at least a try with other devices.
 882                  */
 883                 if (hw->mac.type == e1000_82574) {
 884                         scctx->isc_msix_bar = pci_msix_table_bar(dev);;
 885                 } else {
 886                         scctx->isc_msix_bar = -1;
 887                         scctx->isc_disable_msix = 1;
 888                 }
 889         } else {
 890                 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
 891                 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
 892                 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
 893                 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
 894                 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP;
 895                 scctx->isc_txrx = &lem_txrx;
 896                 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS;
 897                 if (hw->mac.type < e1000_82543)
 898                         scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
 899                 /* INTx only */
 900                 scctx->isc_msix_bar = 0;
 901         }
 902
 903         /* Setup PCI resources */
 904         if (em_allocate_pci_resources(ctx)) {
 905                 device_printf(dev, "Allocation of PCI resources failed\n");
 906                 error = ENXIO;
 907                 goto err_pci;
 908         }
 909
 910         /*
 911         ** For ICH8 and family we need to
 912         ** map the flash memory, and this
 913         ** must happen after the MAC is
 914         ** identified
 915         */
 916         if ((hw->mac.type == e1000_ich8lan) ||
 917             (hw->mac.type == e1000_ich9lan) ||
 918             (hw->mac.type == e1000_ich10lan) ||
 919             (hw->mac.type == e1000_pchlan) ||
 920             (hw->mac.type == e1000_pch2lan) ||
 921             (hw->mac.type == e1000_pch_lpt)) {
 922                 int rid = EM_BAR_TYPE_FLASH;
 923                 adapter->flash = bus_alloc_resource_any(dev,
 924                     SYS_RES_MEMORY, &rid, RF_ACTIVE);
 925                 if (adapter->flash == NULL) {
 926                         device_printf(dev, "Mapping of Flash failed\n");
 927                         error = ENXIO;
 928                         goto err_pci;
 929                 }
 930                 /* This is used in the shared code */
 931                 hw->flash_address = (u8 *)adapter->flash;
 932                 adapter->osdep.flash_bus_space_tag =
 933                     rman_get_bustag(adapter->flash);
 934                 adapter->osdep.flash_bus_space_handle =
 935                     rman_get_bushandle(adapter->flash);
 936         }
 937         /*
 938         ** In the new SPT device flash is not  a
 939         ** separate BAR, rather it is also in BAR0,
 940         ** so use the same tag and an offset handle for the
 941         ** FLASH read/write macros in the shared code.
 942         */
 943         else if (hw->mac.type >= e1000_pch_spt) {
 944                 adapter->osdep.flash_bus_space_tag =
 945                     adapter->osdep.mem_bus_space_tag;
 946                 adapter->osdep.flash_bus_space_handle =
 947                     adapter->osdep.mem_bus_space_handle
 948                     + E1000_FLASH_BASE_ADDR;
 949         }
 950
 951         /* Do Shared Code initialization */
 952         error = e1000_setup_init_funcs(hw, TRUE);
 953         if (error) {
 954                 device_printf(dev, "Setup of Shared code failed, error %d\n",
 955                     error);
 956                 error = ENXIO;
 957                 goto err_pci;
 958         }
 959
 960         em_setup_msix(ctx);
 961         e1000_get_bus_info(hw);
 962
 963         /* Set up some sysctls for the tunable interrupt delays */
 964         em_add_int_delay_sysctl(adapter, "rx_int_delay",
 965             "receive interrupt delay in usecs", &adapter->rx_int_delay,
 966             E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
 967         em_add_int_delay_sysctl(adapter, "tx_int_delay",
 968             "transmit interrupt delay in usecs", &adapter->tx_int_delay,
 969             E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
 970         em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
 971             "receive interrupt delay limit in usecs",
 972             &adapter->rx_abs_int_delay,
 973             E1000_REGISTER(hw, E1000_RADV),
 974             em_rx_abs_int_delay_dflt);
 975         em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
 976             "transmit interrupt delay limit in usecs",
 977             &adapter->tx_abs_int_delay,
 978             E1000_REGISTER(hw, E1000_TADV),
 979             em_tx_abs_int_delay_dflt);
 980         em_add_int_delay_sysctl(adapter, "itr",
 981             "interrupt delay limit in usecs/4",
 982             &adapter->tx_itr,
 983             E1000_REGISTER(hw, E1000_ITR),
 984             DEFAULT_ITR);
 985
 986         hw->mac.autoneg = DO_AUTO_NEG;
 987         hw->phy.autoneg_wait_to_complete = FALSE;
 988         hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 989
 990         if (hw->mac.type < em_mac_min) {
 991                 e1000_init_script_state_82541(hw, TRUE);
 992                 e1000_set_tbi_compatibility_82543(hw, TRUE);
 993         }
 994         /* Copper options */
 995         if (hw->phy.media_type == e1000_media_type_copper) {
 996                 hw->phy.mdix = AUTO_ALL_MODES;
 997                 hw->phy.disable_polarity_correction = FALSE;
 998                 hw->phy.ms_type = EM_MASTER_SLAVE;
 999         }
1000
1001         /*
1002          * Set the frame limits assuming
1003          * standard ethernet sized frames.
1004          */
1005         scctx->isc_max_frame_size = hw->mac.max_frame_size =
1006             ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
1007
1008         /*
1009          * This controls when hardware reports transmit completion
1010          * status.
1011          */
1012         hw->mac.report_tx_early = 1;
1013
1014         /* Allocate multicast array memory. */
1015         adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN *
1016             MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
1017         if (adapter->mta == NULL) {
1018                 device_printf(dev, "Can not allocate multicast setup array\n");
1019                 error = ENOMEM;
1020                 goto err_late;
1021         }
1022
1023         /* Check SOL/IDER usage */
1024         if (e1000_check_reset_block(hw))
1025                 device_printf(dev, "PHY reset is blocked"
1026                               " due to SOL/IDER session.\n");
1027
1028         /* Sysctl for setting Energy Efficient Ethernet */
1029         hw->dev_spec.ich8lan.eee_disable = eee_setting;
1030         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1031             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1032             OID_AUTO, "eee_control",
1033             CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
1034             adapter, 0, em_sysctl_eee, "I",
1035             "Disable Energy Efficient Ethernet");
1036
1037         /*
1038         ** Start from a known state, this is
1039         ** important in reading the nvm and
1040         ** mac from that.
1041         */
1042         e1000_reset_hw(hw);
1043
1044         /* Make sure we have a good EEPROM before we read from it */
1045         if (e1000_validate_nvm_checksum(hw) < 0) {
1046                 /*
1047                 ** Some PCI-E parts fail the first check due to
1048                 ** the link being in sleep state, call it again,
1049                 ** if it fails a second time its a real issue.
1050                 */
1051                 if (e1000_validate_nvm_checksum(hw) < 0) {
1052                         device_printf(dev,
1053                             "The EEPROM Checksum Is Not Valid\n");
1054                         error = EIO;
1055                         goto err_late;
1056                 }
1057         }
1058
1059         /* Copy the permanent MAC address out of the EEPROM */
1060         if (e1000_read_mac_addr(hw) < 0) {
1061                 device_printf(dev, "EEPROM read error while reading MAC"
1062                               " address\n");
1063                 error = EIO;
1064                 goto err_late;
1065         }
1066
1067         if (!em_is_valid_ether_addr(hw->mac.addr)) {
1068                 device_printf(dev, "Invalid MAC address\n");
1069                 error = EIO;
1070                 goto err_late;
1071         }
1072
1073         /* Disable ULP support */
1074         e1000_disable_ulp_lpt_lp(hw, TRUE);
1075
1076         /*
1077          * Get Wake-on-Lan and Management info for later use
1078          */
1079         em_get_wakeup(ctx);
1080
1081         /* Enable only WOL MAGIC by default */
1082         scctx->isc_capenable &= ~IFCAP_WOL;
1083         if (adapter->wol != 0)
1084                 scctx->isc_capenable |= IFCAP_WOL_MAGIC;
1085
1086         iflib_set_mac(ctx, hw->mac.addr);
1087
1088         return (0);
1089
1090 err_late:
1091         em_release_hw_control(adapter);
1092 err_pci:
1093         em_free_pci_resources(ctx);
1094         free(adapter->mta, M_DEVBUF);
1095
1096         return (error);
1097 }
1098
1099 static int
1100 em_if_attach_post(if_ctx_t ctx)
1101 {
1102         struct adapter *adapter = iflib_get_softc(ctx);
1103         struct e1000_hw *hw = &adapter->hw;
1104         int error = 0;
1105
1106         /* Setup OS specific network interface */
1107         error = em_setup_interface(ctx);
1108         if (error != 0) {
1109                 device_printf(adapter->dev, "Interface setup failed: %d\n", error);
1110                 goto err_late;
1111         }
1112
1113         em_reset(ctx);
1114
1115         /* Initialize statistics */
1116         em_update_stats_counters(adapter);
1117         hw->mac.get_link_status = 1;
1118         em_if_update_admin_status(ctx);
1119         em_add_hw_stats(adapter);
1120
1121         /* Non-AMT based hardware can now take control from firmware */
1122         if (adapter->has_manage && !adapter->has_amt)
1123                 em_get_hw_control(adapter);
1124
1125         INIT_DEBUGOUT("em_if_attach_post: end");
1126
1127         return (0);
1128
1129 err_late:
1130         /* upon attach_post() error, iflib calls _if_detach() to free resources. */
1131         return (error);
1132 }
1133
1134 /*********************************************************************
1135  *  Device removal routine
1136  *
1137  *  The detach entry point is called when the driver is being removed.
1138  *  This routine stops the adapter and deallocates all the resources
1139  *  that were allocated for driver operation.
1140  *
1141  *  return 0 on success, positive on failure
1142  *********************************************************************/
1143 static int
1144 em_if_detach(if_ctx_t ctx)
1145 {
1146         struct adapter  *adapter = iflib_get_softc(ctx);
1147
1148         INIT_DEBUGOUT("em_if_detach: begin");
1149
1150         e1000_phy_hw_reset(&adapter->hw);
1151
1152         em_release_manageability(adapter);
1153         em_release_hw_control(adapter);
1154         em_free_pci_resources(ctx);
1155         free(adapter->mta, M_DEVBUF);
1156         adapter->mta = NULL;
1157
1158         return (0);
1159 }
1160
1161 /*********************************************************************
1162  *
1163  *  Shutdown entry point
1164  *
1165  **********************************************************************/
1166
1167 static int
1168 em_if_shutdown(if_ctx_t ctx)
1169 {
1170         return em_if_suspend(ctx);
1171 }
1172
1173 /*
1174  * Suspend/resume device methods.
1175  */
1176 static int
1177 em_if_suspend(if_ctx_t ctx)
1178 {
1179         struct adapter *adapter = iflib_get_softc(ctx);
1180
1181         em_release_manageability(adapter);
1182         em_release_hw_control(adapter);
1183         em_enable_wakeup(ctx);
1184         return (0);
1185 }
1186
1187 static int
1188 em_if_resume(if_ctx_t ctx)
1189 {
1190         struct adapter *adapter = iflib_get_softc(ctx);
1191
1192         if (adapter->hw.mac.type == e1000_pch2lan)
1193                 e1000_resume_workarounds_pchlan(&adapter->hw);
1194         em_if_init(ctx);
1195         em_init_manageability(adapter);
1196
1197         return(0);
1198 }
1199
1200 static int
1201 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
1202 {
1203         int max_frame_size;
1204         struct adapter *adapter = iflib_get_softc(ctx);
1205         if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1206
1207         IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
1208
1209         switch (adapter->hw.mac.type) {
1210         case e1000_82571:
1211         case e1000_82572:
1212         case e1000_ich9lan:
1213         case e1000_ich10lan:
1214         case e1000_pch2lan:
1215         case e1000_pch_lpt:
1216         case e1000_pch_spt:
1217         case e1000_pch_cnp:
1218         case e1000_82574:
1219         case e1000_82583:
1220         case e1000_80003es2lan:
1221                 /* 9K Jumbo Frame size */
1222                 max_frame_size = 9234;
1223                 break;
1224         case e1000_pchlan:
1225                 max_frame_size = 4096;
1226                 break;
1227         case e1000_82542:
1228         case e1000_ich8lan:
1229                 /* Adapters that do not support jumbo frames */
1230                 max_frame_size = ETHER_MAX_LEN;
1231                 break;
1232         default:
1233                 if (adapter->hw.mac.type >= igb_mac_min)
1234                         max_frame_size = 9234;
1235                 else /* lem */
1236                         max_frame_size = MAX_JUMBO_FRAME_SIZE;
1237         }
1238         if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1239                 return (EINVAL);
1240         }
1241
1242         scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size =
1243             mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1244         return (0);
1245 }
1246
1247 /*********************************************************************
1248  *  Init entry point
1249  *
1250  *  This routine is used in two ways. It is used by the stack as
1251  *  init entry point in network interface structure. It is also used
1252  *  by the driver as a hw/sw initialization routine to get to a
1253  *  consistent state.
1254  *
1255  **********************************************************************/
1256 static void
1257 em_if_init(if_ctx_t ctx)
1258 {
1259         struct adapter *adapter = iflib_get_softc(ctx);
1260         if_softc_ctx_t scctx = adapter->shared;
1261         struct ifnet *ifp = iflib_get_ifp(ctx);
1262         struct em_tx_queue *tx_que;
1263         int i;
1264
1265         INIT_DEBUGOUT("em_if_init: begin");
1266
1267         /* Get the latest mac address, User can use a LAA */
1268         bcopy(if_getlladdr(ifp), adapter->hw.mac.addr,
1269             ETHER_ADDR_LEN);
1270
1271         /* Put the address into the Receive Address Array */
1272         e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1273
1274         /*
1275          * With the 82571 adapter, RAR[0] may be overwritten
1276          * when the other port is reset, we make a duplicate
1277          * in RAR[14] for that eventuality, this assures
1278          * the interface continues to function.
1279          */
1280         if (adapter->hw.mac.type == e1000_82571) {
1281                 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1282                 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1283                     E1000_RAR_ENTRIES - 1);
1284         }
1285
1286
1287         /* Initialize the hardware */
1288         em_reset(ctx);
1289         em_if_update_admin_status(ctx);
1290
1291         for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) {
1292                 struct tx_ring *txr = &tx_que->txr;
1293
1294                 txr->tx_rs_cidx = txr->tx_rs_pidx;
1295
1296                 /* Initialize the last processed descriptor to be the end of
1297                  * the ring, rather than the start, so that we avoid an
1298                  * off-by-one error when calculating how many descriptors are
1299                  * done in the credits_update function.
1300                  */
1301                 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
1302         }
1303
1304         /* Setup VLAN support, basic and offload if available */
1305         E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1306
1307         /* Clear bad data from Rx FIFOs */
1308         if (adapter->hw.mac.type >= igb_mac_min)
1309                 e1000_rx_fifo_flush_82575(&adapter->hw);
1310
1311         /* Configure for OS presence */
1312         em_init_manageability(adapter);
1313
1314         /* Prepare transmit descriptors and buffers */
1315         em_initialize_transmit_unit(ctx);
1316
1317         /* Setup Multicast table */
1318         em_if_multi_set(ctx);
1319
1320         adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx);
1321         em_initialize_receive_unit(ctx);
1322
1323         /* Use real VLAN Filter support? */
1324         if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1325                 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
1326                         /* Use real VLAN Filter support */
1327                         em_setup_vlan_hw_support(adapter);
1328                 else {
1329                         u32 ctrl;
1330                         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1331                         ctrl |= E1000_CTRL_VME;
1332                         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1333                 }
1334         } else {
1335                 u32 ctrl;
1336                 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1337                 ctrl &= ~E1000_CTRL_VME;
1338                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1339         }
1340
1341         /* Don't lose promiscuous settings */
1342         em_if_set_promisc(ctx, if_getflags(ifp));
1343         e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1344
1345         /* MSI-X configuration for 82574 */
1346         if (adapter->hw.mac.type == e1000_82574) {
1347                 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1348
1349                 tmp |= E1000_CTRL_EXT_PBA_CLR;
1350                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1351                 /* Set the IVAR - interrupt vector routing. */
1352                 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars);
1353         } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
1354                 igb_configure_queues(adapter);
1355
1356         /* this clears any pending interrupts */
1357         E1000_READ_REG(&adapter->hw, E1000_ICR);
1358         E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC);
1359
1360         /* AMT based hardware can now take control from firmware */
1361         if (adapter->has_manage && adapter->has_amt)
1362                 em_get_hw_control(adapter);
1363
1364         /* Set Energy Efficient Ethernet */
1365         if (adapter->hw.mac.type >= igb_mac_min &&
1366             adapter->hw.phy.media_type == e1000_media_type_copper) {
1367                 if (adapter->hw.mac.type == e1000_i354)
1368                         e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
1369                 else
1370                         e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
1371         }
1372 }
1373
1374 /*********************************************************************
1375  *
1376  *  Fast Legacy/MSI Combined Interrupt Service routine
1377  *
1378  *********************************************************************/
1379 int
1380 em_intr(void *arg)
1381 {
1382         struct adapter *adapter = arg;
1383         if_ctx_t ctx = adapter->ctx;
1384         u32 reg_icr;
1385
1386         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1387
1388         /* Hot eject? */
1389         if (reg_icr == 0xffffffff)
1390                 return FILTER_STRAY;
1391
1392         /* Definitely not our interrupt. */
1393         if (reg_icr == 0x0)
1394                 return FILTER_STRAY;
1395
1396         /*
1397          * Starting with the 82571 chip, bit 31 should be used to
1398          * determine whether the interrupt belongs to us.
1399          */
1400         if (adapter->hw.mac.type >= e1000_82571 &&
1401             (reg_icr & E1000_ICR_INT_ASSERTED) == 0)
1402                 return FILTER_STRAY;
1403
1404         /*
1405          * Only MSI-X interrupts have one-shot behavior by taking advantage
1406          * of the EIAC register.  Thus, explicitly disable interrupts.  This
1407          * also works around the MSI message reordering errata on certain
1408          * systems.
1409          */
1410         IFDI_INTR_DISABLE(ctx);
1411
1412         /* Link status change */
1413         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))
1414                 em_handle_link(ctx);
1415
1416         if (reg_icr & E1000_ICR_RXO)
1417                 adapter->rx_overruns++;
1418
1419         return (FILTER_SCHEDULE_THREAD);
1420 }
1421
1422 static int
1423 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1424 {
1425         struct adapter *adapter = iflib_get_softc(ctx);
1426         struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1427
1428         E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims);
1429         return (0);
1430 }
1431
1432 static int
1433 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1434 {
1435         struct adapter *adapter = iflib_get_softc(ctx);
1436         struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1437
1438         E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims);
1439         return (0);
1440 }
1441
1442 static int
1443 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1444 {
1445         struct adapter *adapter = iflib_get_softc(ctx);
1446         struct em_rx_queue *rxq = &adapter->rx_queues[rxqid];
1447
1448         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims);
1449         return (0);
1450 }
1451
1452 static int
1453 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1454 {
1455         struct adapter *adapter = iflib_get_softc(ctx);
1456         struct em_tx_queue *txq = &adapter->tx_queues[txqid];
1457
1458         E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims);
1459         return (0);
1460 }
1461
1462 /*********************************************************************
1463  *
1464  *  MSI-X RX Interrupt Service routine
1465  *
1466  **********************************************************************/
1467 static int
1468 em_msix_que(void *arg)
1469 {
1470         struct em_rx_queue *que = arg;
1471
1472         ++que->irqs;
1473
1474         return (FILTER_SCHEDULE_THREAD);
1475 }
1476
1477 /*********************************************************************
1478  *
1479  *  MSI-X Link Fast Interrupt Service routine
1480  *
1481  **********************************************************************/
1482 static int
1483 em_msix_link(void *arg)
1484 {
1485         struct adapter *adapter = arg;
1486         u32 reg_icr;
1487
1488         ++adapter->link_irq;
1489         MPASS(adapter->hw.back != NULL);
1490         reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1491
1492         if (reg_icr & E1000_ICR_RXO)
1493                 adapter->rx_overruns++;
1494
1495         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1496                 em_handle_link(adapter->ctx);
1497         } else if (adapter->hw.mac.type == e1000_82574) {
1498                 /* Only re-arm 82574 if em_if_update_admin_status() won't. */
1499                 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK |
1500                     E1000_IMS_LSC);
1501         }
1502
1503         if (adapter->hw.mac.type == e1000_82574) {
1504                 /*
1505                  * Because we must read the ICR for this interrupt it may
1506                  * clear other causes using autoclear, for this reason we
1507                  * simply create a soft interrupt for all these vectors.
1508                  */
1509                 if (reg_icr)
1510                         E1000_WRITE_REG(&adapter->hw, E1000_ICS, adapter->ims);
1511         } else {
1512                 /* Re-arm unconditionally */
1513                 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC);
1514                 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask);
1515         }
1516
1517         return (FILTER_HANDLED);
1518 }
1519
1520 static void
1521 em_handle_link(void *context)
1522 {
1523         if_ctx_t ctx = context;
1524         struct adapter *adapter = iflib_get_softc(ctx);
1525
1526         adapter->hw.mac.get_link_status = 1;
1527         iflib_admin_intr_deferred(ctx);
1528 }
1529
1530 /*********************************************************************
1531  *
1532  *  Media Ioctl callback
1533  *
1534  *  This routine is called whenever the user queries the status of
1535  *  the interface using ifconfig.
1536  *
1537  **********************************************************************/
1538 static void
1539 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1540 {
1541         struct adapter *adapter = iflib_get_softc(ctx);
1542         u_char fiber_type = IFM_1000_SX;
1543
1544         INIT_DEBUGOUT("em_if_media_status: begin");
1545
1546         iflib_admin_intr_deferred(ctx);
1547
1548         ifmr->ifm_status = IFM_AVALID;
1549         ifmr->ifm_active = IFM_ETHER;
1550
1551         if (!adapter->link_active) {
1552                 return;
1553         }
1554
1555         ifmr->ifm_status |= IFM_ACTIVE;
1556
1557         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) ||
1558             (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1559                 if (adapter->hw.mac.type == e1000_82545)
1560                         fiber_type = IFM_1000_LX;
1561                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1562         } else {
1563                 switch (adapter->link_speed) {
1564                 case 10:
1565                         ifmr->ifm_active |= IFM_10_T;
1566                         break;
1567                 case 100:
1568                         ifmr->ifm_active |= IFM_100_TX;
1569                         break;
1570                 case 1000:
1571                         ifmr->ifm_active |= IFM_1000_T;
1572                         break;
1573                 }
1574                 if (adapter->link_duplex == FULL_DUPLEX)
1575                         ifmr->ifm_active |= IFM_FDX;
1576                 else
1577                         ifmr->ifm_active |= IFM_HDX;
1578         }
1579 }
1580
1581 /*********************************************************************
1582  *
1583  *  Media Ioctl callback
1584  *
1585  *  This routine is called when the user changes speed/duplex using
1586  *  media/mediopt option with ifconfig.
1587  *
1588  **********************************************************************/
1589 static int
1590 em_if_media_change(if_ctx_t ctx)
1591 {
1592         struct adapter *adapter = iflib_get_softc(ctx);
1593         struct ifmedia *ifm = iflib_get_media(ctx);
1594
1595         INIT_DEBUGOUT("em_if_media_change: begin");
1596
1597         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1598                 return (EINVAL);
1599
1600         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1601         case IFM_AUTO:
1602                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1603                 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1604                 break;
1605         case IFM_1000_LX:
1606         case IFM_1000_SX:
1607         case IFM_1000_T:
1608                 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1609                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1610                 break;
1611         case IFM_100_TX:
1612                 adapter->hw.mac.autoneg = FALSE;
1613                 adapter->hw.phy.autoneg_advertised = 0;
1614                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1615                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1616                 else
1617                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1618                 break;
1619         case IFM_10_T:
1620                 adapter->hw.mac.autoneg = FALSE;
1621                 adapter->hw.phy.autoneg_advertised = 0;
1622                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1623                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1624                 else
1625                         adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1626                 break;
1627         default:
1628                 device_printf(adapter->dev, "Unsupported media type\n");
1629         }
1630
1631         em_if_init(ctx);
1632
1633         return (0);
1634 }
1635
1636 static int
1637 em_if_set_promisc(if_ctx_t ctx, int flags)
1638 {
1639         struct adapter *adapter = iflib_get_softc(ctx);
1640         u32 reg_rctl;
1641
1642         em_disable_promisc(ctx);
1643
1644         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1645
1646         if (flags & IFF_PROMISC) {
1647                 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1648                 /* Turn this on if you want to see bad packets */
1649                 if (em_debug_sbp)
1650                         reg_rctl |= E1000_RCTL_SBP;
1651                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1652         } else if (flags & IFF_ALLMULTI) {
1653                 reg_rctl |= E1000_RCTL_MPE;
1654                 reg_rctl &= ~E1000_RCTL_UPE;
1655                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1656         }
1657         return (0);
1658 }
1659
1660 static void
1661 em_disable_promisc(if_ctx_t ctx)
1662 {
1663         struct adapter *adapter = iflib_get_softc(ctx);
1664         struct ifnet *ifp = iflib_get_ifp(ctx);
1665         u32 reg_rctl;
1666         int mcnt = 0;
1667
1668         reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1669         reg_rctl &= (~E1000_RCTL_UPE);
1670         if (if_getflags(ifp) & IFF_ALLMULTI)
1671                 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1672         else
1673                 mcnt = if_llmaddr_count(ifp);
1674         /* Don't disable if in MAX groups */
1675         if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1676                 reg_rctl &=  (~E1000_RCTL_MPE);
1677         reg_rctl &=  (~E1000_RCTL_SBP);
1678         E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1679 }
1680
1681
1682 static u_int
1683 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1684 {
1685         u8 *mta = arg;
1686
1687         if (cnt == MAX_NUM_MULTICAST_ADDRESSES)
1688                 return (1);
1689
1690         bcopy(LLADDR(sdl), &mta[cnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1691
1692         return (1);
1693 }
1694
1695 /*********************************************************************
1696  *  Multicast Update
1697  *
1698  *  This routine is called whenever multicast address list is updated.
1699  *
1700  **********************************************************************/
1701
1702 static void
1703 em_if_multi_set(if_ctx_t ctx)
1704 {
1705         struct adapter *adapter = iflib_get_softc(ctx);
1706         struct ifnet *ifp = iflib_get_ifp(ctx);
1707         u32 reg_rctl = 0;
1708         u8  *mta; /* Multicast array memory */
1709         int mcnt = 0;
1710
1711         IOCTL_DEBUGOUT("em_set_multi: begin");
1712
1713         mta = adapter->mta;
1714         bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1715
1716         if (adapter->hw.mac.type == e1000_82542 &&
1717             adapter->hw.revision_id == E1000_REVISION_2) {
1718                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1719                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1720                         e1000_pci_clear_mwi(&adapter->hw);
1721                 reg_rctl |= E1000_RCTL_RST;
1722                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1723                 msec_delay(5);
1724         }
1725
1726         mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta);
1727
1728         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1729                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1730                 reg_rctl |= E1000_RCTL_MPE;
1731                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1732         } else
1733                 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
1734
1735         if (adapter->hw.mac.type == e1000_82542 &&
1736             adapter->hw.revision_id == E1000_REVISION_2) {
1737                 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1738                 reg_rctl &= ~E1000_RCTL_RST;
1739                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1740                 msec_delay(5);
1741                 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1742                         e1000_pci_set_mwi(&adapter->hw);
1743         }
1744 }
1745
1746 /*********************************************************************
1747  *  Timer routine
1748  *
1749  *  This routine schedules em_if_update_admin_status() to check for
1750  *  link status and to gather statistics as well as to perform some
1751  *  controller-specific hardware patting.
1752  *
1753  **********************************************************************/
1754 static void
1755 em_if_timer(if_ctx_t ctx, uint16_t qid)
1756 {
1757
1758         if (qid != 0)
1759                 return;
1760
1761         iflib_admin_intr_deferred(ctx);
1762 }
1763
1764 static void
1765 em_if_update_admin_status(if_ctx_t ctx)
1766 {
1767         struct adapter *adapter = iflib_get_softc(ctx);
1768         struct e1000_hw *hw = &adapter->hw;
1769         device_t dev = iflib_get_dev(ctx);
1770         u32 link_check, thstat, ctrl;
1771
1772         link_check = thstat = ctrl = 0;
1773         /* Get the cached link value or read phy for real */
1774         switch (hw->phy.media_type) {
1775         case e1000_media_type_copper:
1776                 if (hw->mac.get_link_status) {
1777                         if (hw->mac.type == e1000_pch_spt)
1778                                 msec_delay(50);
1779                         /* Do the work to read phy */
1780                         e1000_check_for_link(hw);
1781                         link_check = !hw->mac.get_link_status;
1782                         if (link_check) /* ESB2 fix */
1783                                 e1000_cfg_on_link_up(hw);
1784                 } else {
1785                         link_check = TRUE;
1786                 }
1787                 break;
1788         case e1000_media_type_fiber:
1789                 e1000_check_for_link(hw);
1790                 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1791                             E1000_STATUS_LU);
1792                 break;
1793         case e1000_media_type_internal_serdes:
1794                 e1000_check_for_link(hw);
1795                 link_check = hw->mac.serdes_has_link;
1796                 break;
1797         /* VF device is type_unknown */
1798         case e1000_media_type_unknown:
1799                 e1000_check_for_link(hw);
1800                 link_check = !hw->mac.get_link_status;
1801                 /* FALLTHROUGH */
1802         default:
1803                 break;
1804         }
1805
1806         /* Check for thermal downshift or shutdown */
1807         if (hw->mac.type == e1000_i350) {
1808                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1809                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1810         }
1811
1812         /* Now check for a transition */
1813         if (link_check && (adapter->link_active == 0)) {
1814                 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
1815                     &adapter->link_duplex);
1816                 /* Check if we must disable SPEED_MODE bit on PCI-E */
1817                 if ((adapter->link_speed != SPEED_1000) &&
1818                     ((hw->mac.type == e1000_82571) ||
1819                     (hw->mac.type == e1000_82572))) {
1820                         int tarc0;
1821                         tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1822                         tarc0 &= ~TARC_SPEED_MODE_BIT;
1823                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1824                 }
1825                 if (bootverbose)
1826                         device_printf(dev, "Link is up %d Mbps %s\n",
1827                             adapter->link_speed,
1828                             ((adapter->link_duplex == FULL_DUPLEX) ?
1829                             "Full Duplex" : "Half Duplex"));
1830                 adapter->link_active = 1;
1831                 adapter->smartspeed = 0;
1832                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) ==
1833                     E1000_CTRL_EXT_LINK_MODE_GMII &&
1834                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1835                         device_printf(dev, "Link: thermal downshift\n");
1836                 /* Delay Link Up for Phy update */
1837                 if (((hw->mac.type == e1000_i210) ||
1838                     (hw->mac.type == e1000_i211)) &&
1839                     (hw->phy.id == I210_I_PHY_ID))
1840                         msec_delay(I210_LINK_DELAY);
1841                 /* Reset if the media type changed. */
1842                 if (hw->dev_spec._82575.media_changed &&
1843                     hw->mac.type >= igb_mac_min) {
1844                         hw->dev_spec._82575.media_changed = false;
1845                         adapter->flags |= IGB_MEDIA_RESET;
1846                         em_reset(ctx);
1847                 }
1848                 iflib_link_state_change(ctx, LINK_STATE_UP,
1849                     IF_Mbps(adapter->link_speed));
1850         } else if (!link_check && (adapter->link_active == 1)) {
1851                 adapter->link_speed = 0;
1852                 adapter->link_duplex = 0;
1853                 adapter->link_active = 0;
1854                 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
1855         }
1856         em_update_stats_counters(adapter);
1857
1858         /* Reset LAA into RAR[0] on 82571 */
1859         if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw))
1860                 e1000_rar_set(hw, hw->mac.addr, 0);
1861
1862         if (hw->mac.type < em_mac_min)
1863                 lem_smartspeed(adapter);
1864         else if (hw->mac.type == e1000_82574 &&
1865             adapter->intr_type == IFLIB_INTR_MSIX)
1866                 E1000_WRITE_REG(hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC);
1867 }
1868
1869 static void
1870 em_if_watchdog_reset(if_ctx_t ctx)
1871 {
1872         struct adapter *adapter = iflib_get_softc(ctx);
1873
1874         /*
1875          * Just count the event; iflib(4) will already trigger a
1876          * sufficient reset of the controller.
1877          */
1878         adapter->watchdog_events++;
1879 }
1880
1881 /*********************************************************************
1882  *
1883  *  This routine disables all traffic on the adapter by issuing a
1884  *  global reset on the MAC.
1885  *
1886  **********************************************************************/
1887 static void
1888 em_if_stop(if_ctx_t ctx)
1889 {
1890         struct adapter *adapter = iflib_get_softc(ctx);
1891
1892         INIT_DEBUGOUT("em_if_stop: begin");
1893
1894         e1000_reset_hw(&adapter->hw);
1895         if (adapter->hw.mac.type >= e1000_82544)
1896                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0);
1897
1898         e1000_led_off(&adapter->hw);
1899         e1000_cleanup_led(&adapter->hw);
1900 }
1901
1902 /*********************************************************************
1903  *
1904  *  Determine hardware revision.
1905  *
1906  **********************************************************************/
1907 static void
1908 em_identify_hardware(if_ctx_t ctx)
1909 {
1910         device_t dev = iflib_get_dev(ctx);
1911         struct adapter *adapter = iflib_get_softc(ctx);
1912
1913         /* Make sure our PCI config space has the necessary stuff set */
1914         adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1915
1916         /* Save off the information about this board */
1917         adapter->hw.vendor_id = pci_get_vendor(dev);
1918         adapter->hw.device_id = pci_get_device(dev);
1919         adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1920         adapter->hw.subsystem_vendor_id =
1921             pci_read_config(dev, PCIR_SUBVEND_0, 2);
1922         adapter->hw.subsystem_device_id =
1923             pci_read_config(dev, PCIR_SUBDEV_0, 2);
1924
1925         /* Do Shared Code Init and Setup */
1926         if (e1000_set_mac_type(&adapter->hw)) {
1927                 device_printf(dev, "Setup init failure\n");
1928                 return;
1929         }
1930 }
1931
1932 static int
1933 em_allocate_pci_resources(if_ctx_t ctx)
1934 {
1935         struct adapter *adapter = iflib_get_softc(ctx);
1936         device_t dev = iflib_get_dev(ctx);
1937         int rid, val;
1938
1939         rid = PCIR_BAR(0);
1940         adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1941             &rid, RF_ACTIVE);
1942         if (adapter->memory == NULL) {
1943                 device_printf(dev, "Unable to allocate bus resource: memory\n");
1944                 return (ENXIO);
1945         }
1946         adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory);
1947         adapter->osdep.mem_bus_space_handle =
1948             rman_get_bushandle(adapter->memory);
1949         adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle;
1950
1951         /* Only older adapters use IO mapping */
1952         if (adapter->hw.mac.type < em_mac_min &&
1953             adapter->hw.mac.type > e1000_82543) {
1954                 /* Figure our where our IO BAR is ? */
1955                 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1956                         val = pci_read_config(dev, rid, 4);
1957                         if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1958                                 break;
1959                         }
1960                         rid += 4;
1961                         /* check for 64bit BAR */
1962                         if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1963                                 rid += 4;
1964                 }
1965                 if (rid >= PCIR_CIS) {
1966                         device_printf(dev, "Unable to locate IO BAR\n");
1967                         return (ENXIO);
1968                 }
1969                 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
1970                     &rid, RF_ACTIVE);
1971                 if (adapter->ioport == NULL) {
1972                         device_printf(dev, "Unable to allocate bus resource: "
1973                             "ioport\n");
1974                         return (ENXIO);
1975                 }
1976                 adapter->hw.io_base = 0;
1977                 adapter->osdep.io_bus_space_tag =
1978                     rman_get_bustag(adapter->ioport);
1979                 adapter->osdep.io_bus_space_handle =
1980                     rman_get_bushandle(adapter->ioport);
1981         }
1982
1983         adapter->hw.back = &adapter->osdep;
1984
1985         return (0);
1986 }
1987
1988 /*********************************************************************
1989  *
1990  *  Set up the MSI-X Interrupt handlers
1991  *
1992  **********************************************************************/
1993 static int
1994 em_if_msix_intr_assign(if_ctx_t ctx, int msix)
1995 {
1996         struct adapter *adapter = iflib_get_softc(ctx);
1997         struct em_rx_queue *rx_que = adapter->rx_queues;
1998         struct em_tx_queue *tx_que = adapter->tx_queues;
1999         int error, rid, i, vector = 0, rx_vectors;
2000         char buf[16];
2001
2002         /* First set up ring resources */
2003         for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) {
2004                 rid = vector + 1;
2005                 snprintf(buf, sizeof(buf), "rxq%d", i);
2006                 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
2007                 if (error) {
2008                         device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
2009                         adapter->rx_num_queues = i + 1;
2010                         goto fail;
2011                 }
2012
2013                 rx_que->msix =  vector;
2014
2015                 /*
2016                  * Set the bit to enable interrupt
2017                  * in E1000_IMS -- bits 20 and 21
2018                  * are for RX0 and RX1, note this has
2019                  * NOTHING to do with the MSI-X vector
2020                  */
2021                 if (adapter->hw.mac.type == e1000_82574) {
2022                         rx_que->eims = 1 << (20 + i);
2023                         adapter->ims |= rx_que->eims;
2024                         adapter->ivars |= (8 | rx_que->msix) << (i * 4);
2025                 } else if (adapter->hw.mac.type == e1000_82575)
2026                         rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
2027                 else
2028                         rx_que->eims = 1 << vector;
2029         }
2030         rx_vectors = vector;
2031
2032         vector = 0;
2033         for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) {
2034                 snprintf(buf, sizeof(buf), "txq%d", i);
2035                 tx_que = &adapter->tx_queues[i];
2036                 iflib_softirq_alloc_generic(ctx,
2037                     &adapter->rx_queues[i % adapter->rx_num_queues].que_irq,
2038                     IFLIB_INTR_TX, tx_que, tx_que->me, buf);
2039
2040                 tx_que->msix = (vector % adapter->rx_num_queues);
2041
2042                 /*
2043                  * Set the bit to enable interrupt
2044                  * in E1000_IMS -- bits 22 and 23
2045                  * are for TX0 and TX1, note this has
2046                  * NOTHING to do with the MSI-X vector
2047                  */
2048                 if (adapter->hw.mac.type == e1000_82574) {
2049                         tx_que->eims = 1 << (22 + i);
2050                         adapter->ims |= tx_que->eims;
2051                         adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
2052                 } else if (adapter->hw.mac.type == e1000_82575) {
2053                         tx_que->eims = E1000_EICR_TX_QUEUE0 << i;
2054                 } else {
2055                         tx_que->eims = 1 << i;
2056                 }
2057         }
2058
2059         /* Link interrupt */
2060         rid = rx_vectors + 1;
2061         error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq");
2062
2063         if (error) {
2064                 device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
2065                 goto fail;
2066         }
2067         adapter->linkvec = rx_vectors;
2068         if (adapter->hw.mac.type < igb_mac_min) {
2069                 adapter->ivars |=  (8 | rx_vectors) << 16;
2070                 adapter->ivars |= 0x80000000;
2071         }
2072         return (0);
2073 fail:
2074         iflib_irq_free(ctx, &adapter->irq);
2075         rx_que = adapter->rx_queues;
2076         for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++)
2077                 iflib_irq_free(ctx, &rx_que->que_irq);
2078         return (error);
2079 }
2080
2081 static void
2082 igb_configure_queues(struct adapter *adapter)
2083 {
2084         struct e1000_hw *hw = &adapter->hw;
2085         struct em_rx_queue *rx_que;
2086         struct em_tx_queue *tx_que;
2087         u32 tmp, ivar = 0, newitr = 0;
2088
2089         /* First turn on RSS capability */
2090         if (hw->mac.type != e1000_82575)
2091                 E1000_WRITE_REG(hw, E1000_GPIE,
2092                     E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |
2093                     E1000_GPIE_PBA | E1000_GPIE_NSICR);
2094
2095         /* Turn on MSI-X */
2096         switch (hw->mac.type) {
2097         case e1000_82580:
2098         case e1000_i350:
2099         case e1000_i354:
2100         case e1000_i210:
2101         case e1000_i211:
2102         case e1000_vfadapt:
2103         case e1000_vfadapt_i350:
2104                 /* RX entries */
2105                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2106                         u32 index = i >> 1;
2107                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2108                         rx_que = &adapter->rx_queues[i];
2109                         if (i & 1) {
2110                                 ivar &= 0xFF00FFFF;
2111                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2112                         } else {
2113                                 ivar &= 0xFFFFFF00;
2114                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2115                         }
2116                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2117                 }
2118                 /* TX entries */
2119                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2120                         u32 index = i >> 1;
2121                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2122                         tx_que = &adapter->tx_queues[i];
2123                         if (i & 1) {
2124                                 ivar &= 0x00FFFFFF;
2125                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2126                         } else {
2127                                 ivar &= 0xFFFF00FF;
2128                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2129                         }
2130                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2131                         adapter->que_mask |= tx_que->eims;
2132                 }
2133
2134                 /* And for the link interrupt */
2135                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2136                 adapter->link_mask = 1 << adapter->linkvec;
2137                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2138                 break;
2139         case e1000_82576:
2140                 /* RX entries */
2141                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2142                         u32 index = i & 0x7; /* Each IVAR has two entries */
2143                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2144                         rx_que = &adapter->rx_queues[i];
2145                         if (i < 8) {
2146                                 ivar &= 0xFFFFFF00;
2147                                 ivar |= rx_que->msix | E1000_IVAR_VALID;
2148                         } else {
2149                                 ivar &= 0xFF00FFFF;
2150                                 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
2151                         }
2152                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2153                         adapter->que_mask |= rx_que->eims;
2154                 }
2155                 /* TX entries */
2156                 for (int i = 0; i < adapter->tx_num_queues; i++) {
2157                         u32 index = i & 0x7; /* Each IVAR has two entries */
2158                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
2159                         tx_que = &adapter->tx_queues[i];
2160                         if (i < 8) {
2161                                 ivar &= 0xFFFF00FF;
2162                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
2163                         } else {
2164                                 ivar &= 0x00FFFFFF;
2165                                 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
2166                         }
2167                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
2168                         adapter->que_mask |= tx_que->eims;
2169                 }
2170
2171                 /* And for the link interrupt */
2172                 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8;
2173                 adapter->link_mask = 1 << adapter->linkvec;
2174                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
2175                 break;
2176
2177         case e1000_82575:
2178                 /* enable MSI-X support*/
2179                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
2180                 tmp |= E1000_CTRL_EXT_PBA_CLR;
2181                 /* Auto-Mask interrupts upon ICR read. */
2182                 tmp |= E1000_CTRL_EXT_EIAME;
2183                 tmp |= E1000_CTRL_EXT_IRCA;
2184                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
2185
2186                 /* Queues */
2187                 for (int i = 0; i < adapter->rx_num_queues; i++) {
2188                         rx_que = &adapter->rx_queues[i];
2189                         tmp = E1000_EICR_RX_QUEUE0 << i;
2190                         tmp |= E1000_EICR_TX_QUEUE0 << i;
2191                         rx_que->eims = tmp;
2192                         E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
2193                             i, rx_que->eims);
2194                         adapter->que_mask |= rx_que->eims;
2195                 }
2196
2197                 /* Link */
2198                 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec),
2199                     E1000_EIMS_OTHER);
2200                 adapter->link_mask |= E1000_EIMS_OTHER;
2201         default:
2202                 break;
2203         }
2204
2205         /* Set the starting interrupt rate */
2206         if (em_max_interrupt_rate > 0)
2207                 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
2208
2209         if (hw->mac.type == e1000_82575)
2210                 newitr |= newitr << 16;
2211         else
2212                 newitr |= E1000_EITR_CNT_IGNR;
2213
2214         for (int i = 0; i < adapter->rx_num_queues; i++) {
2215                 rx_que = &adapter->rx_queues[i];
2216                 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2217         }
2218
2219         return;
2220 }
2221
2222 static void
2223 em_free_pci_resources(if_ctx_t ctx)
2224 {
2225         struct adapter *adapter = iflib_get_softc(ctx);
2226         struct em_rx_queue *que = adapter->rx_queues;
2227         device_t dev = iflib_get_dev(ctx);
2228
2229         /* Release all MSI-X queue resources */
2230         if (adapter->intr_type == IFLIB_INTR_MSIX)
2231                 iflib_irq_free(ctx, &adapter->irq);
2232
2233         if (que != NULL) {
2234                 for (int i = 0; i < adapter->rx_num_queues; i++, que++) {
2235                         iflib_irq_free(ctx, &que->que_irq);
2236                 }
2237         }
2238
2239         if (adapter->memory != NULL) {
2240                 bus_release_resource(dev, SYS_RES_MEMORY,
2241                     rman_get_rid(adapter->memory), adapter->memory);
2242                 adapter->memory = NULL;
2243         }
2244
2245         if (adapter->flash != NULL) {
2246                 bus_release_resource(dev, SYS_RES_MEMORY,
2247                     rman_get_rid(adapter->flash), adapter->flash);
2248                 adapter->flash = NULL;
2249         }
2250
2251         if (adapter->ioport != NULL) {
2252                 bus_release_resource(dev, SYS_RES_IOPORT,
2253                     rman_get_rid(adapter->ioport), adapter->ioport);
2254                 adapter->ioport = NULL;
2255         }
2256 }
2257
2258 /* Set up MSI or MSI-X */
2259 static int
2260 em_setup_msix(if_ctx_t ctx)
2261 {
2262         struct adapter *adapter = iflib_get_softc(ctx);
2263
2264         if (adapter->hw.mac.type == e1000_82574) {
2265                 em_enable_vectors_82574(ctx);
2266         }
2267         return (0);
2268 }
2269
2270 /*********************************************************************
2271  *
2272  *  Workaround for SmartSpeed on 82541 and 82547 controllers
2273  *
2274  **********************************************************************/
2275 static void
2276 lem_smartspeed(struct adapter *adapter)
2277 {
2278         u16 phy_tmp;
2279
2280         if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) ||
2281             adapter->hw.mac.autoneg == 0 ||
2282             (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2283                 return;
2284
2285         if (adapter->smartspeed == 0) {
2286                 /* If Master/Slave config fault is asserted twice,
2287                  * we assume back-to-back */
2288                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2289                 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2290                         return;
2291                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2292                 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2293                         e1000_read_phy_reg(&adapter->hw,
2294                             PHY_1000T_CTRL, &phy_tmp);
2295                         if(phy_tmp & CR_1000T_MS_ENABLE) {
2296                                 phy_tmp &= ~CR_1000T_MS_ENABLE;
2297                                 e1000_write_phy_reg(&adapter->hw,
2298                                     PHY_1000T_CTRL, phy_tmp);
2299                                 adapter->smartspeed++;
2300                                 if(adapter->hw.mac.autoneg &&
2301                                    !e1000_copper_link_autoneg(&adapter->hw) &&
2302                                    !e1000_read_phy_reg(&adapter->hw,
2303                                     PHY_CONTROL, &phy_tmp)) {
2304                                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2305                                                     MII_CR_RESTART_AUTO_NEG);
2306                                         e1000_write_phy_reg(&adapter->hw,
2307                                             PHY_CONTROL, phy_tmp);
2308                                 }
2309                         }
2310                 }
2311                 return;
2312         } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2313                 /* If still no link, perhaps using 2/3 pair cable */
2314                 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2315                 phy_tmp |= CR_1000T_MS_ENABLE;
2316                 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2317                 if(adapter->hw.mac.autoneg &&
2318                    !e1000_copper_link_autoneg(&adapter->hw) &&
2319                    !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2320                         phy_tmp |= (MII_CR_AUTO_NEG_EN |
2321                                     MII_CR_RESTART_AUTO_NEG);
2322                         e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2323                 }
2324         }
2325         /* Restart process after EM_SMARTSPEED_MAX iterations */
2326         if(adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2327                 adapter->smartspeed = 0;
2328 }
2329
2330 /*********************************************************************
2331  *
2332  *  Initialize the DMA Coalescing feature
2333  *
2334  **********************************************************************/
2335 static void
2336 igb_init_dmac(struct adapter *adapter, u32 pba)
2337 {
2338         device_t        dev = adapter->dev;
2339         struct e1000_hw *hw = &adapter->hw;
2340         u32             dmac, reg = ~E1000_DMACR_DMAC_EN;
2341         u16             hwm;
2342         u16             max_frame_size;
2343
2344         if (hw->mac.type == e1000_i211)
2345                 return;
2346
2347         max_frame_size = adapter->shared->isc_max_frame_size;
2348         if (hw->mac.type > e1000_82580) {
2349
2350                 if (adapter->dmac == 0) { /* Disabling it */
2351                         E1000_WRITE_REG(hw, E1000_DMACR, reg);
2352                         return;
2353                 } else
2354                         device_printf(dev, "DMA Coalescing enabled\n");
2355
2356                 /* Set starting threshold */
2357                 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
2358
2359                 hwm = 64 * pba - max_frame_size / 16;
2360                 if (hwm < 64 * (pba - 6))
2361                         hwm = 64 * (pba - 6);
2362                 reg = E1000_READ_REG(hw, E1000_FCRTC);
2363                 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
2364                 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
2365                     & E1000_FCRTC_RTH_COAL_MASK);
2366                 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
2367
2368
2369                 dmac = pba - max_frame_size / 512;
2370                 if (dmac < pba - 10)
2371                         dmac = pba - 10;
2372                 reg = E1000_READ_REG(hw, E1000_DMACR);
2373                 reg &= ~E1000_DMACR_DMACTHR_MASK;
2374                 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT)
2375                     & E1000_DMACR_DMACTHR_MASK);
2376
2377                 /* transition to L0x or L1 if available..*/
2378                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
2379
2380                 /* Check if status is 2.5Gb backplane connection
2381                 * before configuration of watchdog timer, which is
2382                 * in msec values in 12.8usec intervals
2383                 * watchdog timer= msec values in 32usec intervals
2384                 * for non 2.5Gb connection
2385                 */
2386                 if (hw->mac.type == e1000_i354) {
2387                         int status = E1000_READ_REG(hw, E1000_STATUS);
2388                         if ((status & E1000_STATUS_2P5_SKU) &&
2389                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2390                                 reg |= ((adapter->dmac * 5) >> 6);
2391                         else
2392                                 reg |= (adapter->dmac >> 5);
2393                 } else {
2394                         reg |= (adapter->dmac >> 5);
2395                 }
2396
2397                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
2398
2399                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
2400
2401                 /* Set the interval before transition */
2402                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
2403                 if (hw->mac.type == e1000_i350)
2404                         reg |= IGB_DMCTLX_DCFLUSH_DIS;
2405                 /*
2406                 ** in 2.5Gb connection, TTLX unit is 0.4 usec
2407                 ** which is 0x4*2 = 0xA. But delay is still 4 usec
2408                 */
2409                 if (hw->mac.type == e1000_i354) {
2410                         int status = E1000_READ_REG(hw, E1000_STATUS);
2411                         if ((status & E1000_STATUS_2P5_SKU) &&
2412                             (!(status & E1000_STATUS_2P5_SKU_OVER)))
2413                                 reg |= 0xA;
2414                         else
2415                                 reg |= 0x4;
2416                 } else {
2417                         reg |= 0x4;
2418                 }
2419
2420                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
2421
2422                 /* free space in tx packet buffer to wake from DMA coal */
2423                 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE -
2424                     (2 * max_frame_size)) >> 6);
2425
2426                 /* make low power state decision controlled by DMA coal */
2427                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2428                 reg &= ~E1000_PCIEMISC_LX_DECISION;
2429                 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
2430
2431         } else if (hw->mac.type == e1000_82580) {
2432                 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
2433                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
2434                     reg & ~E1000_PCIEMISC_LX_DECISION);
2435                 E1000_WRITE_REG(hw, E1000_DMACR, 0);
2436         }
2437 }
2438
2439 /*********************************************************************
2440  *
2441  *  Initialize the hardware to a configuration as specified by the
2442  *  adapter structure.
2443  *
2444  **********************************************************************/
2445 static void
2446 em_reset(if_ctx_t ctx)
2447 {
2448         device_t dev = iflib_get_dev(ctx);
2449         struct adapter *adapter = iflib_get_softc(ctx);
2450         struct ifnet *ifp = iflib_get_ifp(ctx);
2451         struct e1000_hw *hw = &adapter->hw;
2452         u16 rx_buffer_size;
2453         u32 pba;
2454
2455         INIT_DEBUGOUT("em_reset: begin");
2456         /* Let the firmware know the OS is in control */
2457         em_get_hw_control(adapter);
2458
2459         /* Set up smart power down as default off on newer adapters. */
2460         if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
2461             hw->mac.type == e1000_82572)) {
2462                 u16 phy_tmp = 0;
2463
2464                 /* Speed up time to link by disabling smart power down. */
2465                 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2466                 phy_tmp &= ~IGP02E1000_PM_SPD;
2467                 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2468         }
2469
2470         /*
2471          * Packet Buffer Allocation (PBA)
2472          * Writing PBA sets the receive portion of the buffer
2473          * the remainder is used for the transmit buffer.
2474          */
2475         switch (hw->mac.type) {
2476         /* Total Packet Buffer on these is 48K */
2477         case e1000_82571:
2478         case e1000_82572:
2479         case e1000_80003es2lan:
2480                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2481                 break;
2482         case e1000_82573: /* 82573: Total Packet Buffer is 32K */
2483                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2484                 break;
2485         case e1000_82574:
2486         case e1000_82583:
2487                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2488                 break;
2489         case e1000_ich8lan:
2490                 pba = E1000_PBA_8K;
2491                 break;
2492         case e1000_ich9lan:
2493         case e1000_ich10lan:
2494                 /* Boost Receive side for jumbo frames */
2495                 if (hw->mac.max_frame_size > 4096)
2496                         pba = E1000_PBA_14K;
2497                 else
2498                         pba = E1000_PBA_10K;
2499                 break;
2500         case e1000_pchlan:
2501         case e1000_pch2lan:
2502         case e1000_pch_lpt:
2503         case e1000_pch_spt:
2504         case e1000_pch_cnp:
2505                 pba = E1000_PBA_26K;
2506                 break;
2507         case e1000_82575:
2508                 pba = E1000_PBA_32K;
2509                 break;
2510         case e1000_82576:
2511         case e1000_vfadapt:
2512                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2513                 pba &= E1000_RXPBS_SIZE_MASK_82576;
2514                 break;
2515         case e1000_82580:
2516         case e1000_i350:
2517         case e1000_i354:
2518         case e1000_vfadapt_i350:
2519                 pba = E1000_READ_REG(hw, E1000_RXPBS);
2520                 pba = e1000_rxpbs_adjust_82580(pba);
2521                 break;
2522         case e1000_i210:
2523         case e1000_i211:
2524                 pba = E1000_PBA_34K;
2525                 break;
2526         default:
2527                 if (hw->mac.max_frame_size > 8192)
2528                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2529                 else
2530                         pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2531         }
2532
2533         /* Special needs in case of Jumbo frames */
2534         if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) {
2535                 u32 tx_space, min_tx, min_rx;
2536                 pba = E1000_READ_REG(hw, E1000_PBA);
2537                 tx_space = pba >> 16;
2538                 pba &= 0xffff;
2539                 min_tx = (hw->mac.max_frame_size +
2540                     sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
2541                 min_tx = roundup2(min_tx, 1024);
2542                 min_tx >>= 10;
2543                 min_rx = hw->mac.max_frame_size;
2544                 min_rx = roundup2(min_rx, 1024);
2545                 min_rx >>= 10;
2546                 if (tx_space < min_tx &&
2547                     ((min_tx - tx_space) < pba)) {
2548                         pba = pba - (min_tx - tx_space);
2549                         /*
2550                          * if short on rx space, rx wins
2551                          * and must trump tx adjustment
2552                          */
2553                         if (pba < min_rx)
2554                                 pba = min_rx;
2555                 }
2556                 E1000_WRITE_REG(hw, E1000_PBA, pba);
2557         }
2558
2559         if (hw->mac.type < igb_mac_min)
2560                 E1000_WRITE_REG(hw, E1000_PBA, pba);
2561
2562         INIT_DEBUGOUT1("em_reset: pba=%dK",pba);
2563
2564         /*
2565          * These parameters control the automatic generation (Tx) and
2566          * response (Rx) to Ethernet PAUSE frames.
2567          * - High water mark should allow for at least two frames to be
2568          *   received after sending an XOFF.
2569          * - Low water mark works best when it is very near the high water mark.
2570          *   This allows the receiver to restart by sending XON when it has
2571          *   drained a bit. Here we use an arbitrary value of 1500 which will
2572          *   restart after one full frame is pulled from the buffer. There
2573          *   could be several smaller frames in the buffer and if so they will
2574          *   not trigger the XON until their total number reduces the buffer
2575          *   by 1500.
2576          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2577          */
2578         rx_buffer_size = (pba & 0xffff) << 10;
2579         hw->fc.high_water = rx_buffer_size -
2580             roundup2(hw->mac.max_frame_size, 1024);
2581         hw->fc.low_water = hw->fc.high_water - 1500;
2582
2583         if (adapter->fc) /* locally set flow control value? */
2584                 hw->fc.requested_mode = adapter->fc;
2585         else
2586                 hw->fc.requested_mode = e1000_fc_full;
2587
2588         if (hw->mac.type == e1000_80003es2lan)
2589                 hw->fc.pause_time = 0xFFFF;
2590         else
2591                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
2592
2593         hw->fc.send_xon = TRUE;
2594
2595         /* Device specific overrides/settings */
2596         switch (hw->mac.type) {
2597         case e1000_pchlan:
2598                 /* Workaround: no TX flow ctrl for PCH */
2599                 hw->fc.requested_mode = e1000_fc_rx_pause;
2600                 hw->fc.pause_time = 0xFFFF; /* override */
2601                 if (if_getmtu(ifp) > ETHERMTU) {
2602                         hw->fc.high_water = 0x3500;
2603                         hw->fc.low_water = 0x1500;
2604                 } else {
2605                         hw->fc.high_water = 0x5000;
2606                         hw->fc.low_water = 0x3000;
2607                 }
2608                 hw->fc.refresh_time = 0x1000;
2609                 break;
2610         case e1000_pch2lan:
2611         case e1000_pch_lpt:
2612         case e1000_pch_spt:
2613         case e1000_pch_cnp:
2614                 hw->fc.high_water = 0x5C20;
2615                 hw->fc.low_water = 0x5048;
2616                 hw->fc.pause_time = 0x0650;
2617                 hw->fc.refresh_time = 0x0400;
2618                 /* Jumbos need adjusted PBA */
2619                 if (if_getmtu(ifp) > ETHERMTU)
2620                         E1000_WRITE_REG(hw, E1000_PBA, 12);
2621                 else
2622                         E1000_WRITE_REG(hw, E1000_PBA, 26);
2623                 break;
2624         case e1000_82575:
2625         case e1000_82576:
2626                 /* 8-byte granularity */
2627                 hw->fc.low_water = hw->fc.high_water - 8;
2628                 break;
2629         case e1000_82580:
2630         case e1000_i350:
2631         case e1000_i354:
2632         case e1000_i210:
2633         case e1000_i211:
2634         case e1000_vfadapt:
2635         case e1000_vfadapt_i350:
2636                 /* 16-byte granularity */
2637                 hw->fc.low_water = hw->fc.high_water - 16;
2638                 break;
2639         case e1000_ich9lan:
2640         case e1000_ich10lan:
2641                 if (if_getmtu(ifp) > ETHERMTU) {
2642                         hw->fc.high_water = 0x2800;
2643                         hw->fc.low_water = hw->fc.high_water - 8;
2644                         break;
2645                 }
2646                 /* FALLTHROUGH */
2647         default:
2648                 if (hw->mac.type == e1000_80003es2lan)
2649                         hw->fc.pause_time = 0xFFFF;
2650                 break;
2651         }
2652
2653         /* Issue a global reset */
2654         e1000_reset_hw(hw);
2655         if (hw->mac.type >= igb_mac_min) {
2656                 E1000_WRITE_REG(hw, E1000_WUC, 0);
2657         } else {
2658                 E1000_WRITE_REG(hw, E1000_WUFC, 0);
2659                 em_disable_aspm(adapter);
2660         }
2661         if (adapter->flags & IGB_MEDIA_RESET) {
2662                 e1000_setup_init_funcs(hw, TRUE);
2663                 e1000_get_bus_info(hw);
2664                 adapter->flags &= ~IGB_MEDIA_RESET;
2665         }
2666         /* and a re-init */
2667         if (e1000_init_hw(hw) < 0) {
2668                 device_printf(dev, "Hardware Initialization Failed\n");
2669                 return;
2670         }
2671         if (hw->mac.type >= igb_mac_min)
2672                 igb_init_dmac(adapter, pba);
2673
2674         E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
2675         e1000_get_phy_info(hw);
2676         e1000_check_for_link(hw);
2677 }
2678
2679 /*
2680  * Initialise the RSS mapping for NICs that support multiple transmit/
2681  * receive rings.
2682  */
2683
2684 #define RSSKEYLEN 10
2685 static void
2686 em_initialize_rss_mapping(struct adapter *adapter)
2687 {
2688         uint8_t  rss_key[4 * RSSKEYLEN];
2689         uint32_t reta = 0;
2690         struct e1000_hw *hw = &adapter->hw;
2691         int i;
2692
2693         /*
2694          * Configure RSS key
2695          */
2696         arc4rand(rss_key, sizeof(rss_key), 0);
2697         for (i = 0; i < RSSKEYLEN; ++i) {
2698                 uint32_t rssrk = 0;
2699
2700                 rssrk = EM_RSSRK_VAL(rss_key, i);
2701                 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk);
2702         }
2703
2704         /*
2705          * Configure RSS redirect table in following fashion:
2706          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2707          */
2708         for (i = 0; i < sizeof(reta); ++i) {
2709                 uint32_t q;
2710
2711                 q = (i % adapter->rx_num_queues) << 7;
2712                 reta |= q << (8 * i);
2713         }
2714
2715         for (i = 0; i < 32; ++i)
2716                 E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2717
2718         E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q |
2719                         E1000_MRQC_RSS_FIELD_IPV4_TCP |
2720                         E1000_MRQC_RSS_FIELD_IPV4 |
2721                         E1000_MRQC_RSS_FIELD_IPV6_TCP_EX |
2722                         E1000_MRQC_RSS_FIELD_IPV6_EX |
2723                         E1000_MRQC_RSS_FIELD_IPV6);
2724 }
2725
2726 static void
2727 igb_initialize_rss_mapping(struct adapter *adapter)
2728 {
2729         struct e1000_hw *hw = &adapter->hw;
2730         int i;
2731         int queue_id;
2732         u32 reta;
2733         u32 rss_key[10], mrqc, shift = 0;
2734
2735         /* XXX? */
2736         if (hw->mac.type == e1000_82575)
2737                 shift = 6;
2738
2739         /*
2740          * The redirection table controls which destination
2741          * queue each bucket redirects traffic to.
2742          * Each DWORD represents four queues, with the LSB
2743          * being the first queue in the DWORD.
2744          *
2745          * This just allocates buckets to queues using round-robin
2746          * allocation.
2747          *
2748          * NOTE: It Just Happens to line up with the default
2749          * RSS allocation method.
2750          */
2751
2752         /* Warning FM follows */
2753         reta = 0;
2754         for (i = 0; i < 128; i++) {
2755 #ifdef RSS
2756                 queue_id = rss_get_indirection_to_bucket(i);
2757                 /*
2758                  * If we have more queues than buckets, we'll
2759                  * end up mapping buckets to a subset of the
2760                  * queues.
2761                  *
2762                  * If we have more buckets than queues, we'll
2763                  * end up instead assigning multiple buckets
2764                  * to queues.
2765                  *
2766                  * Both are suboptimal, but we need to handle
2767                  * the case so we don't go out of bounds
2768                  * indexing arrays and such.
2769                  */
2770                 queue_id = queue_id % adapter->rx_num_queues;
2771 #else
2772                 queue_id = (i % adapter->rx_num_queues);
2773 #endif
2774                 /* Adjust if required */
2775                 queue_id = queue_id << shift;
2776
2777                 /*
2778                  * The low 8 bits are for hash value (n+0);
2779                  * The next 8 bits are for hash value (n+1), etc.
2780                  */
2781                 reta = reta >> 8;
2782                 reta = reta | ( ((uint32_t) queue_id) << 24);
2783                 if ((i & 3) == 3) {
2784                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2785                         reta = 0;
2786                 }
2787         }
2788
2789         /* Now fill in hash table */
2790
2791         /*
2792          * MRQC: Multiple Receive Queues Command
2793          * Set queuing to RSS control, number depends on the device.
2794          */
2795         mrqc = E1000_MRQC_ENABLE_RSS_8Q;
2796
2797 #ifdef RSS
2798         /* XXX ew typecasting */
2799         rss_getkey((uint8_t *) &rss_key);
2800 #else
2801         arc4rand(&rss_key, sizeof(rss_key), 0);
2802 #endif
2803         for (i = 0; i < 10; i++)
2804                 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]);
2805
2806         /*
2807          * Configure the RSS fields to hash upon.
2808          */
2809         mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2810             E1000_MRQC_RSS_FIELD_IPV4_TCP);
2811         mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2812             E1000_MRQC_RSS_FIELD_IPV6_TCP);
2813         mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2814             E1000_MRQC_RSS_FIELD_IPV6_UDP);
2815         mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2816             E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2817
2818         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2819 }
2820
2821 /*********************************************************************
2822  *
2823  *  Setup networking device structure and register interface media.
2824  *
2825  **********************************************************************/
2826 static int
2827 em_setup_interface(if_ctx_t ctx)
2828 {
2829         struct ifnet *ifp = iflib_get_ifp(ctx);
2830         struct adapter *adapter = iflib_get_softc(ctx);
2831         if_softc_ctx_t scctx = adapter->shared;
2832
2833         INIT_DEBUGOUT("em_setup_interface: begin");
2834
2835         /* Single Queue */
2836         if (adapter->tx_num_queues == 1) {
2837                 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
2838                 if_setsendqready(ifp);
2839         }
2840
2841         /*
2842          * Specify the media types supported by this adapter and register
2843          * callbacks to update media and link information
2844          */
2845         if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2846             adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
2847                 u_char fiber_type = IFM_1000_SX;        /* default type */
2848
2849                 if (adapter->hw.mac.type == e1000_82545)
2850                         fiber_type = IFM_1000_LX;
2851                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
2852                 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2853         } else {
2854                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2855                 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2856                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2857                 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2858                 if (adapter->hw.phy.type != e1000_phy_ife) {
2859                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2860                         ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2861                 }
2862         }
2863         ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2864         ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO);
2865         return (0);
2866 }
2867
2868 static int
2869 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
2870 {
2871         struct adapter *adapter = iflib_get_softc(ctx);
2872         if_softc_ctx_t scctx = adapter->shared;
2873         int error = E1000_SUCCESS;
2874         struct em_tx_queue *que;
2875         int i, j;
2876
2877         MPASS(adapter->tx_num_queues > 0);
2878         MPASS(adapter->tx_num_queues == ntxqsets);
2879
2880         /* First allocate the top level queue structs */
2881         if (!(adapter->tx_queues =
2882             (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
2883             adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2884                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2885                 return(ENOMEM);
2886         }
2887
2888         for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) {
2889                 /* Set up some basics */
2890
2891                 struct tx_ring *txr = &que->txr;
2892                 txr->adapter = que->adapter = adapter;
2893                 que->me = txr->me =  i;
2894
2895                 /* Allocate report status array */
2896                 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2897                         device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n");
2898                         error = ENOMEM;
2899                         goto fail;
2900                 }
2901                 for (j = 0; j < scctx->isc_ntxd[0]; j++)
2902                         txr->tx_rsq[j] = QIDX_INVALID;
2903                 /* get the virtual and physical address of the hardware queues */
2904                 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
2905                 txr->tx_paddr = paddrs[i*ntxqs];
2906         }
2907
2908         if (bootverbose)
2909                 device_printf(iflib_get_dev(ctx),
2910                     "allocated for %d tx_queues\n", adapter->tx_num_queues);
2911         return (0);
2912 fail:
2913         em_if_queues_free(ctx);
2914         return (error);
2915 }
2916
2917 static int
2918 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
2919 {
2920         struct adapter *adapter = iflib_get_softc(ctx);
2921         int error = E1000_SUCCESS;
2922         struct em_rx_queue *que;
2923         int i;
2924
2925         MPASS(adapter->rx_num_queues > 0);
2926         MPASS(adapter->rx_num_queues == nrxqsets);
2927
2928         /* First allocate the top level queue structs */
2929         if (!(adapter->rx_queues =
2930             (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
2931             adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2932                 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
2933                 error = ENOMEM;
2934                 goto fail;
2935         }
2936
2937         for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) {
2938                 /* Set up some basics */
2939                 struct rx_ring *rxr = &que->rxr;
2940                 rxr->adapter = que->adapter = adapter;
2941                 rxr->que = que;
2942                 que->me = rxr->me =  i;
2943
2944                 /* get the virtual and physical address of the hardware queues */
2945                 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
2946                 rxr->rx_paddr = paddrs[i*nrxqs];
2947         }
2948
2949         if (bootverbose)
2950                 device_printf(iflib_get_dev(ctx),
2951                     "allocated for %d rx_queues\n", adapter->rx_num_queues);
2952
2953         return (0);
2954 fail:
2955         em_if_queues_free(ctx);
2956         return (error);
2957 }
2958
2959 static void
2960 em_if_queues_free(if_ctx_t ctx)
2961 {
2962         struct adapter *adapter = iflib_get_softc(ctx);
2963         struct em_tx_queue *tx_que = adapter->tx_queues;
2964         struct em_rx_queue *rx_que = adapter->rx_queues;
2965
2966         if (tx_que != NULL) {
2967                 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
2968                         struct tx_ring *txr = &tx_que->txr;
2969                         if (txr->tx_rsq == NULL)
2970                                 break;
2971
2972                         free(txr->tx_rsq, M_DEVBUF);
2973                         txr->tx_rsq = NULL;
2974                 }
2975                 free(adapter->tx_queues, M_DEVBUF);
2976                 adapter->tx_queues = NULL;
2977         }
2978
2979         if (rx_que != NULL) {
2980                 free(adapter->rx_queues, M_DEVBUF);
2981                 adapter->rx_queues = NULL;
2982         }
2983 }
2984
2985 /*********************************************************************
2986  *
2987  *  Enable transmit unit.
2988  *
2989  **********************************************************************/
2990 static void
2991 em_initialize_transmit_unit(if_ctx_t ctx)
2992 {
2993         struct adapter *adapter = iflib_get_softc(ctx);
2994         if_softc_ctx_t scctx = adapter->shared;
2995         struct em_tx_queue *que;
2996         struct tx_ring  *txr;
2997         struct e1000_hw *hw = &adapter->hw;
2998         u32 tctl, txdctl = 0, tarc, tipg = 0;
2999
3000         INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
3001
3002         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
3003                 u64 bus_addr;
3004                 caddr_t offp, endp;
3005
3006                 que = &adapter->tx_queues[i];
3007                 txr = &que->txr;
3008                 bus_addr = txr->tx_paddr;
3009
3010                 /* Clear checksum offload context. */
3011                 offp = (caddr_t)&txr->csum_flags;
3012                 endp = (caddr_t)(txr + 1);
3013                 bzero(offp, endp - offp);
3014
3015                 /* Base and Len of TX Ring */
3016                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
3017                     scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
3018                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
3019                     (u32)(bus_addr >> 32));
3020                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
3021                     (u32)bus_addr);
3022                 /* Init the HEAD/TAIL indices */
3023                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
3024                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
3025
3026                 HW_DEBUGOUT2("Base = %x, Length = %x\n",
3027                     E1000_READ_REG(hw, E1000_TDBAL(i)),
3028                     E1000_READ_REG(hw, E1000_TDLEN(i)));
3029
3030                 txdctl = 0; /* clear txdctl */
3031                 txdctl |= 0x1f; /* PTHRESH */
3032                 txdctl |= 1 << 8; /* HTHRESH */
3033                 txdctl |= 1 << 16;/* WTHRESH */
3034                 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
3035                 txdctl |= E1000_TXDCTL_GRAN;
3036                 txdctl |= 1 << 25; /* LWTHRESH */
3037
3038                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
3039         }
3040
3041         /* Set the default values for the Tx Inter Packet Gap timer */
3042         switch (hw->mac.type) {
3043         case e1000_80003es2lan:
3044                 tipg = DEFAULT_82543_TIPG_IPGR1;
3045                 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
3046                     E1000_TIPG_IPGR2_SHIFT;
3047                 break;
3048         case e1000_82542:
3049                 tipg = DEFAULT_82542_TIPG_IPGT;
3050                 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3051                 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3052                 break;
3053         default:
3054                 if (hw->phy.media_type == e1000_media_type_fiber ||
3055                     hw->phy.media_type == e1000_media_type_internal_serdes)
3056                         tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
3057                 else
3058                         tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
3059                 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
3060                 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
3061         }
3062
3063         E1000_WRITE_REG(hw, E1000_TIPG, tipg);
3064         E1000_WRITE_REG(hw, E1000_TIDV, adapter->tx_int_delay.value);
3065
3066         if(hw->mac.type >= e1000_82540)
3067                 E1000_WRITE_REG(hw, E1000_TADV,
3068                     adapter->tx_abs_int_delay.value);
3069
3070         if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) {
3071                 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3072                 tarc |= TARC_SPEED_MODE_BIT;
3073                 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3074         } else if (hw->mac.type == e1000_80003es2lan) {
3075                 /* errata: program both queues to unweighted RR */
3076                 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3077                 tarc |= 1;
3078                 E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3079                 tarc = E1000_READ_REG(hw, E1000_TARC(1));
3080                 tarc |= 1;
3081                 E1000_WRITE_REG(hw, E1000_TARC(1), tarc);
3082         } else if (hw->mac.type == e1000_82574) {
3083                 tarc = E1000_READ_REG(hw, E1000_TARC(0));
3084                 tarc |= TARC_ERRATA_BIT;
3085                 if ( adapter->tx_num_queues > 1) {
3086                         tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX);
3087                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3088                         E1000_WRITE_REG(hw, E1000_TARC(1), tarc);
3089                 } else
3090                         E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
3091         }
3092
3093         if (adapter->tx_int_delay.value > 0)
3094                 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3095
3096         /* Program the Transmit Control Register */
3097         tctl = E1000_READ_REG(hw, E1000_TCTL);
3098         tctl &= ~E1000_TCTL_CT;
3099         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
3100                    (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
3101
3102         if (hw->mac.type >= e1000_82571)
3103                 tctl |= E1000_TCTL_MULR;
3104
3105         /* This write will effectively turn on the transmit unit. */
3106         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
3107
3108         /* SPT and KBL errata workarounds */
3109         if (hw->mac.type == e1000_pch_spt) {
3110                 u32 reg;
3111                 reg = E1000_READ_REG(hw, E1000_IOSFPC);
3112                 reg |= E1000_RCTL_RDMTS_HEX;
3113                 E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
3114                 /* i218-i219 Specification Update 1.5.4.5 */
3115                 reg = E1000_READ_REG(hw, E1000_TARC(0));
3116                 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3117                 reg |= E1000_TARC0_CB_MULTIQ_2_REQ;
3118                 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3119         }
3120 }
3121
3122 /*********************************************************************
3123  *
3124  *  Enable receive unit.
3125  *
3126  **********************************************************************/
3127
3128 static void
3129 em_initialize_receive_unit(if_ctx_t ctx)
3130 {
3131         struct adapter *adapter = iflib_get_softc(ctx);
3132         if_softc_ctx_t scctx = adapter->shared;
3133         struct ifnet *ifp = iflib_get_ifp(ctx);
3134         struct e1000_hw *hw = &adapter->hw;
3135         struct em_rx_queue *que;
3136         int i;
3137         u32 rctl, rxcsum, rfctl;
3138
3139         INIT_DEBUGOUT("em_initialize_receive_units: begin");
3140
3141         /*
3142          * Make sure receives are disabled while setting
3143          * up the descriptor ring
3144          */
3145         rctl = E1000_READ_REG(hw, E1000_RCTL);
3146         /* Do not disable if ever enabled on this hardware */
3147         if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
3148                 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3149
3150         /* Setup the Receive Control Register */
3151         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3152         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3153             E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3154             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3155
3156         /* Do not store bad packets */
3157         rctl &= ~E1000_RCTL_SBP;
3158
3159         /* Enable Long Packet receive */
3160         if (if_getmtu(ifp) > ETHERMTU)
3161                 rctl |= E1000_RCTL_LPE;
3162         else
3163                 rctl &= ~E1000_RCTL_LPE;
3164
3165         /* Strip the CRC */
3166         if (!em_disable_crc_stripping)
3167                 rctl |= E1000_RCTL_SECRC;
3168
3169         if (hw->mac.type >= e1000_82540) {
3170                 E1000_WRITE_REG(hw, E1000_RADV,
3171                     adapter->rx_abs_int_delay.value);
3172
3173                 /*
3174                  * Set the interrupt throttling rate. Value is calculated
3175                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
3176                  */
3177                 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
3178         }
3179         E1000_WRITE_REG(hw, E1000_RDTR, adapter->rx_int_delay.value);
3180
3181         /* Use extended rx descriptor formats */
3182         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3183         rfctl |= E1000_RFCTL_EXTEN;
3184         /*
3185          * When using MSI-X interrupts we need to throttle
3186          * using the EITR register (82574 only)
3187          */
3188         if (hw->mac.type == e1000_82574) {
3189                 for (int i = 0; i < 4; i++)
3190                         E1000_WRITE_REG(hw, E1000_EITR_82574(i),
3191                             DEFAULT_ITR);
3192                 /* Disable accelerated acknowledge */
3193                 rfctl |= E1000_RFCTL_ACK_DIS;
3194         }
3195         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3196
3197         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
3198         if (if_getcapenable(ifp) & IFCAP_RXCSUM &&
3199             hw->mac.type >= e1000_82543) {
3200                 if (adapter->tx_num_queues > 1) {
3201                         if (hw->mac.type >= igb_mac_min) {
3202                                 rxcsum |= E1000_RXCSUM_PCSD;
3203                                 if (hw->mac.type != e1000_82575)
3204                                         rxcsum |= E1000_RXCSUM_CRCOFL;
3205                         } else
3206                                 rxcsum |= E1000_RXCSUM_TUOFL |
3207                                         E1000_RXCSUM_IPOFL |
3208                                         E1000_RXCSUM_PCSD;
3209                 } else {
3210                         if (hw->mac.type >= igb_mac_min)
3211                                 rxcsum |= E1000_RXCSUM_IPPCSE;
3212                         else
3213                                 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
3214                         if (hw->mac.type > e1000_82575)
3215                                 rxcsum |= E1000_RXCSUM_CRCOFL;
3216                 }
3217         } else
3218                 rxcsum &= ~E1000_RXCSUM_TUOFL;
3219
3220         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
3221
3222         if (adapter->rx_num_queues > 1) {
3223                 if (hw->mac.type >= igb_mac_min)
3224                         igb_initialize_rss_mapping(adapter);
3225                 else
3226                         em_initialize_rss_mapping(adapter);
3227         }
3228
3229         /*
3230          * XXX TEMPORARY WORKAROUND: on some systems with 82573
3231          * long latencies are observed, like Lenovo X60. This
3232          * change eliminates the problem, but since having positive
3233          * values in RDTR is a known source of problems on other
3234          * platforms another solution is being sought.
3235          */
3236         if (hw->mac.type == e1000_82573)
3237                 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
3238
3239         for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3240                 struct rx_ring *rxr = &que->rxr;
3241                 /* Setup the Base and Length of the Rx Descriptor Ring */
3242                 u64 bus_addr = rxr->rx_paddr;
3243 #if 0
3244                 u32 rdt = adapter->rx_num_queues -1;  /* default */
3245 #endif
3246
3247                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
3248                     scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
3249                 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
3250                 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
3251                 /* Setup the Head and Tail Descriptor Pointers */
3252                 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
3253                 E1000_WRITE_REG(hw, E1000_RDT(i), 0);
3254         }
3255
3256         /*
3257          * Set PTHRESH for improved jumbo performance
3258          * According to 10.2.5.11 of Intel 82574 Datasheet,
3259          * RXDCTL(1) is written whenever RXDCTL(0) is written.
3260          * Only write to RXDCTL(1) if there is a need for different
3261          * settings.
3262          */
3263         if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan ||
3264             hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) {
3265                 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
3266                 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
3267         } else if (hw->mac.type == e1000_82574) {
3268                 for (int i = 0; i < adapter->rx_num_queues; i++) {
3269                         u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3270                         rxdctl |= 0x20; /* PTHRESH */
3271                         rxdctl |= 4 << 8; /* HTHRESH */
3272                         rxdctl |= 4 << 16;/* WTHRESH */
3273                         rxdctl |= 1 << 24; /* Switch to granularity */
3274                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3275                 }
3276         } else if (hw->mac.type >= igb_mac_min) {
3277                 u32 psize, srrctl = 0;
3278
3279                 if (if_getmtu(ifp) > ETHERMTU) {
3280                         /* Set maximum packet len */
3281                         if (adapter->rx_mbuf_sz <= 4096) {
3282                                 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3283                                 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3284                         } else if (adapter->rx_mbuf_sz > 4096) {
3285                                 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3286                                 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3287                         }
3288                         psize = scctx->isc_max_frame_size;
3289                         /* are we on a vlan? */
3290                         if (ifp->if_vlantrunk != NULL)
3291                                 psize += VLAN_TAG_SIZE;
3292                         E1000_WRITE_REG(hw, E1000_RLPML, psize);
3293                 } else {
3294                         srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3295                         rctl |= E1000_RCTL_SZ_2048;
3296                 }
3297
3298                 /*
3299                  * If TX flow control is disabled and there's >1 queue defined,
3300                  * enable DROP.
3301                  *
3302                  * This drops frames rather than hanging the RX MAC for all queues.
3303                  */
3304                 if ((adapter->rx_num_queues > 1) &&
3305                     (adapter->fc == e1000_fc_none ||
3306                      adapter->fc == e1000_fc_rx_pause)) {
3307                         srrctl |= E1000_SRRCTL_DROP_EN;
3308                 }
3309                         /* Setup the Base and Length of the Rx Descriptor Rings */
3310                 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) {
3311                         struct rx_ring *rxr = &que->rxr;
3312                         u64 bus_addr = rxr->rx_paddr;
3313                         u32 rxdctl;
3314
3315 #ifdef notyet
3316                         /* Configure for header split? -- ignore for now */
3317                         rxr->hdr_split = igb_header_split;
3318 #else
3319                         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3320 #endif
3321
3322                         E1000_WRITE_REG(hw, E1000_RDLEN(i),
3323                                         scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
3324                         E1000_WRITE_REG(hw, E1000_RDBAH(i),
3325                                         (uint32_t)(bus_addr >> 32));
3326                         E1000_WRITE_REG(hw, E1000_RDBAL(i),
3327                                         (uint32_t)bus_addr);
3328                         E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
3329                         /* Enable this Queue */
3330                         rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
3331                         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3332                         rxdctl &= 0xFFF00000;
3333                         rxdctl |= IGB_RX_PTHRESH;
3334                         rxdctl |= IGB_RX_HTHRESH << 8;
3335                         rxdctl |= IGB_RX_WTHRESH << 16;
3336                         E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
3337                 }
3338         } else if (hw->mac.type >= e1000_pch2lan) {
3339                 if (if_getmtu(ifp) > ETHERMTU)
3340                         e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
3341                 else
3342                         e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
3343         }
3344
3345         /* Make sure VLAN Filters are off */
3346         rctl &= ~E1000_RCTL_VFE;
3347
3348         if (hw->mac.type < igb_mac_min) {
3349                 if (adapter->rx_mbuf_sz == MCLBYTES)
3350                         rctl |= E1000_RCTL_SZ_2048;
3351                 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE)
3352                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
3353                 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE)
3354                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
3355
3356                 /* ensure we clear use DTYPE of 00 here */
3357                 rctl &= ~0x00000C00;
3358         }
3359
3360         /* Write out the settings */
3361         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3362
3363         return;
3364 }
3365
3366 static void
3367 em_if_vlan_register(if_ctx_t ctx, u16 vtag)
3368 {
3369         struct adapter *adapter = iflib_get_softc(ctx);
3370         u32 index, bit;
3371
3372         index = (vtag >> 5) & 0x7F;
3373         bit = vtag & 0x1F;
3374         adapter->shadow_vfta[index] |= (1 << bit);
3375         ++adapter->num_vlans;
3376 }
3377
3378 static void
3379 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
3380 {
3381         struct adapter *adapter = iflib_get_softc(ctx);
3382         u32 index, bit;
3383
3384         index = (vtag >> 5) & 0x7F;
3385         bit = vtag & 0x1F;
3386         adapter->shadow_vfta[index] &= ~(1 << bit);
3387         --adapter->num_vlans;
3388 }
3389
3390 static void
3391 em_setup_vlan_hw_support(struct adapter *adapter)
3392 {
3393         struct e1000_hw *hw = &adapter->hw;
3394         u32 reg;
3395
3396         /*
3397          * We get here thru init_locked, meaning
3398          * a soft reset, this has already cleared
3399          * the VFTA and other state, so if there
3400          * have been no vlan's registered do nothing.
3401          */
3402         if (adapter->num_vlans == 0)
3403                 return;
3404
3405         /*
3406          * A soft reset zero's out the VFTA, so
3407          * we need to repopulate it now.
3408          */
3409         for (int i = 0; i < EM_VFTA_SIZE; i++)
3410                 if (adapter->shadow_vfta[i] != 0)
3411                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
3412                             i, adapter->shadow_vfta[i]);
3413
3414         reg = E1000_READ_REG(hw, E1000_CTRL);
3415         reg |= E1000_CTRL_VME;
3416         E1000_WRITE_REG(hw, E1000_CTRL, reg);
3417
3418         /* Enable the Filter Table */
3419         reg = E1000_READ_REG(hw, E1000_RCTL);
3420         reg &= ~E1000_RCTL_CFIEN;
3421         reg |= E1000_RCTL_VFE;
3422         E1000_WRITE_REG(hw, E1000_RCTL, reg);
3423 }
3424
3425 static void
3426 em_if_intr_enable(if_ctx_t ctx)
3427 {
3428         struct adapter *adapter = iflib_get_softc(ctx);
3429         struct e1000_hw *hw = &adapter->hw;
3430         u32 ims_mask = IMS_ENABLE_MASK;
3431
3432         if (hw->mac.type == e1000_82574) {
3433                 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK);
3434                 ims_mask |= adapter->ims;
3435         }
3436         E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
3437 }
3438
3439 static void
3440 em_if_intr_disable(if_ctx_t ctx)
3441 {
3442         struct adapter *adapter = iflib_get_softc(ctx);
3443         struct e1000_hw *hw = &adapter->hw;
3444
3445         if (hw->mac.type == e1000_82574)
3446                 E1000_WRITE_REG(hw, EM_EIAC, 0);
3447         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3448 }
3449
3450 static void
3451 igb_if_intr_enable(if_ctx_t ctx)
3452 {
3453         struct adapter *adapter = iflib_get_softc(ctx);
3454         struct e1000_hw *hw = &adapter->hw;
3455         u32 mask;
3456
3457         if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) {
3458                 mask = (adapter->que_mask | adapter->link_mask);
3459                 E1000_WRITE_REG(hw, E1000_EIAC, mask);
3460                 E1000_WRITE_REG(hw, E1000_EIAM, mask);
3461                 E1000_WRITE_REG(hw, E1000_EIMS, mask);
3462                 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
3463         } else
3464                 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
3465         E1000_WRITE_FLUSH(hw);
3466 }
3467
3468 static void
3469 igb_if_intr_disable(if_ctx_t ctx)
3470 {
3471         struct adapter *adapter = iflib_get_softc(ctx);
3472         struct e1000_hw *hw = &adapter->hw;
3473
3474         if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) {
3475                 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff);
3476                 E1000_WRITE_REG(hw, E1000_EIAC, 0);
3477         }
3478         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3479         E1000_WRITE_FLUSH(hw);
3480 }
3481
3482 /*
3483  * Bit of a misnomer, what this really means is
3484  * to enable OS management of the system... aka
3485  * to disable special hardware management features
3486  */
3487 static void
3488 em_init_manageability(struct adapter *adapter)
3489 {
3490         /* A shared code workaround */
3491 #define E1000_82542_MANC2H E1000_MANC2H
3492         if (adapter->has_manage) {
3493                 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3494                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3495
3496                 /* disable hardware interception of ARP */
3497                 manc &= ~(E1000_MANC_ARP_EN);
3498
3499                 /* enable receiving management packets to the host */
3500                 manc |= E1000_MANC_EN_MNG2HOST;
3501 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3502 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3503                 manc2h |= E1000_MNG2HOST_PORT_623;
3504                 manc2h |= E1000_MNG2HOST_PORT_664;
3505                 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3506                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3507         }
3508 }
3509
3510 /*
3511  * Give control back to hardware management
3512  * controller if there is one.
3513  */
3514 static void
3515 em_release_manageability(struct adapter *adapter)
3516 {
3517         if (adapter->has_manage) {
3518                 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3519
3520                 /* re-enable hardware interception of ARP */
3521                 manc |= E1000_MANC_ARP_EN;
3522                 manc &= ~E1000_MANC_EN_MNG2HOST;
3523
3524                 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3525         }
3526 }
3527
3528 /*
3529  * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
3530  * For ASF and Pass Through versions of f/w this means
3531  * that the driver is loaded. For AMT version type f/w
3532  * this means that the network i/f is open.
3533  */
3534 static void
3535 em_get_hw_control(struct adapter *adapter)
3536 {
3537         u32 ctrl_ext, swsm;
3538
3539         if (adapter->vf_ifp)
3540                 return;
3541
3542         if (adapter->hw.mac.type == e1000_82573) {
3543                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3544                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3545                     swsm | E1000_SWSM_DRV_LOAD);
3546                 return;
3547         }
3548         /* else */
3549         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3550         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3551             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3552 }
3553
3554 /*
3555  * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3556  * For ASF and Pass Through versions of f/w this means that
3557  * the driver is no longer loaded. For AMT versions of the
3558  * f/w this means that the network i/f is closed.
3559  */
3560 static void
3561 em_release_hw_control(struct adapter *adapter)
3562 {
3563         u32 ctrl_ext, swsm;
3564
3565         if (!adapter->has_manage)
3566                 return;
3567
3568         if (adapter->hw.mac.type == e1000_82573) {
3569                 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3570                 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3571                     swsm & ~E1000_SWSM_DRV_LOAD);
3572                 return;
3573         }
3574         /* else */
3575         ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3576         E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3577             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3578         return;
3579 }
3580
3581 static int
3582 em_is_valid_ether_addr(u8 *addr)
3583 {
3584         char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3585
3586         if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3587                 return (FALSE);
3588         }
3589
3590         return (TRUE);
3591 }
3592
3593 /*
3594 ** Parse the interface capabilities with regard
3595 ** to both system management and wake-on-lan for
3596 ** later use.
3597 */
3598 static void
3599 em_get_wakeup(if_ctx_t ctx)
3600 {
3601         struct adapter *adapter = iflib_get_softc(ctx);
3602         device_t dev = iflib_get_dev(ctx);
3603         u16 eeprom_data = 0, device_id, apme_mask;
3604
3605         adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
3606         apme_mask = EM_EEPROM_APME;
3607
3608         switch (adapter->hw.mac.type) {
3609         case e1000_82542:
3610         case e1000_82543:
3611                 break;
3612         case e1000_82544:
3613                 e1000_read_nvm(&adapter->hw,
3614                     NVM_INIT_CONTROL2_REG, 1, &eeprom_data);
3615                 apme_mask = EM_82544_APME;
3616                 break;
3617         case e1000_82546:
3618         case e1000_82546_rev_3:
3619                 if (adapter->hw.bus.func == 1) {
3620                         e1000_read_nvm(&adapter->hw,
3621                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3622                         break;
3623                 } else
3624                         e1000_read_nvm(&adapter->hw,
3625                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3626                 break;
3627         case e1000_82573:
3628         case e1000_82583:
3629                 adapter->has_amt = TRUE;
3630                 /* FALLTHROUGH */
3631         case e1000_82571:
3632         case e1000_82572:
3633         case e1000_80003es2lan:
3634                 if (adapter->hw.bus.func == 1) {
3635                         e1000_read_nvm(&adapter->hw,
3636                             NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3637                         break;
3638                 } else
3639                         e1000_read_nvm(&adapter->hw,
3640                             NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3641                 break;
3642         case e1000_ich8lan:
3643         case e1000_ich9lan:
3644         case e1000_ich10lan:
3645         case e1000_pchlan:
3646         case e1000_pch2lan:
3647         case e1000_pch_lpt:
3648         case e1000_pch_spt:
3649         case e1000_82575:       /* listing all igb devices */
3650         case e1000_82576:
3651         case e1000_82580:
3652         case e1000_i350:
3653         case e1000_i354:
3654         case e1000_i210:
3655         case e1000_i211:
3656         case e1000_vfadapt:
3657         case e1000_vfadapt_i350:
3658                 apme_mask = E1000_WUC_APME;
3659                 adapter->has_amt = TRUE;
3660                 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
3661                 break;
3662         default:
3663                 e1000_read_nvm(&adapter->hw,
3664                     NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
3665                 break;
3666         }
3667         if (eeprom_data & apme_mask)
3668                 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
3669         /*
3670          * We have the eeprom settings, now apply the special cases
3671          * where the eeprom may be wrong or the board won't support
3672          * wake on lan on a particular port
3673          */
3674         device_id = pci_get_device(dev);
3675         switch (device_id) {
3676         case E1000_DEV_ID_82546GB_PCIE:
3677                 adapter->wol = 0;
3678                 break;
3679         case E1000_DEV_ID_82546EB_FIBER:
3680         case E1000_DEV_ID_82546GB_FIBER:
3681                 /* Wake events only supported on port A for dual fiber
3682                  * regardless of eeprom setting */
3683                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3684                     E1000_STATUS_FUNC_1)
3685                         adapter->wol = 0;
3686                 break;
3687         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
3688                 /* if quad port adapter, disable WoL on all but port A */
3689                 if (global_quad_port_a != 0)
3690                         adapter->wol = 0;
3691                 /* Reset for multiple quad port adapters */
3692                 if (++global_quad_port_a == 4)
3693                         global_quad_port_a = 0;
3694                 break;
3695         case E1000_DEV_ID_82571EB_FIBER:
3696                 /* Wake events only supported on port A for dual fiber
3697                  * regardless of eeprom setting */
3698                 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
3699                     E1000_STATUS_FUNC_1)
3700                         adapter->wol = 0;
3701                 break;
3702         case E1000_DEV_ID_82571EB_QUAD_COPPER:
3703         case E1000_DEV_ID_82571EB_QUAD_FIBER:
3704         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
3705                 /* if quad port adapter, disable WoL on all but port A */
3706                 if (global_quad_port_a != 0)
3707                         adapter->wol = 0;
3708                 /* Reset for multiple quad port adapters */
3709                 if (++global_quad_port_a == 4)
3710                         global_quad_port_a = 0;
3711                 break;
3712         }
3713         return;
3714 }
3715
3716
3717 /*
3718  * Enable PCI Wake On Lan capability
3719  */
3720 static void
3721 em_enable_wakeup(if_ctx_t ctx)
3722 {
3723         struct adapter *adapter = iflib_get_softc(ctx);
3724         device_t dev = iflib_get_dev(ctx);
3725         if_t ifp = iflib_get_ifp(ctx);
3726         int error = 0;
3727         u32 pmc, ctrl, ctrl_ext, rctl;
3728         u16 status;
3729
3730         if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
3731                 return;
3732
3733         /*
3734          * Determine type of Wakeup: note that wol
3735          * is set with all bits on by default.
3736          */
3737         if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
3738                 adapter->wol &= ~E1000_WUFC_MAG;
3739
3740         if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
3741                 adapter->wol &= ~E1000_WUFC_EX;
3742
3743         if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
3744                 adapter->wol &= ~E1000_WUFC_MC;
3745         else {
3746                 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3747                 rctl |= E1000_RCTL_MPE;
3748                 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3749         }
3750
3751         if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC)))
3752                 goto pme;
3753
3754         /* Advertise the wakeup capability */
3755         ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
3756         ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3);
3757         E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
3758
3759         /* Keep the laser running on Fiber adapters */
3760         if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3761             adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
3762                 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3763                 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
3764                 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext);
3765         }
3766
3767         if ((adapter->hw.mac.type == e1000_ich8lan) ||
3768             (adapter->hw.mac.type == e1000_pchlan) ||
3769             (adapter->hw.mac.type == e1000_ich9lan) ||
3770             (adapter->hw.mac.type == e1000_ich10lan))
3771                 e1000_suspend_workarounds_ich8lan(&adapter->hw);
3772
3773         if ( adapter->hw.mac.type >= e1000_pchlan) {
3774                 error = em_enable_phy_wakeup(adapter);
3775                 if (error)
3776                         goto pme;
3777         } else {
3778                 /* Enable wakeup by the MAC */
3779                 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
3780                 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
3781         }
3782
3783         if (adapter->hw.phy.type == e1000_phy_igp_3)
3784                 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
3785
3786 pme:
3787         status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
3788         status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3789         if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
3790                 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3791         pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
3792
3793         return;
3794 }
3795
3796 /*
3797  * WOL in the newer chipset interfaces (pchlan)
3798  * require thing to be copied into the phy
3799  */
3800 static int
3801 em_enable_phy_wakeup(struct adapter *adapter)
3802 {
3803         struct e1000_hw *hw = &adapter->hw;
3804         u32 mreg, ret = 0;
3805         u16 preg;
3806
3807         /* copy MAC RARs to PHY RARs */
3808         e1000_copy_rx_addrs_to_phy_ich8lan(hw);
3809
3810         /* copy MAC MTA to PHY MTA */
3811         for (int i = 0; i < hw->mac.mta_reg_count; i++) {
3812                 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
3813                 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF));
3814                 e1000_write_phy_reg(hw, BM_MTA(i) + 1,
3815                     (u16)((mreg >> 16) & 0xFFFF));
3816         }
3817
3818         /* configure PHY Rx Control register */
3819         e1000_read_phy_reg(hw, BM_RCTL, &preg);
3820         mreg = E1000_READ_REG(hw, E1000_RCTL);
3821         if (mreg & E1000_RCTL_UPE)
3822                 preg |= BM_RCTL_UPE;
3823         if (mreg & E1000_RCTL_MPE)
3824                 preg |= BM_RCTL_MPE;
3825         preg &= ~(BM_RCTL_MO_MASK);
3826         if (mreg & E1000_RCTL_MO_3)
3827                 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
3828                                 << BM_RCTL_MO_SHIFT);
3829         if (mreg & E1000_RCTL_BAM)
3830                 preg |= BM_RCTL_BAM;
3831         if (mreg & E1000_RCTL_PMCF)
3832                 preg |= BM_RCTL_PMCF;
3833         mreg = E1000_READ_REG(hw, E1000_CTRL);
3834         if (mreg & E1000_CTRL_RFCE)
3835                 preg |= BM_RCTL_RFCE;
3836         e1000_write_phy_reg(hw, BM_RCTL, preg);
3837
3838         /* enable PHY wakeup in MAC register */
3839         E1000_WRITE_REG(hw, E1000_WUC,
3840             E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME);
3841         E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol);
3842
3843         /* configure and enable PHY wakeup in PHY registers */
3844         e1000_write_phy_reg(hw, BM_WUFC, adapter->wol);
3845         e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN);
3846
3847         /* activate PHY wakeup */
3848         ret = hw->phy.ops.acquire(hw);
3849         if (ret) {
3850                 printf("Could not acquire PHY\n");
3851                 return ret;
3852         }
3853         e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3854                                  (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3855         ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg);
3856         if (ret) {
3857                 printf("Could not read PHY page 769\n");
3858                 goto out;
3859         }
3860         preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
3861         ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg);
3862         if (ret)
3863                 printf("Could not set PHY Host Wakeup bit\n");
3864 out:
3865         hw->phy.ops.release(hw);
3866
3867         return ret;
3868 }
3869
3870 static void
3871 em_if_led_func(if_ctx_t ctx, int onoff)
3872 {
3873         struct adapter *adapter = iflib_get_softc(ctx);
3874
3875         if (onoff) {
3876                 e1000_setup_led(&adapter->hw);
3877                 e1000_led_on(&adapter->hw);
3878         } else {
3879                 e1000_led_off(&adapter->hw);
3880                 e1000_cleanup_led(&adapter->hw);
3881         }
3882 }
3883
3884 /*
3885  * Disable the L0S and L1 LINK states
3886  */
3887 static void
3888 em_disable_aspm(struct adapter *adapter)
3889 {
3890         int base, reg;
3891         u16 link_cap,link_ctrl;
3892         device_t dev = adapter->dev;
3893
3894         switch (adapter->hw.mac.type) {
3895         case e1000_82573:
3896         case e1000_82574:
3897         case e1000_82583:
3898                 break;
3899         default:
3900                 return;
3901         }
3902         if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0)
3903                 return;
3904         reg = base + PCIER_LINK_CAP;
3905         link_cap = pci_read_config(dev, reg, 2);
3906         if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0)
3907                 return;
3908         reg = base + PCIER_LINK_CTL;
3909         link_ctrl = pci_read_config(dev, reg, 2);
3910         link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
3911         pci_write_config(dev, reg, link_ctrl, 2);
3912         return;
3913 }
3914
3915 /**********************************************************************
3916  *
3917  *  Update the board statistics counters.
3918  *
3919  **********************************************************************/
3920 static void
3921 em_update_stats_counters(struct adapter *adapter)
3922 {
3923         u64 prev_xoffrxc = adapter->stats.xoffrxc;
3924
3925         if(adapter->hw.phy.media_type == e1000_media_type_copper ||
3926            (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3927                 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
3928                 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
3929         }
3930         adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
3931         adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
3932         adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
3933         adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
3934
3935         adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
3936         adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
3937         adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
3938         adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
3939         adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
3940         adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
3941         adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
3942         adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
3943         /*
3944          ** For watchdog management we need to know if we have been
3945          ** paused during the last interval, so capture that here.
3946         */
3947         if (adapter->stats.xoffrxc != prev_xoffrxc)
3948                 adapter->shared->isc_pause_frames = 1;
3949         adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
3950         adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
3951         adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
3952         adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
3953         adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
3954         adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
3955         adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
3956         adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
3957         adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
3958         adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
3959         adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
3960         adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
3961
3962         /* For the 64-bit byte counters the low dword must be read first. */
3963         /* Both registers clear on the read of the high dword */
3964
3965         adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) +
3966             ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32);
3967         adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) +
3968             ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32);
3969
3970         adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
3971         adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
3972         adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
3973         adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
3974         adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
3975
3976         adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
3977         adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
3978
3979         adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
3980         adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
3981         adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
3982         adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
3983         adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
3984         adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
3985         adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
3986         adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
3987         adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
3988         adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
3989
3990         /* Interrupt Counts */
3991
3992         adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC);
3993         adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC);
3994         adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC);
3995         adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC);
3996         adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC);
3997         adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC);
3998         adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC);
3999         adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC);
4000         adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC);
4001
4002         if (adapter->hw.mac.type >= e1000_82543) {
4003                 adapter->stats.algnerrc +=
4004                 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
4005                 adapter->stats.rxerrc +=
4006                 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
4007                 adapter->stats.tncrs +=
4008                 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
4009                 adapter->stats.cexterr +=
4010                 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
4011                 adapter->stats.tsctc +=
4012                 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
4013                 adapter->stats.tsctfc +=
4014                 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
4015         }
4016 }
4017
4018 static uint64_t
4019 em_if_get_counter(if_ctx_t ctx, ift_counter cnt)
4020 {
4021         struct adapter *adapter = iflib_get_softc(ctx);
4022         struct ifnet *ifp = iflib_get_ifp(ctx);
4023
4024         switch (cnt) {
4025         case IFCOUNTER_COLLISIONS:
4026                 return (adapter->stats.colc);
4027         case IFCOUNTER_IERRORS:
4028                 return (adapter->dropped_pkts + adapter->stats.rxerrc +
4029                     adapter->stats.crcerrs + adapter->stats.algnerrc +
4030                     adapter->stats.ruc + adapter->stats.roc +
4031                     adapter->stats.mpc + adapter->stats.cexterr);
4032         case IFCOUNTER_OERRORS:
4033                 return (adapter->stats.ecol + adapter->stats.latecol +
4034                     adapter->watchdog_events);
4035         default:
4036                 return (if_get_counter_default(ifp, cnt));
4037         }
4038 }
4039
4040 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized
4041  * @ctx: iflib context
4042  * @event: event code to check
4043  *
4044  * Defaults to returning true for unknown events.
4045  *
4046  * @returns true if iflib needs to reinit the interface
4047  */
4048 static bool
4049 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
4050 {
4051         switch (event) {
4052         case IFLIB_RESTART_VLAN_CONFIG:
4053         default:
4054                 return (true);
4055         }
4056 }
4057
4058 /* Export a single 32-bit register via a read-only sysctl. */
4059 static int
4060 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
4061 {
4062         struct adapter *adapter;
4063         u_int val;
4064
4065         adapter = oidp->oid_arg1;
4066         val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2);
4067         return (sysctl_handle_int(oidp, &val, 0, req));
4068 }
4069
4070 /*
4071  * Add sysctl variables, one per statistic, to the system.
4072  */
4073 static void
4074 em_add_hw_stats(struct adapter *adapter)
4075 {
4076         device_t dev = iflib_get_dev(adapter->ctx);
4077         struct em_tx_queue *tx_que = adapter->tx_queues;
4078         struct em_rx_queue *rx_que = adapter->rx_queues;
4079
4080         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
4081         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
4082         struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
4083         struct e1000_hw_stats *stats = &adapter->stats;
4084
4085         struct sysctl_oid *stat_node, *queue_node, *int_node;
4086         struct sysctl_oid_list *stat_list, *queue_list, *int_list;
4087
4088 #define QUEUE_NAME_LEN 32
4089         char namebuf[QUEUE_NAME_LEN];
4090
4091         /* Driver Statistics */
4092         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
4093                         CTLFLAG_RD, &adapter->dropped_pkts,
4094                         "Driver dropped packets");
4095         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
4096                         CTLFLAG_RD, &adapter->link_irq,
4097                         "Link MSI-X IRQ Handled");
4098         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
4099                         CTLFLAG_RD, &adapter->rx_overruns,
4100                         "RX overruns");
4101         SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
4102                         CTLFLAG_RD, &adapter->watchdog_events,
4103                         "Watchdog timeouts");
4104         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
4105             CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
4106             adapter, E1000_CTRL, em_sysctl_reg_handler, "IU",
4107             "Device Control Register");
4108         SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
4109             CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
4110             adapter, E1000_RCTL, em_sysctl_reg_handler, "IU",
4111             "Receiver Control Register");
4112         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
4113                         CTLFLAG_RD, &adapter->hw.fc.high_water, 0,
4114                         "Flow Control High Watermark");
4115         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
4116                         CTLFLAG_RD, &adapter->hw.fc.low_water, 0,
4117                         "Flow Control Low Watermark");
4118
4119         for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) {
4120                 struct tx_ring *txr = &tx_que->txr;
4121                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
4122                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4123                     CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name");
4124                 queue_list = SYSCTL_CHILDREN(queue_node);
4125
4126                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
4127                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4128                     E1000_TDH(txr->me), em_sysctl_reg_handler, "IU",
4129                     "Transmit Descriptor Head");
4130                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
4131                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4132                     E1000_TDT(txr->me), em_sysctl_reg_handler, "IU",
4133                     "Transmit Descriptor Tail");
4134                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
4135                                 CTLFLAG_RD, &txr->tx_irq,
4136                                 "Queue MSI-X Transmit Interrupts");
4137         }
4138
4139         for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) {
4140                 struct rx_ring *rxr = &rx_que->rxr;
4141                 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
4142                 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
4143                     CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name");
4144                 queue_list = SYSCTL_CHILDREN(queue_node);
4145
4146                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
4147                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4148                     E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU",
4149                     "Receive Descriptor Head");
4150                 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
4151                     CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter,
4152                     E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU",
4153                     "Receive Descriptor Tail");
4154                 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
4155                                 CTLFLAG_RD, &rxr->rx_irq,
4156                                 "Queue MSI-X Receive Interrupts");
4157         }
4158
4159         /* MAC stats get their own sub node */
4160
4161         stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
4162             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics");
4163         stat_list = SYSCTL_CHILDREN(stat_node);
4164
4165         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
4166                         CTLFLAG_RD, &stats->ecol,
4167                         "Excessive collisions");
4168         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
4169                         CTLFLAG_RD, &stats->scc,
4170                         "Single collisions");
4171         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
4172                         CTLFLAG_RD, &stats->mcc,
4173                         "Multiple collisions");
4174         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
4175                         CTLFLAG_RD, &stats->latecol,
4176                         "Late collisions");
4177         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
4178                         CTLFLAG_RD, &stats->colc,
4179                         "Collision Count");
4180         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
4181                         CTLFLAG_RD, &adapter->stats.symerrs,
4182                         "Symbol Errors");
4183         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
4184                         CTLFLAG_RD, &adapter->stats.sec,
4185                         "Sequence Errors");
4186         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
4187                         CTLFLAG_RD, &adapter->stats.dc,
4188                         "Defer Count");
4189         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
4190                         CTLFLAG_RD, &adapter->stats.mpc,
4191                         "Missed Packets");
4192         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
4193                         CTLFLAG_RD, &adapter->stats.rnbc,
4194                         "Receive No Buffers");
4195         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
4196                         CTLFLAG_RD, &adapter->stats.ruc,
4197                         "Receive Undersize");
4198         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
4199                         CTLFLAG_RD, &adapter->stats.rfc,
4200                         "Fragmented Packets Received ");
4201         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
4202                         CTLFLAG_RD, &adapter->stats.roc,
4203                         "Oversized Packets Received");
4204         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
4205                         CTLFLAG_RD, &adapter->stats.rjc,
4206                         "Recevied Jabber");
4207         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
4208                         CTLFLAG_RD, &adapter->stats.rxerrc,
4209                         "Receive Errors");
4210         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
4211                         CTLFLAG_RD, &adapter->stats.crcerrs,
4212                         "CRC errors");
4213         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
4214                         CTLFLAG_RD, &adapter->stats.algnerrc,
4215                         "Alignment Errors");
4216         /* On 82575 these are collision counts */
4217         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
4218                         CTLFLAG_RD, &adapter->stats.cexterr,
4219                         "Collision/Carrier extension errors");
4220         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
4221                         CTLFLAG_RD, &adapter->stats.xonrxc,
4222                         "XON Received");
4223         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
4224                         CTLFLAG_RD, &adapter->stats.xontxc,
4225                         "XON Transmitted");
4226         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
4227                         CTLFLAG_RD, &adapter->stats.xoffrxc,
4228                         "XOFF Received");
4229         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
4230                         CTLFLAG_RD, &adapter->stats.xofftxc,
4231                         "XOFF Transmitted");
4232
4233         /* Packet Reception Stats */
4234         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
4235                         CTLFLAG_RD, &adapter->stats.tpr,
4236                         "Total Packets Received ");
4237         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
4238                         CTLFLAG_RD, &adapter->stats.gprc,
4239                         "Good Packets Received");
4240         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
4241                         CTLFLAG_RD, &adapter->stats.bprc,
4242                         "Broadcast Packets Received");
4243         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
4244                         CTLFLAG_RD, &adapter->stats.mprc,
4245                         "Multicast Packets Received");
4246         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
4247                         CTLFLAG_RD, &adapter->stats.prc64,
4248                         "64 byte frames received ");
4249         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
4250                         CTLFLAG_RD, &adapter->stats.prc127,
4251                         "65-127 byte frames received");
4252         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
4253                         CTLFLAG_RD, &adapter->stats.prc255,
4254                         "128-255 byte frames received");
4255         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
4256                         CTLFLAG_RD, &adapter->stats.prc511,
4257                         "256-511 byte frames received");
4258         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
4259                         CTLFLAG_RD, &adapter->stats.prc1023,
4260                         "512-1023 byte frames received");
4261         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
4262                         CTLFLAG_RD, &adapter->stats.prc1522,
4263                         "1023-1522 byte frames received");
4264         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
4265                         CTLFLAG_RD, &adapter->stats.gorc,
4266                         "Good Octets Received");
4267
4268         /* Packet Transmission Stats */
4269         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
4270                         CTLFLAG_RD, &adapter->stats.gotc,
4271                         "Good Octets Transmitted");
4272         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
4273                         CTLFLAG_RD, &adapter->stats.tpt,
4274                         "Total Packets Transmitted");
4275         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
4276                         CTLFLAG_RD, &adapter->stats.gptc,
4277                         "Good Packets Transmitted");
4278         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
4279                         CTLFLAG_RD, &adapter->stats.bptc,
4280                         "Broadcast Packets Transmitted");
4281         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
4282                         CTLFLAG_RD, &adapter->stats.mptc,
4283                         "Multicast Packets Transmitted");
4284         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
4285                         CTLFLAG_RD, &adapter->stats.ptc64,
4286                         "64 byte frames transmitted ");
4287         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
4288                         CTLFLAG_RD, &adapter->stats.ptc127,
4289                         "65-127 byte frames transmitted");
4290         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
4291                         CTLFLAG_RD, &adapter->stats.ptc255,
4292                         "128-255 byte frames transmitted");
4293         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
4294                         CTLFLAG_RD, &adapter->stats.ptc511,
4295                         "256-511 byte frames transmitted");
4296         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
4297                         CTLFLAG_RD, &adapter->stats.ptc1023,
4298                         "512-1023 byte frames transmitted");
4299         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
4300                         CTLFLAG_RD, &adapter->stats.ptc1522,
4301                         "1024-1522 byte frames transmitted");
4302         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
4303                         CTLFLAG_RD, &adapter->stats.tsctc,
4304                         "TSO Contexts Transmitted");
4305         SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
4306                         CTLFLAG_RD, &adapter->stats.tsctfc,
4307                         "TSO Contexts Failed");
4308
4309
4310         /* Interrupt Stats */
4311
4312         int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
4313             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics");
4314         int_list = SYSCTL_CHILDREN(int_node);
4315
4316         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
4317                         CTLFLAG_RD, &adapter->stats.iac,
4318                         "Interrupt Assertion Count");
4319
4320         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
4321                         CTLFLAG_RD, &adapter->stats.icrxptc,
4322                         "Interrupt Cause Rx Pkt Timer Expire Count");
4323
4324         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
4325                         CTLFLAG_RD, &adapter->stats.icrxatc,
4326                         "Interrupt Cause Rx Abs Timer Expire Count");
4327
4328         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
4329                         CTLFLAG_RD, &adapter->stats.ictxptc,
4330                         "Interrupt Cause Tx Pkt Timer Expire Count");
4331
4332         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
4333                         CTLFLAG_RD, &adapter->stats.ictxatc,
4334                         "Interrupt Cause Tx Abs Timer Expire Count");
4335
4336         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
4337                         CTLFLAG_RD, &adapter->stats.ictxqec,
4338                         "Interrupt Cause Tx Queue Empty Count");
4339
4340         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
4341                         CTLFLAG_RD, &adapter->stats.ictxqmtc,
4342                         "Interrupt Cause Tx Queue Min Thresh Count");
4343
4344         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
4345                         CTLFLAG_RD, &adapter->stats.icrxdmtc,
4346                         "Interrupt Cause Rx Desc Min Thresh Count");
4347
4348         SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
4349                         CTLFLAG_RD, &adapter->stats.icrxoc,
4350                         "Interrupt Cause Receiver Overrun Count");
4351 }
4352
4353 /**********************************************************************
4354  *
4355  *  This routine provides a way to dump out the adapter eeprom,
4356  *  often a useful debug/service tool. This only dumps the first
4357  *  32 words, stuff that matters is in that extent.
4358  *
4359  **********************************************************************/
4360 static int
4361 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
4362 {
4363         struct adapter *adapter = (struct adapter *)arg1;
4364         int error;
4365         int result;
4366
4367         result = -1;
4368         error = sysctl_handle_int(oidp, &result, 0, req);
4369
4370         if (error || !req->newptr)
4371                 return (error);
4372
4373         /*
4374          * This value will cause a hex dump of the
4375          * first 32 16-bit words of the EEPROM to
4376          * the screen.
4377          */
4378         if (result == 1)
4379                 em_print_nvm_info(adapter);
4380
4381         return (error);
4382 }
4383
4384 static void
4385 em_print_nvm_info(struct adapter *adapter)
4386 {
4387         u16 eeprom_data;
4388         int i, j, row = 0;
4389
4390         /* Its a bit crude, but it gets the job done */
4391         printf("\nInterface EEPROM Dump:\n");
4392         printf("Offset\n0x0000  ");
4393         for (i = 0, j = 0; i < 32; i++, j++) {
4394                 if (j == 8) { /* Make the offset block */
4395                         j = 0; ++row;
4396                         printf("\n0x00%x0  ",row);
4397                 }
4398                 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
4399                 printf("%04x ", eeprom_data);
4400         }
4401         printf("\n");
4402 }
4403
4404 static int
4405 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4406 {
4407         struct em_int_delay_info *info;
4408         struct adapter *adapter;
4409         u32 regval;
4410         int error, usecs, ticks;
4411
4412         info = (struct em_int_delay_info *) arg1;
4413         usecs = info->value;
4414         error = sysctl_handle_int(oidp, &usecs, 0, req);
4415         if (error != 0 || req->newptr == NULL)
4416                 return (error);
4417         if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535))
4418                 return (EINVAL);
4419         info->value = usecs;
4420         ticks = EM_USECS_TO_TICKS(usecs);
4421         if (info->offset == E1000_ITR)  /* units are 256ns here */
4422                 ticks *= 4;
4423
4424         adapter = info->adapter;
4425
4426         regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
4427         regval = (regval & ~0xffff) | (ticks & 0xffff);
4428         /* Handle a few special cases. */
4429         switch (info->offset) {
4430         case E1000_RDTR:
4431                 break;
4432         case E1000_TIDV:
4433                 if (ticks == 0) {
4434                         adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
4435                         /* Don't write 0 into the TIDV register. */
4436                         regval++;
4437                 } else
4438                         adapter->txd_cmd |= E1000_TXD_CMD_IDE;
4439                 break;
4440         }
4441         E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
4442         return (0);
4443 }
4444
4445 static void
4446 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
4447         const char *description, struct em_int_delay_info *info,
4448         int offset, int value)
4449 {
4450         info->adapter = adapter;
4451         info->offset = offset;
4452         info->value = value;
4453         SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev),
4454             SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
4455             OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
4456             info, 0, em_sysctl_int_delay, "I", description);
4457 }
4458
4459 /*
4460  * Set flow control using sysctl:
4461  * Flow control values:
4462  *      0 - off
4463  *      1 - rx pause
4464  *      2 - tx pause
4465  *      3 - full
4466  */
4467 static int
4468 em_set_flowcntl(SYSCTL_HANDLER_ARGS)
4469 {
4470         int error;
4471         static int input = 3; /* default is full */
4472         struct adapter  *adapter = (struct adapter *) arg1;
4473
4474         error = sysctl_handle_int(oidp, &input, 0, req);
4475
4476         if ((error) || (req->newptr == NULL))
4477                 return (error);
4478
4479         if (input == adapter->fc) /* no change? */
4480                 return (error);
4481
4482         switch (input) {
4483         case e1000_fc_rx_pause:
4484         case e1000_fc_tx_pause:
4485         case e1000_fc_full:
4486         case e1000_fc_none:
4487                 adapter->hw.fc.requested_mode = input;
4488                 adapter->fc = input;
4489                 break;
4490         default:
4491                 /* Do nothing */
4492                 return (error);
4493         }
4494
4495         adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
4496         e1000_force_mac_fc(&adapter->hw);
4497         return (error);
4498 }
4499
4500 /*
4501  * Manage Energy Efficient Ethernet:
4502  * Control values:
4503  *     0/1 - enabled/disabled
4504  */
4505 static int
4506 em_sysctl_eee(SYSCTL_HANDLER_ARGS)
4507 {
4508         struct adapter *adapter = (struct adapter *) arg1;
4509         int error, value;
4510
4511         value = adapter->hw.dev_spec.ich8lan.eee_disable;
4512         error = sysctl_handle_int(oidp, &value, 0, req);
4513         if (error || req->newptr == NULL)
4514                 return (error);
4515         adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0);
4516         em_if_init(adapter->ctx);
4517
4518         return (0);
4519 }
4520
4521 static int
4522 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
4523 {
4524         struct adapter *adapter;
4525         int error;
4526         int result;
4527
4528         result = -1;
4529         error = sysctl_handle_int(oidp, &result, 0, req);
4530
4531         if (error || !req->newptr)
4532                 return (error);
4533
4534         if (result == 1) {
4535                 adapter = (struct adapter *) arg1;
4536                 em_print_debug_info(adapter);
4537         }
4538
4539         return (error);
4540 }
4541
4542 static int
4543 em_get_rs(SYSCTL_HANDLER_ARGS)
4544 {
4545         struct adapter *adapter = (struct adapter *) arg1;
4546         int error;
4547         int result;
4548
4549         result = 0;
4550         error = sysctl_handle_int(oidp, &result, 0, req);
4551
4552         if (error || !req->newptr || result != 1)
4553                 return (error);
4554         em_dump_rs(adapter);
4555
4556         return (error);
4557 }
4558
4559 static void
4560 em_if_debug(if_ctx_t ctx)
4561 {
4562         em_dump_rs(iflib_get_softc(ctx));
4563 }
4564
4565 /*
4566  * This routine is meant to be fluid, add whatever is
4567  * needed for debugging a problem.  -jfv
4568  */
4569 static void
4570 em_print_debug_info(struct adapter *adapter)
4571 {
4572         device_t dev = iflib_get_dev(adapter->ctx);
4573         struct ifnet *ifp = iflib_get_ifp(adapter->ctx);
4574         struct tx_ring *txr = &adapter->tx_queues->txr;
4575         struct rx_ring *rxr = &adapter->rx_queues->rxr;
4576
4577         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
4578                 printf("Interface is RUNNING ");
4579         else
4580                 printf("Interface is NOT RUNNING\n");
4581
4582         if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
4583                 printf("and INACTIVE\n");
4584         else
4585                 printf("and ACTIVE\n");
4586
4587         for (int i = 0; i < adapter->tx_num_queues; i++, txr++) {
4588                 device_printf(dev, "TX Queue %d ------\n", i);
4589                 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
4590                         E1000_READ_REG(&adapter->hw, E1000_TDH(i)),
4591                         E1000_READ_REG(&adapter->hw, E1000_TDT(i)));
4592
4593         }
4594         for (int j=0; j < adapter->rx_num_queues; j++, rxr++) {
4595                 device_printf(dev, "RX Queue %d ------\n", j);
4596                 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
4597                         E1000_READ_REG(&adapter->hw, E1000_RDH(j)),
4598                         E1000_READ_REG(&adapter->hw, E1000_RDT(j)));
4599         }
4600 }
4601
4602 /*
4603  * 82574 only:
4604  * Write a new value to the EEPROM increasing the number of MSI-X
4605  * vectors from 3 to 5, for proper multiqueue support.
4606  */
4607 static void
4608 em_enable_vectors_82574(if_ctx_t ctx)
4609 {
4610         struct adapter *adapter = iflib_get_softc(ctx);
4611         struct e1000_hw *hw = &adapter->hw;
4612         device_t dev = iflib_get_dev(ctx);
4613         u16 edata;
4614
4615         e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4616         if (bootverbose)
4617                 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata);
4618         if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) {
4619                 device_printf(dev, "Writing to eeprom: increasing "
4620                     "reported MSI-X vectors from 3 to 5...\n");
4621                 edata &= ~(EM_NVM_MSIX_N_MASK);
4622                 edata |= 4 << EM_NVM_MSIX_N_SHIFT;
4623                 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata);
4624                 e1000_update_nvm_checksum(hw);
4625                 device_printf(dev, "Writing to eeprom: done\n");
4626         }
4627 }