1 /******************************************************************************
3 Copyright (c) 2001-2013, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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32 ******************************************************************************/
35 #ifndef _IGB_H_DEFINED_
36 #define _IGB_H_DEFINED_
41 * IGB_TXD: Maximum number of Transmit Descriptors
43 * This value is the number of transmit descriptors allocated by the driver.
44 * Increasing this value allows the driver to queue more transmits. Each
45 * descriptor is 16 bytes.
46 * Since TDLEN should be multiple of 128bytes, the number of transmit
47 * desscriptors should meet the following condition.
48 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
50 #define IGB_MIN_TXD 256
51 #define IGB_DEFAULT_TXD 1024
52 #define IGB_MAX_TXD 4096
55 * IGB_RXD: Maximum number of Receive Descriptors
57 * This value is the number of receive descriptors allocated by the driver.
58 * Increasing this value allows the driver to buffer more incoming packets.
59 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
60 * descriptor. The maximum MTU size is 16110.
61 * Since TDLEN should be multiple of 128bytes, the number of transmit
62 * desscriptors should meet the following condition.
63 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
65 #define IGB_MIN_RXD 256
66 #define IGB_DEFAULT_RXD 1024
67 #define IGB_MAX_RXD 4096
70 * IGB_TIDV - Transmit Interrupt Delay Value
71 * Valid Range: 0-65535 (0=off)
73 * This value delays the generation of transmit interrupts in units of
74 * 1.024 microseconds. Transmit interrupt reduction can improve CPU
75 * efficiency if properly tuned for specific network traffic. If the
76 * system is reporting dropped transmits, this value may be set too high
77 * causing the driver to run out of available transmit descriptors.
82 * IGB_TADV - Transmit Absolute Interrupt Delay Value
83 * Valid Range: 0-65535 (0=off)
85 * This value, in units of 1.024 microseconds, limits the delay in which a
86 * transmit interrupt is generated. Useful only if IGB_TIDV is non-zero,
87 * this value ensures that an interrupt is generated after the initial
88 * packet is sent on the wire within the set amount of time. Proper tuning,
89 * along with IGB_TIDV, may improve traffic throughput in specific
95 * IGB_RDTR - Receive Interrupt Delay Timer (Packet Timer)
96 * Valid Range: 0-65535 (0=off)
98 * This value delays the generation of receive interrupts in units of 1.024
99 * microseconds. Receive interrupt reduction can improve CPU efficiency if
100 * properly tuned for specific network traffic. Increasing this value adds
101 * extra latency to frame reception and can end up decreasing the throughput
102 * of TCP traffic. If the system is reporting dropped receives, this value
103 * may be set too high, causing the driver to run out of available receive
106 * CAUTION: When setting IGB_RDTR to a value other than 0, adapters
107 * may hang (stop transmitting) under certain network conditions.
108 * If this occurs a WATCHDOG message is logged in the system
109 * event log. In addition, the controller is automatically reset,
110 * restoring the network connection. To eliminate the potential
111 * for the hang ensure that IGB_RDTR is set to 0.
116 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
117 * Valid Range: 0-65535 (0=off)
119 * This value, in units of 1.024 microseconds, limits the delay in which a
120 * receive interrupt is generated. Useful only if IGB_RDTR is non-zero,
121 * this value ensures that an interrupt is generated after the initial
122 * packet is received within the set amount of time. Proper tuning,
123 * along with IGB_RDTR, may improve traffic throughput in specific network
129 * This parameter controls the duration of transmit watchdog timer.
131 #define IGB_WATCHDOG (10 * hz)
134 * This parameter controls when the driver calls the routine to reclaim
135 * transmit descriptors. Cleaning earlier seems a win.
137 #define IGB_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 2)
140 * This parameter controls whether or not autonegotation is enabled.
141 * 0 - Disable autonegotiation
142 * 1 - Enable autonegotiation
144 #define DO_AUTO_NEG 1
147 * This parameter control whether or not the driver will wait for
148 * autonegotiation to complete.
149 * 1 - Wait for autonegotiation to complete
150 * 0 - Don't wait for autonegotiation to complete
152 #define WAIT_FOR_AUTO_NEG_DEFAULT 0
154 /* Tunables -- End */
156 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
157 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
160 #define AUTO_ALL_MODES 0
162 /* PHY master/slave setting */
163 #define IGB_MASTER_SLAVE e1000_ms_hw_default
165 /* Support AutoMediaDetect for Marvell M88 PHY in i354 */
166 #define IGB_MEDIA_RESET (1 << 0)
169 * Micellaneous constants
171 #define IGB_VENDOR_ID 0x8086
173 #define IGB_JUMBO_PBA 0x00000028
174 #define IGB_DEFAULT_PBA 0x00000030
175 #define IGB_SMARTSPEED_DOWNSHIFT 3
176 #define IGB_SMARTSPEED_MAX 15
177 #define IGB_MAX_LOOP 10
179 #define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : \
180 ((hw->mac.type <= e1000_82576) ? 16 : 8))
181 #define IGB_RX_HTHRESH 8
182 #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
183 adapter->msix_mem) ? 1 : 4)
185 #define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
186 #define IGB_TX_HTHRESH 1
187 #define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \
188 adapter->msix_mem) ? 1 : 16)
190 #define MAX_NUM_MULTICAST_ADDRESSES 128
191 #define PCI_ANY_ID (~0U)
192 #define ETHER_ALIGN 2
193 #define IGB_TX_BUFFER_SIZE ((uint32_t) 1514)
194 #define IGB_FC_PAUSE_TIME 0x0680
195 #define IGB_EEPROM_APME 0x400;
196 /* Queue minimum free for use */
197 #define IGB_QUEUE_THRESHOLD (adapter->num_tx_desc / 8)
200 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
201 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
202 * also optimize cache line size effect. H/W supports up to cache line size 128.
204 #define IGB_DBA_ALIGN 128
206 #define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */
208 /* PCI Config defines */
209 #define IGB_MSIX_BAR 3
211 /* Defines for printing debug information */
213 #define DEBUG_IOCTL 0
216 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
217 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
218 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
219 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
220 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
221 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
222 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
223 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
224 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
226 #define IGB_MAX_SCATTER 64
227 #define IGB_VFTA_SIZE 128
228 #define IGB_BR_SIZE 4096 /* ring buf size */
229 #define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header))
230 #define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */
231 #define IGB_TXPBSIZE 20408
232 #define IGB_HDR_BUF 128
233 #define IGB_PKTTYPE_MASK 0x0000FFF0
234 #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */
236 #define ETH_ADDR_LEN 6
238 /* Offload bits in mbuf flag */
239 #if __FreeBSD_version >= 800000
240 #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP)
242 #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP)
245 /* Define the starting Interrupt rate per Queue */
246 #define IGB_INTS_PER_SEC 8000
247 #define IGB_DEFAULT_ITR ((1000000/IGB_INTS_PER_SEC) << 2)
249 #define IGB_LINK_ITR 2000
250 #define I210_LINK_DELAY 1000
252 /* Precision Time Sync (IEEE 1588) defines */
253 #define ETHERTYPE_IEEE1588 0x88F7
254 #define PICOSECS_PER_TICK 20833
255 #define TSYNC_PORT 319 /* UDP port for the protocol */
258 * Bus dma allocation structure used by
259 * e1000_dma_malloc and e1000_dma_free.
261 struct igb_dma_alloc {
262 bus_addr_t dma_paddr;
264 bus_dma_tag_t dma_tag;
265 bus_dmamap_t dma_map;
266 bus_dma_segment_t dma_seg;
272 ** Driver queue struct: this is the interrupt container
273 ** for the associated tx and rx ring.
276 struct adapter *adapter;
277 u32 msix; /* This queue's MSIX vector */
278 u32 eims; /* This queue's EIMS bit */
280 struct resource *res;
284 struct task que_task;
285 struct taskqueue *tq;
290 * The transmit ring, one per queue
293 struct adapter *adapter;
297 union e1000_adv_tx_desc *tx_base;
298 struct igb_tx_buf *tx_buffers;
299 struct igb_dma_alloc txdma;
300 volatile u16 tx_avail;
307 IGB_QUEUE_WORKING = 2,
309 IGB_QUEUE_DEPLETED = 8,
314 #ifndef IGB_LEGACY_TX
316 struct task txq_task;
318 u32 bytes; /* used for AIM */
321 unsigned long tso_tx;
322 unsigned long no_tx_map_avail;
323 unsigned long no_tx_dma_setup;
329 * Receive ring: one per queue
332 struct adapter *adapter;
334 struct igb_dma_alloc rxdma;
335 union e1000_adv_rx_desc *rx_base;
344 struct igb_rx_buf *rx_buffers;
345 bus_dma_tag_t htag; /* dma tag for rx head */
346 bus_dma_tag_t ptag; /* dma tag for rx packet */
348 * First/last mbuf pointers, for
349 * collecting multisegment RX packets.
360 u64 rx_split_packets;
370 struct e1000_osdep osdep;
372 struct cdev *led_dev;
374 struct resource *pci_mem;
375 struct resource *msix_mem;
379 * Interrupt resources: this set is
380 * either used for legacy, or for Link
384 struct resource *res;
386 struct ifmedia media;
387 struct callout timer;
394 eventhandler_tag vlan_attach;
395 eventhandler_tag vlan_detach;
401 ** Shadow VFTA table, this is needed because
402 ** the real vlan filter table gets cleared during
403 ** a soft reset and the driver needs to be able
406 u32 shadow_vfta[IGB_VFTA_SIZE];
408 /* Info about the interface */
410 u32 fc; /* local flow ctrl setting */
411 int advertise; /* link speeds */
425 /* Mbuf cluster size */
428 /* Support for pluggable optics */
430 struct task link_task; /* Link tasklet */
431 struct task mod_task; /* SFP tasklet */
432 struct task msf_task; /* Multispeed Fiber */
433 struct taskqueue *tq;
437 ** This is the irq holder, it has
438 ** and RX/TX pair or rings associated
441 struct igb_queue *queues;
445 * Allocated at run time, an array of rings.
447 struct tx_ring *tx_rings;
452 * Allocated at run time, an array of rings.
454 struct rx_ring *rx_rings;
458 /* Multicast array memory */
461 /* Misc stats maintained by the driver */
462 unsigned long dropped_pkts;
463 unsigned long mbuf_defrag_failed;
464 unsigned long mbuf_header_failed;
465 unsigned long mbuf_packet_failed;
466 unsigned long no_tx_dma_setup;
467 unsigned long watchdog_events;
468 unsigned long link_irq;
469 unsigned long rx_overruns;
470 unsigned long device_control;
471 unsigned long rx_control;
472 unsigned long int_mask;
473 unsigned long eint_mask;
474 unsigned long packet_buf_alloc_rx;
475 unsigned long packet_buf_alloc_tx;
476 /* Used in pf and vf */
482 int rx_process_limit;
483 u16 vf_ifp; /* a VF interface */
484 bool in_detach; /* Used only in igb_ioctl */
488 /* ******************************************************************************
491 * This array contains the list of Subvendor/Subdevice IDs on which the driver
494 * ******************************************************************************/
495 typedef struct _igb_vendor_info_t {
496 unsigned int vendor_id;
497 unsigned int device_id;
498 unsigned int subvendor_id;
499 unsigned int subdevice_id;
504 union e1000_adv_tx_desc *eop;
512 bus_dmamap_t hmap; /* bus_dma map for header */
513 bus_dmamap_t pmap; /* bus_dma map for packet */
517 ** Find the number of unrefreshed RX descriptors
520 igb_rx_unrefreshed(struct rx_ring *rxr)
522 struct adapter *adapter = rxr->adapter;
524 if (rxr->next_to_check > rxr->next_to_refresh)
525 return (rxr->next_to_check - rxr->next_to_refresh - 1);
527 return ((adapter->num_rx_desc + rxr->next_to_check) -
528 rxr->next_to_refresh - 1);
531 #define IGB_CORE_LOCK_INIT(_sc, _name) \
532 mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF)
533 #define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)
534 #define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx)
535 #define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx)
536 #define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED)
538 #define IGB_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx)
539 #define IGB_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx)
540 #define IGB_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx)
541 #define IGB_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx)
542 #define IGB_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
544 #define IGB_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx)
545 #define IGB_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx)
546 #define IGB_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx)
547 #define IGB_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rx_mtx, MA_OWNED)
549 #define UPDATE_VF_REG(reg, last, cur) \
551 u32 new = E1000_READ_REG(hw, reg); \
553 cur += 0x100000000LL; \
555 cur &= 0xFFFFFFFF00000000LL; \
559 #if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504
561 drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br)
564 if (ALTQ_IS_ENABLED(&ifp->if_snd))
567 return (!buf_ring_empty(br));
571 #endif /* _IGB_H_DEFINED_ */