2 * Copyright (c) 1995, David Greenman
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
32 * adapters. By David Greenman, 29-April-1993
34 * Currently supports the Western Digital/SMC 8003 and 8013 series,
35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
36 * and a variety of similar clones.
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/sockio.h>
46 #include <sys/kernel.h>
47 #include <sys/socket.h>
48 #include <sys/syslog.h>
52 #include <machine/bus.h>
54 #include <machine/resource.h>
56 #include <net/ethernet.h>
58 #include <net/if_arp.h>
59 #include <net/if_dl.h>
60 #include <net/if_mib.h>
61 #include <net/if_media.h>
64 #include <dev/mii/mii.h>
65 #include <dev/mii/miivar.h>
71 #include <net/bridge.h>
74 #include <machine/md_var.h>
76 #include <dev/ed/if_edreg.h>
77 #include <dev/ed/if_edvar.h>
79 devclass_t ed_devclass;
81 static void ed_init __P((void *));
82 static int ed_ioctl __P((struct ifnet *, u_long, caddr_t));
83 static void ed_start __P((struct ifnet *));
84 static void ed_reset __P((struct ifnet *));
85 static void ed_watchdog __P((struct ifnet *));
87 static void ed_tick __P((void *));
90 static void ds_getmcaf __P((struct ed_softc *, u_int32_t *));
92 static void ed_get_packet __P((struct ed_softc *, char *, /* u_short */ int));
94 static __inline void ed_rint __P((struct ed_softc *));
95 static __inline void ed_xmit __P((struct ed_softc *));
96 static __inline char * ed_ring_copy __P((struct ed_softc *, char *, char *,
98 static void ed_hpp_set_physical_link __P((struct ed_softc *));
99 static void ed_hpp_readmem __P((struct ed_softc *, int, unsigned char *,
101 static void ed_hpp_writemem __P((struct ed_softc *, unsigned char *,
102 /* u_short */ int, /* u_short */ int));
103 static u_short ed_hpp_write_mbufs __P((struct ed_softc *, struct mbuf *,
106 static u_short ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *,
109 static void ed_setrcr __P((struct ed_softc *));
111 static u_int32_t ds_crc __P((u_char *ep));
114 * Interrupt conversion table for WD/SMC ASIC/83C584
116 static unsigned short ed_intr_val[] = {
128 * Interrupt conversion table for 83C790
130 static unsigned short ed_790_intr_val[] = {
142 * Interrupt conversion table for the HP PC LAN+
145 static unsigned short ed_hpp_intr_val[] = {
165 * Generic probe routine for testing for the existance of a DS8390.
166 * Must be called after the NIC has just been reset. This routine
167 * works by looking at certain register values that are guaranteed
168 * to be initialized a certain way after power-up or reset. Seems
169 * not to currently work on the 83C690.
173 * Register reset bits set bits
174 * Command Register (CR) TXP, STA RD2, STP
175 * Interrupt Status (ISR) RST
176 * Interrupt Mask (IMR) All bits
177 * Data Control (DCR) LAS
178 * Transmit Config. (TCR) LB1, LB0
180 * We only look at the CR and ISR registers, however, because looking at
181 * the others would require changing register pages (which would be
182 * intrusive if this isn't an 8390).
184 * Return 1 if 8390 was found, 0 if not.
188 ed_probe_generic8390(sc)
191 if ((ed_nic_inb(sc, ED_P0_CR) &
192 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
193 (ED_CR_RD2 | ED_CR_STP))
195 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
202 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
205 ed_probe_WD80x3_generic(dev, flags, intr_vals)
208 unsigned short *intr_vals[];
210 struct ed_softc *sc = device_get_softc(dev);
213 u_int memsize, maddr;
214 u_char iptr, isa16bit, sum, totalsum;
215 u_long conf_maddr, conf_msize, irq, junk;
217 sc->chip_type = ED_CHIP_TYPE_DP8390;
219 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
220 totalsum = ED_WD_ROM_CHECKSUM_TOTAL_TOSH_ETHER;
221 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_POW);
225 totalsum = ED_WD_ROM_CHECKSUM_TOTAL;
228 * Attempt to do a checksum over the station address PROM. If it
229 * fails, it's probably not a SMC/WD board. There is a problem with
230 * this, though: some clone WD boards don't pass the checksum test.
231 * Danpex boards for one.
233 for (sum = 0, i = 0; i < 8; ++i)
234 sum += ed_asic_inb(sc, ED_WD_PROM + i);
236 if (sum != totalsum) {
239 * Checksum is invalid. This often happens with cheap WD8003E
240 * clones. In this case, the checksum byte (the eighth byte)
241 * seems to always be zero.
243 if (ed_asic_inb(sc, ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
244 ed_asic_inb(sc, ED_WD_PROM + 7) != 0)
247 /* reset card to force it into a known state. */
248 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER)
249 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
251 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST);
254 ed_asic_outb(sc, ED_WD_MSR, ed_asic_inb(sc, ED_WD_MSR) & ~ED_WD_MSR_RST);
255 /* wait in the case this card is reading its EEROM */
258 sc->vendor = ED_VENDOR_WD_SMC;
259 sc->type = ed_asic_inb(sc, ED_WD_CARD_ID);
262 * Set initial values for width/size.
267 case ED_TYPE_WD8003S:
268 sc->type_str = "WD8003S";
270 case ED_TYPE_WD8003E:
271 sc->type_str = "WD8003E";
273 case ED_TYPE_WD8003EB:
274 sc->type_str = "WD8003EB";
276 case ED_TYPE_WD8003W:
277 sc->type_str = "WD8003W";
279 case ED_TYPE_WD8013EBT:
280 sc->type_str = "WD8013EBT";
284 case ED_TYPE_WD8013W:
285 sc->type_str = "WD8013W";
289 case ED_TYPE_WD8013EP: /* also WD8003EP */
290 if (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) {
293 sc->type_str = "WD8013EP";
295 sc->type_str = "WD8003EP";
298 case ED_TYPE_WD8013WC:
299 sc->type_str = "WD8013WC";
303 case ED_TYPE_WD8013EBP:
304 sc->type_str = "WD8013EBP";
308 case ED_TYPE_WD8013EPC:
309 sc->type_str = "WD8013EPC";
313 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */
314 case ED_TYPE_SMC8216T:
315 if (sc->type == ED_TYPE_SMC8216C) {
316 sc->type_str = "SMC8216/SMC8216C";
318 sc->type_str = "SMC8216T";
321 ed_asic_outb(sc, ED_WD790_HWR,
322 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
323 switch (ed_asic_inb(sc, ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
324 case ED_WD790_RAR_SZ64:
327 case ED_WD790_RAR_SZ32:
330 case ED_WD790_RAR_SZ16:
333 case ED_WD790_RAR_SZ8:
334 /* 8216 has 16K shared mem -- 8416 has 8K */
335 if (sc->type == ED_TYPE_SMC8216C) {
336 sc->type_str = "SMC8416C/SMC8416BT";
338 sc->type_str = "SMC8416T";
343 ed_asic_outb(sc, ED_WD790_HWR,
344 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
347 sc->chip_type = ED_CHIP_TYPE_WD790;
349 case ED_TYPE_TOSHIBA1:
350 sc->type_str = "Toshiba1";
354 case ED_TYPE_TOSHIBA4:
355 sc->type_str = "Toshiba4";
365 * Make some adjustments to initial values depending on what is found
368 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
369 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
370 && ((ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
375 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
376 &conf_maddr, &conf_msize);
381 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
382 sc->type, sc->type_str, isa16bit, memsize, conf_msize);
383 for (i = 0; i < 8; i++)
384 printf("%x -> %x\n", i, ed_asic_inb(sc, i));
388 * Allow the user to override the autoconfiguration
391 memsize = conf_msize;
394 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) {
395 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n",
396 maddr, maddr + memsize);
401 * (note that if the user specifies both of the following flags that
402 * '8bit' mode intentionally has precedence)
404 if (flags & ED_FLAGS_FORCE_16BIT_MODE)
406 if (flags & ED_FLAGS_FORCE_8BIT_MODE)
410 * If possible, get the assigned interrupt number from the card and
413 if ((sc->type & ED_WD_SOFTCONFIG) &&
414 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
417 * Assemble together the encoded interrupt number.
419 iptr = (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_IR2) |
420 ((ed_asic_inb(sc, ED_WD_IRR) &
421 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
424 * If no interrupt specified (or "?"), use what the board tells us.
426 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
428 if (error && intr_vals[0] != NULL) {
429 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
430 intr_vals[0][iptr], 1);
436 * Enable the interrupt.
438 ed_asic_outb(sc, ED_WD_IRR,
439 ed_asic_inb(sc, ED_WD_IRR) | ED_WD_IRR_IEN);
441 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
442 ed_asic_outb(sc, ED_WD790_HWR,
443 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
444 iptr = (((ed_asic_inb(sc, ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
445 (ed_asic_inb(sc, ED_WD790_GCR) &
446 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
447 ed_asic_outb(sc, ED_WD790_HWR,
448 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
451 * If no interrupt specified (or "?"), use what the board tells us.
453 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
455 if (error && intr_vals[1] != NULL) {
456 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
457 intr_vals[1][iptr], 1);
465 ed_asic_outb(sc, ED_WD790_ICR,
466 ed_asic_inb(sc, ED_WD790_ICR) | ED_WD790_ICR_EIL);
468 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
471 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n",
475 sc->isa16bit = isa16bit;
478 error = ed_alloc_memory(dev, 0, memsize);
480 printf("*** ed_alloc_memory() failed! (%d)\n", error);
483 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
486 * allocate one xmit buffer if < 16k, two buffers otherwise
488 if ((memsize < 16384) ||
489 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
494 sc->tx_page_start = ED_WD_PAGE_OFFSET;
495 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt;
496 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE;
497 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start);
498 sc->mem_size = memsize;
499 sc->mem_end = sc->mem_start + memsize;
502 * Get station address from on-board ROM
504 for (i = 0; i < ETHER_ADDR_LEN; ++i)
505 sc->arpcom.ac_enaddr[i] = ed_asic_inb(sc, ED_WD_PROM + i);
508 * Set upper address bits and 8/16 bit access to shared memory.
511 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
512 sc->wd_laar_proto = ed_asic_inb(sc, ED_WD_LAAR);
514 sc->wd_laar_proto = ED_WD_LAAR_L16EN |
515 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
518 * Enable 16bit access
520 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto |
523 if (((sc->type & ED_WD_SOFTCONFIG) ||
524 (sc->type == ED_TYPE_TOSHIBA1) ||
525 (sc->type == ED_TYPE_TOSHIBA4) ||
526 (sc->type == ED_TYPE_WD8013EBT)) &&
527 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
528 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
530 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto);
535 * Set address and enable interface shared memory.
537 if (sc->chip_type != ED_CHIP_TYPE_WD790) {
538 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
539 ed_asic_outb(sc, ED_WD_MSR + 1,
540 ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
541 ed_asic_outb(sc, ED_WD_MSR + 2,
542 ((kvtop(sc->mem_start) >> 16) & 0x0f));
543 ed_asic_outb(sc, ED_WD_MSR,
544 ED_WD_MSR_MENB | ED_WD_MSR_POW);
546 ed_asic_outb(sc, ED_WD_MSR,
547 ((kvtop(sc->mem_start) >> 13) &
548 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
550 sc->cr_proto = ED_CR_RD2;
552 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
553 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH));
554 ed_asic_outb(sc, ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
555 ((kvtop(sc->mem_start) >> 11) & 0x40) |
556 (ed_asic_inb(sc, ED_WD790_RAR) & 0xb0));
557 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
562 printf("starting memory performance test at 0x%x, size %d...\n",
563 sc->mem_start, memsize*16384);
564 for (i = 0; i < 16384; i++)
565 bzero(sc->mem_start, memsize);
566 printf("***DONE***\n");
570 * Now zero memory and verify that it is clear
572 bzero(sc->mem_start, memsize);
574 for (i = 0; i < memsize; ++i) {
575 if (sc->mem_start[i]) {
576 device_printf(dev, "failed to clear shared memory at %lx - check configuration\n",
577 kvtop(sc->mem_start + i));
580 * Disable 16 bit access to shared memory
583 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
584 ed_asic_outb(sc, ED_WD_MSR, 0x00);
586 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
594 * Disable 16bit access to shared memory - we leave it
595 * disabled so that 1) machines reboot properly when the board
596 * is set 16 bit mode and there are conflicting 8bit
597 * devices/ROMS in the same 128k address space as this boards
598 * shared memory. and 2) so that other 8 bit devices with
599 * shared memory can be used in this 128k region, too.
602 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
603 ed_asic_outb(sc, ED_WD_MSR, 0x00);
605 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
612 ed_probe_WD80x3(dev, port_rid, flags)
617 struct ed_softc *sc = device_get_softc(dev);
619 static unsigned short *intr_vals[] = {ed_intr_val, ed_790_intr_val};
621 error = ed_alloc_port(dev, port_rid, ED_WD_IO_PORTS);
625 sc->asic_offset = ED_WD_ASIC_OFFSET;
626 sc->nic_offset = ED_WD_NIC_OFFSET;
628 return ed_probe_WD80x3_generic(dev, flags, intr_vals);
632 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
635 ed_probe_3Com(dev, port_rid, flags)
640 struct ed_softc *sc = device_get_softc(dev);
645 u_long conf_maddr, conf_msize, irq, junk;
647 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS);
651 sc->asic_offset = ED_3COM_ASIC_OFFSET;
652 sc->nic_offset = ED_3COM_NIC_OFFSET;
655 * Verify that the kernel configured I/O address matches the board
658 switch (ed_asic_inb(sc, ED_3COM_BCFR)) {
659 case ED_3COM_BCFR_300:
660 if (rman_get_start(sc->port_res) != 0x300)
663 case ED_3COM_BCFR_310:
664 if (rman_get_start(sc->port_res) != 0x310)
667 case ED_3COM_BCFR_330:
668 if (rman_get_start(sc->port_res) != 0x330)
671 case ED_3COM_BCFR_350:
672 if (rman_get_start(sc->port_res) != 0x350)
675 case ED_3COM_BCFR_250:
676 if (rman_get_start(sc->port_res) != 0x250)
679 case ED_3COM_BCFR_280:
680 if (rman_get_start(sc->port_res) != 0x280)
683 case ED_3COM_BCFR_2A0:
684 if (rman_get_start(sc->port_res) != 0x2a0)
687 case ED_3COM_BCFR_2E0:
688 if (rman_get_start(sc->port_res) != 0x2e0)
695 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
696 &conf_maddr, &conf_msize);
701 * Verify that the kernel shared memory address matches the board
702 * configured address.
704 switch (ed_asic_inb(sc, ED_3COM_PCFR)) {
705 case ED_3COM_PCFR_DC000:
706 if (conf_maddr != 0xdc000)
709 case ED_3COM_PCFR_D8000:
710 if (conf_maddr != 0xd8000)
713 case ED_3COM_PCFR_CC000:
714 if (conf_maddr != 0xcc000)
717 case ED_3COM_PCFR_C8000:
718 if (conf_maddr != 0xc8000)
727 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
728 * sequence because it'll lock up if the cable isn't connected if we
731 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
734 * Wait for a while, then un-reset it
739 * The 3Com ASIC defaults to rather strange settings for the CR after
740 * a reset - it's important to set it again after the following outb
741 * (this is done when we map the PROM below).
743 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
746 * Wait a bit for the NIC to recover from the reset
750 sc->vendor = ED_VENDOR_3COM;
751 sc->type_str = "3c503";
753 sc->cr_proto = ED_CR_RD2;
756 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
762 * Get station address from on-board ROM
766 * First, map ethernet address PROM over the top of where the NIC
767 * registers normally appear.
769 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
771 for (i = 0; i < ETHER_ADDR_LEN; ++i)
772 sc->arpcom.ac_enaddr[i] = ed_nic_inb(sc, i);
775 * Unmap PROM - select NIC registers. The proper setting of the
776 * tranceiver is set in ed_init so that the attach code is given a
777 * chance to set the default based on a compile-time config option
779 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
782 * Determine if this is an 8bit or 16bit board
786 * select page 0 registers
788 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
791 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
794 ed_nic_outb(sc, ED_P0_DCR, 0);
797 * select page 2 registers
799 ed_nic_outb(sc, ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
802 * The 3c503 forces the WTS bit to a one if this is a 16bit board
804 if (ed_nic_inb(sc, ED_P2_DCR) & ED_DCR_WTS)
810 * select page 0 registers
812 ed_nic_outb(sc, ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
814 error = ed_alloc_memory(dev, 0, memsize);
818 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
819 sc->mem_size = memsize;
820 sc->mem_end = sc->mem_start + memsize;
823 * We have an entire 8k window to put the transmit buffers on the
824 * 16bit boards. But since the 16bit 3c503's shared memory is only
825 * fast enough to overlap the loading of one full-size packet, trying
826 * to load more than 2 buffers can actually leave the transmitter idle
827 * during the load. So 2 seems the best value. (Although a mix of
828 * variable-sized packets might change this assumption. Nonetheless,
829 * we optimize for linear transfers of same-size packets.)
832 if (flags & ED_FLAGS_NO_MULTI_BUFFERING)
837 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
838 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
839 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
840 ED_3COM_RX_PAGE_OFFSET_16BIT;
841 sc->mem_ring = sc->mem_start;
844 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
845 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
846 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
847 ED_3COM_TX_PAGE_OFFSET_8BIT;
848 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
851 sc->isa16bit = isa16bit;
854 * Initialize GA page start/stop registers. Probably only needed if
855 * doing DMA, but what the hell.
857 ed_asic_outb(sc, ED_3COM_PSTR, sc->rec_page_start);
858 ed_asic_outb(sc, ED_3COM_PSPR, sc->rec_page_stop);
861 * Set IRQ. 3c503 only allows a choice of irq 2-5.
863 error = bus_get_resource(dev, SYS_RES_IRQ, 0, &irq, &junk);
870 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
873 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
876 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
879 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
882 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n",
888 * Initialize GA configuration register. Set bank and enable shared
891 ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
895 * Initialize "Vector Pointer" registers. These gawd-awful things are
896 * compared to 20 bits of the address on ISA, and if they match, the
897 * shared memory is disabled. We set them to 0xffff0...allegedly the
900 ed_asic_outb(sc, ED_3COM_VPTR2, 0xff);
901 ed_asic_outb(sc, ED_3COM_VPTR1, 0xff);
902 ed_asic_outb(sc, ED_3COM_VPTR0, 0x00);
905 * Zero memory and verify that it is clear
907 bzero(sc->mem_start, memsize);
909 for (i = 0; i < memsize; ++i)
910 if (sc->mem_start[i]) {
911 device_printf(dev, "failed to clear shared memory at %lx - check configuration\n",
912 kvtop(sc->mem_start + i));
919 * Probe and vendor-specific initialization routine for NE1000/2000 boards
922 ed_probe_Novell_generic(dev, flags)
926 struct ed_softc *sc = device_get_softc(dev);
928 u_char romdata[16], tmp;
929 static char test_pattern[32] = "THIS is A memory TEST pattern";
930 char test_buffer[32];
932 /* XXX - do Novell-specific probe here */
934 /* Reset the board */
935 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
936 ed_asic_outb(sc, ED_NOVELL_RESET, 0);
939 tmp = ed_asic_inb(sc, ED_NOVELL_RESET);
942 * I don't know if this is necessary; probably cruft leftover from
943 * Clarkson packet driver code. Doesn't do a thing on the boards I've
944 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is
945 * non-invasive...but some boards don't seem to reset and I don't have
946 * complete documentation on what the 'right' thing to do is...so we
947 * do the invasive thing for now. Yuck.]
949 ed_asic_outb(sc, ED_NOVELL_RESET, tmp);
953 * This is needed because some NE clones apparently don't reset the
954 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
955 * - this makes the probe invasive! ...Done against my better
958 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
962 /* Make sure that we really have an 8390 based board */
963 if (!ed_probe_generic8390(sc))
966 sc->vendor = ED_VENDOR_NOVELL;
968 sc->cr_proto = ED_CR_RD2;
971 * Test the ability to read and write to the NIC memory. This has the
972 * side affect of determining if this is an NE1000 or an NE2000.
976 * This prevents packets from being stored in the NIC memory when the
977 * readmem routine turns on the start bit in the CR.
979 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
981 /* Temporarily initialize DCR for byte operations */
982 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
984 ed_nic_outb(sc, ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
985 ed_nic_outb(sc, ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
990 * Write a test pattern in byte mode. If this fails, then there
991 * probably isn't any memory at 8k - which likely means that the board
994 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
995 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
997 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
998 sc->type = ED_TYPE_NE1000;
999 sc->type_str = "NE1000";
1002 /* neither an NE1000 nor a Linksys - try NE2000 */
1003 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
1004 ed_nic_outb(sc, ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
1005 ed_nic_outb(sc, ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
1010 * Write a test pattern in word mode. If this also fails, then
1011 * we don't know what this board is.
1013 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
1014 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
1015 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1016 sc->type = ED_TYPE_NE2000;
1017 sc->type_str = "NE2000";
1024 /* 8k of memory plus an additional 8k if 16bit */
1025 memsize = 8192 + sc->isa16bit * 8192;
1027 #if 0 /* probably not useful - NE boards only come two ways */
1028 /* allow kernel config file overrides */
1029 if (isa_dev->id_msize)
1030 memsize = isa_dev->id_msize;
1033 sc->mem_size = memsize;
1035 /* NIC memory doesn't start at zero on an NE board */
1036 /* The start address is tied to the bus width */
1037 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1038 sc->mem_end = sc->mem_start + memsize;
1039 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1041 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
1042 int x, i, mstart = 0, msize = 0;
1043 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
1045 for (i = 0; i < ED_PAGE_SIZE; i++)
1048 /* Clear all the memory. */
1049 for (x = 1; x < 256; x++)
1050 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE);
1052 /* Search for the start of RAM. */
1053 for (x = 1; x < 256; x++) {
1054 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1055 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1056 for (i = 0; i < ED_PAGE_SIZE; i++)
1058 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1059 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1060 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) {
1061 mstart = x * ED_PAGE_SIZE;
1062 msize = ED_PAGE_SIZE;
1069 device_printf(dev, "Cannot find start of RAM.\n");
1072 /* Search for the start of RAM. */
1073 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) {
1074 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1075 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1076 for (i = 0; i < ED_PAGE_SIZE; i++)
1078 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1079 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1080 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0)
1081 msize += ED_PAGE_SIZE;
1091 device_printf(dev, "Cannot find any RAM, start : %d, x = %d.\n", mstart, x);
1094 device_printf(dev, "RAM start at %d, size : %d.\n", mstart, msize);
1096 sc->mem_size = msize;
1097 sc->mem_start = (caddr_t) mstart;
1098 sc->mem_end = (caddr_t) (msize + mstart);
1099 sc->tx_page_start = mstart / ED_PAGE_SIZE;
1103 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1106 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))
1111 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1112 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1114 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1116 ed_pio_readmem(sc, 0, romdata, 16);
1117 for (n = 0; n < ETHER_ADDR_LEN; n++)
1118 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)];
1120 if ((ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) &&
1121 (sc->arpcom.ac_enaddr[2] == 0x86)) {
1122 sc->type_str = "Gateway AT";
1125 /* clear any pending interrupts that might have occurred above */
1126 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1132 ed_probe_Novell(dev, port_rid, flags)
1137 struct ed_softc *sc = device_get_softc(dev);
1140 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS);
1144 sc->asic_offset = ED_NOVELL_ASIC_OFFSET;
1145 sc->nic_offset = ED_NOVELL_NIC_OFFSET;
1147 return ed_probe_Novell_generic(dev, flags);
1150 #define ED_HPP_TEST_SIZE 16
1153 * Probe and vendor specific initialization for the HP PC Lan+ Cards.
1154 * (HP Part nos: 27247B and 27252A).
1156 * The card has an asic wrapper around a DS8390 core. The asic handles
1157 * host accesses and offers both standard register IO and memory mapped
1158 * IO. Memory mapped I/O allows better performance at the expense of greater
1159 * chance of an incompatibility with existing ISA cards.
1161 * The card has a few caveats: it isn't tolerant of byte wide accesses, only
1162 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
1163 * don't allow 32 bit accesses; these are indicated by a bit in the software
1164 * ID register (see if_edreg.h).
1166 * Other caveats are: we should read the MAC address only when the card
1169 * For more information; please consult the CRYNWR packet driver.
1171 * The AUI port is turned on using the "link2" option on the ifconfig
1175 ed_probe_HP_pclanp(dev, port_rid, flags)
1180 struct ed_softc *sc = device_get_softc(dev);
1182 int n; /* temp var */
1183 int memsize; /* mem on board */
1184 u_char checksum; /* checksum of board address */
1185 u_char irq; /* board configured IRQ */
1186 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */
1187 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
1188 u_long conf_maddr, conf_msize, conf_irq, junk;
1190 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS);
1194 /* Fill in basic information */
1195 sc->asic_offset = ED_HPP_ASIC_OFFSET;
1196 sc->nic_offset = ED_HPP_NIC_OFFSET;
1198 sc->chip_type = ED_CHIP_TYPE_DP8390;
1199 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */
1202 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
1205 if ((ed_asic_inb(sc, ED_HPP_ID) != 0x50) ||
1206 (ed_asic_inb(sc, ED_HPP_ID + 1) != 0x48) ||
1207 ((ed_asic_inb(sc, ED_HPP_ID + 2) & 0xF0) != 0) ||
1208 (ed_asic_inb(sc, ED_HPP_ID + 3) != 0x53))
1212 * Read the MAC address and verify checksum on the address.
1215 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_MAC);
1216 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
1217 checksum += (sc->arpcom.ac_enaddr[n] =
1218 ed_asic_inb(sc, ED_HPP_MAC_ADDR + n));
1220 checksum += ed_asic_inb(sc, ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
1222 if (checksum != 0xFF)
1226 * Verify that the software model number is 0.
1229 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_ID);
1230 if (((sc->hpp_id = ed_asic_inw(sc, ED_HPP_PAGE_4)) &
1231 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
1235 * Read in and save the current options configured on card.
1238 sc->hpp_options = ed_asic_inw(sc, ED_HPP_OPTION);
1240 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET |
1241 ED_HPP_OPTION_CHIP_RESET |
1242 ED_HPP_OPTION_ENABLE_IRQ);
1245 * Reset the chip. This requires writing to the option register
1246 * so take care to preserve the other bits.
1249 ed_asic_outw(sc, ED_HPP_OPTION,
1250 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET |
1251 ED_HPP_OPTION_CHIP_RESET)));
1253 DELAY(5000); /* wait for chip reset to complete */
1255 ed_asic_outw(sc, ED_HPP_OPTION,
1256 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
1257 ED_HPP_OPTION_CHIP_RESET |
1258 ED_HPP_OPTION_ENABLE_IRQ)));
1262 if (!(ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST))
1263 return ENXIO; /* reset did not complete */
1266 * Read out configuration information.
1269 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1271 irq = ed_asic_inb(sc, ED_HPP_HW_IRQ);
1274 * Check for impossible IRQ.
1277 if (irq >= (sizeof(ed_hpp_intr_val) / sizeof(ed_hpp_intr_val[0])))
1281 * If the kernel IRQ was specified with a '?' use the cards idea
1282 * of the IRQ. If the kernel IRQ was explicitly specified, it
1283 * should match that of the hardware.
1285 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
1288 bus_set_resource(dev, SYS_RES_IRQ, 0,
1289 ed_hpp_intr_val[irq], 1);
1291 if (conf_irq != ed_hpp_intr_val[irq])
1296 * Fill in softconfig info.
1299 sc->vendor = ED_VENDOR_HP;
1300 sc->type = ED_TYPE_HP_PCLANPLUS;
1301 sc->type_str = "HP-PCLAN+";
1303 sc->mem_shared = 0; /* we DON'T have dual ported RAM */
1304 sc->mem_start = 0; /* we use offsets inside the card RAM */
1306 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
1309 * The board has 32KB of memory. Is there a way to determine
1310 * this programmatically?
1316 * Check if memory mapping of the I/O registers possible.
1319 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE)
1324 * determine the memory address from the board.
1327 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1328 mem_addr = (ed_asic_inw(sc, ED_HPP_HW_MEM_MAP) << 8);
1331 * Check that the kernel specified start of memory and
1332 * hardware's idea of it match.
1334 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
1335 &conf_maddr, &conf_msize);
1339 if (mem_addr != conf_maddr)
1342 error = ed_alloc_memory(dev, 0, memsize);
1346 sc->hpp_mem_start = rman_get_virtual(sc->mem_res);
1350 * Fill in the rest of the soft config structure.
1354 * The transmit page index.
1357 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
1359 if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING)
1365 * Memory description
1368 sc->mem_size = memsize;
1369 sc->mem_ring = sc->mem_start +
1370 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
1371 sc->mem_end = sc->mem_start + sc->mem_size;
1374 * Receive area starts after the transmit area and
1375 * continues till the end of memory.
1378 sc->rec_page_start = sc->tx_page_start +
1379 (sc->txb_cnt * ED_TXBUF_SIZE);
1380 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
1383 sc->cr_proto = 0; /* value works */
1386 * Set the wrap registers for string I/O reads.
1389 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1390 ed_asic_outw(sc, ED_HPP_HW_WRAP,
1391 ((sc->rec_page_start / ED_PAGE_SIZE) |
1392 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
1395 * Reset the register page to normal operation.
1398 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1401 * Verify that we can read/write from adapter memory.
1402 * Create test pattern.
1405 for (n = 0; n < ED_HPP_TEST_SIZE; n++)
1407 test_pattern[n] = (n*n) ^ ~n;
1410 #undef ED_HPP_TEST_SIZE
1413 * Check that the memory is accessible thru the I/O ports.
1414 * Write out the contents of "test_pattern", read back
1415 * into "test_buffer" and compare the two for any
1419 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
1421 ed_hpp_writemem(sc, test_pattern, (n * ED_PAGE_SIZE),
1422 sizeof(test_pattern));
1423 ed_hpp_readmem(sc, (n * ED_PAGE_SIZE),
1424 test_buffer, sizeof(test_pattern));
1426 if (bcmp(test_pattern, test_buffer,
1427 sizeof(test_pattern)))
1431 return (ED_HPP_IO_PORTS);
1436 * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
1440 ed_hpp_set_physical_link(struct ed_softc *sc)
1442 struct ifnet *ifp = &sc->arpcom.ac_if;
1445 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1446 lan_page = ed_asic_inw(sc, ED_HPP_PAGE_0);
1448 if (ifp->if_flags & IFF_ALTPHYS) {
1454 lan_page |= ED_HPP_LAN_AUI;
1456 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1457 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1463 * Use the ThinLan interface
1466 lan_page &= ~ED_HPP_LAN_AUI;
1468 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1469 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1474 * Wait for the lan card to re-initialize itself
1477 DELAY(150000); /* wait 150 ms */
1480 * Restore normal pages.
1483 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1488 * Allocate a port resource with the given resource id.
1491 ed_alloc_port(dev, rid, size)
1496 struct ed_softc *sc = device_get_softc(dev);
1497 struct resource *res;
1499 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1500 0ul, ~0ul, size, RF_ACTIVE);
1504 sc->port_used = size;
1512 * Allocate a memory resource with the given resource id.
1515 ed_alloc_memory(dev, rid, size)
1520 struct ed_softc *sc = device_get_softc(dev);
1521 struct resource *res;
1523 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1524 0ul, ~0ul, size, RF_ACTIVE);
1528 sc->mem_used = size;
1536 * Allocate an irq resource with the given resource id.
1539 ed_alloc_irq(dev, rid, flags)
1544 struct ed_softc *sc = device_get_softc(dev);
1545 struct resource *res;
1547 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
1548 0ul, ~0ul, 1, (RF_ACTIVE | flags));
1559 * Release all resources
1562 ed_release_resources(dev)
1565 struct ed_softc *sc = device_get_softc(dev);
1568 bus_deactivate_resource(dev, SYS_RES_IOPORT,
1569 sc->port_rid, sc->port_res);
1570 bus_release_resource(dev, SYS_RES_IOPORT,
1571 sc->port_rid, sc->port_res);
1575 bus_deactivate_resource(dev, SYS_RES_MEMORY,
1576 sc->mem_rid, sc->mem_res);
1577 bus_release_resource(dev, SYS_RES_MEMORY,
1578 sc->mem_rid, sc->mem_res);
1582 bus_deactivate_resource(dev, SYS_RES_IRQ,
1583 sc->irq_rid, sc->irq_res);
1584 bus_release_resource(dev, SYS_RES_IRQ,
1585 sc->irq_rid, sc->irq_res);
1591 * Install interface into kernel networking data structures
1594 ed_attach(sc, unit, flags)
1595 struct ed_softc *sc;
1599 struct ifnet *ifp = &sc->arpcom.ac_if;
1601 callout_handle_init(&sc->tick_ch);
1603 * Set interface to stopped condition (reset)
1607 if (!ifp->if_name) {
1609 * Initialize ifnet structure
1612 ifp->if_unit = unit;
1613 ifp->if_name = "ed";
1614 ifp->if_output = ether_output;
1615 ifp->if_start = ed_start;
1616 ifp->if_ioctl = ed_ioctl;
1617 ifp->if_watchdog = ed_watchdog;
1618 ifp->if_init = ed_init;
1619 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1620 ifp->if_linkmib = &sc->mibdata;
1621 ifp->if_linkmiblen = sizeof sc->mibdata;
1623 * XXX - should do a better job.
1625 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1626 sc->mibdata.dot3StatsEtherChipSet =
1627 DOT3CHIPSET(dot3VendorWesternDigital,
1628 dot3ChipSetWesternDigital83C790);
1630 sc->mibdata.dot3StatsEtherChipSet =
1631 DOT3CHIPSET(dot3VendorNational,
1632 dot3ChipSetNational8390);
1633 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
1636 * Set default state for ALTPHYS flag (used to disable the
1637 * tranceiver for AUI operation), based on compile-time
1640 if (flags & ED_FLAGS_DISABLE_TRANCEIVER)
1641 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1642 IFF_MULTICAST | IFF_ALTPHYS);
1644 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1648 * Attach the interface
1650 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1652 /* device attach does transition from UNCONFIGURED to IDLE state */
1655 * Print additional info when attached
1657 printf("%s%d: address %6D, ", ifp->if_name, ifp->if_unit,
1658 sc->arpcom.ac_enaddr, ":");
1660 if (sc->type_str && (*sc->type_str != 0))
1661 printf("type %s ", sc->type_str);
1663 printf("type unknown (0x%x) ", sc->type);
1665 if (sc->vendor == ED_VENDOR_HP)
1666 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
1667 "16-bit" : "32-bit",
1668 sc->hpp_mem_start ? "memory mapped" : "regular");
1670 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)");
1672 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) ||
1673 (sc->vendor == ED_VENDOR_HP)) &&
1674 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : "");
1686 struct ed_softc *sc = ifp->if_softc;
1694 * Stop interface and re-initialize.
1703 * Take interface offline.
1707 struct ed_softc *sc;
1711 #ifndef ED_NO_MIIBUS
1712 untimeout(ed_tick, sc, sc->tick_ch);
1713 callout_handle_init(&sc->tick_ch);
1718 * Stop everything on the interface, and select page 0 registers.
1720 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1723 * Wait for interface to enter stopped state, but limit # of checks to
1724 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
1725 * just in case it's an old one.
1727 if (sc->chip_type != ED_CHIP_TYPE_AX88190)
1728 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1732 * Device timeout/watchdog routine. Entered if the device neglects to
1733 * generate an interrupt after a transmit has been started on it.
1739 struct ed_softc *sc = ifp->if_softc;
1743 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit);
1749 #ifndef ED_NO_MIIBUS
1754 struct ed_softc *sc = arg;
1755 struct mii_data *mii;
1759 callout_handle_init(&sc->tick_ch);
1763 if (sc->miibus != NULL) {
1764 mii = device_get_softc(sc->miibus);
1767 sc->tick_ch = timeout(ed_tick, sc, hz);
1773 * Initialize device.
1779 struct ed_softc *sc = xsc;
1780 struct ifnet *ifp = &sc->arpcom.ac_if;
1786 /* address not known */
1787 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */
1791 * Initialize the NIC in the exact order outlined in the NS manual.
1792 * This init procedure is "mandatory"...don't change what or when
1797 /* reset transmitter flags */
1803 sc->txb_next_tx = 0;
1805 /* This variable is used below - don't move this assignment */
1806 sc->next_packet = sc->rec_page_start + 1;
1809 * Set interface for page 0, Remote DMA complete, Stopped
1811 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1816 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
1817 * order=80x86, word-wide DMA xfers,
1819 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
1823 * Same as above, but byte-wide DMA xfers
1825 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1829 * Clear Remote Byte Count Registers
1831 ed_nic_outb(sc, ED_P0_RBCR0, 0);
1832 ed_nic_outb(sc, ED_P0_RBCR1, 0);
1835 * For the moment, don't store incoming packets in memory.
1837 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
1840 * Place NIC in internal loopback mode
1842 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0);
1845 * Initialize transmit/receive (ring-buffer) Page Start
1847 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start);
1848 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start);
1849 /* Set lower bits of byte addressable framing to 0 */
1850 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1851 ed_nic_outb(sc, 0x09, 0);
1854 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1856 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop);
1857 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start);
1860 * Clear all interrupts. A '1' in each bit position clears the
1861 * corresponding flag.
1863 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1866 * Enable the following interrupts: receive/transmit complete,
1867 * receive/transmit error, and Receiver OverWrite.
1869 * Counter overflow and Remote DMA complete are *not* enabled.
1871 ed_nic_outb(sc, ED_P0_IMR,
1872 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
1875 * Program Command Register for page 1
1877 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1880 * Copy out our station address
1882 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1883 ed_nic_outb(sc, ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]);
1886 * Set Current Page pointer to next_packet (initialized above)
1888 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet);
1891 * Program Receiver Configuration Register and multicast filter. CR is
1892 * set to page 0 on return.
1897 * Take interface out of loopback
1899 ed_nic_outb(sc, ED_P0_TCR, 0);
1902 * If this is a 3Com board, the tranceiver must be software enabled
1903 * (there is no settable hardware default).
1905 if (sc->vendor == ED_VENDOR_3COM) {
1906 if (ifp->if_flags & IFF_ALTPHYS) {
1907 ed_asic_outb(sc, ED_3COM_CR, 0);
1909 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
1913 #ifndef ED_NO_MIIBUS
1914 if (sc->miibus != NULL) {
1915 struct mii_data *mii;
1916 mii = device_get_softc(sc->miibus);
1921 * Set 'running' flag, and clear output active flag.
1923 ifp->if_flags |= IFF_RUNNING;
1924 ifp->if_flags &= ~IFF_OACTIVE;
1927 * ...and attempt to start output
1931 #ifndef ED_NO_MIIBUS
1932 untimeout(ed_tick, sc, sc->tick_ch);
1933 sc->tick_ch = timeout(ed_tick, sc, hz);
1939 * This routine actually starts the transmission on the interface
1941 static __inline void
1943 struct ed_softc *sc;
1945 struct ifnet *ifp = (struct ifnet *)sc;
1950 len = sc->txb_len[sc->txb_next_tx];
1953 * Set NIC for page 0 register access
1955 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
1958 * Set TX buffer start page
1960 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start +
1961 sc->txb_next_tx * ED_TXBUF_SIZE);
1966 ed_nic_outb(sc, ED_P0_TBCR0, len);
1967 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8);
1970 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
1972 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
1976 * Point to next transmit buffer slot and wrap if necessary.
1979 if (sc->txb_next_tx == sc->txb_cnt)
1980 sc->txb_next_tx = 0;
1983 * Set a timer just in case we never hear from the board again
1989 * Start output on interface.
1990 * We make two assumptions here:
1991 * 1) that the current priority is set to splimp _before_ this code
1992 * is called *and* is returned to the appropriate priority after
1994 * 2) that the IFF_OACTIVE flag is checked before this code is called
1995 * (i.e. that the output part of the interface is idle)
2001 struct ed_softc *sc = ifp->if_softc;
2002 struct mbuf *m0, *m;
2007 printf("ed_start(%p) GONE\n",ifp);
2013 * First, see if there are buffered packets and an idle transmitter -
2014 * should never happen at this point.
2016 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
2017 printf("ed: packets buffered, but transmitter idle\n");
2022 * See if there is room to put another packet in the buffer.
2024 if (sc->txb_inuse == sc->txb_cnt) {
2027 * No room. Indicate this to the outside world and exit.
2029 ifp->if_flags |= IFF_OACTIVE;
2032 IF_DEQUEUE(&ifp->if_snd, m);
2036 * We are using the !OACTIVE flag to indicate to the outside
2037 * world that we can accept an additional packet rather than
2038 * that the transmitter is _actually_ active. Indeed, the
2039 * transmitter may be active, but if we haven't filled all the
2040 * buffers with data then we still want to accept more.
2042 ifp->if_flags &= ~IFF_OACTIVE;
2047 * Copy the mbuf chain into the transmit buffer
2052 /* txb_new points to next open buffer slot */
2053 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
2055 if (sc->mem_shared) {
2058 * Special case setup for 16 bit boards...
2061 switch (sc->vendor) {
2064 * For 16bit 3Com boards (which have 16k of
2065 * memory), we have the xmit buffers in a
2066 * different page of memory ('page 0') - so
2069 case ED_VENDOR_3COM:
2070 ed_asic_outb(sc, ED_3COM_GACFR,
2071 ED_3COM_GACFR_RSEL);
2075 * Enable 16bit access to shared memory on
2078 case ED_VENDOR_WD_SMC:
2079 ed_asic_outb(sc, ED_WD_LAAR,
2080 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2081 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2082 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
2087 for (len = 0; m != 0; m = m->m_next) {
2088 bcopy(mtod(m, caddr_t), buffer, m->m_len);
2094 * Restore previous shared memory access
2097 switch (sc->vendor) {
2098 case ED_VENDOR_3COM:
2099 ed_asic_outb(sc, ED_3COM_GACFR,
2100 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
2102 case ED_VENDOR_WD_SMC:
2103 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2104 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2106 ed_asic_outb(sc, ED_WD_LAAR,
2107 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2112 len = ed_pio_write_mbufs(sc, m, (int)buffer);
2117 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
2122 * Point to next buffer slot and wrap if necessary.
2125 if (sc->txb_new == sc->txb_cnt)
2128 if (sc->xmit_busy == 0)
2132 * Tap off here if there is a bpf listener.
2141 * Loop back to the top to possibly buffer more packets
2147 * Ethernet interface receiver interrupt.
2149 static __inline void
2151 struct ed_softc *sc;
2153 struct ifnet *ifp = &sc->arpcom.ac_if;
2156 struct ed_ring packet_hdr;
2163 * Set NIC to page 1 registers to get 'current' pointer
2165 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2168 * 'sc->next_packet' is the logical beginning of the ring-buffer -
2169 * i.e. it points to where new data has been buffered. The 'CURR'
2170 * (current) register points to the logical end of the ring-buffer -
2171 * i.e. it points to where additional new data will be added. We loop
2172 * here until the logical beginning equals the logical end (or in
2173 * other words, until the ring-buffer is empty).
2175 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) {
2177 /* get pointer to this buffer's header structure */
2178 packet_ptr = sc->mem_ring +
2179 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
2182 * The byte count includes a 4 byte header that was added by
2186 packet_hdr = *(struct ed_ring *) packet_ptr;
2188 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr,
2189 sizeof(packet_hdr));
2190 len = packet_hdr.count;
2191 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
2192 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
2194 * Length is a wild value. There's a good chance that
2195 * this was caused by the NIC being old and buggy.
2196 * The bug is that the length low byte is duplicated in
2197 * the high byte. Try to recalculate the length based on
2198 * the pointer to the next packet.
2201 * NOTE: sc->next_packet is pointing at the current packet.
2203 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
2204 if (packet_hdr.next_packet >= sc->next_packet) {
2205 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
2207 len += ((packet_hdr.next_packet - sc->rec_page_start) +
2208 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
2211 * because buffers are aligned on 256-byte boundary,
2212 * the length computed above is off by 256 in almost
2213 * all cases. Fix it...
2217 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
2218 + sizeof(struct ed_ring)))
2219 sc->mibdata.dot3StatsFrameTooLongs++;
2222 * Be fairly liberal about what we allow as a "reasonable" length
2223 * so that a [crufty] packet will make it to BPF (and can thus
2224 * be analyzed). Note that all that is really important is that
2225 * we have a length that will fit into one mbuf cluster or less;
2226 * the upper layer protocols can then figure out the length from
2227 * their own length field(s).
2228 * But make sure that we have at least a full ethernet header
2229 * or we would be unable to call ether_input() later.
2231 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) &&
2232 (len <= MCLBYTES) &&
2233 (packet_hdr.next_packet >= sc->rec_page_start) &&
2234 (packet_hdr.next_packet < sc->rec_page_stop)) {
2238 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
2239 len - sizeof(struct ed_ring));
2243 * Really BAD. The ring pointers are corrupted.
2246 "ed%d: NIC memory corrupt - invalid packet length %d\n",
2254 * Update next packet pointer
2256 sc->next_packet = packet_hdr.next_packet;
2259 * Update NIC boundry pointer - being careful to keep it one
2260 * buffer behind. (as recommended by NS databook)
2262 boundry = sc->next_packet - 1;
2263 if (boundry < sc->rec_page_start)
2264 boundry = sc->rec_page_stop - 1;
2267 * Set NIC to page 0 registers to update boundry register
2269 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2271 ed_nic_outb(sc, ED_P0_BNRY, boundry);
2274 * Set NIC to page 1 registers before looping to top (prepare
2275 * to get 'CURR' current pointer)
2277 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2282 * Ethernet interface interrupt processor
2288 struct ed_softc *sc = (struct ed_softc*) arg;
2289 struct ifnet *ifp = (struct ifnet *)sc;
2295 * Set NIC to page 0 registers
2297 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2300 * loop until there are no more new interrupts
2302 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0) {
2305 * reset all the bits that we are 'acknowledging' by writing a
2306 * '1' to each bit position that was set (writing a '1'
2309 ed_nic_outb(sc, ED_P0_ISR, isr);
2311 /* XXX workaround for AX88190 */
2312 if (sc->chip_type == ED_CHIP_TYPE_AX88190) {
2313 while (ed_nic_inb(sc, ED_P0_ISR) & isr) {
2314 ed_nic_outb(sc, ED_P0_ISR,0);
2315 ed_nic_outb(sc, ED_P0_ISR,isr);
2320 * Handle transmitter interrupts. Handle these first because
2321 * the receiver will reset the board under some conditions.
2323 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
2324 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f;
2327 * Check for transmit error. If a TX completed with an
2328 * error, we end up throwing the packet away. Really
2329 * the only error that is possible is excessive
2330 * collisions, and in this case it is best to allow
2331 * the automatic mechanisms of TCP to backoff the
2332 * flow. Of course, with UDP we're screwed, but this
2333 * is expected when a network is heavily loaded.
2335 (void) ed_nic_inb(sc, ED_P0_TSR);
2336 if (isr & ED_ISR_TXE) {
2340 * Excessive collisions (16)
2342 tsr = ed_nic_inb(sc, ED_P0_TSR);
2343 if ((tsr & ED_TSR_ABT)
2344 && (collisions == 0)) {
2347 * When collisions total 16, the
2348 * P0_NCR will indicate 0, and the
2352 sc->mibdata.dot3StatsExcessiveCollisions++;
2353 sc->mibdata.dot3StatsCollFrequencies[15]++;
2355 if (tsr & ED_TSR_OWC)
2356 sc->mibdata.dot3StatsLateCollisions++;
2357 if (tsr & ED_TSR_CDH)
2358 sc->mibdata.dot3StatsSQETestErrors++;
2359 if (tsr & ED_TSR_CRS)
2360 sc->mibdata.dot3StatsCarrierSenseErrors++;
2361 if (tsr & ED_TSR_FU)
2362 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
2365 * update output errors counter
2371 * Update total number of successfully
2372 * transmitted packets.
2378 * reset tx busy and output active flags
2381 ifp->if_flags &= ~IFF_OACTIVE;
2384 * clear watchdog timer
2389 * Add in total number of collisions on last
2392 ifp->if_collisions += collisions;
2393 switch(collisions) {
2398 sc->mibdata.dot3StatsSingleCollisionFrames++;
2399 sc->mibdata.dot3StatsCollFrequencies[0]++;
2402 sc->mibdata.dot3StatsMultipleCollisionFrames++;
2404 dot3StatsCollFrequencies[collisions-1]
2410 * Decrement buffer in-use count if not zero (can only
2411 * be zero if a transmitter interrupt occured while
2412 * not actually transmitting). If data is ready to
2413 * transmit, start it transmitting, otherwise defer
2414 * until after handling receiver
2416 if (sc->txb_inuse && --sc->txb_inuse)
2421 * Handle receiver interrupts
2423 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
2426 * Overwrite warning. In order to make sure that a
2427 * lockup of the local DMA hasn't occurred, we reset
2428 * and re-init the NIC. The NSC manual suggests only a
2429 * partial reset/re-init is necessary - but some chips
2430 * seem to want more. The DMA lockup has been seen
2431 * only with early rev chips - Methinks this bug was
2432 * fixed in later revs. -DG
2434 if (isr & ED_ISR_OVW) {
2438 "ed%d: warning - receiver ring buffer overrun\n",
2443 * Stop/reset/re-init NIC
2449 * Receiver Error. One or more of: CRC error,
2450 * frame alignment error FIFO overrun, or
2453 if (isr & ED_ISR_RXE) {
2455 rsr = ed_nic_inb(sc, ED_P0_RSR);
2456 if (rsr & ED_RSR_CRC)
2457 sc->mibdata.dot3StatsFCSErrors++;
2458 if (rsr & ED_RSR_FAE)
2459 sc->mibdata.dot3StatsAlignmentErrors++;
2460 if (rsr & ED_RSR_FO)
2461 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
2464 printf("ed%d: receive error %x\n", ifp->if_unit,
2465 ed_nic_inb(sc, ED_P0_RSR));
2470 * Go get the packet(s) XXX - Doing this on an
2471 * error is dubious because there shouldn't be
2472 * any data to get (we've configured the
2473 * interface to not accept packets with
2478 * Enable 16bit access to shared memory first
2482 (sc->vendor == ED_VENDOR_WD_SMC)) {
2484 ed_asic_outb(sc, ED_WD_LAAR,
2485 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2486 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2487 ed_asic_outb(sc, ED_WD_MSR,
2493 /* disable 16bit access */
2495 (sc->vendor == ED_VENDOR_WD_SMC)) {
2497 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2498 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2500 ed_asic_outb(sc, ED_WD_LAAR,
2501 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2507 * If it looks like the transmitter can take more data,
2508 * attempt to start output on the interface. This is done
2509 * after handling the receiver to give the receiver priority.
2511 if ((ifp->if_flags & IFF_OACTIVE) == 0)
2515 * return NIC CR to standard state: page 0, remote DMA
2516 * complete, start (toggling the TXP bit off, even if was just
2517 * set in the transmit routine, is *okay* - it is 'edge'
2518 * triggered from low to high)
2520 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2523 * If the Network Talley Counters overflow, read them to reset
2524 * them. It appears that old 8390's won't clear the ISR flag
2525 * otherwise - resulting in an infinite loop.
2527 if (isr & ED_ISR_CNT) {
2528 (void) ed_nic_inb(sc, ED_P0_CNTR0);
2529 (void) ed_nic_inb(sc, ED_P0_CNTR1);
2530 (void) ed_nic_inb(sc, ED_P0_CNTR2);
2536 * Process an ioctl request. This code needs some work - it looks
2540 ed_ioctl(ifp, command, data)
2541 register struct ifnet *ifp;
2545 struct ed_softc *sc = ifp->if_softc;
2546 #ifndef ED_NO_MIIBUS
2547 struct ifreq *ifr = (struct ifreq *)data;
2548 struct mii_data *mii;
2552 if (sc == NULL || sc->gone) {
2553 ifp->if_flags &= ~IFF_RUNNING;
2563 error = ether_ioctl(ifp, command, data);
2569 * If the interface is marked up and stopped, then start it.
2570 * If it is marked down and running, then stop it.
2572 if (ifp->if_flags & IFF_UP) {
2573 if ((ifp->if_flags & IFF_RUNNING) == 0)
2576 if (ifp->if_flags & IFF_RUNNING) {
2578 ifp->if_flags &= ~IFF_RUNNING;
2583 * Promiscuous flag may have changed, so reprogram the RCR.
2588 * An unfortunate hack to provide the (required) software
2589 * control of the tranceiver for 3Com boards. The ALTPHYS flag
2590 * disables the tranceiver if set.
2592 if (sc->vendor == ED_VENDOR_3COM) {
2593 if (ifp->if_flags & IFF_ALTPHYS) {
2594 ed_asic_outb(sc, ED_3COM_CR, 0);
2596 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
2598 } else if (sc->vendor == ED_VENDOR_HP)
2599 ed_hpp_set_physical_link(sc);
2605 * Multicast list has changed; set the hardware filter
2612 #ifndef ED_NO_MIIBUS
2615 if (sc->miibus == NULL) {
2619 mii = device_get_softc(sc->miibus);
2620 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2632 * Given a source and destination address, copy 'amount' of a packet from
2633 * the ring buffer into a linear destination buffer. Takes into account
2636 static __inline char *
2637 ed_ring_copy(sc, src, dst, amount)
2638 struct ed_softc *sc;
2645 /* does copy wrap to lower addr in ring buffer? */
2646 if (src + amount > sc->mem_end) {
2647 tmp_amount = sc->mem_end - src;
2649 /* copy amount up to end of NIC memory */
2651 bcopy(src, dst, tmp_amount);
2653 ed_pio_readmem(sc, (int)src, dst, tmp_amount);
2655 amount -= tmp_amount;
2660 bcopy(src, dst, amount);
2662 ed_pio_readmem(sc, (int)src, dst, amount);
2664 return (src + amount);
2668 * Retreive packet from shared memory and send to the next level up via
2672 ed_get_packet(sc, buf, len)
2673 struct ed_softc *sc;
2677 struct ether_header *eh;
2680 /* Allocate a header mbuf */
2681 MGETHDR(m, M_DONTWAIT, MT_DATA);
2684 m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
2685 m->m_pkthdr.len = m->m_len = len;
2688 * We always put the received packet in a single buffer -
2689 * either with just an mbuf header or in a cluster attached
2690 * to the header. The +2 is to compensate for the alignment
2693 if ((len + 2) > MHLEN) {
2694 /* Attach an mbuf cluster */
2695 MCLGET(m, M_DONTWAIT);
2697 /* Insist on getting a cluster */
2698 if ((m->m_flags & M_EXT) == 0) {
2705 * The +2 is to longword align the start of the real packet.
2706 * This is important for NFS.
2709 eh = mtod(m, struct ether_header *);
2713 * Don't read in the entire packet if we know we're going to drop it
2714 * and no bpf is active.
2716 if (!sc->arpcom.ac_if.if_bpf && do_bridge && bdg_forward_ptr != NULL &&
2717 BDG_USED( (&sc->arpcom.ac_if) ) ) {
2720 ed_ring_copy(sc, buf, (char *)eh, ETHER_HDR_LEN);
2721 bif = bridge_in_ptr(&sc->arpcom.ac_if, eh) ;
2722 if (bif == BDG_DROP) {
2726 if (len > ETHER_HDR_LEN)
2727 ed_ring_copy(sc, buf + ETHER_HDR_LEN,
2728 (char *)(eh + 1), len - ETHER_HDR_LEN);
2732 * Get packet, including link layer address, from interface.
2734 ed_ring_copy(sc, buf, (char *)eh, len);
2737 * Remove link layer address.
2739 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header);
2740 m->m_data += sizeof(struct ether_header);
2742 ether_input(&sc->arpcom.ac_if, eh, m);
2746 * Supporting routines
2750 * Given a NIC memory source address and a host memory destination
2751 * address, copy 'amount' from NIC to host using Programmed I/O.
2752 * The 'amount' is rounded up to a word - okay as long as mbufs
2754 * This routine is currently Novell-specific.
2757 ed_pio_readmem(sc, src, dst, amount)
2758 struct ed_softc *sc;
2761 unsigned short amount;
2763 /* HP PC Lan+ cards need special handling */
2764 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2765 ed_hpp_readmem(sc, src, dst, amount);
2769 /* Regular Novell cards */
2770 /* select page 0 registers */
2771 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2773 /* round up to a word */
2777 /* set up DMA byte count */
2778 ed_nic_outb(sc, ED_P0_RBCR0, amount);
2779 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8);
2781 /* set up source address in NIC mem */
2782 ed_nic_outb(sc, ED_P0_RSAR0, src);
2783 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8);
2785 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2788 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2);
2790 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount);
2795 * Stripped down routine for writing a linear buffer to NIC memory.
2796 * Only used in the probe routine to test the memory. 'len' must
2800 ed_pio_writemem(sc, src, dst, len)
2801 struct ed_softc *sc;
2806 int maxwait = 200; /* about 240us */
2808 /* select page 0 registers */
2809 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2811 /* reset remote DMA complete flag */
2812 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2814 /* set up DMA byte count */
2815 ed_nic_outb(sc, ED_P0_RBCR0, len);
2816 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8);
2818 /* set up destination address in NIC mem */
2819 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2820 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2822 /* set remote DMA write */
2823 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2826 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2);
2828 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len);
2832 * Wait for remote DMA complete. This is necessary because on the
2833 * transmit side, data is handled internally by the NIC in bursts and
2834 * we can't start another remote DMA until this one completes. Not
2835 * waiting causes really bad things to happen - like the NIC
2836 * irrecoverably jamming the ISA bus.
2838 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2842 * Write an mbuf chain to the destination NIC memory address using
2846 ed_pio_write_mbufs(sc, m, dst)
2847 struct ed_softc *sc;
2851 struct ifnet *ifp = (struct ifnet *)sc;
2852 unsigned short total_len, dma_len;
2854 int maxwait = 200; /* about 240us */
2856 /* HP PC Lan+ cards need special handling */
2857 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2858 return ed_hpp_write_mbufs(sc, m, dst);
2861 /* Regular Novell cards */
2862 /* First, count up the total number of bytes to copy */
2863 for (total_len = 0, mp = m; mp; mp = mp->m_next)
2864 total_len += mp->m_len;
2866 dma_len = total_len;
2867 if (sc->isa16bit && (dma_len & 1))
2870 /* select page 0 registers */
2871 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2873 /* reset remote DMA complete flag */
2874 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2876 /* set up DMA byte count */
2877 ed_nic_outb(sc, ED_P0_RBCR0, dma_len);
2878 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8);
2880 /* set up destination address in NIC mem */
2881 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2882 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2884 /* set remote DMA write */
2885 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2888 * Transfer the mbuf chain to the NIC memory.
2889 * 16-bit cards require that data be transferred as words, and only words.
2890 * So that case requires some extra code to patch over odd-length mbufs.
2893 if (!sc->isa16bit) {
2894 /* NE1000s are easy */
2897 ed_asic_outsb(sc, ED_NOVELL_DATA,
2898 m->m_data, m->m_len);
2903 /* NE2000s are a pain */
2904 unsigned char *data;
2906 unsigned char savebyte[2];
2913 data = mtod(m, caddr_t);
2914 /* finish the last word */
2916 savebyte[1] = *data;
2917 ed_asic_outw(sc, ED_NOVELL_DATA,
2918 *(u_short *)savebyte);
2923 /* output contiguous words */
2925 ed_asic_outsw(sc, ED_NOVELL_DATA,
2930 /* save last byte, if necessary */
2932 savebyte[0] = *data;
2938 /* spit last byte */
2940 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte);
2945 * Wait for remote DMA complete. This is necessary because on the
2946 * transmit side, data is handled internally by the NIC in bursts and
2947 * we can't start another remote DMA until this one completes. Not
2948 * waiting causes really bad things to happen - like the NIC
2949 * irrecoverably jamming the ISA bus.
2951 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2954 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n",
2963 * Support routines to handle the HP PC Lan+ card.
2967 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
2972 ed_hpp_readmem(sc, src, dst, amount)
2973 struct ed_softc *sc;
2976 unsigned short amount;
2979 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
2982 /* Program the source address in RAM */
2983 ed_asic_outw(sc, ED_HPP_PAGE_2, src);
2986 * The HP PC Lan+ card supports word reads as well as
2987 * a memory mapped i/o port that is aliased to every
2988 * even address on the board.
2991 if (sc->hpp_mem_start) {
2993 /* Enable memory mapped access. */
2994 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
2995 ~(ED_HPP_OPTION_MEM_DISABLE |
2996 ED_HPP_OPTION_BOOT_ROM_ENB));
2998 if (use_32bit_access && (amount > 3)) {
2999 u_int32_t *dl = (u_int32_t *) dst;
3000 volatile u_int32_t *const sl =
3001 (u_int32_t *) sc->hpp_mem_start;
3002 u_int32_t *const fence = dl + (amount >> 2);
3004 /* Copy out NIC data. We could probably write this
3005 as a `movsl'. The currently generated code is lousy.
3011 dst += (amount & ~3);
3016 /* Finish off any words left, as a series of short reads */
3018 u_short *d = (u_short *) dst;
3019 volatile u_short *const s =
3020 (u_short *) sc->hpp_mem_start;
3021 u_short *const fence = d + (amount >> 1);
3023 /* Copy out NIC data. */
3028 dst += (amount & ~1);
3033 * read in a byte; however we need to always read 16 bits
3034 * at a time or the hardware gets into a funny state
3038 /* need to read in a short and copy LSB */
3039 volatile u_short *const s =
3040 (volatile u_short *) sc->hpp_mem_start;
3045 /* Restore Boot ROM access. */
3047 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3051 /* Read in data using the I/O port */
3052 if (use_32bit_access && (amount > 3)) {
3053 ed_asic_insl(sc, ED_HPP_PAGE_4, dst, amount >> 2);
3054 dst += (amount & ~3);
3058 ed_asic_insw(sc, ED_HPP_PAGE_4, dst, amount >> 1);
3059 dst += (amount & ~1);
3062 if (amount == 1) { /* read in a short and keep the LSB */
3063 *dst = ed_asic_inw(sc, ED_HPP_PAGE_4) & 0xFF;
3069 * HP PC Lan+: Write to NIC memory, using either PIO or memory mapped
3071 * Only used in the probe routine to test the memory. 'len' must
3075 ed_hpp_writemem(sc, src, dst, len)
3076 struct ed_softc *sc;
3081 /* reset remote DMA complete flag */
3082 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3084 /* program the write address in RAM */
3085 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3087 if (sc->hpp_mem_start) {
3088 u_short *s = (u_short *) src;
3089 volatile u_short *d = (u_short *) sc->hpp_mem_start;
3090 u_short *const fence = s + (len >> 1);
3093 * Enable memory mapped access.
3096 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3097 ~(ED_HPP_OPTION_MEM_DISABLE |
3098 ED_HPP_OPTION_BOOT_ROM_ENB));
3101 * Copy to NIC memory.
3108 * Restore Boot ROM access.
3111 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3114 /* write data using I/O writes */
3115 ed_asic_outsw(sc, ED_HPP_PAGE_4, src, len / 2);
3120 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using
3121 * outsw() or via the memory mapped interface to the same register.
3122 * Writes have to be in word units; byte accesses won't work and may cause
3123 * the NIC to behave weirdly. Long word accesses are permitted if the ASIC
3128 ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
3131 unsigned short total_len;
3132 unsigned char savebyte[2];
3133 volatile u_short * const d =
3134 (volatile u_short *) sc->hpp_mem_start;
3135 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3137 /* select page 0 registers */
3138 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3140 /* reset remote DMA complete flag */
3141 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3143 /* program the write address in RAM */
3144 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3146 if (sc->hpp_mem_start) /* enable memory mapped I/O */
3147 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3148 ~(ED_HPP_OPTION_MEM_DISABLE |
3149 ED_HPP_OPTION_BOOT_ROM_ENB));
3154 if (sc->hpp_mem_start) { /* Memory mapped I/O port */
3156 total_len += (len = m->m_len);
3158 caddr_t data = mtod(m, caddr_t);
3159 /* finish the last word of the previous mbuf */
3161 savebyte[1] = *data;
3162 *d = *((ushort *) savebyte);
3163 data++; len--; wantbyte = 0;
3165 /* output contiguous words */
3166 if ((len > 3) && (use_32bit_accesses)) {
3167 volatile u_int32_t *const dl =
3168 (volatile u_int32_t *) d;
3169 u_int32_t *sl = (u_int32_t *) data;
3170 u_int32_t *fence = sl + (len >> 2);
3178 /* finish off remain 16 bit writes */
3180 u_short *s = (u_short *) data;
3181 u_short *fence = s + (len >> 1);
3189 /* save last byte if needed */
3190 if ((wantbyte = (len == 1)) != 0)
3191 savebyte[0] = *data;
3193 m = m->m_next; /* to next mbuf */
3195 if (wantbyte) /* write last byte */
3196 *d = *((u_short *) savebyte);
3198 /* use programmed I/O */
3200 total_len += (len = m->m_len);
3202 caddr_t data = mtod(m, caddr_t);
3203 /* finish the last word of the previous mbuf */
3205 savebyte[1] = *data;
3206 ed_asic_outw(sc, ED_HPP_PAGE_4,
3207 *((u_short *)savebyte));
3212 /* output contiguous words */
3213 if ((len > 3) && use_32bit_accesses) {
3214 ed_asic_outsl(sc, ED_HPP_PAGE_4,
3219 /* finish off remaining 16 bit accesses */
3221 ed_asic_outsw(sc, ED_HPP_PAGE_4,
3226 if ((wantbyte = (len == 1)) != 0)
3227 savebyte[0] = *data;
3232 if (wantbyte) /* spit last byte */
3233 ed_asic_outw(sc, ED_HPP_PAGE_4, *(u_short *)savebyte);
3237 if (sc->hpp_mem_start) /* turn off memory mapped i/o */
3238 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3243 #ifndef ED_NO_MIIBUS
3245 * MII bus support routines.
3248 ed_miibus_readreg(dev, phy, reg)
3252 struct ed_softc *sc;
3256 sc = device_get_softc(dev);
3262 (*sc->mii_writebits)(sc, 0xffffffff, 32);
3263 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
3264 (*sc->mii_writebits)(sc, ED_MII_READOP, ED_MII_OP_BITS);
3265 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
3266 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
3268 failed = (*sc->mii_readbits)(sc, ED_MII_ACK_BITS);
3269 val = (*sc->mii_readbits)(sc, ED_MII_DATA_BITS);
3270 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
3273 return (failed ? 0 : val);
3277 ed_miibus_writereg(dev, phy, reg, data)
3281 struct ed_softc *sc;
3285 sc = device_get_softc(dev);
3291 (*sc->mii_writebits)(sc, 0xffffffff, 32);
3292 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
3293 (*sc->mii_writebits)(sc, ED_MII_WRITEOP, ED_MII_OP_BITS);
3294 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
3295 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
3296 (*sc->mii_writebits)(sc, ED_MII_TURNAROUND, ED_MII_TURNAROUND_BITS);
3297 (*sc->mii_writebits)(sc, data, ED_MII_DATA_BITS);
3298 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
3307 struct ed_softc *sc;
3308 struct mii_data *mii;
3311 if (sc->gone || sc->miibus == NULL)
3314 mii = device_get_softc(sc->miibus);
3315 return mii_mediachg(mii);
3319 ed_ifmedia_sts(ifp, ifmr)
3321 struct ifmediareq *ifmr;
3323 struct ed_softc *sc;
3324 struct mii_data *mii;
3327 if (sc->gone || sc->miibus == NULL)
3330 mii = device_get_softc(sc->miibus);
3332 ifmr->ifm_active = mii->mii_media_active;
3333 ifmr->ifm_status = mii->mii_media_status;
3337 ed_child_detached(dev, child)
3341 struct ed_softc *sc;
3343 sc = device_get_softc(dev);
3344 if (child == sc->miibus)
3351 struct ed_softc *sc;
3353 struct ifnet *ifp = (struct ifnet *)sc;
3357 /* Bit 6 in AX88190 RCR register must be set. */
3358 if (sc->chip_type == ED_CHIP_TYPE_AX88190)
3363 /* set page 1 registers */
3364 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
3366 if (ifp->if_flags & IFF_PROMISC) {
3369 * Reconfigure the multicast filter.
3371 for (i = 0; i < 8; i++)
3372 ed_nic_outb(sc, ED_P1_MAR(i), 0xff);
3375 * And turn on promiscuous mode. Also enable reception of
3376 * runts and packets with CRC & alignment errors.
3378 /* Set page 0 registers */
3379 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3381 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
3382 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1);
3384 /* set up multicast addresses and filter modes */
3385 if (ifp->if_flags & IFF_MULTICAST) {
3388 if (ifp->if_flags & IFF_ALLMULTI) {
3389 mcaf[0] = 0xffffffff;
3390 mcaf[1] = 0xffffffff;
3392 ds_getmcaf(sc, mcaf);
3395 * Set multicast filter on chip.
3397 for (i = 0; i < 8; i++)
3398 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]);
3400 /* Set page 0 registers */
3401 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3403 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1);
3407 * Initialize multicast address hashing registers to
3408 * not accept multicasts.
3410 for (i = 0; i < 8; ++i)
3411 ed_nic_outb(sc, ED_P1_MAR(i), 0x00);
3413 /* Set page 0 registers */
3414 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3416 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1);
3423 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3427 * Compute crc for ethernet address
3433 #define POLYNOMIAL 0x04c11db6
3434 register u_int32_t crc = 0xffffffff;
3435 register int carry, i, j;
3438 for (i = 6; --i >= 0;) {
3440 for (j = 8; --j >= 0;) {
3441 carry = ((crc & 0x80000000) ? 1 : 0) ^ (b & 0x01);
3445 crc = (crc ^ POLYNOMIAL) | carry;
3453 * Compute the multicast address filter from the
3454 * list of multicast addresses we need to listen to.
3457 ds_getmcaf(sc, mcaf)
3458 struct ed_softc *sc;
3461 register u_int32_t index;
3462 register u_char *af = (u_char *) mcaf;
3463 struct ifmultiaddr *ifma;
3468 TAILQ_FOREACH(ifma, &sc->arpcom.ac_if.if_multiaddrs, ifma_link) {
3469 if (ifma->ifma_addr->sa_family != AF_LINK)
3471 index = ds_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr))
3473 af[index >> 3] |= 1 << (index & 7);