2 * Copyright (c) 1995, David Greenman
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef SYS_DEV_ED_IF_EDVAR_H
31 #define SYS_DEV_ED_IF_EDVAR_H
33 * ed_softc: per line info and status
36 struct arpcom arpcom; /* ethernet common */
38 char *type_str; /* pointer to type string */
39 u_char vendor; /* interface vendor */
40 u_char type; /* interface type code */
41 u_char chip_type; /* the type of chip (one of ED_CHIP_TYPE_*) */
42 u_char gone; /* HW missing, presumed having a good time */
43 u_char isa16bit; /* width of access to card 0=8 or 1=16 */
44 u_char mem_shared; /* NIC memory is shared with host */
45 u_char xmit_busy; /* transmitter is busy */
47 int port_rid; /* resource id for port range */
48 int port_used; /* nonzero if ports used */
49 struct resource* port_res; /* resource for port range */
50 bus_space_tag_t port_bst;
51 bus_space_handle_t port_bsh;
52 int mem_rid; /* resource id for memory range */
53 int mem_used; /* nonzero if memory used */
54 struct resource* mem_res; /* resource for memory range */
55 bus_space_tag_t mem_bst;
56 bus_space_handle_t mem_bsh;
57 int irq_rid; /* resource id for irq */
58 struct resource* irq_res; /* resource for irq */
59 void* irq_handle; /* handle for irq handler */
60 device_t miibus; /* MII bus for cards with MII. */
61 void (*mii_writebits)(struct ed_softc *, u_int, int);
62 u_int (*mii_readbits)(struct ed_softc *, int);
63 struct callout_handle tick_ch; /* Callout handle for ed_tick */
65 int nic_offset; /* NIC (DS8390) I/O bus address offset */
66 int asic_offset; /* ASIC I/O bus address offset */
69 * The following 'proto' variable is part of a work-around for 8013EBT asics
70 * being write-only. It's sort of a prototype/shadow of the real thing.
76 * HP PC LAN PLUS card support.
79 u_short hpp_options; /* flags controlling behaviour of the HP card */
80 u_short hpp_id; /* software revision and other fields */
81 caddr_t hpp_mem_start; /* Memory-mapped IO register address */
83 caddr_t mem_start; /* NIC memory start address */
84 caddr_t mem_end; /* NIC memory end address */
85 uint32_t mem_size; /* total NIC memory size */
86 caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */
88 u_char txb_cnt; /* number of transmit buffers */
89 u_char txb_inuse; /* number of TX buffers currently in-use */
91 u_char txb_new; /* pointer to where new buffer will be added */
92 u_char txb_next_tx; /* pointer to next buffer ready to xmit */
93 u_short txb_len[8]; /* buffered xmit buffer lengths */
94 u_char tx_page_start; /* first page of TX buffer area */
95 u_char rec_page_start; /* first page of RX ring-buffer */
96 u_char rec_page_stop; /* last page of RX ring-buffer */
97 u_char next_packet; /* pointer to next unread RX packet */
98 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */
101 #define ed_nic_inb(sc, port) \
102 bus_space_read_1(sc->port_bst, sc->port_bsh, (sc)->nic_offset + (port))
104 #define ed_nic_outb(sc, port, value) \
105 bus_space_write_1(sc->port_bst, sc->port_bsh, \
106 (sc)->nic_offset + (port), (value))
108 #define ed_nic_inw(sc, port) \
109 bus_space_read_2(sc->port_bst, sc->port_bsh, (sc)->nic_offset + (port))
111 #define ed_nic_outw(sc, port, value) \
112 bus_space_write_2(sc->port_bst, sc->port_bsh, \
113 (sc)->nic_offset + (port), (value))
115 #define ed_nic_insb(sc, port, addr, count) \
116 bus_space_read_multi_1(sc->port_bst, sc->port_bsh, \
117 (sc)->nic_offset + (port), (addr), (count))
119 #define ed_nic_outsb(sc, port, addr, count) \
120 bus_space_write_multi_1(sc->port_bst, sc->port_bsh, \
121 (sc)->nic_offset + (port), (addr), (count))
123 #define ed_nic_insw(sc, port, addr, count) \
124 bus_space_read_multi_2(sc->port_bst, sc->port_bsh, \
125 (sc)->nic_offset + (port), (uint16_t *)(addr), (count))
127 #define ed_nic_outsw(sc, port, addr, count) \
128 bus_space_write_multi_2(sc->port_bst, sc->port_bsh, \
129 (sc)->nic_offset + (port), (uint16_t *)(addr), (count))
131 #define ed_nic_insl(sc, port, addr, count) \
132 bus_space_read_multi_4(sc->port_bst, sc->port_bsh, \
133 (sc)->nic_offset + (port), (uint32_t *)(addr), (count))
135 #define ed_nic_outsl(sc, port, addr, count) \
136 bus_space_write_multi_4(sc->port_bst, sc->port_bsh, \
137 (sc)->nic_offset + (port), (uint32_t *)(addr), (count))
139 #define ed_asic_inb(sc, port) \
140 bus_space_read_1(sc->port_bst, sc->port_bsh, \
141 (sc)->asic_offset + (port))
143 #define ed_asic_outb(sc, port, value) \
144 bus_space_write_1(sc->port_bst, sc->port_bsh, \
145 (sc)->asic_offset + (port), (value))
147 #define ed_asic_inw(sc, port) \
148 bus_space_read_2(sc->port_bst, sc->port_bsh, \
149 (sc)->asic_offset + (port))
151 #define ed_asic_outw(sc, port, value) \
152 bus_space_write_2(sc->port_bst, sc->port_bsh, \
153 (sc)->asic_offset + (port), (value))
155 #define ed_asic_insb(sc, port, addr, count) \
156 bus_space_read_multi_1(sc->port_bst, sc->port_bsh, \
157 (sc)->asic_offset + (port), (addr), (count))
159 #define ed_asic_outsb(sc, port, addr, count) \
160 bus_space_write_multi_1(sc->port_bst, sc->port_bsh, \
161 (sc)->asic_offset + (port), (addr), (count))
163 #define ed_asic_insw(sc, port, addr, count) \
164 bus_space_read_multi_2(sc->port_bst, sc->port_bsh, \
165 (sc)->asic_offset + (port), (uint16_t *)(addr), (count))
167 #define ed_asic_outsw(sc, port, addr, count) \
168 bus_space_write_multi_2(sc->port_bst, sc->port_bsh, \
169 (sc)->asic_offset + (port), (uint16_t *)(addr), (count))
171 #define ed_asic_insl(sc, port, addr, count) \
172 bus_space_read_multi_4(sc->port_bst, sc->port_bsh, \
173 (sc)->asic_offset + (port), (uint32_t *)(addr), (count))
175 #define ed_asic_outsl(sc, port, addr, count) \
176 bus_space_write_multi_4(sc->port_bst, sc->port_bsh, \
177 (sc)->asic_offset + (port), (uint32_t *)(addr), (count))
179 void ed_release_resources(device_t);
180 int ed_alloc_port(device_t, int, int);
181 int ed_alloc_memory(device_t, int, int);
182 int ed_alloc_irq(device_t, int, int);
184 int ed_probe_generic8390(struct ed_softc *);
185 int ed_probe_WD80x3(device_t, int, int);
186 int ed_probe_WD80x3_generic(device_t, int, uint16_t *[]);
188 int ed_probe_3Com(device_t, int, int);
191 int ed_probe_SIC(device_t, int, int);
193 int ed_probe_Novell(device_t, int, int);
194 void ed_Novell_read_mac(struct ed_softc *);
196 int ed_probe_HP_pclanp(device_t, int, int);
199 int ed_attach(device_t);
200 int ed_detach(device_t);
201 int ed_clear_memory(device_t);
202 int ed_isa_mem_ok(device_t, u_long, u_int); /* XXX isa specific */
203 void ed_stop(struct ed_softc *);
204 void ed_pio_readmem(struct ed_softc *, long, uint8_t *, uint16_t);
205 void ed_pio_writemem(struct ed_softc *, uint8_t *, uint16_t, uint16_t);
207 int ed_miibus_readreg(device_t, int, int);
208 void ed_miibus_writereg(device_t, int, int, int);
209 int ed_ifmedia_upd(struct ifnet *);
210 void ed_ifmedia_sts(struct ifnet *, struct ifmediareq *);
211 void ed_child_detached(device_t, device_t);
214 /* The following is unsatisfying XXX */
216 void ed_hpp_set_physical_link(struct ed_softc *);
217 void ed_hpp_readmem(struct ed_softc *, long, uint8_t *, uint16_t);
218 u_short ed_hpp_write_mbufs(struct ed_softc *, struct mbuf *, int);
221 void ed_disable_16bit_access(struct ed_softc *);
222 void ed_enable_16bit_access(struct ed_softc *);
224 driver_intr_t edintr;
226 extern devclass_t ed_devclass;
232 #define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */
233 #define ED_VENDOR_3COM 0x01 /* 3Com */
234 #define ED_VENDOR_NOVELL 0x02 /* Novell */
235 #define ED_VENDOR_HP 0x03 /* Hewlett Packard */
236 #define ED_VENDOR_SIC 0x04 /* Allied-Telesis SIC */
239 * Compile-time config flags
242 * this sets the default for enabling/disabling the transceiver
244 #define ED_FLAGS_DISABLE_TRANCEIVER 0x0001
247 * This forces the board to be used in 8/16bit mode even if it
248 * autoconfigs differently
250 #define ED_FLAGS_FORCE_8BIT_MODE 0x0002
251 #define ED_FLAGS_FORCE_16BIT_MODE 0x0004
254 * This disables the use of double transmit buffers.
256 #define ED_FLAGS_NO_MULTI_BUFFERING 0x0008
259 * This forces all operations with the NIC memory to use Programmed
260 * I/O (i.e. not via shared memory)
262 #define ED_FLAGS_FORCE_PIO 0x0010
265 * These are flags describing the chip type.
267 #define ED_FLAGS_TOSH_ETHER 0x10000
268 #define ED_FLAGS_GWETHER 0x20000
269 #define ED_FLAGS_AX88190 0x30000
270 #define ED_FLAGS_LINKSYS 0x80000
272 #define ED_FLAGS_GETTYPE(flg) ((flg) & 0xff0000)
274 #endif /* SYS_DEV_ED_IF_EDVAR_H */