1 /*******************************************************************************
3 Copyright (c) 2001-2007, Intel Corporation
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32 *******************************************************************************/
36 #include "e1000_api.h"
37 #include "e1000_nvm.h"
40 * e1000_raise_eec_clk - Raise EEPROM clock
41 * @hw: pointer to the HW structure
42 * @eecd: pointer to the EEPROM
44 * Enable/Raise the EEPROM clock bit.
46 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
48 *eecd = *eecd | E1000_EECD_SK;
49 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
50 E1000_WRITE_FLUSH(hw);
51 usec_delay(hw->nvm.delay_usec);
55 * e1000_lower_eec_clk - Lower EEPROM clock
56 * @hw: pointer to the HW structure
57 * @eecd: pointer to the EEPROM
59 * Clear/Lower the EEPROM clock bit.
61 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
63 *eecd = *eecd & ~E1000_EECD_SK;
64 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
65 E1000_WRITE_FLUSH(hw);
66 usec_delay(hw->nvm.delay_usec);
70 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
71 * @hw: pointer to the HW structure
72 * @data: data to send to the EEPROM
73 * @count: number of bits to shift out
75 * We need to shift 'count' bits out to the EEPROM. So, the value in the
76 * "data" parameter will be shifted out to the EEPROM one bit at a time.
77 * In order to do this, "data" must be broken down into bits.
79 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
81 struct e1000_nvm_info *nvm = &hw->nvm;
82 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
85 DEBUGFUNC("e1000_shift_out_eec_bits");
87 mask = 0x01 << (count - 1);
88 if (nvm->type == e1000_nvm_eeprom_microwire)
89 eecd &= ~E1000_EECD_DO;
90 else if (nvm->type == e1000_nvm_eeprom_spi)
91 eecd |= E1000_EECD_DO;
94 eecd &= ~E1000_EECD_DI;
97 eecd |= E1000_EECD_DI;
99 E1000_WRITE_REG(hw, E1000_EECD, eecd);
100 E1000_WRITE_FLUSH(hw);
102 usec_delay(nvm->delay_usec);
104 e1000_raise_eec_clk(hw, &eecd);
105 e1000_lower_eec_clk(hw, &eecd);
110 eecd &= ~E1000_EECD_DI;
111 E1000_WRITE_REG(hw, E1000_EECD, eecd);
115 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
116 * @hw: pointer to the HW structure
117 * @count: number of bits to shift in
119 * In order to read a register from the EEPROM, we need to shift 'count' bits
120 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
121 * the EEPROM (setting the SK bit), and then reading the value of the data out
122 * "DO" bit. During this "shifting in" process the data in "DI" bit should
125 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
131 DEBUGFUNC("e1000_shift_in_eec_bits");
133 eecd = E1000_READ_REG(hw, E1000_EECD);
135 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
138 for (i = 0; i < count; i++) {
140 e1000_raise_eec_clk(hw, &eecd);
142 eecd = E1000_READ_REG(hw, E1000_EECD);
144 eecd &= ~E1000_EECD_DI;
145 if (eecd & E1000_EECD_DO)
148 e1000_lower_eec_clk(hw, &eecd);
155 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
156 * @hw: pointer to the HW structure
157 * @ee_reg: EEPROM flag for polling
159 * Polls the EEPROM status bit for either read or write completion based
160 * upon the value of 'ee_reg'.
162 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
164 u32 attempts = 100000;
166 s32 ret_val = -E1000_ERR_NVM;
168 DEBUGFUNC("e1000_poll_eerd_eewr_done");
170 for (i = 0; i < attempts; i++) {
171 if (ee_reg == E1000_NVM_POLL_READ)
172 reg = E1000_READ_REG(hw, E1000_EERD);
174 reg = E1000_READ_REG(hw, E1000_EEWR);
176 if (reg & E1000_NVM_RW_REG_DONE) {
177 ret_val = E1000_SUCCESS;
188 * e1000_acquire_nvm_generic - Generic request for access to EEPROM
189 * @hw: pointer to the HW structure
191 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
192 * Return successful if access grant bit set, else clear the request for
193 * EEPROM access and return -E1000_ERR_NVM (-1).
195 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
197 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
198 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
199 s32 ret_val = E1000_SUCCESS;
201 DEBUGFUNC("e1000_acquire_nvm_generic");
203 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
204 eecd = E1000_READ_REG(hw, E1000_EECD);
207 if (eecd & E1000_EECD_GNT)
210 eecd = E1000_READ_REG(hw, E1000_EECD);
215 eecd &= ~E1000_EECD_REQ;
216 E1000_WRITE_REG(hw, E1000_EECD, eecd);
217 DEBUGOUT("Could not acquire NVM grant\n");
218 ret_val = -E1000_ERR_NVM;
225 * e1000_standby_nvm - Return EEPROM to standby state
226 * @hw: pointer to the HW structure
228 * Return the EEPROM to a standby state.
230 static void e1000_standby_nvm(struct e1000_hw *hw)
232 struct e1000_nvm_info *nvm = &hw->nvm;
233 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
235 DEBUGFUNC("e1000_standby_nvm");
237 if (nvm->type == e1000_nvm_eeprom_microwire) {
238 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
239 E1000_WRITE_REG(hw, E1000_EECD, eecd);
240 E1000_WRITE_FLUSH(hw);
241 usec_delay(nvm->delay_usec);
243 e1000_raise_eec_clk(hw, &eecd);
246 eecd |= E1000_EECD_CS;
247 E1000_WRITE_REG(hw, E1000_EECD, eecd);
248 E1000_WRITE_FLUSH(hw);
249 usec_delay(nvm->delay_usec);
251 e1000_lower_eec_clk(hw, &eecd);
252 } else if (nvm->type == e1000_nvm_eeprom_spi) {
253 /* Toggle CS to flush commands */
254 eecd |= E1000_EECD_CS;
255 E1000_WRITE_REG(hw, E1000_EECD, eecd);
256 E1000_WRITE_FLUSH(hw);
257 usec_delay(nvm->delay_usec);
258 eecd &= ~E1000_EECD_CS;
259 E1000_WRITE_REG(hw, E1000_EECD, eecd);
260 E1000_WRITE_FLUSH(hw);
261 usec_delay(nvm->delay_usec);
266 * e1000_stop_nvm - Terminate EEPROM command
267 * @hw: pointer to the HW structure
269 * Terminates the current command by inverting the EEPROM's chip select pin.
271 void e1000_stop_nvm(struct e1000_hw *hw)
275 DEBUGFUNC("e1000_stop_nvm");
277 eecd = E1000_READ_REG(hw, E1000_EECD);
278 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
280 eecd |= E1000_EECD_CS;
281 e1000_lower_eec_clk(hw, &eecd);
282 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
283 /* CS on Microcwire is active-high */
284 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
285 E1000_WRITE_REG(hw, E1000_EECD, eecd);
286 e1000_raise_eec_clk(hw, &eecd);
287 e1000_lower_eec_clk(hw, &eecd);
292 * e1000_release_nvm_generic - Release exclusive access to EEPROM
293 * @hw: pointer to the HW structure
295 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
297 void e1000_release_nvm_generic(struct e1000_hw *hw)
301 DEBUGFUNC("e1000_release_nvm_generic");
305 eecd = E1000_READ_REG(hw, E1000_EECD);
306 eecd &= ~E1000_EECD_REQ;
307 E1000_WRITE_REG(hw, E1000_EECD, eecd);
311 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
312 * @hw: pointer to the HW structure
314 * Setups the EEPROM for reading and writing.
316 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
318 struct e1000_nvm_info *nvm = &hw->nvm;
319 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
320 s32 ret_val = E1000_SUCCESS;
324 DEBUGFUNC("e1000_ready_nvm_eeprom");
326 if (nvm->type == e1000_nvm_eeprom_microwire) {
327 /* Clear SK and DI */
328 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
329 E1000_WRITE_REG(hw, E1000_EECD, eecd);
331 eecd |= E1000_EECD_CS;
332 E1000_WRITE_REG(hw, E1000_EECD, eecd);
333 } else if (nvm->type == e1000_nvm_eeprom_spi) {
334 /* Clear SK and CS */
335 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
336 E1000_WRITE_REG(hw, E1000_EECD, eecd);
338 timeout = NVM_MAX_RETRY_SPI;
341 * Read "Status Register" repeatedly until the LSB is cleared.
342 * The EEPROM will signal that the command has been completed
343 * by clearing bit 0 of the internal status register. If it's
344 * not cleared within 'timeout', then error out.
347 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
348 hw->nvm.opcode_bits);
349 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
350 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
354 e1000_standby_nvm(hw);
359 DEBUGOUT("SPI NVM Status error\n");
360 ret_val = -E1000_ERR_NVM;
370 * e1000_read_nvm_spi - Read EEPROM's using SPI
371 * @hw: pointer to the HW structure
372 * @offset: offset of word in the EEPROM to read
373 * @words: number of words to read
374 * @data: word read from the EEPROM
376 * Reads a 16 bit word from the EEPROM.
378 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
380 struct e1000_nvm_info *nvm = &hw->nvm;
384 u8 read_opcode = NVM_READ_OPCODE_SPI;
386 DEBUGFUNC("e1000_read_nvm_spi");
389 * A check for invalid values: offset too large, too many words,
390 * and not enough words.
392 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
394 DEBUGOUT("nvm parameter(s) out of bounds\n");
395 ret_val = -E1000_ERR_NVM;
399 ret_val = e1000_acquire_nvm(hw);
403 ret_val = e1000_ready_nvm_eeprom(hw);
407 e1000_standby_nvm(hw);
409 if ((nvm->address_bits == 8) && (offset >= 128))
410 read_opcode |= NVM_A8_OPCODE_SPI;
412 /* Send the READ command (opcode + addr) */
413 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
414 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
417 * Read the data. SPI NVMs increment the address with each byte
418 * read and will roll over if reading beyond the end. This allows
419 * us to read the whole NVM from any offset
421 for (i = 0; i < words; i++) {
422 word_in = e1000_shift_in_eec_bits(hw, 16);
423 data[i] = (word_in >> 8) | (word_in << 8);
427 e1000_release_nvm(hw);
434 * e1000_read_nvm_microwire - Reads EEPROM's using microwire
435 * @hw: pointer to the HW structure
436 * @offset: offset of word in the EEPROM to read
437 * @words: number of words to read
438 * @data: word read from the EEPROM
440 * Reads a 16 bit word from the EEPROM.
442 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
445 struct e1000_nvm_info *nvm = &hw->nvm;
448 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
450 DEBUGFUNC("e1000_read_nvm_microwire");
453 * A check for invalid values: offset too large, too many words,
454 * and not enough words.
456 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
458 DEBUGOUT("nvm parameter(s) out of bounds\n");
459 ret_val = -E1000_ERR_NVM;
463 ret_val = e1000_acquire_nvm(hw);
467 ret_val = e1000_ready_nvm_eeprom(hw);
471 for (i = 0; i < words; i++) {
472 /* Send the READ command (opcode + addr) */
473 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
474 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
478 * Read the data. For microwire, each word requires the
479 * overhead of setup and tear-down.
481 data[i] = e1000_shift_in_eec_bits(hw, 16);
482 e1000_standby_nvm(hw);
486 e1000_release_nvm(hw);
493 * e1000_read_nvm_eerd - Reads EEPROM using EERD register
494 * @hw: pointer to the HW structure
495 * @offset: offset of word in the EEPROM to read
496 * @words: number of words to read
497 * @data: word read from the EEPROM
499 * Reads a 16 bit word from the EEPROM using the EERD register.
501 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
503 struct e1000_nvm_info *nvm = &hw->nvm;
505 s32 ret_val = E1000_SUCCESS;
507 DEBUGFUNC("e1000_read_nvm_eerd");
510 * A check for invalid values: offset too large, too many words,
511 * and not enough words.
513 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
515 DEBUGOUT("nvm parameter(s) out of bounds\n");
516 ret_val = -E1000_ERR_NVM;
520 for (i = 0; i < words; i++) {
521 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
522 E1000_NVM_RW_REG_START;
524 E1000_WRITE_REG(hw, E1000_EERD, eerd);
525 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
529 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
530 E1000_NVM_RW_REG_DATA);
538 * e1000_write_nvm_spi - Write to EEPROM using SPI
539 * @hw: pointer to the HW structure
540 * @offset: offset within the EEPROM to be written to
541 * @words: number of words to write
542 * @data: 16 bit word(s) to be written to the EEPROM
544 * Writes data to EEPROM at offset using SPI interface.
546 * If e1000_update_nvm_checksum is not called after this function , the
547 * EEPROM will most likley contain an invalid checksum.
549 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
551 struct e1000_nvm_info *nvm = &hw->nvm;
555 DEBUGFUNC("e1000_write_nvm_spi");
558 * A check for invalid values: offset too large, too many words,
559 * and not enough words.
561 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
563 DEBUGOUT("nvm parameter(s) out of bounds\n");
564 ret_val = -E1000_ERR_NVM;
568 ret_val = e1000_acquire_nvm(hw);
574 while (widx < words) {
575 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
577 ret_val = e1000_ready_nvm_eeprom(hw);
581 e1000_standby_nvm(hw);
583 /* Send the WRITE ENABLE command (8 bit opcode) */
584 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
587 e1000_standby_nvm(hw);
590 * Some SPI eeproms use the 8th address bit embedded in the
593 if ((nvm->address_bits == 8) && (offset >= 128))
594 write_opcode |= NVM_A8_OPCODE_SPI;
596 /* Send the Write command (8-bit opcode + addr) */
597 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
598 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
601 /* Loop to allow for up to whole page write of eeprom */
602 while (widx < words) {
603 u16 word_out = data[widx];
604 word_out = (word_out >> 8) | (word_out << 8);
605 e1000_shift_out_eec_bits(hw, word_out, 16);
608 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
609 e1000_standby_nvm(hw);
617 e1000_release_nvm(hw);
624 * e1000_write_nvm_microwire - Writes EEPROM using microwire
625 * @hw: pointer to the HW structure
626 * @offset: offset within the EEPROM to be written to
627 * @words: number of words to write
628 * @data: 16 bit word(s) to be written to the EEPROM
630 * Writes data to EEPROM at offset using microwire interface.
632 * If e1000_update_nvm_checksum is not called after this function , the
633 * EEPROM will most likley contain an invalid checksum.
635 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
638 struct e1000_nvm_info *nvm = &hw->nvm;
641 u16 words_written = 0;
644 DEBUGFUNC("e1000_write_nvm_microwire");
647 * A check for invalid values: offset too large, too many words,
648 * and not enough words.
650 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
652 DEBUGOUT("nvm parameter(s) out of bounds\n");
653 ret_val = -E1000_ERR_NVM;
657 ret_val = e1000_acquire_nvm(hw);
661 ret_val = e1000_ready_nvm_eeprom(hw);
665 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
666 (u16)(nvm->opcode_bits + 2));
668 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
670 e1000_standby_nvm(hw);
672 while (words_written < words) {
673 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
676 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
679 e1000_shift_out_eec_bits(hw, data[words_written], 16);
681 e1000_standby_nvm(hw);
683 for (widx = 0; widx < 200; widx++) {
684 eecd = E1000_READ_REG(hw, E1000_EECD);
685 if (eecd & E1000_EECD_DO)
691 DEBUGOUT("NVM Write did not complete\n");
692 ret_val = -E1000_ERR_NVM;
696 e1000_standby_nvm(hw);
701 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
702 (u16)(nvm->opcode_bits + 2));
704 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
707 e1000_release_nvm(hw);
714 * e1000_read_part_num_generic - Read device part number
715 * @hw: pointer to the HW structure
716 * @part_num: pointer to device part number
718 * Reads the product board assembly (PBA) number from the EEPROM and stores
719 * the value in part_num.
721 s32 e1000_read_part_num_generic(struct e1000_hw *hw, u32 *part_num)
726 DEBUGFUNC("e1000_read_part_num_generic");
728 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
730 DEBUGOUT("NVM Read Error\n");
733 *part_num = (u32)(nvm_data << 16);
735 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
737 DEBUGOUT("NVM Read Error\n");
740 *part_num |= nvm_data;
747 * e1000_read_mac_addr_generic - Read device MAC address
748 * @hw: pointer to the HW structure
750 * Reads the device MAC address from the EEPROM and stores the value.
751 * Since devices with two ports use the same EEPROM, we increment the
752 * last bit in the MAC address for the second port.
754 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
756 s32 ret_val = E1000_SUCCESS;
757 u16 offset, nvm_data, i;
759 DEBUGFUNC("e1000_read_mac_addr");
761 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
763 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
765 DEBUGOUT("NVM Read Error\n");
768 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
769 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
772 /* Flip last bit of mac address if we're on second port */
773 if (hw->bus.func == E1000_FUNC_1)
774 hw->mac.perm_addr[5] ^= 1;
776 for (i = 0; i < ETH_ADDR_LEN; i++)
777 hw->mac.addr[i] = hw->mac.perm_addr[i];
784 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
785 * @hw: pointer to the HW structure
787 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
788 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
790 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
792 s32 ret_val = E1000_SUCCESS;
796 DEBUGFUNC("e1000_validate_nvm_checksum_generic");
798 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
799 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
801 DEBUGOUT("NVM Read Error\n");
804 checksum += nvm_data;
807 if (checksum != (u16) NVM_SUM) {
808 DEBUGOUT("NVM Checksum Invalid\n");
809 ret_val = -E1000_ERR_NVM;
818 * e1000_update_nvm_checksum_generic - Update EEPROM checksum
819 * @hw: pointer to the HW structure
821 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
822 * up to the checksum. Then calculates the EEPROM checksum and writes the
823 * value to the EEPROM.
825 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
831 DEBUGFUNC("e1000_update_nvm_checksum");
833 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
834 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
836 DEBUGOUT("NVM Read Error while updating checksum.\n");
839 checksum += nvm_data;
841 checksum = (u16) NVM_SUM - checksum;
842 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
844 DEBUGOUT("NVM Write Error while updating checksum.\n");
852 * e1000_reload_nvm_generic - Reloads EEPROM
853 * @hw: pointer to the HW structure
855 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
856 * extended control register.
858 void e1000_reload_nvm_generic(struct e1000_hw *hw)
862 DEBUGFUNC("e1000_reload_nvm_generic");
865 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
866 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
867 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
868 E1000_WRITE_FLUSH(hw);
871 /* Function pointers local to this file and not intended for public use */
874 * e1000_acquire_nvm - Acquire exclusive access to EEPROM
875 * @hw: pointer to the HW structure
877 * For those silicon families which have implemented a NVM acquire function,
878 * run the defined function else return success.
880 s32 e1000_acquire_nvm(struct e1000_hw *hw)
882 if (hw->func.acquire_nvm)
883 return hw->func.acquire_nvm(hw);
885 return E1000_SUCCESS;
889 * e1000_release_nvm - Release exclusive access to EEPROM
890 * @hw: pointer to the HW structure
892 * For those silicon families which have implemented a NVM release function,
893 * run the defined fucntion else return success.
895 void e1000_release_nvm(struct e1000_hw *hw)
897 if (hw->func.release_nvm)
898 hw->func.release_nvm(hw);