1 /*******************************************************************************
3 Copyright (c) 2001-2002 Intel Corporation
6 Redistribution and use in source and binary forms of the Software, with or
7 without modification, are permitted provided that the following conditions
10 1. Redistributions of source code of the Software may retain the above
11 copyright notice, this list of conditions and the following disclaimer.
13 2. Redistributions in binary form of the Software may reproduce the above
14 copyright notice, this list of conditions and the following disclaimer
15 in the documentation and/or other materials provided with the
18 3. Neither the name of the Intel Corporation nor the names of its
19 contributors shall be used to endorse or promote products derived from
20 this Software without specific prior written permission.
22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS CONTRIBUTORS BE LIABLE
26 FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 *******************************************************************************/
38 * Shared functions for accessing and configuring the MAC
41 #include <dev/em/if_em_hw.h>
43 static int32_t em_setup_fiber_link(struct em_hw *hw);
44 static int32_t em_setup_copper_link(struct em_hw *hw);
45 static int32_t em_phy_force_speed_duplex(struct em_hw *hw);
46 static int32_t em_config_mac_to_phy(struct em_hw *hw);
47 static int32_t em_force_mac_fc(struct em_hw *hw);
48 static void em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
49 static void em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
50 static void em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count);
51 static uint16_t em_shift_in_mdi_bits(struct em_hw *hw);
52 static int32_t em_phy_reset_dsp(struct em_hw *hw);
53 static void em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd);
54 static void em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd);
55 static void em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, uint16_t count);
56 static uint16_t em_shift_in_ee_bits(struct em_hw *hw);
57 static void em_setup_eeprom(struct em_hw *hw);
58 static void em_standby_eeprom(struct em_hw *hw);
59 static int32_t em_id_led_init(struct em_hw * hw);
61 /******************************************************************************
62 * Reset the transmit and receive units; mask and clear all interrupts.
64 * hw - Struct containing variables accessed by shared code
65 *****************************************************************************/
67 em_reset_hw(struct em_hw *hw)
73 uint16_t pci_cmd_word;
75 DEBUGFUNC("em_reset_hw");
77 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
78 if(hw->mac_type == em_82542_rev2_0) {
79 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) {
80 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
81 pci_cmd_word = hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE;
82 em_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &pci_cmd_word);
86 /* Clear interrupt mask to stop board from generating interrupts */
87 DEBUGOUT("Masking off all interrupts\n");
88 E1000_WRITE_REG(hw, IMC, 0xffffffff);
90 /* Disable the Transmit and Receive units. Then delay to allow
91 * any pending transactions to complete before we hit the MAC with
94 E1000_WRITE_REG(hw, RCTL, 0);
95 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
97 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
98 hw->tbi_compatibility_on = FALSE;
100 /* Delay to allow any outstanding PCI transactions to complete before
101 * resetting the device
105 /* Issue a global reset to the MAC. This will reset the chip's
106 * transmit, receive, DMA, and link units. It will not effect
107 * the current PCI configuration. The global reset bit is self-
108 * clearing, and should clear within a microsecond.
110 DEBUGOUT("Issuing a global reset to MAC\n");
111 ctrl = E1000_READ_REG(hw, CTRL);
112 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
114 /* Force a reload from the EEPROM if necessary */
115 if(hw->mac_type < em_82540) {
116 /* Wait for reset to complete */
118 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
119 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
120 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
121 /* Wait for EEPROM reload */
124 /* Wait for EEPROM reload (it happens automatically) */
126 /* Dissable HW ARPs on ASF enabled adapters */
127 manc = E1000_READ_REG(hw, MANC);
128 manc &= ~(E1000_MANC_ARP_EN);
129 E1000_WRITE_REG(hw, MANC, manc);
132 /* Clear interrupt mask to stop board from generating interrupts */
133 DEBUGOUT("Masking off all interrupts\n");
134 E1000_WRITE_REG(hw, IMC, 0xffffffff);
136 /* Clear any pending interrupt events. */
137 icr = E1000_READ_REG(hw, ICR);
139 /* If MWI was previously enabled, reenable it. */
140 if(hw->mac_type == em_82542_rev2_0) {
141 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
142 em_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->pci_cmd_word);
146 /******************************************************************************
147 * Performs basic configuration of the adapter.
149 * hw - Struct containing variables accessed by shared code
151 * Assumes that the controller has previously been reset and is in a
152 * post-reset uninitialized state. Initializes the receive address registers,
153 * multicast table, and VLAN filter table. Calls routines to setup link
154 * configuration and flow control settings. Clears all on-chip counters. Leaves
155 * the transmit and receive units disabled and uninitialized.
156 *****************************************************************************/
158 em_init_hw(struct em_hw *hw)
160 uint32_t ctrl, status;
163 uint16_t pci_cmd_word;
165 DEBUGFUNC("em_init_hw");
167 /* Initialize Identification LED */
168 ret_val = em_id_led_init(hw);
170 DEBUGOUT("Error Initializing Identification LED\n");
174 /* Set the Media Type and exit with error if it is not valid. */
175 if(hw->mac_type != em_82543) {
176 /* tbi_compatibility is only valid on 82543 */
177 hw->tbi_compatibility_en = FALSE;
180 if(hw->mac_type >= em_82543) {
181 status = E1000_READ_REG(hw, STATUS);
182 if(status & E1000_STATUS_TBIMODE) {
183 hw->media_type = em_media_type_fiber;
184 /* tbi_compatibility not valid on fiber */
185 hw->tbi_compatibility_en = FALSE;
187 hw->media_type = em_media_type_copper;
190 /* This is an 82542 (fiber only) */
191 hw->media_type = em_media_type_fiber;
194 /* Disabling VLAN filtering. */
195 DEBUGOUT("Initializing the IEEE VLAN\n");
196 E1000_WRITE_REG(hw, VET, 0);
200 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
201 if(hw->mac_type == em_82542_rev2_0) {
202 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) {
203 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
204 pci_cmd_word = hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE;
205 em_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &pci_cmd_word);
207 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
211 /* Setup the receive address. This involves initializing all of the Receive
212 * Address Registers (RARs 0 - 15).
214 em_init_rx_addrs(hw);
216 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
217 if(hw->mac_type == em_82542_rev2_0) {
218 E1000_WRITE_REG(hw, RCTL, 0);
220 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
221 em_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->pci_cmd_word);
224 /* Zero out the Multicast HASH table */
225 DEBUGOUT("Zeroing the MTA\n");
226 for(i = 0; i < E1000_MC_TBL_SIZE; i++)
227 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
229 /* Set the PCI priority bit correctly in the CTRL register. This
230 * determines if the adapter gives priority to receives, or if it
231 * gives equal priority to transmits and receives.
233 if(hw->dma_fairness) {
234 ctrl = E1000_READ_REG(hw, CTRL);
235 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
238 /* Call a subroutine to configure the link and setup flow control. */
239 ret_val = em_setup_link(hw);
241 /* Clear all of the statistics registers (clear on read). It is
242 * important that we do this after we have tried to establish link
243 * because the symbol error count will increment wildly if there
246 em_clear_hw_cntrs(hw);
251 /******************************************************************************
252 * Configures flow control and link settings.
254 * hw - Struct containing variables accessed by shared code
256 * Determines which flow control settings to use. Calls the apropriate media-
257 * specific link configuration function. Configures the flow control settings.
258 * Assuming the adapter has a valid link partner, a valid link should be
259 * established. Assumes the hardware has previously been reset and the
260 * transmitter and receiver are not enabled.
261 *****************************************************************************/
263 em_setup_link(struct em_hw *hw)
267 uint16_t eeprom_data;
269 DEBUGFUNC("em_setup_link");
271 /* Read and store word 0x0F of the EEPROM. This word contains bits
272 * that determine the hardware's default PAUSE (flow control) mode,
273 * a bit that determines whether the HW defaults to enabling or
274 * disabling auto-negotiation, and the direction of the
275 * SW defined pins. If there is no SW over-ride of the flow
276 * control setting, then the variable hw->fc will
277 * be initialized based on a value in the EEPROM.
279 if(em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, &eeprom_data) < 0) {
280 DEBUGOUT("EEPROM Read Error\n");
281 return -E1000_ERR_EEPROM;
284 if(hw->fc == em_fc_default) {
285 if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
287 else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
288 EEPROM_WORD0F_ASM_DIR)
289 hw->fc = em_fc_tx_pause;
294 /* We want to save off the original Flow Control configuration just
295 * in case we get disconnected and then reconnected into a different
296 * hub or switch with different Flow Control capabilities.
298 if(hw->mac_type == em_82542_rev2_0)
299 hw->fc &= (~em_fc_tx_pause);
301 if((hw->mac_type < em_82543) && (hw->report_tx_early == 1))
302 hw->fc &= (~em_fc_rx_pause);
304 hw->original_fc = hw->fc;
306 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
308 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
309 * polarity value for the SW controlled pins, and setup the
310 * Extended Device Control reg with that info.
311 * This is needed because one of the SW controlled pins is used for
312 * signal detection. So this should be done before em_setup_pcs_link()
313 * or em_phy_setup() is called.
315 if(hw->mac_type == em_82543) {
316 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
318 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
321 /* Call the necessary subroutine to configure the link. */
322 ret_val = (hw->media_type == em_media_type_fiber) ?
323 em_setup_fiber_link(hw) :
324 em_setup_copper_link(hw);
326 /* Initialize the flow control address, type, and PAUSE timer
327 * registers to their default values. This is done even if flow
328 * control is disabled, because it does not hurt anything to
329 * initialize these registers.
331 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
333 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
334 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
335 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
336 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
338 /* Set the flow control receive threshold registers. Normally,
339 * these registers will be set to a default threshold that may be
340 * adjusted later by the driver's runtime code. However, if the
341 * ability to transmit pause frames in not enabled, then these
342 * registers will be set to 0.
344 if(!(hw->fc & em_fc_tx_pause)) {
345 E1000_WRITE_REG(hw, FCRTL, 0);
346 E1000_WRITE_REG(hw, FCRTH, 0);
348 /* We need to set up the Receive Threshold high and low water marks
349 * as well as (optionally) enabling the transmission of XON frames.
351 if(hw->fc_send_xon) {
352 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
353 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
355 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
356 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
362 /******************************************************************************
363 * Sets up link for a fiber based adapter
365 * hw - Struct containing variables accessed by shared code
366 * ctrl - Current value of the device control register
368 * Manipulates Physical Coding Sublayer functions in order to configure
369 * link. Assumes the hardware has been previously reset and the transmitter
370 * and receiver are not enabled.
371 *****************************************************************************/
373 em_setup_fiber_link(struct em_hw *hw)
382 DEBUGFUNC("em_setup_fiber_link");
384 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
385 * set when the optics detect a signal. On older adapters, it will be
386 * cleared when there is a signal
388 ctrl = E1000_READ_REG(hw, CTRL);
389 if(hw->mac_type > em_82544) signal = E1000_CTRL_SWDPIN1;
392 /* Take the link out of reset */
393 ctrl &= ~(E1000_CTRL_LRST);
395 em_config_collision_dist(hw);
397 /* Check for a software override of the flow control settings, and setup
398 * the device accordingly. If auto-negotiation is enabled, then software
399 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
400 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
401 * auto-negotiation is disabled, then software will have to manually
402 * configure the two flow control enable bits in the CTRL register.
404 * The possible values of the "fc" parameter are:
405 * 0: Flow control is completely disabled
406 * 1: Rx flow control is enabled (we can receive pause frames, but
407 * not send pause frames).
408 * 2: Tx flow control is enabled (we can send pause frames but we do
409 * not support receiving pause frames).
410 * 3: Both Rx and TX flow control (symmetric) are enabled.
414 /* Flow control is completely disabled by a software over-ride. */
415 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
418 /* RX Flow control is enabled and TX Flow control is disabled by a
419 * software over-ride. Since there really isn't a way to advertise
420 * that we are capable of RX Pause ONLY, we will advertise that we
421 * support both symmetric and asymmetric RX PAUSE. Later, we will
422 * disable the adapter's ability to send PAUSE frames.
424 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
427 /* TX Flow control is enabled, and RX Flow control is disabled, by a
428 * software over-ride.
430 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
433 /* Flow control (both RX and TX) is enabled by a software over-ride. */
434 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
437 DEBUGOUT("Flow control param set incorrectly\n");
438 return -E1000_ERR_CONFIG;
442 /* Since auto-negotiation is enabled, take the link out of reset (the link
443 * will be in reset, because we previously reset the chip). This will
444 * restart auto-negotiation. If auto-neogtiation is successful then the
445 * link-up status bit will be set and the flow control enable bits (RFCE
446 * and TFCE) will be set according to their negotiated value.
448 DEBUGOUT("Auto-negotiation enabled\n");
450 E1000_WRITE_REG(hw, TXCW, txcw);
451 E1000_WRITE_REG(hw, CTRL, ctrl);
456 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
457 * indication in the Device Status Register. Time-out if a link isn't
458 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
459 * less than 500 milliseconds even if the other end is doing it in SW).
461 if((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
462 DEBUGOUT("Looking for Link\n");
463 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
465 status = E1000_READ_REG(hw, STATUS);
466 if(status & E1000_STATUS_LU) break;
468 if(i == (LINK_UP_TIMEOUT / 10)) {
469 /* AutoNeg failed to achieve a link, so we'll call
470 * em_check_for_link. This routine will force the link up if we
471 * detect a signal. This will allow us to communicate with
472 * non-autonegotiating link partners.
474 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
475 hw->autoneg_failed = 1;
476 ret_val = em_check_for_link(hw);
478 DEBUGOUT("Error while checking for link\n");
481 hw->autoneg_failed = 0;
483 hw->autoneg_failed = 0;
484 DEBUGOUT("Valid Link Found\n");
487 DEBUGOUT("No Signal Detected\n");
492 /******************************************************************************
493 * Detects which PHY is present and the speed and duplex
495 * hw - Struct containing variables accessed by shared code
496 * ctrl - current value of the device control register
497 ******************************************************************************/
499 em_setup_copper_link(struct em_hw *hw)
506 DEBUGFUNC("em_setup_copper_link");
508 ctrl = E1000_READ_REG(hw, CTRL);
509 /* With 82543, we need to force speed and duplex on the MAC equal to what
510 * the PHY speed and duplex configuration is. In addition, we need to
511 * perform a hardware reset on the PHY to take it out of reset.
513 if(hw->mac_type > em_82543) {
514 ctrl |= E1000_CTRL_SLU;
515 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
516 E1000_WRITE_REG(hw, CTRL, ctrl);
518 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
519 E1000_WRITE_REG(hw, CTRL, ctrl);
523 /* Make sure we have a valid PHY */
524 ret_val = em_detect_gig_phy(hw);
526 DEBUGOUT("Error, did not detect valid phy.\n");
529 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
531 /* Enable CRS on TX. This must be set for half-duplex operation. */
532 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
533 DEBUGOUT("PHY Read Error\n");
534 return -E1000_ERR_PHY;
536 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
539 * MDI/MDI-X = 0 (default)
540 * 0 - Auto for all speeds
543 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
545 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
549 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
552 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
555 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
559 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
564 * disable_polarity_correction = 0 (default)
565 * Automatic Correction for Reversed Cable Polarity
569 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
570 if(hw->disable_polarity_correction == 1)
571 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
572 if(em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
573 DEBUGOUT("PHY Write Error\n");
574 return -E1000_ERR_PHY;
577 /* Force TX_CLK in the Extended PHY Specific Control Register
580 if(em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) {
581 DEBUGOUT("PHY Read Error\n");
582 return -E1000_ERR_PHY;
584 phy_data |= M88E1000_EPSCR_TX_CLK_25;
585 /* Configure Master and Slave downshift values */
586 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
587 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
588 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
589 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
590 if(em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) {
591 DEBUGOUT("PHY Write Error\n");
592 return -E1000_ERR_PHY;
595 /* SW Reset the PHY so all changes take effect */
596 ret_val = em_phy_reset(hw);
598 DEBUGOUT("Error Resetting the PHY\n");
603 * autoneg = 1 (default)
604 * PHY will advertise value(s) parsed from
605 * autoneg_advertised and fc
607 * PHY will be set to 10H, 10F, 100H, or 100F
608 * depending on value parsed from forced_speed_duplex.
611 /* Is autoneg enabled? This is enabled by default or by software override.
612 * If so, call em_phy_setup_autoneg routine to parse the
613 * autoneg_advertised and fc options. If autoneg is NOT enabled, then the
614 * user should have provided a speed/duplex override. If so, then call
615 * em_phy_force_speed_duplex to parse and set this up.
618 /* Perform some bounds checking on the hw->autoneg_advertised
619 * parameter. If this variable is zero, then set it to the default.
621 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
623 /* If autoneg_advertised is zero, we assume it was not defaulted
624 * by the calling code so we set to advertise full capability.
626 if(hw->autoneg_advertised == 0)
627 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
629 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
630 ret_val = em_phy_setup_autoneg(hw);
632 DEBUGOUT("Error Setting up Auto-Negotiation\n");
635 DEBUGOUT("Restarting Auto-Neg\n");
637 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
638 * the Auto Neg Restart bit in the PHY control register.
640 if(em_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
641 DEBUGOUT("PHY Read Error\n");
642 return -E1000_ERR_PHY;
644 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
645 if(em_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
646 DEBUGOUT("PHY Write Error\n");
647 return -E1000_ERR_PHY;
650 /* Does the user want to wait for Auto-Neg to complete here, or
651 * check at a later time (for example, callback routine).
653 if(hw->wait_autoneg_complete) {
654 ret_val = em_wait_autoneg(hw);
656 DEBUGOUT("Error while waiting for autoneg to complete\n");
661 DEBUGOUT("Forcing speed and duplex\n");
662 ret_val = em_phy_force_speed_duplex(hw);
664 DEBUGOUT("Error Forcing Speed and Duplex\n");
669 /* Check link status. Wait up to 100 microseconds for link to become
672 for(i = 0; i < 10; i++) {
673 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
674 DEBUGOUT("PHY Read Error\n");
675 return -E1000_ERR_PHY;
677 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
678 DEBUGOUT("PHY Read Error\n");
679 return -E1000_ERR_PHY;
681 if(phy_data & MII_SR_LINK_STATUS) {
682 /* We have link, so we need to finish the config process:
683 * 1) Set up the MAC to the current PHY speed/duplex
684 * if we are on 82543. If we
685 * are on newer silicon, we only need to configure
686 * collision distance in the Transmit Control Register.
687 * 2) Set up flow control on the MAC to that established with
690 if(hw->mac_type >= em_82544) {
691 em_config_collision_dist(hw);
693 ret_val = em_config_mac_to_phy(hw);
695 DEBUGOUT("Error configuring MAC to PHY settings\n");
699 ret_val = em_config_fc_after_link_up(hw);
701 DEBUGOUT("Error Configuring Flow Control\n");
704 DEBUGOUT("Valid link established!!!\n");
710 DEBUGOUT("Unable to establish link!!!\n");
714 /******************************************************************************
715 * Configures PHY autoneg and flow control advertisement settings
717 * hw - Struct containing variables accessed by shared code
718 ******************************************************************************/
720 em_phy_setup_autoneg(struct em_hw *hw)
722 uint16_t mii_autoneg_adv_reg;
723 uint16_t mii_1000t_ctrl_reg;
725 DEBUGFUNC("em_phy_setup_autoneg");
727 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
728 if(em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg) < 0) {
729 DEBUGOUT("PHY Read Error\n");
730 return -E1000_ERR_PHY;
733 /* Read the MII 1000Base-T Control Register (Address 9). */
734 if(em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg) < 0) {
735 DEBUGOUT("PHY Read Error\n");
736 return -E1000_ERR_PHY;
739 /* Need to parse both autoneg_advertised and fc and set up
740 * the appropriate PHY registers. First we will parse for
741 * autoneg_advertised software override. Since we can advertise
742 * a plethora of combinations, we need to check each bit
746 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
747 * Advertisement Register (Address 4) and the 1000 mb speed bits in
748 * the 1000Base-T Control Register (Address 9).
750 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
751 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
753 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
755 /* Do we want to advertise 10 Mb Half Duplex? */
756 if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
757 DEBUGOUT("Advertise 10mb Half duplex\n");
758 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
761 /* Do we want to advertise 10 Mb Full Duplex? */
762 if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
763 DEBUGOUT("Advertise 10mb Full duplex\n");
764 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
767 /* Do we want to advertise 100 Mb Half Duplex? */
768 if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
769 DEBUGOUT("Advertise 100mb Half duplex\n");
770 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
773 /* Do we want to advertise 100 Mb Full Duplex? */
774 if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
775 DEBUGOUT("Advertise 100mb Full duplex\n");
776 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
779 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
780 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
781 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
784 /* Do we want to advertise 1000 Mb Full Duplex? */
785 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
786 DEBUGOUT("Advertise 1000mb Full duplex\n");
787 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
790 /* Check for a software override of the flow control settings, and
791 * setup the PHY advertisement registers accordingly. If
792 * auto-negotiation is enabled, then software will have to set the
793 * "PAUSE" bits to the correct value in the Auto-Negotiation
794 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
796 * The possible values of the "fc" parameter are:
797 * 0: Flow control is completely disabled
798 * 1: Rx flow control is enabled (we can receive pause frames
799 * but not send pause frames).
800 * 2: Tx flow control is enabled (we can send pause frames
801 * but we do not support receiving pause frames).
802 * 3: Both Rx and TX flow control (symmetric) are enabled.
803 * other: No software override. The flow control configuration
804 * in the EEPROM is used.
807 case em_fc_none: /* 0 */
808 /* Flow control (RX & TX) is completely disabled by a
809 * software over-ride.
811 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
813 case em_fc_rx_pause: /* 1 */
814 /* RX Flow control is enabled, and TX Flow control is
815 * disabled, by a software over-ride.
817 /* Since there really isn't a way to advertise that we are
818 * capable of RX Pause ONLY, we will advertise that we
819 * support both symmetric and asymmetric RX PAUSE. Later
820 * (in em_config_fc_after_link_up) we will disable the
821 *hw's ability to send PAUSE frames.
823 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
825 case em_fc_tx_pause: /* 2 */
826 /* TX Flow control is enabled, and RX Flow control is
827 * disabled, by a software over-ride.
829 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
830 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
832 case em_fc_full: /* 3 */
833 /* Flow control (both RX and TX) is enabled by a software
836 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
839 DEBUGOUT("Flow control param set incorrectly\n");
840 return -E1000_ERR_CONFIG;
843 if(em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg) < 0) {
844 DEBUGOUT("PHY Write Error\n");
845 return -E1000_ERR_PHY;
848 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
850 if(em_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg) < 0) {
851 DEBUGOUT("PHY Write Error\n");
852 return -E1000_ERR_PHY;
857 /******************************************************************************
858 * Force PHY speed and duplex settings to hw->forced_speed_duplex
860 * hw - Struct containing variables accessed by shared code
861 ******************************************************************************/
863 em_phy_force_speed_duplex(struct em_hw *hw)
867 uint16_t mii_ctrl_reg;
868 uint16_t mii_status_reg;
872 DEBUGFUNC("em_phy_force_speed_duplex");
874 /* Turn off Flow control if we are forcing speed and duplex. */
877 DEBUGOUT1("hw->fc = %d\n", hw->fc);
879 /* Read the Device Control Register. */
880 ctrl = E1000_READ_REG(hw, CTRL);
882 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
883 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
884 ctrl &= ~(DEVICE_SPEED_MASK);
886 /* Clear the Auto Speed Detect Enable bit. */
887 ctrl &= ~E1000_CTRL_ASDE;
889 /* Read the MII Control Register. */
890 if(em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg) < 0) {
891 DEBUGOUT("PHY Read Error\n");
892 return -E1000_ERR_PHY;
895 /* We need to disable autoneg in order to force link and duplex. */
897 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
899 /* Are we forcing Full or Half Duplex? */
900 if(hw->forced_speed_duplex == em_100_full ||
901 hw->forced_speed_duplex == em_10_full) {
902 /* We want to force full duplex so we SET the full duplex bits in the
903 * Device and MII Control Registers.
905 ctrl |= E1000_CTRL_FD;
906 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
907 DEBUGOUT("Full Duplex\n");
909 /* We want to force half duplex so we CLEAR the full duplex bits in
910 * the Device and MII Control Registers.
912 ctrl &= ~E1000_CTRL_FD;
913 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
914 DEBUGOUT("Half Duplex\n");
917 /* Are we forcing 100Mbps??? */
918 if(hw->forced_speed_duplex == em_100_full ||
919 hw->forced_speed_duplex == em_100_half) {
920 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
921 ctrl |= E1000_CTRL_SPD_100;
922 mii_ctrl_reg |= MII_CR_SPEED_100;
923 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
924 DEBUGOUT("Forcing 100mb ");
926 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
927 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
928 mii_ctrl_reg |= MII_CR_SPEED_10;
929 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
930 DEBUGOUT("Forcing 10mb ");
933 em_config_collision_dist(hw);
935 /* Write the configured values back to the Device Control Reg. */
936 E1000_WRITE_REG(hw, CTRL, ctrl);
938 /* Write the MII Control Register with the new PHY configuration. */
939 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
940 DEBUGOUT("PHY Read Error\n");
941 return -E1000_ERR_PHY;
944 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
945 * forced whenever speed are duplex are forced.
947 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
948 if(em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
949 DEBUGOUT("PHY Write Error\n");
950 return -E1000_ERR_PHY;
952 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
954 /* Need to reset the PHY or these changes will be ignored */
955 mii_ctrl_reg |= MII_CR_RESET;
956 if(em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg) < 0) {
957 DEBUGOUT("PHY Write Error\n");
958 return -E1000_ERR_PHY;
962 /* The wait_autoneg_complete flag may be a little misleading here.
963 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
964 * But we do want to delay for a period while forcing only so we
965 * don't generate false No Link messages. So we will wait here
966 * only if the user has set wait_autoneg_complete to 1, which is
969 if(hw->wait_autoneg_complete) {
970 /* We will wait for autoneg to complete. */
971 DEBUGOUT("Waiting for forced speed/duplex link.\n");
974 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
975 for(i = PHY_FORCE_TIME; i > 0; i--) {
976 /* Read the MII Status Register and wait for Auto-Neg Complete bit
979 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
980 DEBUGOUT("PHY Read Error\n");
981 return -E1000_ERR_PHY;
983 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
984 DEBUGOUT("PHY Read Error\n");
985 return -E1000_ERR_PHY;
987 if(mii_status_reg & MII_SR_LINK_STATUS) break;
990 if(i == 0) { /* We didn't get link */
991 /* Reset the DSP and wait again for link. */
993 ret_val = em_phy_reset_dsp(hw);
995 DEBUGOUT("Error Resetting PHY DSP\n");
999 /* This loop will early-out if the link condition has been met. */
1000 for(i = PHY_FORCE_TIME; i > 0; i--) {
1001 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1003 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1006 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
1007 DEBUGOUT("PHY Read Error\n");
1008 return -E1000_ERR_PHY;
1010 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
1011 DEBUGOUT("PHY Read Error\n");
1012 return -E1000_ERR_PHY;
1017 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1018 * Extended PHY Specific Control Register to 25MHz clock. This value
1019 * defaults back to a 2.5MHz clock when the PHY is reset.
1021 if(em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) {
1022 DEBUGOUT("PHY Read Error\n");
1023 return -E1000_ERR_PHY;
1025 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1026 if(em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) {
1027 DEBUGOUT("PHY Write Error\n");
1028 return -E1000_ERR_PHY;
1031 /* In addition, because of the s/w reset above, we need to enable CRS on
1032 * TX. This must be set for both full and half duplex operation.
1034 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
1035 DEBUGOUT("PHY Read Error\n");
1036 return -E1000_ERR_PHY;
1038 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1039 if(em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
1040 DEBUGOUT("PHY Write Error\n");
1041 return -E1000_ERR_PHY;
1046 /******************************************************************************
1047 * Sets the collision distance in the Transmit Control register
1049 * hw - Struct containing variables accessed by shared code
1051 * Link should have been established previously. Reads the speed and duplex
1052 * information from the Device Status register.
1053 ******************************************************************************/
1055 em_config_collision_dist(struct em_hw *hw)
1059 tctl = E1000_READ_REG(hw, TCTL);
1061 tctl &= ~E1000_TCTL_COLD;
1062 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1064 E1000_WRITE_REG(hw, TCTL, tctl);
1067 /******************************************************************************
1068 * Sets MAC speed and duplex settings to reflect the those in the PHY
1070 * hw - Struct containing variables accessed by shared code
1071 * mii_reg - data to write to the MII control register
1073 * The contents of the PHY register containing the needed information need to
1075 ******************************************************************************/
1077 em_config_mac_to_phy(struct em_hw *hw)
1082 DEBUGFUNC("em_config_mac_to_phy");
1084 /* Read the Device Control Register and set the bits to Force Speed
1087 ctrl = E1000_READ_REG(hw, CTRL);
1088 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1089 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1091 /* Set up duplex in the Device Control and Transmit Control
1092 * registers depending on negotiated values.
1094 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
1095 DEBUGOUT("PHY Read Error\n");
1096 return -E1000_ERR_PHY;
1098 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
1099 else ctrl &= ~E1000_CTRL_FD;
1101 em_config_collision_dist(hw);
1103 /* Set up speed in the Device Control register depending on
1104 * negotiated values.
1106 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1107 ctrl |= E1000_CTRL_SPD_1000;
1108 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1109 ctrl |= E1000_CTRL_SPD_100;
1110 /* Write the configured values back to the Device Control Reg. */
1111 E1000_WRITE_REG(hw, CTRL, ctrl);
1115 /******************************************************************************
1116 * Forces the MAC's flow control settings.
1118 * hw - Struct containing variables accessed by shared code
1120 * Sets the TFCE and RFCE bits in the device control register to reflect
1121 * the adapter settings. TFCE and RFCE need to be explicitly set by
1122 * software when a Copper PHY is used because autonegotiation is managed
1123 * by the PHY rather than the MAC. Software must also configure these
1124 * bits when link is forced on a fiber connection.
1125 *****************************************************************************/
1127 em_force_mac_fc(struct em_hw *hw)
1131 DEBUGFUNC("em_force_mac_fc");
1133 /* Get the current configuration of the Device Control Register */
1134 ctrl = E1000_READ_REG(hw, CTRL);
1136 /* Because we didn't get link via the internal auto-negotiation
1137 * mechanism (we either forced link or we got link via PHY
1138 * auto-neg), we have to manually enable/disable transmit an
1139 * receive flow control.
1141 * The "Case" statement below enables/disable flow control
1142 * according to the "hw->fc" parameter.
1144 * The possible values of the "fc" parameter are:
1145 * 0: Flow control is completely disabled
1146 * 1: Rx flow control is enabled (we can receive pause
1147 * frames but not send pause frames).
1148 * 2: Tx flow control is enabled (we can send pause frames
1149 * frames but we do not receive pause frames).
1150 * 3: Both Rx and TX flow control (symmetric) is enabled.
1151 * other: No other values should be possible at this point.
1156 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1158 case em_fc_rx_pause:
1159 ctrl &= (~E1000_CTRL_TFCE);
1160 ctrl |= E1000_CTRL_RFCE;
1162 case em_fc_tx_pause:
1163 ctrl &= (~E1000_CTRL_RFCE);
1164 ctrl |= E1000_CTRL_TFCE;
1167 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1170 DEBUGOUT("Flow control param set incorrectly\n");
1171 return -E1000_ERR_CONFIG;
1174 /* Disable TX Flow Control for 82542 (rev 2.0) */
1175 if(hw->mac_type == em_82542_rev2_0)
1176 ctrl &= (~E1000_CTRL_TFCE);
1178 E1000_WRITE_REG(hw, CTRL, ctrl);
1182 /******************************************************************************
1183 * Configures flow control settings after link is established
1185 * hw - Struct containing variables accessed by shared code
1187 * Should be called immediately after a valid link has been established.
1188 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
1189 * and autonegotiation is enabled, the MAC flow control settings will be set
1190 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
1191 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
1192 *****************************************************************************/
1194 em_config_fc_after_link_up(struct em_hw *hw)
1197 uint16_t mii_status_reg;
1198 uint16_t mii_nway_adv_reg;
1199 uint16_t mii_nway_lp_ability_reg;
1203 DEBUGFUNC("em_config_fc_after_link_up");
1205 /* Check for the case where we have fiber media and auto-neg failed
1206 * so we had to force link. In this case, we need to force the
1207 * configuration of the MAC to match the "fc" parameter.
1209 if(((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) ||
1210 ((hw->media_type == em_media_type_copper) && (!hw->autoneg))) {
1211 ret_val = em_force_mac_fc(hw);
1213 DEBUGOUT("Error forcing flow control settings\n");
1218 /* Check for the case where we have copper media and auto-neg is
1219 * enabled. In this case, we need to check and see if Auto-Neg
1220 * has completed, and if so, how the PHY and link partner has
1221 * flow control configured.
1223 if((hw->media_type == em_media_type_copper) && hw->autoneg) {
1224 /* Read the MII Status Register and check to see if AutoNeg
1225 * has completed. We read this twice because this reg has
1226 * some "sticky" (latched) bits.
1228 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
1229 DEBUGOUT("PHY Read Error \n");
1230 return -E1000_ERR_PHY;
1232 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
1233 DEBUGOUT("PHY Read Error \n");
1234 return -E1000_ERR_PHY;
1237 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1238 /* The AutoNeg process has completed, so we now need to
1239 * read both the Auto Negotiation Advertisement Register
1240 * (Address 4) and the Auto_Negotiation Base Page Ability
1241 * Register (Address 5) to determine how flow control was
1244 if(em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
1245 DEBUGOUT("PHY Read Error\n");
1246 return -E1000_ERR_PHY;
1248 if(em_read_phy_reg(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg) < 0) {
1249 DEBUGOUT("PHY Read Error\n");
1250 return -E1000_ERR_PHY;
1253 /* Two bits in the Auto Negotiation Advertisement Register
1254 * (Address 4) and two bits in the Auto Negotiation Base
1255 * Page Ability Register (Address 5) determine flow control
1256 * for both the PHY and the link partner. The following
1257 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1258 * 1999, describes these PAUSE resolution bits and how flow
1259 * control is determined based upon these settings.
1260 * NOTE: DC = Don't Care
1262 * LOCAL DEVICE | LINK PARTNER
1263 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1264 *-------|---------|-------|---------|--------------------
1265 * 0 | 0 | DC | DC | em_fc_none
1266 * 0 | 1 | 0 | DC | em_fc_none
1267 * 0 | 1 | 1 | 0 | em_fc_none
1268 * 0 | 1 | 1 | 1 | em_fc_tx_pause
1269 * 1 | 0 | 0 | DC | em_fc_none
1270 * 1 | DC | 1 | DC | em_fc_full
1271 * 1 | 1 | 0 | 0 | em_fc_none
1272 * 1 | 1 | 0 | 1 | em_fc_rx_pause
1275 /* Are both PAUSE bits set to 1? If so, this implies
1276 * Symmetric Flow Control is enabled at both ends. The
1277 * ASM_DIR bits are irrelevant per the spec.
1279 * For Symmetric Flow Control:
1281 * LOCAL DEVICE | LINK PARTNER
1282 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1283 *-------|---------|-------|---------|--------------------
1284 * 1 | DC | 1 | DC | em_fc_full
1287 if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1288 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1289 /* Now we need to check if the user selected RX ONLY
1290 * of pause frames. In this case, we had to advertise
1291 * FULL flow control because we could not advertise RX
1292 * ONLY. Hence, we must now check to see if we need to
1293 * turn OFF the TRANSMISSION of PAUSE frames.
1295 if(hw->original_fc == em_fc_full) {
1296 hw->fc = em_fc_full;
1297 DEBUGOUT("Flow Control = FULL.\r\n");
1299 hw->fc = em_fc_rx_pause;
1300 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1303 /* For receiving PAUSE frames ONLY.
1305 * LOCAL DEVICE | LINK PARTNER
1306 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1307 *-------|---------|-------|---------|--------------------
1308 * 0 | 1 | 1 | 1 | em_fc_tx_pause
1311 else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1312 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1313 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1314 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1315 hw->fc = em_fc_tx_pause;
1316 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
1318 /* For transmitting PAUSE frames ONLY.
1320 * LOCAL DEVICE | LINK PARTNER
1321 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1322 *-------|---------|-------|---------|--------------------
1323 * 1 | 1 | 0 | 1 | em_fc_rx_pause
1326 else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1327 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1328 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1329 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1330 hw->fc = em_fc_rx_pause;
1331 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1333 /* Per the IEEE spec, at this point flow control should be
1334 * disabled. However, we want to consider that we could
1335 * be connected to a legacy switch that doesn't advertise
1336 * desired flow control, but can be forced on the link
1337 * partner. So if we advertised no flow control, that is
1338 * what we will resolve to. If we advertised some kind of
1339 * receive capability (Rx Pause Only or Full Flow Control)
1340 * and the link partner advertised none, we will configure
1341 * ourselves to enable Rx Flow Control only. We can do
1342 * this safely for two reasons: If the link partner really
1343 * didn't want flow control enabled, and we enable Rx, no
1344 * harm done since we won't be receiving any PAUSE frames
1345 * anyway. If the intent on the link partner was to have
1346 * flow control enabled, then by us enabling RX only, we
1347 * can at least receive pause frames and process them.
1348 * This is a good idea because in most cases, since we are
1349 * predominantly a server NIC, more times than not we will
1350 * be asked to delay transmission of packets than asking
1351 * our link partner to pause transmission of frames.
1353 else if(hw->original_fc == em_fc_none ||
1354 hw->original_fc == em_fc_tx_pause) {
1355 hw->fc = em_fc_none;
1356 DEBUGOUT("Flow Control = NONE.\r\n");
1358 hw->fc = em_fc_rx_pause;
1359 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1362 /* Now we need to do one last check... If we auto-
1363 * negotiated to HALF DUPLEX, flow control should not be
1364 * enabled per IEEE 802.3 spec.
1366 em_get_speed_and_duplex(hw, &speed, &duplex);
1368 if(duplex == HALF_DUPLEX)
1369 hw->fc = em_fc_none;
1371 /* Now we call a subroutine to actually force the MAC
1372 * controller to use the correct flow control settings.
1374 ret_val = em_force_mac_fc(hw);
1376 DEBUGOUT("Error forcing flow control settings\n");
1380 DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
1386 /******************************************************************************
1387 * Checks to see if the link status of the hardware has changed.
1389 * hw - Struct containing variables accessed by shared code
1391 * Called by any function that needs to check the link status of the adapter.
1392 *****************************************************************************/
1394 em_check_for_link(struct em_hw *hw)
1403 uint16_t lp_capability;
1405 DEBUGFUNC("em_check_for_link");
1407 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
1408 * set when the optics detect a signal. On older adapters, it will be
1409 * cleared when there is a signal
1411 if(hw->mac_type > em_82544) signal = E1000_CTRL_SWDPIN1;
1414 ctrl = E1000_READ_REG(hw, CTRL);
1415 status = E1000_READ_REG(hw, STATUS);
1416 rxcw = E1000_READ_REG(hw, RXCW);
1418 /* If we have a copper PHY then we only want to go out to the PHY
1419 * registers to see if Auto-Neg has completed and/or if our link
1420 * status has changed. The get_link_status flag will be set if we
1421 * receive a Link Status Change interrupt or we have Rx Sequence
1424 if((hw->media_type == em_media_type_copper) && hw->get_link_status) {
1425 /* First we want to see if the MII Status Register reports
1426 * link. If so, then we want to get the current speed/duplex
1428 * Read the register twice since the link bit is sticky.
1430 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
1431 DEBUGOUT("PHY Read Error\n");
1432 return -E1000_ERR_PHY;
1434 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
1435 DEBUGOUT("PHY Read Error\n");
1436 return -E1000_ERR_PHY;
1439 if(phy_data & MII_SR_LINK_STATUS) {
1440 hw->get_link_status = FALSE;
1442 /* No link detected */
1446 /* If we are forcing speed/duplex, then we simply return since
1447 * we have already determined whether we have link or not.
1449 if(!hw->autoneg) return -E1000_ERR_CONFIG;
1451 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
1452 * have Si on board that is 82544 or newer, Auto
1453 * Speed Detection takes care of MAC speed/duplex
1454 * configuration. So we only need to configure Collision
1455 * Distance in the MAC. Otherwise, we need to force
1456 * speed/duplex on the MAC to the current PHY speed/duplex
1459 if(hw->mac_type >= em_82544)
1460 em_config_collision_dist(hw);
1462 ret_val = em_config_mac_to_phy(hw);
1464 DEBUGOUT("Error configuring MAC to PHY settings\n");
1469 /* Configure Flow Control now that Auto-Neg has completed. First, we
1470 * need to restore the desired flow control settings because we may
1471 * have had to re-autoneg with a different link partner.
1473 ret_val = em_config_fc_after_link_up(hw);
1475 DEBUGOUT("Error configuring flow control\n");
1479 /* At this point we know that we are on copper and we have
1480 * auto-negotiated link. These are conditions for checking the link
1481 * parter capability register. We use the link partner capability to
1482 * determine if TBI Compatibility needs to be turned on or off. If
1483 * the link partner advertises any speed in addition to Gigabit, then
1484 * we assume that they are GMII-based, and TBI compatibility is not
1485 * needed. If no other speeds are advertised, we assume the link
1486 * partner is TBI-based, and we turn on TBI Compatibility.
1488 if(hw->tbi_compatibility_en) {
1489 if(em_read_phy_reg(hw, PHY_LP_ABILITY, &lp_capability) < 0) {
1490 DEBUGOUT("PHY Read Error\n");
1491 return -E1000_ERR_PHY;
1493 if(lp_capability & (NWAY_LPAR_10T_HD_CAPS |
1494 NWAY_LPAR_10T_FD_CAPS |
1495 NWAY_LPAR_100TX_HD_CAPS |
1496 NWAY_LPAR_100TX_FD_CAPS |
1497 NWAY_LPAR_100T4_CAPS)) {
1498 /* If our link partner advertises anything in addition to
1499 * gigabit, we do not need to enable TBI compatibility.
1501 if(hw->tbi_compatibility_on) {
1502 /* If we previously were in the mode, turn it off. */
1503 rctl = E1000_READ_REG(hw, RCTL);
1504 rctl &= ~E1000_RCTL_SBP;
1505 E1000_WRITE_REG(hw, RCTL, rctl);
1506 hw->tbi_compatibility_on = FALSE;
1509 /* If TBI compatibility is was previously off, turn it on. For
1510 * compatibility with a TBI link partner, we will store bad
1511 * packets. Some frames have an additional byte on the end and
1512 * will look like CRC errors to to the hardware.
1514 if(!hw->tbi_compatibility_on) {
1515 hw->tbi_compatibility_on = TRUE;
1516 rctl = E1000_READ_REG(hw, RCTL);
1517 rctl |= E1000_RCTL_SBP;
1518 E1000_WRITE_REG(hw, RCTL, rctl);
1523 /* If we don't have link (auto-negotiation failed or link partner cannot
1524 * auto-negotiate), the cable is plugged in (we have signal), and our
1525 * link partner is not trying to auto-negotiate with us (we are receiving
1526 * idles or data), we need to force link up. We also need to give
1527 * auto-negotiation time to complete, in case the cable was just plugged
1528 * in. The autoneg_failed flag does this.
1530 else if((hw->media_type == em_media_type_fiber) &&
1531 (!(status & E1000_STATUS_LU)) &&
1532 ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
1533 (!(rxcw & E1000_RXCW_C))) {
1534 if(hw->autoneg_failed == 0) {
1535 hw->autoneg_failed = 1;
1538 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
1540 /* Disable auto-negotiation in the TXCW register */
1541 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
1543 /* Force link-up and also force full-duplex. */
1544 ctrl = E1000_READ_REG(hw, CTRL);
1545 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1546 E1000_WRITE_REG(hw, CTRL, ctrl);
1548 /* Configure Flow Control after forcing link up. */
1549 ret_val = em_config_fc_after_link_up(hw);
1551 DEBUGOUT("Error configuring flow control\n");
1555 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
1556 * auto-negotiation in the TXCW register and disable forced link in the
1557 * Device Control register in an attempt to auto-negotiate with our link
1560 else if((hw->media_type == em_media_type_fiber) &&
1561 (ctrl & E1000_CTRL_SLU) &&
1562 (rxcw & E1000_RXCW_C)) {
1563 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
1564 E1000_WRITE_REG(hw, TXCW, hw->txcw);
1565 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
1570 /******************************************************************************
1571 * Detects the current speed and duplex settings of the hardware.
1573 * hw - Struct containing variables accessed by shared code
1574 * speed - Speed of the connection
1575 * duplex - Duplex setting of the connection
1576 *****************************************************************************/
1578 em_get_speed_and_duplex(struct em_hw *hw,
1584 DEBUGFUNC("em_get_speed_and_duplex");
1586 if(hw->mac_type >= em_82543) {
1587 status = E1000_READ_REG(hw, STATUS);
1588 if(status & E1000_STATUS_SPEED_1000) {
1589 *speed = SPEED_1000;
1590 DEBUGOUT("1000 Mbs, ");
1591 } else if(status & E1000_STATUS_SPEED_100) {
1593 DEBUGOUT("100 Mbs, ");
1596 DEBUGOUT("10 Mbs, ");
1599 if(status & E1000_STATUS_FD) {
1600 *duplex = FULL_DUPLEX;
1601 DEBUGOUT("Full Duplex\r\n");
1603 *duplex = HALF_DUPLEX;
1604 DEBUGOUT(" Half Duplex\r\n");
1607 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
1608 *speed = SPEED_1000;
1609 *duplex = FULL_DUPLEX;
1613 /******************************************************************************
1614 * Blocks until autoneg completes or times out (~4.5 seconds)
1616 * hw - Struct containing variables accessed by shared code
1617 ******************************************************************************/
1619 em_wait_autoneg(struct em_hw *hw)
1624 DEBUGFUNC("em_wait_autoneg");
1625 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
1627 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1628 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
1629 /* Read the MII Status Register and wait for Auto-Neg
1630 * Complete bit to be set.
1632 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
1633 DEBUGOUT("PHY Read Error\n");
1634 return -E1000_ERR_PHY;
1636 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
1637 DEBUGOUT("PHY Read Error\n");
1638 return -E1000_ERR_PHY;
1640 if(phy_data & MII_SR_AUTONEG_COMPLETE) {
1648 /******************************************************************************
1649 * Raises the Management Data Clock
1651 * hw - Struct containing variables accessed by shared code
1652 * ctrl - Device control register's current value
1653 ******************************************************************************/
1655 em_raise_mdi_clk(struct em_hw *hw,
1658 /* Raise the clock input to the Management Data Clock (by setting the MDC
1659 * bit), and then delay 2 microseconds.
1661 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
1665 /******************************************************************************
1666 * Lowers the Management Data Clock
1668 * hw - Struct containing variables accessed by shared code
1669 * ctrl - Device control register's current value
1670 ******************************************************************************/
1672 em_lower_mdi_clk(struct em_hw *hw,
1675 /* Lower the clock input to the Management Data Clock (by clearing the MDC
1676 * bit), and then delay 2 microseconds.
1678 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
1682 /******************************************************************************
1683 * Shifts data bits out to the PHY
1685 * hw - Struct containing variables accessed by shared code
1686 * data - Data to send out to the PHY
1687 * count - Number of bits to shift out
1689 * Bits are shifted out in MSB to LSB order.
1690 ******************************************************************************/
1692 em_shift_out_mdi_bits(struct em_hw *hw,
1699 /* We need to shift "count" number of bits out to the PHY. So, the value
1700 * in the "data" parameter will be shifted out to the PHY one bit at a
1701 * time. In order to do this, "data" must be broken down into bits.
1704 mask <<= (count - 1);
1706 ctrl = E1000_READ_REG(hw, CTRL);
1708 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
1709 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
1712 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
1713 * then raising and lowering the Management Data Clock. A "0" is
1714 * shifted out to the PHY by setting the MDIO bit to "0" and then
1715 * raising and lowering the clock.
1717 if(data & mask) ctrl |= E1000_CTRL_MDIO;
1718 else ctrl &= ~E1000_CTRL_MDIO;
1720 E1000_WRITE_REG(hw, CTRL, ctrl);
1724 em_raise_mdi_clk(hw, &ctrl);
1725 em_lower_mdi_clk(hw, &ctrl);
1730 /* Clear the data bit just before leaving this routine. */
1731 ctrl &= ~E1000_CTRL_MDIO;
1734 /******************************************************************************
1735 * Shifts data bits in from the PHY
1737 * hw - Struct containing variables accessed by shared code
1739 * Bits are shifted in in MSB to LSB order.
1740 ******************************************************************************/
1742 em_shift_in_mdi_bits(struct em_hw *hw)
1748 /* In order to read a register from the PHY, we need to shift in a total
1749 * of 18 bits from the PHY. The first two bit (turnaround) times are used
1750 * to avoid contention on the MDIO pin when a read operation is performed.
1751 * These two bits are ignored by us and thrown away. Bits are "shifted in"
1752 * by raising the input to the Management Data Clock (setting the MDC bit),
1753 * and then reading the value of the MDIO bit.
1755 ctrl = E1000_READ_REG(hw, CTRL);
1757 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
1758 ctrl &= ~E1000_CTRL_MDIO_DIR;
1759 ctrl &= ~E1000_CTRL_MDIO;
1761 E1000_WRITE_REG(hw, CTRL, ctrl);
1763 /* Raise and Lower the clock before reading in the data. This accounts for
1764 * the turnaround bits. The first clock occurred when we clocked out the
1765 * last bit of the Register Address.
1767 em_raise_mdi_clk(hw, &ctrl);
1768 em_lower_mdi_clk(hw, &ctrl);
1770 for(data = 0, i = 0; i < 16; i++) {
1772 em_raise_mdi_clk(hw, &ctrl);
1773 ctrl = E1000_READ_REG(hw, CTRL);
1774 /* Check to see if we shifted in a "1". */
1775 if(ctrl & E1000_CTRL_MDIO) data |= 1;
1776 em_lower_mdi_clk(hw, &ctrl);
1779 em_raise_mdi_clk(hw, &ctrl);
1780 em_lower_mdi_clk(hw, &ctrl);
1782 /* Clear the MDIO bit just before leaving this routine. */
1783 ctrl &= ~E1000_CTRL_MDIO;
1788 /*****************************************************************************
1789 * Reads the value from a PHY register
1791 * hw - Struct containing variables accessed by shared code
1792 * reg_addr - address of the PHY register to read
1793 ******************************************************************************/
1795 em_read_phy_reg(struct em_hw *hw,
1801 const uint32_t phy_addr = 1;
1803 DEBUGFUNC("em_read_phy_reg");
1805 if(reg_addr > MAX_PHY_REG_ADDRESS) {
1806 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
1807 return -E1000_ERR_PARAM;
1810 if(hw->mac_type > em_82543) {
1811 /* Set up Op-code, Phy Address, and register address in the MDI
1812 * Control register. The MAC will take care of interfacing with the
1813 * PHY to retrieve the desired data.
1815 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
1816 (phy_addr << E1000_MDIC_PHY_SHIFT) |
1817 (E1000_MDIC_OP_READ));
1819 E1000_WRITE_REG(hw, MDIC, mdic);
1821 /* Poll the ready bit to see if the MDI read completed */
1822 for(i = 0; i < 64; i++) {
1824 mdic = E1000_READ_REG(hw, MDIC);
1825 if(mdic & E1000_MDIC_READY) break;
1827 if(!(mdic & E1000_MDIC_READY)) {
1828 DEBUGOUT("MDI Read did not complete\n");
1829 return -E1000_ERR_PHY;
1831 if(mdic & E1000_MDIC_ERROR) {
1832 DEBUGOUT("MDI Error\n");
1833 return -E1000_ERR_PHY;
1835 *phy_data = (uint16_t) mdic;
1837 /* We must first send a preamble through the MDIO pin to signal the
1838 * beginning of an MII instruction. This is done by sending 32
1839 * consecutive "1" bits.
1841 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
1843 /* Now combine the next few fields that are required for a read
1844 * operation. We use this method instead of calling the
1845 * em_shift_out_mdi_bits routine five different times. The format of
1846 * a MII read instruction consists of a shift out of 14 bits and is
1847 * defined as follows:
1848 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
1849 * followed by a shift in of 18 bits. This first two bits shifted in
1850 * are TurnAround bits used to avoid contention on the MDIO pin when a
1851 * READ operation is performed. These two bits are thrown away
1852 * followed by a shift in of 16 bits which contains the desired data.
1854 mdic = ((reg_addr) | (phy_addr << 5) |
1855 (PHY_OP_READ << 10) | (PHY_SOF << 12));
1857 em_shift_out_mdi_bits(hw, mdic, 14);
1859 /* Now that we've shifted out the read command to the MII, we need to
1860 * "shift in" the 16-bit value (18 total bits) of the requested PHY
1863 *phy_data = em_shift_in_mdi_bits(hw);
1868 /******************************************************************************
1869 * Writes a value to a PHY register
1871 * hw - Struct containing variables accessed by shared code
1872 * reg_addr - address of the PHY register to write
1873 * data - data to write to the PHY
1874 ******************************************************************************/
1876 em_write_phy_reg(struct em_hw *hw,
1882 const uint32_t phy_addr = 1;
1884 DEBUGFUNC("em_write_phy_reg");
1886 if(reg_addr > MAX_PHY_REG_ADDRESS) {
1887 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
1888 return -E1000_ERR_PARAM;
1891 if(hw->mac_type > em_82543) {
1892 /* Set up Op-code, Phy Address, register address, and data intended
1893 * for the PHY register in the MDI Control register. The MAC will take
1894 * care of interfacing with the PHY to send the desired data.
1896 mdic = (((uint32_t) phy_data) |
1897 (reg_addr << E1000_MDIC_REG_SHIFT) |
1898 (phy_addr << E1000_MDIC_PHY_SHIFT) |
1899 (E1000_MDIC_OP_WRITE));
1901 E1000_WRITE_REG(hw, MDIC, mdic);
1903 /* Poll the ready bit to see if the MDI read completed */
1904 for(i = 0; i < 64; i++) {
1906 mdic = E1000_READ_REG(hw, MDIC);
1907 if(mdic & E1000_MDIC_READY) break;
1909 if(!(mdic & E1000_MDIC_READY)) {
1910 DEBUGOUT("MDI Write did not complete\n");
1911 return -E1000_ERR_PHY;
1914 /* We'll need to use the SW defined pins to shift the write command
1915 * out to the PHY. We first send a preamble to the PHY to signal the
1916 * beginning of the MII instruction. This is done by sending 32
1917 * consecutive "1" bits.
1919 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
1921 /* Now combine the remaining required fields that will indicate a
1922 * write operation. We use this method instead of calling the
1923 * em_shift_out_mdi_bits routine for each field in the command. The
1924 * format of a MII write instruction is as follows:
1925 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
1927 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
1928 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
1930 mdic |= (uint32_t) phy_data;
1932 em_shift_out_mdi_bits(hw, mdic, 32);
1937 /******************************************************************************
1938 * Returns the PHY to the power-on reset state
1940 * hw - Struct containing variables accessed by shared code
1941 ******************************************************************************/
1943 em_phy_hw_reset(struct em_hw *hw)
1948 DEBUGFUNC("em_phy_hw_reset");
1950 DEBUGOUT("Resetting Phy...\n");
1952 if(hw->mac_type > em_82543) {
1953 /* Read the device control register and assert the E1000_CTRL_PHY_RST
1954 * bit. Then, take it out of reset.
1956 ctrl = E1000_READ_REG(hw, CTRL);
1957 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
1959 E1000_WRITE_REG(hw, CTRL, ctrl);
1961 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
1962 * bit to put the PHY into reset. Then, take it out of reset.
1964 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1965 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
1966 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
1967 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1969 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
1970 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1975 /******************************************************************************
1978 * hw - Struct containing variables accessed by shared code
1980 * Sets bit 15 of the MII Control regiser
1981 ******************************************************************************/
1983 em_phy_reset(struct em_hw *hw)
1987 DEBUGFUNC("em_phy_reset");
1989 if(em_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
1990 DEBUGOUT("PHY Read Error\n");
1991 return -E1000_ERR_PHY;
1993 phy_data |= MII_CR_RESET;
1994 if(em_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
1995 DEBUGOUT("PHY Write Error\n");
1996 return -E1000_ERR_PHY;
2002 /******************************************************************************
2003 * Probes the expected PHY address for known PHY IDs
2005 * hw - Struct containing variables accessed by shared code
2006 ******************************************************************************/
2008 em_detect_gig_phy(struct em_hw *hw)
2010 uint16_t phy_id_high, phy_id_low;
2011 boolean_t match = FALSE;
2013 DEBUGFUNC("em_detect_gig_phy");
2015 /* Read the PHY ID Registers to identify which PHY is onboard. */
2016 if(em_read_phy_reg(hw, PHY_ID1, &phy_id_high) < 0) {
2017 DEBUGOUT("PHY Read Error\n");
2018 return -E1000_ERR_PHY;
2020 hw->phy_id = (uint32_t) (phy_id_high << 16);
2022 if(em_read_phy_reg(hw, PHY_ID2, &phy_id_low) < 0) {
2023 DEBUGOUT("PHY Read Error\n");
2024 return -E1000_ERR_PHY;
2026 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
2028 switch(hw->mac_type) {
2030 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
2033 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
2038 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
2041 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
2042 return -E1000_ERR_CONFIG;
2045 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
2048 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
2049 return -E1000_ERR_PHY;
2052 /******************************************************************************
2053 * Resets the PHY's DSP
2055 * hw - Struct containing variables accessed by shared code
2056 ******************************************************************************/
2058 em_phy_reset_dsp(struct em_hw *hw)
2060 int32_t ret_val = -E1000_ERR_PHY;
2061 DEBUGFUNC("em_phy_reset_dsp");
2064 if(em_write_phy_reg(hw, 29, 0x001d) < 0) break;
2065 if(em_write_phy_reg(hw, 30, 0x00c1) < 0) break;
2066 if(em_write_phy_reg(hw, 30, 0x0000) < 0) break;
2070 if(ret_val < 0) DEBUGOUT("PHY Write Error\n");
2074 /******************************************************************************
2075 * Get PHY information from various PHY registers
2077 * hw - Struct containing variables accessed by shared code
2078 * phy_info - PHY information structure
2079 ******************************************************************************/
2081 em_phy_get_info(struct em_hw *hw,
2082 struct em_phy_info *phy_info)
2084 int32_t ret_val = -E1000_ERR_PHY;
2087 DEBUGFUNC("em_phy_get_info");
2089 phy_info->cable_length = em_cable_length_undefined;
2090 phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_undefined;
2091 phy_info->cable_polarity = em_rev_polarity_undefined;
2092 phy_info->polarity_correction = em_polarity_reversal_undefined;
2093 phy_info->mdix_mode = em_auto_x_mode_undefined;
2094 phy_info->local_rx = em_1000t_rx_status_undefined;
2095 phy_info->remote_rx = em_1000t_rx_status_undefined;
2097 if(hw->media_type != em_media_type_copper) {
2098 DEBUGOUT("PHY info is only valid for copper media\n");
2099 return -E1000_ERR_CONFIG;
2103 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) break;
2104 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) break;
2105 if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
2106 DEBUGOUT("PHY info is only valid if link is up\n");
2107 return -E1000_ERR_CONFIG;
2110 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0)
2112 phy_info->extended_10bt_distance =
2113 (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
2114 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
2115 phy_info->polarity_correction =
2116 (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
2117 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
2119 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0)
2121 phy_info->cable_polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
2122 M88E1000_PSSR_REV_POLARITY_SHIFT;
2123 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
2124 M88E1000_PSSR_MDIX_SHIFT;
2125 if(phy_data & M88E1000_PSSR_1000MBS) {
2126 /* Cable Length Estimation and Local/Remote Receiver Informatoion
2127 * are only valid at 1000 Mbps
2129 phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2130 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2131 if(em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data) < 0)
2133 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2134 SR_1000T_LOCAL_RX_STATUS_SHIFT;
2135 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2136 SR_1000T_REMOTE_RX_STATUS_SHIFT;
2141 if(ret_val < 0) DEBUGOUT("PHY Read Error\n");
2146 em_validate_mdi_setting(struct em_hw *hw)
2148 DEBUGFUNC("em_validate_mdi_settings");
2150 if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
2151 DEBUGOUT("Invalid MDI setting detected\n");
2153 return -E1000_ERR_CONFIG;
2158 /******************************************************************************
2159 * Raises the EEPROM's clock input.
2161 * hw - Struct containing variables accessed by shared code
2162 * eecd - EECD's current value
2163 *****************************************************************************/
2165 em_raise_ee_clk(struct em_hw *hw,
2168 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
2169 * wait 50 microseconds.
2171 *eecd = *eecd | E1000_EECD_SK;
2172 E1000_WRITE_REG(hw, EECD, *eecd);
2176 /******************************************************************************
2177 * Lowers the EEPROM's clock input.
2179 * hw - Struct containing variables accessed by shared code
2180 * eecd - EECD's current value
2181 *****************************************************************************/
2183 em_lower_ee_clk(struct em_hw *hw,
2186 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
2187 * wait 50 microseconds.
2189 *eecd = *eecd & ~E1000_EECD_SK;
2190 E1000_WRITE_REG(hw, EECD, *eecd);
2194 /******************************************************************************
2195 * Shift data bits out to the EEPROM.
2197 * hw - Struct containing variables accessed by shared code
2198 * data - data to send to the EEPROM
2199 * count - number of bits to shift out
2200 *****************************************************************************/
2202 em_shift_out_ee_bits(struct em_hw *hw,
2209 /* We need to shift "count" bits out to the EEPROM. So, value in the
2210 * "data" parameter will be shifted out to the EEPROM one bit at a time.
2211 * In order to do this, "data" must be broken down into bits.
2213 mask = 0x01 << (count - 1);
2214 eecd = E1000_READ_REG(hw, EECD);
2215 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
2217 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
2218 * and then raising and then lowering the clock (the SK bit controls
2219 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
2220 * by setting "DI" to "0" and then raising and then lowering the clock.
2222 eecd &= ~E1000_EECD_DI;
2225 eecd |= E1000_EECD_DI;
2227 E1000_WRITE_REG(hw, EECD, eecd);
2231 em_raise_ee_clk(hw, &eecd);
2232 em_lower_ee_clk(hw, &eecd);
2238 /* We leave the "DI" bit set to "0" when we leave this routine. */
2239 eecd &= ~E1000_EECD_DI;
2240 E1000_WRITE_REG(hw, EECD, eecd);
2243 /******************************************************************************
2244 * Shift data bits in from the EEPROM
2246 * hw - Struct containing variables accessed by shared code
2247 *****************************************************************************/
2249 em_shift_in_ee_bits(struct em_hw *hw)
2255 /* In order to read a register from the EEPROM, we need to shift 16 bits
2256 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
2257 * the EEPROM (setting the SK bit), and then reading the value of the "DO"
2258 * bit. During this "shifting in" process the "DI" bit should always be
2262 eecd = E1000_READ_REG(hw, EECD);
2264 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
2267 for(i = 0; i < 16; i++) {
2269 em_raise_ee_clk(hw, &eecd);
2271 eecd = E1000_READ_REG(hw, EECD);
2273 eecd &= ~(E1000_EECD_DI);
2274 if(eecd & E1000_EECD_DO)
2277 em_lower_ee_clk(hw, &eecd);
2283 /******************************************************************************
2284 * Prepares EEPROM for access
2286 * hw - Struct containing variables accessed by shared code
2288 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
2289 * function should be called before issuing a command to the EEPROM.
2290 *****************************************************************************/
2292 em_setup_eeprom(struct em_hw *hw)
2296 eecd = E1000_READ_REG(hw, EECD);
2298 /* Clear SK and DI */
2299 eecd &= ~(E1000_EECD_SK | E1000_EECD_DI);
2300 E1000_WRITE_REG(hw, EECD, eecd);
2303 eecd |= E1000_EECD_CS;
2304 E1000_WRITE_REG(hw, EECD, eecd);
2307 /******************************************************************************
2308 * Returns EEPROM to a "standby" state
2310 * hw - Struct containing variables accessed by shared code
2311 *****************************************************************************/
2313 em_standby_eeprom(struct em_hw *hw)
2317 eecd = E1000_READ_REG(hw, EECD);
2319 /* Deselct EEPROM */
2320 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
2321 E1000_WRITE_REG(hw, EECD, eecd);
2325 eecd |= E1000_EECD_SK;
2326 E1000_WRITE_REG(hw, EECD, eecd);
2330 eecd |= E1000_EECD_CS;
2331 E1000_WRITE_REG(hw, EECD, eecd);
2335 eecd &= ~E1000_EECD_SK;
2336 E1000_WRITE_REG(hw, EECD, eecd);
2341 /******************************************************************************
2342 * Reads a 16 bit word from the EEPROM.
2344 * hw - Struct containing variables accessed by shared code
2345 * offset - offset of word in the EEPROM to read
2346 * data - word read from the EEPROM
2347 *****************************************************************************/
2349 em_read_eeprom(struct em_hw *hw,
2355 boolean_t large_eeprom = FALSE;
2357 DEBUGFUNC("em_read_eeprom");
2359 /* Request EEPROM Access */
2360 if(hw->mac_type > em_82544) {
2361 eecd = E1000_READ_REG(hw, EECD);
2362 if(eecd & E1000_EECD_SIZE) large_eeprom = TRUE;
2363 eecd |= E1000_EECD_REQ;
2364 E1000_WRITE_REG(hw, EECD, eecd);
2365 eecd = E1000_READ_REG(hw, EECD);
2366 while((!(eecd & E1000_EECD_GNT)) && (i < 100)) {
2369 eecd = E1000_READ_REG(hw, EECD);
2371 if(!(eecd & E1000_EECD_GNT)) {
2372 eecd &= ~E1000_EECD_REQ;
2373 E1000_WRITE_REG(hw, EECD, eecd);
2374 DEBUGOUT("Could not acquire EEPROM grant\n");
2375 return -E1000_ERR_EEPROM;
2379 /* Prepare the EEPROM for reading */
2380 em_setup_eeprom(hw);
2382 /* Send the READ command (opcode + addr) */
2383 em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE, 3);
2385 /* If we have a 256 word EEPROM, there are 8 address bits */
2386 em_shift_out_ee_bits(hw, offset, 8);
2388 /* If we have a 64 word EEPROM, there are 6 address bits */
2389 em_shift_out_ee_bits(hw, offset, 6);
2393 *data = em_shift_in_ee_bits(hw);
2395 /* End this read operation */
2396 em_standby_eeprom(hw);
2398 /* Stop requesting EEPROM access */
2399 if(hw->mac_type > em_82544) {
2400 eecd = E1000_READ_REG(hw, EECD);
2401 eecd &= ~E1000_EECD_REQ;
2402 E1000_WRITE_REG(hw, EECD, eecd);
2408 /******************************************************************************
2409 * Verifies that the EEPROM has a valid checksum
2411 * hw - Struct containing variables accessed by shared code
2413 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
2414 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
2416 *****************************************************************************/
2418 em_validate_eeprom_checksum(struct em_hw *hw)
2420 uint16_t checksum = 0;
2421 uint16_t i, eeprom_data;
2423 DEBUGFUNC("em_validate_eeprom_checksum");
2425 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
2426 if(em_read_eeprom(hw, i, &eeprom_data) < 0) {
2427 DEBUGOUT("EEPROM Read Error\n");
2428 return -E1000_ERR_EEPROM;
2430 checksum += eeprom_data;
2433 if(checksum == (uint16_t) EEPROM_SUM) {
2436 DEBUGOUT("EEPROM Checksum Invalid\n");
2437 return -E1000_ERR_EEPROM;
2441 /******************************************************************************
2442 * Reads the adapter's part number from the EEPROM
2444 * hw - Struct containing variables accessed by shared code
2445 * part_num - Adapter's part number
2446 *****************************************************************************/
2448 em_read_part_num(struct em_hw *hw,
2451 uint16_t offset = EEPROM_PBA_BYTE_1;
2452 uint16_t eeprom_data;
2454 DEBUGFUNC("em_read_part_num");
2456 /* Get word 0 from EEPROM */
2457 if(em_read_eeprom(hw, offset, &eeprom_data) < 0) {
2458 DEBUGOUT("EEPROM Read Error\n");
2459 return -E1000_ERR_EEPROM;
2461 /* Save word 0 in upper half of part_num */
2462 *part_num = (uint32_t) (eeprom_data << 16);
2464 /* Get word 1 from EEPROM */
2465 if(em_read_eeprom(hw, ++offset, &eeprom_data) < 0) {
2466 DEBUGOUT("EEPROM Read Error\n");
2467 return -E1000_ERR_EEPROM;
2469 /* Save word 1 in lower half of part_num */
2470 *part_num |= eeprom_data;
2475 /******************************************************************************
2476 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
2477 * second function of dual function devices
2479 * hw - Struct containing variables accessed by shared code
2480 *****************************************************************************/
2482 em_read_mac_addr(struct em_hw * hw)
2485 uint16_t eeprom_data, i;
2487 DEBUGFUNC("em_read_mac_addr");
2489 for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
2491 if(em_read_eeprom(hw, offset, &eeprom_data) < 0) {
2492 DEBUGOUT("EEPROM Read Error\n");
2493 return -E1000_ERR_EEPROM;
2495 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
2496 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
2498 if((hw->mac_type == em_82546) &&
2499 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
2500 if(hw->perm_mac_addr[5] & 0x01)
2501 hw->perm_mac_addr[5] &= ~(0x01);
2503 hw->perm_mac_addr[5] |= 0x01;
2505 for(i = 0; i < NODE_ADDRESS_SIZE; i++)
2506 hw->mac_addr[i] = hw->perm_mac_addr[i];
2510 /******************************************************************************
2511 * Initializes receive address filters.
2513 * hw - Struct containing variables accessed by shared code
2515 * Places the MAC address in receive address register 0 and clears the rest
2516 * of the receive addresss registers. Clears the multicast table. Assumes
2517 * the receiver is in reset when the routine is called.
2518 *****************************************************************************/
2520 em_init_rx_addrs(struct em_hw *hw)
2526 DEBUGFUNC("em_init_rx_addrs");
2528 /* Setup the receive address. */
2529 DEBUGOUT("Programming MAC Address into RAR[0]\n");
2530 addr_low = (hw->mac_addr[0] |
2531 (hw->mac_addr[1] << 8) |
2532 (hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24));
2534 addr_high = (hw->mac_addr[4] |
2535 (hw->mac_addr[5] << 8) | E1000_RAH_AV);
2537 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
2538 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
2540 /* Zero out the other 15 receive addresses. */
2541 DEBUGOUT("Clearing RAR[1-15]\n");
2542 for(i = 1; i < E1000_RAR_ENTRIES; i++) {
2543 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
2544 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
2548 /******************************************************************************
2549 * Updates the MAC's list of multicast addresses.
2551 * hw - Struct containing variables accessed by shared code
2552 * mc_addr_list - the list of new multicast addresses
2553 * mc_addr_count - number of addresses
2554 * pad - number of bytes between addresses in the list
2556 * The given list replaces any existing list. Clears the last 15 receive
2557 * address registers and the multicast table. Uses receive address registers
2558 * for the first 15 multicast addresses, and hashes the rest into the
2560 *****************************************************************************/
2562 em_mc_addr_list_update(struct em_hw *hw,
2563 uint8_t *mc_addr_list,
2564 uint32_t mc_addr_count,
2567 uint32_t hash_value;
2569 uint32_t rar_used_count = 1; /* RAR[0] is used for our MAC address */
2571 DEBUGFUNC("em_mc_addr_list_update");
2573 /* Set the new number of MC addresses that we are being requested to use. */
2574 hw->num_mc_addrs = mc_addr_count;
2576 /* Clear RAR[1-15] */
2577 DEBUGOUT(" Clearing RAR[1-15]\n");
2578 for(i = rar_used_count; i < E1000_RAR_ENTRIES; i++) {
2579 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
2580 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
2584 DEBUGOUT(" Clearing MTA\n");
2585 for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++) {
2586 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
2589 /* Add the new addresses */
2590 for(i = 0; i < mc_addr_count; i++) {
2591 DEBUGOUT(" Adding the multicast addresses:\n");
2592 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
2593 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
2594 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
2595 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
2596 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
2597 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
2598 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
2600 hash_value = em_hash_mc_addr(hw,
2602 (i * (ETH_LENGTH_OF_ADDRESS + pad)));
2604 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
2606 /* Place this multicast address in the RAR if there is room, *
2607 * else put it in the MTA
2609 if(rar_used_count < E1000_RAR_ENTRIES) {
2611 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
2615 em_mta_set(hw, hash_value);
2618 DEBUGOUT("MC Update Complete\n");
2621 /******************************************************************************
2622 * Hashes an address to determine its location in the multicast table
2624 * hw - Struct containing variables accessed by shared code
2625 * mc_addr - the multicast address to hash
2626 *****************************************************************************/
2628 em_hash_mc_addr(struct em_hw *hw,
2631 uint32_t hash_value = 0;
2633 /* The portion of the address that is used for the hash table is
2634 * determined by the mc_filter_type setting.
2636 switch (hw->mc_filter_type) {
2637 /* [0] [1] [2] [3] [4] [5]
2642 /* [47:36] i.e. 0x563 for above example address */
2643 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
2646 /* [46:35] i.e. 0xAC6 for above example address */
2647 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
2650 /* [45:34] i.e. 0x5D8 for above example address */
2651 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
2654 /* [43:32] i.e. 0x634 for above example address */
2655 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
2659 hash_value &= 0xFFF;
2663 /******************************************************************************
2664 * Sets the bit in the multicast table corresponding to the hash value.
2666 * hw - Struct containing variables accessed by shared code
2667 * hash_value - Multicast address hash value
2668 *****************************************************************************/
2670 em_mta_set(struct em_hw *hw,
2671 uint32_t hash_value)
2673 uint32_t hash_bit, hash_reg;
2677 /* The MTA is a register array of 128 32-bit registers.
2678 * It is treated like an array of 4096 bits. We want to set
2679 * bit BitArray[hash_value]. So we figure out what register
2680 * the bit is in, read it, OR in the new bit, then write
2681 * back the new value. The register is determined by the
2682 * upper 7 bits of the hash value and the bit within that
2683 * register are determined by the lower 5 bits of the value.
2685 hash_reg = (hash_value >> 5) & 0x7F;
2686 hash_bit = hash_value & 0x1F;
2688 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
2690 mta |= (1 << hash_bit);
2692 /* If we are on an 82544 and we are trying to write an odd offset
2693 * in the MTA, save off the previous entry before writing and
2694 * restore the old value after writing.
2696 if((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) {
2697 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
2698 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
2699 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
2701 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
2705 /******************************************************************************
2706 * Puts an ethernet address into a receive address register.
2708 * hw - Struct containing variables accessed by shared code
2709 * addr - Address to put into receive address register
2710 * index - Receive address register to write
2711 *****************************************************************************/
2713 em_rar_set(struct em_hw *hw,
2717 uint32_t rar_low, rar_high;
2719 /* HW expects these in little endian so we reverse the byte order
2720 * from network order (big endian) to little endian
2722 rar_low = ((uint32_t) addr[0] |
2723 ((uint32_t) addr[1] << 8) |
2724 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
2726 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV);
2728 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
2729 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
2732 /******************************************************************************
2733 * Writes a value to the specified offset in the VLAN filter table.
2735 * hw - Struct containing variables accessed by shared code
2736 * offset - Offset in VLAN filer table to write
2737 * value - Value to write into VLAN filter table
2738 *****************************************************************************/
2740 em_write_vfta(struct em_hw *hw,
2746 if((hw->mac_type == em_82544) && ((offset & 0x1) == 1)) {
2747 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
2748 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
2749 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
2751 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
2755 /******************************************************************************
2756 * Clears the VLAN filer table
2758 * hw - Struct containing variables accessed by shared code
2759 *****************************************************************************/
2761 em_clear_vfta(struct em_hw *hw)
2765 for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
2766 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
2770 em_id_led_init(struct em_hw * hw)
2773 const uint32_t ledctl_mask = 0x000000FF;
2774 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
2775 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
2776 uint16_t eeprom_data, i, temp;
2777 const uint16_t led_mask = 0x0F;
2779 DEBUGFUNC("em_id_led_init");
2781 if(hw->mac_type < em_82540) {
2786 ledctl = E1000_READ_REG(hw, LEDCTL);
2787 hw->ledctl_default = ledctl;
2788 hw->ledctl_mode1 = hw->ledctl_default;
2789 hw->ledctl_mode2 = hw->ledctl_default;
2791 if(em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, &eeprom_data) < 0) {
2792 DEBUGOUT("EEPROM Read Error\n");
2793 return -E1000_ERR_EEPROM;
2795 if((eeprom_data== ID_LED_RESERVED_0000) ||
2796 (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT;
2797 for(i = 0; i < 4; i++) {
2798 temp = (eeprom_data >> (i << 2)) & led_mask;
2800 case ID_LED_ON1_DEF2:
2801 case ID_LED_ON1_ON2:
2802 case ID_LED_ON1_OFF2:
2803 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
2804 hw->ledctl_mode1 |= ledctl_on << (i << 3);
2806 case ID_LED_OFF1_DEF2:
2807 case ID_LED_OFF1_ON2:
2808 case ID_LED_OFF1_OFF2:
2809 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
2810 hw->ledctl_mode1 |= ledctl_off << (i << 3);
2817 case ID_LED_DEF1_ON2:
2818 case ID_LED_ON1_ON2:
2819 case ID_LED_OFF1_ON2:
2820 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
2821 hw->ledctl_mode2 |= ledctl_on << (i << 3);
2823 case ID_LED_DEF1_OFF2:
2824 case ID_LED_ON1_OFF2:
2825 case ID_LED_OFF1_OFF2:
2826 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
2827 hw->ledctl_mode2 |= ledctl_off << (i << 3);
2837 /******************************************************************************
2838 * Prepares SW controlable LED for use and saves the current state of the LED.
2840 * hw - Struct containing variables accessed by shared code
2841 *****************************************************************************/
2843 em_setup_led(struct em_hw *hw)
2847 DEBUGFUNC("em_setup_led");
2849 switch(hw->device_id) {
2850 case E1000_DEV_ID_82542:
2851 case E1000_DEV_ID_82543GC_FIBER:
2852 case E1000_DEV_ID_82543GC_COPPER:
2853 case E1000_DEV_ID_82544EI_COPPER:
2854 case E1000_DEV_ID_82544EI_FIBER:
2855 case E1000_DEV_ID_82544GC_COPPER:
2856 case E1000_DEV_ID_82544GC_LOM:
2857 /* No setup necessary */
2859 case E1000_DEV_ID_82545EM_FIBER:
2860 case E1000_DEV_ID_82546EB_FIBER:
2861 ledctl = E1000_READ_REG(hw, LEDCTL);
2862 /* Save current LEDCTL settings */
2863 hw->ledctl_default = ledctl;
2865 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
2866 E1000_LEDCTL_LED0_BLINK |
2867 E1000_LEDCTL_LED0_MODE_MASK);
2868 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << E1000_LEDCTL_LED0_MODE_SHIFT);
2869 E1000_WRITE_REG(hw, LEDCTL, ledctl);
2871 case E1000_DEV_ID_82540EM:
2872 case E1000_DEV_ID_82540EM_LOM:
2873 case E1000_DEV_ID_82545EM_COPPER:
2874 case E1000_DEV_ID_82546EB_COPPER:
2875 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
2878 DEBUGOUT("Invalid device ID\n");
2879 return -E1000_ERR_CONFIG;
2884 /******************************************************************************
2885 * Restores the saved state of the SW controlable LED.
2887 * hw - Struct containing variables accessed by shared code
2888 *****************************************************************************/
2890 em_cleanup_led(struct em_hw *hw)
2892 DEBUGFUNC("em_cleanup_led");
2894 switch(hw->device_id) {
2895 case E1000_DEV_ID_82542:
2896 case E1000_DEV_ID_82543GC_FIBER:
2897 case E1000_DEV_ID_82543GC_COPPER:
2898 case E1000_DEV_ID_82544EI_COPPER:
2899 case E1000_DEV_ID_82544EI_FIBER:
2900 case E1000_DEV_ID_82544GC_COPPER:
2901 case E1000_DEV_ID_82544GC_LOM:
2902 /* No cleanup necessary */
2904 case E1000_DEV_ID_82540EM:
2905 case E1000_DEV_ID_82540EM_LOM:
2906 case E1000_DEV_ID_82545EM_COPPER:
2907 case E1000_DEV_ID_82545EM_FIBER:
2908 case E1000_DEV_ID_82546EB_COPPER:
2909 case E1000_DEV_ID_82546EB_FIBER:
2910 /* Restore LEDCTL settings */
2911 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
2914 DEBUGOUT("Invalid device ID\n");
2915 return -E1000_ERR_CONFIG;
2920 /******************************************************************************
2921 * Turns on the software controllable LED
2923 * hw - Struct containing variables accessed by shared code
2924 *****************************************************************************/
2926 em_led_on(struct em_hw *hw)
2930 DEBUGFUNC("em_led_on");
2932 switch(hw->device_id) {
2933 case E1000_DEV_ID_82542:
2934 case E1000_DEV_ID_82543GC_FIBER:
2935 case E1000_DEV_ID_82543GC_COPPER:
2936 case E1000_DEV_ID_82544EI_FIBER:
2937 ctrl = E1000_READ_REG(hw, CTRL);
2938 /* Set SW Defineable Pin 0 to turn on the LED */
2939 ctrl |= E1000_CTRL_SWDPIN0;
2940 ctrl |= E1000_CTRL_SWDPIO0;
2941 E1000_WRITE_REG(hw, CTRL, ctrl);
2943 case E1000_DEV_ID_82544EI_COPPER:
2944 case E1000_DEV_ID_82544GC_COPPER:
2945 case E1000_DEV_ID_82544GC_LOM:
2946 case E1000_DEV_ID_82545EM_FIBER:
2947 case E1000_DEV_ID_82546EB_FIBER:
2948 ctrl = E1000_READ_REG(hw, CTRL);
2949 /* Clear SW Defineable Pin 0 to turn on the LED */
2950 ctrl &= ~E1000_CTRL_SWDPIN0;
2951 ctrl |= E1000_CTRL_SWDPIO0;
2952 E1000_WRITE_REG(hw, CTRL, ctrl);
2954 case E1000_DEV_ID_82540EM:
2955 case E1000_DEV_ID_82540EM_LOM:
2956 case E1000_DEV_ID_82545EM_COPPER:
2957 case E1000_DEV_ID_82546EB_COPPER:
2958 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
2961 DEBUGOUT("Invalid device ID\n");
2962 return -E1000_ERR_CONFIG;
2967 /******************************************************************************
2968 * Turns off the software controllable LED
2970 * hw - Struct containing variables accessed by shared code
2971 *****************************************************************************/
2973 em_led_off(struct em_hw *hw)
2977 DEBUGFUNC("em_led_off");
2979 switch(hw->device_id) {
2980 case E1000_DEV_ID_82542:
2981 case E1000_DEV_ID_82543GC_FIBER:
2982 case E1000_DEV_ID_82543GC_COPPER:
2983 case E1000_DEV_ID_82544EI_FIBER:
2984 ctrl = E1000_READ_REG(hw, CTRL);
2985 /* Clear SW Defineable Pin 0 to turn off the LED */
2986 ctrl &= ~E1000_CTRL_SWDPIN0;
2987 ctrl |= E1000_CTRL_SWDPIO0;
2988 E1000_WRITE_REG(hw, CTRL, ctrl);
2990 case E1000_DEV_ID_82544EI_COPPER:
2991 case E1000_DEV_ID_82544GC_COPPER:
2992 case E1000_DEV_ID_82544GC_LOM:
2993 case E1000_DEV_ID_82545EM_FIBER:
2994 case E1000_DEV_ID_82546EB_FIBER:
2995 ctrl = E1000_READ_REG(hw, CTRL);
2996 /* Set SW Defineable Pin 0 to turn off the LED */
2997 ctrl |= E1000_CTRL_SWDPIN0;
2998 ctrl |= E1000_CTRL_SWDPIO0;
2999 E1000_WRITE_REG(hw, CTRL, ctrl);
3001 case E1000_DEV_ID_82540EM:
3002 case E1000_DEV_ID_82540EM_LOM:
3003 case E1000_DEV_ID_82545EM_COPPER:
3004 case E1000_DEV_ID_82546EB_COPPER:
3005 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
3008 DEBUGOUT("Invalid device ID\n");
3009 return -E1000_ERR_CONFIG;
3014 /******************************************************************************
3015 * Clears all hardware statistics counters.
3017 * hw - Struct containing variables accessed by shared code
3018 *****************************************************************************/
3020 em_clear_hw_cntrs(struct em_hw *hw)
3022 volatile uint32_t temp;
3024 temp = E1000_READ_REG(hw, CRCERRS);
3025 temp = E1000_READ_REG(hw, SYMERRS);
3026 temp = E1000_READ_REG(hw, MPC);
3027 temp = E1000_READ_REG(hw, SCC);
3028 temp = E1000_READ_REG(hw, ECOL);
3029 temp = E1000_READ_REG(hw, MCC);
3030 temp = E1000_READ_REG(hw, LATECOL);
3031 temp = E1000_READ_REG(hw, COLC);
3032 temp = E1000_READ_REG(hw, DC);
3033 temp = E1000_READ_REG(hw, SEC);
3034 temp = E1000_READ_REG(hw, RLEC);
3035 temp = E1000_READ_REG(hw, XONRXC);
3036 temp = E1000_READ_REG(hw, XONTXC);
3037 temp = E1000_READ_REG(hw, XOFFRXC);
3038 temp = E1000_READ_REG(hw, XOFFTXC);
3039 temp = E1000_READ_REG(hw, FCRUC);
3040 temp = E1000_READ_REG(hw, PRC64);
3041 temp = E1000_READ_REG(hw, PRC127);
3042 temp = E1000_READ_REG(hw, PRC255);
3043 temp = E1000_READ_REG(hw, PRC511);
3044 temp = E1000_READ_REG(hw, PRC1023);
3045 temp = E1000_READ_REG(hw, PRC1522);
3046 temp = E1000_READ_REG(hw, GPRC);
3047 temp = E1000_READ_REG(hw, BPRC);
3048 temp = E1000_READ_REG(hw, MPRC);
3049 temp = E1000_READ_REG(hw, GPTC);
3050 temp = E1000_READ_REG(hw, GORCL);
3051 temp = E1000_READ_REG(hw, GORCH);
3052 temp = E1000_READ_REG(hw, GOTCL);
3053 temp = E1000_READ_REG(hw, GOTCH);
3054 temp = E1000_READ_REG(hw, RNBC);
3055 temp = E1000_READ_REG(hw, RUC);
3056 temp = E1000_READ_REG(hw, RFC);
3057 temp = E1000_READ_REG(hw, ROC);
3058 temp = E1000_READ_REG(hw, RJC);
3059 temp = E1000_READ_REG(hw, TORL);
3060 temp = E1000_READ_REG(hw, TORH);
3061 temp = E1000_READ_REG(hw, TOTL);
3062 temp = E1000_READ_REG(hw, TOTH);
3063 temp = E1000_READ_REG(hw, TPR);
3064 temp = E1000_READ_REG(hw, TPT);
3065 temp = E1000_READ_REG(hw, PTC64);
3066 temp = E1000_READ_REG(hw, PTC127);
3067 temp = E1000_READ_REG(hw, PTC255);
3068 temp = E1000_READ_REG(hw, PTC511);
3069 temp = E1000_READ_REG(hw, PTC1023);
3070 temp = E1000_READ_REG(hw, PTC1522);
3071 temp = E1000_READ_REG(hw, MPTC);
3072 temp = E1000_READ_REG(hw, BPTC);
3074 if(hw->mac_type < em_82543) return;
3076 temp = E1000_READ_REG(hw, ALGNERRC);
3077 temp = E1000_READ_REG(hw, RXERRC);
3078 temp = E1000_READ_REG(hw, TNCRS);
3079 temp = E1000_READ_REG(hw, CEXTERR);
3080 temp = E1000_READ_REG(hw, TSCTC);
3081 temp = E1000_READ_REG(hw, TSCTFC);
3083 if(hw->mac_type <= em_82544) return;
3085 temp = E1000_READ_REG(hw, MGTPRC);
3086 temp = E1000_READ_REG(hw, MGTPDC);
3087 temp = E1000_READ_REG(hw, MGTPTC);
3090 /******************************************************************************
3091 * Resets Adaptive IFS to its default state.
3093 * hw - Struct containing variables accessed by shared code
3095 * Call this after em_init_hw. You may override the IFS defaults by setting
3096 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
3097 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
3098 * before calling this function.
3099 *****************************************************************************/
3101 em_reset_adaptive(struct em_hw *hw)
3103 DEBUGFUNC("em_reset_adaptive");
3105 if(hw->adaptive_ifs) {
3106 if(!hw->ifs_params_forced) {
3107 hw->current_ifs_val = 0;
3108 hw->ifs_min_val = IFS_MIN;
3109 hw->ifs_max_val = IFS_MAX;
3110 hw->ifs_step_size = IFS_STEP;
3111 hw->ifs_ratio = IFS_RATIO;
3113 hw->in_ifs_mode = FALSE;
3114 E1000_WRITE_REG(hw, AIT, 0);
3116 DEBUGOUT("Not in Adaptive IFS mode!\n");
3120 /******************************************************************************
3121 * Called during the callback/watchdog routine to update IFS value based on
3122 * the ratio of transmits to collisions.
3124 * hw - Struct containing variables accessed by shared code
3125 * tx_packets - Number of transmits since last callback
3126 * total_collisions - Number of collisions since last callback
3127 *****************************************************************************/
3129 em_update_adaptive(struct em_hw *hw)
3131 DEBUGFUNC("em_update_adaptive");
3133 if(hw->adaptive_ifs) {
3134 if((hw->collision_delta * hw->ifs_ratio) >
3135 hw->tx_packet_delta) {
3136 if(hw->tx_packet_delta > MIN_NUM_XMITS) {
3137 hw->in_ifs_mode = TRUE;
3138 if(hw->current_ifs_val < hw->ifs_max_val) {
3139 if(hw->current_ifs_val == 0)
3140 hw->current_ifs_val = hw->ifs_min_val;
3142 hw->current_ifs_val += hw->ifs_step_size;
3143 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
3147 if((hw->in_ifs_mode == TRUE) &&
3148 (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
3149 hw->current_ifs_val = 0;
3150 hw->in_ifs_mode = FALSE;
3151 E1000_WRITE_REG(hw, AIT, 0);
3155 DEBUGOUT("Not in Adaptive IFS mode!\n");
3159 /******************************************************************************
3160 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
3162 * hw - Struct containing variables accessed by shared code
3163 * frame_len - The length of the frame in question
3164 * mac_addr - The Ethernet destination address of the frame in question
3165 *****************************************************************************/
3167 em_tbi_adjust_stats(struct em_hw *hw,
3168 struct em_hw_stats *stats,
3174 /* First adjust the frame length. */
3176 /* We need to adjust the statistics counters, since the hardware
3177 * counters overcount this packet as a CRC error and undercount
3178 * the packet as a good packet
3180 /* This packet should not be counted as a CRC error. */
3182 /* This packet does count as a Good Packet Received. */
3185 /* Adjust the Good Octets received counters */
3186 carry_bit = 0x80000000 & stats->gorcl;
3187 stats->gorcl += frame_len;
3188 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
3189 * Received Count) was one before the addition,
3190 * AND it is zero after, then we lost the carry out,
3191 * need to add one to Gorch (Good Octets Received Count High).
3192 * This could be simplified if all environments supported
3195 if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
3197 /* Is this a broadcast or multicast? Check broadcast first,
3198 * since the test for a multicast frame will test positive on
3199 * a broadcast frame.
3201 if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
3202 /* Broadcast packet */
3204 else if(*mac_addr & 0x01)
3205 /* Multicast packet */
3208 if(frame_len == hw->max_frame_size) {
3209 /* In this case, the hardware has overcounted the number of
3216 /* Adjust the bin counters when the extra byte put the frame in the
3217 * wrong bin. Remember that the frame_len was adjusted above.
3219 if(frame_len == 64) {
3222 } else if(frame_len == 127) {
3225 } else if(frame_len == 255) {
3228 } else if(frame_len == 511) {
3231 } else if(frame_len == 1023) {
3234 } else if(frame_len == 1522) {
3239 /******************************************************************************
3240 * Gets the current PCI bus type, speed, and width of the hardware
3242 * hw - Struct containing variables accessed by shared code
3243 *****************************************************************************/
3245 em_get_bus_info(struct em_hw *hw)
3249 if(hw->mac_type < em_82543) {
3250 hw->bus_type = em_bus_type_unknown;
3251 hw->bus_speed = em_bus_speed_unknown;
3252 hw->bus_width = em_bus_width_unknown;
3256 status = E1000_READ_REG(hw, STATUS);
3257 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
3258 em_bus_type_pcix : em_bus_type_pci;
3259 if(hw->bus_type == em_bus_type_pci) {
3260 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
3261 em_bus_speed_66 : em_bus_speed_33;
3263 switch (status & E1000_STATUS_PCIX_SPEED) {
3264 case E1000_STATUS_PCIX_SPEED_66:
3265 hw->bus_speed = em_bus_speed_66;
3267 case E1000_STATUS_PCIX_SPEED_100:
3268 hw->bus_speed = em_bus_speed_100;
3270 case E1000_STATUS_PCIX_SPEED_133:
3271 hw->bus_speed = em_bus_speed_133;
3274 hw->bus_speed = em_bus_speed_reserved;
3278 hw->bus_width = (status & E1000_STATUS_BUS64) ?
3279 em_bus_width_64 : em_bus_width_32;