1 /*******************************************************************************
3 Copyright (c) 2001-2002 Intel Corporation
6 Redistribution and use in source and binary forms of the Software, with or
7 without modification, are permitted provided that the following conditions
10 1. Redistributions of source code of the Software may retain the above
11 copyright notice, this list of conditions and the following disclaimer.
13 2. Redistributions in binary form of the Software may reproduce the above
14 copyright notice, this list of conditions and the following disclaimer
15 in the documentation and/or other materials provided with the
18 3. Neither the name of the Intel Corporation nor the names of its
19 contributors shall be used to endorse or promote products derived from
20 this Software without specific prior written permission.
22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS CONTRIBUTORS BE LIABLE
26 FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 *******************************************************************************/
38 * Structures, enums, and macros for the MAC
44 #include <dev/em/if_em_osdep.h>
46 /* Forward declarations of structures used by the shared code */
50 /* Enumerated types specific to the e1000 hardware */
51 /* Media Access Controlers */
65 em_media_type_copper = 0,
66 em_media_type_fiber = 1,
75 } em_speed_duplex_type;
77 /* Flow Control Settings */
88 em_bus_type_unknown = 0,
95 em_bus_speed_unknown = 0,
100 em_bus_speed_reserved
105 em_bus_width_unknown = 0,
110 /* PHY status info structure and supporting enums */
112 em_cable_length_50 = 0,
113 em_cable_length_50_80,
114 em_cable_length_80_110,
115 em_cable_length_110_140,
117 em_cable_length_undefined = 0xFF
121 em_10bt_ext_dist_enable_normal = 0,
122 em_10bt_ext_dist_enable_lower,
123 em_10bt_ext_dist_enable_undefined = 0xFF
124 } em_10bt_ext_dist_enable;
127 em_rev_polarity_normal = 0,
128 em_rev_polarity_reversed,
129 em_rev_polarity_undefined = 0xFF
133 em_polarity_reversal_enabled = 0,
134 em_polarity_reversal_disabled,
135 em_polarity_reversal_undefined = 0xFF
136 } em_polarity_reversal;
139 em_auto_x_mode_manual_mdi = 0,
140 em_auto_x_mode_manual_mdix,
141 em_auto_x_mode_auto1,
142 em_auto_x_mode_auto2,
143 em_auto_x_mode_undefined = 0xFF
147 em_1000t_rx_status_not_ok = 0,
148 em_1000t_rx_status_ok,
149 em_1000t_rx_status_undefined = 0xFF
150 } em_1000t_rx_status;
153 em_cable_length cable_length;
154 em_10bt_ext_dist_enable extended_10bt_distance;
155 em_rev_polarity cable_polarity;
156 em_polarity_reversal polarity_correction;
157 em_auto_x_mode mdix_mode;
158 em_1000t_rx_status local_rx;
159 em_1000t_rx_status remote_rx;
162 struct em_phy_stats {
163 uint32_t idle_errors;
164 uint32_t receive_errors;
170 #define E1000_SUCCESS 0
171 #define E1000_ERR_EEPROM 1
172 #define E1000_ERR_PHY 2
173 #define E1000_ERR_CONFIG 3
174 #define E1000_ERR_PARAM 4
176 /* Function prototypes */
178 void em_reset_hw(struct em_hw *hw);
179 int32_t em_init_hw(struct em_hw *hw);
181 /* Link Configuration */
182 int32_t em_setup_link(struct em_hw *hw);
183 int32_t em_phy_setup_autoneg(struct em_hw *hw);
184 void em_config_collision_dist(struct em_hw *hw);
185 int32_t em_config_fc_after_link_up(struct em_hw *hw);
186 int32_t em_check_for_link(struct em_hw *hw);
187 void em_get_speed_and_duplex(struct em_hw *hw, uint16_t * speed, uint16_t * duplex);
188 int32_t em_wait_autoneg(struct em_hw *hw);
191 int32_t em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
192 int32_t em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data);
193 void em_phy_hw_reset(struct em_hw *hw);
194 int32_t em_phy_reset(struct em_hw *hw);
195 int32_t em_detect_gig_phy(struct em_hw *hw);
196 int32_t em_phy_get_info(struct em_hw *hw, struct em_phy_info *phy_info);
197 int32_t em_validate_mdi_setting(struct em_hw *hw);
199 /* EEPROM Functions */
200 int32_t em_read_eeprom(struct em_hw *hw, uint16_t reg, uint16_t *data);
201 int32_t em_validate_eeprom_checksum(struct em_hw *hw);
202 int32_t em_update_eeprom_checksum(struct em_hw *hw);
203 int32_t em_write_eeprom(struct em_hw *hw, uint16_t reg, uint16_t data);
204 int32_t em_read_part_num(struct em_hw *hw, uint32_t * part_num);
205 int32_t em_read_mac_addr(struct em_hw * hw);
207 /* Filters (multicast, vlan, receive) */
208 void em_init_rx_addrs(struct em_hw *hw);
209 void em_mc_addr_list_update(struct em_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad);
210 uint32_t em_hash_mc_addr(struct em_hw *hw, uint8_t * mc_addr);
211 void em_mta_set(struct em_hw *hw, uint32_t hash_value);
212 void em_rar_set(struct em_hw *hw, uint8_t * mc_addr, uint32_t rar_index);
213 void em_write_vfta(struct em_hw *hw, uint32_t offset, uint32_t value);
214 void em_clear_vfta(struct em_hw *hw);
217 int32_t em_setup_led(struct em_hw *hw);
218 int32_t em_cleanup_led(struct em_hw *hw);
219 int32_t em_led_on(struct em_hw *hw);
220 int32_t em_led_off(struct em_hw *hw);
222 /* Adaptive IFS Functions */
224 /* Everything else */
225 void em_clear_hw_cntrs(struct em_hw *hw);
226 void em_reset_adaptive(struct em_hw *hw);
227 void em_update_adaptive(struct em_hw *hw);
228 void em_tbi_adjust_stats(struct em_hw *hw, struct em_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr);
229 void em_get_bus_info(struct em_hw *hw);
230 void em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t * value);
231 void em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t * value);
232 /* Port I/O is only supported on 82544 and newer */
233 uint32_t em_io_read(struct em_hw *hw, uint32_t port);
234 uint32_t em_read_reg_io(struct em_hw *hw, uint32_t offset);
235 void em_io_write(struct em_hw *hw, uint32_t port, uint32_t value);
236 void em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value);
237 #define E1000_READ_REG_IO(a, reg) \
238 em_read_reg_io((a), E1000_##reg)
239 #define E1000_WRITE_REG_IO(a, reg, val) \
240 em_write_reg_io((a), E1000_##reg, val)
243 #define E1000_DEV_ID_82542 0x1000
244 #define E1000_DEV_ID_82543GC_FIBER 0x1001
245 #define E1000_DEV_ID_82543GC_COPPER 0x1004
246 #define E1000_DEV_ID_82544EI_COPPER 0x1008
247 #define E1000_DEV_ID_82544EI_FIBER 0x1009
248 #define E1000_DEV_ID_82544GC_COPPER 0x100C
249 #define E1000_DEV_ID_82544GC_LOM 0x100D
250 #define E1000_DEV_ID_82540EM 0x100E
251 #define E1000_DEV_ID_82540EM_LOM 0x1015
252 #define E1000_DEV_ID_82545EM_COPPER 0x100F
253 #define E1000_DEV_ID_82545EM_FIBER 0x1011
254 #define E1000_DEV_ID_82546EB_COPPER 0x1010
255 #define E1000_DEV_ID_82546EB_FIBER 0x1012
256 #define NUM_DEV_IDS 13
258 #define NODE_ADDRESS_SIZE 6
259 #define ETH_LENGTH_OF_ADDRESS 6
261 /* MAC decode size is 128K - This is the size of BAR0 */
262 #define MAC_DECODE_SIZE (128 * 1024)
264 #define E1000_82542_2_0_REV_ID 2
265 #define E1000_82542_2_1_REV_ID 3
268 #define SPEED_100 100
269 #define SPEED_1000 1000
270 #define HALF_DUPLEX 1
271 #define FULL_DUPLEX 2
273 /* The sizes (in bytes) of a ethernet packet */
274 #define ENET_HEADER_SIZE 14
275 #define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */
276 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
277 #define ETHERNET_FCS_SIZE 4
278 #define MAXIMUM_ETHERNET_PACKET_SIZE \
279 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
280 #define MINIMUM_ETHERNET_PACKET_SIZE \
281 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
282 #define CRC_LENGTH ETHERNET_FCS_SIZE
283 #define MAX_JUMBO_FRAME_SIZE 0x3F00
286 /* 802.1q VLAN Packet Sizes */
287 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
289 /* Ethertype field values */
290 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
291 #define ETHERNET_IP_TYPE 0x0800 /* IP packets */
292 #define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
294 /* Packet Header defines */
295 #define IP_PROTOCOL_TCP 6
296 #define IP_PROTOCOL_UDP 0x11
298 /* This defines the bits that are set in the Interrupt Mask
299 * Set/Read Register. Each bit is documented below:
300 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
301 * o RXSEQ = Receive Sequence Error
303 #define POLL_IMS_ENABLE_MASK ( \
307 /* This defines the bits that are set in the Interrupt Mask
308 * Set/Read Register. Each bit is documented below:
309 * o RXT0 = Receiver Timer Interrupt (ring 0)
310 * o TXDW = Transmit Descriptor Written Back
311 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
312 * o RXSEQ = Receive Sequence Error
313 * o LSC = Link Status Change
315 #define IMS_ENABLE_MASK ( \
322 /* The number of high/low register pairs in the RAR. The RAR (Receive Address
323 * Registers) holds the directed and multicast addresses that we monitor. We
324 * reserve one of these spots for our directed address, allowing us room for
325 * E1000_RAR_ENTRIES - 1 multicast addresses.
327 #define E1000_RAR_ENTRIES 16
329 #define MIN_NUMBER_OF_DESCRIPTORS 8
330 #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
332 /* Receive Descriptor */
334 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
335 uint16_t length; /* Length of data DMAed into data buffer */
336 uint16_t csum; /* Packet checksum */
337 uint8_t status; /* Descriptor status */
338 uint8_t errors; /* Descriptor Errors */
342 /* Receive Decriptor bit definitions */
343 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
344 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
345 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
346 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
347 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
348 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
349 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
350 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */
351 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
352 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
353 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
354 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
355 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
356 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
357 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
358 #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
359 #define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */
360 #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
361 #define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */
363 /* mask to determine if packets should be dropped due to frame errors */
364 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
367 E1000_RXD_ERR_SEQ | \
368 E1000_RXD_ERR_CXE | \
371 /* Transmit Descriptor */
373 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
377 uint16_t length; /* Data buffer length */
378 uint8_t cso; /* Checksum offset */
379 uint8_t cmd; /* Descriptor control */
385 uint8_t status; /* Descriptor status */
386 uint8_t css; /* Checksum start */
392 /* Transmit Descriptor bit definitions */
393 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
394 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
395 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
396 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
397 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
398 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
399 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
400 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
401 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
402 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
403 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
404 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
405 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
406 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
407 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
408 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
409 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
410 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
411 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
412 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
414 /* Offload Context Descriptor */
415 struct em_context_desc {
419 uint8_t ipcss; /* IP checksum start */
420 uint8_t ipcso; /* IP checksum offset */
421 uint16_t ipcse; /* IP checksum end */
427 uint8_t tucss; /* TCP checksum start */
428 uint8_t tucso; /* TCP checksum offset */
429 uint16_t tucse; /* TCP checksum end */
432 uint32_t cmd_and_length; /* */
436 uint8_t status; /* Descriptor status */
437 uint8_t hdr_len; /* Header length */
438 uint16_t mss; /* Maximum segment size */
443 /* Offload data descriptor */
444 struct em_data_desc {
445 uint64_t buffer_addr; /* Address of the descriptor's buffer address */
449 uint16_t length; /* Data buffer length */
450 uint8_t typ_len_ext; /* */
457 uint8_t status; /* Descriptor status */
458 uint8_t popts; /* Packet Options */
459 uint16_t special; /* */
465 #define E1000_NUM_UNICAST 16 /* Unicast filter entries */
466 #define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
467 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
470 /* Receive Address Register */
472 volatile uint32_t low; /* receive address low */
473 volatile uint32_t high; /* receive address high */
476 /* The number of entries in the Multicast Table Array (MTA). */
477 #define E1000_NUM_MTA_REGISTERS 128
479 /* IPv4 Address Table Entry */
480 struct em_ipv4_at_entry {
481 volatile uint32_t ipv4_addr; /* IP Address (RW) */
482 volatile uint32_t reserved;
485 /* Four wakeup IP addresses are supported */
486 #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
487 #define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
488 #define E1000_IP6AT_SIZE 1
490 /* IPv6 Address Table Entry */
491 struct em_ipv6_at_entry {
492 volatile uint8_t ipv6_addr[16];
495 /* Flexible Filter Length Table Entry */
496 struct em_fflt_entry {
497 volatile uint32_t length; /* Flexible Filter Length (RW) */
498 volatile uint32_t reserved;
501 /* Flexible Filter Mask Table Entry */
502 struct em_ffmt_entry {
503 volatile uint32_t mask; /* Flexible Filter Mask (RW) */
504 volatile uint32_t reserved;
507 /* Flexible Filter Value Table Entry */
508 struct em_ffvt_entry {
509 volatile uint32_t value; /* Flexible Filter Value (RW) */
510 volatile uint32_t reserved;
513 /* Four Flexible Filters are supported */
514 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
516 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
517 #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
519 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
520 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
521 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
523 /* Register Set. (82543, 82544)
525 * Registers are defined to be 32 bits and should be accessed as 32 bit values.
526 * These registers are physically located on the NIC, but are mapped into the
527 * host memory address space.
529 * RW - register is both readable and writable
530 * RO - register is read only
531 * WO - register is write only
532 * R/clr - register is read only and is cleared when read
535 #define E1000_CTRL 0x00000 /* Device Control - RW */
536 #define E1000_STATUS 0x00008 /* Device Status - RO */
537 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
538 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
539 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
540 #define E1000_MDIC 0x00020 /* MDI Control - RW */
541 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
542 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
543 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
544 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */
545 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
546 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
547 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
548 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
549 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
550 #define E1000_RCTL 0x00100 /* RX Control - RW */
551 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
552 #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
553 #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
554 #define E1000_TCTL 0x00400 /* TX Control - RW */
555 #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
556 #define E1000_TBT 0x00448 /* TX Burst Timer - RW */
557 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
558 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */
559 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
560 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
561 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
562 #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
563 #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
564 #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
565 #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
566 #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
567 #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
568 #define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
569 #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
570 #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
571 #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
572 #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
573 #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
574 #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
575 #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
576 #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
577 #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
578 #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
579 #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
580 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
581 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
582 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
583 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
584 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
585 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
586 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
587 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
588 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
589 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
590 #define E1000_COLC 0x04028 /* Collision Count - R/clr */
591 #define E1000_DC 0x04030 /* Defer Count - R/clr */
592 #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
593 #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
594 #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
595 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
596 #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
597 #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
598 #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
599 #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
600 #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
601 #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
602 #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
603 #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
604 #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
605 #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
606 #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
607 #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
608 #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
609 #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
610 #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
611 #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
612 #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
613 #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
614 #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
615 #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
616 #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
617 #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
618 #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
619 #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
620 #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
621 #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
622 #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
623 #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
624 #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
625 #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
626 #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
627 #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
628 #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
629 #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
630 #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
631 #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
632 #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
633 #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
634 #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
635 #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
636 #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
637 #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
638 #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
639 #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
640 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
641 #define E1000_RA 0x05400 /* Receive Address - RW Array */
642 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
643 #define E1000_WUC 0x05800 /* Wakeup Control - RW */
644 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
645 #define E1000_WUS 0x05810 /* Wakeup Status - RO */
646 #define E1000_MANC 0x05820 /* Management Control - RW */
647 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */
648 #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
649 #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
650 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
651 #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
652 #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
653 #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
654 #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
656 /* Register Set (82542)
658 * Some of the 82542 registers are located at different offsets than they are
659 * in more current versions of the 8254x. Despite the difference in location,
660 * the registers function in the same manner.
662 #define E1000_82542_CTRL E1000_CTRL
663 #define E1000_82542_STATUS E1000_STATUS
664 #define E1000_82542_EECD E1000_EECD
665 #define E1000_82542_EERD E1000_EERD
666 #define E1000_82542_CTRL_EXT E1000_CTRL_EXT
667 #define E1000_82542_MDIC E1000_MDIC
668 #define E1000_82542_FCAL E1000_FCAL
669 #define E1000_82542_FCAH E1000_FCAH
670 #define E1000_82542_FCT E1000_FCT
671 #define E1000_82542_VET E1000_VET
672 #define E1000_82542_RA 0x00040
673 #define E1000_82542_ICR E1000_ICR
674 #define E1000_82542_ITR E1000_ITR
675 #define E1000_82542_ICS E1000_ICS
676 #define E1000_82542_IMS E1000_IMS
677 #define E1000_82542_IMC E1000_IMC
678 #define E1000_82542_RCTL E1000_RCTL
679 #define E1000_82542_RDTR 0x00108
680 #define E1000_82542_RDBAL 0x00110
681 #define E1000_82542_RDBAH 0x00114
682 #define E1000_82542_RDLEN 0x00118
683 #define E1000_82542_RDH 0x00120
684 #define E1000_82542_RDT 0x00128
685 #define E1000_82542_FCRTH 0x00160
686 #define E1000_82542_FCRTL 0x00168
687 #define E1000_82542_FCTTV E1000_FCTTV
688 #define E1000_82542_TXCW E1000_TXCW
689 #define E1000_82542_RXCW E1000_RXCW
690 #define E1000_82542_MTA 0x00200
691 #define E1000_82542_TCTL E1000_TCTL
692 #define E1000_82542_TIPG E1000_TIPG
693 #define E1000_82542_TDBAL 0x00420
694 #define E1000_82542_TDBAH 0x00424
695 #define E1000_82542_TDLEN 0x00428
696 #define E1000_82542_TDH 0x00430
697 #define E1000_82542_TDT 0x00438
698 #define E1000_82542_TIDV 0x00440
699 #define E1000_82542_TBT E1000_TBT
700 #define E1000_82542_AIT E1000_AIT
701 #define E1000_82542_VFTA 0x00600
702 #define E1000_82542_LEDCTL E1000_LEDCTL
703 #define E1000_82542_PBA E1000_PBA
704 #define E1000_82542_RXDCTL E1000_RXDCTL
705 #define E1000_82542_RADV E1000_RADV
706 #define E1000_82542_RSRPD E1000_RSRPD
707 #define E1000_82542_TXDMAC E1000_TXDMAC
708 #define E1000_82542_TXDCTL E1000_TXDCTL
709 #define E1000_82542_TADV E1000_TADV
710 #define E1000_82542_TSPMT E1000_TSPMT
711 #define E1000_82542_CRCERRS E1000_CRCERRS
712 #define E1000_82542_ALGNERRC E1000_ALGNERRC
713 #define E1000_82542_SYMERRS E1000_SYMERRS
714 #define E1000_82542_RXERRC E1000_RXERRC
715 #define E1000_82542_MPC E1000_MPC
716 #define E1000_82542_SCC E1000_SCC
717 #define E1000_82542_ECOL E1000_ECOL
718 #define E1000_82542_MCC E1000_MCC
719 #define E1000_82542_LATECOL E1000_LATECOL
720 #define E1000_82542_COLC E1000_COLC
721 #define E1000_82542_DC E1000_DC
722 #define E1000_82542_TNCRS E1000_TNCRS
723 #define E1000_82542_SEC E1000_SEC
724 #define E1000_82542_CEXTERR E1000_CEXTERR
725 #define E1000_82542_RLEC E1000_RLEC
726 #define E1000_82542_XONRXC E1000_XONRXC
727 #define E1000_82542_XONTXC E1000_XONTXC
728 #define E1000_82542_XOFFRXC E1000_XOFFRXC
729 #define E1000_82542_XOFFTXC E1000_XOFFTXC
730 #define E1000_82542_FCRUC E1000_FCRUC
731 #define E1000_82542_PRC64 E1000_PRC64
732 #define E1000_82542_PRC127 E1000_PRC127
733 #define E1000_82542_PRC255 E1000_PRC255
734 #define E1000_82542_PRC511 E1000_PRC511
735 #define E1000_82542_PRC1023 E1000_PRC1023
736 #define E1000_82542_PRC1522 E1000_PRC1522
737 #define E1000_82542_GPRC E1000_GPRC
738 #define E1000_82542_BPRC E1000_BPRC
739 #define E1000_82542_MPRC E1000_MPRC
740 #define E1000_82542_GPTC E1000_GPTC
741 #define E1000_82542_GORCL E1000_GORCL
742 #define E1000_82542_GORCH E1000_GORCH
743 #define E1000_82542_GOTCL E1000_GOTCL
744 #define E1000_82542_GOTCH E1000_GOTCH
745 #define E1000_82542_RNBC E1000_RNBC
746 #define E1000_82542_RUC E1000_RUC
747 #define E1000_82542_RFC E1000_RFC
748 #define E1000_82542_ROC E1000_ROC
749 #define E1000_82542_RJC E1000_RJC
750 #define E1000_82542_MGTPRC E1000_MGTPRC
751 #define E1000_82542_MGTPDC E1000_MGTPDC
752 #define E1000_82542_MGTPTC E1000_MGTPTC
753 #define E1000_82542_TORL E1000_TORL
754 #define E1000_82542_TORH E1000_TORH
755 #define E1000_82542_TOTL E1000_TOTL
756 #define E1000_82542_TOTH E1000_TOTH
757 #define E1000_82542_TPR E1000_TPR
758 #define E1000_82542_TPT E1000_TPT
759 #define E1000_82542_PTC64 E1000_PTC64
760 #define E1000_82542_PTC127 E1000_PTC127
761 #define E1000_82542_PTC255 E1000_PTC255
762 #define E1000_82542_PTC511 E1000_PTC511
763 #define E1000_82542_PTC1023 E1000_PTC1023
764 #define E1000_82542_PTC1522 E1000_PTC1522
765 #define E1000_82542_MPTC E1000_MPTC
766 #define E1000_82542_BPTC E1000_BPTC
767 #define E1000_82542_TSCTC E1000_TSCTC
768 #define E1000_82542_TSCTFC E1000_TSCTFC
769 #define E1000_82542_RXCSUM E1000_RXCSUM
770 #define E1000_82542_WUC E1000_WUC
771 #define E1000_82542_WUFC E1000_WUFC
772 #define E1000_82542_WUS E1000_WUS
773 #define E1000_82542_MANC E1000_MANC
774 #define E1000_82542_IPAV E1000_IPAV
775 #define E1000_82542_IP4AT E1000_IP4AT
776 #define E1000_82542_IP6AT E1000_IP6AT
777 #define E1000_82542_WUPL E1000_WUPL
778 #define E1000_82542_WUPM E1000_WUPM
779 #define E1000_82542_FFLT E1000_FFLT
780 #define E1000_82542_FFMT E1000_FFMT
781 #define E1000_82542_FFVT E1000_FFVT
783 /* Statistics counters collected by the MAC */
845 /* Structure containing variables used by the shared code (em_hw.c) */
848 em_mac_type mac_type;
849 em_media_type media_type;
852 em_bus_speed bus_speed;
853 em_bus_width bus_width;
854 em_bus_type bus_type;
858 uint32_t original_fc;
860 uint32_t autoneg_failed;
861 uint32_t max_frame_size;
862 uint32_t min_frame_size;
863 uint32_t mc_filter_type;
864 uint32_t num_mc_addrs;
865 uint32_t collision_delta;
866 uint32_t tx_packet_delta;
867 uint32_t ledctl_default;
868 uint32_t ledctl_mode1;
869 uint32_t ledctl_mode2;
870 uint16_t autoneg_advertised;
871 uint16_t pci_cmd_word;
872 uint16_t fc_high_water;
873 uint16_t fc_low_water;
874 uint16_t fc_pause_time;
875 uint16_t current_ifs_val;
876 uint16_t ifs_min_val;
877 uint16_t ifs_max_val;
878 uint16_t ifs_step_size;
882 uint16_t subsystem_id;
883 uint16_t subsystem_vendor_id;
887 uint8_t forced_speed_duplex;
888 uint8_t wait_autoneg_complete;
889 uint8_t dma_fairness;
890 uint8_t mac_addr[NODE_ADDRESS_SIZE];
891 uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
892 boolean_t disable_polarity_correction;
893 boolean_t get_link_status;
894 boolean_t tbi_compatibility_en;
895 boolean_t tbi_compatibility_on;
896 boolean_t fc_send_xon;
897 boolean_t report_tx_early;
898 boolean_t adaptive_ifs;
899 boolean_t ifs_params_forced;
900 boolean_t in_ifs_mode;
904 #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
905 #define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
907 /* Register Bit Masks */
909 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
910 #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
911 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
912 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
913 #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
914 #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
915 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
916 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
917 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
918 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
919 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
920 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
921 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
922 #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
923 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
924 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
925 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
926 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
927 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
928 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
929 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
930 #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
931 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
932 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
933 #define E1000_CTRL_RST 0x04000000 /* Global reset */
934 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
935 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
936 #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
937 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
938 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
941 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
942 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
943 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
944 #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
945 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
946 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
947 #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
948 #define E1000_STATUS_SPEED_MASK 0x000000C0
949 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
950 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
951 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
952 #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
953 #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
954 #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
955 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
956 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
957 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
959 /* Constants used to intrepret the masked PCI-X bus speed. */
960 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
961 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
962 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
964 /* EEPROM/Flash Control */
965 #define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
966 #define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
967 #define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
968 #define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
969 #define E1000_EECD_FWE_MASK 0x00000030
970 #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
971 #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
972 #define E1000_EECD_FWE_SHIFT 4
973 #define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
974 #define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
975 #define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
976 #define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
979 #define E1000_EERD_START 0x00000001 /* Start Read */
980 #define E1000_EERD_DONE 0x00000010 /* Read Done */
981 #define E1000_EERD_ADDR_SHIFT 8
982 #define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
983 #define E1000_EERD_DATA_SHIFT 16
984 #define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
986 /* Extended Device Control */
987 #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
988 #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
989 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
990 #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
991 #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
992 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
993 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
994 #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
995 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
996 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
997 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
998 #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
999 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
1000 #define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
1001 #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
1002 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
1003 #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
1004 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
1005 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1006 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1007 #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
1008 #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
1009 #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
1010 #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1011 #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1012 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1015 #define E1000_MDIC_DATA_MASK 0x0000FFFF
1016 #define E1000_MDIC_REG_MASK 0x001F0000
1017 #define E1000_MDIC_REG_SHIFT 16
1018 #define E1000_MDIC_PHY_MASK 0x03E00000
1019 #define E1000_MDIC_PHY_SHIFT 21
1020 #define E1000_MDIC_OP_WRITE 0x04000000
1021 #define E1000_MDIC_OP_READ 0x08000000
1022 #define E1000_MDIC_READY 0x10000000
1023 #define E1000_MDIC_INT_EN 0x20000000
1024 #define E1000_MDIC_ERROR 0x40000000
1027 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1028 #define E1000_LEDCTL_LED0_MODE_SHIFT 0
1029 #define E1000_LEDCTL_LED0_IVRT 0x00000040
1030 #define E1000_LEDCTL_LED0_BLINK 0x00000080
1031 #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
1032 #define E1000_LEDCTL_LED1_MODE_SHIFT 8
1033 #define E1000_LEDCTL_LED1_IVRT 0x00004000
1034 #define E1000_LEDCTL_LED1_BLINK 0x00008000
1035 #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
1036 #define E1000_LEDCTL_LED2_MODE_SHIFT 16
1037 #define E1000_LEDCTL_LED2_IVRT 0x00400000
1038 #define E1000_LEDCTL_LED2_BLINK 0x00800000
1039 #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
1040 #define E1000_LEDCTL_LED3_MODE_SHIFT 24
1041 #define E1000_LEDCTL_LED3_IVRT 0x40000000
1042 #define E1000_LEDCTL_LED3_BLINK 0x80000000
1044 #define E1000_LEDCTL_MODE_LINK_10_1000 0x0
1045 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1
1046 #define E1000_LEDCTL_MODE_LINK_UP 0x2
1047 #define E1000_LEDCTL_MODE_ACTIVITY 0x3
1048 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
1049 #define E1000_LEDCTL_MODE_LINK_10 0x5
1050 #define E1000_LEDCTL_MODE_LINK_100 0x6
1051 #define E1000_LEDCTL_MODE_LINK_1000 0x7
1052 #define E1000_LEDCTL_MODE_PCIX_MODE 0x8
1053 #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
1054 #define E1000_LEDCTL_MODE_COLLISION 0xA
1055 #define E1000_LEDCTL_MODE_BUS_SPEED 0xB
1056 #define E1000_LEDCTL_MODE_BUS_SIZE 0xC
1057 #define E1000_LEDCTL_MODE_PAUSED 0xD
1058 #define E1000_LEDCTL_MODE_LED_ON 0xE
1059 #define E1000_LEDCTL_MODE_LED_OFF 0xF
1061 /* Receive Address */
1062 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1064 /* Interrupt Cause Read */
1065 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
1066 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
1067 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */
1068 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1069 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
1070 #define E1000_ICR_RXO 0x00000040 /* rx overrun */
1071 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1072 #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
1073 #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
1074 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
1075 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
1076 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
1077 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
1078 #define E1000_ICR_TXD_LOW 0x00008000
1079 #define E1000_ICR_SRPD 0x00010000
1081 /* Interrupt Cause Set */
1082 #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1083 #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1084 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
1085 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1086 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1087 #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
1088 #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1089 #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1090 #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1091 #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1092 #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1093 #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1094 #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1095 #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1096 #define E1000_ICS_SRPD E1000_ICR_SRPD
1098 /* Interrupt Mask Set */
1099 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1100 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1101 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
1102 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1103 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1104 #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
1105 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1106 #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1107 #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1108 #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1109 #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1110 #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1111 #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1112 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1113 #define E1000_IMS_SRPD E1000_ICR_SRPD
1115 /* Interrupt Mask Clear */
1116 #define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1117 #define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1118 #define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
1119 #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1120 #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1121 #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
1122 #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1123 #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
1124 #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1125 #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1126 #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1127 #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1128 #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1129 #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1130 #define E1000_IMC_SRPD E1000_ICR_SRPD
1132 /* Receive Control */
1133 #define E1000_RCTL_RST 0x00000001 /* Software reset */
1134 #define E1000_RCTL_EN 0x00000002 /* enable */
1135 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */
1136 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
1137 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
1138 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */
1139 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
1140 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1141 #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1142 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
1143 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1144 #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1145 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
1146 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
1147 #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
1148 #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
1149 #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
1150 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
1151 #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
1152 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
1153 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
1154 #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1155 #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1156 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1157 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
1158 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
1159 #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1160 #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1161 #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1162 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
1163 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
1164 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
1165 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
1166 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1167 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
1169 /* Receive Descriptor */
1170 #define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
1171 #define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
1172 #define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
1173 #define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
1174 #define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
1177 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
1178 #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
1179 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1180 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1182 /* Receive Descriptor Control */
1183 #define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1184 #define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
1185 #define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
1186 #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
1188 /* Transmit Descriptor Control */
1189 #define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */
1190 #define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */
1191 #define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */
1192 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
1193 #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1195 /* Transmit Configuration Word */
1196 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
1197 #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
1198 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
1199 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
1200 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
1201 #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
1202 #define E1000_TXCW_NP 0x00008000 /* TXCW next page */
1203 #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
1204 #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1205 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1207 /* Receive Configuration Word */
1208 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
1209 #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
1210 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
1211 #define E1000_RXCW_CC 0x10000000 /* Receive config change */
1212 #define E1000_RXCW_C 0x20000000 /* Receive config */
1213 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
1214 #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
1216 /* Transmit Control */
1217 #define E1000_TCTL_RST 0x00000001 /* software reset */
1218 #define E1000_TCTL_EN 0x00000002 /* enable tx */
1219 #define E1000_TCTL_BCE 0x00000004 /* busy check enable */
1220 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */
1221 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
1222 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */
1223 #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
1224 #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
1225 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1226 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
1228 /* Receive Checksum Control */
1229 #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
1230 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
1231 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
1232 #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
1234 /* Definitions for power management and wakeup registers */
1235 /* Wake Up Control */
1236 #define E1000_WUC_APME 0x00000001 /* APM Enable */
1237 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
1238 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
1239 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
1241 /* Wake Up Filter Control */
1242 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
1243 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
1244 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
1245 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
1246 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
1247 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
1248 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
1249 #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
1250 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
1251 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
1252 #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
1253 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
1254 #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
1255 #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
1256 #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1258 /* Wake Up Status */
1259 #define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
1260 #define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
1261 #define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
1262 #define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
1263 #define E1000_WUS_BC 0x00000010 /* Broadcast Received */
1264 #define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
1265 #define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
1266 #define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
1267 #define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
1268 #define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
1269 #define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
1270 #define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
1271 #define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1273 /* Management Control */
1274 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
1275 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
1276 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
1277 #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
1278 #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
1279 #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
1280 #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
1281 #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
1282 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
1283 #define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
1285 #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
1286 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
1287 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
1288 #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
1289 #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
1290 #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
1291 #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
1292 #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
1293 #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
1295 #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
1296 #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
1298 /* Wake Up Packet Length */
1299 #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
1301 #define E1000_MDALIGN 4096
1303 /* EEPROM Commands */
1304 #define EEPROM_READ_OPCODE 0x6 /* EERPOM read opcode */
1305 #define EEPROM_WRITE_OPCODE 0x5 /* EERPOM write opcode */
1306 #define EEPROM_ERASE_OPCODE 0x7 /* EERPOM erase opcode */
1307 #define EEPROM_EWEN_OPCODE 0x13 /* EERPOM erase/write enable */
1308 #define EEPROM_EWDS_OPCODE 0x10 /* EERPOM erast/write disable */
1310 /* EEPROM Word Offsets */
1311 #define EEPROM_COMPAT 0x0003
1312 #define EEPROM_ID_LED_SETTINGS 0x0004
1313 #define EEPROM_INIT_CONTROL1_REG 0x000A
1314 #define EEPROM_INIT_CONTROL2_REG 0x000F
1315 #define EEPROM_FLASH_VERSION 0x0032
1316 #define EEPROM_CHECKSUM_REG 0x003F
1318 /* Word definitions for ID LED Settings */
1319 #define ID_LED_RESERVED_0000 0x0000
1320 #define ID_LED_RESERVED_FFFF 0xFFFF
1321 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
1322 (ID_LED_OFF1_OFF2 << 8) | \
1323 (ID_LED_DEF1_DEF2 << 4) | \
1325 #define ID_LED_DEF1_DEF2 0x1
1326 #define ID_LED_DEF1_ON2 0x2
1327 #define ID_LED_DEF1_OFF2 0x3
1328 #define ID_LED_ON1_DEF2 0x4
1329 #define ID_LED_ON1_ON2 0x5
1330 #define ID_LED_ON1_OFF2 0x6
1331 #define ID_LED_OFF1_DEF2 0x7
1332 #define ID_LED_OFF1_ON2 0x8
1333 #define ID_LED_OFF1_OFF2 0x9
1335 /* Mask bits for fields in Word 0x03 of the EEPROM */
1336 #define EEPROM_COMPAT_SERVER 0x0400
1337 #define EEPROM_COMPAT_CLIENT 0x0200
1339 /* Mask bits for fields in Word 0x0a of the EEPROM */
1340 #define EEPROM_WORD0A_ILOS 0x0010
1341 #define EEPROM_WORD0A_SWDPIO 0x01E0
1342 #define EEPROM_WORD0A_LRST 0x0200
1343 #define EEPROM_WORD0A_FD 0x0400
1344 #define EEPROM_WORD0A_66MHZ 0x0800
1346 /* Mask bits for fields in Word 0x0f of the EEPROM */
1347 #define EEPROM_WORD0F_PAUSE_MASK 0x3000
1348 #define EEPROM_WORD0F_PAUSE 0x1000
1349 #define EEPROM_WORD0F_ASM_DIR 0x2000
1350 #define EEPROM_WORD0F_ANE 0x0800
1351 #define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
1353 /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
1354 #define EEPROM_SUM 0xBABA
1356 /* EEPROM Map defines (WORD OFFSETS)*/
1357 #define EEPROM_NODE_ADDRESS_BYTE_0 0
1358 #define EEPROM_PBA_BYTE_1 8
1360 /* EEPROM Map Sizes (Byte Counts) */
1363 /* Collision related configuration parameters */
1364 #define E1000_COLLISION_THRESHOLD 16
1365 #define E1000_CT_SHIFT 4
1366 #define E1000_COLLISION_DISTANCE 64
1367 #define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
1368 #define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
1369 #define E1000_GB_HDX_COLLISION_DISTANCE 512
1370 #define E1000_COLD_SHIFT 12
1372 /* The number of Transmit and Receive Descriptors must be a multiple of 8 */
1373 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
1374 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
1376 /* Default values for the transmit IPG register */
1377 #define DEFAULT_82542_TIPG_IPGT 10
1378 #define DEFAULT_82543_TIPG_IPGT_FIBER 9
1379 #define DEFAULT_82543_TIPG_IPGT_COPPER 8
1381 #define E1000_TIPG_IPGT_MASK 0x000003FF
1382 #define E1000_TIPG_IPGR1_MASK 0x000FFC00
1383 #define E1000_TIPG_IPGR2_MASK 0x3FF00000
1385 #define DEFAULT_82542_TIPG_IPGR1 2
1386 #define DEFAULT_82543_TIPG_IPGR1 8
1387 #define E1000_TIPG_IPGR1_SHIFT 10
1389 #define DEFAULT_82542_TIPG_IPGR2 10
1390 #define DEFAULT_82543_TIPG_IPGR2 6
1391 #define E1000_TIPG_IPGR2_SHIFT 20
1393 #define E1000_TXDMAC_DPP 0x00000001
1395 /* Adaptive IFS defines */
1396 #define TX_THRESHOLD_START 8
1397 #define TX_THRESHOLD_INCREMENT 10
1398 #define TX_THRESHOLD_DECREMENT 1
1399 #define TX_THRESHOLD_STOP 190
1400 #define TX_THRESHOLD_DISABLE 0
1401 #define TX_THRESHOLD_TIMER_MS 10000
1402 #define MIN_NUM_XMITS 1000
1409 #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
1410 #define E1000_PBA_24K 0x0018
1411 #define E1000_PBA_40K 0x0028
1412 #define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
1414 /* Flow Control Constants */
1415 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
1416 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
1417 #define FLOW_CONTROL_TYPE 0x8808
1419 /* The historical defaults for the flow control values are given below. */
1420 #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
1421 #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
1422 #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
1424 /* PCIX Config space */
1425 #define PCIX_COMMAND_REGISTER 0xE6
1426 #define PCIX_STATUS_REGISTER_LO 0xE8
1427 #define PCIX_STATUS_REGISTER_HI 0xEA
1429 #define PCIX_COMMAND_MMRBC_MASK 0x000C
1430 #define PCIX_COMMAND_MMRBC_SHIFT 0x2
1431 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060
1432 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
1435 /* The number of bits that we need to shift right to move the "pause"
1436 * bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field
1437 * in the TXCW register
1439 #define PAUSE_SHIFT 5
1441 /* The number of bits that we need to shift left to move the "SWDPIO"
1442 * bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field
1443 * in the CTRL register
1445 #define SWDPIO_SHIFT 17
1447 /* The number of bits that we need to shift left to move the "SWDPIO_EXT"
1448 * bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The
1449 * Extended CTRL register.
1450 * in the CTRL register
1452 #define SWDPIO__EXT_SHIFT 4
1454 /* The number of bits that we need to shift left to move the "ILOS"
1455 * bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field
1456 * in the CTRL register
1458 #define ILOS_SHIFT 3
1461 #define RECEIVE_BUFFER_ALIGN_SIZE (256)
1463 /* The number of milliseconds we wait for auto-negotiation to complete */
1464 #define LINK_UP_TIMEOUT 500
1466 #define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
1468 /* The carrier extension symbol, as received by the NIC. */
1469 #define CARRIER_EXTENSION 0x0F
1471 /* TBI_ACCEPT macro definition:
1473 * This macro requires:
1474 * adapter = a pointer to struct em_hw
1475 * status = the 8 bit status field of the RX descriptor with EOP set
1476 * error = the 8 bit error field of the RX descriptor with EOP set
1477 * length = the sum of all the length fields of the RX descriptors that
1478 * make up the current frame
1479 * last_byte = the last byte of the frame DMAed by the hardware
1480 * max_frame_length = the maximum frame length we want to accept.
1481 * min_frame_length = the minimum frame length we want to accept.
1483 * This macro is a conditional that should be used in the interrupt
1484 * handler's Rx processing routine when RxErrors have been detected.
1489 * accept_frame = TRUE;
1490 * em_tbi_adjust_stats(adapter, MacAddress);
1493 * accept_frame = FALSE;
1498 #define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
1499 ((adapter)->tbi_compatibility_on && \
1500 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
1501 ((last_byte) == CARRIER_EXTENSION) && \
1502 (((status) & E1000_RXD_STAT_VP) ? \
1503 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
1504 ((length) <= ((adapter)->max_frame_size + 1))) : \
1505 (((length) > (adapter)->min_frame_size) && \
1506 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
1509 /* Structures, enums, and macros for the PHY */
1511 /* Bit definitions for the Management Data IO (MDIO) and Management Data
1512 * Clock (MDC) pins in the Device Control Register.
1514 #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
1515 #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
1516 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
1517 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
1518 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
1519 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
1520 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
1521 #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
1523 /* PHY 1000 MII Register/Bit Definitions */
1524 /* PHY Registers defined by IEEE */
1525 #define PHY_CTRL 0x00 /* Control Register */
1526 #define PHY_STATUS 0x01 /* Status Regiser */
1527 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
1528 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
1529 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
1530 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
1531 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
1532 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
1533 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
1534 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1535 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1536 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
1538 /* M88E1000 Specific Registers */
1539 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
1540 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
1541 #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
1542 #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
1543 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
1544 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
1546 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1548 /* PHY Control Register */
1549 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
1550 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
1551 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
1552 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
1553 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
1554 #define MII_CR_POWER_DOWN 0x0800 /* Power down */
1555 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
1556 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
1557 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
1558 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
1560 /* PHY Status Register */
1561 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
1562 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
1563 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
1564 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
1565 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
1566 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
1567 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
1568 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
1569 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
1570 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
1571 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
1572 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
1573 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
1574 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
1575 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
1577 /* Autoneg Advertisement Register */
1578 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
1579 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
1580 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
1581 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
1582 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
1583 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
1584 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
1585 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
1586 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
1587 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
1589 /* Link Partner Ability Register (Base Page) */
1590 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
1591 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
1592 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
1593 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
1594 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
1595 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
1596 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
1597 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
1598 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
1599 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
1600 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
1602 /* Autoneg Expansion Register */
1603 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
1604 #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
1605 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
1606 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
1607 #define NWAY_ER_PAR_DETECT_FAULT 0x0100 /* LP is 100TX Full Duplex Capable */
1609 /* Next Page TX Register */
1610 #define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
1611 #define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
1614 #define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
1615 * 0 = cannot comply with msg
1617 #define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
1618 #define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
1619 * 0 = sending last NP
1622 /* Link Partner Next Page Register */
1623 #define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
1624 #define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
1627 #define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
1628 * 0 = cannot comply with msg
1630 #define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
1631 #define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
1632 #define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
1633 * 0 = sending last NP
1636 /* 1000BASE-T Control Register */
1637 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
1638 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
1639 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
1640 #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
1642 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
1643 /* 0=Configure PHY as Slave */
1644 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
1645 /* 0=Automatic Master/Slave config */
1646 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
1647 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
1648 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
1649 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
1650 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
1652 /* 1000BASE-T Status Register */
1653 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
1654 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
1655 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
1656 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
1657 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
1658 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
1659 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
1660 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
1661 #define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
1662 #define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
1664 /* Extended Status Register */
1665 #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
1666 #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
1667 #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
1668 #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
1670 #define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
1671 #define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
1673 #define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
1674 /* (0=enable, 1=disable) */
1676 /* M88E1000 PHY Specific Control Register */
1677 #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
1678 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
1679 #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
1680 #define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
1683 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
1684 /* Manual MDI configuration */
1685 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
1686 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
1687 * 100BASE-TX/10BASE-T:
1690 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
1693 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
1694 /* 1=Enable Extended 10BASE-T distance
1695 * (Lower 10BASE-T RX Threshold)
1696 * 0=Normal 10BASE-T RX Threshold */
1697 #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
1698 /* 1=5-Bit interface in 100BASE-TX
1699 * 0=MII interface in 100BASE-TX */
1700 #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
1701 #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
1702 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
1704 #define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
1705 #define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
1706 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
1708 /* M88E1000 PHY Specific Status Register */
1709 #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
1710 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
1711 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
1712 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
1713 * 3=110-140M;4=>140M */
1714 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
1715 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
1716 #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
1717 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
1718 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
1719 #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
1720 #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
1721 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
1723 #define M88E1000_PSSR_REV_POLARITY_SHIFT 1
1724 #define M88E1000_PSSR_MDIX_SHIFT 6
1725 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1727 /* M88E1000 Extended PHY Specific Control Register */
1728 #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
1729 #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
1730 * Will assert lost lock and bring
1731 * link down if idle not seen
1732 * within 1ms in 1000BASE-T
1734 /* Number of times we will attempt to autonegotiate before downshifting if we
1736 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1737 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
1738 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
1739 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
1740 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
1741 /* Number of times we will attempt to autonegotiate before downshifting if we
1743 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
1744 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
1745 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
1746 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
1747 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
1748 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
1749 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
1750 #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
1752 /* Bit definitions for valid PHY IDs. */
1753 #define M88E1000_E_PHY_ID 0x01410C50
1754 #define M88E1000_I_PHY_ID 0x01410C30
1755 #define M88E1011_I_PHY_ID 0x01410C20
1756 #define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
1757 #define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
1759 /* Miscellaneous PHY bit definitions. */
1760 #define PHY_PREAMBLE 0xFFFFFFFF
1761 #define PHY_SOF 0x01
1762 #define PHY_OP_READ 0x02
1763 #define PHY_OP_WRITE 0x01
1764 #define PHY_TURNAROUND 0x02
1765 #define PHY_PREAMBLE_SIZE 32
1766 #define MII_CR_SPEED_1000 0x0040
1767 #define MII_CR_SPEED_100 0x2000
1768 #define MII_CR_SPEED_10 0x0000
1769 #define E1000_PHY_ADDRESS 0x01
1770 #define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
1771 #define PHY_FORCE_TIME 20 /* 2.0 Seconds */
1772 #define PHY_REVISION_MASK 0xFFFFFFF0
1773 #define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
1774 #define REG4_SPEED_MASK 0x01E0
1775 #define REG9_SPEED_MASK 0x0300
1776 #define ADVERTISE_10_HALF 0x0001
1777 #define ADVERTISE_10_FULL 0x0002
1778 #define ADVERTISE_100_HALF 0x0004
1779 #define ADVERTISE_100_FULL 0x0008
1780 #define ADVERTISE_1000_HALF 0x0010
1781 #define ADVERTISE_1000_FULL 0x0020
1782 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
1784 #endif /* _EM_HW_H_ */