1 /* $NetBSD: midway.c,v 1.30 1997/09/29 17:40:38 chuck Exp $ */
2 /* (sync'd to midway.c 1.68) */
5 * Copyright (c) 1996 Charles D. Cranor and Washington University.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Charles D. Cranor and
19 * Washington University.
20 * 4. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
39 * m i d w a y . c e n i 1 5 5 d r i v e r
41 * author: Chuck Cranor <chuck@ccrc.wustl.edu>
42 * started: spring, 1996 (written from scratch).
44 * notes from the author:
45 * Extra special thanks go to Werner Almesberger, EPFL LRC. Werner's
46 * ENI driver was especially useful in figuring out how this card works.
47 * I would also like to thank Werner for promptly answering email and being
52 #define EN_DDBHOOK 1 /* compile in ddb functions */
55 * Note on EN_ENIDMAFIX: the byte aligner on the ENI version of the card
56 * appears to be broken. it works just fine if there is no load... however
57 * when the card is loaded the data get corrupted. to see this, one only
58 * has to use "telnet" over ATM. do the following command in "telnet":
59 * cat /usr/share/misc/termcap
60 * "telnet" seems to generate lots of 1023 byte mbufs (which make great
61 * use of the byte aligner). watch "netstat -s" for checksum errors.
63 * I further tested this by adding a function that compared the transmit
64 * data on the card's SRAM with the data in the mbuf chain _after_ the
65 * "transmit DMA complete" interrupt. using the "telnet" test I got data
66 * mismatches where the byte-aligned data should have been. using ddb
67 * and en_dumpmem() I verified that the DTQs fed into the card were
68 * absolutely correct. thus, we are forced to concluded that the ENI
69 * hardware is buggy. note that the Adaptec version of the card works
70 * just fine with byte DMA.
72 * bottom line: we set EN_ENIDMAFIX to 1 to avoid byte DMAs on the ENI
76 #if defined(DIAGNOSTIC) && !defined(EN_DIAG)
77 #define EN_DIAG /* link in with master DIAG option */
80 #define EN_COUNT(X) (X)++
88 * This macro removes almost all the EN_DEBUG conditionals in the code that make
89 * to code a good deal less readable.
91 #define DBG(SC, FL, PRINT) do { \
92 if ((SC)->debug & DBG_##FL) { \
93 device_printf((SC)->dev, "%s: "#FL": ", __func__); \
100 DBG_INIT = 0x0001, /* debug attach/detach */
101 DBG_TX = 0x0002, /* debug transmitting */
102 DBG_SERV = 0x0004, /* debug service interrupts */
103 DBG_IOCTL = 0x0008, /* debug ioctls */
104 DBG_VC = 0x0010, /* debug VC handling */
105 DBG_INTR = 0x0020, /* debug interrupts */
106 DBG_DMA = 0x0040, /* debug DMA probing */
107 DBG_IPACKETS = 0x0080, /* print input packets */
108 DBG_REG = 0x0100, /* print all register access */
109 DBG_LOCK = 0x0200, /* debug locking */
114 #define DBG(SC, FL, PRINT) do { } while (0)
116 #endif /* EN_DEBUG */
118 #include "opt_inet.h"
119 #include "opt_natm.h"
127 #include <sys/param.h>
128 #include <sys/systm.h>
129 #include <sys/queue.h>
130 #include <sys/sockio.h>
131 #include <sys/socket.h>
132 #include <sys/mbuf.h>
133 #include <sys/endian.h>
134 #include <sys/stdint.h>
135 #include <sys/lock.h>
136 #include <sys/mutex.h>
137 #include <sys/condvar.h>
141 #include <net/if_media.h>
142 #include <net/if_atm.h>
144 #if defined(NATM) || defined(INET) || defined(INET6)
145 #include <netinet/in.h>
146 #if defined(INET) || defined(INET6)
147 #include <netinet/if_atm.h>
152 #include <netnatm/natm.h>
156 #include <machine/bus.h>
157 #include <sys/rman.h>
158 #include <sys/module.h>
159 #include <sys/sysctl.h>
160 #include <sys/malloc.h>
161 #include <machine/resource.h>
162 #include <dev/utopia/utopia.h>
163 #include <dev/en/midwayreg.h>
164 #include <dev/en/midwayvar.h>
172 #define EN_TXHIWAT (64 * 1024) /* max 64 KB waiting to be DMAd out */
175 SYSCTL_DECL(_hw_atm);
180 * The plan is indexed by the number of words to transfer.
181 * The maximum index is 15 for 60 words.
184 uint8_t bcode; /* code */
185 uint8_t divshift; /* byte divisor */
188 static const struct en_dmatab en_dmaplan[] = {
189 { 0, 0 }, /* 0 */ { MIDDMA_WORD, 2}, /* 1 */
190 { MIDDMA_2WORD, 3}, /* 2 */ { MIDDMA_WORD, 2}, /* 3 */
191 { MIDDMA_4WORD, 4}, /* 4 */ { MIDDMA_WORD, 2}, /* 5 */
192 { MIDDMA_2WORD, 3}, /* 6 */ { MIDDMA_WORD, 2}, /* 7 */
193 { MIDDMA_8WORD, 5}, /* 8 */ { MIDDMA_WORD, 2}, /* 9 */
194 { MIDDMA_2WORD, 3}, /* 10 */ { MIDDMA_WORD, 2}, /* 11 */
195 { MIDDMA_4WORD, 4}, /* 12 */ { MIDDMA_WORD, 2}, /* 13 */
196 { MIDDMA_2WORD, 3}, /* 14 */ { MIDDMA_WORD, 2}, /* 15 */
197 { MIDDMA_16WORD,6}, /* 16 */
204 int en_dump(int unit, int level);
205 int en_dumpmem(int,int,int);
207 static void en_close_finish(struct en_softc *sc, struct en_vcc *vc);
209 #define EN_LOCK(SC) do { \
210 DBG(SC, LOCK, ("ENLOCK %d\n", __LINE__)); \
211 mtx_lock(&sc->en_mtx); \
213 #define EN_UNLOCK(SC) do { \
214 DBG(SC, LOCK, ("ENUNLOCK %d\n", __LINE__)); \
215 mtx_unlock(&sc->en_mtx); \
217 #define EN_CHECKLOCK(sc) mtx_assert(&sc->en_mtx, MA_OWNED)
220 * While a transmit mbuf is waiting to get transmit DMA resources we
221 * need to keep some information with it. We don't want to allocate
222 * additional memory for this so we stuff it into free fields in the
223 * mbuf packet header. Neither the checksum fields nor the rcvif field are used
226 #define TX_AAL5 0x1 /* transmit AAL5 PDU */
227 #define TX_HAS_TBD 0x2 /* TBD did fit into mbuf */
228 #define TX_HAS_PAD 0x4 /* padding did fit into mbuf */
229 #define TX_HAS_PDU 0x8 /* PDU trailer did fit into mbuf */
231 #define MBUF_SET_TX(M, VCI, FLAGS, DATALEN, PAD, MAP) do { \
232 (M)->m_pkthdr.csum_data = (VCI) | ((FLAGS) << MID_VCI_BITS); \
233 (M)->m_pkthdr.csum_flags = ((DATALEN) & 0xffff) | \
234 ((PAD & 0x3f) << 16); \
235 (M)->m_pkthdr.rcvif = (void *)(MAP); \
238 #define MBUF_GET_TX(M, VCI, FLAGS, DATALEN, PAD, MAP) do { \
239 (VCI) = (M)->m_pkthdr.csum_data & ((1 << MID_VCI_BITS) - 1); \
240 (FLAGS) = ((M)->m_pkthdr.csum_data >> MID_VCI_BITS) & 0xf; \
241 (DATALEN) = (M)->m_pkthdr.csum_flags & 0xffff; \
242 (PAD) = ((M)->m_pkthdr.csum_flags >> 16) & 0x3f; \
243 (MAP) = (void *)((M)->m_pkthdr.rcvif); \
247 #define EN_WRAPADD(START, STOP, CUR, VAL) do { \
248 (CUR) = (CUR) + (VAL); \
249 if ((CUR) >= (STOP)) \
250 (CUR) = (START) + ((CUR) - (STOP)); \
253 #define WORD_IDX(START, X) (((X) - (START)) / sizeof(uint32_t))
255 #define SETQ_END(SC, VAL) ((SC)->is_adaptec ? \
256 ((VAL) | (MID_DMA_END >> 4)) : \
257 ((VAL) | (MID_DMA_END)))
260 * The dtq and drq members are set for each END entry in the corresponding
261 * card queue entry. It is used to find out, when a buffer has been
262 * finished DMAing and can be freed.
264 * We store sc->dtq and sc->drq data in the following format...
265 * the 0x80000 ensures we != 0
267 #define EN_DQ_MK(SLOT, LEN) (((SLOT) << 20) | (LEN) | (0x80000))
268 #define EN_DQ_SLOT(X) ((X) >> 20)
269 #define EN_DQ_LEN(X) ((X) & 0x3ffff)
274 static uma_zone_t en_vcc_zone;
276 /***********************************************************************/
279 * en_read{x}: read a word from the card. These are the only functions
280 * that read from the card.
282 static __inline uint32_t
283 en_readx(struct en_softc *sc, uint32_t r)
288 if (r > MID_MAXOFF || (r % 4))
289 panic("en_read out of range, r=0x%x", r);
291 v = bus_space_read_4(sc->en_memt, sc->en_base, r);
295 static __inline uint32_t
296 en_read(struct en_softc *sc, uint32_t r)
301 if (r > MID_MAXOFF || (r % 4))
302 panic("en_read out of range, r=0x%x", r);
304 v = bus_space_read_4(sc->en_memt, sc->en_base, r);
305 DBG(sc, REG, ("en_read(%#x) -> %08x", r, v));
310 * en_write: write a word to the card. This is the only function that
311 * writes to the card.
314 en_write(struct en_softc *sc, uint32_t r, uint32_t v)
317 if (r > MID_MAXOFF || (r % 4))
318 panic("en_write out of range, r=0x%x", r);
320 DBG(sc, REG, ("en_write(%#x) <- %08x", r, v));
321 bus_space_write_4(sc->en_memt, sc->en_base, r, v);
325 * en_k2sz: convert KBytes to a size parameter (a log2)
338 case 128: return (7);
344 #define en_log2(X) en_k2sz(X)
347 * en_b2sz: convert a DMA burst code to its byte size
353 case MIDDMA_WORD: return (1*4);
355 case MIDDMA_2WORD: return (2*4);
357 case MIDDMA_4WORD: return (4*4);
359 case MIDDMA_8WORD: return (8*4);
360 case MIDDMA_16WMAYBE:
361 case MIDDMA_16WORD: return (16*4);
369 * en_sz2b: convert a burst size (bytes) to DMA burst code
375 case 1*4: return (MIDDMA_WORD);
376 case 2*4: return (MIDDMA_2WORD);
377 case 4*4: return (MIDDMA_4WORD);
378 case 8*4: return (MIDDMA_8WORD);
379 case 16*4: return (MIDDMA_16WORD);
391 en_dump_packet(struct en_softc *sc, struct mbuf *m)
393 int plen = m->m_pkthdr.len;
399 device_printf(sc->dev, "packet len=%d", plen);
402 ptr = mtod(m, u_char *);
403 for (len = 0; len < m->m_len; len++, pos++, ptr++) {
408 printf(" %02x", *ptr);
414 printf("sum of m_len=%u\n", totlen);
418 /*********************************************************************/
424 * Map constructor for a MAP.
426 * This is called each time when a map is allocated
427 * from the pool and about to be returned to the user. Here we actually
428 * allocate the map if there isn't one. The problem is that we may fail
429 * to allocate the DMA map yet have no means to signal this error. Therefor
430 * when allocating a map, the call must check that there is a map. An
431 * additional problem is, that i386 maps will be NULL, yet are ok and must
432 * be freed so let's use a flag to signal allocation.
434 * Caveat: we have no way to know that we are called from an interrupt context
435 * here. We rely on the fact, that bus_dmamap_create uses M_NOWAIT in all
438 * LOCK: any, not needed
441 en_map_ctor(void *mem, int size, void *arg, int flags)
443 struct en_softc *sc = arg;
444 struct en_map *map = mem;
447 err = bus_dmamap_create(sc->txtag, 0, &map->map);
449 device_printf(sc->dev, "cannot create DMA map %d\n", err);
452 map->flags = ENMAP_ALLOC;
460 * Called when a map is disposed into the zone. If the map is loaded, unload
463 * LOCK: any, not needed
466 en_map_dtor(void *mem, int size, void *arg)
468 struct en_map *map = mem;
470 if (map->flags & ENMAP_LOADED) {
471 bus_dmamap_unload(map->sc->txtag, map->map);
472 map->flags &= ~ENMAP_LOADED;
479 * This is called each time a map is returned from the zone to the system.
480 * Get rid of the dmamap here.
482 * LOCK: any, not needed
485 en_map_fini(void *mem, int size)
487 struct en_map *map = mem;
489 bus_dmamap_destroy(map->sc->txtag, map->map);
492 /*********************************************************************/
498 * Argument structure to load a transmit DMA map
504 u_int chan; /* transmit channel */
505 u_int datalen; /* length of user data */
507 u_int wait; /* return: out of resources */
511 * TX DMA map loader helper. This function is the callback when the map
512 * is loaded. It should fill the DMA segment descriptors into the hardware.
514 * LOCK: locked, needed
517 en_txdma_load(void *uarg, bus_dma_segment_t *segs, int nseg, bus_size_t mapsize,
520 struct txarg *tx = uarg;
521 struct en_softc *sc = tx->sc;
522 struct en_txslot *slot = &sc->txslot[tx->chan];
523 uint32_t cur; /* on-card buffer position (bytes offset) */
524 uint32_t dtq; /* on-card queue position (byte offset) */
525 uint32_t last_dtq; /* last DTQ we have written */
527 u_int free; /* free queue entries on card */
528 u_int needalign, cnt;
529 bus_size_t rest; /* remaining bytes in current segment */
531 bus_dma_segment_t *s;
532 uint32_t count, bcode;
542 last_dtq = 0; /* make gcc happy */
545 * Local macro to add an entry to the transmit DMA area. If there
546 * are no entries left, return. Save the byte offset of the entry
547 * in last_dtq for later use.
549 #define PUT_DTQ_ENTRY(ENI, BCODE, COUNT, ADDR) \
551 EN_COUNT(sc->stats.txdtqout); \
556 en_write(sc, dtq + 0, (ENI || !sc->is_adaptec) ? \
557 MID_MK_TXQ_ENI(COUNT, tx->chan, 0, BCODE) : \
558 MID_MK_TXQ_ADP(COUNT, tx->chan, 0, BCODE)); \
559 en_write(sc, dtq + 4, ADDR); \
561 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, dtq, 8); \
565 * Local macro to generate a DMA entry to DMA cnt bytes. Updates
566 * the current buffer byte offset accordingly.
568 #define DO_DTQ(TYPE) do { \
570 EN_WRAPADD(slot->start, slot->stop, cur, cnt); \
571 DBG(sc, TX, ("tx%d: "TYPE" %u bytes, %ju left, cur %#x", \
572 tx->chan, cnt, (uintmax_t)rest, cur)); \
574 PUT_DTQ_ENTRY(1, bcode, count, addr); \
579 if (!(tx->flags & TX_HAS_TBD)) {
581 * Prepend the TBD - it did not fit into the first mbuf
583 tmp = MID_TBD_MK1((tx->flags & TX_AAL5) ?
584 MID_TBD_AAL5 : MID_TBD_NOAAL5,
585 sc->vccs[tx->vci]->txspeed,
586 tx->m->m_pkthdr.len / MID_ATMDATASZ);
587 en_write(sc, cur, tmp);
588 EN_WRAPADD(slot->start, slot->stop, cur, 4);
590 tmp = MID_TBD_MK2(tx->vci, 0, 0);
591 en_write(sc, cur, tmp);
592 EN_WRAPADD(slot->start, slot->stop, cur, 4);
594 /* update DMA address */
595 PUT_DTQ_ENTRY(0, MIDDMA_JK, WORD_IDX(slot->start, cur), 0);
598 for (i = 0, s = segs; i < nseg; i++, s++) {
602 if (sc->is_adaptec) {
603 /* adaptec card - simple */
605 /* advance the on-card buffer pointer */
606 EN_WRAPADD(slot->start, slot->stop, cur, rest);
607 DBG(sc, TX, ("tx%d: adp %ju bytes %#jx (cur now 0x%x)",
608 tx->chan, (uintmax_t)rest, (uintmax_t)addr, cur));
610 PUT_DTQ_ENTRY(0, 0, rest, addr);
616 * do we need to do a DMA op to align to the maximum
617 * burst? Note, that we are alway 32-bit aligned.
620 (needalign = (addr & sc->bestburstmask)) != 0) {
621 /* compute number of bytes, words and code */
622 cnt = sc->bestburstlen - needalign;
625 count = cnt / sizeof(uint32_t);
626 if (sc->noalbursts) {
629 bcode = en_dmaplan[count].bcode;
630 count = cnt >> en_dmaplan[count].divshift;
635 /* do we need to do a max-sized burst? */
636 if (rest >= sc->bestburstlen) {
637 count = rest >> sc->bestburstshift;
638 cnt = count << sc->bestburstshift;
639 bcode = sc->bestburstcode;
643 /* do we need to do a cleanup burst? */
646 count = rest / sizeof(uint32_t);
647 if (sc->noalbursts) {
650 bcode = en_dmaplan[count].bcode;
651 count = cnt >> en_dmaplan[count].divshift;
657 KASSERT (tx->flags & TX_HAS_PAD, ("PDU not padded"));
659 if ((tx->flags & TX_AAL5) && !(tx->flags & TX_HAS_PDU)) {
661 * Append the AAL5 PDU trailer
663 tmp = MID_PDU_MK1(0, 0, tx->datalen);
664 en_write(sc, cur, tmp);
665 EN_WRAPADD(slot->start, slot->stop, cur, 4);
667 en_write(sc, cur, 0);
668 EN_WRAPADD(slot->start, slot->stop, cur, 4);
670 /* update DMA address */
671 PUT_DTQ_ENTRY(0, MIDDMA_JK, WORD_IDX(slot->start, cur), 0);
674 /* record the end for the interrupt routine */
675 sc->dtq[MID_DTQ_A2REG(last_dtq)] =
676 EN_DQ_MK(tx->chan, tx->m->m_pkthdr.len);
678 /* set the end flag in the last descriptor */
679 en_write(sc, last_dtq + 0, SETQ_END(sc, en_read(sc, last_dtq + 0)));
690 en_write(sc, MID_DMA_WRTX, MID_DTQ_A2REG(sc->dtq_us));
694 * en_txdma: start transmit DMA on the given channel, if possible
696 * This is called from two places: when we got new packets from the upper
697 * layer or when we found that buffer space has freed up during interrupt
700 * LOCK: locked, needed
703 en_txdma(struct en_softc *sc, struct en_txslot *slot)
711 DBG(sc, TX, ("tx%td: starting ...", slot - sc->txslot));
713 bzero(&tx, sizeof(tx));
714 tx.chan = slot - sc->txslot;
718 * get an mbuf waiting for DMA
720 _IF_DEQUEUE(&slot->q, tx.m);
722 DBG(sc, TX, ("tx%td: ...done!", slot - sc->txslot));
725 MBUF_GET_TX(tx.m, tx.vci, tx.flags, tx.datalen, pad, map);
728 * note: don't use the entire buffer space. if WRTX becomes equal
729 * to RDTX, the transmitter stops assuming the buffer is empty! --kjc
731 if (tx.m->m_pkthdr.len >= slot->bfree) {
732 EN_COUNT(sc->stats.txoutspace);
733 DBG(sc, TX, ("tx%td: out of transmit space", slot - sc->txslot));
738 if (!(tx.flags & TX_HAS_PAD)) {
740 /* Append the padding buffer */
741 (void)m_length(tx.m, &lastm);
742 lastm->m_next = sc->padbuf;
743 sc->padbuf->m_len = pad;
745 tx.flags |= TX_HAS_PAD;
749 * Try to load that map
751 error = bus_dmamap_load_mbuf(sc->txtag, map->map, tx.m,
752 en_txdma_load, &tx, BUS_DMA_NOWAIT);
755 lastm->m_next = NULL;
758 device_printf(sc->dev, "loading TX map failed %d\n",
762 map->flags |= ENMAP_LOADED;
764 /* probably not enough space */
765 bus_dmamap_unload(map->sc->txtag, map->map);
766 map->flags &= ~ENMAP_LOADED;
769 DBG(sc, TX, ("tx%td: out of transmit DTQs", slot - sc->txslot));
773 EN_COUNT(sc->stats.launch);
774 sc->ifp->if_opackets++;
776 sc->vccs[tx.vci]->opackets++;
777 sc->vccs[tx.vci]->obytes += tx.datalen;
780 if (bpf_peers_present(sc->ifp->if_bpf)) {
782 * adjust the top of the mbuf to skip the TBD if present
783 * before passing the packet to bpf.
784 * Also remove padding and the PDU trailer. Assume both of
785 * them to be in the same mbuf. pktlen, m_len and m_data
786 * are not needed anymore so we can change them.
788 if (tx.flags & TX_HAS_TBD) {
789 tx.m->m_data += MID_TBD_SIZE;
790 tx.m->m_len -= MID_TBD_SIZE;
792 tx.m->m_pkthdr.len = m_length(tx.m, &lastm);
793 if (tx.m->m_pkthdr.len > tx.datalen) {
794 lastm->m_len -= tx.m->m_pkthdr.len - tx.datalen;
795 tx.m->m_pkthdr.len = tx.datalen;
798 bpf_mtap(sc->ifp->if_bpf, tx.m);
803 * do some housekeeping and get the next packet
805 slot->bfree -= tx.m->m_pkthdr.len;
806 _IF_ENQUEUE(&slot->indma, tx.m);
811 * error handling. This is jumped to when we just want to drop
812 * the packet. Must be unlocked here.
816 uma_zfree(sc->map_zone, map);
818 slot->mbsize -= tx.m->m_pkthdr.len;
825 _IF_PREPEND(&slot->q, tx.m);
829 * Create a copy of a single mbuf. It can have either internal or
830 * external data, it may have a packet header. External data is really
831 * copied, so the new buffer is writeable.
833 * LOCK: any, not needed
836 copy_mbuf(struct mbuf *m)
840 MGET(new, M_WAIT, MT_DATA);
842 if (m->m_flags & M_PKTHDR) {
843 M_MOVE_PKTHDR(new, m);
844 if (m->m_len > MHLEN)
851 bcopy(m->m_data, new->m_data, m->m_len);
852 new->m_len = m->m_len;
853 new->m_flags &= ~M_RDONLY;
859 * This function is called when we have an ENI adapter. It fixes the
860 * mbuf chain, so that all addresses and lengths are 4 byte aligned.
861 * The overall length is already padded to multiple of cells plus the
862 * TBD so this must always succeed. The routine can fail, when it
863 * needs to copy an mbuf (this may happen if an mbuf is readonly).
865 * We assume here, that aligning the virtual addresses to 4 bytes also
866 * aligns the physical addresses.
868 * LOCK: locked, needed
871 en_fix_mchain(struct en_softc *sc, struct mbuf *m0, u_int *pad)
873 struct mbuf **prev = &m0;
880 d = mtod(m, u_char *);
881 if ((off = (uintptr_t)d % sizeof(uint32_t)) != 0) {
882 EN_COUNT(sc->stats.mfixaddr);
884 bcopy(d, d - off, m->m_len);
887 if ((new = copy_mbuf(m)) == NULL) {
888 EN_COUNT(sc->stats.mfixfail);
892 new->m_next = m_free(m);
897 if ((off = m->m_len % sizeof(uint32_t)) != 0) {
898 EN_COUNT(sc->stats.mfixlen);
899 if (!M_WRITABLE(m)) {
900 if ((new = copy_mbuf(m)) == NULL) {
901 EN_COUNT(sc->stats.mfixfail);
905 new->m_next = m_free(m);
908 d = mtod(m, u_char *) + m->m_len;
911 while (m->m_next && m->m_next->m_len == 0)
912 m->m_next = m_free(m->m_next);
914 if (m->m_next == NULL) {
916 KASSERT(*pad > 0, ("no padding space"));
919 *d++ = *mtod(m->m_next, u_char *);
936 * en_start: start transmitting the next packet that needs to go out
937 * if there is one. We take off all packets from the interface's queue and
938 * put them into the channels queue.
940 * Here we also prepend the transmit packet descriptor and append the padding
941 * and (for aal5) the PDU trailer. This is different from the original driver:
942 * we assume, that allocating one or two additional mbufs is actually cheaper
943 * than all this algorithmic fiddling we would need otherwise.
945 * While the packet is on the channels wait queue we use the csum_* fields
946 * in the packet header to hold the original datalen, the AAL5 flag and the
947 * VCI. The packet length field in the header holds the needed buffer space.
948 * This may actually be more than the length of the current mbuf chain (when
949 * one or more of TBD, padding and PDU do not fit).
951 * LOCK: unlocked, needed
954 en_start(struct ifnet *ifp)
956 struct en_softc *sc = (struct en_softc *)ifp->if_softc;
957 struct mbuf *m, *lastm;
958 struct atm_pseudohdr *ap;
959 u_int pad; /* 0-bytes to pad at PDU end */
960 u_int datalen; /* length of user data */
961 u_int vci; /* the VCI we are transmitting on */
967 struct en_txslot *tx;
970 IF_DEQUEUE(&ifp->if_snd, m);
976 ap = mtod(m, struct atm_pseudohdr *);
977 vci = ATM_PH_VCI(ap);
979 if (ATM_PH_VPI(ap) != 0 || vci >= MID_N_VC ||
980 (vc = sc->vccs[vci]) == NULL ||
981 (vc->vflags & VCC_CLOSE_RX)) {
982 DBG(sc, TX, ("output vpi=%u, vci=%u -- drop",
983 ATM_PH_VPI(ap), vci));
987 if (vc->vcc.aal == ATMIO_AAL_5)
989 m_adj(m, sizeof(struct atm_pseudohdr));
992 * (re-)calculate size of packet (in bytes)
994 m->m_pkthdr.len = datalen = m_length(m, &lastm);
997 * computing how much padding we need on the end of the mbuf,
998 * then see if we can put the TBD at the front of the mbuf
999 * where the link header goes (well behaved protocols will
1000 * reserve room for us). Last, check if room for PDU tail.
1002 if (flags & TX_AAL5)
1003 m->m_pkthdr.len += MID_PDU_SIZE;
1004 m->m_pkthdr.len = roundup(m->m_pkthdr.len, MID_ATMDATASZ);
1005 pad = m->m_pkthdr.len - datalen;
1006 if (flags & TX_AAL5)
1007 pad -= MID_PDU_SIZE;
1008 m->m_pkthdr.len += MID_TBD_SIZE;
1010 DBG(sc, TX, ("txvci%d: buflen=%u datalen=%u lead=%d trail=%d",
1011 vci, m->m_pkthdr.len, datalen, (int)M_LEADINGSPACE(m),
1012 (int)M_TRAILINGSPACE(lastm)));
1015 * From here on we need access to sc
1020 * Allocate a map. We do this here rather then in en_txdma,
1021 * because en_txdma is also called from the interrupt handler
1022 * and we are going to have a locking problem then. We must
1023 * use NOWAIT here, because the ip_output path holds various
1026 map = uma_zalloc_arg(sc->map_zone, sc, M_NOWAIT);
1028 /* drop that packet */
1029 EN_COUNT(sc->stats.txnomap);
1035 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1037 uma_zfree(sc->map_zone, map);
1043 * Look, whether we can prepend the TBD (8 byte)
1045 if (M_WRITABLE(m) && M_LEADINGSPACE(m) >= MID_TBD_SIZE) {
1046 tbd[0] = htobe32(MID_TBD_MK1((flags & TX_AAL5) ?
1047 MID_TBD_AAL5 : MID_TBD_NOAAL5,
1048 vc->txspeed, m->m_pkthdr.len / MID_ATMDATASZ));
1049 tbd[1] = htobe32(MID_TBD_MK2(vci, 0, 0));
1051 m->m_data -= MID_TBD_SIZE;
1052 bcopy(tbd, m->m_data, MID_TBD_SIZE);
1053 m->m_len += MID_TBD_SIZE;
1054 flags |= TX_HAS_TBD;
1058 * Check whether the padding fits (must be writeable -
1059 * we pad with zero).
1061 if (M_WRITABLE(lastm) && M_TRAILINGSPACE(lastm) >= pad) {
1062 bzero(lastm->m_data + lastm->m_len, pad);
1063 lastm->m_len += pad;
1064 flags |= TX_HAS_PAD;
1066 if ((flags & TX_AAL5) &&
1067 M_TRAILINGSPACE(lastm) > MID_PDU_SIZE) {
1068 pdu[0] = htobe32(MID_PDU_MK1(0, 0, datalen));
1070 bcopy(pdu, lastm->m_data + lastm->m_len,
1072 lastm->m_len += MID_PDU_SIZE;
1073 flags |= TX_HAS_PDU;
1077 if (!sc->is_adaptec &&
1078 (m = en_fix_mchain(sc, m, &pad)) == NULL) {
1080 uma_zfree(sc->map_zone, map);
1085 * get assigned channel (will be zero unless txspeed is set)
1089 if (m->m_pkthdr.len > EN_TXSZ * 1024) {
1090 DBG(sc, TX, ("tx%td: packet larger than xmit buffer "
1091 "(%d > %d)\n", tx - sc->txslot, m->m_pkthdr.len,
1095 uma_zfree(sc->map_zone, map);
1099 if (tx->mbsize > EN_TXHIWAT) {
1100 EN_COUNT(sc->stats.txmbovr);
1101 DBG(sc, TX, ("tx%td: buffer space shortage",
1105 uma_zfree(sc->map_zone, map);
1110 tx->mbsize += m->m_pkthdr.len;
1112 DBG(sc, TX, ("tx%td: VCI=%d, speed=0x%x, buflen=%d, mbsize=%d",
1113 tx - sc->txslot, vci, sc->vccs[vci]->txspeed,
1114 m->m_pkthdr.len, tx->mbsize));
1116 MBUF_SET_TX(m, vci, flags, datalen, pad, map);
1118 _IF_ENQUEUE(&tx->q, m);
1126 /*********************************************************************/
1132 * en_loadvc: load a vc tab entry from a slot
1134 * LOCK: locked, needed
1137 en_loadvc(struct en_softc *sc, struct en_vcc *vc)
1139 uint32_t reg = en_read(sc, MID_VC(vc->vcc.vci));
1141 reg = MIDV_SETMODE(reg, MIDV_TRASH);
1142 en_write(sc, MID_VC(vc->vcc.vci), reg);
1145 /* no need to set CRC */
1147 /* read pointer = 0, desc. start = 0 */
1148 en_write(sc, MID_DST_RP(vc->vcc.vci), 0);
1149 /* write pointer = 0 */
1150 en_write(sc, MID_WP_ST_CNT(vc->vcc.vci), 0);
1151 /* set mode, size, loc */
1152 en_write(sc, MID_VC(vc->vcc.vci), vc->rxslot->mode);
1154 vc->rxslot->cur = vc->rxslot->start;
1156 DBG(sc, VC, ("rx%td: assigned to VCI %d", vc->rxslot - sc->rxslot,
1161 * Open the given vcc.
1163 * LOCK: unlocked, needed
1166 en_open_vcc(struct en_softc *sc, struct atmio_openvcc *op)
1168 uint32_t oldmode, newmode;
1169 struct en_rxslot *slot;
1173 DBG(sc, IOCTL, ("enable vpi=%d, vci=%d, flags=%#x",
1174 op->param.vpi, op->param.vci, op->param.flags));
1176 if (op->param.vpi != 0 || op->param.vci >= MID_N_VC)
1179 vc = uma_zalloc(en_vcc_zone, M_NOWAIT | M_ZERO);
1185 if (sc->vccs[op->param.vci] != NULL) {
1190 /* find a free receive slot */
1191 for (slot = sc->rxslot; slot < &sc->rxslot[sc->en_nrx]; slot++)
1192 if (slot->vcc == NULL)
1194 if (slot == &sc->rxslot[sc->en_nrx]) {
1200 vc->rxhand = op->rxhand;
1201 vc->vcc = op->param;
1203 oldmode = slot->mode;
1204 newmode = (op->param.aal == ATMIO_AAL_5) ? MIDV_AAL5 : MIDV_NOAAL;
1205 slot->mode = MIDV_SETMODE(oldmode, newmode);
1208 KASSERT (_IF_QLEN(&slot->indma) == 0 && _IF_QLEN(&slot->q) == 0,
1209 ("en_rxctl: left over mbufs on enable slot=%td",
1210 vc->rxslot - sc->rxslot));
1213 vc->txslot = sc->txslot;
1214 vc->txslot->nref++; /* bump reference count */
1216 en_loadvc(sc, vc); /* does debug printf for us */
1218 /* don't free below */
1219 sc->vccs[vc->vcc.vci] = vc;
1225 uma_zfree(en_vcc_zone, vc);
1235 en_close_finish(struct en_softc *sc, struct en_vcc *vc)
1238 if (vc->rxslot != NULL)
1239 vc->rxslot->vcc = NULL;
1241 DBG(sc, VC, ("vci: %u free (%p)", vc->vcc.vci, vc));
1243 sc->vccs[vc->vcc.vci] = NULL;
1244 uma_zfree(en_vcc_zone, vc);
1249 * LOCK: unlocked, needed
1252 en_close_vcc(struct en_softc *sc, struct atmio_closevcc *cl)
1254 uint32_t oldmode, newmode;
1258 DBG(sc, IOCTL, ("disable vpi=%d, vci=%d", cl->vpi, cl->vci));
1260 if (cl->vpi != 0 || cl->vci >= MID_N_VC)
1264 if ((vc = sc->vccs[cl->vci]) == NULL) {
1272 if (vc->rxslot == NULL) {
1276 if (vc->vflags & VCC_DRAIN) {
1281 oldmode = en_read(sc, MID_VC(cl->vci));
1282 newmode = MIDV_SETMODE(oldmode, MIDV_TRASH) & ~MIDV_INSERVICE;
1283 en_write(sc, MID_VC(cl->vci), (newmode | (oldmode & MIDV_INSERVICE)));
1285 /* halt in tracks, be careful to preserve inservice bit */
1287 vc->rxslot->mode = newmode;
1291 /* if stuff is still going on we are going to have to drain it out */
1292 if (_IF_QLEN(&vc->rxslot->indma) == 0 &&
1293 _IF_QLEN(&vc->rxslot->q) == 0 &&
1294 (vc->vflags & VCC_SWSL) == 0) {
1295 en_close_finish(sc, vc);
1299 vc->vflags |= VCC_DRAIN;
1300 DBG(sc, IOCTL, ("VCI %u now draining", cl->vci));
1302 if (vc->vcc.flags & ATMIO_FLAG_ASYNC)
1305 vc->vflags |= VCC_CLOSE_RX;
1306 while ((sc->ifp->if_drv_flags & IFF_DRV_RUNNING) &&
1307 (vc->vflags & VCC_DRAIN))
1308 cv_wait(&sc->cv_close, &sc->en_mtx);
1310 en_close_finish(sc, vc);
1311 if (!(sc->ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1322 /*********************************************************************/
1324 * starting/stopping the card
1328 * en_reset_ul: reset the board, throw away work in progress.
1329 * must en_init to recover.
1331 * LOCK: locked, needed
1334 en_reset_ul(struct en_softc *sc)
1338 struct en_rxslot *rx;
1341 device_printf(sc->dev, "reset\n");
1342 sc->ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1344 if (sc->en_busreset)
1345 sc->en_busreset(sc);
1346 en_write(sc, MID_RESID, 0x0); /* reset hardware */
1349 * recv: dump any mbufs we are dma'ing into, if DRAINing, then a reset
1350 * will free us! Don't release the rxslot from the channel.
1352 for (lcv = 0 ; lcv < MID_N_VC ; lcv++) {
1353 if (sc->vccs[lcv] == NULL)
1355 rx = sc->vccs[lcv]->rxslot;
1358 _IF_DEQUEUE(&rx->indma, m);
1361 map = (void *)m->m_pkthdr.rcvif;
1362 uma_zfree(sc->map_zone, map);
1366 _IF_DEQUEUE(&rx->q, m);
1371 sc->vccs[lcv]->vflags = 0;
1375 * xmit: dump everything
1377 for (lcv = 0 ; lcv < EN_NTX ; lcv++) {
1379 _IF_DEQUEUE(&sc->txslot[lcv].indma, m);
1382 map = (void *)m->m_pkthdr.rcvif;
1383 uma_zfree(sc->map_zone, map);
1387 _IF_DEQUEUE(&sc->txslot[lcv].q, m);
1390 map = (void *)m->m_pkthdr.rcvif;
1391 uma_zfree(sc->map_zone, map);
1394 sc->txslot[lcv].mbsize = 0;
1398 * Unstop all waiters
1400 cv_broadcast(&sc->cv_close);
1404 * en_reset: reset the board, throw away work in progress.
1405 * must en_init to recover.
1407 * LOCK: unlocked, needed
1409 * Use en_reset_ul if you alreay have the lock
1412 en_reset(struct en_softc *sc)
1421 * en_init: init board and sync the card with the data in the softc.
1423 * LOCK: locked, needed
1426 en_init(struct en_softc *sc)
1431 if ((sc->ifp->if_flags & IFF_UP) == 0) {
1432 DBG(sc, INIT, ("going down"));
1433 en_reset(sc); /* to be safe */
1437 DBG(sc, INIT, ("going up"));
1438 sc->ifp->if_drv_flags |= IFF_DRV_RUNNING; /* enable */
1440 if (sc->en_busreset)
1441 sc->en_busreset(sc);
1442 en_write(sc, MID_RESID, 0x0); /* reset */
1445 bus_space_set_region_4(sc->en_memt, sc->en_base,
1446 MID_RAMOFF, 0, sc->en_obmemsz / 4);
1449 * init obmem data structures: vc tab, dma q's, slist.
1451 * note that we set drq_free/dtq_free to one less than the total number
1452 * of DTQ/DRQs present. we do this because the card uses the condition
1453 * (drq_chip == drq_us) to mean "list is empty"... but if you allow the
1454 * circular list to be completely full then (drq_chip == drq_us) [i.e.
1455 * the drq_us pointer will wrap all the way around]. by restricting
1456 * the number of active requests to (N - 1) we prevent the list from
1457 * becoming completely full. note that the card will sometimes give
1458 * us an interrupt for a DTQ/DRQ we have already processes... this helps
1459 * keep that interrupt from messing us up.
1461 bzero(&sc->drq, sizeof(sc->drq));
1462 sc->drq_free = MID_DRQ_N - 1;
1463 sc->drq_chip = MID_DRQ_REG2A(en_read(sc, MID_DMA_RDRX));
1464 en_write(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip));
1465 sc->drq_us = sc->drq_chip;
1467 bzero(&sc->dtq, sizeof(sc->dtq));
1468 sc->dtq_free = MID_DTQ_N - 1;
1469 sc->dtq_chip = MID_DTQ_REG2A(en_read(sc, MID_DMA_RDTX));
1470 en_write(sc, MID_DMA_WRTX, MID_DRQ_A2REG(sc->dtq_chip));
1471 sc->dtq_us = sc->dtq_chip;
1473 sc->hwslistp = MID_SL_REG2A(en_read(sc, MID_SERV_WRITE));
1474 sc->swsl_size = sc->swsl_head = sc->swsl_tail = 0;
1476 DBG(sc, INIT, ("drq free/chip: %d/0x%x, dtq free/chip: %d/0x%x, "
1477 "hwslist: 0x%x", sc->drq_free, sc->drq_chip, sc->dtq_free,
1478 sc->dtq_chip, sc->hwslistp));
1480 for (slot = 0 ; slot < EN_NTX ; slot++) {
1481 sc->txslot[slot].bfree = EN_TXSZ * 1024;
1482 en_write(sc, MIDX_READPTR(slot), 0);
1483 en_write(sc, MIDX_DESCSTART(slot), 0);
1484 loc = sc->txslot[slot].cur = sc->txslot[slot].start;
1485 loc = loc - MID_RAMOFF;
1486 /* mask, cvt to words */
1487 loc = (loc & ~((EN_TXSZ * 1024) - 1)) >> 2;
1489 loc = loc >> MIDV_LOCTOPSHFT;
1490 en_write(sc, MIDX_PLACE(slot), MIDX_MKPLACE(en_k2sz(EN_TXSZ),
1492 DBG(sc, INIT, ("tx%d: place 0x%x", slot,
1493 (u_int)en_read(sc, MIDX_PLACE(slot))));
1496 for (vc = 0; vc < MID_N_VC; vc++)
1497 if (sc->vccs[vc] != NULL)
1498 en_loadvc(sc, sc->vccs[vc]);
1503 en_write(sc, MID_INTENA, MID_INT_TX | MID_INT_DMA_OVR | MID_INT_IDENT |
1504 MID_INT_LERR | MID_INT_DMA_ERR | MID_INT_DMA_RX | MID_INT_DMA_TX |
1505 MID_INT_SERVICE | MID_INT_SUNI | MID_INT_STATS);
1506 en_write(sc, MID_MAST_CSR, MID_SETIPL(sc->ipl) | MID_MCSR_ENDMA |
1507 MID_MCSR_ENTX | MID_MCSR_ENRX);
1510 /*********************************************************************/
1515 * en_ioctl: handle ioctl requests
1517 * NOTE: if you add an ioctl to set txspeed, you should choose a new
1518 * TX channel/slot. Choose the one with the lowest sc->txslot[slot].nref
1519 * value, subtract one from sc->txslot[0].nref, add one to the
1520 * sc->txslot[slot].nref, set sc->txvc2slot[vci] = slot, and then set
1523 * LOCK: unlocked, needed
1526 en_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1528 struct en_softc *sc = (struct en_softc *)ifp->if_softc;
1529 #if defined(INET) || defined(INET6)
1530 struct ifaddr *ifa = (struct ifaddr *)data;
1532 struct ifreq *ifr = (struct ifreq *)data;
1533 struct atmio_vcctable *vtab;
1540 ifp->if_flags |= IFF_UP;
1541 #if defined(INET) || defined(INET6)
1542 if (ifa->ifa_addr->sa_family == AF_INET
1543 || ifa->ifa_addr->sa_family == AF_INET6) {
1544 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1548 ifa->ifa_rtrequest = atm_rtrequest; /* ??? */
1553 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1562 if (ifp->if_flags & IFF_UP) {
1563 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1566 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1574 * Set the interface MTU.
1576 if (ifr->ifr_mtu > ATMMTU) {
1580 ifp->if_mtu = ifr->ifr_mtu;
1585 error = ifmedia_ioctl(ifp, ifr, &sc->media, cmd);
1588 case SIOCATMOPENVCC: /* kernel internal use */
1589 error = en_open_vcc(sc, (struct atmio_openvcc *)data);
1592 case SIOCATMCLOSEVCC: /* kernel internal use */
1593 error = en_close_vcc(sc, (struct atmio_closevcc *)data);
1596 case SIOCATMGETVCCS: /* internal netgraph use */
1597 vtab = atm_getvccs((struct atmio_vcc **)sc->vccs,
1598 MID_N_VC, sc->vccs_open, &sc->en_mtx, 0);
1603 *(void **)data = vtab;
1606 case SIOCATMGVCCS: /* return vcc table */
1607 vtab = atm_getvccs((struct atmio_vcc **)sc->vccs,
1608 MID_N_VC, sc->vccs_open, &sc->en_mtx, 1);
1609 error = copyout(vtab, ifr->ifr_data, sizeof(*vtab) +
1610 vtab->count * sizeof(vtab->vccs[0]));
1611 free(vtab, M_DEVBUF);
1621 /*********************************************************************/
1627 * Sysctl handler for internal statistics
1629 * LOCK: unlocked, needed
1632 en_sysctl_istats(SYSCTL_HANDLER_ARGS)
1634 struct en_softc *sc = arg1;
1638 ret = malloc(sizeof(sc->stats), M_TEMP, M_WAITOK);
1641 bcopy(&sc->stats, ret, sizeof(sc->stats));
1644 error = SYSCTL_OUT(req, ret, sizeof(sc->stats));
1650 /*********************************************************************/
1656 * Transmit interrupt handler
1658 * check for tx complete, if detected then this means that some space
1659 * has come free on the card. we must account for it and arrange to
1660 * kick the channel to life (in case it is stalled waiting on the card).
1662 * LOCK: locked, needed
1665 en_intr_tx(struct en_softc *sc, uint32_t reg)
1672 kick = 0; /* bitmask of channels to kick */
1674 for (mask = 1, chan = 0; chan < EN_NTX; chan++, mask *= 2) {
1675 if (!(reg & MID_TXCHAN(chan)))
1680 /* current read pointer */
1681 val = en_read(sc, MIDX_READPTR(chan));
1683 val = (val * sizeof(uint32_t)) + sc->txslot[chan].start;
1684 if (val > sc->txslot[chan].cur)
1685 sc->txslot[chan].bfree = val - sc->txslot[chan].cur;
1687 sc->txslot[chan].bfree = (val + (EN_TXSZ * 1024)) -
1688 sc->txslot[chan].cur;
1689 DBG(sc, INTR, ("tx%d: transmit done. %d bytes now free in "
1690 "buffer", chan, sc->txslot[chan].bfree));
1698 * check for TX DMA complete, if detected then this means
1699 * that some DTQs are now free. it also means some indma
1700 * mbufs can be freed. if we needed DTQs, kick all channels.
1702 * LOCK: locked, needed
1705 en_intr_tx_dma(struct en_softc *sc)
1715 val = en_read(sc, MID_DMA_RDTX); /* chip's current location */
1716 idx = MID_DTQ_A2REG(sc->dtq_chip); /* where we last saw chip */
1718 if (sc->need_dtqs) {
1719 kick = MID_NTX_CH - 1; /* assume power of 2, kick all! */
1720 sc->need_dtqs = 0; /* recalculated in "kick" loop below */
1721 DBG(sc, INTR, ("cleared need DTQ condition"));
1724 while (idx != val) {
1726 if ((dtq = sc->dtq[idx]) != 0) {
1727 /* don't forget to zero it out when done */
1729 slot = EN_DQ_SLOT(dtq);
1731 _IF_DEQUEUE(&sc->txslot[slot].indma, m);
1733 panic("enintr: dtqsync");
1734 map = (void *)m->m_pkthdr.rcvif;
1735 uma_zfree(sc->map_zone, map);
1738 sc->txslot[slot].mbsize -= EN_DQ_LEN(dtq);
1739 DBG(sc, INTR, ("tx%d: free %d dma bytes, mbsize now "
1740 "%d", slot, EN_DQ_LEN(dtq),
1741 sc->txslot[slot].mbsize));
1743 EN_WRAPADD(0, MID_DTQ_N, idx, 1);
1745 sc->dtq_chip = MID_DTQ_REG2A(val); /* sync softc */
1753 * LOCK: locked, needed
1756 en_intr_service(struct en_softc *sc)
1760 int need_softserv = 0;
1763 chip = MID_SL_REG2A(en_read(sc, MID_SERV_WRITE));
1765 while (sc->hwslistp != chip) {
1766 /* fetch and remove it from hardware service list */
1767 vci = en_read(sc, sc->hwslistp);
1768 EN_WRAPADD(MID_SLOFF, MID_SLEND, sc->hwslistp, 4);
1770 if ((vc = sc->vccs[vci]) == NULL ||
1771 (vc->vcc.flags & ATMIO_FLAG_NORX)) {
1772 DBG(sc, INTR, ("unexpected rx interrupt VCI %d", vci));
1773 en_write(sc, MID_VC(vci), MIDV_TRASH); /* rx off */
1777 /* remove from hwsl */
1778 en_write(sc, MID_VC(vci), vc->rxslot->mode);
1779 EN_COUNT(sc->stats.hwpull);
1781 DBG(sc, INTR, ("pulled VCI %d off hwslist", vci));
1783 /* add it to the software service list (if needed) */
1784 if ((vc->vflags & VCC_SWSL) == 0) {
1785 EN_COUNT(sc->stats.swadd);
1787 vc->vflags |= VCC_SWSL;
1788 sc->swslist[sc->swsl_tail] = vci;
1789 EN_WRAPADD(0, MID_SL_N, sc->swsl_tail, 1);
1791 DBG(sc, INTR, ("added VCI %d to swslist", vci));
1794 return (need_softserv);
1798 * Handle a receive DMA completion
1801 en_rx_drain(struct en_softc *sc, u_int drq)
1803 struct en_rxslot *slot;
1806 struct atm_pseudohdr ah;
1808 slot = &sc->rxslot[EN_DQ_SLOT(drq)];
1810 m = NULL; /* assume "JK" trash DMA */
1811 if (EN_DQ_LEN(drq) != 0) {
1812 _IF_DEQUEUE(&slot->indma, m);
1813 KASSERT(m != NULL, ("drqsync: %s: lost mbuf in slot %td!",
1814 sc->ifp->if_xname, slot - sc->rxslot));
1815 uma_zfree(sc->map_zone, (struct en_map *)m->m_pkthdr.rcvif);
1817 if ((vc = slot->vcc) == NULL) {
1824 /* do something with this mbuf */
1825 if (vc->vflags & VCC_DRAIN) {
1829 if (_IF_QLEN(&slot->indma) == 0 && _IF_QLEN(&slot->q) == 0 &&
1830 (en_read(sc, MID_VC(vc->vcc.vci)) & MIDV_INSERVICE) == 0 &&
1831 (vc->vflags & VCC_SWSL) == 0) {
1832 vc->vflags &= ~VCC_CLOSE_RX;
1833 if (vc->vcc.flags & ATMIO_FLAG_ASYNC)
1834 en_close_finish(sc, vc);
1836 cv_signal(&sc->cv_close);
1842 ATM_PH_FLAGS(&ah) = vc->vcc.flags;
1843 ATM_PH_VPI(&ah) = 0;
1844 ATM_PH_SETVCI(&ah, vc->vcc.vci);
1846 DBG(sc, INTR, ("rx%td: rxvci%d: atm_input, mbuf %p, len %d, "
1847 "hand %p", slot - sc->rxslot, vc->vcc.vci, m,
1848 EN_DQ_LEN(drq), vc->rxhand));
1850 m->m_pkthdr.rcvif = sc->ifp;
1851 sc->ifp->if_ipackets++;
1854 vc->ibytes += m->m_pkthdr.len;
1857 if (sc->debug & DBG_IPACKETS)
1858 en_dump_packet(sc, m);
1861 BPF_MTAP(sc->ifp, m);
1864 atm_input(sc->ifp, &ah, m, vc->rxhand);
1870 * check for RX DMA complete, and pass the data "upstairs"
1872 * LOCK: locked, needed
1875 en_intr_rx_dma(struct en_softc *sc)
1881 val = en_read(sc, MID_DMA_RDRX); /* chip's current location */
1882 idx = MID_DRQ_A2REG(sc->drq_chip); /* where we last saw chip */
1884 while (idx != val) {
1886 if ((drq = sc->drq[idx]) != 0) {
1887 /* don't forget to zero it out when done */
1889 en_rx_drain(sc, drq);
1891 EN_WRAPADD(0, MID_DRQ_N, idx, 1);
1893 sc->drq_chip = MID_DRQ_REG2A(val); /* sync softc */
1895 if (sc->need_drqs) {
1896 /* true if we had a DRQ shortage */
1898 DBG(sc, INTR, ("cleared need DRQ condition"));
1905 * en_mget: get an mbuf chain that can hold totlen bytes and return it
1906 * (for recv). For the actual allocation totlen is rounded up to a multiple
1907 * of 4. We also ensure, that each mbuf has a multiple of 4 bytes.
1909 * After this call the sum of all the m_len's in the chain will be totlen.
1910 * This is called at interrupt time, so we can't wait here.
1912 * LOCK: any, not needed
1914 static struct mbuf *
1915 en_mget(struct en_softc *sc, u_int pktlen)
1917 struct mbuf *m, *tmp;
1920 totlen = roundup(pktlen, sizeof(uint32_t));
1921 pad = totlen - pktlen;
1924 * First get an mbuf with header. Keep space for a couple of
1925 * words at the begin.
1927 /* called from interrupt context */
1928 MGETHDR(m, M_DONTWAIT, MT_DATA);
1932 m->m_pkthdr.rcvif = NULL;
1933 m->m_pkthdr.len = pktlen;
1934 m->m_len = EN_RX1BUF;
1935 MH_ALIGN(m, EN_RX1BUF);
1936 if (m->m_len >= totlen) {
1942 /* called from interrupt context */
1943 tmp = m_getm(m, totlen, M_DONTWAIT, MT_DATA);
1949 /* m_getm could do this for us */
1950 while (tmp != NULL) {
1951 tmp->m_len = min(MCLBYTES, totlen);
1952 totlen -= tmp->m_len;
1961 * Argument for RX DMAMAP loader.
1964 struct en_softc *sc;
1966 u_int pre_skip; /* number of bytes to skip at begin */
1967 u_int post_skip; /* number of bytes to skip at end */
1968 struct en_vcc *vc; /* vc we are receiving on */
1969 int wait; /* wait for DRQ entries */
1973 * Copy the segment table to the buffer for later use. And compute the
1974 * number of dma queue entries we need.
1976 * LOCK: locked, needed
1979 en_rxdma_load(void *uarg, bus_dma_segment_t *segs, int nseg,
1980 bus_size_t mapsize, int error)
1982 struct rxarg *rx = uarg;
1983 struct en_softc *sc = rx->sc;
1984 struct en_rxslot *slot = rx->vc->rxslot;
1985 u_int free; /* number of free DRQ entries */
1986 uint32_t cur; /* current buffer offset */
1987 uint32_t drq; /* DRQ entry pointer */
1988 uint32_t last_drq; /* where we have written last */
1989 u_int needalign, cnt, count, bcode;
1996 if (nseg > EN_MAX_DMASEG)
1997 panic("too many DMA segments");
2001 free = sc->drq_free;
2008 * Local macro to add an entry to the receive DMA area. If there
2009 * are no entries left, return. Save the byte offset of the entry
2010 * in last_drq for later use.
2012 #define PUT_DRQ_ENTRY(ENI, BCODE, COUNT, ADDR) \
2014 EN_COUNT(sc->stats.rxdrqout); \
2019 en_write(sc, drq + 0, (ENI || !sc->is_adaptec) ? \
2020 MID_MK_RXQ_ENI(COUNT, rx->vc->vcc.vci, 0, BCODE) : \
2021 MID_MK_RXQ_ADP(COUNT, rx->vc->vcc.vci, 0, BCODE)); \
2022 en_write(sc, drq + 4, ADDR); \
2024 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, drq, 8); \
2028 * Local macro to generate a DMA entry to DMA cnt bytes. Updates
2029 * the current buffer byte offset accordingly.
2031 #define DO_DRQ(TYPE) do { \
2033 EN_WRAPADD(slot->start, slot->stop, cur, cnt); \
2034 DBG(sc, SERV, ("rx%td: "TYPE" %u bytes, %ju left, cur %#x", \
2035 slot - sc->rxslot, cnt, (uintmax_t)rest, cur)); \
2037 PUT_DRQ_ENTRY(1, bcode, count, addr); \
2043 * Skip the RBD at the beginning
2045 if (rx->pre_skip > 0) {
2046 /* update DMA address */
2047 EN_WRAPADD(slot->start, slot->stop, cur, rx->pre_skip);
2049 PUT_DRQ_ENTRY(0, MIDDMA_JK, WORD_IDX(slot->start, cur), 0);
2052 for (i = 0; i < nseg; i++, segs++) {
2053 addr = segs->ds_addr;
2054 rest = segs->ds_len;
2056 if (sc->is_adaptec) {
2057 /* adaptec card - simple */
2059 /* advance the on-card buffer pointer */
2060 EN_WRAPADD(slot->start, slot->stop, cur, rest);
2061 DBG(sc, SERV, ("rx%td: adp %ju bytes %#jx "
2062 "(cur now 0x%x)", slot - sc->rxslot,
2063 (uintmax_t)rest, (uintmax_t)addr, cur));
2065 PUT_DRQ_ENTRY(0, 0, rest, addr);
2071 * do we need to do a DMA op to align to the maximum
2072 * burst? Note, that we are alway 32-bit aligned.
2075 (needalign = (addr & sc->bestburstmask)) != 0) {
2076 /* compute number of bytes, words and code */
2077 cnt = sc->bestburstlen - needalign;
2080 count = cnt / sizeof(uint32_t);
2081 if (sc->noalbursts) {
2082 bcode = MIDDMA_WORD;
2084 bcode = en_dmaplan[count].bcode;
2085 count = cnt >> en_dmaplan[count].divshift;
2090 /* do we need to do a max-sized burst? */
2091 if (rest >= sc->bestburstlen) {
2092 count = rest >> sc->bestburstshift;
2093 cnt = count << sc->bestburstshift;
2094 bcode = sc->bestburstcode;
2098 /* do we need to do a cleanup burst? */
2101 count = rest / sizeof(uint32_t);
2102 if (sc->noalbursts) {
2103 bcode = MIDDMA_WORD;
2105 bcode = en_dmaplan[count].bcode;
2106 count = cnt >> en_dmaplan[count].divshift;
2108 DO_DRQ("clean_dma");
2113 * Skip stuff at the end
2115 if (rx->post_skip > 0) {
2116 /* update DMA address */
2117 EN_WRAPADD(slot->start, slot->stop, cur, rx->post_skip);
2119 PUT_DRQ_ENTRY(0, MIDDMA_JK, WORD_IDX(slot->start, cur), 0);
2122 /* record the end for the interrupt routine */
2123 sc->drq[MID_DRQ_A2REG(last_drq)] =
2124 EN_DQ_MK(slot - sc->rxslot, rx->m->m_pkthdr.len);
2126 /* set the end flag in the last descriptor */
2127 en_write(sc, last_drq + 0, SETQ_END(sc, en_read(sc, last_drq + 0)));
2129 #undef PUT_DRQ_ENTRY
2134 sc->drq_free = free;
2137 /* signal to card */
2138 en_write(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_us));
2142 * en_service: handle a service interrupt
2144 * Q: why do we need a software service list?
2146 * A: if we remove a VCI from the hardware list and we find that we are
2147 * out of DRQs we must defer processing until some DRQs become free.
2148 * so we must remember to look at this RX VCI/slot later, but we can't
2149 * put it back on the hardware service list (since that isn't allowed).
2150 * so we instead save it on the software service list. it would be nice
2151 * if we could peek at the VCI on top of the hwservice list without removing
2152 * it, however this leads to a race condition: if we peek at it and
2153 * decide we are done with it new data could come in before we have a
2154 * chance to remove it from the hwslist. by the time we get it out of
2155 * the list the interrupt for the new data will be lost. oops!
2157 * LOCK: locked, needed
2160 en_service(struct en_softc *sc)
2162 struct mbuf *m, *lastm;
2166 uint32_t dstart; /* data start (as reported by card) */
2167 uint32_t rbd; /* receive buffer descriptor */
2168 uint32_t pdu; /* AAL5 trailer */
2171 struct en_rxslot *slot;
2177 if (sc->swsl_size == 0) {
2178 DBG(sc, SERV, ("en_service done"));
2183 * get vcc to service
2185 rx.vc = vc = sc->vccs[sc->swslist[sc->swsl_head]];
2187 KASSERT (slot->vcc->rxslot == slot, ("en_service: rx slot/vci sync"));
2190 * determine our mode and if we've got any work to do
2192 DBG(sc, SERV, ("rx%td: service vci=%d start/stop/cur=0x%x 0x%x "
2193 "0x%x", slot - sc->rxslot, vc->vcc.vci, slot->start,
2194 slot->stop, slot->cur));
2199 dstart = MIDV_DSTART(en_read(sc, MID_DST_RP(vc->vcc.vci)));
2200 dstart = (dstart * sizeof(uint32_t)) + slot->start;
2202 /* check to see if there is any data at all */
2203 if (dstart == cur) {
2204 EN_WRAPADD(0, MID_SL_N, sc->swsl_head, 1);
2205 /* remove from swslist */
2206 vc->vflags &= ~VCC_SWSL;
2208 DBG(sc, SERV, ("rx%td: remove vci %d from swslist",
2209 slot - sc->rxslot, vc->vcc.vci));
2214 * figure out how many bytes we need
2215 * [mlen = # bytes to go in mbufs]
2217 rbd = en_read(sc, cur);
2218 if (MID_RBD_ID(rbd) != MID_RBD_STDID)
2219 panic("en_service: id mismatch");
2221 if (rbd & MID_RBD_T) {
2222 mlen = 0; /* we've got trash */
2223 rx.pre_skip = MID_RBD_SIZE;
2225 EN_COUNT(sc->stats.ttrash);
2226 DBG(sc, SERV, ("RX overflow lost %d cells!", MID_RBD_CNT(rbd)));
2228 } else if (vc->vcc.aal != ATMIO_AAL_5) {
2230 mlen = MID_CHDR_SIZE + MID_ATMDATASZ;
2231 rx.pre_skip = MID_RBD_SIZE;
2235 rx.pre_skip = MID_RBD_SIZE;
2237 /* get PDU trailer in correct byte order */
2238 pdu = cur + MID_RBD_CNT(rbd) * MID_ATMDATASZ +
2239 MID_RBD_SIZE - MID_PDU_SIZE;
2240 if (pdu >= slot->stop)
2241 pdu -= EN_RXSZ * 1024;
2242 pdu = en_read(sc, pdu);
2244 if (MID_RBD_CNT(rbd) * MID_ATMDATASZ <
2246 device_printf(sc->dev, "invalid AAL5 length\n");
2247 rx.post_skip = MID_RBD_CNT(rbd) * MID_ATMDATASZ;
2249 sc->ifp->if_ierrors++;
2251 } else if (rbd & MID_RBD_CRCERR) {
2252 device_printf(sc->dev, "CRC error\n");
2253 rx.post_skip = MID_RBD_CNT(rbd) * MID_ATMDATASZ;
2255 sc->ifp->if_ierrors++;
2258 mlen = MID_PDU_LEN(pdu);
2259 rx.post_skip = MID_RBD_CNT(rbd) * MID_ATMDATASZ - mlen;
2264 * now allocate mbufs for mlen bytes of data, if out of mbufs, trash all
2267 * 1. it is possible that we've already allocated an mbuf for this pkt
2268 * but ran out of DRQs, in which case we saved the allocated mbuf
2270 * 2. if we save an buf in "q" we store the "cur" (pointer) in the
2271 * buf as an identity (that we can check later).
2272 * 3. after this block of code, if m is still NULL then we ran out of
2275 _IF_DEQUEUE(&slot->q, m);
2277 if (m->m_pkthdr.csum_data != cur) {
2279 DBG(sc, SERV, ("rx%td: q'ed buf %p not ours",
2280 slot - sc->rxslot, m));
2281 _IF_PREPEND(&slot->q, m);
2283 EN_COUNT(sc->stats.rxqnotus);
2285 EN_COUNT(sc->stats.rxqus);
2286 DBG(sc, SERV, ("rx%td: recovered q'ed buf %p",
2287 slot - sc->rxslot, m));
2290 if (mlen == 0 && m != NULL) {
2291 /* should not happen */
2296 if (mlen != 0 && m == NULL) {
2297 m = en_mget(sc, mlen);
2299 rx.post_skip += mlen;
2301 EN_COUNT(sc->stats.rxmbufout);
2302 DBG(sc, SERV, ("rx%td: out of mbufs",
2303 slot - sc->rxslot));
2305 rx.post_skip -= roundup(mlen, sizeof(uint32_t)) - mlen;
2307 DBG(sc, SERV, ("rx%td: allocate buf %p, mlen=%d",
2308 slot - sc->rxslot, m, mlen));
2311 DBG(sc, SERV, ("rx%td: VCI %d, rbuf %p, mlen %d, skip %u/%u",
2312 slot - sc->rxslot, vc->vcc.vci, m, mlen, rx.pre_skip,
2316 /* M_NOWAIT - called from interrupt context */
2317 map = uma_zalloc_arg(sc->map_zone, sc, M_NOWAIT);
2319 rx.post_skip += mlen;
2321 DBG(sc, SERV, ("rx%td: out of maps",
2322 slot - sc->rxslot));
2326 error = bus_dmamap_load_mbuf(sc->txtag, map->map, m,
2327 en_rxdma_load, &rx, BUS_DMA_NOWAIT);
2330 device_printf(sc->dev, "loading RX map failed "
2332 uma_zfree(sc->map_zone, map);
2334 rx.post_skip += mlen;
2338 map->flags |= ENMAP_LOADED;
2341 /* out of DRQs - wait */
2342 uma_zfree(sc->map_zone, map);
2344 m->m_pkthdr.csum_data = cur;
2345 _IF_ENQUEUE(&slot->q, m);
2346 EN_COUNT(sc->stats.rxdrqout);
2348 sc->need_drqs = 1; /* flag condition */
2352 (void)m_length(m, &lastm);
2353 lastm->m_len -= roundup(mlen, sizeof(uint32_t)) - mlen;
2355 m->m_pkthdr.rcvif = (void *)map;
2356 _IF_ENQUEUE(&slot->indma, m);
2358 /* get next packet in this slot */
2363 * Here we end if we should drop the packet from the receive buffer.
2364 * The number of bytes to drop is in fill. We can do this with on
2365 * JK entry. If we don't even have that one - wait.
2367 if (sc->drq_free == 0) {
2368 sc->need_drqs = 1; /* flag condition */
2371 rx.post_skip += rx.pre_skip;
2372 DBG(sc, SERV, ("rx%td: skipping %u", slot - sc->rxslot, rx.post_skip));
2374 /* advance buffer address */
2375 EN_WRAPADD(slot->start, slot->stop, cur, rx.post_skip);
2377 /* write DRQ entry */
2379 en_write(sc, sc->drq_us,
2380 MID_MK_RXQ_ADP(WORD_IDX(slot->start, cur),
2381 vc->vcc.vci, MID_DMA_END, MIDDMA_JK));
2383 en_write(sc, sc->drq_us,
2384 MID_MK_RXQ_ENI(WORD_IDX(slot->start, cur),
2385 vc->vcc.vci, MID_DMA_END, MIDDMA_JK));
2386 en_write(sc, sc->drq_us + 4, 0);
2387 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, sc->drq_us, 8);
2390 /* signal to RX interrupt */
2391 sc->drq[MID_DRQ_A2REG(sc->drq_us)] = EN_DQ_MK(slot - sc->rxslot, 0);
2394 /* signal to card */
2395 en_write(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_us));
2403 * LOCK: unlocked, needed
2408 struct en_softc *sc = arg;
2409 uint32_t reg, kick, mask;
2410 int lcv, need_softserv;
2414 reg = en_read(sc, MID_INTACK);
2415 DBG(sc, INTR, ("interrupt=0x%b", reg, MID_INTBITS));
2417 if ((reg & MID_INT_ANY) == 0) {
2423 * unexpected errors that need a reset
2425 if ((reg & (MID_INT_IDENT | MID_INT_LERR | MID_INT_DMA_ERR)) != 0) {
2426 device_printf(sc->dev, "unexpected interrupt=0x%b, "
2427 "resetting\n", reg, MID_INTBITS);
2429 panic("en: unexpected error");
2438 if (reg & MID_INT_SUNI)
2439 utopia_intr(&sc->utopia);
2442 if (reg & MID_INT_TX)
2443 kick |= en_intr_tx(sc, reg);
2445 if (reg & MID_INT_DMA_TX)
2446 kick |= en_intr_tx_dma(sc);
2449 * kick xmit channels as needed.
2452 DBG(sc, INTR, ("tx kick mask = 0x%x", kick));
2453 for (mask = 1, lcv = 0 ; lcv < EN_NTX ; lcv++, mask = mask * 2)
2454 if ((kick & mask) && _IF_QLEN(&sc->txslot[lcv].q) != 0)
2455 en_txdma(sc, &sc->txslot[lcv]);
2459 if (reg & MID_INT_DMA_RX)
2460 need_softserv |= en_intr_rx_dma(sc);
2462 if (reg & MID_INT_SERVICE)
2463 need_softserv |= en_intr_service(sc);
2471 if (reg & MID_INT_DMA_OVR) {
2472 EN_COUNT(sc->stats.dmaovr);
2473 DBG(sc, INTR, ("MID_INT_DMA_OVR"));
2475 reg = en_read(sc, MID_STAT);
2476 sc->stats.otrash += MID_OTRASH(reg);
2477 sc->stats.vtrash += MID_VTRASH(reg);
2483 * Read at most n SUNI regs starting at reg into val
2486 en_utopia_readregs(struct ifatm *ifatm, u_int reg, uint8_t *val, u_int *n)
2488 struct en_softc *sc = ifatm->ifp->if_softc;
2492 if (reg >= MID_NSUNI)
2494 if (reg + *n > MID_NSUNI)
2495 *n = MID_NSUNI - reg;
2497 for (i = 0; i < *n; i++)
2498 val[i] = en_read(sc, MID_SUNIOFF + 4 * (reg + i));
2504 * change the bits given by mask to them in val in register reg
2507 en_utopia_writereg(struct ifatm *ifatm, u_int reg, u_int mask, u_int val)
2509 struct en_softc *sc = ifatm->ifp->if_softc;
2513 if (reg >= MID_NSUNI)
2515 regval = en_read(sc, MID_SUNIOFF + 4 * reg);
2516 regval = (regval & ~mask) | (val & mask);
2517 en_write(sc, MID_SUNIOFF + 4 * reg, regval);
2521 static const struct utopia_methods en_utopia_methods = {
2526 /*********************************************************************/
2528 * Probing the DMA brokeness of the card
2532 * Physical address load helper function for DMA probe
2534 * LOCK: unlocked, not needed
2537 en_dmaprobe_load(void *uarg, bus_dma_segment_t *segs, int nseg, int error)
2540 *(bus_addr_t *)uarg = segs[0].ds_addr;
2544 * en_dmaprobe: helper function for en_attach.
2546 * see how the card handles DMA by running a few DMA tests. we need
2547 * to figure out the largest number of bytes we can DMA in one burst
2548 * ("bestburstlen"), and if the starting address for a burst needs to
2549 * be aligned on any sort of boundary or not ("alburst").
2551 * Things turn out more complex than that, because on my (harti) brand
2552 * new motherboard (2.4GHz) we can do 64byte aligned DMAs, but everything
2553 * we more than 4 bytes fails (with an RX DMA timeout) for physical
2554 * addresses that end with 0xc. Therefor we search not only the largest
2555 * burst that is supported (hopefully 64) but also check what is the largerst
2556 * unaligned supported size. If that appears to be lesser than 4 words,
2557 * set the noalbursts flag. That will be set only if also alburst is set.
2561 * en_dmaprobe_doit: do actual testing for the DMA test.
2562 * Cycle through all bursts sizes from 8 up to 64 and try whether it works.
2563 * Return the largest one that works.
2565 * LOCK: unlocked, not needed
2568 en_dmaprobe_doit(struct en_softc *sc, uint8_t *sp, bus_addr_t psp)
2570 uint8_t *dp = sp + MIDDMA_MAXBURST;
2571 bus_addr_t pdp = psp + MIDDMA_MAXBURST;
2572 int lcv, retval = 4, cnt;
2573 uint32_t reg, bcode, midvloc;
2575 if (sc->en_busreset)
2576 sc->en_busreset(sc);
2577 en_write(sc, MID_RESID, 0x0); /* reset card before touching RAM */
2580 * set up a 1k buffer at MID_BUFOFF
2582 midvloc = ((MID_BUFOFF - MID_RAMOFF) / sizeof(uint32_t))
2584 en_write(sc, MIDX_PLACE(0), MIDX_MKPLACE(en_k2sz(1), midvloc));
2585 en_write(sc, MID_VC(0), (midvloc << MIDV_LOCSHIFT)
2586 | (en_k2sz(1) << MIDV_SZSHIFT) | MIDV_TRASH);
2587 en_write(sc, MID_DST_RP(0), 0);
2588 en_write(sc, MID_WP_ST_CNT(0), 0);
2590 /* set up sample data */
2591 for (lcv = 0 ; lcv < MIDDMA_MAXBURST; lcv++)
2594 /* enable DMA (only) */
2595 en_write(sc, MID_MAST_CSR, MID_MCSR_ENDMA);
2597 sc->drq_chip = MID_DRQ_REG2A(en_read(sc, MID_DMA_RDRX));
2598 sc->dtq_chip = MID_DTQ_REG2A(en_read(sc, MID_DMA_RDTX));
2601 * try it now . . . DMA it out, then DMA it back in and compare
2603 * note: in order to get the dma stuff to reverse directions it wants
2604 * the "end" flag set! since we are not dma'ing valid data we may
2605 * get an ident mismatch interrupt (which we will ignore).
2607 DBG(sc, DMA, ("test sp=%p/%#lx, dp=%p/%#lx",
2608 sp, (u_long)psp, dp, (u_long)pdp));
2609 for (lcv = 8 ; lcv <= MIDDMA_MAXBURST ; lcv = lcv * 2) {
2610 DBG(sc, DMA, ("test lcv=%d", lcv));
2612 /* zero SRAM and dest buffer */
2613 bus_space_set_region_4(sc->en_memt, sc->en_base,
2614 MID_BUFOFF, 0, 1024 / 4);
2615 bzero(dp, MIDDMA_MAXBURST);
2617 bcode = en_sz2b(lcv);
2619 /* build lcv-byte-DMA x NBURSTS */
2621 en_write(sc, sc->dtq_chip,
2622 MID_MK_TXQ_ADP(lcv, 0, MID_DMA_END, 0));
2624 en_write(sc, sc->dtq_chip,
2625 MID_MK_TXQ_ENI(1, 0, MID_DMA_END, bcode));
2626 en_write(sc, sc->dtq_chip + 4, psp);
2627 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, sc->dtq_chip, 8);
2628 en_write(sc, MID_DMA_WRTX, MID_DTQ_A2REG(sc->dtq_chip));
2631 while ((reg = en_readx(sc, MID_DMA_RDTX)) !=
2632 MID_DTQ_A2REG(sc->dtq_chip)) {
2635 DBG(sc, DMA, ("unexpected timeout in tx "
2636 "DMA test\n alignment=0x%lx, burst size=%d"
2637 ", dma addr reg=%#x, rdtx=%#x, stat=%#x\n",
2638 (u_long)sp & 63, lcv,
2639 en_read(sc, MID_DMA_ADDR), reg,
2640 en_read(sc, MID_INTSTAT)));
2645 reg = en_read(sc, MID_INTACK);
2646 if ((reg & MID_INT_DMA_TX) != MID_INT_DMA_TX) {
2647 DBG(sc, DMA, ("unexpected status in tx DMA test: %#x\n",
2651 /* re-enable DMA (only) */
2652 en_write(sc, MID_MAST_CSR, MID_MCSR_ENDMA);
2654 /* "return to sender..." address is known ... */
2656 /* build lcv-byte-DMA x NBURSTS */
2658 en_write(sc, sc->drq_chip,
2659 MID_MK_RXQ_ADP(lcv, 0, MID_DMA_END, 0));
2661 en_write(sc, sc->drq_chip,
2662 MID_MK_RXQ_ENI(1, 0, MID_DMA_END, bcode));
2663 en_write(sc, sc->drq_chip + 4, pdp);
2664 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, sc->drq_chip, 8);
2665 en_write(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip));
2667 while ((reg = en_readx(sc, MID_DMA_RDRX)) !=
2668 MID_DRQ_A2REG(sc->drq_chip)) {
2672 DBG(sc, DMA, ("unexpected timeout in rx "
2673 "DMA test, rdrx=%#x\n", reg));
2677 reg = en_read(sc, MID_INTACK);
2678 if ((reg & MID_INT_DMA_RX) != MID_INT_DMA_RX) {
2679 DBG(sc, DMA, ("unexpected status in rx DMA "
2680 "test: 0x%x\n", reg));
2683 if (bcmp(sp, dp, lcv)) {
2684 DBG(sc, DMA, ("DMA test failed! lcv=%d, sp=%p, "
2685 "dp=%p", lcv, sp, dp));
2691 return (retval); /* studly 64 byte DMA present! oh baby!! */
2695 * Find the best DMA parameters
2697 * LOCK: unlocked, not needed
2700 en_dmaprobe(struct en_softc *sc)
2706 int bestalgn, lcv, try, bestnoalgn;
2714 * Allocate some DMA-able memory.
2715 * We need 3 times the max burst size aligned to the max burst size.
2717 err = bus_dma_tag_create(NULL, MIDDMA_MAXBURST, 0,
2718 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2719 3 * MIDDMA_MAXBURST, 1, 3 * MIDDMA_MAXBURST, 0,
2722 panic("%s: cannot create test DMA tag %d", __func__, err);
2724 err = bus_dmamem_alloc(tag, &buffer, 0, &map);
2726 panic("%s: cannot allocate test DMA memory %d", __func__, err);
2728 err = bus_dmamap_load(tag, map, buffer, 3 * MIDDMA_MAXBURST,
2729 en_dmaprobe_load, &phys, BUS_DMA_NOWAIT);
2731 panic("%s: cannot load test DMA map %d", __func__, err);
2733 DBG(sc, DMA, ("phys=%#lx addr=%p", (u_long)phys, addr));
2736 * Now get the best burst size of the aligned case.
2738 bestalgn = bestnoalgn = en_dmaprobe_doit(sc, addr, phys);
2741 * Now try unaligned.
2743 for (lcv = 4; lcv < MIDDMA_MAXBURST; lcv += 4) {
2744 try = en_dmaprobe_doit(sc, addr + lcv, phys + lcv);
2746 if (try < bestnoalgn)
2750 if (bestnoalgn < bestalgn) {
2752 if (bestnoalgn < 32)
2756 sc->bestburstlen = bestalgn;
2757 sc->bestburstshift = en_log2(bestalgn);
2758 sc->bestburstmask = sc->bestburstlen - 1; /* must be power of 2 */
2759 sc->bestburstcode = en_sz2b(bestalgn);
2762 * Reset the chip before freeing the buffer. It may still be trying
2765 if (sc->en_busreset)
2766 sc->en_busreset(sc);
2767 en_write(sc, MID_RESID, 0x0); /* reset card before touching RAM */
2769 DELAY(10000); /* may still do DMA */
2772 * Free the DMA stuff
2774 bus_dmamap_unload(tag, map);
2775 bus_dmamem_free(tag, buffer, map);
2776 bus_dma_tag_destroy(tag);
2779 /*********************************************************************/
2785 * Attach to the card.
2787 * LOCK: unlocked, not needed (but initialized)
2790 en_attach(struct en_softc *sc)
2792 struct ifnet *ifp = sc->ifp;
2794 uint32_t reg, lcv, check, ptr, sav, midvloc;
2797 sc->debug = EN_DEBUG;
2801 * Probe card to determine memory size.
2803 * The stupid ENI card always reports to PCI that it needs 4MB of
2804 * space (2MB regs and 2MB RAM). If it has less than 2MB RAM the
2805 * addresses wrap in the RAM address space (i.e. on a 512KB card
2806 * addresses 0x3ffffc, 0x37fffc, and 0x2ffffc are aliases for
2807 * 0x27fffc [note that RAM starts at offset 0x200000]).
2810 /* reset card before touching RAM */
2811 if (sc->en_busreset)
2812 sc->en_busreset(sc);
2813 en_write(sc, MID_RESID, 0x0);
2815 for (lcv = MID_PROBEOFF; lcv <= MID_MAXOFF ; lcv += MID_PROBSIZE) {
2816 en_write(sc, lcv, lcv); /* data[address] = address */
2817 for (check = MID_PROBEOFF; check < lcv ;check += MID_PROBSIZE) {
2818 reg = en_read(sc, check);
2820 /* found an alias! - quit */
2825 lcv -= MID_PROBSIZE; /* take one step back */
2826 sc->en_obmemsz = (lcv + 4) - MID_RAMOFF;
2829 * determine the largest DMA burst supported
2838 if (sc->en_busreset)
2839 sc->en_busreset(sc);
2840 en_write(sc, MID_RESID, 0x0); /* reset */
2843 bus_space_set_region_4(sc->en_memt, sc->en_base,
2844 MID_RAMOFF, 0, sc->en_obmemsz / 4);
2846 reg = en_read(sc, MID_RESID);
2848 device_printf(sc->dev, "ATM midway v%d, board IDs %d.%d, %s%s%s, "
2849 "%ldKB on-board RAM\n", MID_VER(reg), MID_MID(reg), MID_DID(reg),
2850 (MID_IS_SABRE(reg)) ? "sabre controller, " : "",
2851 (MID_IS_SUNI(reg)) ? "SUNI" : "Utopia",
2852 (!MID_IS_SUNI(reg) && MID_IS_UPIPE(reg)) ? " (pipelined)" : "",
2853 (long)sc->en_obmemsz / 1024);
2856 * fill in common ATM interface stuff
2858 IFP2IFATM(sc->ifp)->mib.hw_version = (MID_VER(reg) << 16) |
2859 (MID_MID(reg) << 8) | MID_DID(reg);
2860 if (MID_DID(reg) & 0x4)
2861 IFP2IFATM(sc->ifp)->mib.media = IFM_ATM_UTP_155;
2863 IFP2IFATM(sc->ifp)->mib.media = IFM_ATM_MM_155;
2865 IFP2IFATM(sc->ifp)->mib.pcr = ATM_RATE_155M;
2866 IFP2IFATM(sc->ifp)->mib.vpi_bits = 0;
2867 IFP2IFATM(sc->ifp)->mib.vci_bits = MID_VCI_BITS;
2868 IFP2IFATM(sc->ifp)->mib.max_vccs = MID_N_VC;
2869 IFP2IFATM(sc->ifp)->mib.max_vpcs = 0;
2871 if (sc->is_adaptec) {
2872 IFP2IFATM(sc->ifp)->mib.device = ATM_DEVICE_ADP155P;
2873 if (sc->bestburstlen == 64 && sc->alburst == 0)
2874 device_printf(sc->dev,
2875 "passed 64 byte DMA test\n");
2877 device_printf(sc->dev, "FAILED DMA TEST: "
2878 "burst=%d, alburst=%d\n", sc->bestburstlen,
2881 IFP2IFATM(sc->ifp)->mib.device = ATM_DEVICE_ENI155P;
2882 device_printf(sc->dev, "maximum DMA burst length = %d "
2883 "bytes%s\n", sc->bestburstlen, sc->alburst ?
2884 sc->noalbursts ? " (no large bursts)" : " (must align)" :
2889 * link into network subsystem and prepare card
2891 sc->ifp->if_softc = sc;
2892 ifp->if_flags = IFF_SIMPLEX;
2893 ifp->if_ioctl = en_ioctl;
2894 ifp->if_start = en_start;
2896 mtx_init(&sc->en_mtx, device_get_nameunit(sc->dev),
2897 MTX_NETWORK_LOCK, MTX_DEF);
2898 cv_init(&sc->cv_close, "VC close");
2901 * Make the sysctl tree
2903 sysctl_ctx_init(&sc->sysctl_ctx);
2905 if ((sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
2906 SYSCTL_STATIC_CHILDREN(_hw_atm), OID_AUTO,
2907 device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "")) == NULL)
2910 if (SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
2911 OID_AUTO, "istats", CTLFLAG_RD, sc, 0, en_sysctl_istats,
2912 "S", "internal statistics") == NULL)
2916 if (SYSCTL_ADD_UINT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
2917 OID_AUTO, "debug", CTLFLAG_RW , &sc->debug, 0, "") == NULL)
2921 IFP2IFATM(sc->ifp)->phy = &sc->utopia;
2922 utopia_attach(&sc->utopia, IFP2IFATM(sc->ifp), &sc->media, &sc->en_mtx,
2923 &sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
2924 &en_utopia_methods);
2925 utopia_init_media(&sc->utopia);
2927 MGET(sc->padbuf, M_WAIT, MT_DATA);
2928 bzero(sc->padbuf->m_data, MLEN);
2930 if (bus_dma_tag_create(NULL, 1, 0,
2931 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2932 EN_TXSZ * 1024, EN_MAX_DMASEG, EN_TXSZ * 1024, 0,
2933 NULL, NULL, &sc->txtag))
2936 sc->map_zone = uma_zcreate("en dma maps", sizeof(struct en_map),
2937 en_map_ctor, en_map_dtor, NULL, en_map_fini, UMA_ALIGN_PTR,
2939 if (sc->map_zone == NULL)
2941 uma_zone_set_max(sc->map_zone, EN_MAX_MAPS);
2946 sc->vccs = malloc(MID_N_VC * sizeof(sc->vccs[0]),
2947 M_DEVBUF, M_ZERO | M_WAITOK);
2949 sz = sc->en_obmemsz - (MID_BUFOFF - MID_RAMOFF);
2950 ptr = sav = MID_BUFOFF;
2951 ptr = roundup(ptr, EN_TXSZ * 1024); /* align */
2952 sz = sz - (ptr - sav);
2953 if (EN_TXSZ*1024 * EN_NTX > sz) {
2954 device_printf(sc->dev, "EN_NTX/EN_TXSZ too big\n");
2957 for (lcv = 0 ;lcv < EN_NTX ;lcv++) {
2958 sc->txslot[lcv].mbsize = 0;
2959 sc->txslot[lcv].start = ptr;
2960 ptr += (EN_TXSZ * 1024);
2961 sz -= (EN_TXSZ * 1024);
2962 sc->txslot[lcv].stop = ptr;
2963 sc->txslot[lcv].nref = 0;
2964 DBG(sc, INIT, ("tx%d: start 0x%x, stop 0x%x", lcv,
2965 sc->txslot[lcv].start, sc->txslot[lcv].stop));
2969 ptr = roundup(ptr, EN_RXSZ * 1024); /* align */
2970 sz = sz - (ptr - sav);
2971 sc->en_nrx = sz / (EN_RXSZ * 1024);
2972 if (sc->en_nrx <= 0) {
2973 device_printf(sc->dev, "EN_NTX/EN_TXSZ/EN_RXSZ too big\n");
2978 * ensure that there is always one VC slot on the service list free
2979 * so that we can tell the difference between a full and empty list.
2981 if (sc->en_nrx >= MID_N_VC)
2982 sc->en_nrx = MID_N_VC - 1;
2984 for (lcv = 0 ; lcv < sc->en_nrx ; lcv++) {
2985 sc->rxslot[lcv].vcc = NULL;
2986 midvloc = sc->rxslot[lcv].start = ptr;
2987 ptr += (EN_RXSZ * 1024);
2988 sz -= (EN_RXSZ * 1024);
2989 sc->rxslot[lcv].stop = ptr;
2990 midvloc = midvloc - MID_RAMOFF;
2991 /* mask, cvt to words */
2992 midvloc = (midvloc & ~((EN_RXSZ*1024) - 1)) >> 2;
2993 /* we only want the top 11 bits */
2994 midvloc = midvloc >> MIDV_LOCTOPSHFT;
2995 midvloc = (midvloc & MIDV_LOCMASK) << MIDV_LOCSHIFT;
2996 sc->rxslot[lcv].mode = midvloc |
2997 (en_k2sz(EN_RXSZ) << MIDV_SZSHIFT) | MIDV_TRASH;
2999 DBG(sc, INIT, ("rx%d: start 0x%x, stop 0x%x, mode 0x%x", lcv,
3000 sc->rxslot[lcv].start, sc->rxslot[lcv].stop,
3001 sc->rxslot[lcv].mode));
3004 device_printf(sc->dev, "%d %dKB receive buffers, %d %dKB transmit "
3005 "buffers\n", sc->en_nrx, EN_RXSZ, EN_NTX, EN_TXSZ);
3006 device_printf(sc->dev, "end station identifier (mac address) "
3007 "%6D\n", IFP2IFATM(sc->ifp)->mib.esi, ":");
3010 * Start SUNI stuff. This will call our readregs/writeregs
3011 * functions and these assume the lock to be held so we must get it
3015 utopia_start(&sc->utopia);
3016 utopia_reset(&sc->utopia);
3025 bpfattach(ifp, DLT_ATM_RFC1483, sizeof(struct atmllc));
3036 * Free all internal resources. No access to bus resources here.
3037 * No locking required here (interrupt is already disabled).
3039 * LOCK: unlocked, needed (but destroyed)
3042 en_destroy(struct en_softc *sc)
3046 if (sc->utopia.state & UTP_ST_ATTACHED) {
3047 /* these assume the lock to be held */
3049 utopia_stop(&sc->utopia);
3050 utopia_detach(&sc->utopia);
3054 if (sc->vccs != NULL) {
3055 /* get rid of sticky VCCs */
3056 for (i = 0; i < MID_N_VC; i++)
3057 if (sc->vccs[i] != NULL)
3058 uma_zfree(en_vcc_zone, sc->vccs[i]);
3059 free(sc->vccs, M_DEVBUF);
3062 if (sc->padbuf != NULL)
3066 * Destroy the map zone before the tag (the fini function will
3067 * destroy the DMA maps using the tag)
3069 if (sc->map_zone != NULL)
3070 uma_zdestroy(sc->map_zone);
3072 if (sc->txtag != NULL)
3073 bus_dma_tag_destroy(sc->txtag);
3075 (void)sysctl_ctx_free(&sc->sysctl_ctx);
3077 cv_destroy(&sc->cv_close);
3078 mtx_destroy(&sc->en_mtx);
3082 * Module loaded/unloaded
3085 en_modevent(module_t mod __unused, int event, void *arg __unused)
3091 en_vcc_zone = uma_zcreate("EN vccs", sizeof(struct en_vcc),
3092 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 0);
3093 if (en_vcc_zone == NULL)
3098 uma_zdestroy(en_vcc_zone);
3104 /*********************************************************************/
3111 * functions we can call from ddb
3115 * en_dump: dump the state
3117 #define END_SWSL 0x00000040 /* swsl state */
3118 #define END_DRQ 0x00000020 /* drq state */
3119 #define END_DTQ 0x00000010 /* dtq state */
3120 #define END_RX 0x00000008 /* rx state */
3121 #define END_TX 0x00000004 /* tx state */
3122 #define END_MREGS 0x00000002 /* registers */
3123 #define END_STATS 0x00000001 /* dump stats */
3125 #define END_BITS "\20\7SWSL\6DRQ\5DTQ\4RX\3TX\2MREGS\1STATS"
3128 en_dump_stats(const struct en_stats *s)
3130 printf("en_stats:\n");
3131 printf("\t%d/%d mfix (%d failed)\n", s->mfixaddr, s->mfixlen,
3133 printf("\t%d rx dma overflow interrupts\n", s->dmaovr);
3134 printf("\t%d times out of TX space and stalled\n", s->txoutspace);
3135 printf("\t%d times out of DTQs\n", s->txdtqout);
3136 printf("\t%d times launched a packet\n", s->launch);
3137 printf("\t%d times pulled the hw service list\n", s->hwpull);
3138 printf("\t%d times pushed a vci on the sw service list\n", s->swadd);
3139 printf("\t%d times RX pulled an mbuf from Q that wasn't ours\n",
3141 printf("\t%d times RX pulled a good mbuf from Q\n", s->rxqus);
3142 printf("\t%d times ran out of DRQs\n", s->rxdrqout);
3143 printf("\t%d transmit packets dropped due to mbsize\n", s->txmbovr);
3144 printf("\t%d cells trashed due to turned off rxvc\n", s->vtrash);
3145 printf("\t%d cells trashed due to totally full buffer\n", s->otrash);
3146 printf("\t%d cells trashed due almost full buffer\n", s->ttrash);
3147 printf("\t%d rx mbuf allocation failures\n", s->rxmbufout);
3148 printf("\t%d times out of tx maps\n", s->txnomap);
3151 printf("\tnatmintr so_rcv: ok/drop cnt: %d/%d, ok/drop bytes: %d/%d\n",
3152 natm_sookcnt, natm_sodropcnt, natm_sookbytes, natm_sodropbytes);
3158 en_dump_mregs(struct en_softc *sc)
3163 printf("resid = 0x%x\n", en_read(sc, MID_RESID));
3164 printf("interrupt status = 0x%b\n",
3165 (int)en_read(sc, MID_INTSTAT), MID_INTBITS);
3166 printf("interrupt enable = 0x%b\n",
3167 (int)en_read(sc, MID_INTENA), MID_INTBITS);
3168 printf("mcsr = 0x%b\n", (int)en_read(sc, MID_MAST_CSR), MID_MCSRBITS);
3169 printf("serv_write = [chip=%u] [us=%u]\n", en_read(sc, MID_SERV_WRITE),
3170 MID_SL_A2REG(sc->hwslistp));
3171 printf("dma addr = 0x%x\n", en_read(sc, MID_DMA_ADDR));
3172 printf("DRQ: chip[rd=0x%x,wr=0x%x], sc[chip=0x%x,us=0x%x]\n",
3173 MID_DRQ_REG2A(en_read(sc, MID_DMA_RDRX)),
3174 MID_DRQ_REG2A(en_read(sc, MID_DMA_WRRX)), sc->drq_chip, sc->drq_us);
3175 printf("DTQ: chip[rd=0x%x,wr=0x%x], sc[chip=0x%x,us=0x%x]\n",
3176 MID_DTQ_REG2A(en_read(sc, MID_DMA_RDTX)),
3177 MID_DTQ_REG2A(en_read(sc, MID_DMA_WRTX)), sc->dtq_chip, sc->dtq_us);
3179 printf(" unusal txspeeds:");
3180 for (cnt = 0 ; cnt < MID_N_VC ; cnt++)
3181 if (sc->vccs[cnt]->txspeed)
3182 printf(" vci%d=0x%x", cnt, sc->vccs[cnt]->txspeed);
3185 printf(" rxvc slot mappings:");
3186 for (cnt = 0 ; cnt < MID_N_VC ; cnt++)
3187 if (sc->vccs[cnt]->rxslot != NULL)
3188 printf(" %d->%td", cnt,
3189 sc->vccs[cnt]->rxslot - sc->rxslot);
3194 en_dump_tx(struct en_softc *sc)
3199 for (slot = 0 ; slot < EN_NTX; slot++) {
3200 printf("tx%d: start/stop/cur=0x%x/0x%x/0x%x [%d] ", slot,
3201 sc->txslot[slot].start, sc->txslot[slot].stop,
3202 sc->txslot[slot].cur,
3203 (sc->txslot[slot].cur - sc->txslot[slot].start) / 4);
3204 printf("mbsize=%d, bfree=%d\n", sc->txslot[slot].mbsize,
3205 sc->txslot[slot].bfree);
3206 printf("txhw: base_address=0x%x, size=%u, read=%u, "
3208 (u_int)MIDX_BASE(en_read(sc, MIDX_PLACE(slot))),
3209 MIDX_SZ(en_read(sc, MIDX_PLACE(slot))),
3210 en_read(sc, MIDX_READPTR(slot)),
3211 en_read(sc, MIDX_DESCSTART(slot)));
3216 en_dump_rx(struct en_softc *sc)
3218 struct en_rxslot *slot;
3220 printf(" recv slots:\n");
3221 for (slot = sc->rxslot ; slot < &sc->rxslot[sc->en_nrx]; slot++) {
3222 printf("rx%td: start/stop/cur=0x%x/0x%x/0x%x mode=0x%x ",
3223 slot - sc->rxslot, slot->start, slot->stop, slot->cur,
3225 if (slot->vcc != NULL) {
3226 printf("vci=%u\n", slot->vcc->vcc.vci);
3227 printf("RXHW: mode=0x%x, DST_RP=0x%x, WP_ST_CNT=0x%x\n",
3228 en_read(sc, MID_VC(slot->vcc->vcc.vci)),
3229 en_read(sc, MID_DST_RP(slot->vcc->vcc.vci)),
3230 en_read(sc, MID_WP_ST_CNT(slot->vcc->vcc.vci)));
3236 * This is only correct for non-adaptec adapters
3239 en_dump_dtqs(struct en_softc *sc)
3243 printf(" dtq [need_dtqs=%d,dtq_free=%d]:\n", sc->need_dtqs,
3246 while (ptr != sc->dtq_us) {
3247 reg = en_read(sc, ptr);
3248 printf("\t0x%x=[%#x cnt=%d, chan=%d, end=%d, type=%d @ 0x%x]\n",
3249 sc->dtq[MID_DTQ_A2REG(ptr)], reg, MID_DMA_CNT(reg),
3250 MID_DMA_TXCHAN(reg), (reg & MID_DMA_END) != 0,
3251 MID_DMA_TYPE(reg), en_read(sc, ptr + 4));
3252 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, ptr, 8);
3257 en_dump_drqs(struct en_softc *sc)
3261 printf(" drq [need_drqs=%d,drq_free=%d]:\n", sc->need_drqs,
3264 while (ptr != sc->drq_us) {
3265 reg = en_read(sc, ptr);
3266 printf("\t0x%x=[cnt=%d, chan=%d, end=%d, type=%d @ 0x%x]\n",
3267 sc->drq[MID_DRQ_A2REG(ptr)], MID_DMA_CNT(reg),
3268 MID_DMA_RXVCI(reg), (reg & MID_DMA_END) != 0,
3269 MID_DMA_TYPE(reg), en_read(sc, ptr + 4));
3270 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, ptr, 8);
3274 /* Do not staticize - meant for calling from DDB! */
3276 en_dump(int unit, int level)
3278 struct en_softc *sc;
3283 dc = devclass_find("en");
3285 printf("%s: can't find devclass!\n", __func__);
3288 maxunit = devclass_get_maxunit(dc);
3289 for (lcv = 0 ; lcv < maxunit ; lcv++) {
3290 sc = devclass_get_softc(dc, lcv);
3293 if (unit != -1 && unit != lcv)
3296 device_printf(sc->dev, "dumping device at level 0x%b\n",
3299 if (sc->dtq_us == 0) {
3300 printf("<hasn't been en_init'd yet>\n");
3304 if (level & END_STATS)
3305 en_dump_stats(&sc->stats);
3306 if (level & END_MREGS)
3312 if (level & END_DTQ)
3314 if (level & END_DRQ)
3317 if (level & END_SWSL) {
3318 printf(" swslist [size=%d]: ", sc->swsl_size);
3319 for (cnt = sc->swsl_head ; cnt != sc->swsl_tail ;
3320 cnt = (cnt + 1) % MID_SL_N)
3321 printf("0x%x ", sc->swslist[cnt]);
3329 * en_dumpmem: dump the memory
3331 * Do not staticize - meant for calling from DDB!
3334 en_dumpmem(int unit, int addr, int len)
3336 struct en_softc *sc;
3340 dc = devclass_find("en");
3342 printf("%s: can't find devclass\n", __func__);
3345 sc = devclass_get_softc(dc, unit);
3347 printf("%s: invalid unit number: %d\n", __func__, unit);
3352 if (addr < MID_RAMOFF || addr + len * 4 > MID_MAXOFF || len <= 0) {
3353 printf("invalid addr/len number: %d, %d\n", addr, len);
3356 printf("dumping %d words starting at offset 0x%x\n", len, addr);
3358 reg = en_read(sc, addr);
3359 printf("mem[0x%x] = 0x%x\n", addr, reg);